1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * mtk-base-afe.h -- Mediatek base afe structure 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (c) 2016 MediaTek Inc. 6*4882a593Smuzhiyun * Author: Garlic Tseng <garlic.tseng@mediatek.com> 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef _MTK_BASE_AFE_H_ 10*4882a593Smuzhiyun #define _MTK_BASE_AFE_H_ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define MTK_STREAM_NUM (SNDRV_PCM_STREAM_LAST + 1) 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun struct mtk_base_memif_data { 15*4882a593Smuzhiyun int id; 16*4882a593Smuzhiyun const char *name; 17*4882a593Smuzhiyun int reg_ofs_base; 18*4882a593Smuzhiyun int reg_ofs_cur; 19*4882a593Smuzhiyun int reg_ofs_end; 20*4882a593Smuzhiyun int reg_ofs_base_msb; 21*4882a593Smuzhiyun int reg_ofs_cur_msb; 22*4882a593Smuzhiyun int reg_ofs_end_msb; 23*4882a593Smuzhiyun int fs_reg; 24*4882a593Smuzhiyun int fs_shift; 25*4882a593Smuzhiyun int fs_maskbit; 26*4882a593Smuzhiyun int mono_reg; 27*4882a593Smuzhiyun int mono_shift; 28*4882a593Smuzhiyun int mono_invert; 29*4882a593Smuzhiyun int quad_ch_reg; 30*4882a593Smuzhiyun int quad_ch_mask; 31*4882a593Smuzhiyun int quad_ch_shift; 32*4882a593Smuzhiyun int enable_reg; 33*4882a593Smuzhiyun int enable_shift; 34*4882a593Smuzhiyun int hd_reg; 35*4882a593Smuzhiyun int hd_shift; 36*4882a593Smuzhiyun int hd_align_reg; 37*4882a593Smuzhiyun int hd_align_mshift; 38*4882a593Smuzhiyun int msb_reg; 39*4882a593Smuzhiyun int msb_shift; 40*4882a593Smuzhiyun int msb2_reg; 41*4882a593Smuzhiyun int msb2_shift; 42*4882a593Smuzhiyun int agent_disable_reg; 43*4882a593Smuzhiyun int agent_disable_shift; 44*4882a593Smuzhiyun /* playback memif only */ 45*4882a593Smuzhiyun int pbuf_reg; 46*4882a593Smuzhiyun int pbuf_mask; 47*4882a593Smuzhiyun int pbuf_shift; 48*4882a593Smuzhiyun int minlen_reg; 49*4882a593Smuzhiyun int minlen_mask; 50*4882a593Smuzhiyun int minlen_shift; 51*4882a593Smuzhiyun }; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun struct mtk_base_irq_data { 54*4882a593Smuzhiyun int id; 55*4882a593Smuzhiyun int irq_cnt_reg; 56*4882a593Smuzhiyun int irq_cnt_shift; 57*4882a593Smuzhiyun int irq_cnt_maskbit; 58*4882a593Smuzhiyun int irq_fs_reg; 59*4882a593Smuzhiyun int irq_fs_shift; 60*4882a593Smuzhiyun int irq_fs_maskbit; 61*4882a593Smuzhiyun int irq_en_reg; 62*4882a593Smuzhiyun int irq_en_shift; 63*4882a593Smuzhiyun int irq_clr_reg; 64*4882a593Smuzhiyun int irq_clr_shift; 65*4882a593Smuzhiyun }; 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun struct device; 68*4882a593Smuzhiyun struct list_head; 69*4882a593Smuzhiyun struct mtk_base_afe_memif; 70*4882a593Smuzhiyun struct mtk_base_afe_irq; 71*4882a593Smuzhiyun struct mtk_base_afe_dai; 72*4882a593Smuzhiyun struct regmap; 73*4882a593Smuzhiyun struct snd_pcm_substream; 74*4882a593Smuzhiyun struct snd_soc_dai; 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun struct mtk_base_afe { 77*4882a593Smuzhiyun void __iomem *base_addr; 78*4882a593Smuzhiyun struct device *dev; 79*4882a593Smuzhiyun struct regmap *regmap; 80*4882a593Smuzhiyun struct mutex irq_alloc_lock; /* dynamic alloc irq lock */ 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun unsigned int const *reg_back_up_list; 83*4882a593Smuzhiyun unsigned int *reg_back_up; 84*4882a593Smuzhiyun unsigned int reg_back_up_list_num; 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun int (*runtime_suspend)(struct device *dev); 87*4882a593Smuzhiyun int (*runtime_resume)(struct device *dev); 88*4882a593Smuzhiyun bool suspended; 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun struct mtk_base_afe_memif *memif; 91*4882a593Smuzhiyun int memif_size; 92*4882a593Smuzhiyun struct mtk_base_afe_irq *irqs; 93*4882a593Smuzhiyun int irqs_size; 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun struct list_head sub_dais; 96*4882a593Smuzhiyun struct snd_soc_dai_driver *dai_drivers; 97*4882a593Smuzhiyun unsigned int num_dai_drivers; 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun const struct snd_pcm_hardware *mtk_afe_hardware; 100*4882a593Smuzhiyun int (*memif_fs)(struct snd_pcm_substream *substream, 101*4882a593Smuzhiyun unsigned int rate); 102*4882a593Smuzhiyun int (*irq_fs)(struct snd_pcm_substream *substream, 103*4882a593Smuzhiyun unsigned int rate); 104*4882a593Smuzhiyun int (*get_dai_fs)(struct mtk_base_afe *afe, 105*4882a593Smuzhiyun int dai_id, unsigned int rate); 106*4882a593Smuzhiyun int (*get_memif_pbuf_size)(struct snd_pcm_substream *substream); 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun int (*request_dram_resource)(struct device *dev); 109*4882a593Smuzhiyun int (*release_dram_resource)(struct device *dev); 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun void *platform_priv; 112*4882a593Smuzhiyun }; 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun struct mtk_base_afe_memif { 115*4882a593Smuzhiyun unsigned int phys_buf_addr; 116*4882a593Smuzhiyun int buffer_size; 117*4882a593Smuzhiyun struct snd_pcm_substream *substream; 118*4882a593Smuzhiyun const struct mtk_base_memif_data *data; 119*4882a593Smuzhiyun int irq_usage; 120*4882a593Smuzhiyun int const_irq; 121*4882a593Smuzhiyun unsigned char *dma_area; 122*4882a593Smuzhiyun dma_addr_t dma_addr; 123*4882a593Smuzhiyun size_t dma_bytes; 124*4882a593Smuzhiyun }; 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun struct mtk_base_afe_irq { 127*4882a593Smuzhiyun const struct mtk_base_irq_data *irq_data; 128*4882a593Smuzhiyun int irq_occupyed; 129*4882a593Smuzhiyun }; 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun struct mtk_base_afe_dai { 132*4882a593Smuzhiyun struct snd_soc_dai_driver *dai_drivers; 133*4882a593Smuzhiyun unsigned int num_dai_drivers; 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun const struct snd_kcontrol_new *controls; 136*4882a593Smuzhiyun unsigned int num_controls; 137*4882a593Smuzhiyun const struct snd_soc_dapm_widget *dapm_widgets; 138*4882a593Smuzhiyun unsigned int num_dapm_widgets; 139*4882a593Smuzhiyun const struct snd_soc_dapm_route *dapm_routes; 140*4882a593Smuzhiyun unsigned int num_dapm_routes; 141*4882a593Smuzhiyun 142*4882a593Smuzhiyun struct list_head list; 143*4882a593Smuzhiyun }; 144*4882a593Smuzhiyun 145*4882a593Smuzhiyun #endif 146*4882a593Smuzhiyun 147