1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Intel SKL IPC Support 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2014-15, Intel Corporation. 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __SKL_IPC_H 9*4882a593Smuzhiyun #define __SKL_IPC_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include <linux/irqreturn.h> 12*4882a593Smuzhiyun #include "../common/sst-ipc.h" 13*4882a593Smuzhiyun #include "skl-sst-dsp.h" 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun struct sst_dsp; 16*4882a593Smuzhiyun struct sst_generic_ipc; 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun enum skl_ipc_pipeline_state { 19*4882a593Smuzhiyun PPL_INVALID_STATE = 0, 20*4882a593Smuzhiyun PPL_UNINITIALIZED = 1, 21*4882a593Smuzhiyun PPL_RESET = 2, 22*4882a593Smuzhiyun PPL_PAUSED = 3, 23*4882a593Smuzhiyun PPL_RUNNING = 4, 24*4882a593Smuzhiyun PPL_ERROR_STOP = 5, 25*4882a593Smuzhiyun PPL_SAVED = 6, 26*4882a593Smuzhiyun PPL_RESTORED = 7 27*4882a593Smuzhiyun }; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun struct skl_ipc_dxstate_info { 30*4882a593Smuzhiyun u32 core_mask; 31*4882a593Smuzhiyun u32 dx_mask; 32*4882a593Smuzhiyun }; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun struct skl_ipc_header { 35*4882a593Smuzhiyun u32 primary; 36*4882a593Smuzhiyun u32 extension; 37*4882a593Smuzhiyun }; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun struct skl_dsp_cores { 40*4882a593Smuzhiyun unsigned int count; 41*4882a593Smuzhiyun enum skl_dsp_states *state; 42*4882a593Smuzhiyun int *usage_count; 43*4882a593Smuzhiyun }; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun /** 46*4882a593Smuzhiyun * skl_d0i3_data: skl D0i3 counters data struct 47*4882a593Smuzhiyun * 48*4882a593Smuzhiyun * @streaming: Count of usecases that can attempt streaming D0i3 49*4882a593Smuzhiyun * @non_streaming: Count of usecases that can attempt non-streaming D0i3 50*4882a593Smuzhiyun * @non_d0i3: Count of usecases that cannot attempt D0i3 51*4882a593Smuzhiyun * @state: current state 52*4882a593Smuzhiyun * @work: D0i3 worker thread 53*4882a593Smuzhiyun */ 54*4882a593Smuzhiyun struct skl_d0i3_data { 55*4882a593Smuzhiyun int streaming; 56*4882a593Smuzhiyun int non_streaming; 57*4882a593Smuzhiyun int non_d0i3; 58*4882a593Smuzhiyun enum skl_dsp_d0i3_states state; 59*4882a593Smuzhiyun struct delayed_work work; 60*4882a593Smuzhiyun }; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun #define SKL_LIB_NAME_LENGTH 128 63*4882a593Smuzhiyun #define SKL_MAX_LIB 16 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun struct skl_lib_info { 66*4882a593Smuzhiyun char name[SKL_LIB_NAME_LENGTH]; 67*4882a593Smuzhiyun const struct firmware *fw; 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun struct skl_ipc_init_instance_msg { 71*4882a593Smuzhiyun u32 module_id; 72*4882a593Smuzhiyun u32 instance_id; 73*4882a593Smuzhiyun u16 param_data_size; 74*4882a593Smuzhiyun u8 ppl_instance_id; 75*4882a593Smuzhiyun u8 core_id; 76*4882a593Smuzhiyun u8 domain; 77*4882a593Smuzhiyun }; 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun struct skl_ipc_bind_unbind_msg { 80*4882a593Smuzhiyun u32 module_id; 81*4882a593Smuzhiyun u32 instance_id; 82*4882a593Smuzhiyun u32 dst_module_id; 83*4882a593Smuzhiyun u32 dst_instance_id; 84*4882a593Smuzhiyun u8 src_queue; 85*4882a593Smuzhiyun u8 dst_queue; 86*4882a593Smuzhiyun bool bind; 87*4882a593Smuzhiyun }; 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun struct skl_ipc_large_config_msg { 90*4882a593Smuzhiyun u32 module_id; 91*4882a593Smuzhiyun u32 instance_id; 92*4882a593Smuzhiyun u32 large_param_id; 93*4882a593Smuzhiyun u32 param_data_size; 94*4882a593Smuzhiyun }; 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun struct skl_ipc_d0ix_msg { 97*4882a593Smuzhiyun u32 module_id; 98*4882a593Smuzhiyun u32 instance_id; 99*4882a593Smuzhiyun u8 streaming; 100*4882a593Smuzhiyun u8 wake; 101*4882a593Smuzhiyun }; 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun #define SKL_IPC_BOOT_MSECS 3000 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun #define SKL_IPC_D3_MASK 0 106*4882a593Smuzhiyun #define SKL_IPC_D0_MASK 3 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun irqreturn_t skl_dsp_irq_thread_handler(int irq, void *context); 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun int skl_ipc_create_pipeline(struct sst_generic_ipc *ipc, 111*4882a593Smuzhiyun u16 ppl_mem_size, u8 ppl_type, u8 instance_id, u8 lp_mode); 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun int skl_ipc_delete_pipeline(struct sst_generic_ipc *ipc, u8 instance_id); 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun int skl_ipc_set_pipeline_state(struct sst_generic_ipc *ipc, 116*4882a593Smuzhiyun u8 instance_id, enum skl_ipc_pipeline_state state); 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun int skl_ipc_save_pipeline(struct sst_generic_ipc *ipc, 119*4882a593Smuzhiyun u8 instance_id, int dma_id); 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun int skl_ipc_restore_pipeline(struct sst_generic_ipc *ipc, u8 instance_id); 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun int skl_ipc_init_instance(struct sst_generic_ipc *ipc, 124*4882a593Smuzhiyun struct skl_ipc_init_instance_msg *msg, void *param_data); 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun int skl_ipc_bind_unbind(struct sst_generic_ipc *ipc, 127*4882a593Smuzhiyun struct skl_ipc_bind_unbind_msg *msg); 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun int skl_ipc_load_modules(struct sst_generic_ipc *ipc, 130*4882a593Smuzhiyun u8 module_cnt, void *data); 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun int skl_ipc_unload_modules(struct sst_generic_ipc *ipc, 133*4882a593Smuzhiyun u8 module_cnt, void *data); 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun int skl_ipc_set_dx(struct sst_generic_ipc *ipc, 136*4882a593Smuzhiyun u8 instance_id, u16 module_id, struct skl_ipc_dxstate_info *dx); 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun int skl_ipc_set_large_config(struct sst_generic_ipc *ipc, 139*4882a593Smuzhiyun struct skl_ipc_large_config_msg *msg, u32 *param); 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun int skl_ipc_get_large_config(struct sst_generic_ipc *ipc, 142*4882a593Smuzhiyun struct skl_ipc_large_config_msg *msg, 143*4882a593Smuzhiyun u32 **payload, size_t *bytes); 144*4882a593Smuzhiyun 145*4882a593Smuzhiyun int skl_sst_ipc_load_library(struct sst_generic_ipc *ipc, 146*4882a593Smuzhiyun u8 dma_id, u8 table_id, bool wait); 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun int skl_ipc_set_d0ix(struct sst_generic_ipc *ipc, 149*4882a593Smuzhiyun struct skl_ipc_d0ix_msg *msg); 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun int skl_ipc_check_D0i0(struct sst_dsp *dsp, bool state); 152*4882a593Smuzhiyun 153*4882a593Smuzhiyun void skl_ipc_int_enable(struct sst_dsp *ctx); 154*4882a593Smuzhiyun void skl_ipc_op_int_enable(struct sst_dsp *ctx); 155*4882a593Smuzhiyun void skl_ipc_op_int_disable(struct sst_dsp *ctx); 156*4882a593Smuzhiyun void skl_ipc_int_disable(struct sst_dsp *ctx); 157*4882a593Smuzhiyun 158*4882a593Smuzhiyun bool skl_ipc_int_status(struct sst_dsp *ctx); 159*4882a593Smuzhiyun void skl_ipc_free(struct sst_generic_ipc *ipc); 160*4882a593Smuzhiyun int skl_ipc_init(struct device *dev, struct skl_dev *skl); 161*4882a593Smuzhiyun void skl_clear_module_cnt(struct sst_dsp *ctx); 162*4882a593Smuzhiyun 163*4882a593Smuzhiyun void skl_ipc_process_reply(struct sst_generic_ipc *ipc, 164*4882a593Smuzhiyun struct skl_ipc_header header); 165*4882a593Smuzhiyun int skl_ipc_process_notification(struct sst_generic_ipc *ipc, 166*4882a593Smuzhiyun struct skl_ipc_header header); 167*4882a593Smuzhiyun void skl_ipc_tx_data_copy(struct ipc_message *msg, char *tx_data, 168*4882a593Smuzhiyun size_t tx_size); 169*4882a593Smuzhiyun #endif /* __SKL_IPC_H */ 170