1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * skl-ssp-clk.h - Skylake ssp clock information and ipc structure 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2017 Intel Corp 6*4882a593Smuzhiyun * Author: Jaikrishna Nemallapudi <jaikrishnax.nemallapudi@intel.com> 7*4882a593Smuzhiyun * Author: Subhransu S. Prusty <subhransu.s.prusty@intel.com> 8*4882a593Smuzhiyun * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 9*4882a593Smuzhiyun * 10*4882a593Smuzhiyun * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 11*4882a593Smuzhiyun */ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #ifndef SOUND_SOC_SKL_SSP_CLK_H 14*4882a593Smuzhiyun #define SOUND_SOC_SKL_SSP_CLK_H 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #define SKL_MAX_SSP 6 17*4882a593Smuzhiyun /* xtal/cardinal/pll, parent of ssp clocks and mclk */ 18*4882a593Smuzhiyun #define SKL_MAX_CLK_SRC 3 19*4882a593Smuzhiyun #define SKL_MAX_SSP_CLK_TYPES 3 /* mclk, sclk, sclkfs */ 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #define SKL_MAX_CLK_CNT (SKL_MAX_SSP * SKL_MAX_SSP_CLK_TYPES) 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun /* Max number of configurations supported for each clock */ 24*4882a593Smuzhiyun #define SKL_MAX_CLK_RATES 10 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #define SKL_SCLK_OFS SKL_MAX_SSP 27*4882a593Smuzhiyun #define SKL_SCLKFS_OFS (SKL_SCLK_OFS + SKL_MAX_SSP) 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun enum skl_clk_type { 30*4882a593Smuzhiyun SKL_MCLK, 31*4882a593Smuzhiyun SKL_SCLK, 32*4882a593Smuzhiyun SKL_SCLK_FS, 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun enum skl_clk_src_type { 36*4882a593Smuzhiyun SKL_XTAL, 37*4882a593Smuzhiyun SKL_CARDINAL, 38*4882a593Smuzhiyun SKL_PLL, 39*4882a593Smuzhiyun }; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun struct skl_clk_parent_src { 42*4882a593Smuzhiyun u8 clk_id; 43*4882a593Smuzhiyun const char *name; 44*4882a593Smuzhiyun unsigned long rate; 45*4882a593Smuzhiyun const char *parent_name; 46*4882a593Smuzhiyun }; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun struct skl_tlv_hdr { 49*4882a593Smuzhiyun u32 type; 50*4882a593Smuzhiyun u32 size; 51*4882a593Smuzhiyun }; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun struct skl_dmactrl_mclk_cfg { 54*4882a593Smuzhiyun struct skl_tlv_hdr hdr; 55*4882a593Smuzhiyun /* DMA Clk TLV params */ 56*4882a593Smuzhiyun u32 clk_warm_up:16; 57*4882a593Smuzhiyun u32 mclk:1; 58*4882a593Smuzhiyun u32 warm_up_over:1; 59*4882a593Smuzhiyun u32 rsvd0:14; 60*4882a593Smuzhiyun u32 clk_stop_delay:16; 61*4882a593Smuzhiyun u32 keep_running:1; 62*4882a593Smuzhiyun u32 clk_stop_over:1; 63*4882a593Smuzhiyun u32 rsvd1:14; 64*4882a593Smuzhiyun }; 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun struct skl_dmactrl_sclkfs_cfg { 67*4882a593Smuzhiyun struct skl_tlv_hdr hdr; 68*4882a593Smuzhiyun /* DMA SClk&FS TLV params */ 69*4882a593Smuzhiyun u32 sampling_frequency; 70*4882a593Smuzhiyun u32 bit_depth; 71*4882a593Smuzhiyun u32 channel_map; 72*4882a593Smuzhiyun u32 channel_config; 73*4882a593Smuzhiyun u32 interleaving_style; 74*4882a593Smuzhiyun u32 number_of_channels : 8; 75*4882a593Smuzhiyun u32 valid_bit_depth : 8; 76*4882a593Smuzhiyun u32 sample_type : 8; 77*4882a593Smuzhiyun u32 reserved : 8; 78*4882a593Smuzhiyun }; 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun union skl_clk_ctrl_ipc { 81*4882a593Smuzhiyun struct skl_dmactrl_mclk_cfg mclk; 82*4882a593Smuzhiyun struct skl_dmactrl_sclkfs_cfg sclk_fs; 83*4882a593Smuzhiyun }; 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun struct skl_clk_rate_cfg_table { 86*4882a593Smuzhiyun unsigned long rate; 87*4882a593Smuzhiyun union skl_clk_ctrl_ipc dma_ctl_ipc; 88*4882a593Smuzhiyun void *config; 89*4882a593Smuzhiyun }; 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun /* 92*4882a593Smuzhiyun * rate for mclk will be in rates[0]. For sclk and sclkfs, rates[] store 93*4882a593Smuzhiyun * all possible clocks ssp can generate for that platform. 94*4882a593Smuzhiyun */ 95*4882a593Smuzhiyun struct skl_ssp_clk { 96*4882a593Smuzhiyun const char *name; 97*4882a593Smuzhiyun const char *parent_name; 98*4882a593Smuzhiyun struct skl_clk_rate_cfg_table rate_cfg[SKL_MAX_CLK_RATES]; 99*4882a593Smuzhiyun }; 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun struct skl_clk_pdata { 102*4882a593Smuzhiyun struct skl_clk_parent_src *parent_clks; 103*4882a593Smuzhiyun int num_clks; 104*4882a593Smuzhiyun struct skl_ssp_clk *ssp_clks; 105*4882a593Smuzhiyun void *pvt_data; 106*4882a593Smuzhiyun }; 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun #endif /* SOUND_SOC_SKL_SSP_CLK_H */ 109