1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Cannonlake SST DSP Support 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2016-17, Intel Corporation. 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __CNL_SST_DSP_H__ 9*4882a593Smuzhiyun #define __CNL_SST_DSP_H__ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun struct sst_dsp; 12*4882a593Smuzhiyun struct sst_dsp_device; 13*4882a593Smuzhiyun struct sst_generic_ipc; 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /* Intel HD Audio General DSP Registers */ 16*4882a593Smuzhiyun #define CNL_ADSP_GEN_BASE 0x0 17*4882a593Smuzhiyun #define CNL_ADSP_REG_ADSPCS (CNL_ADSP_GEN_BASE + 0x04) 18*4882a593Smuzhiyun #define CNL_ADSP_REG_ADSPIC (CNL_ADSP_GEN_BASE + 0x08) 19*4882a593Smuzhiyun #define CNL_ADSP_REG_ADSPIS (CNL_ADSP_GEN_BASE + 0x0c) 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun /* Intel HD Audio Inter-Processor Communication Registers */ 22*4882a593Smuzhiyun #define CNL_ADSP_IPC_BASE 0xc0 23*4882a593Smuzhiyun #define CNL_ADSP_REG_HIPCTDR (CNL_ADSP_IPC_BASE + 0x00) 24*4882a593Smuzhiyun #define CNL_ADSP_REG_HIPCTDA (CNL_ADSP_IPC_BASE + 0x04) 25*4882a593Smuzhiyun #define CNL_ADSP_REG_HIPCTDD (CNL_ADSP_IPC_BASE + 0x08) 26*4882a593Smuzhiyun #define CNL_ADSP_REG_HIPCIDR (CNL_ADSP_IPC_BASE + 0x10) 27*4882a593Smuzhiyun #define CNL_ADSP_REG_HIPCIDA (CNL_ADSP_IPC_BASE + 0x14) 28*4882a593Smuzhiyun #define CNL_ADSP_REG_HIPCIDD (CNL_ADSP_IPC_BASE + 0x18) 29*4882a593Smuzhiyun #define CNL_ADSP_REG_HIPCCTL (CNL_ADSP_IPC_BASE + 0x28) 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /* HIPCTDR */ 32*4882a593Smuzhiyun #define CNL_ADSP_REG_HIPCTDR_BUSY BIT(31) 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun /* HIPCTDA */ 35*4882a593Smuzhiyun #define CNL_ADSP_REG_HIPCTDA_DONE BIT(31) 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /* HIPCIDR */ 38*4882a593Smuzhiyun #define CNL_ADSP_REG_HIPCIDR_BUSY BIT(31) 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun /* HIPCIDA */ 41*4882a593Smuzhiyun #define CNL_ADSP_REG_HIPCIDA_DONE BIT(31) 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun /* CNL HIPCCTL */ 44*4882a593Smuzhiyun #define CNL_ADSP_REG_HIPCCTL_DONE BIT(1) 45*4882a593Smuzhiyun #define CNL_ADSP_REG_HIPCCTL_BUSY BIT(0) 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun /* CNL HIPCT */ 48*4882a593Smuzhiyun #define CNL_ADSP_REG_HIPCT_BUSY BIT(31) 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun /* Intel HD Audio SRAM Window 1 */ 51*4882a593Smuzhiyun #define CNL_ADSP_SRAM1_BASE 0xa0000 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun #define CNL_ADSP_MMIO_LEN 0x10000 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun #define CNL_ADSP_W0_STAT_SZ 0x1000 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun #define CNL_ADSP_W0_UP_SZ 0x1000 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun #define CNL_ADSP_W1_SZ 0x1000 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun #define CNL_FW_STS_MASK 0xf 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun #define CNL_ADSPIC_IPC 0x1 64*4882a593Smuzhiyun #define CNL_ADSPIS_IPC 0x1 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun #define CNL_DSP_CORES 4 67*4882a593Smuzhiyun #define CNL_DSP_CORES_MASK ((1 << CNL_DSP_CORES) - 1) 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun /* core reset - asserted high */ 70*4882a593Smuzhiyun #define CNL_ADSPCS_CRST_SHIFT 0 71*4882a593Smuzhiyun #define CNL_ADSPCS_CRST(x) (x << CNL_ADSPCS_CRST_SHIFT) 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun /* core run/stall - when set to 1 core is stalled */ 74*4882a593Smuzhiyun #define CNL_ADSPCS_CSTALL_SHIFT 8 75*4882a593Smuzhiyun #define CNL_ADSPCS_CSTALL(x) (x << CNL_ADSPCS_CSTALL_SHIFT) 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun /* set power active - when set to 1 turn core on */ 78*4882a593Smuzhiyun #define CNL_ADSPCS_SPA_SHIFT 16 79*4882a593Smuzhiyun #define CNL_ADSPCS_SPA(x) (x << CNL_ADSPCS_SPA_SHIFT) 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun /* current power active - power status of cores, set by hardware */ 82*4882a593Smuzhiyun #define CNL_ADSPCS_CPA_SHIFT 24 83*4882a593Smuzhiyun #define CNL_ADSPCS_CPA(x) (x << CNL_ADSPCS_CPA_SHIFT) 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun int cnl_dsp_enable_core(struct sst_dsp *ctx, unsigned int core_mask); 86*4882a593Smuzhiyun int cnl_dsp_disable_core(struct sst_dsp *ctx, unsigned int core_mask); 87*4882a593Smuzhiyun irqreturn_t cnl_dsp_sst_interrupt(int irq, void *dev_id); 88*4882a593Smuzhiyun void cnl_dsp_free(struct sst_dsp *dsp); 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun void cnl_ipc_int_enable(struct sst_dsp *ctx); 91*4882a593Smuzhiyun void cnl_ipc_int_disable(struct sst_dsp *ctx); 92*4882a593Smuzhiyun void cnl_ipc_op_int_enable(struct sst_dsp *ctx); 93*4882a593Smuzhiyun void cnl_ipc_op_int_disable(struct sst_dsp *ctx); 94*4882a593Smuzhiyun bool cnl_ipc_int_status(struct sst_dsp *ctx); 95*4882a593Smuzhiyun void cnl_ipc_free(struct sst_generic_ipc *ipc); 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun int cnl_sst_dsp_init(struct device *dev, void __iomem *mmio_base, int irq, 98*4882a593Smuzhiyun const char *fw_name, struct skl_dsp_loader_ops dsp_ops, 99*4882a593Smuzhiyun struct skl_dev **dsp); 100*4882a593Smuzhiyun int cnl_sst_init_fw(struct device *dev, struct skl_dev *skl); 101*4882a593Smuzhiyun void cnl_sst_dsp_cleanup(struct device *dev, struct skl_dev *skl); 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun #endif /*__CNL_SST_DSP_H__*/ 104