1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Intel KeemBay Platform driver 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2020 Intel Corporation. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef KMB_PLATFORM_H_ 10*4882a593Smuzhiyun #define KMB_PLATFORM_H_ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #include <linux/bits.h> 13*4882a593Smuzhiyun #include <linux/bitfield.h> 14*4882a593Smuzhiyun #include <linux/types.h> 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* Register values with reference to KMB databook v1.1 */ 17*4882a593Smuzhiyun /* common register for all channel */ 18*4882a593Smuzhiyun #define IER 0x000 19*4882a593Smuzhiyun #define IRER 0x004 20*4882a593Smuzhiyun #define ITER 0x008 21*4882a593Smuzhiyun #define CER 0x00C 22*4882a593Smuzhiyun #define CCR 0x010 23*4882a593Smuzhiyun #define RXFFR 0x014 24*4882a593Smuzhiyun #define TXFFR 0x018 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun /* Interrupt status register fields */ 27*4882a593Smuzhiyun #define ISR_TXFO BIT(5) 28*4882a593Smuzhiyun #define ISR_TXFE BIT(4) 29*4882a593Smuzhiyun #define ISR_RXFO BIT(1) 30*4882a593Smuzhiyun #define ISR_RXDA BIT(0) 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun /* I2S Tx Rx Registers for all channels */ 33*4882a593Smuzhiyun #define LRBR_LTHR(x) (0x40 * (x) + 0x020) 34*4882a593Smuzhiyun #define RRBR_RTHR(x) (0x40 * (x) + 0x024) 35*4882a593Smuzhiyun #define RER(x) (0x40 * (x) + 0x028) 36*4882a593Smuzhiyun #define TER(x) (0x40 * (x) + 0x02C) 37*4882a593Smuzhiyun #define RCR(x) (0x40 * (x) + 0x030) 38*4882a593Smuzhiyun #define TCR(x) (0x40 * (x) + 0x034) 39*4882a593Smuzhiyun #define ISR(x) (0x40 * (x) + 0x038) 40*4882a593Smuzhiyun #define IMR(x) (0x40 * (x) + 0x03C) 41*4882a593Smuzhiyun #define ROR(x) (0x40 * (x) + 0x040) 42*4882a593Smuzhiyun #define TOR(x) (0x40 * (x) + 0x044) 43*4882a593Smuzhiyun #define RFCR(x) (0x40 * (x) + 0x048) 44*4882a593Smuzhiyun #define TFCR(x) (0x40 * (x) + 0x04C) 45*4882a593Smuzhiyun #define RFF(x) (0x40 * (x) + 0x050) 46*4882a593Smuzhiyun #define TFF(x) (0x40 * (x) + 0x054) 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun /* I2S COMP Registers */ 49*4882a593Smuzhiyun #define I2S_COMP_PARAM_2 0x01F0 50*4882a593Smuzhiyun #define I2S_COMP_PARAM_1 0x01F4 51*4882a593Smuzhiyun #define I2S_COMP_VERSION 0x01F8 52*4882a593Smuzhiyun #define I2S_COMP_TYPE 0x01FC 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun /* PSS_GEN_CTRL_I2S_GEN_CFG_0 Registers */ 55*4882a593Smuzhiyun #define I2S_GEN_CFG_0 0x000 56*4882a593Smuzhiyun #define PSS_CPR_RST_EN 0x010 57*4882a593Smuzhiyun #define PSS_CPR_RST_SET 0x014 58*4882a593Smuzhiyun #define PSS_CPR_CLK_CLR 0x000 59*4882a593Smuzhiyun #define PSS_CPR_AUX_RST_EN 0x070 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun #define MASTER_MODE BIT(13) 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun /* Interrupt Flag */ 64*4882a593Smuzhiyun #define TX_INT_FLAG GENMASK(5, 4) 65*4882a593Smuzhiyun #define RX_INT_FLAG GENMASK(1, 0) 66*4882a593Smuzhiyun /* 67*4882a593Smuzhiyun * Component parameter register fields - define the I2S block's 68*4882a593Smuzhiyun * configuration. 69*4882a593Smuzhiyun */ 70*4882a593Smuzhiyun #define COMP1_TX_WORDSIZE_3(r) FIELD_GET(GENMASK(27, 25), (r)) 71*4882a593Smuzhiyun #define COMP1_TX_WORDSIZE_2(r) FIELD_GET(GENMASK(24, 22), (r)) 72*4882a593Smuzhiyun #define COMP1_TX_WORDSIZE_1(r) FIELD_GET(GENMASK(21, 19), (r)) 73*4882a593Smuzhiyun #define COMP1_TX_WORDSIZE_0(r) FIELD_GET(GENMASK(18, 16), (r)) 74*4882a593Smuzhiyun #define COMP1_RX_ENABLED(r) FIELD_GET(BIT(6), (r)) 75*4882a593Smuzhiyun #define COMP1_TX_ENABLED(r) FIELD_GET(BIT(5), (r)) 76*4882a593Smuzhiyun #define COMP1_MODE_EN(r) FIELD_GET(BIT(4), (r)) 77*4882a593Smuzhiyun #define COMP1_APB_DATA_WIDTH(r) FIELD_GET(GENMASK(1, 0), (r)) 78*4882a593Smuzhiyun #define COMP2_RX_WORDSIZE_3(r) FIELD_GET(GENMASK(12, 10), (r)) 79*4882a593Smuzhiyun #define COMP2_RX_WORDSIZE_2(r) FIELD_GET(GENMASK(9, 7), (r)) 80*4882a593Smuzhiyun #define COMP2_RX_WORDSIZE_1(r) FIELD_GET(GENMASK(5, 3), (r)) 81*4882a593Smuzhiyun #define COMP2_RX_WORDSIZE_0(r) FIELD_GET(GENMASK(2, 0), (r)) 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun /* Add 1 to the below registers to indicate the actual size */ 84*4882a593Smuzhiyun #define COMP1_TX_CHANNELS(r) (FIELD_GET(GENMASK(10, 9), (r)) + 1) 85*4882a593Smuzhiyun #define COMP1_RX_CHANNELS(r) (FIELD_GET(GENMASK(8, 7), (r)) + 1) 86*4882a593Smuzhiyun #define COMP1_FIFO_DEPTH(r) (FIELD_GET(GENMASK(3, 2), (r)) + 1) 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun /* Number of entries in WORDSIZE and DATA_WIDTH parameter registers */ 89*4882a593Smuzhiyun #define COMP_MAX_WORDSIZE 8 /* 3 bits register width */ 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun #define MAX_CHANNEL_NUM 8 92*4882a593Smuzhiyun #define MIN_CHANNEL_NUM 2 93*4882a593Smuzhiyun #define MAX_ISR 4 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun #define TWO_CHANNEL_SUPPORT 2 /* up to 2.0 */ 96*4882a593Smuzhiyun #define FOUR_CHANNEL_SUPPORT 4 /* up to 3.1 */ 97*4882a593Smuzhiyun #define SIX_CHANNEL_SUPPORT 6 /* up to 5.1 */ 98*4882a593Smuzhiyun #define EIGHT_CHANNEL_SUPPORT 8 /* up to 7.1 */ 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun #define DWC_I2S_PLAY BIT(0) 101*4882a593Smuzhiyun #define DWC_I2S_RECORD BIT(1) 102*4882a593Smuzhiyun #define DW_I2S_SLAVE BIT(2) 103*4882a593Smuzhiyun #define DW_I2S_MASTER BIT(3) 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun #define I2S_RXDMA 0x01C0 106*4882a593Smuzhiyun #define I2S_TXDMA 0x01C8 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun /* 109*4882a593Smuzhiyun * struct i2s_clk_config_data - represent i2s clk configuration data 110*4882a593Smuzhiyun * @chan_nr: number of channel 111*4882a593Smuzhiyun * @data_width: number of bits per sample (8/16/24/32 bit) 112*4882a593Smuzhiyun * @sample_rate: sampling frequency (8Khz, 16Khz, 48Khz) 113*4882a593Smuzhiyun */ 114*4882a593Smuzhiyun struct i2s_clk_config_data { 115*4882a593Smuzhiyun int chan_nr; 116*4882a593Smuzhiyun u32 data_width; 117*4882a593Smuzhiyun u32 sample_rate; 118*4882a593Smuzhiyun }; 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun struct kmb_i2s_info { 121*4882a593Smuzhiyun void __iomem *i2s_base; 122*4882a593Smuzhiyun void __iomem *pss_base; 123*4882a593Smuzhiyun struct clk *clk_i2s; 124*4882a593Smuzhiyun struct clk *clk_apb; 125*4882a593Smuzhiyun int active; 126*4882a593Smuzhiyun unsigned int capability; 127*4882a593Smuzhiyun unsigned int i2s_reg_comp1; 128*4882a593Smuzhiyun unsigned int i2s_reg_comp2; 129*4882a593Smuzhiyun struct device *dev; 130*4882a593Smuzhiyun u32 ccr; 131*4882a593Smuzhiyun u32 xfer_resolution; 132*4882a593Smuzhiyun u32 fifo_th; 133*4882a593Smuzhiyun bool master; 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun struct i2s_clk_config_data config; 136*4882a593Smuzhiyun int (*i2s_clk_cfg)(struct i2s_clk_config_data *config); 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun /* data related to PIO transfers */ 139*4882a593Smuzhiyun bool use_pio; 140*4882a593Smuzhiyun struct snd_pcm_substream *tx_substream; 141*4882a593Smuzhiyun struct snd_pcm_substream *rx_substream; 142*4882a593Smuzhiyun unsigned int tx_ptr; 143*4882a593Smuzhiyun unsigned int rx_ptr; 144*4882a593Smuzhiyun }; 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun #endif /* KMB_PLATFORM_H_ */ 147