xref: /OK3568_Linux_fs/kernel/sound/soc/intel/catpt/loader.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun //
3*4882a593Smuzhiyun // Copyright(c) 2020 Intel Corporation. All rights reserved.
4*4882a593Smuzhiyun //
5*4882a593Smuzhiyun // Author: Cezary Rojewski <cezary.rojewski@intel.com>
6*4882a593Smuzhiyun //
7*4882a593Smuzhiyun 
8*4882a593Smuzhiyun #include <linux/dma-mapping.h>
9*4882a593Smuzhiyun #include <linux/firmware.h>
10*4882a593Smuzhiyun #include <linux/slab.h>
11*4882a593Smuzhiyun #include "core.h"
12*4882a593Smuzhiyun #include "registers.h"
13*4882a593Smuzhiyun 
14*4882a593Smuzhiyun /* FW load (200ms) plus operational delays */
15*4882a593Smuzhiyun #define FW_READY_TIMEOUT_MS	250
16*4882a593Smuzhiyun 
17*4882a593Smuzhiyun #define FW_SIGNATURE		"$SST"
18*4882a593Smuzhiyun #define FW_SIGNATURE_SIZE	4
19*4882a593Smuzhiyun 
20*4882a593Smuzhiyun struct catpt_fw_hdr {
21*4882a593Smuzhiyun 	char signature[FW_SIGNATURE_SIZE];
22*4882a593Smuzhiyun 	u32 file_size;
23*4882a593Smuzhiyun 	u32 modules;
24*4882a593Smuzhiyun 	u32 file_format;
25*4882a593Smuzhiyun 	u32 reserved[4];
26*4882a593Smuzhiyun } __packed;
27*4882a593Smuzhiyun 
28*4882a593Smuzhiyun struct catpt_fw_mod_hdr {
29*4882a593Smuzhiyun 	char signature[FW_SIGNATURE_SIZE];
30*4882a593Smuzhiyun 	u32 mod_size;
31*4882a593Smuzhiyun 	u32 blocks;
32*4882a593Smuzhiyun 	u16 slot;
33*4882a593Smuzhiyun 	u16 module_id;
34*4882a593Smuzhiyun 	u32 entry_point;
35*4882a593Smuzhiyun 	u32 persistent_size;
36*4882a593Smuzhiyun 	u32 scratch_size;
37*4882a593Smuzhiyun } __packed;
38*4882a593Smuzhiyun 
39*4882a593Smuzhiyun enum catpt_ram_type {
40*4882a593Smuzhiyun 	CATPT_RAM_TYPE_IRAM = 1,
41*4882a593Smuzhiyun 	CATPT_RAM_TYPE_DRAM = 2,
42*4882a593Smuzhiyun 	/* DRAM with module's initial state */
43*4882a593Smuzhiyun 	CATPT_RAM_TYPE_INSTANCE = 3,
44*4882a593Smuzhiyun };
45*4882a593Smuzhiyun 
46*4882a593Smuzhiyun struct catpt_fw_block_hdr {
47*4882a593Smuzhiyun 	u32 ram_type;
48*4882a593Smuzhiyun 	u32 size;
49*4882a593Smuzhiyun 	u32 ram_offset;
50*4882a593Smuzhiyun 	u32 rsvd;
51*4882a593Smuzhiyun } __packed;
52*4882a593Smuzhiyun 
catpt_sram_init(struct resource * sram,u32 start,u32 size)53*4882a593Smuzhiyun void catpt_sram_init(struct resource *sram, u32 start, u32 size)
54*4882a593Smuzhiyun {
55*4882a593Smuzhiyun 	sram->start = start;
56*4882a593Smuzhiyun 	sram->end = start + size - 1;
57*4882a593Smuzhiyun }
58*4882a593Smuzhiyun 
catpt_sram_free(struct resource * sram)59*4882a593Smuzhiyun void catpt_sram_free(struct resource *sram)
60*4882a593Smuzhiyun {
61*4882a593Smuzhiyun 	struct resource *res, *save;
62*4882a593Smuzhiyun 
63*4882a593Smuzhiyun 	for (res = sram->child; res;) {
64*4882a593Smuzhiyun 		save = res->sibling;
65*4882a593Smuzhiyun 		release_resource(res);
66*4882a593Smuzhiyun 		kfree(res);
67*4882a593Smuzhiyun 		res = save;
68*4882a593Smuzhiyun 	}
69*4882a593Smuzhiyun }
70*4882a593Smuzhiyun 
71*4882a593Smuzhiyun struct resource *
catpt_request_region(struct resource * root,resource_size_t size)72*4882a593Smuzhiyun catpt_request_region(struct resource *root, resource_size_t size)
73*4882a593Smuzhiyun {
74*4882a593Smuzhiyun 	struct resource *res = root->child;
75*4882a593Smuzhiyun 	resource_size_t addr = root->start;
76*4882a593Smuzhiyun 
77*4882a593Smuzhiyun 	for (;;) {
78*4882a593Smuzhiyun 		if (res->start - addr >= size)
79*4882a593Smuzhiyun 			break;
80*4882a593Smuzhiyun 		addr = res->end + 1;
81*4882a593Smuzhiyun 		res = res->sibling;
82*4882a593Smuzhiyun 		if (!res)
83*4882a593Smuzhiyun 			return NULL;
84*4882a593Smuzhiyun 	}
85*4882a593Smuzhiyun 
86*4882a593Smuzhiyun 	return __request_region(root, addr, size, NULL, 0);
87*4882a593Smuzhiyun }
88*4882a593Smuzhiyun 
catpt_store_streams_context(struct catpt_dev * cdev,struct dma_chan * chan)89*4882a593Smuzhiyun int catpt_store_streams_context(struct catpt_dev *cdev, struct dma_chan *chan)
90*4882a593Smuzhiyun {
91*4882a593Smuzhiyun 	struct catpt_stream_runtime *stream;
92*4882a593Smuzhiyun 
93*4882a593Smuzhiyun 	list_for_each_entry(stream, &cdev->stream_list, node) {
94*4882a593Smuzhiyun 		u32 off, size;
95*4882a593Smuzhiyun 		int ret;
96*4882a593Smuzhiyun 
97*4882a593Smuzhiyun 		off = stream->persistent->start;
98*4882a593Smuzhiyun 		size = resource_size(stream->persistent);
99*4882a593Smuzhiyun 		dev_dbg(cdev->dev, "storing stream %d ctx: off 0x%08x size %d\n",
100*4882a593Smuzhiyun 			stream->info.stream_hw_id, off, size);
101*4882a593Smuzhiyun 
102*4882a593Smuzhiyun 		ret = catpt_dma_memcpy_fromdsp(cdev, chan,
103*4882a593Smuzhiyun 					       cdev->dxbuf_paddr + off,
104*4882a593Smuzhiyun 					       cdev->lpe_base + off,
105*4882a593Smuzhiyun 					       ALIGN(size, 4));
106*4882a593Smuzhiyun 		if (ret) {
107*4882a593Smuzhiyun 			dev_err(cdev->dev, "memcpy fromdsp failed: %d\n", ret);
108*4882a593Smuzhiyun 			return ret;
109*4882a593Smuzhiyun 		}
110*4882a593Smuzhiyun 	}
111*4882a593Smuzhiyun 
112*4882a593Smuzhiyun 	return 0;
113*4882a593Smuzhiyun }
114*4882a593Smuzhiyun 
catpt_store_module_states(struct catpt_dev * cdev,struct dma_chan * chan)115*4882a593Smuzhiyun int catpt_store_module_states(struct catpt_dev *cdev, struct dma_chan *chan)
116*4882a593Smuzhiyun {
117*4882a593Smuzhiyun 	int i;
118*4882a593Smuzhiyun 
119*4882a593Smuzhiyun 	for (i = 0; i < ARRAY_SIZE(cdev->modules); i++) {
120*4882a593Smuzhiyun 		struct catpt_module_type *type;
121*4882a593Smuzhiyun 		u32 off;
122*4882a593Smuzhiyun 		int ret;
123*4882a593Smuzhiyun 
124*4882a593Smuzhiyun 		type = &cdev->modules[i];
125*4882a593Smuzhiyun 		if (!type->loaded || !type->state_size)
126*4882a593Smuzhiyun 			continue;
127*4882a593Smuzhiyun 
128*4882a593Smuzhiyun 		off = type->state_offset;
129*4882a593Smuzhiyun 		dev_dbg(cdev->dev, "storing mod %d state: off 0x%08x size %d\n",
130*4882a593Smuzhiyun 			i, off, type->state_size);
131*4882a593Smuzhiyun 
132*4882a593Smuzhiyun 		ret = catpt_dma_memcpy_fromdsp(cdev, chan,
133*4882a593Smuzhiyun 					       cdev->dxbuf_paddr + off,
134*4882a593Smuzhiyun 					       cdev->lpe_base + off,
135*4882a593Smuzhiyun 					       ALIGN(type->state_size, 4));
136*4882a593Smuzhiyun 		if (ret) {
137*4882a593Smuzhiyun 			dev_err(cdev->dev, "memcpy fromdsp failed: %d\n", ret);
138*4882a593Smuzhiyun 			return ret;
139*4882a593Smuzhiyun 		}
140*4882a593Smuzhiyun 	}
141*4882a593Smuzhiyun 
142*4882a593Smuzhiyun 	return 0;
143*4882a593Smuzhiyun }
144*4882a593Smuzhiyun 
catpt_store_memdumps(struct catpt_dev * cdev,struct dma_chan * chan)145*4882a593Smuzhiyun int catpt_store_memdumps(struct catpt_dev *cdev, struct dma_chan *chan)
146*4882a593Smuzhiyun {
147*4882a593Smuzhiyun 	int i;
148*4882a593Smuzhiyun 
149*4882a593Smuzhiyun 	for (i = 0; i < cdev->dx_ctx.num_meminfo; i++) {
150*4882a593Smuzhiyun 		struct catpt_save_meminfo *info;
151*4882a593Smuzhiyun 		u32 off;
152*4882a593Smuzhiyun 		int ret;
153*4882a593Smuzhiyun 
154*4882a593Smuzhiyun 		info = &cdev->dx_ctx.meminfo[i];
155*4882a593Smuzhiyun 		if (info->source != CATPT_DX_TYPE_MEMORY_DUMP)
156*4882a593Smuzhiyun 			continue;
157*4882a593Smuzhiyun 
158*4882a593Smuzhiyun 		off = catpt_to_host_offset(info->offset);
159*4882a593Smuzhiyun 		if (off < cdev->dram.start || off > cdev->dram.end)
160*4882a593Smuzhiyun 			continue;
161*4882a593Smuzhiyun 
162*4882a593Smuzhiyun 		dev_dbg(cdev->dev, "storing memdump: off 0x%08x size %d\n",
163*4882a593Smuzhiyun 			off, info->size);
164*4882a593Smuzhiyun 
165*4882a593Smuzhiyun 		ret = catpt_dma_memcpy_fromdsp(cdev, chan,
166*4882a593Smuzhiyun 					       cdev->dxbuf_paddr + off,
167*4882a593Smuzhiyun 					       cdev->lpe_base + off,
168*4882a593Smuzhiyun 					       ALIGN(info->size, 4));
169*4882a593Smuzhiyun 		if (ret) {
170*4882a593Smuzhiyun 			dev_err(cdev->dev, "memcpy fromdsp failed: %d\n", ret);
171*4882a593Smuzhiyun 			return ret;
172*4882a593Smuzhiyun 		}
173*4882a593Smuzhiyun 	}
174*4882a593Smuzhiyun 
175*4882a593Smuzhiyun 	return 0;
176*4882a593Smuzhiyun }
177*4882a593Smuzhiyun 
178*4882a593Smuzhiyun static int
catpt_restore_streams_context(struct catpt_dev * cdev,struct dma_chan * chan)179*4882a593Smuzhiyun catpt_restore_streams_context(struct catpt_dev *cdev, struct dma_chan *chan)
180*4882a593Smuzhiyun {
181*4882a593Smuzhiyun 	struct catpt_stream_runtime *stream;
182*4882a593Smuzhiyun 
183*4882a593Smuzhiyun 	list_for_each_entry(stream, &cdev->stream_list, node) {
184*4882a593Smuzhiyun 		u32 off, size;
185*4882a593Smuzhiyun 		int ret;
186*4882a593Smuzhiyun 
187*4882a593Smuzhiyun 		off = stream->persistent->start;
188*4882a593Smuzhiyun 		size = resource_size(stream->persistent);
189*4882a593Smuzhiyun 		dev_dbg(cdev->dev, "restoring stream %d ctx: off 0x%08x size %d\n",
190*4882a593Smuzhiyun 			stream->info.stream_hw_id, off, size);
191*4882a593Smuzhiyun 
192*4882a593Smuzhiyun 		ret = catpt_dma_memcpy_todsp(cdev, chan,
193*4882a593Smuzhiyun 					     cdev->lpe_base + off,
194*4882a593Smuzhiyun 					     cdev->dxbuf_paddr + off,
195*4882a593Smuzhiyun 					     ALIGN(size, 4));
196*4882a593Smuzhiyun 		if (ret) {
197*4882a593Smuzhiyun 			dev_err(cdev->dev, "memcpy fromdsp failed: %d\n", ret);
198*4882a593Smuzhiyun 			return ret;
199*4882a593Smuzhiyun 		}
200*4882a593Smuzhiyun 	}
201*4882a593Smuzhiyun 
202*4882a593Smuzhiyun 	return 0;
203*4882a593Smuzhiyun }
204*4882a593Smuzhiyun 
catpt_restore_memdumps(struct catpt_dev * cdev,struct dma_chan * chan)205*4882a593Smuzhiyun static int catpt_restore_memdumps(struct catpt_dev *cdev, struct dma_chan *chan)
206*4882a593Smuzhiyun {
207*4882a593Smuzhiyun 	int i;
208*4882a593Smuzhiyun 
209*4882a593Smuzhiyun 	for (i = 0; i < cdev->dx_ctx.num_meminfo; i++) {
210*4882a593Smuzhiyun 		struct catpt_save_meminfo *info;
211*4882a593Smuzhiyun 		u32 off;
212*4882a593Smuzhiyun 		int ret;
213*4882a593Smuzhiyun 
214*4882a593Smuzhiyun 		info = &cdev->dx_ctx.meminfo[i];
215*4882a593Smuzhiyun 		if (info->source != CATPT_DX_TYPE_MEMORY_DUMP)
216*4882a593Smuzhiyun 			continue;
217*4882a593Smuzhiyun 
218*4882a593Smuzhiyun 		off = catpt_to_host_offset(info->offset);
219*4882a593Smuzhiyun 		if (off < cdev->dram.start || off > cdev->dram.end)
220*4882a593Smuzhiyun 			continue;
221*4882a593Smuzhiyun 
222*4882a593Smuzhiyun 		dev_dbg(cdev->dev, "restoring memdump: off 0x%08x size %d\n",
223*4882a593Smuzhiyun 			off, info->size);
224*4882a593Smuzhiyun 
225*4882a593Smuzhiyun 		ret = catpt_dma_memcpy_todsp(cdev, chan,
226*4882a593Smuzhiyun 					     cdev->lpe_base + off,
227*4882a593Smuzhiyun 					     cdev->dxbuf_paddr + off,
228*4882a593Smuzhiyun 					     ALIGN(info->size, 4));
229*4882a593Smuzhiyun 		if (ret) {
230*4882a593Smuzhiyun 			dev_err(cdev->dev, "restore block failed: %d\n", ret);
231*4882a593Smuzhiyun 			return ret;
232*4882a593Smuzhiyun 		}
233*4882a593Smuzhiyun 	}
234*4882a593Smuzhiyun 
235*4882a593Smuzhiyun 	return 0;
236*4882a593Smuzhiyun }
237*4882a593Smuzhiyun 
catpt_restore_fwimage(struct catpt_dev * cdev,struct dma_chan * chan,dma_addr_t paddr,struct catpt_fw_block_hdr * blk)238*4882a593Smuzhiyun static int catpt_restore_fwimage(struct catpt_dev *cdev,
239*4882a593Smuzhiyun 				 struct dma_chan *chan, dma_addr_t paddr,
240*4882a593Smuzhiyun 				 struct catpt_fw_block_hdr *blk)
241*4882a593Smuzhiyun {
242*4882a593Smuzhiyun 	struct resource r1, r2, common;
243*4882a593Smuzhiyun 	int i;
244*4882a593Smuzhiyun 
245*4882a593Smuzhiyun 	print_hex_dump_debug(__func__, DUMP_PREFIX_OFFSET, 8, 4,
246*4882a593Smuzhiyun 			     blk, sizeof(*blk), false);
247*4882a593Smuzhiyun 
248*4882a593Smuzhiyun 	r1.start = cdev->dram.start + blk->ram_offset;
249*4882a593Smuzhiyun 	r1.end = r1.start + blk->size - 1;
250*4882a593Smuzhiyun 	/* advance to data area */
251*4882a593Smuzhiyun 	paddr += sizeof(*blk);
252*4882a593Smuzhiyun 
253*4882a593Smuzhiyun 	for (i = 0; i < cdev->dx_ctx.num_meminfo; i++) {
254*4882a593Smuzhiyun 		struct catpt_save_meminfo *info;
255*4882a593Smuzhiyun 		u32 off;
256*4882a593Smuzhiyun 		int ret;
257*4882a593Smuzhiyun 
258*4882a593Smuzhiyun 		info = &cdev->dx_ctx.meminfo[i];
259*4882a593Smuzhiyun 
260*4882a593Smuzhiyun 		if (info->source != CATPT_DX_TYPE_FW_IMAGE)
261*4882a593Smuzhiyun 			continue;
262*4882a593Smuzhiyun 
263*4882a593Smuzhiyun 		off = catpt_to_host_offset(info->offset);
264*4882a593Smuzhiyun 		if (off < cdev->dram.start || off > cdev->dram.end)
265*4882a593Smuzhiyun 			continue;
266*4882a593Smuzhiyun 
267*4882a593Smuzhiyun 		r2.start = off;
268*4882a593Smuzhiyun 		r2.end = r2.start + info->size - 1;
269*4882a593Smuzhiyun 
270*4882a593Smuzhiyun 		if (!catpt_resource_overlapping(&r2, &r1, &common))
271*4882a593Smuzhiyun 			continue;
272*4882a593Smuzhiyun 		/* calculate start offset of common data area */
273*4882a593Smuzhiyun 		off = common.start - r1.start;
274*4882a593Smuzhiyun 
275*4882a593Smuzhiyun 		dev_dbg(cdev->dev, "restoring fwimage: %pr\n", &common);
276*4882a593Smuzhiyun 
277*4882a593Smuzhiyun 		ret = catpt_dma_memcpy_todsp(cdev, chan, common.start,
278*4882a593Smuzhiyun 					     paddr + off,
279*4882a593Smuzhiyun 					     resource_size(&common));
280*4882a593Smuzhiyun 		if (ret) {
281*4882a593Smuzhiyun 			dev_err(cdev->dev, "memcpy todsp failed: %d\n", ret);
282*4882a593Smuzhiyun 			return ret;
283*4882a593Smuzhiyun 		}
284*4882a593Smuzhiyun 	}
285*4882a593Smuzhiyun 
286*4882a593Smuzhiyun 	return 0;
287*4882a593Smuzhiyun }
288*4882a593Smuzhiyun 
catpt_load_block(struct catpt_dev * cdev,struct dma_chan * chan,dma_addr_t paddr,struct catpt_fw_block_hdr * blk,bool alloc)289*4882a593Smuzhiyun static int catpt_load_block(struct catpt_dev *cdev,
290*4882a593Smuzhiyun 			    struct dma_chan *chan, dma_addr_t paddr,
291*4882a593Smuzhiyun 			    struct catpt_fw_block_hdr *blk, bool alloc)
292*4882a593Smuzhiyun {
293*4882a593Smuzhiyun 	struct resource *sram, *res;
294*4882a593Smuzhiyun 	dma_addr_t dst_addr;
295*4882a593Smuzhiyun 	int ret;
296*4882a593Smuzhiyun 
297*4882a593Smuzhiyun 	print_hex_dump_debug(__func__, DUMP_PREFIX_OFFSET, 8, 4,
298*4882a593Smuzhiyun 			     blk, sizeof(*blk), false);
299*4882a593Smuzhiyun 
300*4882a593Smuzhiyun 	switch (blk->ram_type) {
301*4882a593Smuzhiyun 	case CATPT_RAM_TYPE_IRAM:
302*4882a593Smuzhiyun 		sram = &cdev->iram;
303*4882a593Smuzhiyun 		break;
304*4882a593Smuzhiyun 	default:
305*4882a593Smuzhiyun 		sram = &cdev->dram;
306*4882a593Smuzhiyun 		break;
307*4882a593Smuzhiyun 	};
308*4882a593Smuzhiyun 
309*4882a593Smuzhiyun 	dst_addr = sram->start + blk->ram_offset;
310*4882a593Smuzhiyun 	if (alloc) {
311*4882a593Smuzhiyun 		res = __request_region(sram, dst_addr, blk->size, NULL, 0);
312*4882a593Smuzhiyun 		if (!res)
313*4882a593Smuzhiyun 			return -EBUSY;
314*4882a593Smuzhiyun 	}
315*4882a593Smuzhiyun 
316*4882a593Smuzhiyun 	/* advance to data area */
317*4882a593Smuzhiyun 	paddr += sizeof(*blk);
318*4882a593Smuzhiyun 
319*4882a593Smuzhiyun 	ret = catpt_dma_memcpy_todsp(cdev, chan, dst_addr, paddr, blk->size);
320*4882a593Smuzhiyun 	if (ret) {
321*4882a593Smuzhiyun 		dev_err(cdev->dev, "memcpy error: %d\n", ret);
322*4882a593Smuzhiyun 		__release_region(sram, dst_addr, blk->size);
323*4882a593Smuzhiyun 	}
324*4882a593Smuzhiyun 
325*4882a593Smuzhiyun 	return ret;
326*4882a593Smuzhiyun }
327*4882a593Smuzhiyun 
catpt_restore_basefw(struct catpt_dev * cdev,struct dma_chan * chan,dma_addr_t paddr,struct catpt_fw_mod_hdr * basefw)328*4882a593Smuzhiyun static int catpt_restore_basefw(struct catpt_dev *cdev,
329*4882a593Smuzhiyun 				struct dma_chan *chan, dma_addr_t paddr,
330*4882a593Smuzhiyun 				struct catpt_fw_mod_hdr *basefw)
331*4882a593Smuzhiyun {
332*4882a593Smuzhiyun 	u32 offset = sizeof(*basefw);
333*4882a593Smuzhiyun 	int ret, i;
334*4882a593Smuzhiyun 
335*4882a593Smuzhiyun 	print_hex_dump_debug(__func__, DUMP_PREFIX_OFFSET, 8, 4,
336*4882a593Smuzhiyun 			     basefw, sizeof(*basefw), false);
337*4882a593Smuzhiyun 
338*4882a593Smuzhiyun 	/* restore basefw image */
339*4882a593Smuzhiyun 	for (i = 0; i < basefw->blocks; i++) {
340*4882a593Smuzhiyun 		struct catpt_fw_block_hdr *blk;
341*4882a593Smuzhiyun 
342*4882a593Smuzhiyun 		blk = (struct catpt_fw_block_hdr *)((u8 *)basefw + offset);
343*4882a593Smuzhiyun 
344*4882a593Smuzhiyun 		switch (blk->ram_type) {
345*4882a593Smuzhiyun 		case CATPT_RAM_TYPE_IRAM:
346*4882a593Smuzhiyun 			ret = catpt_load_block(cdev, chan, paddr + offset,
347*4882a593Smuzhiyun 					       blk, false);
348*4882a593Smuzhiyun 			break;
349*4882a593Smuzhiyun 		default:
350*4882a593Smuzhiyun 			ret = catpt_restore_fwimage(cdev, chan, paddr + offset,
351*4882a593Smuzhiyun 						    blk);
352*4882a593Smuzhiyun 			break;
353*4882a593Smuzhiyun 		}
354*4882a593Smuzhiyun 
355*4882a593Smuzhiyun 		if (ret) {
356*4882a593Smuzhiyun 			dev_err(cdev->dev, "restore block failed: %d\n", ret);
357*4882a593Smuzhiyun 			return ret;
358*4882a593Smuzhiyun 		}
359*4882a593Smuzhiyun 
360*4882a593Smuzhiyun 		offset += sizeof(*blk) + blk->size;
361*4882a593Smuzhiyun 	}
362*4882a593Smuzhiyun 
363*4882a593Smuzhiyun 	/* then proceed with memory dumps */
364*4882a593Smuzhiyun 	ret = catpt_restore_memdumps(cdev, chan);
365*4882a593Smuzhiyun 	if (ret)
366*4882a593Smuzhiyun 		dev_err(cdev->dev, "restore memdumps failed: %d\n", ret);
367*4882a593Smuzhiyun 
368*4882a593Smuzhiyun 	return ret;
369*4882a593Smuzhiyun }
370*4882a593Smuzhiyun 
catpt_restore_module(struct catpt_dev * cdev,struct dma_chan * chan,dma_addr_t paddr,struct catpt_fw_mod_hdr * mod)371*4882a593Smuzhiyun static int catpt_restore_module(struct catpt_dev *cdev,
372*4882a593Smuzhiyun 				struct dma_chan *chan, dma_addr_t paddr,
373*4882a593Smuzhiyun 				struct catpt_fw_mod_hdr *mod)
374*4882a593Smuzhiyun {
375*4882a593Smuzhiyun 	u32 offset = sizeof(*mod);
376*4882a593Smuzhiyun 	int i;
377*4882a593Smuzhiyun 
378*4882a593Smuzhiyun 	print_hex_dump_debug(__func__, DUMP_PREFIX_OFFSET, 8, 4,
379*4882a593Smuzhiyun 			     mod, sizeof(*mod), false);
380*4882a593Smuzhiyun 
381*4882a593Smuzhiyun 	for (i = 0; i < mod->blocks; i++) {
382*4882a593Smuzhiyun 		struct catpt_fw_block_hdr *blk;
383*4882a593Smuzhiyun 		int ret;
384*4882a593Smuzhiyun 
385*4882a593Smuzhiyun 		blk = (struct catpt_fw_block_hdr *)((u8 *)mod + offset);
386*4882a593Smuzhiyun 
387*4882a593Smuzhiyun 		switch (blk->ram_type) {
388*4882a593Smuzhiyun 		case CATPT_RAM_TYPE_INSTANCE:
389*4882a593Smuzhiyun 			/* restore module state */
390*4882a593Smuzhiyun 			ret = catpt_dma_memcpy_todsp(cdev, chan,
391*4882a593Smuzhiyun 					cdev->lpe_base + blk->ram_offset,
392*4882a593Smuzhiyun 					cdev->dxbuf_paddr + blk->ram_offset,
393*4882a593Smuzhiyun 					ALIGN(blk->size, 4));
394*4882a593Smuzhiyun 			break;
395*4882a593Smuzhiyun 		default:
396*4882a593Smuzhiyun 			ret = catpt_load_block(cdev, chan, paddr + offset,
397*4882a593Smuzhiyun 					       blk, false);
398*4882a593Smuzhiyun 			break;
399*4882a593Smuzhiyun 		}
400*4882a593Smuzhiyun 
401*4882a593Smuzhiyun 		if (ret) {
402*4882a593Smuzhiyun 			dev_err(cdev->dev, "restore block failed: %d\n", ret);
403*4882a593Smuzhiyun 			return ret;
404*4882a593Smuzhiyun 		}
405*4882a593Smuzhiyun 
406*4882a593Smuzhiyun 		offset += sizeof(*blk) + blk->size;
407*4882a593Smuzhiyun 	}
408*4882a593Smuzhiyun 
409*4882a593Smuzhiyun 	return 0;
410*4882a593Smuzhiyun }
411*4882a593Smuzhiyun 
catpt_load_module(struct catpt_dev * cdev,struct dma_chan * chan,dma_addr_t paddr,struct catpt_fw_mod_hdr * mod)412*4882a593Smuzhiyun static int catpt_load_module(struct catpt_dev *cdev,
413*4882a593Smuzhiyun 			     struct dma_chan *chan, dma_addr_t paddr,
414*4882a593Smuzhiyun 			     struct catpt_fw_mod_hdr *mod)
415*4882a593Smuzhiyun {
416*4882a593Smuzhiyun 	struct catpt_module_type *type;
417*4882a593Smuzhiyun 	u32 offset = sizeof(*mod);
418*4882a593Smuzhiyun 	int i;
419*4882a593Smuzhiyun 
420*4882a593Smuzhiyun 	print_hex_dump_debug(__func__, DUMP_PREFIX_OFFSET, 8, 4,
421*4882a593Smuzhiyun 			     mod, sizeof(*mod), false);
422*4882a593Smuzhiyun 
423*4882a593Smuzhiyun 	type = &cdev->modules[mod->module_id];
424*4882a593Smuzhiyun 
425*4882a593Smuzhiyun 	for (i = 0; i < mod->blocks; i++) {
426*4882a593Smuzhiyun 		struct catpt_fw_block_hdr *blk;
427*4882a593Smuzhiyun 		int ret;
428*4882a593Smuzhiyun 
429*4882a593Smuzhiyun 		blk = (struct catpt_fw_block_hdr *)((u8 *)mod + offset);
430*4882a593Smuzhiyun 
431*4882a593Smuzhiyun 		ret = catpt_load_block(cdev, chan, paddr + offset, blk, true);
432*4882a593Smuzhiyun 		if (ret) {
433*4882a593Smuzhiyun 			dev_err(cdev->dev, "load block failed: %d\n", ret);
434*4882a593Smuzhiyun 			return ret;
435*4882a593Smuzhiyun 		}
436*4882a593Smuzhiyun 
437*4882a593Smuzhiyun 		/*
438*4882a593Smuzhiyun 		 * Save state window coordinates - these will be
439*4882a593Smuzhiyun 		 * used to capture module state on D0 exit.
440*4882a593Smuzhiyun 		 */
441*4882a593Smuzhiyun 		if (blk->ram_type == CATPT_RAM_TYPE_INSTANCE) {
442*4882a593Smuzhiyun 			type->state_offset = blk->ram_offset;
443*4882a593Smuzhiyun 			type->state_size = blk->size;
444*4882a593Smuzhiyun 		}
445*4882a593Smuzhiyun 
446*4882a593Smuzhiyun 		offset += sizeof(*blk) + blk->size;
447*4882a593Smuzhiyun 	}
448*4882a593Smuzhiyun 
449*4882a593Smuzhiyun 	/* init module type static info */
450*4882a593Smuzhiyun 	type->loaded = true;
451*4882a593Smuzhiyun 	/* DSP expects address from module header substracted by 4 */
452*4882a593Smuzhiyun 	type->entry_point = mod->entry_point - 4;
453*4882a593Smuzhiyun 	type->persistent_size = mod->persistent_size;
454*4882a593Smuzhiyun 	type->scratch_size = mod->scratch_size;
455*4882a593Smuzhiyun 
456*4882a593Smuzhiyun 	return 0;
457*4882a593Smuzhiyun }
458*4882a593Smuzhiyun 
catpt_restore_firmware(struct catpt_dev * cdev,struct dma_chan * chan,dma_addr_t paddr,struct catpt_fw_hdr * fw)459*4882a593Smuzhiyun static int catpt_restore_firmware(struct catpt_dev *cdev,
460*4882a593Smuzhiyun 				  struct dma_chan *chan, dma_addr_t paddr,
461*4882a593Smuzhiyun 				  struct catpt_fw_hdr *fw)
462*4882a593Smuzhiyun {
463*4882a593Smuzhiyun 	u32 offset = sizeof(*fw);
464*4882a593Smuzhiyun 	int i;
465*4882a593Smuzhiyun 
466*4882a593Smuzhiyun 	print_hex_dump_debug(__func__, DUMP_PREFIX_OFFSET, 8, 4,
467*4882a593Smuzhiyun 			     fw, sizeof(*fw), false);
468*4882a593Smuzhiyun 
469*4882a593Smuzhiyun 	for (i = 0; i < fw->modules; i++) {
470*4882a593Smuzhiyun 		struct catpt_fw_mod_hdr *mod;
471*4882a593Smuzhiyun 		int ret;
472*4882a593Smuzhiyun 
473*4882a593Smuzhiyun 		mod = (struct catpt_fw_mod_hdr *)((u8 *)fw + offset);
474*4882a593Smuzhiyun 		if (strncmp(fw->signature, mod->signature,
475*4882a593Smuzhiyun 			    FW_SIGNATURE_SIZE)) {
476*4882a593Smuzhiyun 			dev_err(cdev->dev, "module signature mismatch\n");
477*4882a593Smuzhiyun 			return -EINVAL;
478*4882a593Smuzhiyun 		}
479*4882a593Smuzhiyun 
480*4882a593Smuzhiyun 		if (mod->module_id > CATPT_MODID_LAST)
481*4882a593Smuzhiyun 			return -EINVAL;
482*4882a593Smuzhiyun 
483*4882a593Smuzhiyun 		switch (mod->module_id) {
484*4882a593Smuzhiyun 		case CATPT_MODID_BASE_FW:
485*4882a593Smuzhiyun 			ret = catpt_restore_basefw(cdev, chan, paddr + offset,
486*4882a593Smuzhiyun 						   mod);
487*4882a593Smuzhiyun 			break;
488*4882a593Smuzhiyun 		default:
489*4882a593Smuzhiyun 			ret = catpt_restore_module(cdev, chan, paddr + offset,
490*4882a593Smuzhiyun 						   mod);
491*4882a593Smuzhiyun 			break;
492*4882a593Smuzhiyun 		}
493*4882a593Smuzhiyun 
494*4882a593Smuzhiyun 		if (ret) {
495*4882a593Smuzhiyun 			dev_err(cdev->dev, "restore module failed: %d\n", ret);
496*4882a593Smuzhiyun 			return ret;
497*4882a593Smuzhiyun 		}
498*4882a593Smuzhiyun 
499*4882a593Smuzhiyun 		offset += sizeof(*mod) + mod->mod_size;
500*4882a593Smuzhiyun 	}
501*4882a593Smuzhiyun 
502*4882a593Smuzhiyun 	return 0;
503*4882a593Smuzhiyun }
504*4882a593Smuzhiyun 
catpt_load_firmware(struct catpt_dev * cdev,struct dma_chan * chan,dma_addr_t paddr,struct catpt_fw_hdr * fw)505*4882a593Smuzhiyun static int catpt_load_firmware(struct catpt_dev *cdev,
506*4882a593Smuzhiyun 			       struct dma_chan *chan, dma_addr_t paddr,
507*4882a593Smuzhiyun 			       struct catpt_fw_hdr *fw)
508*4882a593Smuzhiyun {
509*4882a593Smuzhiyun 	u32 offset = sizeof(*fw);
510*4882a593Smuzhiyun 	int i;
511*4882a593Smuzhiyun 
512*4882a593Smuzhiyun 	print_hex_dump_debug(__func__, DUMP_PREFIX_OFFSET, 8, 4,
513*4882a593Smuzhiyun 			     fw, sizeof(*fw), false);
514*4882a593Smuzhiyun 
515*4882a593Smuzhiyun 	for (i = 0; i < fw->modules; i++) {
516*4882a593Smuzhiyun 		struct catpt_fw_mod_hdr *mod;
517*4882a593Smuzhiyun 		int ret;
518*4882a593Smuzhiyun 
519*4882a593Smuzhiyun 		mod = (struct catpt_fw_mod_hdr *)((u8 *)fw + offset);
520*4882a593Smuzhiyun 		if (strncmp(fw->signature, mod->signature,
521*4882a593Smuzhiyun 			    FW_SIGNATURE_SIZE)) {
522*4882a593Smuzhiyun 			dev_err(cdev->dev, "module signature mismatch\n");
523*4882a593Smuzhiyun 			return -EINVAL;
524*4882a593Smuzhiyun 		}
525*4882a593Smuzhiyun 
526*4882a593Smuzhiyun 		if (mod->module_id > CATPT_MODID_LAST)
527*4882a593Smuzhiyun 			return -EINVAL;
528*4882a593Smuzhiyun 
529*4882a593Smuzhiyun 		ret = catpt_load_module(cdev, chan, paddr + offset, mod);
530*4882a593Smuzhiyun 		if (ret) {
531*4882a593Smuzhiyun 			dev_err(cdev->dev, "load module failed: %d\n", ret);
532*4882a593Smuzhiyun 			return ret;
533*4882a593Smuzhiyun 		}
534*4882a593Smuzhiyun 
535*4882a593Smuzhiyun 		offset += sizeof(*mod) + mod->mod_size;
536*4882a593Smuzhiyun 	}
537*4882a593Smuzhiyun 
538*4882a593Smuzhiyun 	return 0;
539*4882a593Smuzhiyun }
540*4882a593Smuzhiyun 
catpt_load_image(struct catpt_dev * cdev,struct dma_chan * chan,const char * name,const char * signature,bool restore)541*4882a593Smuzhiyun static int catpt_load_image(struct catpt_dev *cdev, struct dma_chan *chan,
542*4882a593Smuzhiyun 			    const char *name, const char *signature,
543*4882a593Smuzhiyun 			    bool restore)
544*4882a593Smuzhiyun {
545*4882a593Smuzhiyun 	struct catpt_fw_hdr *fw;
546*4882a593Smuzhiyun 	struct firmware *img;
547*4882a593Smuzhiyun 	dma_addr_t paddr;
548*4882a593Smuzhiyun 	void *vaddr;
549*4882a593Smuzhiyun 	int ret;
550*4882a593Smuzhiyun 
551*4882a593Smuzhiyun 	ret = request_firmware((const struct firmware **)&img, name, cdev->dev);
552*4882a593Smuzhiyun 	if (ret)
553*4882a593Smuzhiyun 		return ret;
554*4882a593Smuzhiyun 
555*4882a593Smuzhiyun 	fw = (struct catpt_fw_hdr *)img->data;
556*4882a593Smuzhiyun 	if (strncmp(fw->signature, signature, FW_SIGNATURE_SIZE)) {
557*4882a593Smuzhiyun 		dev_err(cdev->dev, "firmware signature mismatch\n");
558*4882a593Smuzhiyun 		ret = -EINVAL;
559*4882a593Smuzhiyun 		goto release_fw;
560*4882a593Smuzhiyun 	}
561*4882a593Smuzhiyun 
562*4882a593Smuzhiyun 	vaddr = dma_alloc_coherent(cdev->dev, img->size, &paddr, GFP_KERNEL);
563*4882a593Smuzhiyun 	if (!vaddr) {
564*4882a593Smuzhiyun 		ret = -ENOMEM;
565*4882a593Smuzhiyun 		goto release_fw;
566*4882a593Smuzhiyun 	}
567*4882a593Smuzhiyun 
568*4882a593Smuzhiyun 	memcpy(vaddr, img->data, img->size);
569*4882a593Smuzhiyun 	fw = (struct catpt_fw_hdr *)vaddr;
570*4882a593Smuzhiyun 	if (restore)
571*4882a593Smuzhiyun 		ret = catpt_restore_firmware(cdev, chan, paddr, fw);
572*4882a593Smuzhiyun 	else
573*4882a593Smuzhiyun 		ret = catpt_load_firmware(cdev, chan, paddr, fw);
574*4882a593Smuzhiyun 
575*4882a593Smuzhiyun 	dma_free_coherent(cdev->dev, img->size, vaddr, paddr);
576*4882a593Smuzhiyun release_fw:
577*4882a593Smuzhiyun 	release_firmware(img);
578*4882a593Smuzhiyun 	return ret;
579*4882a593Smuzhiyun }
580*4882a593Smuzhiyun 
catpt_load_images(struct catpt_dev * cdev,bool restore)581*4882a593Smuzhiyun static int catpt_load_images(struct catpt_dev *cdev, bool restore)
582*4882a593Smuzhiyun {
583*4882a593Smuzhiyun 	static const char *const names[] = {
584*4882a593Smuzhiyun 		"intel/IntcSST1.bin",
585*4882a593Smuzhiyun 		"intel/IntcSST2.bin",
586*4882a593Smuzhiyun 	};
587*4882a593Smuzhiyun 	struct dma_chan *chan;
588*4882a593Smuzhiyun 	int ret;
589*4882a593Smuzhiyun 
590*4882a593Smuzhiyun 	chan = catpt_dma_request_config_chan(cdev);
591*4882a593Smuzhiyun 	if (IS_ERR(chan))
592*4882a593Smuzhiyun 		return PTR_ERR(chan);
593*4882a593Smuzhiyun 
594*4882a593Smuzhiyun 	ret = catpt_load_image(cdev, chan, names[cdev->spec->core_id - 1],
595*4882a593Smuzhiyun 			       FW_SIGNATURE, restore);
596*4882a593Smuzhiyun 	if (ret)
597*4882a593Smuzhiyun 		goto release_dma_chan;
598*4882a593Smuzhiyun 
599*4882a593Smuzhiyun 	if (!restore)
600*4882a593Smuzhiyun 		goto release_dma_chan;
601*4882a593Smuzhiyun 	ret = catpt_restore_streams_context(cdev, chan);
602*4882a593Smuzhiyun 	if (ret)
603*4882a593Smuzhiyun 		dev_err(cdev->dev, "restore streams ctx failed: %d\n", ret);
604*4882a593Smuzhiyun release_dma_chan:
605*4882a593Smuzhiyun 	dma_release_channel(chan);
606*4882a593Smuzhiyun 	return ret;
607*4882a593Smuzhiyun }
608*4882a593Smuzhiyun 
catpt_boot_firmware(struct catpt_dev * cdev,bool restore)609*4882a593Smuzhiyun int catpt_boot_firmware(struct catpt_dev *cdev, bool restore)
610*4882a593Smuzhiyun {
611*4882a593Smuzhiyun 	int ret;
612*4882a593Smuzhiyun 
613*4882a593Smuzhiyun 	catpt_dsp_stall(cdev, true);
614*4882a593Smuzhiyun 
615*4882a593Smuzhiyun 	ret = catpt_load_images(cdev, restore);
616*4882a593Smuzhiyun 	if (ret) {
617*4882a593Smuzhiyun 		dev_err(cdev->dev, "load binaries failed: %d\n", ret);
618*4882a593Smuzhiyun 		return ret;
619*4882a593Smuzhiyun 	}
620*4882a593Smuzhiyun 
621*4882a593Smuzhiyun 	reinit_completion(&cdev->fw_ready);
622*4882a593Smuzhiyun 	catpt_dsp_stall(cdev, false);
623*4882a593Smuzhiyun 
624*4882a593Smuzhiyun 	ret = wait_for_completion_timeout(&cdev->fw_ready,
625*4882a593Smuzhiyun 			msecs_to_jiffies(FW_READY_TIMEOUT_MS));
626*4882a593Smuzhiyun 	if (!ret) {
627*4882a593Smuzhiyun 		dev_err(cdev->dev, "firmware ready timeout\n");
628*4882a593Smuzhiyun 		return -ETIMEDOUT;
629*4882a593Smuzhiyun 	}
630*4882a593Smuzhiyun 
631*4882a593Smuzhiyun 	/* update sram pg & clock once done booting */
632*4882a593Smuzhiyun 	catpt_dsp_update_srampge(cdev, &cdev->dram, cdev->spec->dram_mask);
633*4882a593Smuzhiyun 	catpt_dsp_update_srampge(cdev, &cdev->iram, cdev->spec->iram_mask);
634*4882a593Smuzhiyun 
635*4882a593Smuzhiyun 	return catpt_dsp_update_lpclock(cdev);
636*4882a593Smuzhiyun }
637*4882a593Smuzhiyun 
catpt_first_boot_firmware(struct catpt_dev * cdev)638*4882a593Smuzhiyun int catpt_first_boot_firmware(struct catpt_dev *cdev)
639*4882a593Smuzhiyun {
640*4882a593Smuzhiyun 	struct resource *res;
641*4882a593Smuzhiyun 	int ret;
642*4882a593Smuzhiyun 
643*4882a593Smuzhiyun 	ret = catpt_boot_firmware(cdev, false);
644*4882a593Smuzhiyun 	if (ret) {
645*4882a593Smuzhiyun 		dev_err(cdev->dev, "basefw boot failed: %d\n", ret);
646*4882a593Smuzhiyun 		return ret;
647*4882a593Smuzhiyun 	}
648*4882a593Smuzhiyun 
649*4882a593Smuzhiyun 	/* restrict FW Core dump area */
650*4882a593Smuzhiyun 	__request_region(&cdev->dram, 0, 0x200, NULL, 0);
651*4882a593Smuzhiyun 	/* restrict entire area following BASE_FW - highest offset in DRAM */
652*4882a593Smuzhiyun 	for (res = cdev->dram.child; res->sibling; res = res->sibling)
653*4882a593Smuzhiyun 		;
654*4882a593Smuzhiyun 	__request_region(&cdev->dram, res->end + 1,
655*4882a593Smuzhiyun 			 cdev->dram.end - res->end, NULL, 0);
656*4882a593Smuzhiyun 
657*4882a593Smuzhiyun 	ret = catpt_ipc_get_mixer_stream_info(cdev, &cdev->mixer);
658*4882a593Smuzhiyun 	if (ret)
659*4882a593Smuzhiyun 		return CATPT_IPC_ERROR(ret);
660*4882a593Smuzhiyun 
661*4882a593Smuzhiyun 	ret = catpt_arm_stream_templates(cdev);
662*4882a593Smuzhiyun 	if (ret) {
663*4882a593Smuzhiyun 		dev_err(cdev->dev, "arm templates failed: %d\n", ret);
664*4882a593Smuzhiyun 		return ret;
665*4882a593Smuzhiyun 	}
666*4882a593Smuzhiyun 
667*4882a593Smuzhiyun 	/* update dram pg for scratch and restricted regions */
668*4882a593Smuzhiyun 	catpt_dsp_update_srampge(cdev, &cdev->dram, cdev->spec->dram_mask);
669*4882a593Smuzhiyun 
670*4882a593Smuzhiyun 	return 0;
671*4882a593Smuzhiyun }
672