1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Intel Skylake I2S Machine Driver with MAXIM98357A
4*4882a593Smuzhiyun * and NAU88L25
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Copyright (C) 2015, Intel Corporation. All rights reserved.
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <linux/module.h>
10*4882a593Smuzhiyun #include <linux/platform_device.h>
11*4882a593Smuzhiyun #include <sound/core.h>
12*4882a593Smuzhiyun #include <sound/jack.h>
13*4882a593Smuzhiyun #include <sound/pcm.h>
14*4882a593Smuzhiyun #include <sound/pcm_params.h>
15*4882a593Smuzhiyun #include <sound/soc.h>
16*4882a593Smuzhiyun #include <sound/soc-acpi.h>
17*4882a593Smuzhiyun #include "../../codecs/nau8825.h"
18*4882a593Smuzhiyun #include "../../codecs/hdac_hdmi.h"
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun #define SKL_NUVOTON_CODEC_DAI "nau8825-hifi"
21*4882a593Smuzhiyun #define SKL_MAXIM_CODEC_DAI "HiFi"
22*4882a593Smuzhiyun #define DMIC_CH(p) p->list[p->count-1]
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun static struct snd_soc_jack skylake_headset;
25*4882a593Smuzhiyun static struct snd_soc_card skylake_audio_card;
26*4882a593Smuzhiyun static const struct snd_pcm_hw_constraint_list *dmic_constraints;
27*4882a593Smuzhiyun static struct snd_soc_jack skylake_hdmi[3];
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun struct skl_hdmi_pcm {
30*4882a593Smuzhiyun struct list_head head;
31*4882a593Smuzhiyun struct snd_soc_dai *codec_dai;
32*4882a593Smuzhiyun int device;
33*4882a593Smuzhiyun };
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun struct skl_nau8825_private {
36*4882a593Smuzhiyun struct list_head hdmi_pcm_list;
37*4882a593Smuzhiyun };
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun enum {
40*4882a593Smuzhiyun SKL_DPCM_AUDIO_PB = 0,
41*4882a593Smuzhiyun SKL_DPCM_AUDIO_CP,
42*4882a593Smuzhiyun SKL_DPCM_AUDIO_REF_CP,
43*4882a593Smuzhiyun SKL_DPCM_AUDIO_DMIC_CP,
44*4882a593Smuzhiyun SKL_DPCM_AUDIO_HDMI1_PB,
45*4882a593Smuzhiyun SKL_DPCM_AUDIO_HDMI2_PB,
46*4882a593Smuzhiyun SKL_DPCM_AUDIO_HDMI3_PB,
47*4882a593Smuzhiyun };
48*4882a593Smuzhiyun
platform_clock_control(struct snd_soc_dapm_widget * w,struct snd_kcontrol * k,int event)49*4882a593Smuzhiyun static int platform_clock_control(struct snd_soc_dapm_widget *w,
50*4882a593Smuzhiyun struct snd_kcontrol *k, int event)
51*4882a593Smuzhiyun {
52*4882a593Smuzhiyun struct snd_soc_dapm_context *dapm = w->dapm;
53*4882a593Smuzhiyun struct snd_soc_card *card = dapm->card;
54*4882a593Smuzhiyun struct snd_soc_dai *codec_dai;
55*4882a593Smuzhiyun int ret;
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun codec_dai = snd_soc_card_get_codec_dai(card, SKL_NUVOTON_CODEC_DAI);
58*4882a593Smuzhiyun if (!codec_dai) {
59*4882a593Smuzhiyun dev_err(card->dev, "Codec dai not found; Unable to set platform clock\n");
60*4882a593Smuzhiyun return -EIO;
61*4882a593Smuzhiyun }
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun if (SND_SOC_DAPM_EVENT_ON(event)) {
64*4882a593Smuzhiyun ret = snd_soc_dai_set_sysclk(codec_dai,
65*4882a593Smuzhiyun NAU8825_CLK_MCLK, 24000000, SND_SOC_CLOCK_IN);
66*4882a593Smuzhiyun if (ret < 0) {
67*4882a593Smuzhiyun dev_err(card->dev, "set sysclk err = %d\n", ret);
68*4882a593Smuzhiyun return -EIO;
69*4882a593Smuzhiyun }
70*4882a593Smuzhiyun } else {
71*4882a593Smuzhiyun ret = snd_soc_dai_set_sysclk(codec_dai,
72*4882a593Smuzhiyun NAU8825_CLK_INTERNAL, 0, SND_SOC_CLOCK_IN);
73*4882a593Smuzhiyun if (ret < 0) {
74*4882a593Smuzhiyun dev_err(card->dev, "set sysclk err = %d\n", ret);
75*4882a593Smuzhiyun return -EIO;
76*4882a593Smuzhiyun }
77*4882a593Smuzhiyun }
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun return ret;
80*4882a593Smuzhiyun }
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun static const struct snd_kcontrol_new skylake_controls[] = {
83*4882a593Smuzhiyun SOC_DAPM_PIN_SWITCH("Headphone Jack"),
84*4882a593Smuzhiyun SOC_DAPM_PIN_SWITCH("Headset Mic"),
85*4882a593Smuzhiyun SOC_DAPM_PIN_SWITCH("Spk"),
86*4882a593Smuzhiyun };
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun static const struct snd_soc_dapm_widget skylake_widgets[] = {
89*4882a593Smuzhiyun SND_SOC_DAPM_HP("Headphone Jack", NULL),
90*4882a593Smuzhiyun SND_SOC_DAPM_MIC("Headset Mic", NULL),
91*4882a593Smuzhiyun SND_SOC_DAPM_SPK("Spk", NULL),
92*4882a593Smuzhiyun SND_SOC_DAPM_MIC("SoC DMIC", NULL),
93*4882a593Smuzhiyun SND_SOC_DAPM_SPK("DP1", NULL),
94*4882a593Smuzhiyun SND_SOC_DAPM_SPK("DP2", NULL),
95*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("Platform Clock", SND_SOC_NOPM, 0, 0,
96*4882a593Smuzhiyun platform_clock_control, SND_SOC_DAPM_PRE_PMU |
97*4882a593Smuzhiyun SND_SOC_DAPM_POST_PMD),
98*4882a593Smuzhiyun };
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun static const struct snd_soc_dapm_route skylake_map[] = {
101*4882a593Smuzhiyun /* HP jack connectors - unknown if we have jack detection */
102*4882a593Smuzhiyun { "Headphone Jack", NULL, "HPOL" },
103*4882a593Smuzhiyun { "Headphone Jack", NULL, "HPOR" },
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun /* speaker */
106*4882a593Smuzhiyun { "Spk", NULL, "Speaker" },
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun /* other jacks */
109*4882a593Smuzhiyun { "MIC", NULL, "Headset Mic" },
110*4882a593Smuzhiyun { "DMic", NULL, "SoC DMIC" },
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun /* CODEC BE connections */
113*4882a593Smuzhiyun { "HiFi Playback", NULL, "ssp0 Tx" },
114*4882a593Smuzhiyun { "ssp0 Tx", NULL, "codec0_out" },
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun { "Playback", NULL, "ssp1 Tx" },
117*4882a593Smuzhiyun { "ssp1 Tx", NULL, "codec1_out" },
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun { "codec0_in", NULL, "ssp1 Rx" },
120*4882a593Smuzhiyun { "ssp1 Rx", NULL, "Capture" },
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun /* DMIC */
123*4882a593Smuzhiyun { "dmic01_hifi", NULL, "DMIC01 Rx" },
124*4882a593Smuzhiyun { "DMIC01 Rx", NULL, "DMIC AIF" },
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun { "hifi3", NULL, "iDisp3 Tx"},
127*4882a593Smuzhiyun { "iDisp3 Tx", NULL, "iDisp3_out"},
128*4882a593Smuzhiyun { "hifi2", NULL, "iDisp2 Tx"},
129*4882a593Smuzhiyun { "iDisp2 Tx", NULL, "iDisp2_out"},
130*4882a593Smuzhiyun { "hifi1", NULL, "iDisp1 Tx"},
131*4882a593Smuzhiyun { "iDisp1 Tx", NULL, "iDisp1_out"},
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun { "Headphone Jack", NULL, "Platform Clock" },
134*4882a593Smuzhiyun { "Headset Mic", NULL, "Platform Clock" },
135*4882a593Smuzhiyun };
136*4882a593Smuzhiyun
skylake_ssp_fixup(struct snd_soc_pcm_runtime * rtd,struct snd_pcm_hw_params * params)137*4882a593Smuzhiyun static int skylake_ssp_fixup(struct snd_soc_pcm_runtime *rtd,
138*4882a593Smuzhiyun struct snd_pcm_hw_params *params)
139*4882a593Smuzhiyun {
140*4882a593Smuzhiyun struct snd_interval *rate = hw_param_interval(params,
141*4882a593Smuzhiyun SNDRV_PCM_HW_PARAM_RATE);
142*4882a593Smuzhiyun struct snd_interval *chan = hw_param_interval(params,
143*4882a593Smuzhiyun SNDRV_PCM_HW_PARAM_CHANNELS);
144*4882a593Smuzhiyun struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun /* The ADSP will covert the FE rate to 48k, stereo */
147*4882a593Smuzhiyun rate->min = rate->max = 48000;
148*4882a593Smuzhiyun chan->min = chan->max = 2;
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun /* set SSP0 to 24 bit */
151*4882a593Smuzhiyun snd_mask_none(fmt);
152*4882a593Smuzhiyun snd_mask_set_format(fmt, SNDRV_PCM_FORMAT_S24_LE);
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun return 0;
155*4882a593Smuzhiyun }
156*4882a593Smuzhiyun
skylake_nau8825_codec_init(struct snd_soc_pcm_runtime * rtd)157*4882a593Smuzhiyun static int skylake_nau8825_codec_init(struct snd_soc_pcm_runtime *rtd)
158*4882a593Smuzhiyun {
159*4882a593Smuzhiyun int ret;
160*4882a593Smuzhiyun struct snd_soc_component *component = asoc_rtd_to_codec(rtd, 0)->component;
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun /*
163*4882a593Smuzhiyun * Headset buttons map to the google Reference headset.
164*4882a593Smuzhiyun * These can be configured by userspace.
165*4882a593Smuzhiyun */
166*4882a593Smuzhiyun ret = snd_soc_card_jack_new(&skylake_audio_card, "Headset Jack",
167*4882a593Smuzhiyun SND_JACK_HEADSET | SND_JACK_BTN_0 | SND_JACK_BTN_1 |
168*4882a593Smuzhiyun SND_JACK_BTN_2 | SND_JACK_BTN_3, &skylake_headset,
169*4882a593Smuzhiyun NULL, 0);
170*4882a593Smuzhiyun if (ret) {
171*4882a593Smuzhiyun dev_err(rtd->dev, "Headset Jack creation failed %d\n", ret);
172*4882a593Smuzhiyun return ret;
173*4882a593Smuzhiyun }
174*4882a593Smuzhiyun
175*4882a593Smuzhiyun nau8825_enable_jack_detect(component, &skylake_headset);
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun snd_soc_dapm_ignore_suspend(&rtd->card->dapm, "SoC DMIC");
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun return ret;
180*4882a593Smuzhiyun }
181*4882a593Smuzhiyun
skylake_hdmi1_init(struct snd_soc_pcm_runtime * rtd)182*4882a593Smuzhiyun static int skylake_hdmi1_init(struct snd_soc_pcm_runtime *rtd)
183*4882a593Smuzhiyun {
184*4882a593Smuzhiyun struct skl_nau8825_private *ctx = snd_soc_card_get_drvdata(rtd->card);
185*4882a593Smuzhiyun struct snd_soc_dai *dai = asoc_rtd_to_codec(rtd, 0);
186*4882a593Smuzhiyun struct skl_hdmi_pcm *pcm;
187*4882a593Smuzhiyun
188*4882a593Smuzhiyun pcm = devm_kzalloc(rtd->card->dev, sizeof(*pcm), GFP_KERNEL);
189*4882a593Smuzhiyun if (!pcm)
190*4882a593Smuzhiyun return -ENOMEM;
191*4882a593Smuzhiyun
192*4882a593Smuzhiyun pcm->device = SKL_DPCM_AUDIO_HDMI1_PB;
193*4882a593Smuzhiyun pcm->codec_dai = dai;
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun list_add_tail(&pcm->head, &ctx->hdmi_pcm_list);
196*4882a593Smuzhiyun
197*4882a593Smuzhiyun return 0;
198*4882a593Smuzhiyun }
199*4882a593Smuzhiyun
skylake_hdmi2_init(struct snd_soc_pcm_runtime * rtd)200*4882a593Smuzhiyun static int skylake_hdmi2_init(struct snd_soc_pcm_runtime *rtd)
201*4882a593Smuzhiyun {
202*4882a593Smuzhiyun struct skl_nau8825_private *ctx = snd_soc_card_get_drvdata(rtd->card);
203*4882a593Smuzhiyun struct snd_soc_dai *dai = asoc_rtd_to_codec(rtd, 0);
204*4882a593Smuzhiyun struct skl_hdmi_pcm *pcm;
205*4882a593Smuzhiyun
206*4882a593Smuzhiyun pcm = devm_kzalloc(rtd->card->dev, sizeof(*pcm), GFP_KERNEL);
207*4882a593Smuzhiyun if (!pcm)
208*4882a593Smuzhiyun return -ENOMEM;
209*4882a593Smuzhiyun
210*4882a593Smuzhiyun pcm->device = SKL_DPCM_AUDIO_HDMI2_PB;
211*4882a593Smuzhiyun pcm->codec_dai = dai;
212*4882a593Smuzhiyun
213*4882a593Smuzhiyun list_add_tail(&pcm->head, &ctx->hdmi_pcm_list);
214*4882a593Smuzhiyun
215*4882a593Smuzhiyun return 0;
216*4882a593Smuzhiyun }
217*4882a593Smuzhiyun
skylake_hdmi3_init(struct snd_soc_pcm_runtime * rtd)218*4882a593Smuzhiyun static int skylake_hdmi3_init(struct snd_soc_pcm_runtime *rtd)
219*4882a593Smuzhiyun {
220*4882a593Smuzhiyun struct skl_nau8825_private *ctx = snd_soc_card_get_drvdata(rtd->card);
221*4882a593Smuzhiyun struct snd_soc_dai *dai = asoc_rtd_to_codec(rtd, 0);
222*4882a593Smuzhiyun struct skl_hdmi_pcm *pcm;
223*4882a593Smuzhiyun
224*4882a593Smuzhiyun pcm = devm_kzalloc(rtd->card->dev, sizeof(*pcm), GFP_KERNEL);
225*4882a593Smuzhiyun if (!pcm)
226*4882a593Smuzhiyun return -ENOMEM;
227*4882a593Smuzhiyun
228*4882a593Smuzhiyun pcm->device = SKL_DPCM_AUDIO_HDMI3_PB;
229*4882a593Smuzhiyun pcm->codec_dai = dai;
230*4882a593Smuzhiyun
231*4882a593Smuzhiyun list_add_tail(&pcm->head, &ctx->hdmi_pcm_list);
232*4882a593Smuzhiyun
233*4882a593Smuzhiyun return 0;
234*4882a593Smuzhiyun }
235*4882a593Smuzhiyun
skylake_nau8825_fe_init(struct snd_soc_pcm_runtime * rtd)236*4882a593Smuzhiyun static int skylake_nau8825_fe_init(struct snd_soc_pcm_runtime *rtd)
237*4882a593Smuzhiyun {
238*4882a593Smuzhiyun struct snd_soc_dapm_context *dapm;
239*4882a593Smuzhiyun struct snd_soc_component *component = asoc_rtd_to_cpu(rtd, 0)->component;
240*4882a593Smuzhiyun
241*4882a593Smuzhiyun dapm = snd_soc_component_get_dapm(component);
242*4882a593Smuzhiyun snd_soc_dapm_ignore_suspend(dapm, "Reference Capture");
243*4882a593Smuzhiyun
244*4882a593Smuzhiyun return 0;
245*4882a593Smuzhiyun }
246*4882a593Smuzhiyun
247*4882a593Smuzhiyun static const unsigned int rates[] = {
248*4882a593Smuzhiyun 48000,
249*4882a593Smuzhiyun };
250*4882a593Smuzhiyun
251*4882a593Smuzhiyun static const struct snd_pcm_hw_constraint_list constraints_rates = {
252*4882a593Smuzhiyun .count = ARRAY_SIZE(rates),
253*4882a593Smuzhiyun .list = rates,
254*4882a593Smuzhiyun .mask = 0,
255*4882a593Smuzhiyun };
256*4882a593Smuzhiyun
257*4882a593Smuzhiyun static const unsigned int channels[] = {
258*4882a593Smuzhiyun 2,
259*4882a593Smuzhiyun };
260*4882a593Smuzhiyun
261*4882a593Smuzhiyun static const struct snd_pcm_hw_constraint_list constraints_channels = {
262*4882a593Smuzhiyun .count = ARRAY_SIZE(channels),
263*4882a593Smuzhiyun .list = channels,
264*4882a593Smuzhiyun .mask = 0,
265*4882a593Smuzhiyun };
266*4882a593Smuzhiyun
skl_fe_startup(struct snd_pcm_substream * substream)267*4882a593Smuzhiyun static int skl_fe_startup(struct snd_pcm_substream *substream)
268*4882a593Smuzhiyun {
269*4882a593Smuzhiyun struct snd_pcm_runtime *runtime = substream->runtime;
270*4882a593Smuzhiyun
271*4882a593Smuzhiyun /*
272*4882a593Smuzhiyun * On this platform for PCM device we support,
273*4882a593Smuzhiyun * 48Khz
274*4882a593Smuzhiyun * stereo
275*4882a593Smuzhiyun * 16 bit audio
276*4882a593Smuzhiyun */
277*4882a593Smuzhiyun
278*4882a593Smuzhiyun runtime->hw.channels_max = 2;
279*4882a593Smuzhiyun snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
280*4882a593Smuzhiyun &constraints_channels);
281*4882a593Smuzhiyun
282*4882a593Smuzhiyun runtime->hw.formats = SNDRV_PCM_FMTBIT_S16_LE;
283*4882a593Smuzhiyun snd_pcm_hw_constraint_msbits(runtime, 0, 16, 16);
284*4882a593Smuzhiyun
285*4882a593Smuzhiyun snd_pcm_hw_constraint_list(runtime, 0,
286*4882a593Smuzhiyun SNDRV_PCM_HW_PARAM_RATE, &constraints_rates);
287*4882a593Smuzhiyun
288*4882a593Smuzhiyun return 0;
289*4882a593Smuzhiyun }
290*4882a593Smuzhiyun
291*4882a593Smuzhiyun static const struct snd_soc_ops skylake_nau8825_fe_ops = {
292*4882a593Smuzhiyun .startup = skl_fe_startup,
293*4882a593Smuzhiyun };
294*4882a593Smuzhiyun
skylake_nau8825_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params)295*4882a593Smuzhiyun static int skylake_nau8825_hw_params(struct snd_pcm_substream *substream,
296*4882a593Smuzhiyun struct snd_pcm_hw_params *params)
297*4882a593Smuzhiyun {
298*4882a593Smuzhiyun struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
299*4882a593Smuzhiyun struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
300*4882a593Smuzhiyun int ret;
301*4882a593Smuzhiyun
302*4882a593Smuzhiyun ret = snd_soc_dai_set_sysclk(codec_dai,
303*4882a593Smuzhiyun NAU8825_CLK_MCLK, 24000000, SND_SOC_CLOCK_IN);
304*4882a593Smuzhiyun
305*4882a593Smuzhiyun if (ret < 0)
306*4882a593Smuzhiyun dev_err(rtd->dev, "snd_soc_dai_set_sysclk err = %d\n", ret);
307*4882a593Smuzhiyun
308*4882a593Smuzhiyun return ret;
309*4882a593Smuzhiyun }
310*4882a593Smuzhiyun
311*4882a593Smuzhiyun static const struct snd_soc_ops skylake_nau8825_ops = {
312*4882a593Smuzhiyun .hw_params = skylake_nau8825_hw_params,
313*4882a593Smuzhiyun };
314*4882a593Smuzhiyun
skylake_dmic_fixup(struct snd_soc_pcm_runtime * rtd,struct snd_pcm_hw_params * params)315*4882a593Smuzhiyun static int skylake_dmic_fixup(struct snd_soc_pcm_runtime *rtd,
316*4882a593Smuzhiyun struct snd_pcm_hw_params *params)
317*4882a593Smuzhiyun {
318*4882a593Smuzhiyun struct snd_interval *chan = hw_param_interval(params,
319*4882a593Smuzhiyun SNDRV_PCM_HW_PARAM_CHANNELS);
320*4882a593Smuzhiyun
321*4882a593Smuzhiyun if (params_channels(params) == 2 || DMIC_CH(dmic_constraints) == 2)
322*4882a593Smuzhiyun chan->min = chan->max = 2;
323*4882a593Smuzhiyun else
324*4882a593Smuzhiyun chan->min = chan->max = 4;
325*4882a593Smuzhiyun
326*4882a593Smuzhiyun return 0;
327*4882a593Smuzhiyun }
328*4882a593Smuzhiyun
329*4882a593Smuzhiyun static const unsigned int channels_dmic[] = {
330*4882a593Smuzhiyun 2, 4,
331*4882a593Smuzhiyun };
332*4882a593Smuzhiyun
333*4882a593Smuzhiyun static const struct snd_pcm_hw_constraint_list constraints_dmic_channels = {
334*4882a593Smuzhiyun .count = ARRAY_SIZE(channels_dmic),
335*4882a593Smuzhiyun .list = channels_dmic,
336*4882a593Smuzhiyun .mask = 0,
337*4882a593Smuzhiyun };
338*4882a593Smuzhiyun
339*4882a593Smuzhiyun static const unsigned int dmic_2ch[] = {
340*4882a593Smuzhiyun 2,
341*4882a593Smuzhiyun };
342*4882a593Smuzhiyun
343*4882a593Smuzhiyun static const struct snd_pcm_hw_constraint_list constraints_dmic_2ch = {
344*4882a593Smuzhiyun .count = ARRAY_SIZE(dmic_2ch),
345*4882a593Smuzhiyun .list = dmic_2ch,
346*4882a593Smuzhiyun .mask = 0,
347*4882a593Smuzhiyun };
348*4882a593Smuzhiyun
skylake_dmic_startup(struct snd_pcm_substream * substream)349*4882a593Smuzhiyun static int skylake_dmic_startup(struct snd_pcm_substream *substream)
350*4882a593Smuzhiyun {
351*4882a593Smuzhiyun struct snd_pcm_runtime *runtime = substream->runtime;
352*4882a593Smuzhiyun
353*4882a593Smuzhiyun runtime->hw.channels_max = DMIC_CH(dmic_constraints);
354*4882a593Smuzhiyun snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
355*4882a593Smuzhiyun dmic_constraints);
356*4882a593Smuzhiyun
357*4882a593Smuzhiyun return snd_pcm_hw_constraint_list(substream->runtime, 0,
358*4882a593Smuzhiyun SNDRV_PCM_HW_PARAM_RATE, &constraints_rates);
359*4882a593Smuzhiyun }
360*4882a593Smuzhiyun
361*4882a593Smuzhiyun static const struct snd_soc_ops skylake_dmic_ops = {
362*4882a593Smuzhiyun .startup = skylake_dmic_startup,
363*4882a593Smuzhiyun };
364*4882a593Smuzhiyun
365*4882a593Smuzhiyun static const unsigned int rates_16000[] = {
366*4882a593Smuzhiyun 16000,
367*4882a593Smuzhiyun };
368*4882a593Smuzhiyun
369*4882a593Smuzhiyun static const struct snd_pcm_hw_constraint_list constraints_16000 = {
370*4882a593Smuzhiyun .count = ARRAY_SIZE(rates_16000),
371*4882a593Smuzhiyun .list = rates_16000,
372*4882a593Smuzhiyun };
373*4882a593Smuzhiyun
374*4882a593Smuzhiyun static const unsigned int ch_mono[] = {
375*4882a593Smuzhiyun 1,
376*4882a593Smuzhiyun };
377*4882a593Smuzhiyun
378*4882a593Smuzhiyun static const struct snd_pcm_hw_constraint_list constraints_refcap = {
379*4882a593Smuzhiyun .count = ARRAY_SIZE(ch_mono),
380*4882a593Smuzhiyun .list = ch_mono,
381*4882a593Smuzhiyun };
382*4882a593Smuzhiyun
skylake_refcap_startup(struct snd_pcm_substream * substream)383*4882a593Smuzhiyun static int skylake_refcap_startup(struct snd_pcm_substream *substream)
384*4882a593Smuzhiyun {
385*4882a593Smuzhiyun substream->runtime->hw.channels_max = 1;
386*4882a593Smuzhiyun snd_pcm_hw_constraint_list(substream->runtime, 0,
387*4882a593Smuzhiyun SNDRV_PCM_HW_PARAM_CHANNELS,
388*4882a593Smuzhiyun &constraints_refcap);
389*4882a593Smuzhiyun
390*4882a593Smuzhiyun return snd_pcm_hw_constraint_list(substream->runtime, 0,
391*4882a593Smuzhiyun SNDRV_PCM_HW_PARAM_RATE,
392*4882a593Smuzhiyun &constraints_16000);
393*4882a593Smuzhiyun }
394*4882a593Smuzhiyun
395*4882a593Smuzhiyun static const struct snd_soc_ops skylake_refcap_ops = {
396*4882a593Smuzhiyun .startup = skylake_refcap_startup,
397*4882a593Smuzhiyun };
398*4882a593Smuzhiyun
399*4882a593Smuzhiyun SND_SOC_DAILINK_DEF(dummy,
400*4882a593Smuzhiyun DAILINK_COMP_ARRAY(COMP_DUMMY()));
401*4882a593Smuzhiyun
402*4882a593Smuzhiyun SND_SOC_DAILINK_DEF(system,
403*4882a593Smuzhiyun DAILINK_COMP_ARRAY(COMP_CPU("System Pin")));
404*4882a593Smuzhiyun
405*4882a593Smuzhiyun SND_SOC_DAILINK_DEF(reference,
406*4882a593Smuzhiyun DAILINK_COMP_ARRAY(COMP_CPU("Reference Pin")));
407*4882a593Smuzhiyun
408*4882a593Smuzhiyun SND_SOC_DAILINK_DEF(dmic,
409*4882a593Smuzhiyun DAILINK_COMP_ARRAY(COMP_CPU("DMIC Pin")));
410*4882a593Smuzhiyun
411*4882a593Smuzhiyun SND_SOC_DAILINK_DEF(hdmi1,
412*4882a593Smuzhiyun DAILINK_COMP_ARRAY(COMP_CPU("HDMI1 Pin")));
413*4882a593Smuzhiyun
414*4882a593Smuzhiyun SND_SOC_DAILINK_DEF(hdmi2,
415*4882a593Smuzhiyun DAILINK_COMP_ARRAY(COMP_CPU("HDMI2 Pin")));
416*4882a593Smuzhiyun
417*4882a593Smuzhiyun SND_SOC_DAILINK_DEF(hdmi3,
418*4882a593Smuzhiyun DAILINK_COMP_ARRAY(COMP_CPU("HDMI3 Pin")));
419*4882a593Smuzhiyun
420*4882a593Smuzhiyun SND_SOC_DAILINK_DEF(ssp0_pin,
421*4882a593Smuzhiyun DAILINK_COMP_ARRAY(COMP_CPU("SSP0 Pin")));
422*4882a593Smuzhiyun SND_SOC_DAILINK_DEF(ssp0_codec,
423*4882a593Smuzhiyun DAILINK_COMP_ARRAY(COMP_CODEC("MX98357A:00", SKL_MAXIM_CODEC_DAI)));
424*4882a593Smuzhiyun
425*4882a593Smuzhiyun SND_SOC_DAILINK_DEF(ssp1_pin,
426*4882a593Smuzhiyun DAILINK_COMP_ARRAY(COMP_CPU("SSP1 Pin")));
427*4882a593Smuzhiyun SND_SOC_DAILINK_DEF(ssp1_codec,
428*4882a593Smuzhiyun DAILINK_COMP_ARRAY(COMP_CODEC("i2c-10508825:00",
429*4882a593Smuzhiyun SKL_NUVOTON_CODEC_DAI)));
430*4882a593Smuzhiyun
431*4882a593Smuzhiyun SND_SOC_DAILINK_DEF(dmic_pin,
432*4882a593Smuzhiyun DAILINK_COMP_ARRAY(COMP_CPU("DMIC01 Pin")));
433*4882a593Smuzhiyun SND_SOC_DAILINK_DEF(dmic_codec,
434*4882a593Smuzhiyun DAILINK_COMP_ARRAY(COMP_CODEC("dmic-codec", "dmic-hifi")));
435*4882a593Smuzhiyun
436*4882a593Smuzhiyun SND_SOC_DAILINK_DEF(idisp1_pin,
437*4882a593Smuzhiyun DAILINK_COMP_ARRAY(COMP_CPU("iDisp1 Pin")));
438*4882a593Smuzhiyun SND_SOC_DAILINK_DEF(idisp1_codec,
439*4882a593Smuzhiyun DAILINK_COMP_ARRAY(COMP_CODEC("ehdaudio0D2", "intel-hdmi-hifi1")));
440*4882a593Smuzhiyun
441*4882a593Smuzhiyun SND_SOC_DAILINK_DEF(idisp2_pin,
442*4882a593Smuzhiyun DAILINK_COMP_ARRAY(COMP_CPU("iDisp2 Pin")));
443*4882a593Smuzhiyun SND_SOC_DAILINK_DEF(idisp2_codec,
444*4882a593Smuzhiyun DAILINK_COMP_ARRAY(COMP_CODEC("ehdaudio0D2", "intel-hdmi-hifi2")));
445*4882a593Smuzhiyun
446*4882a593Smuzhiyun SND_SOC_DAILINK_DEF(idisp3_pin,
447*4882a593Smuzhiyun DAILINK_COMP_ARRAY(COMP_CPU("iDisp3 Pin")));
448*4882a593Smuzhiyun SND_SOC_DAILINK_DEF(idisp3_codec,
449*4882a593Smuzhiyun DAILINK_COMP_ARRAY(COMP_CODEC("ehdaudio0D2", "intel-hdmi-hifi3")));
450*4882a593Smuzhiyun
451*4882a593Smuzhiyun SND_SOC_DAILINK_DEF(platform,
452*4882a593Smuzhiyun DAILINK_COMP_ARRAY(COMP_PLATFORM("0000:00:1f.3")));
453*4882a593Smuzhiyun
454*4882a593Smuzhiyun /* skylake digital audio interface glue - connects codec <--> CPU */
455*4882a593Smuzhiyun static struct snd_soc_dai_link skylake_dais[] = {
456*4882a593Smuzhiyun /* Front End DAI links */
457*4882a593Smuzhiyun [SKL_DPCM_AUDIO_PB] = {
458*4882a593Smuzhiyun .name = "Skl Audio Port",
459*4882a593Smuzhiyun .stream_name = "Audio",
460*4882a593Smuzhiyun .dynamic = 1,
461*4882a593Smuzhiyun .nonatomic = 1,
462*4882a593Smuzhiyun .init = skylake_nau8825_fe_init,
463*4882a593Smuzhiyun .trigger = {
464*4882a593Smuzhiyun SND_SOC_DPCM_TRIGGER_POST, SND_SOC_DPCM_TRIGGER_POST},
465*4882a593Smuzhiyun .dpcm_playback = 1,
466*4882a593Smuzhiyun .ops = &skylake_nau8825_fe_ops,
467*4882a593Smuzhiyun SND_SOC_DAILINK_REG(system, dummy, platform),
468*4882a593Smuzhiyun },
469*4882a593Smuzhiyun [SKL_DPCM_AUDIO_CP] = {
470*4882a593Smuzhiyun .name = "Skl Audio Capture Port",
471*4882a593Smuzhiyun .stream_name = "Audio Record",
472*4882a593Smuzhiyun .dynamic = 1,
473*4882a593Smuzhiyun .nonatomic = 1,
474*4882a593Smuzhiyun .trigger = {
475*4882a593Smuzhiyun SND_SOC_DPCM_TRIGGER_POST, SND_SOC_DPCM_TRIGGER_POST},
476*4882a593Smuzhiyun .dpcm_capture = 1,
477*4882a593Smuzhiyun .ops = &skylake_nau8825_fe_ops,
478*4882a593Smuzhiyun SND_SOC_DAILINK_REG(system, dummy, platform),
479*4882a593Smuzhiyun },
480*4882a593Smuzhiyun [SKL_DPCM_AUDIO_REF_CP] = {
481*4882a593Smuzhiyun .name = "Skl Audio Reference cap",
482*4882a593Smuzhiyun .stream_name = "Wake on Voice",
483*4882a593Smuzhiyun .init = NULL,
484*4882a593Smuzhiyun .dpcm_capture = 1,
485*4882a593Smuzhiyun .nonatomic = 1,
486*4882a593Smuzhiyun .dynamic = 1,
487*4882a593Smuzhiyun .ops = &skylake_refcap_ops,
488*4882a593Smuzhiyun SND_SOC_DAILINK_REG(reference, dummy, platform),
489*4882a593Smuzhiyun },
490*4882a593Smuzhiyun [SKL_DPCM_AUDIO_DMIC_CP] = {
491*4882a593Smuzhiyun .name = "Skl Audio DMIC cap",
492*4882a593Smuzhiyun .stream_name = "dmiccap",
493*4882a593Smuzhiyun .init = NULL,
494*4882a593Smuzhiyun .dpcm_capture = 1,
495*4882a593Smuzhiyun .nonatomic = 1,
496*4882a593Smuzhiyun .dynamic = 1,
497*4882a593Smuzhiyun .ops = &skylake_dmic_ops,
498*4882a593Smuzhiyun SND_SOC_DAILINK_REG(dmic, dummy, platform),
499*4882a593Smuzhiyun },
500*4882a593Smuzhiyun [SKL_DPCM_AUDIO_HDMI1_PB] = {
501*4882a593Smuzhiyun .name = "Skl HDMI Port1",
502*4882a593Smuzhiyun .stream_name = "Hdmi1",
503*4882a593Smuzhiyun .dpcm_playback = 1,
504*4882a593Smuzhiyun .init = NULL,
505*4882a593Smuzhiyun .trigger = {
506*4882a593Smuzhiyun SND_SOC_DPCM_TRIGGER_POST, SND_SOC_DPCM_TRIGGER_POST},
507*4882a593Smuzhiyun .nonatomic = 1,
508*4882a593Smuzhiyun .dynamic = 1,
509*4882a593Smuzhiyun SND_SOC_DAILINK_REG(hdmi1, dummy, platform),
510*4882a593Smuzhiyun },
511*4882a593Smuzhiyun [SKL_DPCM_AUDIO_HDMI2_PB] = {
512*4882a593Smuzhiyun .name = "Skl HDMI Port2",
513*4882a593Smuzhiyun .stream_name = "Hdmi2",
514*4882a593Smuzhiyun .dpcm_playback = 1,
515*4882a593Smuzhiyun .init = NULL,
516*4882a593Smuzhiyun .trigger = {
517*4882a593Smuzhiyun SND_SOC_DPCM_TRIGGER_POST, SND_SOC_DPCM_TRIGGER_POST},
518*4882a593Smuzhiyun .nonatomic = 1,
519*4882a593Smuzhiyun .dynamic = 1,
520*4882a593Smuzhiyun SND_SOC_DAILINK_REG(hdmi2, dummy, platform),
521*4882a593Smuzhiyun },
522*4882a593Smuzhiyun [SKL_DPCM_AUDIO_HDMI3_PB] = {
523*4882a593Smuzhiyun .name = "Skl HDMI Port3",
524*4882a593Smuzhiyun .stream_name = "Hdmi3",
525*4882a593Smuzhiyun .trigger = {
526*4882a593Smuzhiyun SND_SOC_DPCM_TRIGGER_POST, SND_SOC_DPCM_TRIGGER_POST},
527*4882a593Smuzhiyun .dpcm_playback = 1,
528*4882a593Smuzhiyun .init = NULL,
529*4882a593Smuzhiyun .nonatomic = 1,
530*4882a593Smuzhiyun .dynamic = 1,
531*4882a593Smuzhiyun SND_SOC_DAILINK_REG(hdmi3, dummy, platform),
532*4882a593Smuzhiyun },
533*4882a593Smuzhiyun
534*4882a593Smuzhiyun /* Back End DAI links */
535*4882a593Smuzhiyun {
536*4882a593Smuzhiyun /* SSP0 - Codec */
537*4882a593Smuzhiyun .name = "SSP0-Codec",
538*4882a593Smuzhiyun .id = 0,
539*4882a593Smuzhiyun .no_pcm = 1,
540*4882a593Smuzhiyun .dai_fmt = SND_SOC_DAIFMT_I2S |
541*4882a593Smuzhiyun SND_SOC_DAIFMT_NB_NF |
542*4882a593Smuzhiyun SND_SOC_DAIFMT_CBS_CFS,
543*4882a593Smuzhiyun .ignore_pmdown_time = 1,
544*4882a593Smuzhiyun .be_hw_params_fixup = skylake_ssp_fixup,
545*4882a593Smuzhiyun .dpcm_playback = 1,
546*4882a593Smuzhiyun SND_SOC_DAILINK_REG(ssp0_pin, ssp0_codec, platform),
547*4882a593Smuzhiyun },
548*4882a593Smuzhiyun {
549*4882a593Smuzhiyun /* SSP1 - Codec */
550*4882a593Smuzhiyun .name = "SSP1-Codec",
551*4882a593Smuzhiyun .id = 1,
552*4882a593Smuzhiyun .no_pcm = 1,
553*4882a593Smuzhiyun .init = skylake_nau8825_codec_init,
554*4882a593Smuzhiyun .dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
555*4882a593Smuzhiyun SND_SOC_DAIFMT_CBS_CFS,
556*4882a593Smuzhiyun .ignore_pmdown_time = 1,
557*4882a593Smuzhiyun .be_hw_params_fixup = skylake_ssp_fixup,
558*4882a593Smuzhiyun .ops = &skylake_nau8825_ops,
559*4882a593Smuzhiyun .dpcm_playback = 1,
560*4882a593Smuzhiyun .dpcm_capture = 1,
561*4882a593Smuzhiyun SND_SOC_DAILINK_REG(ssp1_pin, ssp1_codec, platform),
562*4882a593Smuzhiyun },
563*4882a593Smuzhiyun {
564*4882a593Smuzhiyun .name = "dmic01",
565*4882a593Smuzhiyun .id = 2,
566*4882a593Smuzhiyun .be_hw_params_fixup = skylake_dmic_fixup,
567*4882a593Smuzhiyun .ignore_suspend = 1,
568*4882a593Smuzhiyun .dpcm_capture = 1,
569*4882a593Smuzhiyun .no_pcm = 1,
570*4882a593Smuzhiyun SND_SOC_DAILINK_REG(dmic_pin, dmic_codec, platform),
571*4882a593Smuzhiyun },
572*4882a593Smuzhiyun {
573*4882a593Smuzhiyun .name = "iDisp1",
574*4882a593Smuzhiyun .id = 3,
575*4882a593Smuzhiyun .dpcm_playback = 1,
576*4882a593Smuzhiyun .init = skylake_hdmi1_init,
577*4882a593Smuzhiyun .no_pcm = 1,
578*4882a593Smuzhiyun SND_SOC_DAILINK_REG(idisp1_pin, idisp1_codec, platform),
579*4882a593Smuzhiyun },
580*4882a593Smuzhiyun {
581*4882a593Smuzhiyun .name = "iDisp2",
582*4882a593Smuzhiyun .id = 4,
583*4882a593Smuzhiyun .init = skylake_hdmi2_init,
584*4882a593Smuzhiyun .dpcm_playback = 1,
585*4882a593Smuzhiyun .no_pcm = 1,
586*4882a593Smuzhiyun SND_SOC_DAILINK_REG(idisp2_pin, idisp2_codec, platform),
587*4882a593Smuzhiyun },
588*4882a593Smuzhiyun {
589*4882a593Smuzhiyun .name = "iDisp3",
590*4882a593Smuzhiyun .id = 5,
591*4882a593Smuzhiyun .init = skylake_hdmi3_init,
592*4882a593Smuzhiyun .dpcm_playback = 1,
593*4882a593Smuzhiyun .no_pcm = 1,
594*4882a593Smuzhiyun SND_SOC_DAILINK_REG(idisp3_pin, idisp3_codec, platform),
595*4882a593Smuzhiyun },
596*4882a593Smuzhiyun };
597*4882a593Smuzhiyun
598*4882a593Smuzhiyun #define NAME_SIZE 32
skylake_card_late_probe(struct snd_soc_card * card)599*4882a593Smuzhiyun static int skylake_card_late_probe(struct snd_soc_card *card)
600*4882a593Smuzhiyun {
601*4882a593Smuzhiyun struct skl_nau8825_private *ctx = snd_soc_card_get_drvdata(card);
602*4882a593Smuzhiyun struct skl_hdmi_pcm *pcm;
603*4882a593Smuzhiyun struct snd_soc_component *component = NULL;
604*4882a593Smuzhiyun int err, i = 0;
605*4882a593Smuzhiyun char jack_name[NAME_SIZE];
606*4882a593Smuzhiyun
607*4882a593Smuzhiyun list_for_each_entry(pcm, &ctx->hdmi_pcm_list, head) {
608*4882a593Smuzhiyun component = pcm->codec_dai->component;
609*4882a593Smuzhiyun snprintf(jack_name, sizeof(jack_name),
610*4882a593Smuzhiyun "HDMI/DP, pcm=%d Jack", pcm->device);
611*4882a593Smuzhiyun err = snd_soc_card_jack_new(card, jack_name,
612*4882a593Smuzhiyun SND_JACK_AVOUT,
613*4882a593Smuzhiyun &skylake_hdmi[i],
614*4882a593Smuzhiyun NULL, 0);
615*4882a593Smuzhiyun
616*4882a593Smuzhiyun if (err)
617*4882a593Smuzhiyun return err;
618*4882a593Smuzhiyun
619*4882a593Smuzhiyun err = hdac_hdmi_jack_init(pcm->codec_dai, pcm->device,
620*4882a593Smuzhiyun &skylake_hdmi[i]);
621*4882a593Smuzhiyun if (err < 0)
622*4882a593Smuzhiyun return err;
623*4882a593Smuzhiyun
624*4882a593Smuzhiyun i++;
625*4882a593Smuzhiyun }
626*4882a593Smuzhiyun
627*4882a593Smuzhiyun if (!component)
628*4882a593Smuzhiyun return -EINVAL;
629*4882a593Smuzhiyun
630*4882a593Smuzhiyun return hdac_hdmi_jack_port_init(component, &card->dapm);
631*4882a593Smuzhiyun }
632*4882a593Smuzhiyun
633*4882a593Smuzhiyun /* skylake audio machine driver for SPT + NAU88L25 */
634*4882a593Smuzhiyun static struct snd_soc_card skylake_audio_card = {
635*4882a593Smuzhiyun .name = "sklnau8825max",
636*4882a593Smuzhiyun .owner = THIS_MODULE,
637*4882a593Smuzhiyun .dai_link = skylake_dais,
638*4882a593Smuzhiyun .num_links = ARRAY_SIZE(skylake_dais),
639*4882a593Smuzhiyun .controls = skylake_controls,
640*4882a593Smuzhiyun .num_controls = ARRAY_SIZE(skylake_controls),
641*4882a593Smuzhiyun .dapm_widgets = skylake_widgets,
642*4882a593Smuzhiyun .num_dapm_widgets = ARRAY_SIZE(skylake_widgets),
643*4882a593Smuzhiyun .dapm_routes = skylake_map,
644*4882a593Smuzhiyun .num_dapm_routes = ARRAY_SIZE(skylake_map),
645*4882a593Smuzhiyun .fully_routed = true,
646*4882a593Smuzhiyun .late_probe = skylake_card_late_probe,
647*4882a593Smuzhiyun };
648*4882a593Smuzhiyun
skylake_audio_probe(struct platform_device * pdev)649*4882a593Smuzhiyun static int skylake_audio_probe(struct platform_device *pdev)
650*4882a593Smuzhiyun {
651*4882a593Smuzhiyun struct skl_nau8825_private *ctx;
652*4882a593Smuzhiyun struct snd_soc_acpi_mach *mach;
653*4882a593Smuzhiyun
654*4882a593Smuzhiyun ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL);
655*4882a593Smuzhiyun if (!ctx)
656*4882a593Smuzhiyun return -ENOMEM;
657*4882a593Smuzhiyun
658*4882a593Smuzhiyun INIT_LIST_HEAD(&ctx->hdmi_pcm_list);
659*4882a593Smuzhiyun
660*4882a593Smuzhiyun skylake_audio_card.dev = &pdev->dev;
661*4882a593Smuzhiyun snd_soc_card_set_drvdata(&skylake_audio_card, ctx);
662*4882a593Smuzhiyun
663*4882a593Smuzhiyun mach = pdev->dev.platform_data;
664*4882a593Smuzhiyun if (mach)
665*4882a593Smuzhiyun dmic_constraints = mach->mach_params.dmic_num == 2 ?
666*4882a593Smuzhiyun &constraints_dmic_2ch : &constraints_dmic_channels;
667*4882a593Smuzhiyun
668*4882a593Smuzhiyun return devm_snd_soc_register_card(&pdev->dev, &skylake_audio_card);
669*4882a593Smuzhiyun }
670*4882a593Smuzhiyun
671*4882a593Smuzhiyun static const struct platform_device_id skl_board_ids[] = {
672*4882a593Smuzhiyun { .name = "skl_n88l25_m98357a" },
673*4882a593Smuzhiyun { .name = "kbl_n88l25_m98357a" },
674*4882a593Smuzhiyun { }
675*4882a593Smuzhiyun };
676*4882a593Smuzhiyun
677*4882a593Smuzhiyun static struct platform_driver skylake_audio = {
678*4882a593Smuzhiyun .probe = skylake_audio_probe,
679*4882a593Smuzhiyun .driver = {
680*4882a593Smuzhiyun .name = "skl_n88l25_m98357a",
681*4882a593Smuzhiyun .pm = &snd_soc_pm_ops,
682*4882a593Smuzhiyun },
683*4882a593Smuzhiyun .id_table = skl_board_ids,
684*4882a593Smuzhiyun };
685*4882a593Smuzhiyun
686*4882a593Smuzhiyun module_platform_driver(skylake_audio)
687*4882a593Smuzhiyun
688*4882a593Smuzhiyun /* Module information */
689*4882a593Smuzhiyun MODULE_DESCRIPTION("Audio Machine driver-NAU88L25 & MAX98357A in I2S mode");
690*4882a593Smuzhiyun MODULE_AUTHOR("Rohit Ainapure <rohit.m.ainapure@intel.com");
691*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
692*4882a593Smuzhiyun MODULE_ALIAS("platform:skl_n88l25_m98357a");
693*4882a593Smuzhiyun MODULE_ALIAS("platform:kbl_n88l25_m98357a");
694