1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun // Copyright(c) 2018 Intel Corporation.
3*4882a593Smuzhiyun
4*4882a593Smuzhiyun /*
5*4882a593Smuzhiyun * Intel Geminilake I2S Machine Driver with MAX98357A & RT5682 Codecs
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Modified from:
8*4882a593Smuzhiyun * Intel Apollolake I2S Machine driver
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <linux/input.h>
12*4882a593Smuzhiyun #include <linux/module.h>
13*4882a593Smuzhiyun #include <linux/platform_device.h>
14*4882a593Smuzhiyun #include <sound/core.h>
15*4882a593Smuzhiyun #include <sound/jack.h>
16*4882a593Smuzhiyun #include <sound/pcm.h>
17*4882a593Smuzhiyun #include <sound/pcm_params.h>
18*4882a593Smuzhiyun #include <sound/soc.h>
19*4882a593Smuzhiyun #include <sound/soc-acpi.h>
20*4882a593Smuzhiyun #include "../../codecs/rt5682.h"
21*4882a593Smuzhiyun #include "../../codecs/hdac_hdmi.h"
22*4882a593Smuzhiyun #include "hda_dsp_common.h"
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun /* The platform clock outputs 19.2Mhz clock to codec as I2S MCLK */
25*4882a593Smuzhiyun #define GLK_PLAT_CLK_FREQ 19200000
26*4882a593Smuzhiyun #define RT5682_PLL_FREQ (48000 * 512)
27*4882a593Smuzhiyun #define GLK_REALTEK_CODEC_DAI "rt5682-aif1"
28*4882a593Smuzhiyun #define GLK_MAXIM_CODEC_DAI "HiFi"
29*4882a593Smuzhiyun #define MAXIM_DEV0_NAME "MX98357A:00"
30*4882a593Smuzhiyun #define DUAL_CHANNEL 2
31*4882a593Smuzhiyun #define QUAD_CHANNEL 4
32*4882a593Smuzhiyun #define NAME_SIZE 32
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun static struct snd_soc_jack geminilake_hdmi[3];
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun struct glk_hdmi_pcm {
37*4882a593Smuzhiyun struct list_head head;
38*4882a593Smuzhiyun struct snd_soc_dai *codec_dai;
39*4882a593Smuzhiyun int device;
40*4882a593Smuzhiyun };
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun struct glk_card_private {
43*4882a593Smuzhiyun struct snd_soc_jack geminilake_headset;
44*4882a593Smuzhiyun struct list_head hdmi_pcm_list;
45*4882a593Smuzhiyun bool common_hdmi_codec_drv;
46*4882a593Smuzhiyun };
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun enum {
49*4882a593Smuzhiyun GLK_DPCM_AUDIO_PB = 0,
50*4882a593Smuzhiyun GLK_DPCM_AUDIO_CP,
51*4882a593Smuzhiyun GLK_DPCM_AUDIO_HS_PB,
52*4882a593Smuzhiyun GLK_DPCM_AUDIO_ECHO_REF_CP,
53*4882a593Smuzhiyun GLK_DPCM_AUDIO_REF_CP,
54*4882a593Smuzhiyun GLK_DPCM_AUDIO_DMIC_CP,
55*4882a593Smuzhiyun GLK_DPCM_AUDIO_HDMI1_PB,
56*4882a593Smuzhiyun GLK_DPCM_AUDIO_HDMI2_PB,
57*4882a593Smuzhiyun GLK_DPCM_AUDIO_HDMI3_PB,
58*4882a593Smuzhiyun };
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun static const struct snd_kcontrol_new geminilake_controls[] = {
61*4882a593Smuzhiyun SOC_DAPM_PIN_SWITCH("Headphone Jack"),
62*4882a593Smuzhiyun SOC_DAPM_PIN_SWITCH("Headset Mic"),
63*4882a593Smuzhiyun SOC_DAPM_PIN_SWITCH("Spk"),
64*4882a593Smuzhiyun };
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun static const struct snd_soc_dapm_widget geminilake_widgets[] = {
67*4882a593Smuzhiyun SND_SOC_DAPM_HP("Headphone Jack", NULL),
68*4882a593Smuzhiyun SND_SOC_DAPM_MIC("Headset Mic", NULL),
69*4882a593Smuzhiyun SND_SOC_DAPM_SPK("Spk", NULL),
70*4882a593Smuzhiyun SND_SOC_DAPM_MIC("SoC DMIC", NULL),
71*4882a593Smuzhiyun SND_SOC_DAPM_SPK("HDMI1", NULL),
72*4882a593Smuzhiyun SND_SOC_DAPM_SPK("HDMI2", NULL),
73*4882a593Smuzhiyun SND_SOC_DAPM_SPK("HDMI3", NULL),
74*4882a593Smuzhiyun };
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun static const struct snd_soc_dapm_route geminilake_map[] = {
77*4882a593Smuzhiyun /* HP jack connectors - unknown if we have jack detection */
78*4882a593Smuzhiyun { "Headphone Jack", NULL, "HPOL" },
79*4882a593Smuzhiyun { "Headphone Jack", NULL, "HPOR" },
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun /* speaker */
82*4882a593Smuzhiyun { "Spk", NULL, "Speaker" },
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun /* other jacks */
85*4882a593Smuzhiyun { "IN1P", NULL, "Headset Mic" },
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun /* digital mics */
88*4882a593Smuzhiyun { "DMic", NULL, "SoC DMIC" },
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun /* CODEC BE connections */
91*4882a593Smuzhiyun { "HiFi Playback", NULL, "ssp1 Tx" },
92*4882a593Smuzhiyun { "ssp1 Tx", NULL, "codec0_out" },
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun { "AIF1 Playback", NULL, "ssp2 Tx" },
95*4882a593Smuzhiyun { "ssp2 Tx", NULL, "codec1_out" },
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun { "codec0_in", NULL, "ssp2 Rx" },
98*4882a593Smuzhiyun { "ssp2 Rx", NULL, "AIF1 Capture" },
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun { "HDMI1", NULL, "hif5-0 Output" },
101*4882a593Smuzhiyun { "HDMI2", NULL, "hif6-0 Output" },
102*4882a593Smuzhiyun { "HDMI2", NULL, "hif7-0 Output" },
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun { "hifi3", NULL, "iDisp3 Tx" },
105*4882a593Smuzhiyun { "iDisp3 Tx", NULL, "iDisp3_out" },
106*4882a593Smuzhiyun { "hifi2", NULL, "iDisp2 Tx" },
107*4882a593Smuzhiyun { "iDisp2 Tx", NULL, "iDisp2_out" },
108*4882a593Smuzhiyun { "hifi1", NULL, "iDisp1 Tx" },
109*4882a593Smuzhiyun { "iDisp1 Tx", NULL, "iDisp1_out" },
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun /* DMIC */
112*4882a593Smuzhiyun { "dmic01_hifi", NULL, "DMIC01 Rx" },
113*4882a593Smuzhiyun { "DMIC01 Rx", NULL, "DMIC AIF" },
114*4882a593Smuzhiyun };
115*4882a593Smuzhiyun
geminilake_ssp_fixup(struct snd_soc_pcm_runtime * rtd,struct snd_pcm_hw_params * params)116*4882a593Smuzhiyun static int geminilake_ssp_fixup(struct snd_soc_pcm_runtime *rtd,
117*4882a593Smuzhiyun struct snd_pcm_hw_params *params)
118*4882a593Smuzhiyun {
119*4882a593Smuzhiyun struct snd_interval *rate = hw_param_interval(params,
120*4882a593Smuzhiyun SNDRV_PCM_HW_PARAM_RATE);
121*4882a593Smuzhiyun struct snd_interval *chan = hw_param_interval(params,
122*4882a593Smuzhiyun SNDRV_PCM_HW_PARAM_CHANNELS);
123*4882a593Smuzhiyun struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun /* The ADSP will convert the FE rate to 48k, stereo */
126*4882a593Smuzhiyun rate->min = rate->max = 48000;
127*4882a593Smuzhiyun chan->min = chan->max = DUAL_CHANNEL;
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun /* set SSP to 24 bit */
130*4882a593Smuzhiyun snd_mask_none(fmt);
131*4882a593Smuzhiyun snd_mask_set_format(fmt, SNDRV_PCM_FORMAT_S24_LE);
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun return 0;
134*4882a593Smuzhiyun }
135*4882a593Smuzhiyun
geminilake_rt5682_codec_init(struct snd_soc_pcm_runtime * rtd)136*4882a593Smuzhiyun static int geminilake_rt5682_codec_init(struct snd_soc_pcm_runtime *rtd)
137*4882a593Smuzhiyun {
138*4882a593Smuzhiyun struct glk_card_private *ctx = snd_soc_card_get_drvdata(rtd->card);
139*4882a593Smuzhiyun struct snd_soc_component *component = asoc_rtd_to_codec(rtd, 0)->component;
140*4882a593Smuzhiyun struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
141*4882a593Smuzhiyun struct snd_soc_jack *jack;
142*4882a593Smuzhiyun int ret;
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun ret = snd_soc_dai_set_pll(codec_dai, 0, RT5682_PLL1_S_MCLK,
145*4882a593Smuzhiyun GLK_PLAT_CLK_FREQ, RT5682_PLL_FREQ);
146*4882a593Smuzhiyun if (ret < 0) {
147*4882a593Smuzhiyun dev_err(rtd->dev, "can't set codec pll: %d\n", ret);
148*4882a593Smuzhiyun return ret;
149*4882a593Smuzhiyun }
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun /* Configure sysclk for codec */
152*4882a593Smuzhiyun ret = snd_soc_dai_set_sysclk(codec_dai, RT5682_SCLK_S_PLL1,
153*4882a593Smuzhiyun RT5682_PLL_FREQ, SND_SOC_CLOCK_IN);
154*4882a593Smuzhiyun if (ret < 0)
155*4882a593Smuzhiyun dev_err(rtd->dev, "snd_soc_dai_set_sysclk err = %d\n", ret);
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun /*
158*4882a593Smuzhiyun * Headset buttons map to the google Reference headset.
159*4882a593Smuzhiyun * These can be configured by userspace.
160*4882a593Smuzhiyun */
161*4882a593Smuzhiyun ret = snd_soc_card_jack_new(rtd->card, "Headset Jack",
162*4882a593Smuzhiyun SND_JACK_HEADSET | SND_JACK_BTN_0 | SND_JACK_BTN_1 |
163*4882a593Smuzhiyun SND_JACK_BTN_2 | SND_JACK_BTN_3 | SND_JACK_LINEOUT,
164*4882a593Smuzhiyun &ctx->geminilake_headset, NULL, 0);
165*4882a593Smuzhiyun if (ret) {
166*4882a593Smuzhiyun dev_err(rtd->dev, "Headset Jack creation failed: %d\n", ret);
167*4882a593Smuzhiyun return ret;
168*4882a593Smuzhiyun }
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun jack = &ctx->geminilake_headset;
171*4882a593Smuzhiyun
172*4882a593Smuzhiyun snd_jack_set_key(jack->jack, SND_JACK_BTN_0, KEY_PLAYPAUSE);
173*4882a593Smuzhiyun snd_jack_set_key(jack->jack, SND_JACK_BTN_1, KEY_VOICECOMMAND);
174*4882a593Smuzhiyun snd_jack_set_key(jack->jack, SND_JACK_BTN_2, KEY_VOLUMEUP);
175*4882a593Smuzhiyun snd_jack_set_key(jack->jack, SND_JACK_BTN_3, KEY_VOLUMEDOWN);
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun ret = snd_soc_component_set_jack(component, jack, NULL);
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun if (ret) {
180*4882a593Smuzhiyun dev_err(rtd->dev, "Headset Jack call-back failed: %d\n", ret);
181*4882a593Smuzhiyun return ret;
182*4882a593Smuzhiyun }
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun return ret;
185*4882a593Smuzhiyun };
186*4882a593Smuzhiyun
geminilake_rt5682_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params)187*4882a593Smuzhiyun static int geminilake_rt5682_hw_params(struct snd_pcm_substream *substream,
188*4882a593Smuzhiyun struct snd_pcm_hw_params *params)
189*4882a593Smuzhiyun {
190*4882a593Smuzhiyun struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
191*4882a593Smuzhiyun struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
192*4882a593Smuzhiyun int ret;
193*4882a593Smuzhiyun
194*4882a593Smuzhiyun /* Set valid bitmask & configuration for I2S in 24 bit */
195*4882a593Smuzhiyun ret = snd_soc_dai_set_tdm_slot(codec_dai, 0x0, 0x0, 2, 24);
196*4882a593Smuzhiyun if (ret < 0) {
197*4882a593Smuzhiyun dev_err(rtd->dev, "set TDM slot err:%d\n", ret);
198*4882a593Smuzhiyun return ret;
199*4882a593Smuzhiyun }
200*4882a593Smuzhiyun
201*4882a593Smuzhiyun return ret;
202*4882a593Smuzhiyun }
203*4882a593Smuzhiyun
204*4882a593Smuzhiyun static struct snd_soc_ops geminilake_rt5682_ops = {
205*4882a593Smuzhiyun .hw_params = geminilake_rt5682_hw_params,
206*4882a593Smuzhiyun };
207*4882a593Smuzhiyun
geminilake_hdmi_init(struct snd_soc_pcm_runtime * rtd)208*4882a593Smuzhiyun static int geminilake_hdmi_init(struct snd_soc_pcm_runtime *rtd)
209*4882a593Smuzhiyun {
210*4882a593Smuzhiyun struct glk_card_private *ctx = snd_soc_card_get_drvdata(rtd->card);
211*4882a593Smuzhiyun struct snd_soc_dai *dai = asoc_rtd_to_codec(rtd, 0);
212*4882a593Smuzhiyun struct glk_hdmi_pcm *pcm;
213*4882a593Smuzhiyun
214*4882a593Smuzhiyun pcm = devm_kzalloc(rtd->card->dev, sizeof(*pcm), GFP_KERNEL);
215*4882a593Smuzhiyun if (!pcm)
216*4882a593Smuzhiyun return -ENOMEM;
217*4882a593Smuzhiyun
218*4882a593Smuzhiyun pcm->device = GLK_DPCM_AUDIO_HDMI1_PB + dai->id;
219*4882a593Smuzhiyun pcm->codec_dai = dai;
220*4882a593Smuzhiyun
221*4882a593Smuzhiyun list_add_tail(&pcm->head, &ctx->hdmi_pcm_list);
222*4882a593Smuzhiyun
223*4882a593Smuzhiyun return 0;
224*4882a593Smuzhiyun }
225*4882a593Smuzhiyun
geminilake_rt5682_fe_init(struct snd_soc_pcm_runtime * rtd)226*4882a593Smuzhiyun static int geminilake_rt5682_fe_init(struct snd_soc_pcm_runtime *rtd)
227*4882a593Smuzhiyun {
228*4882a593Smuzhiyun struct snd_soc_component *component = asoc_rtd_to_cpu(rtd, 0)->component;
229*4882a593Smuzhiyun struct snd_soc_dapm_context *dapm;
230*4882a593Smuzhiyun int ret;
231*4882a593Smuzhiyun
232*4882a593Smuzhiyun dapm = snd_soc_component_get_dapm(component);
233*4882a593Smuzhiyun ret = snd_soc_dapm_ignore_suspend(dapm, "Reference Capture");
234*4882a593Smuzhiyun if (ret) {
235*4882a593Smuzhiyun dev_err(rtd->dev, "Ref Cap ignore suspend failed %d\n", ret);
236*4882a593Smuzhiyun return ret;
237*4882a593Smuzhiyun }
238*4882a593Smuzhiyun
239*4882a593Smuzhiyun return ret;
240*4882a593Smuzhiyun }
241*4882a593Smuzhiyun
242*4882a593Smuzhiyun static const unsigned int rates[] = {
243*4882a593Smuzhiyun 48000,
244*4882a593Smuzhiyun };
245*4882a593Smuzhiyun
246*4882a593Smuzhiyun static const struct snd_pcm_hw_constraint_list constraints_rates = {
247*4882a593Smuzhiyun .count = ARRAY_SIZE(rates),
248*4882a593Smuzhiyun .list = rates,
249*4882a593Smuzhiyun .mask = 0,
250*4882a593Smuzhiyun };
251*4882a593Smuzhiyun
252*4882a593Smuzhiyun static unsigned int channels_quad[] = {
253*4882a593Smuzhiyun QUAD_CHANNEL,
254*4882a593Smuzhiyun };
255*4882a593Smuzhiyun
256*4882a593Smuzhiyun static struct snd_pcm_hw_constraint_list constraints_channels_quad = {
257*4882a593Smuzhiyun .count = ARRAY_SIZE(channels_quad),
258*4882a593Smuzhiyun .list = channels_quad,
259*4882a593Smuzhiyun .mask = 0,
260*4882a593Smuzhiyun };
261*4882a593Smuzhiyun
geminilake_dmic_fixup(struct snd_soc_pcm_runtime * rtd,struct snd_pcm_hw_params * params)262*4882a593Smuzhiyun static int geminilake_dmic_fixup(struct snd_soc_pcm_runtime *rtd,
263*4882a593Smuzhiyun struct snd_pcm_hw_params *params)
264*4882a593Smuzhiyun {
265*4882a593Smuzhiyun struct snd_interval *chan = hw_param_interval(params,
266*4882a593Smuzhiyun SNDRV_PCM_HW_PARAM_CHANNELS);
267*4882a593Smuzhiyun
268*4882a593Smuzhiyun /*
269*4882a593Smuzhiyun * set BE channel constraint as user FE channels
270*4882a593Smuzhiyun */
271*4882a593Smuzhiyun chan->min = chan->max = 4;
272*4882a593Smuzhiyun
273*4882a593Smuzhiyun return 0;
274*4882a593Smuzhiyun }
275*4882a593Smuzhiyun
geminilake_dmic_startup(struct snd_pcm_substream * substream)276*4882a593Smuzhiyun static int geminilake_dmic_startup(struct snd_pcm_substream *substream)
277*4882a593Smuzhiyun {
278*4882a593Smuzhiyun struct snd_pcm_runtime *runtime = substream->runtime;
279*4882a593Smuzhiyun
280*4882a593Smuzhiyun runtime->hw.channels_min = runtime->hw.channels_max = QUAD_CHANNEL;
281*4882a593Smuzhiyun snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
282*4882a593Smuzhiyun &constraints_channels_quad);
283*4882a593Smuzhiyun
284*4882a593Smuzhiyun return snd_pcm_hw_constraint_list(substream->runtime, 0,
285*4882a593Smuzhiyun SNDRV_PCM_HW_PARAM_RATE, &constraints_rates);
286*4882a593Smuzhiyun }
287*4882a593Smuzhiyun
288*4882a593Smuzhiyun static const struct snd_soc_ops geminilake_dmic_ops = {
289*4882a593Smuzhiyun .startup = geminilake_dmic_startup,
290*4882a593Smuzhiyun };
291*4882a593Smuzhiyun
292*4882a593Smuzhiyun static const unsigned int rates_16000[] = {
293*4882a593Smuzhiyun 16000,
294*4882a593Smuzhiyun };
295*4882a593Smuzhiyun
296*4882a593Smuzhiyun static const struct snd_pcm_hw_constraint_list constraints_16000 = {
297*4882a593Smuzhiyun .count = ARRAY_SIZE(rates_16000),
298*4882a593Smuzhiyun .list = rates_16000,
299*4882a593Smuzhiyun };
300*4882a593Smuzhiyun
geminilake_refcap_startup(struct snd_pcm_substream * substream)301*4882a593Smuzhiyun static int geminilake_refcap_startup(struct snd_pcm_substream *substream)
302*4882a593Smuzhiyun {
303*4882a593Smuzhiyun return snd_pcm_hw_constraint_list(substream->runtime, 0,
304*4882a593Smuzhiyun SNDRV_PCM_HW_PARAM_RATE,
305*4882a593Smuzhiyun &constraints_16000);
306*4882a593Smuzhiyun };
307*4882a593Smuzhiyun
308*4882a593Smuzhiyun static const struct snd_soc_ops geminilake_refcap_ops = {
309*4882a593Smuzhiyun .startup = geminilake_refcap_startup,
310*4882a593Smuzhiyun };
311*4882a593Smuzhiyun
312*4882a593Smuzhiyun SND_SOC_DAILINK_DEF(dummy,
313*4882a593Smuzhiyun DAILINK_COMP_ARRAY(COMP_DUMMY()));
314*4882a593Smuzhiyun
315*4882a593Smuzhiyun SND_SOC_DAILINK_DEF(system,
316*4882a593Smuzhiyun DAILINK_COMP_ARRAY(COMP_CPU("System Pin")));
317*4882a593Smuzhiyun
318*4882a593Smuzhiyun SND_SOC_DAILINK_DEF(system2,
319*4882a593Smuzhiyun DAILINK_COMP_ARRAY(COMP_CPU("System Pin2")));
320*4882a593Smuzhiyun
321*4882a593Smuzhiyun SND_SOC_DAILINK_DEF(echoref,
322*4882a593Smuzhiyun DAILINK_COMP_ARRAY(COMP_CPU("Echoref Pin")));
323*4882a593Smuzhiyun
324*4882a593Smuzhiyun SND_SOC_DAILINK_DEF(reference,
325*4882a593Smuzhiyun DAILINK_COMP_ARRAY(COMP_CPU("Reference Pin")));
326*4882a593Smuzhiyun
327*4882a593Smuzhiyun SND_SOC_DAILINK_DEF(dmic,
328*4882a593Smuzhiyun DAILINK_COMP_ARRAY(COMP_CPU("DMIC Pin")));
329*4882a593Smuzhiyun
330*4882a593Smuzhiyun SND_SOC_DAILINK_DEF(hdmi1,
331*4882a593Smuzhiyun DAILINK_COMP_ARRAY(COMP_CPU("HDMI1 Pin")));
332*4882a593Smuzhiyun
333*4882a593Smuzhiyun SND_SOC_DAILINK_DEF(hdmi2,
334*4882a593Smuzhiyun DAILINK_COMP_ARRAY(COMP_CPU("HDMI2 Pin")));
335*4882a593Smuzhiyun
336*4882a593Smuzhiyun SND_SOC_DAILINK_DEF(hdmi3,
337*4882a593Smuzhiyun DAILINK_COMP_ARRAY(COMP_CPU("HDMI3 Pin")));
338*4882a593Smuzhiyun
339*4882a593Smuzhiyun SND_SOC_DAILINK_DEF(ssp1_pin,
340*4882a593Smuzhiyun DAILINK_COMP_ARRAY(COMP_CPU("SSP1 Pin")));
341*4882a593Smuzhiyun SND_SOC_DAILINK_DEF(ssp1_codec,
342*4882a593Smuzhiyun DAILINK_COMP_ARRAY(COMP_CODEC(MAXIM_DEV0_NAME,
343*4882a593Smuzhiyun GLK_MAXIM_CODEC_DAI)));
344*4882a593Smuzhiyun
345*4882a593Smuzhiyun SND_SOC_DAILINK_DEF(ssp2_pin,
346*4882a593Smuzhiyun DAILINK_COMP_ARRAY(COMP_CPU("SSP2 Pin")));
347*4882a593Smuzhiyun SND_SOC_DAILINK_DEF(ssp2_codec,
348*4882a593Smuzhiyun DAILINK_COMP_ARRAY(COMP_CODEC("i2c-10EC5682:00",
349*4882a593Smuzhiyun GLK_REALTEK_CODEC_DAI)));
350*4882a593Smuzhiyun
351*4882a593Smuzhiyun SND_SOC_DAILINK_DEF(dmic_pin,
352*4882a593Smuzhiyun DAILINK_COMP_ARRAY(COMP_CPU("DMIC01 Pin")));
353*4882a593Smuzhiyun SND_SOC_DAILINK_DEF(dmic_codec,
354*4882a593Smuzhiyun DAILINK_COMP_ARRAY(COMP_CODEC("dmic-codec", "dmic-hifi")));
355*4882a593Smuzhiyun
356*4882a593Smuzhiyun SND_SOC_DAILINK_DEF(idisp1_pin,
357*4882a593Smuzhiyun DAILINK_COMP_ARRAY(COMP_CPU("iDisp1 Pin")));
358*4882a593Smuzhiyun SND_SOC_DAILINK_DEF(idisp1_codec,
359*4882a593Smuzhiyun DAILINK_COMP_ARRAY(COMP_CODEC("ehdaudio0D2", "intel-hdmi-hifi1")));
360*4882a593Smuzhiyun
361*4882a593Smuzhiyun SND_SOC_DAILINK_DEF(idisp2_pin,
362*4882a593Smuzhiyun DAILINK_COMP_ARRAY(COMP_CPU("iDisp2 Pin")));
363*4882a593Smuzhiyun SND_SOC_DAILINK_DEF(idisp2_codec,
364*4882a593Smuzhiyun DAILINK_COMP_ARRAY(COMP_CODEC("ehdaudio0D2", "intel-hdmi-hifi2")));
365*4882a593Smuzhiyun
366*4882a593Smuzhiyun SND_SOC_DAILINK_DEF(idisp3_pin,
367*4882a593Smuzhiyun DAILINK_COMP_ARRAY(COMP_CPU("iDisp3 Pin")));
368*4882a593Smuzhiyun SND_SOC_DAILINK_DEF(idisp3_codec,
369*4882a593Smuzhiyun DAILINK_COMP_ARRAY(COMP_CODEC("ehdaudio0D2", "intel-hdmi-hifi3")));
370*4882a593Smuzhiyun
371*4882a593Smuzhiyun SND_SOC_DAILINK_DEF(platform,
372*4882a593Smuzhiyun DAILINK_COMP_ARRAY(COMP_PLATFORM("0000:00:0e.0")));
373*4882a593Smuzhiyun
374*4882a593Smuzhiyun /* geminilake digital audio interface glue - connects codec <--> CPU */
375*4882a593Smuzhiyun static struct snd_soc_dai_link geminilake_dais[] = {
376*4882a593Smuzhiyun /* Front End DAI links */
377*4882a593Smuzhiyun [GLK_DPCM_AUDIO_PB] = {
378*4882a593Smuzhiyun .name = "Glk Audio Port",
379*4882a593Smuzhiyun .stream_name = "Audio",
380*4882a593Smuzhiyun .dynamic = 1,
381*4882a593Smuzhiyun .nonatomic = 1,
382*4882a593Smuzhiyun .init = geminilake_rt5682_fe_init,
383*4882a593Smuzhiyun .trigger = {
384*4882a593Smuzhiyun SND_SOC_DPCM_TRIGGER_POST, SND_SOC_DPCM_TRIGGER_POST},
385*4882a593Smuzhiyun .dpcm_playback = 1,
386*4882a593Smuzhiyun SND_SOC_DAILINK_REG(system, dummy, platform),
387*4882a593Smuzhiyun },
388*4882a593Smuzhiyun [GLK_DPCM_AUDIO_CP] = {
389*4882a593Smuzhiyun .name = "Glk Audio Capture Port",
390*4882a593Smuzhiyun .stream_name = "Audio Record",
391*4882a593Smuzhiyun .dynamic = 1,
392*4882a593Smuzhiyun .nonatomic = 1,
393*4882a593Smuzhiyun .trigger = {
394*4882a593Smuzhiyun SND_SOC_DPCM_TRIGGER_POST, SND_SOC_DPCM_TRIGGER_POST},
395*4882a593Smuzhiyun .dpcm_capture = 1,
396*4882a593Smuzhiyun SND_SOC_DAILINK_REG(system, dummy, platform),
397*4882a593Smuzhiyun },
398*4882a593Smuzhiyun [GLK_DPCM_AUDIO_HS_PB] = {
399*4882a593Smuzhiyun .name = "Glk Audio Headset Playback",
400*4882a593Smuzhiyun .stream_name = "Headset Audio",
401*4882a593Smuzhiyun .dpcm_playback = 1,
402*4882a593Smuzhiyun .nonatomic = 1,
403*4882a593Smuzhiyun .dynamic = 1,
404*4882a593Smuzhiyun SND_SOC_DAILINK_REG(system2, dummy, platform),
405*4882a593Smuzhiyun },
406*4882a593Smuzhiyun [GLK_DPCM_AUDIO_ECHO_REF_CP] = {
407*4882a593Smuzhiyun .name = "Glk Audio Echo Reference cap",
408*4882a593Smuzhiyun .stream_name = "Echoreference Capture",
409*4882a593Smuzhiyun .init = NULL,
410*4882a593Smuzhiyun .dpcm_capture = 1,
411*4882a593Smuzhiyun .nonatomic = 1,
412*4882a593Smuzhiyun .dynamic = 1,
413*4882a593Smuzhiyun SND_SOC_DAILINK_REG(echoref, dummy, platform),
414*4882a593Smuzhiyun },
415*4882a593Smuzhiyun [GLK_DPCM_AUDIO_REF_CP] = {
416*4882a593Smuzhiyun .name = "Glk Audio Reference cap",
417*4882a593Smuzhiyun .stream_name = "Refcap",
418*4882a593Smuzhiyun .init = NULL,
419*4882a593Smuzhiyun .dpcm_capture = 1,
420*4882a593Smuzhiyun .nonatomic = 1,
421*4882a593Smuzhiyun .dynamic = 1,
422*4882a593Smuzhiyun .ops = &geminilake_refcap_ops,
423*4882a593Smuzhiyun SND_SOC_DAILINK_REG(reference, dummy, platform),
424*4882a593Smuzhiyun },
425*4882a593Smuzhiyun [GLK_DPCM_AUDIO_DMIC_CP] = {
426*4882a593Smuzhiyun .name = "Glk Audio DMIC cap",
427*4882a593Smuzhiyun .stream_name = "dmiccap",
428*4882a593Smuzhiyun .init = NULL,
429*4882a593Smuzhiyun .dpcm_capture = 1,
430*4882a593Smuzhiyun .nonatomic = 1,
431*4882a593Smuzhiyun .dynamic = 1,
432*4882a593Smuzhiyun .ops = &geminilake_dmic_ops,
433*4882a593Smuzhiyun SND_SOC_DAILINK_REG(dmic, dummy, platform),
434*4882a593Smuzhiyun },
435*4882a593Smuzhiyun [GLK_DPCM_AUDIO_HDMI1_PB] = {
436*4882a593Smuzhiyun .name = "Glk HDMI Port1",
437*4882a593Smuzhiyun .stream_name = "Hdmi1",
438*4882a593Smuzhiyun .dpcm_playback = 1,
439*4882a593Smuzhiyun .init = NULL,
440*4882a593Smuzhiyun .trigger = {
441*4882a593Smuzhiyun SND_SOC_DPCM_TRIGGER_POST, SND_SOC_DPCM_TRIGGER_POST},
442*4882a593Smuzhiyun .nonatomic = 1,
443*4882a593Smuzhiyun .dynamic = 1,
444*4882a593Smuzhiyun SND_SOC_DAILINK_REG(hdmi1, dummy, platform),
445*4882a593Smuzhiyun },
446*4882a593Smuzhiyun [GLK_DPCM_AUDIO_HDMI2_PB] = {
447*4882a593Smuzhiyun .name = "Glk HDMI Port2",
448*4882a593Smuzhiyun .stream_name = "Hdmi2",
449*4882a593Smuzhiyun .dpcm_playback = 1,
450*4882a593Smuzhiyun .init = NULL,
451*4882a593Smuzhiyun .trigger = {
452*4882a593Smuzhiyun SND_SOC_DPCM_TRIGGER_POST, SND_SOC_DPCM_TRIGGER_POST},
453*4882a593Smuzhiyun .nonatomic = 1,
454*4882a593Smuzhiyun .dynamic = 1,
455*4882a593Smuzhiyun SND_SOC_DAILINK_REG(hdmi2, dummy, platform),
456*4882a593Smuzhiyun },
457*4882a593Smuzhiyun [GLK_DPCM_AUDIO_HDMI3_PB] = {
458*4882a593Smuzhiyun .name = "Glk HDMI Port3",
459*4882a593Smuzhiyun .stream_name = "Hdmi3",
460*4882a593Smuzhiyun .trigger = {
461*4882a593Smuzhiyun SND_SOC_DPCM_TRIGGER_POST, SND_SOC_DPCM_TRIGGER_POST},
462*4882a593Smuzhiyun .dpcm_playback = 1,
463*4882a593Smuzhiyun .init = NULL,
464*4882a593Smuzhiyun .nonatomic = 1,
465*4882a593Smuzhiyun .dynamic = 1,
466*4882a593Smuzhiyun SND_SOC_DAILINK_REG(hdmi3, dummy, platform),
467*4882a593Smuzhiyun },
468*4882a593Smuzhiyun /* Back End DAI links */
469*4882a593Smuzhiyun {
470*4882a593Smuzhiyun /* SSP1 - Codec */
471*4882a593Smuzhiyun .name = "SSP1-Codec",
472*4882a593Smuzhiyun .id = 0,
473*4882a593Smuzhiyun .no_pcm = 1,
474*4882a593Smuzhiyun .dai_fmt = SND_SOC_DAIFMT_I2S |
475*4882a593Smuzhiyun SND_SOC_DAIFMT_NB_NF |
476*4882a593Smuzhiyun SND_SOC_DAIFMT_CBS_CFS,
477*4882a593Smuzhiyun .ignore_pmdown_time = 1,
478*4882a593Smuzhiyun .be_hw_params_fixup = geminilake_ssp_fixup,
479*4882a593Smuzhiyun .dpcm_playback = 1,
480*4882a593Smuzhiyun SND_SOC_DAILINK_REG(ssp1_pin, ssp1_codec, platform),
481*4882a593Smuzhiyun },
482*4882a593Smuzhiyun {
483*4882a593Smuzhiyun /* SSP2 - Codec */
484*4882a593Smuzhiyun .name = "SSP2-Codec",
485*4882a593Smuzhiyun .id = 1,
486*4882a593Smuzhiyun .no_pcm = 1,
487*4882a593Smuzhiyun .init = geminilake_rt5682_codec_init,
488*4882a593Smuzhiyun .dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
489*4882a593Smuzhiyun SND_SOC_DAIFMT_CBS_CFS,
490*4882a593Smuzhiyun .ignore_pmdown_time = 1,
491*4882a593Smuzhiyun .be_hw_params_fixup = geminilake_ssp_fixup,
492*4882a593Smuzhiyun .ops = &geminilake_rt5682_ops,
493*4882a593Smuzhiyun .dpcm_playback = 1,
494*4882a593Smuzhiyun .dpcm_capture = 1,
495*4882a593Smuzhiyun SND_SOC_DAILINK_REG(ssp2_pin, ssp2_codec, platform),
496*4882a593Smuzhiyun },
497*4882a593Smuzhiyun {
498*4882a593Smuzhiyun .name = "dmic01",
499*4882a593Smuzhiyun .id = 2,
500*4882a593Smuzhiyun .ignore_suspend = 1,
501*4882a593Smuzhiyun .be_hw_params_fixup = geminilake_dmic_fixup,
502*4882a593Smuzhiyun .dpcm_capture = 1,
503*4882a593Smuzhiyun .no_pcm = 1,
504*4882a593Smuzhiyun SND_SOC_DAILINK_REG(dmic_pin, dmic_codec, platform),
505*4882a593Smuzhiyun },
506*4882a593Smuzhiyun {
507*4882a593Smuzhiyun .name = "iDisp1",
508*4882a593Smuzhiyun .id = 3,
509*4882a593Smuzhiyun .init = geminilake_hdmi_init,
510*4882a593Smuzhiyun .dpcm_playback = 1,
511*4882a593Smuzhiyun .no_pcm = 1,
512*4882a593Smuzhiyun SND_SOC_DAILINK_REG(idisp1_pin, idisp1_codec, platform),
513*4882a593Smuzhiyun },
514*4882a593Smuzhiyun {
515*4882a593Smuzhiyun .name = "iDisp2",
516*4882a593Smuzhiyun .id = 4,
517*4882a593Smuzhiyun .init = geminilake_hdmi_init,
518*4882a593Smuzhiyun .dpcm_playback = 1,
519*4882a593Smuzhiyun .no_pcm = 1,
520*4882a593Smuzhiyun SND_SOC_DAILINK_REG(idisp2_pin, idisp2_codec, platform),
521*4882a593Smuzhiyun },
522*4882a593Smuzhiyun {
523*4882a593Smuzhiyun .name = "iDisp3",
524*4882a593Smuzhiyun .id = 5,
525*4882a593Smuzhiyun .init = geminilake_hdmi_init,
526*4882a593Smuzhiyun .dpcm_playback = 1,
527*4882a593Smuzhiyun .no_pcm = 1,
528*4882a593Smuzhiyun SND_SOC_DAILINK_REG(idisp3_pin, idisp3_codec, platform),
529*4882a593Smuzhiyun },
530*4882a593Smuzhiyun };
531*4882a593Smuzhiyun
glk_card_late_probe(struct snd_soc_card * card)532*4882a593Smuzhiyun static int glk_card_late_probe(struct snd_soc_card *card)
533*4882a593Smuzhiyun {
534*4882a593Smuzhiyun struct glk_card_private *ctx = snd_soc_card_get_drvdata(card);
535*4882a593Smuzhiyun struct snd_soc_component *component = NULL;
536*4882a593Smuzhiyun char jack_name[NAME_SIZE];
537*4882a593Smuzhiyun struct glk_hdmi_pcm *pcm;
538*4882a593Smuzhiyun int err;
539*4882a593Smuzhiyun int i = 0;
540*4882a593Smuzhiyun
541*4882a593Smuzhiyun if (list_empty(&ctx->hdmi_pcm_list))
542*4882a593Smuzhiyun return -EINVAL;
543*4882a593Smuzhiyun
544*4882a593Smuzhiyun if (ctx->common_hdmi_codec_drv) {
545*4882a593Smuzhiyun pcm = list_first_entry(&ctx->hdmi_pcm_list, struct glk_hdmi_pcm,
546*4882a593Smuzhiyun head);
547*4882a593Smuzhiyun component = pcm->codec_dai->component;
548*4882a593Smuzhiyun return hda_dsp_hdmi_build_controls(card, component);
549*4882a593Smuzhiyun }
550*4882a593Smuzhiyun
551*4882a593Smuzhiyun list_for_each_entry(pcm, &ctx->hdmi_pcm_list, head) {
552*4882a593Smuzhiyun component = pcm->codec_dai->component;
553*4882a593Smuzhiyun snprintf(jack_name, sizeof(jack_name),
554*4882a593Smuzhiyun "HDMI/DP, pcm=%d Jack", pcm->device);
555*4882a593Smuzhiyun err = snd_soc_card_jack_new(card, jack_name,
556*4882a593Smuzhiyun SND_JACK_AVOUT, &geminilake_hdmi[i],
557*4882a593Smuzhiyun NULL, 0);
558*4882a593Smuzhiyun
559*4882a593Smuzhiyun if (err)
560*4882a593Smuzhiyun return err;
561*4882a593Smuzhiyun
562*4882a593Smuzhiyun err = hdac_hdmi_jack_init(pcm->codec_dai, pcm->device,
563*4882a593Smuzhiyun &geminilake_hdmi[i]);
564*4882a593Smuzhiyun if (err < 0)
565*4882a593Smuzhiyun return err;
566*4882a593Smuzhiyun
567*4882a593Smuzhiyun i++;
568*4882a593Smuzhiyun }
569*4882a593Smuzhiyun
570*4882a593Smuzhiyun return hdac_hdmi_jack_port_init(component, &card->dapm);
571*4882a593Smuzhiyun }
572*4882a593Smuzhiyun
573*4882a593Smuzhiyun /* geminilake audio machine driver for SPT + RT5682 */
574*4882a593Smuzhiyun static struct snd_soc_card glk_audio_card_rt5682_m98357a = {
575*4882a593Smuzhiyun .name = "glkrt5682max",
576*4882a593Smuzhiyun .owner = THIS_MODULE,
577*4882a593Smuzhiyun .dai_link = geminilake_dais,
578*4882a593Smuzhiyun .num_links = ARRAY_SIZE(geminilake_dais),
579*4882a593Smuzhiyun .controls = geminilake_controls,
580*4882a593Smuzhiyun .num_controls = ARRAY_SIZE(geminilake_controls),
581*4882a593Smuzhiyun .dapm_widgets = geminilake_widgets,
582*4882a593Smuzhiyun .num_dapm_widgets = ARRAY_SIZE(geminilake_widgets),
583*4882a593Smuzhiyun .dapm_routes = geminilake_map,
584*4882a593Smuzhiyun .num_dapm_routes = ARRAY_SIZE(geminilake_map),
585*4882a593Smuzhiyun .fully_routed = true,
586*4882a593Smuzhiyun .late_probe = glk_card_late_probe,
587*4882a593Smuzhiyun };
588*4882a593Smuzhiyun
geminilake_audio_probe(struct platform_device * pdev)589*4882a593Smuzhiyun static int geminilake_audio_probe(struct platform_device *pdev)
590*4882a593Smuzhiyun {
591*4882a593Smuzhiyun struct glk_card_private *ctx;
592*4882a593Smuzhiyun struct snd_soc_acpi_mach *mach;
593*4882a593Smuzhiyun const char *platform_name;
594*4882a593Smuzhiyun struct snd_soc_card *card;
595*4882a593Smuzhiyun int ret;
596*4882a593Smuzhiyun
597*4882a593Smuzhiyun ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL);
598*4882a593Smuzhiyun if (!ctx)
599*4882a593Smuzhiyun return -ENOMEM;
600*4882a593Smuzhiyun
601*4882a593Smuzhiyun INIT_LIST_HEAD(&ctx->hdmi_pcm_list);
602*4882a593Smuzhiyun
603*4882a593Smuzhiyun card = &glk_audio_card_rt5682_m98357a;
604*4882a593Smuzhiyun card->dev = &pdev->dev;
605*4882a593Smuzhiyun snd_soc_card_set_drvdata(card, ctx);
606*4882a593Smuzhiyun
607*4882a593Smuzhiyun /* override plaform name, if required */
608*4882a593Smuzhiyun mach = pdev->dev.platform_data;
609*4882a593Smuzhiyun platform_name = mach->mach_params.platform;
610*4882a593Smuzhiyun
611*4882a593Smuzhiyun ret = snd_soc_fixup_dai_links_platform_name(card, platform_name);
612*4882a593Smuzhiyun if (ret)
613*4882a593Smuzhiyun return ret;
614*4882a593Smuzhiyun
615*4882a593Smuzhiyun ctx->common_hdmi_codec_drv = mach->mach_params.common_hdmi_codec_drv;
616*4882a593Smuzhiyun
617*4882a593Smuzhiyun return devm_snd_soc_register_card(&pdev->dev, card);
618*4882a593Smuzhiyun }
619*4882a593Smuzhiyun
620*4882a593Smuzhiyun static const struct platform_device_id glk_board_ids[] = {
621*4882a593Smuzhiyun {
622*4882a593Smuzhiyun .name = "glk_rt5682_max98357a",
623*4882a593Smuzhiyun .driver_data =
624*4882a593Smuzhiyun (kernel_ulong_t)&glk_audio_card_rt5682_m98357a,
625*4882a593Smuzhiyun },
626*4882a593Smuzhiyun { }
627*4882a593Smuzhiyun };
628*4882a593Smuzhiyun
629*4882a593Smuzhiyun static struct platform_driver geminilake_audio = {
630*4882a593Smuzhiyun .probe = geminilake_audio_probe,
631*4882a593Smuzhiyun .driver = {
632*4882a593Smuzhiyun .name = "glk_rt5682_max98357a",
633*4882a593Smuzhiyun .pm = &snd_soc_pm_ops,
634*4882a593Smuzhiyun },
635*4882a593Smuzhiyun .id_table = glk_board_ids,
636*4882a593Smuzhiyun };
637*4882a593Smuzhiyun module_platform_driver(geminilake_audio)
638*4882a593Smuzhiyun
639*4882a593Smuzhiyun /* Module information */
640*4882a593Smuzhiyun MODULE_DESCRIPTION("Geminilake Audio Machine driver-RT5682 & MAX98357A in I2S mode");
641*4882a593Smuzhiyun MODULE_AUTHOR("Naveen Manohar <naveen.m@intel.com>");
642*4882a593Smuzhiyun MODULE_AUTHOR("Harsha Priya <harshapriya.n@intel.com>");
643*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
644*4882a593Smuzhiyun MODULE_ALIAS("platform:glk_rt5682_max98357a");
645