1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * IMG SPDIF output controller driver
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2015 Imagination Technologies Ltd.
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Author: Damien Horsley <Damien.Horsley@imgtec.com>
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <linux/clk.h>
11*4882a593Smuzhiyun #include <linux/init.h>
12*4882a593Smuzhiyun #include <linux/kernel.h>
13*4882a593Smuzhiyun #include <linux/module.h>
14*4882a593Smuzhiyun #include <linux/of.h>
15*4882a593Smuzhiyun #include <linux/platform_device.h>
16*4882a593Smuzhiyun #include <linux/pm_runtime.h>
17*4882a593Smuzhiyun #include <linux/reset.h>
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun #include <sound/core.h>
20*4882a593Smuzhiyun #include <sound/dmaengine_pcm.h>
21*4882a593Smuzhiyun #include <sound/initval.h>
22*4882a593Smuzhiyun #include <sound/pcm.h>
23*4882a593Smuzhiyun #include <sound/pcm_params.h>
24*4882a593Smuzhiyun #include <sound/soc.h>
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun #define IMG_SPDIF_OUT_TX_FIFO 0x0
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun #define IMG_SPDIF_OUT_CTL 0x4
29*4882a593Smuzhiyun #define IMG_SPDIF_OUT_CTL_FS_MASK BIT(4)
30*4882a593Smuzhiyun #define IMG_SPDIF_OUT_CTL_CLK_MASK BIT(2)
31*4882a593Smuzhiyun #define IMG_SPDIF_OUT_CTL_SRT_MASK BIT(0)
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun #define IMG_SPDIF_OUT_CSL 0x14
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun #define IMG_SPDIF_OUT_CSH_UV 0x18
36*4882a593Smuzhiyun #define IMG_SPDIF_OUT_CSH_UV_CSH_SHIFT 0
37*4882a593Smuzhiyun #define IMG_SPDIF_OUT_CSH_UV_CSH_MASK 0xff
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun struct img_spdif_out {
40*4882a593Smuzhiyun spinlock_t lock;
41*4882a593Smuzhiyun void __iomem *base;
42*4882a593Smuzhiyun struct clk *clk_sys;
43*4882a593Smuzhiyun struct clk *clk_ref;
44*4882a593Smuzhiyun struct snd_dmaengine_dai_dma_data dma_data;
45*4882a593Smuzhiyun struct device *dev;
46*4882a593Smuzhiyun struct reset_control *rst;
47*4882a593Smuzhiyun u32 suspend_ctl;
48*4882a593Smuzhiyun u32 suspend_csl;
49*4882a593Smuzhiyun u32 suspend_csh;
50*4882a593Smuzhiyun };
51*4882a593Smuzhiyun
img_spdif_out_runtime_suspend(struct device * dev)52*4882a593Smuzhiyun static int img_spdif_out_runtime_suspend(struct device *dev)
53*4882a593Smuzhiyun {
54*4882a593Smuzhiyun struct img_spdif_out *spdif = dev_get_drvdata(dev);
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun clk_disable_unprepare(spdif->clk_ref);
57*4882a593Smuzhiyun clk_disable_unprepare(spdif->clk_sys);
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun return 0;
60*4882a593Smuzhiyun }
61*4882a593Smuzhiyun
img_spdif_out_runtime_resume(struct device * dev)62*4882a593Smuzhiyun static int img_spdif_out_runtime_resume(struct device *dev)
63*4882a593Smuzhiyun {
64*4882a593Smuzhiyun struct img_spdif_out *spdif = dev_get_drvdata(dev);
65*4882a593Smuzhiyun int ret;
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun ret = clk_prepare_enable(spdif->clk_sys);
68*4882a593Smuzhiyun if (ret) {
69*4882a593Smuzhiyun dev_err(dev, "clk_enable failed: %d\n", ret);
70*4882a593Smuzhiyun return ret;
71*4882a593Smuzhiyun }
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun ret = clk_prepare_enable(spdif->clk_ref);
74*4882a593Smuzhiyun if (ret) {
75*4882a593Smuzhiyun dev_err(dev, "clk_enable failed: %d\n", ret);
76*4882a593Smuzhiyun clk_disable_unprepare(spdif->clk_sys);
77*4882a593Smuzhiyun return ret;
78*4882a593Smuzhiyun }
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun return 0;
81*4882a593Smuzhiyun }
82*4882a593Smuzhiyun
img_spdif_out_writel(struct img_spdif_out * spdif,u32 val,u32 reg)83*4882a593Smuzhiyun static inline void img_spdif_out_writel(struct img_spdif_out *spdif, u32 val,
84*4882a593Smuzhiyun u32 reg)
85*4882a593Smuzhiyun {
86*4882a593Smuzhiyun writel(val, spdif->base + reg);
87*4882a593Smuzhiyun }
88*4882a593Smuzhiyun
img_spdif_out_readl(struct img_spdif_out * spdif,u32 reg)89*4882a593Smuzhiyun static inline u32 img_spdif_out_readl(struct img_spdif_out *spdif, u32 reg)
90*4882a593Smuzhiyun {
91*4882a593Smuzhiyun return readl(spdif->base + reg);
92*4882a593Smuzhiyun }
93*4882a593Smuzhiyun
img_spdif_out_reset(struct img_spdif_out * spdif)94*4882a593Smuzhiyun static void img_spdif_out_reset(struct img_spdif_out *spdif)
95*4882a593Smuzhiyun {
96*4882a593Smuzhiyun u32 ctl, status_low, status_high;
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun ctl = img_spdif_out_readl(spdif, IMG_SPDIF_OUT_CTL) &
99*4882a593Smuzhiyun ~IMG_SPDIF_OUT_CTL_SRT_MASK;
100*4882a593Smuzhiyun status_low = img_spdif_out_readl(spdif, IMG_SPDIF_OUT_CSL);
101*4882a593Smuzhiyun status_high = img_spdif_out_readl(spdif, IMG_SPDIF_OUT_CSH_UV);
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun reset_control_assert(spdif->rst);
104*4882a593Smuzhiyun reset_control_deassert(spdif->rst);
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun img_spdif_out_writel(spdif, ctl, IMG_SPDIF_OUT_CTL);
107*4882a593Smuzhiyun img_spdif_out_writel(spdif, status_low, IMG_SPDIF_OUT_CSL);
108*4882a593Smuzhiyun img_spdif_out_writel(spdif, status_high, IMG_SPDIF_OUT_CSH_UV);
109*4882a593Smuzhiyun }
110*4882a593Smuzhiyun
img_spdif_out_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)111*4882a593Smuzhiyun static int img_spdif_out_info(struct snd_kcontrol *kcontrol,
112*4882a593Smuzhiyun struct snd_ctl_elem_info *uinfo)
113*4882a593Smuzhiyun {
114*4882a593Smuzhiyun uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
115*4882a593Smuzhiyun uinfo->count = 1;
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun return 0;
118*4882a593Smuzhiyun }
119*4882a593Smuzhiyun
img_spdif_out_get_status_mask(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)120*4882a593Smuzhiyun static int img_spdif_out_get_status_mask(struct snd_kcontrol *kcontrol,
121*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
122*4882a593Smuzhiyun {
123*4882a593Smuzhiyun ucontrol->value.iec958.status[0] = 0xff;
124*4882a593Smuzhiyun ucontrol->value.iec958.status[1] = 0xff;
125*4882a593Smuzhiyun ucontrol->value.iec958.status[2] = 0xff;
126*4882a593Smuzhiyun ucontrol->value.iec958.status[3] = 0xff;
127*4882a593Smuzhiyun ucontrol->value.iec958.status[4] = 0xff;
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun return 0;
130*4882a593Smuzhiyun }
131*4882a593Smuzhiyun
img_spdif_out_get_status(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)132*4882a593Smuzhiyun static int img_spdif_out_get_status(struct snd_kcontrol *kcontrol,
133*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
134*4882a593Smuzhiyun {
135*4882a593Smuzhiyun struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
136*4882a593Smuzhiyun struct img_spdif_out *spdif = snd_soc_dai_get_drvdata(cpu_dai);
137*4882a593Smuzhiyun u32 reg;
138*4882a593Smuzhiyun unsigned long flags;
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun spin_lock_irqsave(&spdif->lock, flags);
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun reg = img_spdif_out_readl(spdif, IMG_SPDIF_OUT_CSL);
143*4882a593Smuzhiyun ucontrol->value.iec958.status[0] = reg & 0xff;
144*4882a593Smuzhiyun ucontrol->value.iec958.status[1] = (reg >> 8) & 0xff;
145*4882a593Smuzhiyun ucontrol->value.iec958.status[2] = (reg >> 16) & 0xff;
146*4882a593Smuzhiyun ucontrol->value.iec958.status[3] = (reg >> 24) & 0xff;
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun reg = img_spdif_out_readl(spdif, IMG_SPDIF_OUT_CSH_UV);
149*4882a593Smuzhiyun ucontrol->value.iec958.status[4] =
150*4882a593Smuzhiyun (reg & IMG_SPDIF_OUT_CSH_UV_CSH_MASK) >>
151*4882a593Smuzhiyun IMG_SPDIF_OUT_CSH_UV_CSH_SHIFT;
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun spin_unlock_irqrestore(&spdif->lock, flags);
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun return 0;
156*4882a593Smuzhiyun }
157*4882a593Smuzhiyun
img_spdif_out_set_status(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)158*4882a593Smuzhiyun static int img_spdif_out_set_status(struct snd_kcontrol *kcontrol,
159*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
160*4882a593Smuzhiyun {
161*4882a593Smuzhiyun struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
162*4882a593Smuzhiyun struct img_spdif_out *spdif = snd_soc_dai_get_drvdata(cpu_dai);
163*4882a593Smuzhiyun u32 reg;
164*4882a593Smuzhiyun unsigned long flags;
165*4882a593Smuzhiyun
166*4882a593Smuzhiyun reg = ((u32)ucontrol->value.iec958.status[3] << 24);
167*4882a593Smuzhiyun reg |= ((u32)ucontrol->value.iec958.status[2] << 16);
168*4882a593Smuzhiyun reg |= ((u32)ucontrol->value.iec958.status[1] << 8);
169*4882a593Smuzhiyun reg |= (u32)ucontrol->value.iec958.status[0];
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun spin_lock_irqsave(&spdif->lock, flags);
172*4882a593Smuzhiyun
173*4882a593Smuzhiyun img_spdif_out_writel(spdif, reg, IMG_SPDIF_OUT_CSL);
174*4882a593Smuzhiyun
175*4882a593Smuzhiyun reg = img_spdif_out_readl(spdif, IMG_SPDIF_OUT_CSH_UV);
176*4882a593Smuzhiyun reg &= ~IMG_SPDIF_OUT_CSH_UV_CSH_MASK;
177*4882a593Smuzhiyun reg |= (u32)ucontrol->value.iec958.status[4] <<
178*4882a593Smuzhiyun IMG_SPDIF_OUT_CSH_UV_CSH_SHIFT;
179*4882a593Smuzhiyun img_spdif_out_writel(spdif, reg, IMG_SPDIF_OUT_CSH_UV);
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun spin_unlock_irqrestore(&spdif->lock, flags);
182*4882a593Smuzhiyun
183*4882a593Smuzhiyun return 0;
184*4882a593Smuzhiyun }
185*4882a593Smuzhiyun
186*4882a593Smuzhiyun static struct snd_kcontrol_new img_spdif_out_controls[] = {
187*4882a593Smuzhiyun {
188*4882a593Smuzhiyun .access = SNDRV_CTL_ELEM_ACCESS_READ,
189*4882a593Smuzhiyun .iface = SNDRV_CTL_ELEM_IFACE_PCM,
190*4882a593Smuzhiyun .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, MASK),
191*4882a593Smuzhiyun .info = img_spdif_out_info,
192*4882a593Smuzhiyun .get = img_spdif_out_get_status_mask
193*4882a593Smuzhiyun },
194*4882a593Smuzhiyun {
195*4882a593Smuzhiyun .iface = SNDRV_CTL_ELEM_IFACE_PCM,
196*4882a593Smuzhiyun .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
197*4882a593Smuzhiyun .info = img_spdif_out_info,
198*4882a593Smuzhiyun .get = img_spdif_out_get_status,
199*4882a593Smuzhiyun .put = img_spdif_out_set_status
200*4882a593Smuzhiyun }
201*4882a593Smuzhiyun };
202*4882a593Smuzhiyun
img_spdif_out_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * dai)203*4882a593Smuzhiyun static int img_spdif_out_trigger(struct snd_pcm_substream *substream, int cmd,
204*4882a593Smuzhiyun struct snd_soc_dai *dai)
205*4882a593Smuzhiyun {
206*4882a593Smuzhiyun struct img_spdif_out *spdif = snd_soc_dai_get_drvdata(dai);
207*4882a593Smuzhiyun u32 reg;
208*4882a593Smuzhiyun unsigned long flags;
209*4882a593Smuzhiyun
210*4882a593Smuzhiyun switch (cmd) {
211*4882a593Smuzhiyun case SNDRV_PCM_TRIGGER_START:
212*4882a593Smuzhiyun case SNDRV_PCM_TRIGGER_RESUME:
213*4882a593Smuzhiyun case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
214*4882a593Smuzhiyun reg = img_spdif_out_readl(spdif, IMG_SPDIF_OUT_CTL);
215*4882a593Smuzhiyun reg |= IMG_SPDIF_OUT_CTL_SRT_MASK;
216*4882a593Smuzhiyun img_spdif_out_writel(spdif, reg, IMG_SPDIF_OUT_CTL);
217*4882a593Smuzhiyun break;
218*4882a593Smuzhiyun case SNDRV_PCM_TRIGGER_STOP:
219*4882a593Smuzhiyun case SNDRV_PCM_TRIGGER_SUSPEND:
220*4882a593Smuzhiyun case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
221*4882a593Smuzhiyun spin_lock_irqsave(&spdif->lock, flags);
222*4882a593Smuzhiyun img_spdif_out_reset(spdif);
223*4882a593Smuzhiyun spin_unlock_irqrestore(&spdif->lock, flags);
224*4882a593Smuzhiyun break;
225*4882a593Smuzhiyun default:
226*4882a593Smuzhiyun return -EINVAL;
227*4882a593Smuzhiyun }
228*4882a593Smuzhiyun
229*4882a593Smuzhiyun return 0;
230*4882a593Smuzhiyun }
231*4882a593Smuzhiyun
img_spdif_out_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)232*4882a593Smuzhiyun static int img_spdif_out_hw_params(struct snd_pcm_substream *substream,
233*4882a593Smuzhiyun struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
234*4882a593Smuzhiyun {
235*4882a593Smuzhiyun struct img_spdif_out *spdif = snd_soc_dai_get_drvdata(dai);
236*4882a593Smuzhiyun unsigned int channels;
237*4882a593Smuzhiyun long pre_div_a, pre_div_b, diff_a, diff_b, rate, clk_rate;
238*4882a593Smuzhiyun u32 reg;
239*4882a593Smuzhiyun snd_pcm_format_t format;
240*4882a593Smuzhiyun
241*4882a593Smuzhiyun rate = params_rate(params);
242*4882a593Smuzhiyun format = params_format(params);
243*4882a593Smuzhiyun channels = params_channels(params);
244*4882a593Smuzhiyun
245*4882a593Smuzhiyun dev_dbg(spdif->dev, "hw_params rate %ld channels %u format %u\n",
246*4882a593Smuzhiyun rate, channels, format);
247*4882a593Smuzhiyun
248*4882a593Smuzhiyun if (format != SNDRV_PCM_FORMAT_S32_LE)
249*4882a593Smuzhiyun return -EINVAL;
250*4882a593Smuzhiyun
251*4882a593Smuzhiyun if (channels != 2)
252*4882a593Smuzhiyun return -EINVAL;
253*4882a593Smuzhiyun
254*4882a593Smuzhiyun pre_div_a = clk_round_rate(spdif->clk_ref, rate * 256);
255*4882a593Smuzhiyun if (pre_div_a < 0)
256*4882a593Smuzhiyun return pre_div_a;
257*4882a593Smuzhiyun pre_div_b = clk_round_rate(spdif->clk_ref, rate * 384);
258*4882a593Smuzhiyun if (pre_div_b < 0)
259*4882a593Smuzhiyun return pre_div_b;
260*4882a593Smuzhiyun
261*4882a593Smuzhiyun diff_a = abs((pre_div_a / 256) - rate);
262*4882a593Smuzhiyun diff_b = abs((pre_div_b / 384) - rate);
263*4882a593Smuzhiyun
264*4882a593Smuzhiyun /* If diffs are equal, use lower clock rate */
265*4882a593Smuzhiyun if (diff_a > diff_b)
266*4882a593Smuzhiyun clk_set_rate(spdif->clk_ref, pre_div_b);
267*4882a593Smuzhiyun else
268*4882a593Smuzhiyun clk_set_rate(spdif->clk_ref, pre_div_a);
269*4882a593Smuzhiyun
270*4882a593Smuzhiyun /*
271*4882a593Smuzhiyun * Another driver (eg machine driver) may have rejected the above
272*4882a593Smuzhiyun * change. Get the current rate and set the register bit according to
273*4882a593Smuzhiyun * the new min diff
274*4882a593Smuzhiyun */
275*4882a593Smuzhiyun clk_rate = clk_get_rate(spdif->clk_ref);
276*4882a593Smuzhiyun
277*4882a593Smuzhiyun diff_a = abs((clk_rate / 256) - rate);
278*4882a593Smuzhiyun diff_b = abs((clk_rate / 384) - rate);
279*4882a593Smuzhiyun
280*4882a593Smuzhiyun reg = img_spdif_out_readl(spdif, IMG_SPDIF_OUT_CTL);
281*4882a593Smuzhiyun if (diff_a <= diff_b)
282*4882a593Smuzhiyun reg &= ~IMG_SPDIF_OUT_CTL_CLK_MASK;
283*4882a593Smuzhiyun else
284*4882a593Smuzhiyun reg |= IMG_SPDIF_OUT_CTL_CLK_MASK;
285*4882a593Smuzhiyun img_spdif_out_writel(spdif, reg, IMG_SPDIF_OUT_CTL);
286*4882a593Smuzhiyun
287*4882a593Smuzhiyun return 0;
288*4882a593Smuzhiyun }
289*4882a593Smuzhiyun
290*4882a593Smuzhiyun static const struct snd_soc_dai_ops img_spdif_out_dai_ops = {
291*4882a593Smuzhiyun .trigger = img_spdif_out_trigger,
292*4882a593Smuzhiyun .hw_params = img_spdif_out_hw_params
293*4882a593Smuzhiyun };
294*4882a593Smuzhiyun
img_spdif_out_dai_probe(struct snd_soc_dai * dai)295*4882a593Smuzhiyun static int img_spdif_out_dai_probe(struct snd_soc_dai *dai)
296*4882a593Smuzhiyun {
297*4882a593Smuzhiyun struct img_spdif_out *spdif = snd_soc_dai_get_drvdata(dai);
298*4882a593Smuzhiyun
299*4882a593Smuzhiyun snd_soc_dai_init_dma_data(dai, &spdif->dma_data, NULL);
300*4882a593Smuzhiyun
301*4882a593Smuzhiyun snd_soc_add_dai_controls(dai, img_spdif_out_controls,
302*4882a593Smuzhiyun ARRAY_SIZE(img_spdif_out_controls));
303*4882a593Smuzhiyun
304*4882a593Smuzhiyun return 0;
305*4882a593Smuzhiyun }
306*4882a593Smuzhiyun
307*4882a593Smuzhiyun static struct snd_soc_dai_driver img_spdif_out_dai = {
308*4882a593Smuzhiyun .probe = img_spdif_out_dai_probe,
309*4882a593Smuzhiyun .playback = {
310*4882a593Smuzhiyun .channels_min = 2,
311*4882a593Smuzhiyun .channels_max = 2,
312*4882a593Smuzhiyun .rates = SNDRV_PCM_RATE_8000_192000,
313*4882a593Smuzhiyun .formats = SNDRV_PCM_FMTBIT_S32_LE
314*4882a593Smuzhiyun },
315*4882a593Smuzhiyun .ops = &img_spdif_out_dai_ops
316*4882a593Smuzhiyun };
317*4882a593Smuzhiyun
318*4882a593Smuzhiyun static const struct snd_soc_component_driver img_spdif_out_component = {
319*4882a593Smuzhiyun .name = "img-spdif-out"
320*4882a593Smuzhiyun };
321*4882a593Smuzhiyun
img_spdif_out_probe(struct platform_device * pdev)322*4882a593Smuzhiyun static int img_spdif_out_probe(struct platform_device *pdev)
323*4882a593Smuzhiyun {
324*4882a593Smuzhiyun struct img_spdif_out *spdif;
325*4882a593Smuzhiyun struct resource *res;
326*4882a593Smuzhiyun void __iomem *base;
327*4882a593Smuzhiyun int ret;
328*4882a593Smuzhiyun struct device *dev = &pdev->dev;
329*4882a593Smuzhiyun
330*4882a593Smuzhiyun spdif = devm_kzalloc(&pdev->dev, sizeof(*spdif), GFP_KERNEL);
331*4882a593Smuzhiyun if (!spdif)
332*4882a593Smuzhiyun return -ENOMEM;
333*4882a593Smuzhiyun
334*4882a593Smuzhiyun platform_set_drvdata(pdev, spdif);
335*4882a593Smuzhiyun
336*4882a593Smuzhiyun spdif->dev = &pdev->dev;
337*4882a593Smuzhiyun
338*4882a593Smuzhiyun res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
339*4882a593Smuzhiyun base = devm_ioremap_resource(&pdev->dev, res);
340*4882a593Smuzhiyun if (IS_ERR(base))
341*4882a593Smuzhiyun return PTR_ERR(base);
342*4882a593Smuzhiyun
343*4882a593Smuzhiyun spdif->base = base;
344*4882a593Smuzhiyun
345*4882a593Smuzhiyun spdif->rst = devm_reset_control_get_exclusive(&pdev->dev, "rst");
346*4882a593Smuzhiyun if (IS_ERR(spdif->rst)) {
347*4882a593Smuzhiyun if (PTR_ERR(spdif->rst) != -EPROBE_DEFER)
348*4882a593Smuzhiyun dev_err(&pdev->dev, "No top level reset found\n");
349*4882a593Smuzhiyun return PTR_ERR(spdif->rst);
350*4882a593Smuzhiyun }
351*4882a593Smuzhiyun
352*4882a593Smuzhiyun spdif->clk_sys = devm_clk_get(&pdev->dev, "sys");
353*4882a593Smuzhiyun if (IS_ERR(spdif->clk_sys)) {
354*4882a593Smuzhiyun if (PTR_ERR(spdif->clk_sys) != -EPROBE_DEFER)
355*4882a593Smuzhiyun dev_err(dev, "Failed to acquire clock 'sys'\n");
356*4882a593Smuzhiyun return PTR_ERR(spdif->clk_sys);
357*4882a593Smuzhiyun }
358*4882a593Smuzhiyun
359*4882a593Smuzhiyun spdif->clk_ref = devm_clk_get(&pdev->dev, "ref");
360*4882a593Smuzhiyun if (IS_ERR(spdif->clk_ref)) {
361*4882a593Smuzhiyun if (PTR_ERR(spdif->clk_ref) != -EPROBE_DEFER)
362*4882a593Smuzhiyun dev_err(dev, "Failed to acquire clock 'ref'\n");
363*4882a593Smuzhiyun return PTR_ERR(spdif->clk_ref);
364*4882a593Smuzhiyun }
365*4882a593Smuzhiyun
366*4882a593Smuzhiyun pm_runtime_enable(&pdev->dev);
367*4882a593Smuzhiyun if (!pm_runtime_enabled(&pdev->dev)) {
368*4882a593Smuzhiyun ret = img_spdif_out_runtime_resume(&pdev->dev);
369*4882a593Smuzhiyun if (ret)
370*4882a593Smuzhiyun goto err_pm_disable;
371*4882a593Smuzhiyun }
372*4882a593Smuzhiyun ret = pm_runtime_get_sync(&pdev->dev);
373*4882a593Smuzhiyun if (ret < 0) {
374*4882a593Smuzhiyun pm_runtime_put_noidle(&pdev->dev);
375*4882a593Smuzhiyun goto err_suspend;
376*4882a593Smuzhiyun }
377*4882a593Smuzhiyun
378*4882a593Smuzhiyun img_spdif_out_writel(spdif, IMG_SPDIF_OUT_CTL_FS_MASK,
379*4882a593Smuzhiyun IMG_SPDIF_OUT_CTL);
380*4882a593Smuzhiyun
381*4882a593Smuzhiyun img_spdif_out_reset(spdif);
382*4882a593Smuzhiyun pm_runtime_put(&pdev->dev);
383*4882a593Smuzhiyun
384*4882a593Smuzhiyun spin_lock_init(&spdif->lock);
385*4882a593Smuzhiyun
386*4882a593Smuzhiyun spdif->dma_data.addr = res->start + IMG_SPDIF_OUT_TX_FIFO;
387*4882a593Smuzhiyun spdif->dma_data.addr_width = 4;
388*4882a593Smuzhiyun spdif->dma_data.maxburst = 4;
389*4882a593Smuzhiyun
390*4882a593Smuzhiyun ret = devm_snd_soc_register_component(&pdev->dev,
391*4882a593Smuzhiyun &img_spdif_out_component,
392*4882a593Smuzhiyun &img_spdif_out_dai, 1);
393*4882a593Smuzhiyun if (ret)
394*4882a593Smuzhiyun goto err_suspend;
395*4882a593Smuzhiyun
396*4882a593Smuzhiyun ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
397*4882a593Smuzhiyun if (ret)
398*4882a593Smuzhiyun goto err_suspend;
399*4882a593Smuzhiyun
400*4882a593Smuzhiyun dev_dbg(&pdev->dev, "Probe successful\n");
401*4882a593Smuzhiyun
402*4882a593Smuzhiyun return 0;
403*4882a593Smuzhiyun
404*4882a593Smuzhiyun err_suspend:
405*4882a593Smuzhiyun if (!pm_runtime_status_suspended(&pdev->dev))
406*4882a593Smuzhiyun img_spdif_out_runtime_suspend(&pdev->dev);
407*4882a593Smuzhiyun err_pm_disable:
408*4882a593Smuzhiyun pm_runtime_disable(&pdev->dev);
409*4882a593Smuzhiyun
410*4882a593Smuzhiyun return ret;
411*4882a593Smuzhiyun }
412*4882a593Smuzhiyun
img_spdif_out_dev_remove(struct platform_device * pdev)413*4882a593Smuzhiyun static int img_spdif_out_dev_remove(struct platform_device *pdev)
414*4882a593Smuzhiyun {
415*4882a593Smuzhiyun pm_runtime_disable(&pdev->dev);
416*4882a593Smuzhiyun if (!pm_runtime_status_suspended(&pdev->dev))
417*4882a593Smuzhiyun img_spdif_out_runtime_suspend(&pdev->dev);
418*4882a593Smuzhiyun
419*4882a593Smuzhiyun return 0;
420*4882a593Smuzhiyun }
421*4882a593Smuzhiyun
422*4882a593Smuzhiyun #ifdef CONFIG_PM_SLEEP
img_spdif_out_suspend(struct device * dev)423*4882a593Smuzhiyun static int img_spdif_out_suspend(struct device *dev)
424*4882a593Smuzhiyun {
425*4882a593Smuzhiyun struct img_spdif_out *spdif = dev_get_drvdata(dev);
426*4882a593Smuzhiyun int ret;
427*4882a593Smuzhiyun
428*4882a593Smuzhiyun if (pm_runtime_status_suspended(dev)) {
429*4882a593Smuzhiyun ret = img_spdif_out_runtime_resume(dev);
430*4882a593Smuzhiyun if (ret)
431*4882a593Smuzhiyun return ret;
432*4882a593Smuzhiyun }
433*4882a593Smuzhiyun
434*4882a593Smuzhiyun spdif->suspend_ctl = img_spdif_out_readl(spdif, IMG_SPDIF_OUT_CTL);
435*4882a593Smuzhiyun spdif->suspend_csl = img_spdif_out_readl(spdif, IMG_SPDIF_OUT_CSL);
436*4882a593Smuzhiyun spdif->suspend_csh = img_spdif_out_readl(spdif, IMG_SPDIF_OUT_CSH_UV);
437*4882a593Smuzhiyun
438*4882a593Smuzhiyun img_spdif_out_runtime_suspend(dev);
439*4882a593Smuzhiyun
440*4882a593Smuzhiyun return 0;
441*4882a593Smuzhiyun }
442*4882a593Smuzhiyun
img_spdif_out_resume(struct device * dev)443*4882a593Smuzhiyun static int img_spdif_out_resume(struct device *dev)
444*4882a593Smuzhiyun {
445*4882a593Smuzhiyun struct img_spdif_out *spdif = dev_get_drvdata(dev);
446*4882a593Smuzhiyun int ret;
447*4882a593Smuzhiyun
448*4882a593Smuzhiyun ret = img_spdif_out_runtime_resume(dev);
449*4882a593Smuzhiyun if (ret)
450*4882a593Smuzhiyun return ret;
451*4882a593Smuzhiyun
452*4882a593Smuzhiyun img_spdif_out_writel(spdif, spdif->suspend_ctl, IMG_SPDIF_OUT_CTL);
453*4882a593Smuzhiyun img_spdif_out_writel(spdif, spdif->suspend_csl, IMG_SPDIF_OUT_CSL);
454*4882a593Smuzhiyun img_spdif_out_writel(spdif, spdif->suspend_csh, IMG_SPDIF_OUT_CSH_UV);
455*4882a593Smuzhiyun
456*4882a593Smuzhiyun if (pm_runtime_status_suspended(dev))
457*4882a593Smuzhiyun img_spdif_out_runtime_suspend(dev);
458*4882a593Smuzhiyun
459*4882a593Smuzhiyun return 0;
460*4882a593Smuzhiyun }
461*4882a593Smuzhiyun #endif
462*4882a593Smuzhiyun static const struct of_device_id img_spdif_out_of_match[] = {
463*4882a593Smuzhiyun { .compatible = "img,spdif-out" },
464*4882a593Smuzhiyun {}
465*4882a593Smuzhiyun };
466*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, img_spdif_out_of_match);
467*4882a593Smuzhiyun
468*4882a593Smuzhiyun static const struct dev_pm_ops img_spdif_out_pm_ops = {
469*4882a593Smuzhiyun SET_RUNTIME_PM_OPS(img_spdif_out_runtime_suspend,
470*4882a593Smuzhiyun img_spdif_out_runtime_resume, NULL)
471*4882a593Smuzhiyun SET_SYSTEM_SLEEP_PM_OPS(img_spdif_out_suspend, img_spdif_out_resume)
472*4882a593Smuzhiyun };
473*4882a593Smuzhiyun
474*4882a593Smuzhiyun static struct platform_driver img_spdif_out_driver = {
475*4882a593Smuzhiyun .driver = {
476*4882a593Smuzhiyun .name = "img-spdif-out",
477*4882a593Smuzhiyun .of_match_table = img_spdif_out_of_match,
478*4882a593Smuzhiyun .pm = &img_spdif_out_pm_ops
479*4882a593Smuzhiyun },
480*4882a593Smuzhiyun .probe = img_spdif_out_probe,
481*4882a593Smuzhiyun .remove = img_spdif_out_dev_remove
482*4882a593Smuzhiyun };
483*4882a593Smuzhiyun module_platform_driver(img_spdif_out_driver);
484*4882a593Smuzhiyun
485*4882a593Smuzhiyun MODULE_AUTHOR("Damien Horsley <Damien.Horsley@imgtec.com>");
486*4882a593Smuzhiyun MODULE_DESCRIPTION("IMG SPDIF Output driver");
487*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
488