1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ 2*4882a593Smuzhiyun * 3*4882a593Smuzhiyun * linux/sound/soc/hisilicon/hi3660-i2s.c 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * I2S IP driver for hi3660. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Copyright (c) 2001-2021, Huawei Tech. Co., Ltd. 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifndef _HI3660_I2S_H 12*4882a593Smuzhiyun #define _HI3660_I2S_H 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun enum hisi_bits { 15*4882a593Smuzhiyun HII2S_BITS_16, 16*4882a593Smuzhiyun HII2S_BITS_18, 17*4882a593Smuzhiyun HII2S_BITS_20, 18*4882a593Smuzhiyun HII2S_BITS_24, 19*4882a593Smuzhiyun }; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun enum hisi_i2s_rates { 22*4882a593Smuzhiyun HII2S_FS_RATE_8KHZ = 0, 23*4882a593Smuzhiyun HII2S_FS_RATE_16KHZ = 1, 24*4882a593Smuzhiyun HII2S_FS_RATE_32KHZ = 2, 25*4882a593Smuzhiyun HII2S_FS_RATE_48KHZ = 4, 26*4882a593Smuzhiyun HII2S_FS_RATE_96KHZ = 5, 27*4882a593Smuzhiyun HII2S_FS_RATE_192KHZ = 6, 28*4882a593Smuzhiyun }; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #define HI_ASP_CFG_R_RST_CTRLEN_REG 0x0 31*4882a593Smuzhiyun #define HI_ASP_CFG_R_RST_CTRLDIS_REG 0x4 32*4882a593Smuzhiyun #define HI_ASP_CFG_R_GATE_EN_REG 0xC 33*4882a593Smuzhiyun #define HI_ASP_CFG_R_GATE_DIS_REG 0x10 34*4882a593Smuzhiyun #define HI_ASP_CFG_R_GATE_CLKEN_REG 0x14 35*4882a593Smuzhiyun #define HI_ASP_CFG_R_GATE_CLKSTAT_REG 0x18 36*4882a593Smuzhiyun #define HI_ASP_CFG_R_GATE_CLKDIV_EN_REG 0x1C 37*4882a593Smuzhiyun #define HI_ASP_CFG_R_CLK1_DIV_REG 0x20 38*4882a593Smuzhiyun #define HI_ASP_CFG_R_CLK2_DIV_REG 0x24 39*4882a593Smuzhiyun #define HI_ASP_CFG_R_CLK3_DIV_REG 0x28 40*4882a593Smuzhiyun #define HI_ASP_CFG_R_CLK4_DIV_REG 0x2C 41*4882a593Smuzhiyun #define HI_ASP_CFG_R_CLK5_DIV_REG 0x30 42*4882a593Smuzhiyun #define HI_ASP_CFG_R_CLK6_DIV_REG 0x34 43*4882a593Smuzhiyun #define HI_ASP_CFG_R_CLK_SEL_REG 0x38 44*4882a593Smuzhiyun #define HI_ASP_CFG_R_SEC_REG 0x100 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun #define HI_ASP_SIO_VERSION_REG (0x3C) 48*4882a593Smuzhiyun #define HI_ASP_SIO_MODE_REG (0x40) 49*4882a593Smuzhiyun #define HI_ASP_SIO_INTSTATUS_REG (0x44) 50*4882a593Smuzhiyun #define HI_ASP_SIO_INTCLR_REG (0x48) 51*4882a593Smuzhiyun #define HI_ASP_SIO_I2S_LEFT_XD_REG (0x4C) 52*4882a593Smuzhiyun #define HI_ASP_SIO_I2S_RIGHT_XD_REG (0x50) 53*4882a593Smuzhiyun #define HI_ASP_SIO_I2S_LEFT_RD_REG (0x54) 54*4882a593Smuzhiyun #define HI_ASP_SIO_I2S_RIGHT_RD_REG (0x58) 55*4882a593Smuzhiyun #define HI_ASP_SIO_CT_SET_REG (0x5C) 56*4882a593Smuzhiyun #define HI_ASP_SIO_CT_CLR_REG (0x60) 57*4882a593Smuzhiyun #define HI_ASP_SIO_RX_STA_REG (0x68) 58*4882a593Smuzhiyun #define HI_ASP_SIO_TX_STA_REG (0x6C) 59*4882a593Smuzhiyun #define HI_ASP_SIO_DATA_WIDTH_SET_REG (0x78) 60*4882a593Smuzhiyun #define HI_ASP_SIO_I2S_START_POS_REG (0x7C) 61*4882a593Smuzhiyun #define HI_ASP_SIO_I2S_POS_FLAG_REG (0x80) 62*4882a593Smuzhiyun #define HI_ASP_SIO_SIGNED_EXT_REG (0x84) 63*4882a593Smuzhiyun #define HI_ASP_SIO_I2S_POS_MERGE_EN_REG (0x88) 64*4882a593Smuzhiyun #define HI_ASP_SIO_INTMASK_REG (0x8C) 65*4882a593Smuzhiyun #define HI_ASP_SIO_I2S_DUAL_RX_CHN_REG (0xA0) 66*4882a593Smuzhiyun #define HI_ASP_SIO_I2S_DUAL_TX_CHN_REG (0xC0) 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun #define HI_ASP_CFG_R_CLK_SEL_EN BIT(2) 70*4882a593Smuzhiyun #define HI_ASP_CFG_R_CLK_SEL 0x140010 71*4882a593Smuzhiyun #define HI_ASP_CFG_R_CLK1_DIV_SEL 0xbcdc9a 72*4882a593Smuzhiyun #define HI_ASP_CFG_R_CLK4_DIV_SEL 0x00ff000f 73*4882a593Smuzhiyun #define HI_ASP_CFG_R_CLK6_DIV_SEL 0x00ff003f 74*4882a593Smuzhiyun #define HI_ASP_CFG_SIO_MODE 0 75*4882a593Smuzhiyun #define HI_ASP_SIO_MODE_SEL_EN BIT(0) 76*4882a593Smuzhiyun #define HI_ASP_MASK 0xffffffff 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun #define HI_ASP_SIO_RX_ENABLE BIT(13) 79*4882a593Smuzhiyun #define HI_ASP_SIO_TX_ENABLE BIT(12) 80*4882a593Smuzhiyun #define HI_ASP_SIO_RX_FIFO_DISABLE BIT(11) 81*4882a593Smuzhiyun #define HI_ASP_SIO_TX_FIFO_DISABLE BIT(10) 82*4882a593Smuzhiyun #define HI_ASP_SIO_RX_DATA_MERGE BIT(9) 83*4882a593Smuzhiyun #define HI_ASP_SIO_TX_DATA_MERGE BIT(8) 84*4882a593Smuzhiyun #define HI_ASP_SIO_RX_FIFO_THRESHOLD (0x5 << 4) 85*4882a593Smuzhiyun #define HI_ASP_SIO_TX_FIFO_THRESHOLD (0xB << 0) 86*4882a593Smuzhiyun #define HI_ASP_SIO_RX_FIFO_THRESHOLD_CLR (0xF << 4) 87*4882a593Smuzhiyun #define HI_ASP_SIO_TX_FIFO_THRESHOLD_CLR (0xF << 0) 88*4882a593Smuzhiyun #define HI_ASP_SIO_BURST (0x4) 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun enum hisi_i2s_formats { 92*4882a593Smuzhiyun HII2S_FORMAT_I2S, 93*4882a593Smuzhiyun HII2S_FORMAT_PCM_STD, 94*4882a593Smuzhiyun HII2S_FORMAT_PCM_USER, 95*4882a593Smuzhiyun HII2S_FORMAT_LEFT_JUST, 96*4882a593Smuzhiyun HII2S_FORMAT_RIGHT_JUST, 97*4882a593Smuzhiyun }; 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun #endif/* _HI3660_I2S_H */ 100