xref: /OK3568_Linux_fs/kernel/sound/soc/fsl/mpc5200_psc_ac97.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun //
3*4882a593Smuzhiyun // linux/sound/mpc5200-ac97.c -- AC97 support for the Freescale MPC52xx chip.
4*4882a593Smuzhiyun //
5*4882a593Smuzhiyun // Copyright (C) 2009 Jon Smirl, Digispeaker
6*4882a593Smuzhiyun // Author: Jon Smirl <jonsmirl@gmail.com>
7*4882a593Smuzhiyun 
8*4882a593Smuzhiyun #include <linux/module.h>
9*4882a593Smuzhiyun #include <linux/of_device.h>
10*4882a593Smuzhiyun #include <linux/of_platform.h>
11*4882a593Smuzhiyun #include <linux/delay.h>
12*4882a593Smuzhiyun #include <linux/time.h>
13*4882a593Smuzhiyun 
14*4882a593Smuzhiyun #include <sound/pcm.h>
15*4882a593Smuzhiyun #include <sound/pcm_params.h>
16*4882a593Smuzhiyun #include <sound/soc.h>
17*4882a593Smuzhiyun 
18*4882a593Smuzhiyun #include <asm/time.h>
19*4882a593Smuzhiyun #include <asm/delay.h>
20*4882a593Smuzhiyun #include <asm/mpc52xx.h>
21*4882a593Smuzhiyun #include <asm/mpc52xx_psc.h>
22*4882a593Smuzhiyun 
23*4882a593Smuzhiyun #include "mpc5200_dma.h"
24*4882a593Smuzhiyun 
25*4882a593Smuzhiyun #define DRV_NAME "mpc5200-psc-ac97"
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun /* ALSA only supports a single AC97 device so static is recommend here */
28*4882a593Smuzhiyun static struct psc_dma *psc_dma;
29*4882a593Smuzhiyun 
psc_ac97_read(struct snd_ac97 * ac97,unsigned short reg)30*4882a593Smuzhiyun static unsigned short psc_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
31*4882a593Smuzhiyun {
32*4882a593Smuzhiyun 	int status;
33*4882a593Smuzhiyun 	unsigned int val;
34*4882a593Smuzhiyun 
35*4882a593Smuzhiyun 	mutex_lock(&psc_dma->mutex);
36*4882a593Smuzhiyun 
37*4882a593Smuzhiyun 	/* Wait for command send status zero = ready */
38*4882a593Smuzhiyun 	status = spin_event_timeout(!(in_be16(&psc_dma->psc_regs->sr_csr.status) &
39*4882a593Smuzhiyun 				MPC52xx_PSC_SR_CMDSEND), 100, 0);
40*4882a593Smuzhiyun 	if (status == 0) {
41*4882a593Smuzhiyun 		pr_err("timeout on ac97 bus (rdy)\n");
42*4882a593Smuzhiyun 		mutex_unlock(&psc_dma->mutex);
43*4882a593Smuzhiyun 		return -ENODEV;
44*4882a593Smuzhiyun 	}
45*4882a593Smuzhiyun 
46*4882a593Smuzhiyun 	/* Force clear the data valid bit */
47*4882a593Smuzhiyun 	in_be32(&psc_dma->psc_regs->ac97_data);
48*4882a593Smuzhiyun 
49*4882a593Smuzhiyun 	/* Send the read */
50*4882a593Smuzhiyun 	out_be32(&psc_dma->psc_regs->ac97_cmd, (1<<31) | ((reg & 0x7f) << 24));
51*4882a593Smuzhiyun 
52*4882a593Smuzhiyun 	/* Wait for the answer */
53*4882a593Smuzhiyun 	status = spin_event_timeout((in_be16(&psc_dma->psc_regs->sr_csr.status) &
54*4882a593Smuzhiyun 				MPC52xx_PSC_SR_DATA_VAL), 100, 0);
55*4882a593Smuzhiyun 	if (status == 0) {
56*4882a593Smuzhiyun 		pr_err("timeout on ac97 read (val) %x\n",
57*4882a593Smuzhiyun 				in_be16(&psc_dma->psc_regs->sr_csr.status));
58*4882a593Smuzhiyun 		mutex_unlock(&psc_dma->mutex);
59*4882a593Smuzhiyun 		return -ENODEV;
60*4882a593Smuzhiyun 	}
61*4882a593Smuzhiyun 	/* Get the data */
62*4882a593Smuzhiyun 	val = in_be32(&psc_dma->psc_regs->ac97_data);
63*4882a593Smuzhiyun 	if (((val >> 24) & 0x7f) != reg) {
64*4882a593Smuzhiyun 		pr_err("reg echo error on ac97 read\n");
65*4882a593Smuzhiyun 		mutex_unlock(&psc_dma->mutex);
66*4882a593Smuzhiyun 		return -ENODEV;
67*4882a593Smuzhiyun 	}
68*4882a593Smuzhiyun 	val = (val >> 8) & 0xffff;
69*4882a593Smuzhiyun 
70*4882a593Smuzhiyun 	mutex_unlock(&psc_dma->mutex);
71*4882a593Smuzhiyun 	return (unsigned short) val;
72*4882a593Smuzhiyun }
73*4882a593Smuzhiyun 
psc_ac97_write(struct snd_ac97 * ac97,unsigned short reg,unsigned short val)74*4882a593Smuzhiyun static void psc_ac97_write(struct snd_ac97 *ac97,
75*4882a593Smuzhiyun 				unsigned short reg, unsigned short val)
76*4882a593Smuzhiyun {
77*4882a593Smuzhiyun 	int status;
78*4882a593Smuzhiyun 
79*4882a593Smuzhiyun 	mutex_lock(&psc_dma->mutex);
80*4882a593Smuzhiyun 
81*4882a593Smuzhiyun 	/* Wait for command status zero = ready */
82*4882a593Smuzhiyun 	status = spin_event_timeout(!(in_be16(&psc_dma->psc_regs->sr_csr.status) &
83*4882a593Smuzhiyun 				MPC52xx_PSC_SR_CMDSEND), 100, 0);
84*4882a593Smuzhiyun 	if (status == 0) {
85*4882a593Smuzhiyun 		pr_err("timeout on ac97 bus (write)\n");
86*4882a593Smuzhiyun 		goto out;
87*4882a593Smuzhiyun 	}
88*4882a593Smuzhiyun 	/* Write data */
89*4882a593Smuzhiyun 	out_be32(&psc_dma->psc_regs->ac97_cmd,
90*4882a593Smuzhiyun 			((reg & 0x7f) << 24) | (val << 8));
91*4882a593Smuzhiyun 
92*4882a593Smuzhiyun  out:
93*4882a593Smuzhiyun 	mutex_unlock(&psc_dma->mutex);
94*4882a593Smuzhiyun }
95*4882a593Smuzhiyun 
psc_ac97_warm_reset(struct snd_ac97 * ac97)96*4882a593Smuzhiyun static void psc_ac97_warm_reset(struct snd_ac97 *ac97)
97*4882a593Smuzhiyun {
98*4882a593Smuzhiyun 	struct mpc52xx_psc __iomem *regs = psc_dma->psc_regs;
99*4882a593Smuzhiyun 
100*4882a593Smuzhiyun 	mutex_lock(&psc_dma->mutex);
101*4882a593Smuzhiyun 
102*4882a593Smuzhiyun 	out_be32(&regs->sicr, psc_dma->sicr | MPC52xx_PSC_SICR_AWR);
103*4882a593Smuzhiyun 	udelay(3);
104*4882a593Smuzhiyun 	out_be32(&regs->sicr, psc_dma->sicr);
105*4882a593Smuzhiyun 
106*4882a593Smuzhiyun 	mutex_unlock(&psc_dma->mutex);
107*4882a593Smuzhiyun }
108*4882a593Smuzhiyun 
psc_ac97_cold_reset(struct snd_ac97 * ac97)109*4882a593Smuzhiyun static void psc_ac97_cold_reset(struct snd_ac97 *ac97)
110*4882a593Smuzhiyun {
111*4882a593Smuzhiyun 	struct mpc52xx_psc __iomem *regs = psc_dma->psc_regs;
112*4882a593Smuzhiyun 
113*4882a593Smuzhiyun 	mutex_lock(&psc_dma->mutex);
114*4882a593Smuzhiyun 	dev_dbg(psc_dma->dev, "cold reset\n");
115*4882a593Smuzhiyun 
116*4882a593Smuzhiyun 	mpc5200_psc_ac97_gpio_reset(psc_dma->id);
117*4882a593Smuzhiyun 
118*4882a593Smuzhiyun 	/* Notify the PSC that a reset has occurred */
119*4882a593Smuzhiyun 	out_be32(&regs->sicr, psc_dma->sicr | MPC52xx_PSC_SICR_ACRB);
120*4882a593Smuzhiyun 
121*4882a593Smuzhiyun 	/* Re-enable RX and TX */
122*4882a593Smuzhiyun 	out_8(&regs->command, MPC52xx_PSC_TX_ENABLE | MPC52xx_PSC_RX_ENABLE);
123*4882a593Smuzhiyun 
124*4882a593Smuzhiyun 	mutex_unlock(&psc_dma->mutex);
125*4882a593Smuzhiyun 
126*4882a593Smuzhiyun 	usleep_range(1000, 2000);
127*4882a593Smuzhiyun 	psc_ac97_warm_reset(ac97);
128*4882a593Smuzhiyun }
129*4882a593Smuzhiyun 
130*4882a593Smuzhiyun static struct snd_ac97_bus_ops psc_ac97_ops = {
131*4882a593Smuzhiyun 	.read		= psc_ac97_read,
132*4882a593Smuzhiyun 	.write		= psc_ac97_write,
133*4882a593Smuzhiyun 	.reset		= psc_ac97_cold_reset,
134*4882a593Smuzhiyun 	.warm_reset	= psc_ac97_warm_reset,
135*4882a593Smuzhiyun };
136*4882a593Smuzhiyun 
psc_ac97_hw_analog_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * cpu_dai)137*4882a593Smuzhiyun static int psc_ac97_hw_analog_params(struct snd_pcm_substream *substream,
138*4882a593Smuzhiyun 				 struct snd_pcm_hw_params *params,
139*4882a593Smuzhiyun 				 struct snd_soc_dai *cpu_dai)
140*4882a593Smuzhiyun {
141*4882a593Smuzhiyun 	struct psc_dma *psc_dma = snd_soc_dai_get_drvdata(cpu_dai);
142*4882a593Smuzhiyun 	struct psc_dma_stream *s = to_psc_dma_stream(substream, psc_dma);
143*4882a593Smuzhiyun 
144*4882a593Smuzhiyun 	dev_dbg(psc_dma->dev, "%s(substream=%p) p_size=%i p_bytes=%i"
145*4882a593Smuzhiyun 		" periods=%i buffer_size=%i  buffer_bytes=%i channels=%i"
146*4882a593Smuzhiyun 		" rate=%i format=%i\n",
147*4882a593Smuzhiyun 		__func__, substream, params_period_size(params),
148*4882a593Smuzhiyun 		params_period_bytes(params), params_periods(params),
149*4882a593Smuzhiyun 		params_buffer_size(params), params_buffer_bytes(params),
150*4882a593Smuzhiyun 		params_channels(params), params_rate(params),
151*4882a593Smuzhiyun 		params_format(params));
152*4882a593Smuzhiyun 
153*4882a593Smuzhiyun 	/* Determine the set of enable bits to turn on */
154*4882a593Smuzhiyun 	s->ac97_slot_bits = (params_channels(params) == 1) ? 0x100 : 0x300;
155*4882a593Smuzhiyun 	if (substream->pstr->stream != SNDRV_PCM_STREAM_CAPTURE)
156*4882a593Smuzhiyun 		s->ac97_slot_bits <<= 16;
157*4882a593Smuzhiyun 	return 0;
158*4882a593Smuzhiyun }
159*4882a593Smuzhiyun 
psc_ac97_hw_digital_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * cpu_dai)160*4882a593Smuzhiyun static int psc_ac97_hw_digital_params(struct snd_pcm_substream *substream,
161*4882a593Smuzhiyun 				 struct snd_pcm_hw_params *params,
162*4882a593Smuzhiyun 				 struct snd_soc_dai *cpu_dai)
163*4882a593Smuzhiyun {
164*4882a593Smuzhiyun 	struct psc_dma *psc_dma = snd_soc_dai_get_drvdata(cpu_dai);
165*4882a593Smuzhiyun 
166*4882a593Smuzhiyun 	dev_dbg(psc_dma->dev, "%s(substream=%p)\n", __func__, substream);
167*4882a593Smuzhiyun 
168*4882a593Smuzhiyun 	if (params_channels(params) == 1)
169*4882a593Smuzhiyun 		out_be32(&psc_dma->psc_regs->ac97_slots, 0x01000000);
170*4882a593Smuzhiyun 	else
171*4882a593Smuzhiyun 		out_be32(&psc_dma->psc_regs->ac97_slots, 0x03000000);
172*4882a593Smuzhiyun 
173*4882a593Smuzhiyun 	return 0;
174*4882a593Smuzhiyun }
175*4882a593Smuzhiyun 
psc_ac97_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * dai)176*4882a593Smuzhiyun static int psc_ac97_trigger(struct snd_pcm_substream *substream, int cmd,
177*4882a593Smuzhiyun 							struct snd_soc_dai *dai)
178*4882a593Smuzhiyun {
179*4882a593Smuzhiyun 	struct psc_dma *psc_dma = snd_soc_dai_get_drvdata(dai);
180*4882a593Smuzhiyun 	struct psc_dma_stream *s = to_psc_dma_stream(substream, psc_dma);
181*4882a593Smuzhiyun 
182*4882a593Smuzhiyun 	switch (cmd) {
183*4882a593Smuzhiyun 	case SNDRV_PCM_TRIGGER_START:
184*4882a593Smuzhiyun 		dev_dbg(psc_dma->dev, "AC97 START: stream=%i\n",
185*4882a593Smuzhiyun 			substream->pstr->stream);
186*4882a593Smuzhiyun 
187*4882a593Smuzhiyun 		/* Set the slot enable bits */
188*4882a593Smuzhiyun 		psc_dma->slots |= s->ac97_slot_bits;
189*4882a593Smuzhiyun 		out_be32(&psc_dma->psc_regs->ac97_slots, psc_dma->slots);
190*4882a593Smuzhiyun 		break;
191*4882a593Smuzhiyun 
192*4882a593Smuzhiyun 	case SNDRV_PCM_TRIGGER_STOP:
193*4882a593Smuzhiyun 		dev_dbg(psc_dma->dev, "AC97 STOP: stream=%i\n",
194*4882a593Smuzhiyun 			substream->pstr->stream);
195*4882a593Smuzhiyun 
196*4882a593Smuzhiyun 		/* Clear the slot enable bits */
197*4882a593Smuzhiyun 		psc_dma->slots &= ~(s->ac97_slot_bits);
198*4882a593Smuzhiyun 		out_be32(&psc_dma->psc_regs->ac97_slots, psc_dma->slots);
199*4882a593Smuzhiyun 		break;
200*4882a593Smuzhiyun 	}
201*4882a593Smuzhiyun 	return 0;
202*4882a593Smuzhiyun }
203*4882a593Smuzhiyun 
psc_ac97_probe(struct snd_soc_dai * cpu_dai)204*4882a593Smuzhiyun static int psc_ac97_probe(struct snd_soc_dai *cpu_dai)
205*4882a593Smuzhiyun {
206*4882a593Smuzhiyun 	struct psc_dma *psc_dma = snd_soc_dai_get_drvdata(cpu_dai);
207*4882a593Smuzhiyun 	struct mpc52xx_psc __iomem *regs = psc_dma->psc_regs;
208*4882a593Smuzhiyun 
209*4882a593Smuzhiyun 	/* Go */
210*4882a593Smuzhiyun 	out_8(&regs->command, MPC52xx_PSC_TX_ENABLE | MPC52xx_PSC_RX_ENABLE);
211*4882a593Smuzhiyun 	return 0;
212*4882a593Smuzhiyun }
213*4882a593Smuzhiyun 
214*4882a593Smuzhiyun /* ---------------------------------------------------------------------
215*4882a593Smuzhiyun  * ALSA SoC Bindings
216*4882a593Smuzhiyun  *
217*4882a593Smuzhiyun  * - Digital Audio Interface (DAI) template
218*4882a593Smuzhiyun  * - create/destroy dai hooks
219*4882a593Smuzhiyun  */
220*4882a593Smuzhiyun 
221*4882a593Smuzhiyun /**
222*4882a593Smuzhiyun  * psc_ac97_dai_template: template CPU Digital Audio Interface
223*4882a593Smuzhiyun  */
224*4882a593Smuzhiyun static const struct snd_soc_dai_ops psc_ac97_analog_ops = {
225*4882a593Smuzhiyun 	.hw_params	= psc_ac97_hw_analog_params,
226*4882a593Smuzhiyun 	.trigger	= psc_ac97_trigger,
227*4882a593Smuzhiyun };
228*4882a593Smuzhiyun 
229*4882a593Smuzhiyun static const struct snd_soc_dai_ops psc_ac97_digital_ops = {
230*4882a593Smuzhiyun 	.hw_params	= psc_ac97_hw_digital_params,
231*4882a593Smuzhiyun };
232*4882a593Smuzhiyun 
233*4882a593Smuzhiyun static struct snd_soc_dai_driver psc_ac97_dai[] = {
234*4882a593Smuzhiyun {
235*4882a593Smuzhiyun 	.name = "mpc5200-psc-ac97.0",
236*4882a593Smuzhiyun 	.probe	= psc_ac97_probe,
237*4882a593Smuzhiyun 	.playback = {
238*4882a593Smuzhiyun 		.stream_name	= "AC97 Playback",
239*4882a593Smuzhiyun 		.channels_min   = 1,
240*4882a593Smuzhiyun 		.channels_max   = 6,
241*4882a593Smuzhiyun 		.rates          = SNDRV_PCM_RATE_8000_48000,
242*4882a593Smuzhiyun 		.formats = SNDRV_PCM_FMTBIT_S32_BE,
243*4882a593Smuzhiyun 	},
244*4882a593Smuzhiyun 	.capture = {
245*4882a593Smuzhiyun 		.stream_name	= "AC97 Capture",
246*4882a593Smuzhiyun 		.channels_min   = 1,
247*4882a593Smuzhiyun 		.channels_max   = 2,
248*4882a593Smuzhiyun 		.rates          = SNDRV_PCM_RATE_8000_48000,
249*4882a593Smuzhiyun 		.formats = SNDRV_PCM_FMTBIT_S32_BE,
250*4882a593Smuzhiyun 	},
251*4882a593Smuzhiyun 	.ops = &psc_ac97_analog_ops,
252*4882a593Smuzhiyun },
253*4882a593Smuzhiyun {
254*4882a593Smuzhiyun 	.name = "mpc5200-psc-ac97.1",
255*4882a593Smuzhiyun 	.playback = {
256*4882a593Smuzhiyun 		.stream_name	= "AC97 SPDIF",
257*4882a593Smuzhiyun 		.channels_min   = 1,
258*4882a593Smuzhiyun 		.channels_max   = 2,
259*4882a593Smuzhiyun 		.rates          = SNDRV_PCM_RATE_32000 | \
260*4882a593Smuzhiyun 			SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
261*4882a593Smuzhiyun 		.formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_BE,
262*4882a593Smuzhiyun 	},
263*4882a593Smuzhiyun 	.ops = &psc_ac97_digital_ops,
264*4882a593Smuzhiyun } };
265*4882a593Smuzhiyun 
266*4882a593Smuzhiyun static const struct snd_soc_component_driver psc_ac97_component = {
267*4882a593Smuzhiyun 	.name		= DRV_NAME,
268*4882a593Smuzhiyun };
269*4882a593Smuzhiyun 
270*4882a593Smuzhiyun 
271*4882a593Smuzhiyun /* ---------------------------------------------------------------------
272*4882a593Smuzhiyun  * OF platform bus binding code:
273*4882a593Smuzhiyun  * - Probe/remove operations
274*4882a593Smuzhiyun  * - OF device match table
275*4882a593Smuzhiyun  */
psc_ac97_of_probe(struct platform_device * op)276*4882a593Smuzhiyun static int psc_ac97_of_probe(struct platform_device *op)
277*4882a593Smuzhiyun {
278*4882a593Smuzhiyun 	int rc;
279*4882a593Smuzhiyun 	struct mpc52xx_psc __iomem *regs;
280*4882a593Smuzhiyun 
281*4882a593Smuzhiyun 	rc = mpc5200_audio_dma_create(op);
282*4882a593Smuzhiyun 	if (rc != 0)
283*4882a593Smuzhiyun 		return rc;
284*4882a593Smuzhiyun 
285*4882a593Smuzhiyun 	rc = snd_soc_set_ac97_ops(&psc_ac97_ops);
286*4882a593Smuzhiyun 	if (rc != 0) {
287*4882a593Smuzhiyun 		dev_err(&op->dev, "Failed to set AC'97 ops: %d\n", rc);
288*4882a593Smuzhiyun 		return rc;
289*4882a593Smuzhiyun 	}
290*4882a593Smuzhiyun 
291*4882a593Smuzhiyun 	rc = snd_soc_register_component(&op->dev, &psc_ac97_component,
292*4882a593Smuzhiyun 					psc_ac97_dai, ARRAY_SIZE(psc_ac97_dai));
293*4882a593Smuzhiyun 	if (rc != 0) {
294*4882a593Smuzhiyun 		dev_err(&op->dev, "Failed to register DAI\n");
295*4882a593Smuzhiyun 		return rc;
296*4882a593Smuzhiyun 	}
297*4882a593Smuzhiyun 
298*4882a593Smuzhiyun 	psc_dma = dev_get_drvdata(&op->dev);
299*4882a593Smuzhiyun 	regs = psc_dma->psc_regs;
300*4882a593Smuzhiyun 
301*4882a593Smuzhiyun 	psc_dma->imr = 0;
302*4882a593Smuzhiyun 	out_be16(&psc_dma->psc_regs->isr_imr.imr, psc_dma->imr);
303*4882a593Smuzhiyun 
304*4882a593Smuzhiyun 	/* Configure the serial interface mode to AC97 */
305*4882a593Smuzhiyun 	psc_dma->sicr = MPC52xx_PSC_SICR_SIM_AC97 | MPC52xx_PSC_SICR_ENAC97;
306*4882a593Smuzhiyun 	out_be32(&regs->sicr, psc_dma->sicr);
307*4882a593Smuzhiyun 
308*4882a593Smuzhiyun 	/* No slots active */
309*4882a593Smuzhiyun 	out_be32(&regs->ac97_slots, 0x00000000);
310*4882a593Smuzhiyun 
311*4882a593Smuzhiyun 	return 0;
312*4882a593Smuzhiyun }
313*4882a593Smuzhiyun 
psc_ac97_of_remove(struct platform_device * op)314*4882a593Smuzhiyun static int psc_ac97_of_remove(struct platform_device *op)
315*4882a593Smuzhiyun {
316*4882a593Smuzhiyun 	mpc5200_audio_dma_destroy(op);
317*4882a593Smuzhiyun 	snd_soc_unregister_component(&op->dev);
318*4882a593Smuzhiyun 	snd_soc_set_ac97_ops(NULL);
319*4882a593Smuzhiyun 	return 0;
320*4882a593Smuzhiyun }
321*4882a593Smuzhiyun 
322*4882a593Smuzhiyun /* Match table for of_platform binding */
323*4882a593Smuzhiyun static const struct of_device_id psc_ac97_match[] = {
324*4882a593Smuzhiyun 	{ .compatible = "fsl,mpc5200-psc-ac97", },
325*4882a593Smuzhiyun 	{ .compatible = "fsl,mpc5200b-psc-ac97", },
326*4882a593Smuzhiyun 	{}
327*4882a593Smuzhiyun };
328*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, psc_ac97_match);
329*4882a593Smuzhiyun 
330*4882a593Smuzhiyun static struct platform_driver psc_ac97_driver = {
331*4882a593Smuzhiyun 	.probe = psc_ac97_of_probe,
332*4882a593Smuzhiyun 	.remove = psc_ac97_of_remove,
333*4882a593Smuzhiyun 	.driver = {
334*4882a593Smuzhiyun 		.name = "mpc5200-psc-ac97",
335*4882a593Smuzhiyun 		.of_match_table = psc_ac97_match,
336*4882a593Smuzhiyun 	},
337*4882a593Smuzhiyun };
338*4882a593Smuzhiyun 
339*4882a593Smuzhiyun module_platform_driver(psc_ac97_driver);
340*4882a593Smuzhiyun 
341*4882a593Smuzhiyun MODULE_AUTHOR("Jon Smirl <jonsmirl@gmail.com>");
342*4882a593Smuzhiyun MODULE_DESCRIPTION("mpc5200 AC97 module");
343*4882a593Smuzhiyun MODULE_LICENSE("GPL");
344*4882a593Smuzhiyun 
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