1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun //
3*4882a593Smuzhiyun // Freescale MPC5200 PSC DMA
4*4882a593Smuzhiyun // ALSA SoC Platform driver
5*4882a593Smuzhiyun //
6*4882a593Smuzhiyun // Copyright (C) 2008 Secret Lab Technologies Ltd.
7*4882a593Smuzhiyun // Copyright (C) 2009 Jon Smirl, Digispeaker
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <linux/module.h>
10*4882a593Smuzhiyun #include <linux/of_device.h>
11*4882a593Smuzhiyun #include <linux/dma-mapping.h>
12*4882a593Smuzhiyun #include <linux/slab.h>
13*4882a593Smuzhiyun #include <linux/of_address.h>
14*4882a593Smuzhiyun #include <linux/of_irq.h>
15*4882a593Smuzhiyun #include <linux/of_platform.h>
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #include <sound/soc.h>
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun #include <linux/fsl/bestcomm/bestcomm.h>
20*4882a593Smuzhiyun #include <linux/fsl/bestcomm/gen_bd.h>
21*4882a593Smuzhiyun #include <asm/mpc52xx_psc.h>
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun #include "mpc5200_dma.h"
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun #define DRV_NAME "mpc5200_dma"
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun /*
28*4882a593Smuzhiyun * Interrupt handlers
29*4882a593Smuzhiyun */
psc_dma_status_irq(int irq,void * _psc_dma)30*4882a593Smuzhiyun static irqreturn_t psc_dma_status_irq(int irq, void *_psc_dma)
31*4882a593Smuzhiyun {
32*4882a593Smuzhiyun struct psc_dma *psc_dma = _psc_dma;
33*4882a593Smuzhiyun struct mpc52xx_psc __iomem *regs = psc_dma->psc_regs;
34*4882a593Smuzhiyun u16 isr;
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun isr = in_be16(®s->mpc52xx_psc_isr);
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun /* Playback underrun error */
39*4882a593Smuzhiyun if (psc_dma->playback.active && (isr & MPC52xx_PSC_IMR_TXEMP))
40*4882a593Smuzhiyun psc_dma->stats.underrun_count++;
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun /* Capture overrun error */
43*4882a593Smuzhiyun if (psc_dma->capture.active && (isr & MPC52xx_PSC_IMR_ORERR))
44*4882a593Smuzhiyun psc_dma->stats.overrun_count++;
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun out_8(®s->command, MPC52xx_PSC_RST_ERR_STAT);
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun return IRQ_HANDLED;
49*4882a593Smuzhiyun }
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun /**
52*4882a593Smuzhiyun * psc_dma_bcom_enqueue_next_buffer - Enqueue another audio buffer
53*4882a593Smuzhiyun * @s: pointer to stream private data structure
54*4882a593Smuzhiyun *
55*4882a593Smuzhiyun * Enqueues another audio period buffer into the bestcomm queue.
56*4882a593Smuzhiyun *
57*4882a593Smuzhiyun * Note: The routine must only be called when there is space available in
58*4882a593Smuzhiyun * the queue. Otherwise the enqueue will fail and the audio ring buffer
59*4882a593Smuzhiyun * will get out of sync
60*4882a593Smuzhiyun */
psc_dma_bcom_enqueue_next_buffer(struct psc_dma_stream * s)61*4882a593Smuzhiyun static void psc_dma_bcom_enqueue_next_buffer(struct psc_dma_stream *s)
62*4882a593Smuzhiyun {
63*4882a593Smuzhiyun struct bcom_bd *bd;
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun /* Prepare and enqueue the next buffer descriptor */
66*4882a593Smuzhiyun bd = bcom_prepare_next_buffer(s->bcom_task);
67*4882a593Smuzhiyun bd->status = s->period_bytes;
68*4882a593Smuzhiyun bd->data[0] = s->runtime->dma_addr + (s->period_next * s->period_bytes);
69*4882a593Smuzhiyun bcom_submit_next_buffer(s->bcom_task, NULL);
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun /* Update for next period */
72*4882a593Smuzhiyun s->period_next = (s->period_next + 1) % s->runtime->periods;
73*4882a593Smuzhiyun }
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun /* Bestcomm DMA irq handler */
psc_dma_bcom_irq(int irq,void * _psc_dma_stream)76*4882a593Smuzhiyun static irqreturn_t psc_dma_bcom_irq(int irq, void *_psc_dma_stream)
77*4882a593Smuzhiyun {
78*4882a593Smuzhiyun struct psc_dma_stream *s = _psc_dma_stream;
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun spin_lock(&s->psc_dma->lock);
81*4882a593Smuzhiyun /* For each finished period, dequeue the completed period buffer
82*4882a593Smuzhiyun * and enqueue a new one in it's place. */
83*4882a593Smuzhiyun while (bcom_buffer_done(s->bcom_task)) {
84*4882a593Smuzhiyun bcom_retrieve_buffer(s->bcom_task, NULL, NULL);
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun s->period_current = (s->period_current+1) % s->runtime->periods;
87*4882a593Smuzhiyun s->period_count++;
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun psc_dma_bcom_enqueue_next_buffer(s);
90*4882a593Smuzhiyun }
91*4882a593Smuzhiyun spin_unlock(&s->psc_dma->lock);
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun /* If the stream is active, then also inform the PCM middle layer
94*4882a593Smuzhiyun * of the period finished event. */
95*4882a593Smuzhiyun if (s->active)
96*4882a593Smuzhiyun snd_pcm_period_elapsed(s->stream);
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun return IRQ_HANDLED;
99*4882a593Smuzhiyun }
100*4882a593Smuzhiyun
psc_dma_hw_free(struct snd_soc_component * component,struct snd_pcm_substream * substream)101*4882a593Smuzhiyun static int psc_dma_hw_free(struct snd_soc_component *component,
102*4882a593Smuzhiyun struct snd_pcm_substream *substream)
103*4882a593Smuzhiyun {
104*4882a593Smuzhiyun snd_pcm_set_runtime_buffer(substream, NULL);
105*4882a593Smuzhiyun return 0;
106*4882a593Smuzhiyun }
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun /**
109*4882a593Smuzhiyun * psc_dma_trigger: start and stop the DMA transfer.
110*4882a593Smuzhiyun *
111*4882a593Smuzhiyun * This function is called by ALSA to start, stop, pause, and resume the DMA
112*4882a593Smuzhiyun * transfer of data.
113*4882a593Smuzhiyun */
psc_dma_trigger(struct snd_soc_component * component,struct snd_pcm_substream * substream,int cmd)114*4882a593Smuzhiyun static int psc_dma_trigger(struct snd_soc_component *component,
115*4882a593Smuzhiyun struct snd_pcm_substream *substream, int cmd)
116*4882a593Smuzhiyun {
117*4882a593Smuzhiyun struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
118*4882a593Smuzhiyun struct psc_dma *psc_dma = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
119*4882a593Smuzhiyun struct snd_pcm_runtime *runtime = substream->runtime;
120*4882a593Smuzhiyun struct psc_dma_stream *s = to_psc_dma_stream(substream, psc_dma);
121*4882a593Smuzhiyun struct mpc52xx_psc __iomem *regs = psc_dma->psc_regs;
122*4882a593Smuzhiyun u16 imr;
123*4882a593Smuzhiyun unsigned long flags;
124*4882a593Smuzhiyun int i;
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun switch (cmd) {
127*4882a593Smuzhiyun case SNDRV_PCM_TRIGGER_START:
128*4882a593Smuzhiyun dev_dbg(psc_dma->dev, "START: stream=%i fbits=%u ps=%u #p=%u\n",
129*4882a593Smuzhiyun substream->pstr->stream, runtime->frame_bits,
130*4882a593Smuzhiyun (int)runtime->period_size, runtime->periods);
131*4882a593Smuzhiyun s->period_bytes = frames_to_bytes(runtime,
132*4882a593Smuzhiyun runtime->period_size);
133*4882a593Smuzhiyun s->period_next = 0;
134*4882a593Smuzhiyun s->period_current = 0;
135*4882a593Smuzhiyun s->active = 1;
136*4882a593Smuzhiyun s->period_count = 0;
137*4882a593Smuzhiyun s->runtime = runtime;
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun /* Fill up the bestcomm bd queue and enable DMA.
140*4882a593Smuzhiyun * This will begin filling the PSC's fifo.
141*4882a593Smuzhiyun */
142*4882a593Smuzhiyun spin_lock_irqsave(&psc_dma->lock, flags);
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun if (substream->pstr->stream == SNDRV_PCM_STREAM_CAPTURE)
145*4882a593Smuzhiyun bcom_gen_bd_rx_reset(s->bcom_task);
146*4882a593Smuzhiyun else
147*4882a593Smuzhiyun bcom_gen_bd_tx_reset(s->bcom_task);
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun for (i = 0; i < runtime->periods; i++)
150*4882a593Smuzhiyun if (!bcom_queue_full(s->bcom_task))
151*4882a593Smuzhiyun psc_dma_bcom_enqueue_next_buffer(s);
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun bcom_enable(s->bcom_task);
154*4882a593Smuzhiyun spin_unlock_irqrestore(&psc_dma->lock, flags);
155*4882a593Smuzhiyun
156*4882a593Smuzhiyun out_8(®s->command, MPC52xx_PSC_RST_ERR_STAT);
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun break;
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun case SNDRV_PCM_TRIGGER_STOP:
161*4882a593Smuzhiyun dev_dbg(psc_dma->dev, "STOP: stream=%i periods_count=%i\n",
162*4882a593Smuzhiyun substream->pstr->stream, s->period_count);
163*4882a593Smuzhiyun s->active = 0;
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun spin_lock_irqsave(&psc_dma->lock, flags);
166*4882a593Smuzhiyun bcom_disable(s->bcom_task);
167*4882a593Smuzhiyun if (substream->pstr->stream == SNDRV_PCM_STREAM_CAPTURE)
168*4882a593Smuzhiyun bcom_gen_bd_rx_reset(s->bcom_task);
169*4882a593Smuzhiyun else
170*4882a593Smuzhiyun bcom_gen_bd_tx_reset(s->bcom_task);
171*4882a593Smuzhiyun spin_unlock_irqrestore(&psc_dma->lock, flags);
172*4882a593Smuzhiyun
173*4882a593Smuzhiyun break;
174*4882a593Smuzhiyun
175*4882a593Smuzhiyun default:
176*4882a593Smuzhiyun dev_dbg(psc_dma->dev, "unhandled trigger: stream=%i cmd=%i\n",
177*4882a593Smuzhiyun substream->pstr->stream, cmd);
178*4882a593Smuzhiyun return -EINVAL;
179*4882a593Smuzhiyun }
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun /* Update interrupt enable settings */
182*4882a593Smuzhiyun imr = 0;
183*4882a593Smuzhiyun if (psc_dma->playback.active)
184*4882a593Smuzhiyun imr |= MPC52xx_PSC_IMR_TXEMP;
185*4882a593Smuzhiyun if (psc_dma->capture.active)
186*4882a593Smuzhiyun imr |= MPC52xx_PSC_IMR_ORERR;
187*4882a593Smuzhiyun out_be16(®s->isr_imr.imr, psc_dma->imr | imr);
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun return 0;
190*4882a593Smuzhiyun }
191*4882a593Smuzhiyun
192*4882a593Smuzhiyun
193*4882a593Smuzhiyun /* ---------------------------------------------------------------------
194*4882a593Smuzhiyun * The PSC DMA 'ASoC platform' driver
195*4882a593Smuzhiyun *
196*4882a593Smuzhiyun * Can be referenced by an 'ASoC machine' driver
197*4882a593Smuzhiyun * This driver only deals with the audio bus; it doesn't have any
198*4882a593Smuzhiyun * interaction with the attached codec
199*4882a593Smuzhiyun */
200*4882a593Smuzhiyun
201*4882a593Smuzhiyun static const struct snd_pcm_hardware psc_dma_hardware = {
202*4882a593Smuzhiyun .info = SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_MMAP_VALID |
203*4882a593Smuzhiyun SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_BLOCK_TRANSFER |
204*4882a593Smuzhiyun SNDRV_PCM_INFO_BATCH,
205*4882a593Smuzhiyun .formats = SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_BE |
206*4882a593Smuzhiyun SNDRV_PCM_FMTBIT_S24_BE | SNDRV_PCM_FMTBIT_S32_BE,
207*4882a593Smuzhiyun .period_bytes_max = 1024 * 1024,
208*4882a593Smuzhiyun .period_bytes_min = 32,
209*4882a593Smuzhiyun .periods_min = 2,
210*4882a593Smuzhiyun .periods_max = 256,
211*4882a593Smuzhiyun .buffer_bytes_max = 2 * 1024 * 1024,
212*4882a593Smuzhiyun .fifo_size = 512,
213*4882a593Smuzhiyun };
214*4882a593Smuzhiyun
psc_dma_open(struct snd_soc_component * component,struct snd_pcm_substream * substream)215*4882a593Smuzhiyun static int psc_dma_open(struct snd_soc_component *component,
216*4882a593Smuzhiyun struct snd_pcm_substream *substream)
217*4882a593Smuzhiyun {
218*4882a593Smuzhiyun struct snd_pcm_runtime *runtime = substream->runtime;
219*4882a593Smuzhiyun struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
220*4882a593Smuzhiyun struct psc_dma *psc_dma = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
221*4882a593Smuzhiyun struct psc_dma_stream *s;
222*4882a593Smuzhiyun int rc;
223*4882a593Smuzhiyun
224*4882a593Smuzhiyun dev_dbg(psc_dma->dev, "psc_dma_open(substream=%p)\n", substream);
225*4882a593Smuzhiyun
226*4882a593Smuzhiyun if (substream->pstr->stream == SNDRV_PCM_STREAM_CAPTURE)
227*4882a593Smuzhiyun s = &psc_dma->capture;
228*4882a593Smuzhiyun else
229*4882a593Smuzhiyun s = &psc_dma->playback;
230*4882a593Smuzhiyun
231*4882a593Smuzhiyun snd_soc_set_runtime_hwparams(substream, &psc_dma_hardware);
232*4882a593Smuzhiyun
233*4882a593Smuzhiyun rc = snd_pcm_hw_constraint_integer(runtime,
234*4882a593Smuzhiyun SNDRV_PCM_HW_PARAM_PERIODS);
235*4882a593Smuzhiyun if (rc < 0) {
236*4882a593Smuzhiyun dev_err(substream->pcm->card->dev, "invalid buffer size\n");
237*4882a593Smuzhiyun return rc;
238*4882a593Smuzhiyun }
239*4882a593Smuzhiyun
240*4882a593Smuzhiyun s->stream = substream;
241*4882a593Smuzhiyun return 0;
242*4882a593Smuzhiyun }
243*4882a593Smuzhiyun
psc_dma_close(struct snd_soc_component * component,struct snd_pcm_substream * substream)244*4882a593Smuzhiyun static int psc_dma_close(struct snd_soc_component *component,
245*4882a593Smuzhiyun struct snd_pcm_substream *substream)
246*4882a593Smuzhiyun {
247*4882a593Smuzhiyun struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
248*4882a593Smuzhiyun struct psc_dma *psc_dma = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
249*4882a593Smuzhiyun struct psc_dma_stream *s;
250*4882a593Smuzhiyun
251*4882a593Smuzhiyun dev_dbg(psc_dma->dev, "psc_dma_close(substream=%p)\n", substream);
252*4882a593Smuzhiyun
253*4882a593Smuzhiyun if (substream->pstr->stream == SNDRV_PCM_STREAM_CAPTURE)
254*4882a593Smuzhiyun s = &psc_dma->capture;
255*4882a593Smuzhiyun else
256*4882a593Smuzhiyun s = &psc_dma->playback;
257*4882a593Smuzhiyun
258*4882a593Smuzhiyun if (!psc_dma->playback.active &&
259*4882a593Smuzhiyun !psc_dma->capture.active) {
260*4882a593Smuzhiyun
261*4882a593Smuzhiyun /* Disable all interrupts and reset the PSC */
262*4882a593Smuzhiyun out_be16(&psc_dma->psc_regs->isr_imr.imr, psc_dma->imr);
263*4882a593Smuzhiyun out_8(&psc_dma->psc_regs->command, 4 << 4); /* reset error */
264*4882a593Smuzhiyun }
265*4882a593Smuzhiyun s->stream = NULL;
266*4882a593Smuzhiyun return 0;
267*4882a593Smuzhiyun }
268*4882a593Smuzhiyun
269*4882a593Smuzhiyun static snd_pcm_uframes_t
psc_dma_pointer(struct snd_soc_component * component,struct snd_pcm_substream * substream)270*4882a593Smuzhiyun psc_dma_pointer(struct snd_soc_component *component,
271*4882a593Smuzhiyun struct snd_pcm_substream *substream)
272*4882a593Smuzhiyun {
273*4882a593Smuzhiyun struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
274*4882a593Smuzhiyun struct psc_dma *psc_dma = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
275*4882a593Smuzhiyun struct psc_dma_stream *s;
276*4882a593Smuzhiyun dma_addr_t count;
277*4882a593Smuzhiyun
278*4882a593Smuzhiyun if (substream->pstr->stream == SNDRV_PCM_STREAM_CAPTURE)
279*4882a593Smuzhiyun s = &psc_dma->capture;
280*4882a593Smuzhiyun else
281*4882a593Smuzhiyun s = &psc_dma->playback;
282*4882a593Smuzhiyun
283*4882a593Smuzhiyun count = s->period_current * s->period_bytes;
284*4882a593Smuzhiyun
285*4882a593Smuzhiyun return bytes_to_frames(substream->runtime, count);
286*4882a593Smuzhiyun }
287*4882a593Smuzhiyun
psc_dma_hw_params(struct snd_soc_component * component,struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params)288*4882a593Smuzhiyun static int psc_dma_hw_params(struct snd_soc_component *component,
289*4882a593Smuzhiyun struct snd_pcm_substream *substream,
290*4882a593Smuzhiyun struct snd_pcm_hw_params *params)
291*4882a593Smuzhiyun {
292*4882a593Smuzhiyun snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer);
293*4882a593Smuzhiyun
294*4882a593Smuzhiyun return 0;
295*4882a593Smuzhiyun }
296*4882a593Smuzhiyun
psc_dma_new(struct snd_soc_component * component,struct snd_soc_pcm_runtime * rtd)297*4882a593Smuzhiyun static int psc_dma_new(struct snd_soc_component *component,
298*4882a593Smuzhiyun struct snd_soc_pcm_runtime *rtd)
299*4882a593Smuzhiyun {
300*4882a593Smuzhiyun struct snd_card *card = rtd->card->snd_card;
301*4882a593Smuzhiyun struct snd_soc_dai *dai = asoc_rtd_to_cpu(rtd, 0);
302*4882a593Smuzhiyun struct snd_pcm *pcm = rtd->pcm;
303*4882a593Smuzhiyun size_t size = psc_dma_hardware.buffer_bytes_max;
304*4882a593Smuzhiyun int rc;
305*4882a593Smuzhiyun
306*4882a593Smuzhiyun dev_dbg(component->dev, "psc_dma_new(card=%p, dai=%p, pcm=%p)\n",
307*4882a593Smuzhiyun card, dai, pcm);
308*4882a593Smuzhiyun
309*4882a593Smuzhiyun rc = dma_coerce_mask_and_coherent(card->dev, DMA_BIT_MASK(32));
310*4882a593Smuzhiyun if (rc)
311*4882a593Smuzhiyun return rc;
312*4882a593Smuzhiyun
313*4882a593Smuzhiyun if (pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream) {
314*4882a593Smuzhiyun rc = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, pcm->card->dev,
315*4882a593Smuzhiyun size, &pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream->dma_buffer);
316*4882a593Smuzhiyun if (rc)
317*4882a593Smuzhiyun goto playback_alloc_err;
318*4882a593Smuzhiyun }
319*4882a593Smuzhiyun
320*4882a593Smuzhiyun if (pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream) {
321*4882a593Smuzhiyun rc = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, pcm->card->dev,
322*4882a593Smuzhiyun size, &pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream->dma_buffer);
323*4882a593Smuzhiyun if (rc)
324*4882a593Smuzhiyun goto capture_alloc_err;
325*4882a593Smuzhiyun }
326*4882a593Smuzhiyun
327*4882a593Smuzhiyun return 0;
328*4882a593Smuzhiyun
329*4882a593Smuzhiyun capture_alloc_err:
330*4882a593Smuzhiyun if (pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream)
331*4882a593Smuzhiyun snd_dma_free_pages(&pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream->dma_buffer);
332*4882a593Smuzhiyun
333*4882a593Smuzhiyun playback_alloc_err:
334*4882a593Smuzhiyun dev_err(card->dev, "Cannot allocate buffer(s)\n");
335*4882a593Smuzhiyun
336*4882a593Smuzhiyun return -ENOMEM;
337*4882a593Smuzhiyun }
338*4882a593Smuzhiyun
psc_dma_free(struct snd_soc_component * component,struct snd_pcm * pcm)339*4882a593Smuzhiyun static void psc_dma_free(struct snd_soc_component *component,
340*4882a593Smuzhiyun struct snd_pcm *pcm)
341*4882a593Smuzhiyun {
342*4882a593Smuzhiyun struct snd_pcm_substream *substream;
343*4882a593Smuzhiyun int stream;
344*4882a593Smuzhiyun
345*4882a593Smuzhiyun dev_dbg(component->dev, "psc_dma_free(pcm=%p)\n", pcm);
346*4882a593Smuzhiyun
347*4882a593Smuzhiyun for (stream = 0; stream < 2; stream++) {
348*4882a593Smuzhiyun substream = pcm->streams[stream].substream;
349*4882a593Smuzhiyun if (substream) {
350*4882a593Smuzhiyun snd_dma_free_pages(&substream->dma_buffer);
351*4882a593Smuzhiyun substream->dma_buffer.area = NULL;
352*4882a593Smuzhiyun substream->dma_buffer.addr = 0;
353*4882a593Smuzhiyun }
354*4882a593Smuzhiyun }
355*4882a593Smuzhiyun }
356*4882a593Smuzhiyun
357*4882a593Smuzhiyun static const struct snd_soc_component_driver mpc5200_audio_dma_component = {
358*4882a593Smuzhiyun .name = DRV_NAME,
359*4882a593Smuzhiyun .open = psc_dma_open,
360*4882a593Smuzhiyun .close = psc_dma_close,
361*4882a593Smuzhiyun .hw_free = psc_dma_hw_free,
362*4882a593Smuzhiyun .pointer = psc_dma_pointer,
363*4882a593Smuzhiyun .trigger = psc_dma_trigger,
364*4882a593Smuzhiyun .hw_params = psc_dma_hw_params,
365*4882a593Smuzhiyun .pcm_construct = psc_dma_new,
366*4882a593Smuzhiyun .pcm_destruct = psc_dma_free,
367*4882a593Smuzhiyun };
368*4882a593Smuzhiyun
mpc5200_audio_dma_create(struct platform_device * op)369*4882a593Smuzhiyun int mpc5200_audio_dma_create(struct platform_device *op)
370*4882a593Smuzhiyun {
371*4882a593Smuzhiyun phys_addr_t fifo;
372*4882a593Smuzhiyun struct psc_dma *psc_dma;
373*4882a593Smuzhiyun struct resource res;
374*4882a593Smuzhiyun int size, irq, rc;
375*4882a593Smuzhiyun const __be32 *prop;
376*4882a593Smuzhiyun void __iomem *regs;
377*4882a593Smuzhiyun int ret;
378*4882a593Smuzhiyun
379*4882a593Smuzhiyun /* Fetch the registers and IRQ of the PSC */
380*4882a593Smuzhiyun irq = irq_of_parse_and_map(op->dev.of_node, 0);
381*4882a593Smuzhiyun if (of_address_to_resource(op->dev.of_node, 0, &res)) {
382*4882a593Smuzhiyun dev_err(&op->dev, "Missing reg property\n");
383*4882a593Smuzhiyun return -ENODEV;
384*4882a593Smuzhiyun }
385*4882a593Smuzhiyun regs = ioremap(res.start, resource_size(&res));
386*4882a593Smuzhiyun if (!regs) {
387*4882a593Smuzhiyun dev_err(&op->dev, "Could not map registers\n");
388*4882a593Smuzhiyun return -ENODEV;
389*4882a593Smuzhiyun }
390*4882a593Smuzhiyun
391*4882a593Smuzhiyun /* Allocate and initialize the driver private data */
392*4882a593Smuzhiyun psc_dma = kzalloc(sizeof *psc_dma, GFP_KERNEL);
393*4882a593Smuzhiyun if (!psc_dma) {
394*4882a593Smuzhiyun ret = -ENOMEM;
395*4882a593Smuzhiyun goto out_unmap;
396*4882a593Smuzhiyun }
397*4882a593Smuzhiyun
398*4882a593Smuzhiyun /* Get the PSC ID */
399*4882a593Smuzhiyun prop = of_get_property(op->dev.of_node, "cell-index", &size);
400*4882a593Smuzhiyun if (!prop || size < sizeof *prop) {
401*4882a593Smuzhiyun ret = -ENODEV;
402*4882a593Smuzhiyun goto out_free;
403*4882a593Smuzhiyun }
404*4882a593Smuzhiyun
405*4882a593Smuzhiyun spin_lock_init(&psc_dma->lock);
406*4882a593Smuzhiyun mutex_init(&psc_dma->mutex);
407*4882a593Smuzhiyun psc_dma->id = be32_to_cpu(*prop);
408*4882a593Smuzhiyun psc_dma->irq = irq;
409*4882a593Smuzhiyun psc_dma->psc_regs = regs;
410*4882a593Smuzhiyun psc_dma->fifo_regs = regs + sizeof *psc_dma->psc_regs;
411*4882a593Smuzhiyun psc_dma->dev = &op->dev;
412*4882a593Smuzhiyun psc_dma->playback.psc_dma = psc_dma;
413*4882a593Smuzhiyun psc_dma->capture.psc_dma = psc_dma;
414*4882a593Smuzhiyun snprintf(psc_dma->name, sizeof psc_dma->name, "PSC%u", psc_dma->id);
415*4882a593Smuzhiyun
416*4882a593Smuzhiyun /* Find the address of the fifo data registers and setup the
417*4882a593Smuzhiyun * DMA tasks */
418*4882a593Smuzhiyun fifo = res.start + offsetof(struct mpc52xx_psc, buffer.buffer_32);
419*4882a593Smuzhiyun psc_dma->capture.bcom_task =
420*4882a593Smuzhiyun bcom_psc_gen_bd_rx_init(psc_dma->id, 10, fifo, 512);
421*4882a593Smuzhiyun psc_dma->playback.bcom_task =
422*4882a593Smuzhiyun bcom_psc_gen_bd_tx_init(psc_dma->id, 10, fifo);
423*4882a593Smuzhiyun if (!psc_dma->capture.bcom_task ||
424*4882a593Smuzhiyun !psc_dma->playback.bcom_task) {
425*4882a593Smuzhiyun dev_err(&op->dev, "Could not allocate bestcomm tasks\n");
426*4882a593Smuzhiyun ret = -ENODEV;
427*4882a593Smuzhiyun goto out_free;
428*4882a593Smuzhiyun }
429*4882a593Smuzhiyun
430*4882a593Smuzhiyun /* Disable all interrupts and reset the PSC */
431*4882a593Smuzhiyun out_be16(&psc_dma->psc_regs->isr_imr.imr, psc_dma->imr);
432*4882a593Smuzhiyun /* reset receiver */
433*4882a593Smuzhiyun out_8(&psc_dma->psc_regs->command, MPC52xx_PSC_RST_RX);
434*4882a593Smuzhiyun /* reset transmitter */
435*4882a593Smuzhiyun out_8(&psc_dma->psc_regs->command, MPC52xx_PSC_RST_TX);
436*4882a593Smuzhiyun /* reset error */
437*4882a593Smuzhiyun out_8(&psc_dma->psc_regs->command, MPC52xx_PSC_RST_ERR_STAT);
438*4882a593Smuzhiyun /* reset mode */
439*4882a593Smuzhiyun out_8(&psc_dma->psc_regs->command, MPC52xx_PSC_SEL_MODE_REG_1);
440*4882a593Smuzhiyun
441*4882a593Smuzhiyun /* Set up mode register;
442*4882a593Smuzhiyun * First write: RxRdy (FIFO Alarm) generates rx FIFO irq
443*4882a593Smuzhiyun * Second write: register Normal mode for non loopback
444*4882a593Smuzhiyun */
445*4882a593Smuzhiyun out_8(&psc_dma->psc_regs->mode, 0);
446*4882a593Smuzhiyun out_8(&psc_dma->psc_regs->mode, 0);
447*4882a593Smuzhiyun
448*4882a593Smuzhiyun /* Set the TX and RX fifo alarm thresholds */
449*4882a593Smuzhiyun out_be16(&psc_dma->fifo_regs->rfalarm, 0x100);
450*4882a593Smuzhiyun out_8(&psc_dma->fifo_regs->rfcntl, 0x4);
451*4882a593Smuzhiyun out_be16(&psc_dma->fifo_regs->tfalarm, 0x100);
452*4882a593Smuzhiyun out_8(&psc_dma->fifo_regs->tfcntl, 0x7);
453*4882a593Smuzhiyun
454*4882a593Smuzhiyun /* Lookup the IRQ numbers */
455*4882a593Smuzhiyun psc_dma->playback.irq =
456*4882a593Smuzhiyun bcom_get_task_irq(psc_dma->playback.bcom_task);
457*4882a593Smuzhiyun psc_dma->capture.irq =
458*4882a593Smuzhiyun bcom_get_task_irq(psc_dma->capture.bcom_task);
459*4882a593Smuzhiyun
460*4882a593Smuzhiyun rc = request_irq(psc_dma->irq, &psc_dma_status_irq, IRQF_SHARED,
461*4882a593Smuzhiyun "psc-dma-status", psc_dma);
462*4882a593Smuzhiyun rc |= request_irq(psc_dma->capture.irq, &psc_dma_bcom_irq, IRQF_SHARED,
463*4882a593Smuzhiyun "psc-dma-capture", &psc_dma->capture);
464*4882a593Smuzhiyun rc |= request_irq(psc_dma->playback.irq, &psc_dma_bcom_irq, IRQF_SHARED,
465*4882a593Smuzhiyun "psc-dma-playback", &psc_dma->playback);
466*4882a593Smuzhiyun if (rc) {
467*4882a593Smuzhiyun ret = -ENODEV;
468*4882a593Smuzhiyun goto out_irq;
469*4882a593Smuzhiyun }
470*4882a593Smuzhiyun
471*4882a593Smuzhiyun /* Save what we've done so it can be found again later */
472*4882a593Smuzhiyun dev_set_drvdata(&op->dev, psc_dma);
473*4882a593Smuzhiyun
474*4882a593Smuzhiyun /* Tell the ASoC OF helpers about it */
475*4882a593Smuzhiyun return devm_snd_soc_register_component(&op->dev,
476*4882a593Smuzhiyun &mpc5200_audio_dma_component, NULL, 0);
477*4882a593Smuzhiyun out_irq:
478*4882a593Smuzhiyun free_irq(psc_dma->irq, psc_dma);
479*4882a593Smuzhiyun free_irq(psc_dma->capture.irq, &psc_dma->capture);
480*4882a593Smuzhiyun free_irq(psc_dma->playback.irq, &psc_dma->playback);
481*4882a593Smuzhiyun out_free:
482*4882a593Smuzhiyun kfree(psc_dma);
483*4882a593Smuzhiyun out_unmap:
484*4882a593Smuzhiyun iounmap(regs);
485*4882a593Smuzhiyun return ret;
486*4882a593Smuzhiyun }
487*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(mpc5200_audio_dma_create);
488*4882a593Smuzhiyun
mpc5200_audio_dma_destroy(struct platform_device * op)489*4882a593Smuzhiyun int mpc5200_audio_dma_destroy(struct platform_device *op)
490*4882a593Smuzhiyun {
491*4882a593Smuzhiyun struct psc_dma *psc_dma = dev_get_drvdata(&op->dev);
492*4882a593Smuzhiyun
493*4882a593Smuzhiyun dev_dbg(&op->dev, "mpc5200_audio_dma_destroy()\n");
494*4882a593Smuzhiyun
495*4882a593Smuzhiyun bcom_gen_bd_rx_release(psc_dma->capture.bcom_task);
496*4882a593Smuzhiyun bcom_gen_bd_tx_release(psc_dma->playback.bcom_task);
497*4882a593Smuzhiyun
498*4882a593Smuzhiyun /* Release irqs */
499*4882a593Smuzhiyun free_irq(psc_dma->irq, psc_dma);
500*4882a593Smuzhiyun free_irq(psc_dma->capture.irq, &psc_dma->capture);
501*4882a593Smuzhiyun free_irq(psc_dma->playback.irq, &psc_dma->playback);
502*4882a593Smuzhiyun
503*4882a593Smuzhiyun iounmap(psc_dma->psc_regs);
504*4882a593Smuzhiyun kfree(psc_dma);
505*4882a593Smuzhiyun dev_set_drvdata(&op->dev, NULL);
506*4882a593Smuzhiyun
507*4882a593Smuzhiyun return 0;
508*4882a593Smuzhiyun }
509*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(mpc5200_audio_dma_destroy);
510*4882a593Smuzhiyun
511*4882a593Smuzhiyun MODULE_AUTHOR("Grant Likely <grant.likely@secretlab.ca>");
512*4882a593Smuzhiyun MODULE_DESCRIPTION("Freescale MPC5200 PSC in DMA mode ASoC Driver");
513*4882a593Smuzhiyun MODULE_LICENSE("GPL");
514