1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * PDM Microphone Interface for the NXP i.MX SoC 4*4882a593Smuzhiyun * Copyright 2018 NXP 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _FSL_MICFIL_H 8*4882a593Smuzhiyun #define _FSL_MICFIL_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* MICFIL Register Map */ 11*4882a593Smuzhiyun #define REG_MICFIL_CTRL1 0x00 12*4882a593Smuzhiyun #define REG_MICFIL_CTRL2 0x04 13*4882a593Smuzhiyun #define REG_MICFIL_STAT 0x08 14*4882a593Smuzhiyun #define REG_MICFIL_FIFO_CTRL 0x10 15*4882a593Smuzhiyun #define REG_MICFIL_FIFO_STAT 0x14 16*4882a593Smuzhiyun #define REG_MICFIL_DATACH0 0x24 17*4882a593Smuzhiyun #define REG_MICFIL_DATACH1 0x28 18*4882a593Smuzhiyun #define REG_MICFIL_DATACH2 0x2C 19*4882a593Smuzhiyun #define REG_MICFIL_DATACH3 0x30 20*4882a593Smuzhiyun #define REG_MICFIL_DATACH4 0x34 21*4882a593Smuzhiyun #define REG_MICFIL_DATACH5 0x38 22*4882a593Smuzhiyun #define REG_MICFIL_DATACH6 0x3C 23*4882a593Smuzhiyun #define REG_MICFIL_DATACH7 0x40 24*4882a593Smuzhiyun #define REG_MICFIL_DC_CTRL 0x64 25*4882a593Smuzhiyun #define REG_MICFIL_OUT_CTRL 0x74 26*4882a593Smuzhiyun #define REG_MICFIL_OUT_STAT 0x7C 27*4882a593Smuzhiyun #define REG_MICFIL_VAD0_CTRL1 0x90 28*4882a593Smuzhiyun #define REG_MICFIL_VAD0_CTRL2 0x94 29*4882a593Smuzhiyun #define REG_MICFIL_VAD0_STAT 0x98 30*4882a593Smuzhiyun #define REG_MICFIL_VAD0_SCONFIG 0x9C 31*4882a593Smuzhiyun #define REG_MICFIL_VAD0_NCONFIG 0xA0 32*4882a593Smuzhiyun #define REG_MICFIL_VAD0_NDATA 0xA4 33*4882a593Smuzhiyun #define REG_MICFIL_VAD0_ZCD 0xA8 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* MICFIL Control Register 1 -- REG_MICFILL_CTRL1 0x00 */ 36*4882a593Smuzhiyun #define MICFIL_CTRL1_MDIS_SHIFT 31 37*4882a593Smuzhiyun #define MICFIL_CTRL1_MDIS_MASK BIT(MICFIL_CTRL1_MDIS_SHIFT) 38*4882a593Smuzhiyun #define MICFIL_CTRL1_MDIS BIT(MICFIL_CTRL1_MDIS_SHIFT) 39*4882a593Smuzhiyun #define MICFIL_CTRL1_DOZEN_SHIFT 30 40*4882a593Smuzhiyun #define MICFIL_CTRL1_DOZEN_MASK BIT(MICFIL_CTRL1_DOZEN_SHIFT) 41*4882a593Smuzhiyun #define MICFIL_CTRL1_DOZEN BIT(MICFIL_CTRL1_DOZEN_SHIFT) 42*4882a593Smuzhiyun #define MICFIL_CTRL1_PDMIEN_SHIFT 29 43*4882a593Smuzhiyun #define MICFIL_CTRL1_PDMIEN_MASK BIT(MICFIL_CTRL1_PDMIEN_SHIFT) 44*4882a593Smuzhiyun #define MICFIL_CTRL1_PDMIEN BIT(MICFIL_CTRL1_PDMIEN_SHIFT) 45*4882a593Smuzhiyun #define MICFIL_CTRL1_DBG_SHIFT 28 46*4882a593Smuzhiyun #define MICFIL_CTRL1_DBG_MASK BIT(MICFIL_CTRL1_DBG_SHIFT) 47*4882a593Smuzhiyun #define MICFIL_CTRL1_DBG BIT(MICFIL_CTRL1_DBG_SHIFT) 48*4882a593Smuzhiyun #define MICFIL_CTRL1_SRES_SHIFT 27 49*4882a593Smuzhiyun #define MICFIL_CTRL1_SRES_MASK BIT(MICFIL_CTRL1_SRES_SHIFT) 50*4882a593Smuzhiyun #define MICFIL_CTRL1_SRES BIT(MICFIL_CTRL1_SRES_SHIFT) 51*4882a593Smuzhiyun #define MICFIL_CTRL1_DBGE_SHIFT 26 52*4882a593Smuzhiyun #define MICFIL_CTRL1_DBGE_MASK BIT(MICFIL_CTRL1_DBGE_SHIFT) 53*4882a593Smuzhiyun #define MICFIL_CTRL1_DBGE BIT(MICFIL_CTRL1_DBGE_SHIFT) 54*4882a593Smuzhiyun #define MICFIL_CTRL1_DISEL_SHIFT 24 55*4882a593Smuzhiyun #define MICFIL_CTRL1_DISEL_WIDTH 2 56*4882a593Smuzhiyun #define MICFIL_CTRL1_DISEL_MASK ((BIT(MICFIL_CTRL1_DISEL_WIDTH) - 1) \ 57*4882a593Smuzhiyun << MICFIL_CTRL1_DISEL_SHIFT) 58*4882a593Smuzhiyun #define MICFIL_CTRL1_DISEL(v) (((v) << MICFIL_CTRL1_DISEL_SHIFT) \ 59*4882a593Smuzhiyun & MICFIL_CTRL1_DISEL_MASK) 60*4882a593Smuzhiyun #define MICFIL_CTRL1_ERREN_SHIFT 23 61*4882a593Smuzhiyun #define MICFIL_CTRL1_ERREN_MASK BIT(MICFIL_CTRL1_ERREN_SHIFT) 62*4882a593Smuzhiyun #define MICFIL_CTRL1_ERREN BIT(MICFIL_CTRL1_ERREN_SHIFT) 63*4882a593Smuzhiyun #define MICFIL_CTRL1_CHEN_SHIFT 0 64*4882a593Smuzhiyun #define MICFIL_CTRL1_CHEN_WIDTH 8 65*4882a593Smuzhiyun #define MICFIL_CTRL1_CHEN_MASK(x) (BIT(x) << MICFIL_CTRL1_CHEN_SHIFT) 66*4882a593Smuzhiyun #define MICFIL_CTRL1_CHEN(x) (MICFIL_CTRL1_CHEN_MASK(x)) 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun /* MICFIL Control Register 2 -- REG_MICFILL_CTRL2 0x04 */ 69*4882a593Smuzhiyun #define MICFIL_CTRL2_QSEL_SHIFT 25 70*4882a593Smuzhiyun #define MICFIL_CTRL2_QSEL_WIDTH 3 71*4882a593Smuzhiyun #define MICFIL_CTRL2_QSEL_MASK ((BIT(MICFIL_CTRL2_QSEL_WIDTH) - 1) \ 72*4882a593Smuzhiyun << MICFIL_CTRL2_QSEL_SHIFT) 73*4882a593Smuzhiyun #define MICFIL_HIGH_QUALITY BIT(MICFIL_CTRL2_QSEL_SHIFT) 74*4882a593Smuzhiyun #define MICFIL_MEDIUM_QUALITY (0 << MICFIL_CTRL2_QSEL_SHIFT) 75*4882a593Smuzhiyun #define MICFIL_LOW_QUALITY (7 << MICFIL_CTRL2_QSEL_SHIFT) 76*4882a593Smuzhiyun #define MICFIL_VLOW0_QUALITY (6 << MICFIL_CTRL2_QSEL_SHIFT) 77*4882a593Smuzhiyun #define MICFIL_VLOW1_QUALITY (5 << MICFIL_CTRL2_QSEL_SHIFT) 78*4882a593Smuzhiyun #define MICFIL_VLOW2_QUALITY (4 << MICFIL_CTRL2_QSEL_SHIFT) 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun #define MICFIL_CTRL2_CICOSR_SHIFT 16 81*4882a593Smuzhiyun #define MICFIL_CTRL2_CICOSR_WIDTH 4 82*4882a593Smuzhiyun #define MICFIL_CTRL2_CICOSR_MASK ((BIT(MICFIL_CTRL2_CICOSR_WIDTH) - 1) \ 83*4882a593Smuzhiyun << MICFIL_CTRL2_CICOSR_SHIFT) 84*4882a593Smuzhiyun #define MICFIL_CTRL2_CICOSR(v) (((v) << MICFIL_CTRL2_CICOSR_SHIFT) \ 85*4882a593Smuzhiyun & MICFIL_CTRL2_CICOSR_MASK) 86*4882a593Smuzhiyun #define MICFIL_CTRL2_CLKDIV_SHIFT 0 87*4882a593Smuzhiyun #define MICFIL_CTRL2_CLKDIV_WIDTH 8 88*4882a593Smuzhiyun #define MICFIL_CTRL2_CLKDIV_MASK ((BIT(MICFIL_CTRL2_CLKDIV_WIDTH) - 1) \ 89*4882a593Smuzhiyun << MICFIL_CTRL2_CLKDIV_SHIFT) 90*4882a593Smuzhiyun #define MICFIL_CTRL2_CLKDIV(v) (((v) << MICFIL_CTRL2_CLKDIV_SHIFT) \ 91*4882a593Smuzhiyun & MICFIL_CTRL2_CLKDIV_MASK) 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun /* MICFIL Status Register -- REG_MICFIL_STAT 0x08 */ 94*4882a593Smuzhiyun #define MICFIL_STAT_BSY_FIL_SHIFT 31 95*4882a593Smuzhiyun #define MICFIL_STAT_BSY_FIL_MASK BIT(MICFIL_STAT_BSY_FIL_SHIFT) 96*4882a593Smuzhiyun #define MICFIL_STAT_BSY_FIL BIT(MICFIL_STAT_BSY_FIL_SHIFT) 97*4882a593Smuzhiyun #define MICFIL_STAT_FIR_RDY_SHIFT 30 98*4882a593Smuzhiyun #define MICFIL_STAT_FIR_RDY_MASK BIT(MICFIL_STAT_FIR_RDY_SHIFT) 99*4882a593Smuzhiyun #define MICFIL_STAT_FIR_RDY BIT(MICFIL_STAT_FIR_RDY_SHIFT) 100*4882a593Smuzhiyun #define MICFIL_STAT_LOWFREQF_SHIFT 29 101*4882a593Smuzhiyun #define MICFIL_STAT_LOWFREQF_MASK BIT(MICFIL_STAT_LOWFREQF_SHIFT) 102*4882a593Smuzhiyun #define MICFIL_STAT_LOWFREQF BIT(MICFIL_STAT_LOWFREQF_SHIFT) 103*4882a593Smuzhiyun #define MICFIL_STAT_CHXF_SHIFT(v) (v) 104*4882a593Smuzhiyun #define MICFIL_STAT_CHXF_MASK(v) BIT(MICFIL_STAT_CHXF_SHIFT(v)) 105*4882a593Smuzhiyun #define MICFIL_STAT_CHXF(v) BIT(MICFIL_STAT_CHXF_SHIFT(v)) 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun /* MICFIL FIFO Control Register -- REG_MICFIL_FIFO_CTRL 0x10 */ 108*4882a593Smuzhiyun #define MICFIL_FIFO_CTRL_FIFOWMK_SHIFT 0 109*4882a593Smuzhiyun #define MICFIL_FIFO_CTRL_FIFOWMK_WIDTH 3 110*4882a593Smuzhiyun #define MICFIL_FIFO_CTRL_FIFOWMK_MASK ((BIT(MICFIL_FIFO_CTRL_FIFOWMK_WIDTH) - 1) \ 111*4882a593Smuzhiyun << MICFIL_FIFO_CTRL_FIFOWMK_SHIFT) 112*4882a593Smuzhiyun #define MICFIL_FIFO_CTRL_FIFOWMK(v) (((v) << MICFIL_FIFO_CTRL_FIFOWMK_SHIFT) \ 113*4882a593Smuzhiyun & MICFIL_FIFO_CTRL_FIFOWMK_MASK) 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun /* MICFIL FIFO Status Register -- REG_MICFIL_FIFO_STAT 0x14 */ 116*4882a593Smuzhiyun #define MICFIL_FIFO_STAT_FIFOX_OVER_SHIFT(v) (v) 117*4882a593Smuzhiyun #define MICFIL_FIFO_STAT_FIFOX_OVER_MASK(v) BIT(MICFIL_FIFO_STAT_FIFOX_OVER_SHIFT(v)) 118*4882a593Smuzhiyun #define MICFIL_FIFO_STAT_FIFOX_UNDER_SHIFT(v) ((v) + 8) 119*4882a593Smuzhiyun #define MICFIL_FIFO_STAT_FIFOX_UNDER_MASK(v) BIT(MICFIL_FIFO_STAT_FIFOX_UNDER_SHIFT(v)) 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun /* MICFIL HWVAD0 Control 1 Register -- REG_MICFIL_VAD0_CTRL1*/ 122*4882a593Smuzhiyun #define MICFIL_VAD0_CTRL1_CHSEL_SHIFT 24 123*4882a593Smuzhiyun #define MICFIL_VAD0_CTRL1_CHSEL_WIDTH 3 124*4882a593Smuzhiyun #define MICFIL_VAD0_CTRL1_CHSEL_MASK ((BIT(MICFIL_VAD0_CTRL1_CHSEL_WIDTH) - 1) \ 125*4882a593Smuzhiyun << MICFIL_VAD0_CTRL1_CHSEL_SHIFT) 126*4882a593Smuzhiyun #define MICFIL_VAD0_CTRL1_CHSEL(v) (((v) << MICFIL_VAD0_CTRL1_CHSEL_SHIFT) \ 127*4882a593Smuzhiyun & MICFIL_VAD0_CTRL1_CHSEL_MASK) 128*4882a593Smuzhiyun #define MICFIL_VAD0_CTRL1_CICOSR_SHIFT 16 129*4882a593Smuzhiyun #define MICFIL_VAD0_CTRL1_CICOSR_WIDTH 4 130*4882a593Smuzhiyun #define MICFIL_VAD0_CTRL1_CICOSR_MASK ((BIT(MICFIL_VAD0_CTRL1_CICOSR_WIDTH) - 1) \ 131*4882a593Smuzhiyun << MICFIL_VAD0_CTRL1_CICOSR_SHIFT) 132*4882a593Smuzhiyun #define MICFIL_VAD0_CTRL1_CICOSR(v) (((v) << MICFIL_VAD0_CTRL1_CICOSR_SHIFT) \ 133*4882a593Smuzhiyun & MICFIL_VAD0_CTRL1_CICOSR_MASK) 134*4882a593Smuzhiyun #define MICFIL_VAD0_CTRL1_INITT_SHIFT 8 135*4882a593Smuzhiyun #define MICFIL_VAD0_CTRL1_INITT_WIDTH 5 136*4882a593Smuzhiyun #define MICFIL_VAD0_CTRL1_INITT_MASK ((BIT(MICFIL_VAD0_CTRL1_INITT_WIDTH) - 1) \ 137*4882a593Smuzhiyun << MICFIL_VAD0_CTRL1_INITT_SHIFT) 138*4882a593Smuzhiyun #define MICFIL_VAD0_CTRL1_INITT(v) (((v) << MICFIL_VAD0_CTRL1_INITT_SHIFT) \ 139*4882a593Smuzhiyun & MICFIL_VAD0_CTRL1_INITT_MASK) 140*4882a593Smuzhiyun #define MICFIL_VAD0_CTRL1_ST10_SHIFT 4 141*4882a593Smuzhiyun #define MICFIL_VAD0_CTRL1_ST10_MASK BIT(MICFIL_VAD0_CTRL1_ST10_SHIFT) 142*4882a593Smuzhiyun #define MICFIL_VAD0_CTRL1_ST10 BIT(MICFIL_VAD0_CTRL1_ST10_SHIFT) 143*4882a593Smuzhiyun #define MICFIL_VAD0_CTRL1_ERIE_SHIFT 3 144*4882a593Smuzhiyun #define MICFIL_VAD0_CTRL1_ERIE_MASK BIT(MICFIL_VAD0_CTRL1_ERIE_SHIFT) 145*4882a593Smuzhiyun #define MICFIL_VAD0_CTRL1_ERIE BIT(MICFIL_VAD0_CTRL1_ERIE_SHIFT) 146*4882a593Smuzhiyun #define MICFIL_VAD0_CTRL1_IE_SHIFT 2 147*4882a593Smuzhiyun #define MICFIL_VAD0_CTRL1_IE_MASK BIT(MICFIL_VAD0_CTRL1_IE_SHIFT) 148*4882a593Smuzhiyun #define MICFIL_VAD0_CTRL1_IE BIT(MICFIL_VAD0_CTRL1_IE_SHIFT) 149*4882a593Smuzhiyun #define MICFIL_VAD0_CTRL1_RST_SHIFT 1 150*4882a593Smuzhiyun #define MICFIL_VAD0_CTRL1_RST_MASK BIT(MICFIL_VAD0_CTRL1_RST_SHIFT) 151*4882a593Smuzhiyun #define MICFIL_VAD0_CTRL1_RST BIT(MICFIL_VAD0_CTRL1_RST_SHIFT) 152*4882a593Smuzhiyun #define MICFIL_VAD0_CTRL1_EN_SHIFT 0 153*4882a593Smuzhiyun #define MICFIL_VAD0_CTRL1_EN_MASK BIT(MICFIL_VAD0_CTRL1_EN_SHIFT) 154*4882a593Smuzhiyun #define MICFIL_VAD0_CTRL1_EN BIT(MICFIL_VAD0_CTRL1_EN_SHIFT) 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun /* MICFIL HWVAD0 Control 2 Register -- REG_MICFIL_VAD0_CTRL2*/ 157*4882a593Smuzhiyun #define MICFIL_VAD0_CTRL2_FRENDIS_SHIFT 31 158*4882a593Smuzhiyun #define MICFIL_VAD0_CTRL2_FRENDIS_MASK BIT(MICFIL_VAD0_CTRL2_FRENDIS_SHIFT) 159*4882a593Smuzhiyun #define MICFIL_VAD0_CTRL2_FRENDIS BIT(MICFIL_VAD0_CTRL2_FRENDIS_SHIFT) 160*4882a593Smuzhiyun #define MICFIL_VAD0_CTRL2_PREFEN_SHIFT 30 161*4882a593Smuzhiyun #define MICFIL_VAD0_CTRL2_PREFEN_MASK BIT(MICFIL_VAD0_CTRL2_PREFEN_SHIFT) 162*4882a593Smuzhiyun #define MICFIL_VAD0_CTRL2_PREFEN BIT(MICFIL_VAD0_CTRL2_PREFEN_SHIFT) 163*4882a593Smuzhiyun #define MICFIL_VAD0_CTRL2_FOUTDIS_SHIFT 28 164*4882a593Smuzhiyun #define MICFIL_VAD0_CTRL2_FOUTDIS_MASK BIT(MICFIL_VAD0_CTRL2_FOUTDIS_SHIFT) 165*4882a593Smuzhiyun #define MICFIL_VAD0_CTRL2_FOUTDIS BIT(MICFIL_VAD0_CTRL2_FOUTDIS_SHIFT) 166*4882a593Smuzhiyun #define MICFIL_VAD0_CTRL2_FRAMET_SHIFT 16 167*4882a593Smuzhiyun #define MICFIL_VAD0_CTRL2_FRAMET_WIDTH 6 168*4882a593Smuzhiyun #define MICFIL_VAD0_CTRL2_FRAMET_MASK ((BIT(MICFIL_VAD0_CTRL2_FRAMET_WIDTH) - 1) \ 169*4882a593Smuzhiyun << MICFIL_VAD0_CTRL2_FRAMET_SHIFT) 170*4882a593Smuzhiyun #define MICFIL_VAD0_CTRL2_FRAMET(v) (((v) << MICFIL_VAD0_CTRL2_FRAMET_SHIFT) \ 171*4882a593Smuzhiyun & MICFIL_VAD0_CTRL2_FRAMET_MASK) 172*4882a593Smuzhiyun #define MICFIL_VAD0_CTRL2_INPGAIN_SHIFT 8 173*4882a593Smuzhiyun #define MICFIL_VAD0_CTRL2_INPGAIN_WIDTH 4 174*4882a593Smuzhiyun #define MICFIL_VAD0_CTRL2_INPGAIN_MASK ((BIT(MICFIL_VAD0_CTRL2_INPGAIN_WIDTH) - 1) \ 175*4882a593Smuzhiyun << MICFIL_VAD0_CTRL2_INPGAIN_SHIFT) 176*4882a593Smuzhiyun #define MICFIL_VAD0_CTRL2_INPGAIN(v) (((v) << MICFIL_VAD0_CTRL2_INPGAIN_SHIFT) \ 177*4882a593Smuzhiyun & MICFIL_VAD0_CTRL2_INPGAIN_MASK) 178*4882a593Smuzhiyun #define MICFIL_VAD0_CTRL2_HPF_SHIFT 0 179*4882a593Smuzhiyun #define MICFIL_VAD0_CTRL2_HPF_WIDTH 2 180*4882a593Smuzhiyun #define MICFIL_VAD0_CTRL2_HPF_MASK ((BIT(MICFIL_VAD0_CTRL2_HPF_WIDTH) - 1) \ 181*4882a593Smuzhiyun << MICFIL_VAD0_CTRL2_HPF_SHIFT) 182*4882a593Smuzhiyun #define MICFIL_VAD0_CTRL2_HPF(v) (((v) << MICFIL_VAD0_CTRL2_HPF_SHIFT) \ 183*4882a593Smuzhiyun & MICFIL_VAD0_CTRL2_HPF_MASK) 184*4882a593Smuzhiyun 185*4882a593Smuzhiyun /* MICFIL HWVAD0 Signal CONFIG Register -- REG_MICFIL_VAD0_SCONFIG */ 186*4882a593Smuzhiyun #define MICFIL_VAD0_SCONFIG_SFILEN_SHIFT 31 187*4882a593Smuzhiyun #define MICFIL_VAD0_SCONFIG_SFILEN_MASK BIT(MICFIL_VAD0_SCONFIG_SFILEN_SHIFT) 188*4882a593Smuzhiyun #define MICFIL_VAD0_SCONFIG_SFILEN BIT(MICFIL_VAD0_SCONFIG_SFILEN_SHIFT) 189*4882a593Smuzhiyun #define MICFIL_VAD0_SCONFIG_SMAXEN_SHIFT 30 190*4882a593Smuzhiyun #define MICFIL_VAD0_SCONFIG_SMAXEN_MASK BIT(MICFIL_VAD0_SCONFIG_SMAXEN_SHIFT) 191*4882a593Smuzhiyun #define MICFIL_VAD0_SCONFIG_SMAXEN BIT(MICFIL_VAD0_SCONFIG_SMAXEN_SHIFT) 192*4882a593Smuzhiyun #define MICFIL_VAD0_SCONFIG_SGAIN_SHIFT 0 193*4882a593Smuzhiyun #define MICFIL_VAD0_SCONFIG_SGAIN_WIDTH 4 194*4882a593Smuzhiyun #define MICFIL_VAD0_SCONFIG_SGAIN_MASK ((BIT(MICFIL_VAD0_SCONFIG_SGAIN_WIDTH) - 1) \ 195*4882a593Smuzhiyun << MICFIL_VAD0_SCONFIG_SGAIN_SHIFT) 196*4882a593Smuzhiyun #define MICFIL_VAD0_SCONFIG_SGAIN(v) (((v) << MICFIL_VAD0_SCONFIG_SGAIN_SHIFT) \ 197*4882a593Smuzhiyun & MICFIL_VAD0_SCONFIG_SGAIN_MASK) 198*4882a593Smuzhiyun 199*4882a593Smuzhiyun /* MICFIL HWVAD0 Noise CONFIG Register -- REG_MICFIL_VAD0_NCONFIG */ 200*4882a593Smuzhiyun #define MICFIL_VAD0_NCONFIG_NFILAUT_SHIFT 31 201*4882a593Smuzhiyun #define MICFIL_VAD0_NCONFIG_NFILAUT_MASK BIT(MICFIL_VAD0_NCONFIG_NFILAUT_SHIFT) 202*4882a593Smuzhiyun #define MICFIL_VAD0_NCONFIG_NFILAUT BIT(MICFIL_VAD0_NCONFIG_NFILAUT_SHIFT) 203*4882a593Smuzhiyun #define MICFIL_VAD0_NCONFIG_NMINEN_SHIFT 30 204*4882a593Smuzhiyun #define MICFIL_VAD0_NCONFIG_NMINEN_MASK BIT(MICFIL_VAD0_NCONFIG_NMINEN_SHIFT) 205*4882a593Smuzhiyun #define MICFIL_VAD0_NCONFIG_NMINEN BIT(MICFIL_VAD0_NCONFIG_NMINEN_SHIFT) 206*4882a593Smuzhiyun #define MICFIL_VAD0_NCONFIG_NDECEN_SHIFT 29 207*4882a593Smuzhiyun #define MICFIL_VAD0_NCONFIG_NDECEN_MASK BIT(MICFIL_VAD0_NCONFIG_NDECEN_SHIFT) 208*4882a593Smuzhiyun #define MICFIL_VAD0_NCONFIG_NDECEN BIT(MICFIL_VAD0_NCONFIG_NDECEN_SHIFT) 209*4882a593Smuzhiyun #define MICFIL_VAD0_NCONFIG_NOREN_SHIFT 28 210*4882a593Smuzhiyun #define MICFIL_VAD0_NCONFIG_NOREN BIT(MICFIL_VAD0_NCONFIG_NOREN_SHIFT) 211*4882a593Smuzhiyun #define MICFIL_VAD0_NCONFIG_NFILADJ_SHIFT 8 212*4882a593Smuzhiyun #define MICFIL_VAD0_NCONFIG_NFILADJ_WIDTH 5 213*4882a593Smuzhiyun #define MICFIL_VAD0_NCONFIG_NFILADJ_MASK ((BIT(MICFIL_VAD0_NCONFIG_NFILADJ_WIDTH) - 1) \ 214*4882a593Smuzhiyun << MICFIL_VAD0_NCONFIG_NFILADJ_SHIFT) 215*4882a593Smuzhiyun #define MICFIL_VAD0_NCONFIG_NFILADJ(v) (((v) << MICFIL_VAD0_NCONFIG_NFILADJ_SHIFT) \ 216*4882a593Smuzhiyun & MICFIL_VAD0_NCONFIG_NFILADJ_MASK) 217*4882a593Smuzhiyun #define MICFIL_VAD0_NCONFIG_NGAIN_SHIFT 0 218*4882a593Smuzhiyun #define MICFIL_VAD0_NCONFIG_NGAIN_WIDTH 4 219*4882a593Smuzhiyun #define MICFIL_VAD0_NCONFIG_NGAIN_MASK ((BIT(MICFIL_VAD0_NCONFIG_NGAIN_WIDTH) - 1) \ 220*4882a593Smuzhiyun << MICFIL_VAD0_NCONFIG_NGAIN_SHIFT) 221*4882a593Smuzhiyun #define MICFIL_VAD0_NCONFIG_NGAIN(v) (((v) << MICFIL_VAD0_NCONFIG_NGAIN_SHIFT) \ 222*4882a593Smuzhiyun & MICFIL_VAD0_NCONFIG_NGAIN_MASK) 223*4882a593Smuzhiyun 224*4882a593Smuzhiyun /* MICFIL HWVAD0 Zero-Crossing Detector - REG_MICFIL_VAD0_ZCD */ 225*4882a593Smuzhiyun #define MICFIL_VAD0_ZCD_ZCDTH_SHIFT 16 226*4882a593Smuzhiyun #define MICFIL_VAD0_ZCD_ZCDTH_WIDTH 10 227*4882a593Smuzhiyun #define MICFIL_VAD0_ZCD_ZCDTH_MASK ((BIT(MICFIL_VAD0_ZCD_ZCDTH_WIDTH) - 1) \ 228*4882a593Smuzhiyun << MICFIL_VAD0_ZCD_ZCDTH_SHIFT) 229*4882a593Smuzhiyun #define MICFIL_VAD0_ZCD_ZCDTH(v) (((v) << MICFIL_VAD0_ZCD_ZCDTH_SHIFT)\ 230*4882a593Smuzhiyun & MICFIL_VAD0_ZCD_ZCDTH_MASK) 231*4882a593Smuzhiyun #define MICFIL_VAD0_ZCD_ZCDADJ_SHIFT 8 232*4882a593Smuzhiyun #define MICFIL_VAD0_ZCD_ZCDADJ_WIDTH 4 233*4882a593Smuzhiyun #define MICFIL_VAD0_ZCD_ZCDADJ_MASK ((BIT(MICFIL_VAD0_ZCD_ZCDADJ_WIDTH) - 1)\ 234*4882a593Smuzhiyun << MICFIL_VAD0_ZCD_ZCDADJ_SHIFT) 235*4882a593Smuzhiyun #define MICFIL_VAD0_ZCD_ZCDADJ(v) (((v) << MICFIL_VAD0_ZCD_ZCDADJ_SHIFT)\ 236*4882a593Smuzhiyun & MICFIL_VAD0_ZCD_ZCDADJ_MASK) 237*4882a593Smuzhiyun #define MICFIL_VAD0_ZCD_ZCDAND_SHIFT 4 238*4882a593Smuzhiyun #define MICFIL_VAD0_ZCD_ZCDAND_MASK BIT(MICFIL_VAD0_ZCD_ZCDAND_SHIFT) 239*4882a593Smuzhiyun #define MICFIL_VAD0_ZCD_ZCDAND BIT(MICFIL_VAD0_ZCD_ZCDAND_SHIFT) 240*4882a593Smuzhiyun #define MICFIL_VAD0_ZCD_ZCDAUT_SHIFT 2 241*4882a593Smuzhiyun #define MICFIL_VAD0_ZCD_ZCDAUT_MASK BIT(MICFIL_VAD0_ZCD_ZCDAUT_SHIFT) 242*4882a593Smuzhiyun #define MICFIL_VAD0_ZCD_ZCDAUT BIT(MICFIL_VAD0_ZCD_ZCDAUT_SHIFT) 243*4882a593Smuzhiyun #define MICFIL_VAD0_ZCD_ZCDEN_SHIFT 0 244*4882a593Smuzhiyun #define MICFIL_VAD0_ZCD_ZCDEN_MASK BIT(MICFIL_VAD0_ZCD_ZCDEN_SHIFT) 245*4882a593Smuzhiyun #define MICFIL_VAD0_ZCD_ZCDEN BIT(MICFIL_VAD0_ZCD_ZCDEN_SHIFT) 246*4882a593Smuzhiyun 247*4882a593Smuzhiyun /* MICFIL HWVAD0 Status Register - REG_MICFIL_VAD0_STAT */ 248*4882a593Smuzhiyun #define MICFIL_VAD0_STAT_INITF_SHIFT 31 249*4882a593Smuzhiyun #define MICFIL_VAD0_STAT_INITF_MASK BIT(MICFIL_VAD0_STAT_INITF_SHIFT) 250*4882a593Smuzhiyun #define MICFIL_VAD0_STAT_INITF BIT(MICFIL_VAD0_STAT_INITF_SHIFT) 251*4882a593Smuzhiyun #define MICFIL_VAD0_STAT_INSATF_SHIFT 16 252*4882a593Smuzhiyun #define MICFIL_VAD0_STAT_INSATF_MASK BIT(MICFIL_VAD0_STAT_INSATF_SHIFT) 253*4882a593Smuzhiyun #define MICFIL_VAD0_STAT_INSATF BIT(MICFIL_VAD0_STAT_INSATF_SHIFT) 254*4882a593Smuzhiyun #define MICFIL_VAD0_STAT_EF_SHIFT 15 255*4882a593Smuzhiyun #define MICFIL_VAD0_STAT_EF_MASK BIT(MICFIL_VAD0_STAT_EF_SHIFT) 256*4882a593Smuzhiyun #define MICFIL_VAD0_STAT_EF BIT(MICFIL_VAD0_STAT_EF_SHIFT) 257*4882a593Smuzhiyun #define MICFIL_VAD0_STAT_IF_SHIFT 0 258*4882a593Smuzhiyun #define MICFIL_VAD0_STAT_IF_MASK BIT(MICFIL_VAD0_STAT_IF_SHIFT) 259*4882a593Smuzhiyun #define MICFIL_VAD0_STAT_IF BIT(MICFIL_VAD0_STAT_IF_SHIFT) 260*4882a593Smuzhiyun 261*4882a593Smuzhiyun /* MICFIL Output Control Register */ 262*4882a593Smuzhiyun #define MICFIL_OUTGAIN_CHX_SHIFT(v) (4 * (v)) 263*4882a593Smuzhiyun 264*4882a593Smuzhiyun /* Constants */ 265*4882a593Smuzhiyun #define MICFIL_DMA_IRQ_DISABLED(v) ((v) & MICFIL_CTRL1_DISEL_MASK) 266*4882a593Smuzhiyun #define MICFIL_DMA_ENABLED(v) ((0x1 << MICFIL_CTRL1_DISEL_SHIFT) \ 267*4882a593Smuzhiyun == ((v) & MICFIL_CTRL1_DISEL_MASK)) 268*4882a593Smuzhiyun #define MICFIL_IRQ_ENABLED(v) ((0x2 << MICFIL_CTRL1_DISEL_SHIFT) \ 269*4882a593Smuzhiyun == ((v) & MICFIL_CTRL1_DISEL_MASK)) 270*4882a593Smuzhiyun #define MICFIL_OUTPUT_CHANNELS 8 271*4882a593Smuzhiyun #define MICFIL_FIFO_NUM 8 272*4882a593Smuzhiyun 273*4882a593Smuzhiyun #define FIFO_PTRWID 3 274*4882a593Smuzhiyun #define FIFO_LEN BIT(FIFO_PTRWID) 275*4882a593Smuzhiyun 276*4882a593Smuzhiyun #define MICFIL_IRQ_LINES 2 277*4882a593Smuzhiyun #define MICFIL_MAX_RETRY 25 278*4882a593Smuzhiyun #define MICFIL_SLEEP_MIN 90000 /* in us */ 279*4882a593Smuzhiyun #define MICFIL_SLEEP_MAX 100000 /* in us */ 280*4882a593Smuzhiyun #define MICFIL_DMA_MAXBURST_RX 6 281*4882a593Smuzhiyun #define MICFIL_CTRL2_OSR_DEFAULT (0 << MICFIL_CTRL2_CICOSR_SHIFT) 282*4882a593Smuzhiyun 283*4882a593Smuzhiyun #endif /* _FSL_MICFIL_H */ 284