1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * mpc8610-pcm.h - ALSA PCM interface for the Freescale MPC8610 SoC 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef _MPC8610_PCM_H 7*4882a593Smuzhiyun #define _MPC8610_PCM_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun struct ccsr_dma { 10*4882a593Smuzhiyun u8 res0[0x100]; 11*4882a593Smuzhiyun struct ccsr_dma_channel { 12*4882a593Smuzhiyun __be32 mr; /* Mode register */ 13*4882a593Smuzhiyun __be32 sr; /* Status register */ 14*4882a593Smuzhiyun __be32 eclndar; /* Current link descriptor extended addr reg */ 15*4882a593Smuzhiyun __be32 clndar; /* Current link descriptor address register */ 16*4882a593Smuzhiyun __be32 satr; /* Source attributes register */ 17*4882a593Smuzhiyun __be32 sar; /* Source address register */ 18*4882a593Smuzhiyun __be32 datr; /* Destination attributes register */ 19*4882a593Smuzhiyun __be32 dar; /* Destination address register */ 20*4882a593Smuzhiyun __be32 bcr; /* Byte count register */ 21*4882a593Smuzhiyun __be32 enlndar; /* Next link descriptor extended address reg */ 22*4882a593Smuzhiyun __be32 nlndar; /* Next link descriptor address register */ 23*4882a593Smuzhiyun u8 res1[4]; 24*4882a593Smuzhiyun __be32 eclsdar; /* Current list descriptor extended addr reg */ 25*4882a593Smuzhiyun __be32 clsdar; /* Current list descriptor address register */ 26*4882a593Smuzhiyun __be32 enlsdar; /* Next list descriptor extended address reg */ 27*4882a593Smuzhiyun __be32 nlsdar; /* Next list descriptor address register */ 28*4882a593Smuzhiyun __be32 ssr; /* Source stride register */ 29*4882a593Smuzhiyun __be32 dsr; /* Destination stride register */ 30*4882a593Smuzhiyun u8 res2[0x38]; 31*4882a593Smuzhiyun } channel[4]; 32*4882a593Smuzhiyun __be32 dgsr; 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #define CCSR_DMA_MR_BWC_DISABLED 0x0F000000 36*4882a593Smuzhiyun #define CCSR_DMA_MR_BWC_SHIFT 24 37*4882a593Smuzhiyun #define CCSR_DMA_MR_BWC_MASK 0x0F000000 38*4882a593Smuzhiyun #define CCSR_DMA_MR_BWC(x) \ 39*4882a593Smuzhiyun ((ilog2(x) << CCSR_DMA_MR_BWC_SHIFT) & CCSR_DMA_MR_BWC_MASK) 40*4882a593Smuzhiyun #define CCSR_DMA_MR_EMP_EN 0x00200000 41*4882a593Smuzhiyun #define CCSR_DMA_MR_EMS_EN 0x00040000 42*4882a593Smuzhiyun #define CCSR_DMA_MR_DAHTS_MASK 0x00030000 43*4882a593Smuzhiyun #define CCSR_DMA_MR_DAHTS_1 0x00000000 44*4882a593Smuzhiyun #define CCSR_DMA_MR_DAHTS_2 0x00010000 45*4882a593Smuzhiyun #define CCSR_DMA_MR_DAHTS_4 0x00020000 46*4882a593Smuzhiyun #define CCSR_DMA_MR_DAHTS_8 0x00030000 47*4882a593Smuzhiyun #define CCSR_DMA_MR_SAHTS_MASK 0x0000C000 48*4882a593Smuzhiyun #define CCSR_DMA_MR_SAHTS_1 0x00000000 49*4882a593Smuzhiyun #define CCSR_DMA_MR_SAHTS_2 0x00004000 50*4882a593Smuzhiyun #define CCSR_DMA_MR_SAHTS_4 0x00008000 51*4882a593Smuzhiyun #define CCSR_DMA_MR_SAHTS_8 0x0000C000 52*4882a593Smuzhiyun #define CCSR_DMA_MR_DAHE 0x00002000 53*4882a593Smuzhiyun #define CCSR_DMA_MR_SAHE 0x00001000 54*4882a593Smuzhiyun #define CCSR_DMA_MR_SRW 0x00000400 55*4882a593Smuzhiyun #define CCSR_DMA_MR_EOSIE 0x00000200 56*4882a593Smuzhiyun #define CCSR_DMA_MR_EOLNIE 0x00000100 57*4882a593Smuzhiyun #define CCSR_DMA_MR_EOLSIE 0x00000080 58*4882a593Smuzhiyun #define CCSR_DMA_MR_EIE 0x00000040 59*4882a593Smuzhiyun #define CCSR_DMA_MR_XFE 0x00000020 60*4882a593Smuzhiyun #define CCSR_DMA_MR_CDSM_SWSM 0x00000010 61*4882a593Smuzhiyun #define CCSR_DMA_MR_CA 0x00000008 62*4882a593Smuzhiyun #define CCSR_DMA_MR_CTM 0x00000004 63*4882a593Smuzhiyun #define CCSR_DMA_MR_CC 0x00000002 64*4882a593Smuzhiyun #define CCSR_DMA_MR_CS 0x00000001 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun #define CCSR_DMA_SR_TE 0x00000080 67*4882a593Smuzhiyun #define CCSR_DMA_SR_CH 0x00000020 68*4882a593Smuzhiyun #define CCSR_DMA_SR_PE 0x00000010 69*4882a593Smuzhiyun #define CCSR_DMA_SR_EOLNI 0x00000008 70*4882a593Smuzhiyun #define CCSR_DMA_SR_CB 0x00000004 71*4882a593Smuzhiyun #define CCSR_DMA_SR_EOSI 0x00000002 72*4882a593Smuzhiyun #define CCSR_DMA_SR_EOLSI 0x00000001 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun /* ECLNDAR takes bits 32-36 of the CLNDAR register */ CCSR_DMA_ECLNDAR_ADDR(u64 x)75*4882a593Smuzhiyunstatic inline u32 CCSR_DMA_ECLNDAR_ADDR(u64 x) 76*4882a593Smuzhiyun { 77*4882a593Smuzhiyun return (x >> 32) & 0xf; 78*4882a593Smuzhiyun } 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun #define CCSR_DMA_CLNDAR_ADDR(x) ((x) & 0xFFFFFFFE) 81*4882a593Smuzhiyun #define CCSR_DMA_CLNDAR_EOSIE 0x00000008 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun /* SATR and DATR, combined */ 84*4882a593Smuzhiyun #define CCSR_DMA_ATR_PBATMU 0x20000000 85*4882a593Smuzhiyun #define CCSR_DMA_ATR_TFLOWLVL_0 0x00000000 86*4882a593Smuzhiyun #define CCSR_DMA_ATR_TFLOWLVL_1 0x06000000 87*4882a593Smuzhiyun #define CCSR_DMA_ATR_TFLOWLVL_2 0x08000000 88*4882a593Smuzhiyun #define CCSR_DMA_ATR_TFLOWLVL_3 0x0C000000 89*4882a593Smuzhiyun #define CCSR_DMA_ATR_PCIORDER 0x02000000 90*4882a593Smuzhiyun #define CCSR_DMA_ATR_SME 0x01000000 91*4882a593Smuzhiyun #define CCSR_DMA_ATR_NOSNOOP 0x00040000 92*4882a593Smuzhiyun #define CCSR_DMA_ATR_SNOOP 0x00050000 93*4882a593Smuzhiyun #define CCSR_DMA_ATR_ESAD_MASK 0x0000000F 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun /** 96*4882a593Smuzhiyun * List Descriptor for extended chaining mode DMA operations. 97*4882a593Smuzhiyun * 98*4882a593Smuzhiyun * The CLSDAR register points to the first (in a linked-list) List 99*4882a593Smuzhiyun * Descriptor. Each object must be aligned on a 32-byte boundary. Each 100*4882a593Smuzhiyun * list descriptor points to a linked-list of link Descriptors. 101*4882a593Smuzhiyun */ 102*4882a593Smuzhiyun struct fsl_dma_list_descriptor { 103*4882a593Smuzhiyun __be64 next; /* Address of next list descriptor */ 104*4882a593Smuzhiyun __be64 first_link; /* Address of first link descriptor */ 105*4882a593Smuzhiyun __be32 source; /* Source stride */ 106*4882a593Smuzhiyun __be32 dest; /* Destination stride */ 107*4882a593Smuzhiyun u8 res[8]; /* Reserved */ 108*4882a593Smuzhiyun } __attribute__ ((aligned(32), packed)); 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun /** 111*4882a593Smuzhiyun * Link Descriptor for basic and extended chaining mode DMA operations. 112*4882a593Smuzhiyun * 113*4882a593Smuzhiyun * A Link Descriptor points to a single DMA buffer. Each link descriptor 114*4882a593Smuzhiyun * must be aligned on a 32-byte boundary. 115*4882a593Smuzhiyun */ 116*4882a593Smuzhiyun struct fsl_dma_link_descriptor { 117*4882a593Smuzhiyun __be32 source_attr; /* Programmed into SATR register */ 118*4882a593Smuzhiyun __be32 source_addr; /* Programmed into SAR register */ 119*4882a593Smuzhiyun __be32 dest_attr; /* Programmed into DATR register */ 120*4882a593Smuzhiyun __be32 dest_addr; /* Programmed into DAR register */ 121*4882a593Smuzhiyun __be64 next; /* Address of next link descriptor */ 122*4882a593Smuzhiyun __be32 count; /* Byte count */ 123*4882a593Smuzhiyun u8 res[4]; /* Reserved */ 124*4882a593Smuzhiyun } __attribute__ ((aligned(32), packed)); 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun #endif 127