1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (ST) 2012 Rajeev Kumar (rajeevkumar.linux@gmail.com)
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * This file is licensed under the terms of the GNU General Public
5*4882a593Smuzhiyun * License version 2. This program is licensed "as is" without any
6*4882a593Smuzhiyun * warranty of any kind, whether express or implied.
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #ifndef __DESIGNWARE_LOCAL_H
10*4882a593Smuzhiyun #define __DESIGNWARE_LOCAL_H
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include <linux/clk.h>
13*4882a593Smuzhiyun #include <linux/device.h>
14*4882a593Smuzhiyun #include <linux/types.h>
15*4882a593Smuzhiyun #include <sound/dmaengine_pcm.h>
16*4882a593Smuzhiyun #include <sound/pcm.h>
17*4882a593Smuzhiyun #include <sound/designware_i2s.h>
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun /* common register for all channel */
20*4882a593Smuzhiyun #define IER 0x000
21*4882a593Smuzhiyun #define IRER 0x004
22*4882a593Smuzhiyun #define ITER 0x008
23*4882a593Smuzhiyun #define CER 0x00C
24*4882a593Smuzhiyun #define CCR 0x010
25*4882a593Smuzhiyun #define RXFFR 0x014
26*4882a593Smuzhiyun #define TXFFR 0x018
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun /* Interrupt status register fields */
29*4882a593Smuzhiyun #define ISR_TXFO BIT(5)
30*4882a593Smuzhiyun #define ISR_TXFE BIT(4)
31*4882a593Smuzhiyun #define ISR_RXFO BIT(1)
32*4882a593Smuzhiyun #define ISR_RXDA BIT(0)
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun /* I2STxRxRegisters for all channels */
35*4882a593Smuzhiyun #define LRBR_LTHR(x) (0x40 * x + 0x020)
36*4882a593Smuzhiyun #define RRBR_RTHR(x) (0x40 * x + 0x024)
37*4882a593Smuzhiyun #define RER(x) (0x40 * x + 0x028)
38*4882a593Smuzhiyun #define TER(x) (0x40 * x + 0x02C)
39*4882a593Smuzhiyun #define RCR(x) (0x40 * x + 0x030)
40*4882a593Smuzhiyun #define TCR(x) (0x40 * x + 0x034)
41*4882a593Smuzhiyun #define ISR(x) (0x40 * x + 0x038)
42*4882a593Smuzhiyun #define IMR(x) (0x40 * x + 0x03C)
43*4882a593Smuzhiyun #define ROR(x) (0x40 * x + 0x040)
44*4882a593Smuzhiyun #define TOR(x) (0x40 * x + 0x044)
45*4882a593Smuzhiyun #define RFCR(x) (0x40 * x + 0x048)
46*4882a593Smuzhiyun #define TFCR(x) (0x40 * x + 0x04C)
47*4882a593Smuzhiyun #define RFF(x) (0x40 * x + 0x050)
48*4882a593Smuzhiyun #define TFF(x) (0x40 * x + 0x054)
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun /* I2SCOMPRegisters */
51*4882a593Smuzhiyun #define I2S_COMP_PARAM_2 0x01F0
52*4882a593Smuzhiyun #define I2S_COMP_PARAM_1 0x01F4
53*4882a593Smuzhiyun #define I2S_COMP_VERSION 0x01F8
54*4882a593Smuzhiyun #define I2S_COMP_TYPE 0x01FC
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun /*
57*4882a593Smuzhiyun * Component parameter register fields - define the I2S block's
58*4882a593Smuzhiyun * configuration.
59*4882a593Smuzhiyun */
60*4882a593Smuzhiyun #define COMP1_TX_WORDSIZE_3(r) (((r) & GENMASK(27, 25)) >> 25)
61*4882a593Smuzhiyun #define COMP1_TX_WORDSIZE_2(r) (((r) & GENMASK(24, 22)) >> 22)
62*4882a593Smuzhiyun #define COMP1_TX_WORDSIZE_1(r) (((r) & GENMASK(21, 19)) >> 19)
63*4882a593Smuzhiyun #define COMP1_TX_WORDSIZE_0(r) (((r) & GENMASK(18, 16)) >> 16)
64*4882a593Smuzhiyun #define COMP1_TX_CHANNELS(r) (((r) & GENMASK(10, 9)) >> 9)
65*4882a593Smuzhiyun #define COMP1_RX_CHANNELS(r) (((r) & GENMASK(8, 7)) >> 7)
66*4882a593Smuzhiyun #define COMP1_RX_ENABLED(r) (((r) & BIT(6)) >> 6)
67*4882a593Smuzhiyun #define COMP1_TX_ENABLED(r) (((r) & BIT(5)) >> 5)
68*4882a593Smuzhiyun #define COMP1_MODE_EN(r) (((r) & BIT(4)) >> 4)
69*4882a593Smuzhiyun #define COMP1_FIFO_DEPTH_GLOBAL(r) (((r) & GENMASK(3, 2)) >> 2)
70*4882a593Smuzhiyun #define COMP1_APB_DATA_WIDTH(r) (((r) & GENMASK(1, 0)) >> 0)
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun #define COMP2_RX_WORDSIZE_3(r) (((r) & GENMASK(12, 10)) >> 10)
73*4882a593Smuzhiyun #define COMP2_RX_WORDSIZE_2(r) (((r) & GENMASK(9, 7)) >> 7)
74*4882a593Smuzhiyun #define COMP2_RX_WORDSIZE_1(r) (((r) & GENMASK(5, 3)) >> 3)
75*4882a593Smuzhiyun #define COMP2_RX_WORDSIZE_0(r) (((r) & GENMASK(2, 0)) >> 0)
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun /* Number of entries in WORDSIZE and DATA_WIDTH parameter registers */
78*4882a593Smuzhiyun #define COMP_MAX_WORDSIZE (1 << 3)
79*4882a593Smuzhiyun #define COMP_MAX_DATA_WIDTH (1 << 2)
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun #define MAX_CHANNEL_NUM 8
82*4882a593Smuzhiyun #define MIN_CHANNEL_NUM 2
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun union dw_i2s_snd_dma_data {
85*4882a593Smuzhiyun struct i2s_dma_data pd;
86*4882a593Smuzhiyun struct snd_dmaengine_dai_dma_data dt;
87*4882a593Smuzhiyun };
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun struct dw_i2s_dev {
90*4882a593Smuzhiyun void __iomem *i2s_base;
91*4882a593Smuzhiyun struct clk *clk;
92*4882a593Smuzhiyun int active;
93*4882a593Smuzhiyun unsigned int capability;
94*4882a593Smuzhiyun unsigned int quirks;
95*4882a593Smuzhiyun unsigned int i2s_reg_comp1;
96*4882a593Smuzhiyun unsigned int i2s_reg_comp2;
97*4882a593Smuzhiyun struct device *dev;
98*4882a593Smuzhiyun u32 ccr;
99*4882a593Smuzhiyun u32 xfer_resolution;
100*4882a593Smuzhiyun u32 fifo_th;
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun /* data related to DMA transfers b/w i2s and DMAC */
103*4882a593Smuzhiyun union dw_i2s_snd_dma_data play_dma_data;
104*4882a593Smuzhiyun union dw_i2s_snd_dma_data capture_dma_data;
105*4882a593Smuzhiyun struct i2s_clk_config_data config;
106*4882a593Smuzhiyun int (*i2s_clk_cfg)(struct i2s_clk_config_data *config);
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun /* data related to PIO transfers */
109*4882a593Smuzhiyun bool use_pio;
110*4882a593Smuzhiyun struct snd_pcm_substream __rcu *tx_substream;
111*4882a593Smuzhiyun struct snd_pcm_substream __rcu *rx_substream;
112*4882a593Smuzhiyun unsigned int (*tx_fn)(struct dw_i2s_dev *dev,
113*4882a593Smuzhiyun struct snd_pcm_runtime *runtime, unsigned int tx_ptr,
114*4882a593Smuzhiyun bool *period_elapsed);
115*4882a593Smuzhiyun unsigned int (*rx_fn)(struct dw_i2s_dev *dev,
116*4882a593Smuzhiyun struct snd_pcm_runtime *runtime, unsigned int rx_ptr,
117*4882a593Smuzhiyun bool *period_elapsed);
118*4882a593Smuzhiyun unsigned int tx_ptr;
119*4882a593Smuzhiyun unsigned int rx_ptr;
120*4882a593Smuzhiyun };
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_SND_DESIGNWARE_PCM)
123*4882a593Smuzhiyun void dw_pcm_push_tx(struct dw_i2s_dev *dev);
124*4882a593Smuzhiyun void dw_pcm_pop_rx(struct dw_i2s_dev *dev);
125*4882a593Smuzhiyun int dw_pcm_register(struct platform_device *pdev);
126*4882a593Smuzhiyun #else
dw_pcm_push_tx(struct dw_i2s_dev * dev)127*4882a593Smuzhiyun void dw_pcm_push_tx(struct dw_i2s_dev *dev) { }
dw_pcm_pop_rx(struct dw_i2s_dev * dev)128*4882a593Smuzhiyun void dw_pcm_pop_rx(struct dw_i2s_dev *dev) { }
dw_pcm_register(struct platform_device * pdev)129*4882a593Smuzhiyun int dw_pcm_register(struct platform_device *pdev)
130*4882a593Smuzhiyun {
131*4882a593Smuzhiyun return -EINVAL;
132*4882a593Smuzhiyun }
133*4882a593Smuzhiyun #endif
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun #endif
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