xref: /OK3568_Linux_fs/kernel/sound/soc/codecs/wm_hubs.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * wm_hubs.c  --  WM8993/4 common code
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright 2009-12 Wolfson Microelectronics plc
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
8*4882a593Smuzhiyun  */
9*4882a593Smuzhiyun 
10*4882a593Smuzhiyun #include <linux/module.h>
11*4882a593Smuzhiyun #include <linux/moduleparam.h>
12*4882a593Smuzhiyun #include <linux/init.h>
13*4882a593Smuzhiyun #include <linux/delay.h>
14*4882a593Smuzhiyun #include <linux/pm.h>
15*4882a593Smuzhiyun #include <linux/i2c.h>
16*4882a593Smuzhiyun #include <linux/mfd/wm8994/registers.h>
17*4882a593Smuzhiyun #include <sound/core.h>
18*4882a593Smuzhiyun #include <sound/pcm.h>
19*4882a593Smuzhiyun #include <sound/pcm_params.h>
20*4882a593Smuzhiyun #include <sound/soc.h>
21*4882a593Smuzhiyun #include <sound/initval.h>
22*4882a593Smuzhiyun #include <sound/tlv.h>
23*4882a593Smuzhiyun 
24*4882a593Smuzhiyun #include "wm8993.h"
25*4882a593Smuzhiyun #include "wm_hubs.h"
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun const DECLARE_TLV_DB_SCALE(wm_hubs_spkmix_tlv, -300, 300, 0);
28*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(wm_hubs_spkmix_tlv);
29*4882a593Smuzhiyun 
30*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(inpga_tlv, -1650, 150, 0);
31*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(inmix_sw_tlv, 0, 3000, 0);
32*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(inmix_tlv, -1500, 300, 1);
33*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(earpiece_tlv, -600, 600, 0);
34*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(outmix_tlv, -2100, 300, 0);
35*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(spkmixout_tlv, -1800, 600, 1);
36*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(outpga_tlv, -5700, 100, 0);
37*4882a593Smuzhiyun static const DECLARE_TLV_DB_RANGE(spkboost_tlv,
38*4882a593Smuzhiyun 	0, 6, TLV_DB_SCALE_ITEM(0, 150, 0),
39*4882a593Smuzhiyun 	7, 7, TLV_DB_SCALE_ITEM(1200, 0, 0)
40*4882a593Smuzhiyun );
41*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(line_tlv, -600, 600, 0);
42*4882a593Smuzhiyun 
43*4882a593Smuzhiyun static const char *speaker_ref_text[] = {
44*4882a593Smuzhiyun 	"SPKVDD/2",
45*4882a593Smuzhiyun 	"VMID",
46*4882a593Smuzhiyun };
47*4882a593Smuzhiyun 
48*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(speaker_ref,
49*4882a593Smuzhiyun 			    WM8993_SPEAKER_MIXER, 8, speaker_ref_text);
50*4882a593Smuzhiyun 
51*4882a593Smuzhiyun static const char *speaker_mode_text[] = {
52*4882a593Smuzhiyun 	"Class D",
53*4882a593Smuzhiyun 	"Class AB",
54*4882a593Smuzhiyun };
55*4882a593Smuzhiyun 
56*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(speaker_mode,
57*4882a593Smuzhiyun 			    WM8993_SPKMIXR_ATTENUATION, 8, speaker_mode_text);
58*4882a593Smuzhiyun 
wait_for_dc_servo(struct snd_soc_component * component,unsigned int op)59*4882a593Smuzhiyun static void wait_for_dc_servo(struct snd_soc_component *component, unsigned int op)
60*4882a593Smuzhiyun {
61*4882a593Smuzhiyun 	struct wm_hubs_data *hubs = snd_soc_component_get_drvdata(component);
62*4882a593Smuzhiyun 	unsigned int reg;
63*4882a593Smuzhiyun 	int count = 0;
64*4882a593Smuzhiyun 	int timeout;
65*4882a593Smuzhiyun 	unsigned int val;
66*4882a593Smuzhiyun 
67*4882a593Smuzhiyun 	val = op | WM8993_DCS_ENA_CHAN_0 | WM8993_DCS_ENA_CHAN_1;
68*4882a593Smuzhiyun 
69*4882a593Smuzhiyun 	/* Trigger the command */
70*4882a593Smuzhiyun 	snd_soc_component_write(component, WM8993_DC_SERVO_0, val);
71*4882a593Smuzhiyun 
72*4882a593Smuzhiyun 	dev_dbg(component->dev, "Waiting for DC servo...\n");
73*4882a593Smuzhiyun 
74*4882a593Smuzhiyun 	if (hubs->dcs_done_irq)
75*4882a593Smuzhiyun 		timeout = 4;
76*4882a593Smuzhiyun 	else
77*4882a593Smuzhiyun 		timeout = 400;
78*4882a593Smuzhiyun 
79*4882a593Smuzhiyun 	do {
80*4882a593Smuzhiyun 		count++;
81*4882a593Smuzhiyun 
82*4882a593Smuzhiyun 		if (hubs->dcs_done_irq)
83*4882a593Smuzhiyun 			wait_for_completion_timeout(&hubs->dcs_done,
84*4882a593Smuzhiyun 						    msecs_to_jiffies(250));
85*4882a593Smuzhiyun 		else
86*4882a593Smuzhiyun 			msleep(1);
87*4882a593Smuzhiyun 
88*4882a593Smuzhiyun 		reg = snd_soc_component_read(component, WM8993_DC_SERVO_0);
89*4882a593Smuzhiyun 		dev_dbg(component->dev, "DC servo: %x\n", reg);
90*4882a593Smuzhiyun 	} while (reg & op && count < timeout);
91*4882a593Smuzhiyun 
92*4882a593Smuzhiyun 	if (reg & op)
93*4882a593Smuzhiyun 		dev_err(component->dev, "Timed out waiting for DC Servo %x\n",
94*4882a593Smuzhiyun 			op);
95*4882a593Smuzhiyun }
96*4882a593Smuzhiyun 
wm_hubs_dcs_done(int irq,void * data)97*4882a593Smuzhiyun irqreturn_t wm_hubs_dcs_done(int irq, void *data)
98*4882a593Smuzhiyun {
99*4882a593Smuzhiyun 	struct wm_hubs_data *hubs = data;
100*4882a593Smuzhiyun 
101*4882a593Smuzhiyun 	complete(&hubs->dcs_done);
102*4882a593Smuzhiyun 
103*4882a593Smuzhiyun 	return IRQ_HANDLED;
104*4882a593Smuzhiyun }
105*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(wm_hubs_dcs_done);
106*4882a593Smuzhiyun 
wm_hubs_dac_hp_direct(struct snd_soc_component * component)107*4882a593Smuzhiyun static bool wm_hubs_dac_hp_direct(struct snd_soc_component *component)
108*4882a593Smuzhiyun {
109*4882a593Smuzhiyun 	int reg;
110*4882a593Smuzhiyun 
111*4882a593Smuzhiyun 	/* If we're going via the mixer we'll need to do additional checks */
112*4882a593Smuzhiyun 	reg = snd_soc_component_read(component, WM8993_OUTPUT_MIXER1);
113*4882a593Smuzhiyun 	if (!(reg & WM8993_DACL_TO_HPOUT1L)) {
114*4882a593Smuzhiyun 		if (reg & ~WM8993_DACL_TO_MIXOUTL) {
115*4882a593Smuzhiyun 			dev_vdbg(component->dev, "Analogue paths connected: %x\n",
116*4882a593Smuzhiyun 				 reg & ~WM8993_DACL_TO_HPOUT1L);
117*4882a593Smuzhiyun 			return false;
118*4882a593Smuzhiyun 		} else {
119*4882a593Smuzhiyun 			dev_vdbg(component->dev, "HPL connected to mixer\n");
120*4882a593Smuzhiyun 		}
121*4882a593Smuzhiyun 	} else {
122*4882a593Smuzhiyun 		dev_vdbg(component->dev, "HPL connected to DAC\n");
123*4882a593Smuzhiyun 	}
124*4882a593Smuzhiyun 
125*4882a593Smuzhiyun 	reg = snd_soc_component_read(component, WM8993_OUTPUT_MIXER2);
126*4882a593Smuzhiyun 	if (!(reg & WM8993_DACR_TO_HPOUT1R)) {
127*4882a593Smuzhiyun 		if (reg & ~WM8993_DACR_TO_MIXOUTR) {
128*4882a593Smuzhiyun 			dev_vdbg(component->dev, "Analogue paths connected: %x\n",
129*4882a593Smuzhiyun 				 reg & ~WM8993_DACR_TO_HPOUT1R);
130*4882a593Smuzhiyun 			return false;
131*4882a593Smuzhiyun 		} else {
132*4882a593Smuzhiyun 			dev_vdbg(component->dev, "HPR connected to mixer\n");
133*4882a593Smuzhiyun 		}
134*4882a593Smuzhiyun 	} else {
135*4882a593Smuzhiyun 		dev_vdbg(component->dev, "HPR connected to DAC\n");
136*4882a593Smuzhiyun 	}
137*4882a593Smuzhiyun 
138*4882a593Smuzhiyun 	return true;
139*4882a593Smuzhiyun }
140*4882a593Smuzhiyun 
141*4882a593Smuzhiyun struct wm_hubs_dcs_cache {
142*4882a593Smuzhiyun 	struct list_head list;
143*4882a593Smuzhiyun 	unsigned int left;
144*4882a593Smuzhiyun 	unsigned int right;
145*4882a593Smuzhiyun 	u16 dcs_cfg;
146*4882a593Smuzhiyun };
147*4882a593Smuzhiyun 
wm_hubs_dcs_cache_get(struct snd_soc_component * component,struct wm_hubs_dcs_cache ** entry)148*4882a593Smuzhiyun static bool wm_hubs_dcs_cache_get(struct snd_soc_component *component,
149*4882a593Smuzhiyun 				  struct wm_hubs_dcs_cache **entry)
150*4882a593Smuzhiyun {
151*4882a593Smuzhiyun 	struct wm_hubs_data *hubs = snd_soc_component_get_drvdata(component);
152*4882a593Smuzhiyun 	struct wm_hubs_dcs_cache *cache;
153*4882a593Smuzhiyun 	unsigned int left, right;
154*4882a593Smuzhiyun 
155*4882a593Smuzhiyun 	left = snd_soc_component_read(component, WM8993_LEFT_OUTPUT_VOLUME);
156*4882a593Smuzhiyun 	left &= WM8993_HPOUT1L_VOL_MASK;
157*4882a593Smuzhiyun 
158*4882a593Smuzhiyun 	right = snd_soc_component_read(component, WM8993_RIGHT_OUTPUT_VOLUME);
159*4882a593Smuzhiyun 	right &= WM8993_HPOUT1R_VOL_MASK;
160*4882a593Smuzhiyun 
161*4882a593Smuzhiyun 	list_for_each_entry(cache, &hubs->dcs_cache, list) {
162*4882a593Smuzhiyun 		if (cache->left != left || cache->right != right)
163*4882a593Smuzhiyun 			continue;
164*4882a593Smuzhiyun 
165*4882a593Smuzhiyun 		*entry = cache;
166*4882a593Smuzhiyun 		return true;
167*4882a593Smuzhiyun 	}
168*4882a593Smuzhiyun 
169*4882a593Smuzhiyun 	return false;
170*4882a593Smuzhiyun }
171*4882a593Smuzhiyun 
wm_hubs_dcs_cache_set(struct snd_soc_component * component,u16 dcs_cfg)172*4882a593Smuzhiyun static void wm_hubs_dcs_cache_set(struct snd_soc_component *component, u16 dcs_cfg)
173*4882a593Smuzhiyun {
174*4882a593Smuzhiyun 	struct wm_hubs_data *hubs = snd_soc_component_get_drvdata(component);
175*4882a593Smuzhiyun 	struct wm_hubs_dcs_cache *cache;
176*4882a593Smuzhiyun 
177*4882a593Smuzhiyun 	if (hubs->no_cache_dac_hp_direct)
178*4882a593Smuzhiyun 		return;
179*4882a593Smuzhiyun 
180*4882a593Smuzhiyun 	cache = devm_kzalloc(component->dev, sizeof(*cache), GFP_KERNEL);
181*4882a593Smuzhiyun 	if (!cache)
182*4882a593Smuzhiyun 		return;
183*4882a593Smuzhiyun 
184*4882a593Smuzhiyun 	cache->left = snd_soc_component_read(component, WM8993_LEFT_OUTPUT_VOLUME);
185*4882a593Smuzhiyun 	cache->left &= WM8993_HPOUT1L_VOL_MASK;
186*4882a593Smuzhiyun 
187*4882a593Smuzhiyun 	cache->right = snd_soc_component_read(component, WM8993_RIGHT_OUTPUT_VOLUME);
188*4882a593Smuzhiyun 	cache->right &= WM8993_HPOUT1R_VOL_MASK;
189*4882a593Smuzhiyun 
190*4882a593Smuzhiyun 	cache->dcs_cfg = dcs_cfg;
191*4882a593Smuzhiyun 
192*4882a593Smuzhiyun 	list_add_tail(&cache->list, &hubs->dcs_cache);
193*4882a593Smuzhiyun }
194*4882a593Smuzhiyun 
wm_hubs_read_dc_servo(struct snd_soc_component * component,u16 * reg_l,u16 * reg_r)195*4882a593Smuzhiyun static int wm_hubs_read_dc_servo(struct snd_soc_component *component,
196*4882a593Smuzhiyun 				  u16 *reg_l, u16 *reg_r)
197*4882a593Smuzhiyun {
198*4882a593Smuzhiyun 	struct wm_hubs_data *hubs = snd_soc_component_get_drvdata(component);
199*4882a593Smuzhiyun 	u16 dcs_reg, reg;
200*4882a593Smuzhiyun 	int ret = 0;
201*4882a593Smuzhiyun 
202*4882a593Smuzhiyun 	switch (hubs->dcs_readback_mode) {
203*4882a593Smuzhiyun 	case 2:
204*4882a593Smuzhiyun 		dcs_reg = WM8994_DC_SERVO_4E;
205*4882a593Smuzhiyun 		break;
206*4882a593Smuzhiyun 	case 1:
207*4882a593Smuzhiyun 		dcs_reg = WM8994_DC_SERVO_READBACK;
208*4882a593Smuzhiyun 		break;
209*4882a593Smuzhiyun 	default:
210*4882a593Smuzhiyun 		dcs_reg = WM8993_DC_SERVO_3;
211*4882a593Smuzhiyun 		break;
212*4882a593Smuzhiyun 	}
213*4882a593Smuzhiyun 
214*4882a593Smuzhiyun 	/* Different chips in the family support different readback
215*4882a593Smuzhiyun 	 * methods.
216*4882a593Smuzhiyun 	 */
217*4882a593Smuzhiyun 	switch (hubs->dcs_readback_mode) {
218*4882a593Smuzhiyun 	case 0:
219*4882a593Smuzhiyun 		*reg_l = snd_soc_component_read(component, WM8993_DC_SERVO_READBACK_1)
220*4882a593Smuzhiyun 			& WM8993_DCS_INTEG_CHAN_0_MASK;
221*4882a593Smuzhiyun 		*reg_r = snd_soc_component_read(component, WM8993_DC_SERVO_READBACK_2)
222*4882a593Smuzhiyun 			& WM8993_DCS_INTEG_CHAN_1_MASK;
223*4882a593Smuzhiyun 		break;
224*4882a593Smuzhiyun 	case 2:
225*4882a593Smuzhiyun 	case 1:
226*4882a593Smuzhiyun 		reg = snd_soc_component_read(component, dcs_reg);
227*4882a593Smuzhiyun 		*reg_r = (reg & WM8993_DCS_DAC_WR_VAL_1_MASK)
228*4882a593Smuzhiyun 			>> WM8993_DCS_DAC_WR_VAL_1_SHIFT;
229*4882a593Smuzhiyun 		*reg_l = reg & WM8993_DCS_DAC_WR_VAL_0_MASK;
230*4882a593Smuzhiyun 		break;
231*4882a593Smuzhiyun 	default:
232*4882a593Smuzhiyun 		WARN(1, "Unknown DCS readback method\n");
233*4882a593Smuzhiyun 		ret = -1;
234*4882a593Smuzhiyun 	}
235*4882a593Smuzhiyun 	return ret;
236*4882a593Smuzhiyun }
237*4882a593Smuzhiyun 
238*4882a593Smuzhiyun /*
239*4882a593Smuzhiyun  * Startup calibration of the DC servo
240*4882a593Smuzhiyun  */
enable_dc_servo(struct snd_soc_component * component)241*4882a593Smuzhiyun static void enable_dc_servo(struct snd_soc_component *component)
242*4882a593Smuzhiyun {
243*4882a593Smuzhiyun 	struct wm_hubs_data *hubs = snd_soc_component_get_drvdata(component);
244*4882a593Smuzhiyun 	struct wm_hubs_dcs_cache *cache;
245*4882a593Smuzhiyun 	s8 offset;
246*4882a593Smuzhiyun 	u16 reg_l, reg_r, dcs_cfg, dcs_reg;
247*4882a593Smuzhiyun 
248*4882a593Smuzhiyun 	switch (hubs->dcs_readback_mode) {
249*4882a593Smuzhiyun 	case 2:
250*4882a593Smuzhiyun 		dcs_reg = WM8994_DC_SERVO_4E;
251*4882a593Smuzhiyun 		break;
252*4882a593Smuzhiyun 	default:
253*4882a593Smuzhiyun 		dcs_reg = WM8993_DC_SERVO_3;
254*4882a593Smuzhiyun 		break;
255*4882a593Smuzhiyun 	}
256*4882a593Smuzhiyun 
257*4882a593Smuzhiyun 	/* If we're using a digital only path and have a previously
258*4882a593Smuzhiyun 	 * callibrated DC servo offset stored then use that. */
259*4882a593Smuzhiyun 	if (wm_hubs_dac_hp_direct(component) &&
260*4882a593Smuzhiyun 	    wm_hubs_dcs_cache_get(component, &cache)) {
261*4882a593Smuzhiyun 		dev_dbg(component->dev, "Using cached DCS offset %x for %d,%d\n",
262*4882a593Smuzhiyun 			cache->dcs_cfg, cache->left, cache->right);
263*4882a593Smuzhiyun 		snd_soc_component_write(component, dcs_reg, cache->dcs_cfg);
264*4882a593Smuzhiyun 		wait_for_dc_servo(component,
265*4882a593Smuzhiyun 				  WM8993_DCS_TRIG_DAC_WR_0 |
266*4882a593Smuzhiyun 				  WM8993_DCS_TRIG_DAC_WR_1);
267*4882a593Smuzhiyun 		return;
268*4882a593Smuzhiyun 	}
269*4882a593Smuzhiyun 
270*4882a593Smuzhiyun 	if (hubs->series_startup) {
271*4882a593Smuzhiyun 		/* Set for 32 series updates */
272*4882a593Smuzhiyun 		snd_soc_component_update_bits(component, WM8993_DC_SERVO_1,
273*4882a593Smuzhiyun 				    WM8993_DCS_SERIES_NO_01_MASK,
274*4882a593Smuzhiyun 				    32 << WM8993_DCS_SERIES_NO_01_SHIFT);
275*4882a593Smuzhiyun 		wait_for_dc_servo(component,
276*4882a593Smuzhiyun 				  WM8993_DCS_TRIG_SERIES_0 |
277*4882a593Smuzhiyun 				  WM8993_DCS_TRIG_SERIES_1);
278*4882a593Smuzhiyun 	} else {
279*4882a593Smuzhiyun 		wait_for_dc_servo(component,
280*4882a593Smuzhiyun 				  WM8993_DCS_TRIG_STARTUP_0 |
281*4882a593Smuzhiyun 				  WM8993_DCS_TRIG_STARTUP_1);
282*4882a593Smuzhiyun 	}
283*4882a593Smuzhiyun 
284*4882a593Smuzhiyun 	if (wm_hubs_read_dc_servo(component, &reg_l, &reg_r) < 0)
285*4882a593Smuzhiyun 		return;
286*4882a593Smuzhiyun 
287*4882a593Smuzhiyun 	dev_dbg(component->dev, "DCS input: %x %x\n", reg_l, reg_r);
288*4882a593Smuzhiyun 
289*4882a593Smuzhiyun 	/* Apply correction to DC servo result */
290*4882a593Smuzhiyun 	if (hubs->dcs_codes_l || hubs->dcs_codes_r) {
291*4882a593Smuzhiyun 		dev_dbg(component->dev,
292*4882a593Smuzhiyun 			"Applying %d/%d code DC servo correction\n",
293*4882a593Smuzhiyun 			hubs->dcs_codes_l, hubs->dcs_codes_r);
294*4882a593Smuzhiyun 
295*4882a593Smuzhiyun 		/* HPOUT1R */
296*4882a593Smuzhiyun 		offset = (s8)reg_r;
297*4882a593Smuzhiyun 		dev_dbg(component->dev, "DCS right %d->%d\n", offset,
298*4882a593Smuzhiyun 			offset + hubs->dcs_codes_r);
299*4882a593Smuzhiyun 		offset += hubs->dcs_codes_r;
300*4882a593Smuzhiyun 		dcs_cfg = (u8)offset << WM8993_DCS_DAC_WR_VAL_1_SHIFT;
301*4882a593Smuzhiyun 
302*4882a593Smuzhiyun 		/* HPOUT1L */
303*4882a593Smuzhiyun 		offset = (s8)reg_l;
304*4882a593Smuzhiyun 		dev_dbg(component->dev, "DCS left %d->%d\n", offset,
305*4882a593Smuzhiyun 			offset + hubs->dcs_codes_l);
306*4882a593Smuzhiyun 		offset += hubs->dcs_codes_l;
307*4882a593Smuzhiyun 		dcs_cfg |= (u8)offset;
308*4882a593Smuzhiyun 
309*4882a593Smuzhiyun 		dev_dbg(component->dev, "DCS result: %x\n", dcs_cfg);
310*4882a593Smuzhiyun 
311*4882a593Smuzhiyun 		/* Do it */
312*4882a593Smuzhiyun 		snd_soc_component_write(component, dcs_reg, dcs_cfg);
313*4882a593Smuzhiyun 		wait_for_dc_servo(component,
314*4882a593Smuzhiyun 				  WM8993_DCS_TRIG_DAC_WR_0 |
315*4882a593Smuzhiyun 				  WM8993_DCS_TRIG_DAC_WR_1);
316*4882a593Smuzhiyun 	} else {
317*4882a593Smuzhiyun 		dcs_cfg = reg_r << WM8993_DCS_DAC_WR_VAL_1_SHIFT;
318*4882a593Smuzhiyun 		dcs_cfg |= reg_l;
319*4882a593Smuzhiyun 	}
320*4882a593Smuzhiyun 
321*4882a593Smuzhiyun 	/* Save the callibrated offset if we're in class W mode and
322*4882a593Smuzhiyun 	 * therefore don't have any analogue signal mixed in. */
323*4882a593Smuzhiyun 	if (wm_hubs_dac_hp_direct(component))
324*4882a593Smuzhiyun 		wm_hubs_dcs_cache_set(component, dcs_cfg);
325*4882a593Smuzhiyun }
326*4882a593Smuzhiyun 
327*4882a593Smuzhiyun /*
328*4882a593Smuzhiyun  * Update the DC servo calibration on gain changes
329*4882a593Smuzhiyun  */
wm8993_put_dc_servo(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)330*4882a593Smuzhiyun static int wm8993_put_dc_servo(struct snd_kcontrol *kcontrol,
331*4882a593Smuzhiyun 			       struct snd_ctl_elem_value *ucontrol)
332*4882a593Smuzhiyun {
333*4882a593Smuzhiyun 	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
334*4882a593Smuzhiyun 	struct wm_hubs_data *hubs = snd_soc_component_get_drvdata(component);
335*4882a593Smuzhiyun 	int ret;
336*4882a593Smuzhiyun 
337*4882a593Smuzhiyun 	ret = snd_soc_put_volsw(kcontrol, ucontrol);
338*4882a593Smuzhiyun 
339*4882a593Smuzhiyun 	/* If we're applying an offset correction then updating the
340*4882a593Smuzhiyun 	 * callibration would be likely to introduce further offsets. */
341*4882a593Smuzhiyun 	if (hubs->dcs_codes_l || hubs->dcs_codes_r || hubs->no_series_update)
342*4882a593Smuzhiyun 		return ret;
343*4882a593Smuzhiyun 
344*4882a593Smuzhiyun 	/* Only need to do this if the outputs are active */
345*4882a593Smuzhiyun 	if (snd_soc_component_read(component, WM8993_POWER_MANAGEMENT_1)
346*4882a593Smuzhiyun 	    & (WM8993_HPOUT1L_ENA | WM8993_HPOUT1R_ENA))
347*4882a593Smuzhiyun 		snd_soc_component_update_bits(component,
348*4882a593Smuzhiyun 				    WM8993_DC_SERVO_0,
349*4882a593Smuzhiyun 				    WM8993_DCS_TRIG_SINGLE_0 |
350*4882a593Smuzhiyun 				    WM8993_DCS_TRIG_SINGLE_1,
351*4882a593Smuzhiyun 				    WM8993_DCS_TRIG_SINGLE_0 |
352*4882a593Smuzhiyun 				    WM8993_DCS_TRIG_SINGLE_1);
353*4882a593Smuzhiyun 
354*4882a593Smuzhiyun 	return ret;
355*4882a593Smuzhiyun }
356*4882a593Smuzhiyun 
357*4882a593Smuzhiyun static const struct snd_kcontrol_new analogue_snd_controls[] = {
358*4882a593Smuzhiyun SOC_SINGLE_TLV("IN1L Volume", WM8993_LEFT_LINE_INPUT_1_2_VOLUME, 0, 31, 0,
359*4882a593Smuzhiyun 	       inpga_tlv),
360*4882a593Smuzhiyun SOC_SINGLE("IN1L Switch", WM8993_LEFT_LINE_INPUT_1_2_VOLUME, 7, 1, 1),
361*4882a593Smuzhiyun SOC_SINGLE("IN1L ZC Switch", WM8993_LEFT_LINE_INPUT_1_2_VOLUME, 6, 1, 0),
362*4882a593Smuzhiyun 
363*4882a593Smuzhiyun SOC_SINGLE_TLV("IN1R Volume", WM8993_RIGHT_LINE_INPUT_1_2_VOLUME, 0, 31, 0,
364*4882a593Smuzhiyun 	       inpga_tlv),
365*4882a593Smuzhiyun SOC_SINGLE("IN1R Switch", WM8993_RIGHT_LINE_INPUT_1_2_VOLUME, 7, 1, 1),
366*4882a593Smuzhiyun SOC_SINGLE("IN1R ZC Switch", WM8993_RIGHT_LINE_INPUT_1_2_VOLUME, 6, 1, 0),
367*4882a593Smuzhiyun 
368*4882a593Smuzhiyun 
369*4882a593Smuzhiyun SOC_SINGLE_TLV("IN2L Volume", WM8993_LEFT_LINE_INPUT_3_4_VOLUME, 0, 31, 0,
370*4882a593Smuzhiyun 	       inpga_tlv),
371*4882a593Smuzhiyun SOC_SINGLE("IN2L Switch", WM8993_LEFT_LINE_INPUT_3_4_VOLUME, 7, 1, 1),
372*4882a593Smuzhiyun SOC_SINGLE("IN2L ZC Switch", WM8993_LEFT_LINE_INPUT_3_4_VOLUME, 6, 1, 0),
373*4882a593Smuzhiyun 
374*4882a593Smuzhiyun SOC_SINGLE_TLV("IN2R Volume", WM8993_RIGHT_LINE_INPUT_3_4_VOLUME, 0, 31, 0,
375*4882a593Smuzhiyun 	       inpga_tlv),
376*4882a593Smuzhiyun SOC_SINGLE("IN2R Switch", WM8993_RIGHT_LINE_INPUT_3_4_VOLUME, 7, 1, 1),
377*4882a593Smuzhiyun SOC_SINGLE("IN2R ZC Switch", WM8993_RIGHT_LINE_INPUT_3_4_VOLUME, 6, 1, 0),
378*4882a593Smuzhiyun 
379*4882a593Smuzhiyun SOC_SINGLE_TLV("MIXINL IN2L Volume", WM8993_INPUT_MIXER3, 7, 1, 0,
380*4882a593Smuzhiyun 	       inmix_sw_tlv),
381*4882a593Smuzhiyun SOC_SINGLE_TLV("MIXINL IN1L Volume", WM8993_INPUT_MIXER3, 4, 1, 0,
382*4882a593Smuzhiyun 	       inmix_sw_tlv),
383*4882a593Smuzhiyun SOC_SINGLE_TLV("MIXINL Output Record Volume", WM8993_INPUT_MIXER3, 0, 7, 0,
384*4882a593Smuzhiyun 	       inmix_tlv),
385*4882a593Smuzhiyun SOC_SINGLE_TLV("MIXINL IN1LP Volume", WM8993_INPUT_MIXER5, 6, 7, 0, inmix_tlv),
386*4882a593Smuzhiyun SOC_SINGLE_TLV("MIXINL Direct Voice Volume", WM8993_INPUT_MIXER5, 0, 6, 0,
387*4882a593Smuzhiyun 	       inmix_tlv),
388*4882a593Smuzhiyun 
389*4882a593Smuzhiyun SOC_SINGLE_TLV("MIXINR IN2R Volume", WM8993_INPUT_MIXER4, 7, 1, 0,
390*4882a593Smuzhiyun 	       inmix_sw_tlv),
391*4882a593Smuzhiyun SOC_SINGLE_TLV("MIXINR IN1R Volume", WM8993_INPUT_MIXER4, 4, 1, 0,
392*4882a593Smuzhiyun 	       inmix_sw_tlv),
393*4882a593Smuzhiyun SOC_SINGLE_TLV("MIXINR Output Record Volume", WM8993_INPUT_MIXER4, 0, 7, 0,
394*4882a593Smuzhiyun 	       inmix_tlv),
395*4882a593Smuzhiyun SOC_SINGLE_TLV("MIXINR IN1RP Volume", WM8993_INPUT_MIXER6, 6, 7, 0, inmix_tlv),
396*4882a593Smuzhiyun SOC_SINGLE_TLV("MIXINR Direct Voice Volume", WM8993_INPUT_MIXER6, 0, 6, 0,
397*4882a593Smuzhiyun 	       inmix_tlv),
398*4882a593Smuzhiyun 
399*4882a593Smuzhiyun SOC_SINGLE_TLV("Left Output Mixer IN2RN Volume", WM8993_OUTPUT_MIXER5, 6, 7, 1,
400*4882a593Smuzhiyun 	       outmix_tlv),
401*4882a593Smuzhiyun SOC_SINGLE_TLV("Left Output Mixer IN2LN Volume", WM8993_OUTPUT_MIXER3, 6, 7, 1,
402*4882a593Smuzhiyun 	       outmix_tlv),
403*4882a593Smuzhiyun SOC_SINGLE_TLV("Left Output Mixer IN2LP Volume", WM8993_OUTPUT_MIXER3, 9, 7, 1,
404*4882a593Smuzhiyun 	       outmix_tlv),
405*4882a593Smuzhiyun SOC_SINGLE_TLV("Left Output Mixer IN1L Volume", WM8993_OUTPUT_MIXER3, 0, 7, 1,
406*4882a593Smuzhiyun 	       outmix_tlv),
407*4882a593Smuzhiyun SOC_SINGLE_TLV("Left Output Mixer IN1R Volume", WM8993_OUTPUT_MIXER3, 3, 7, 1,
408*4882a593Smuzhiyun 	       outmix_tlv),
409*4882a593Smuzhiyun SOC_SINGLE_TLV("Left Output Mixer Right Input Volume",
410*4882a593Smuzhiyun 	       WM8993_OUTPUT_MIXER5, 3, 7, 1, outmix_tlv),
411*4882a593Smuzhiyun SOC_SINGLE_TLV("Left Output Mixer Left Input Volume",
412*4882a593Smuzhiyun 	       WM8993_OUTPUT_MIXER5, 0, 7, 1, outmix_tlv),
413*4882a593Smuzhiyun SOC_SINGLE_TLV("Left Output Mixer DAC Volume", WM8993_OUTPUT_MIXER5, 9, 7, 1,
414*4882a593Smuzhiyun 	       outmix_tlv),
415*4882a593Smuzhiyun 
416*4882a593Smuzhiyun SOC_SINGLE_TLV("Right Output Mixer IN2LN Volume",
417*4882a593Smuzhiyun 	       WM8993_OUTPUT_MIXER6, 6, 7, 1, outmix_tlv),
418*4882a593Smuzhiyun SOC_SINGLE_TLV("Right Output Mixer IN2RN Volume",
419*4882a593Smuzhiyun 	       WM8993_OUTPUT_MIXER4, 6, 7, 1, outmix_tlv),
420*4882a593Smuzhiyun SOC_SINGLE_TLV("Right Output Mixer IN1L Volume",
421*4882a593Smuzhiyun 	       WM8993_OUTPUT_MIXER4, 3, 7, 1, outmix_tlv),
422*4882a593Smuzhiyun SOC_SINGLE_TLV("Right Output Mixer IN1R Volume",
423*4882a593Smuzhiyun 	       WM8993_OUTPUT_MIXER4, 0, 7, 1, outmix_tlv),
424*4882a593Smuzhiyun SOC_SINGLE_TLV("Right Output Mixer IN2RP Volume",
425*4882a593Smuzhiyun 	       WM8993_OUTPUT_MIXER4, 9, 7, 1, outmix_tlv),
426*4882a593Smuzhiyun SOC_SINGLE_TLV("Right Output Mixer Left Input Volume",
427*4882a593Smuzhiyun 	       WM8993_OUTPUT_MIXER6, 3, 7, 1, outmix_tlv),
428*4882a593Smuzhiyun SOC_SINGLE_TLV("Right Output Mixer Right Input Volume",
429*4882a593Smuzhiyun 	       WM8993_OUTPUT_MIXER6, 6, 7, 1, outmix_tlv),
430*4882a593Smuzhiyun SOC_SINGLE_TLV("Right Output Mixer DAC Volume",
431*4882a593Smuzhiyun 	       WM8993_OUTPUT_MIXER6, 9, 7, 1, outmix_tlv),
432*4882a593Smuzhiyun 
433*4882a593Smuzhiyun SOC_DOUBLE_R_TLV("Output Volume", WM8993_LEFT_OPGA_VOLUME,
434*4882a593Smuzhiyun 		 WM8993_RIGHT_OPGA_VOLUME, 0, 63, 0, outpga_tlv),
435*4882a593Smuzhiyun SOC_DOUBLE_R("Output Switch", WM8993_LEFT_OPGA_VOLUME,
436*4882a593Smuzhiyun 	     WM8993_RIGHT_OPGA_VOLUME, 6, 1, 0),
437*4882a593Smuzhiyun SOC_DOUBLE_R("Output ZC Switch", WM8993_LEFT_OPGA_VOLUME,
438*4882a593Smuzhiyun 	     WM8993_RIGHT_OPGA_VOLUME, 7, 1, 0),
439*4882a593Smuzhiyun 
440*4882a593Smuzhiyun SOC_SINGLE("Earpiece Switch", WM8993_HPOUT2_VOLUME, 5, 1, 1),
441*4882a593Smuzhiyun SOC_SINGLE_TLV("Earpiece Volume", WM8993_HPOUT2_VOLUME, 4, 1, 1, earpiece_tlv),
442*4882a593Smuzhiyun 
443*4882a593Smuzhiyun SOC_SINGLE_TLV("SPKL Input Volume", WM8993_SPKMIXL_ATTENUATION,
444*4882a593Smuzhiyun 	       5, 1, 1, wm_hubs_spkmix_tlv),
445*4882a593Smuzhiyun SOC_SINGLE_TLV("SPKL IN1LP Volume", WM8993_SPKMIXL_ATTENUATION,
446*4882a593Smuzhiyun 	       4, 1, 1, wm_hubs_spkmix_tlv),
447*4882a593Smuzhiyun SOC_SINGLE_TLV("SPKL Output Volume", WM8993_SPKMIXL_ATTENUATION,
448*4882a593Smuzhiyun 	       3, 1, 1, wm_hubs_spkmix_tlv),
449*4882a593Smuzhiyun 
450*4882a593Smuzhiyun SOC_SINGLE_TLV("SPKR Input Volume", WM8993_SPKMIXR_ATTENUATION,
451*4882a593Smuzhiyun 	       5, 1, 1, wm_hubs_spkmix_tlv),
452*4882a593Smuzhiyun SOC_SINGLE_TLV("SPKR IN1RP Volume", WM8993_SPKMIXR_ATTENUATION,
453*4882a593Smuzhiyun 	       4, 1, 1, wm_hubs_spkmix_tlv),
454*4882a593Smuzhiyun SOC_SINGLE_TLV("SPKR Output Volume", WM8993_SPKMIXR_ATTENUATION,
455*4882a593Smuzhiyun 	       3, 1, 1, wm_hubs_spkmix_tlv),
456*4882a593Smuzhiyun 
457*4882a593Smuzhiyun SOC_DOUBLE_R_TLV("Speaker Mixer Volume",
458*4882a593Smuzhiyun 		 WM8993_SPKMIXL_ATTENUATION, WM8993_SPKMIXR_ATTENUATION,
459*4882a593Smuzhiyun 		 0, 3, 1, spkmixout_tlv),
460*4882a593Smuzhiyun SOC_DOUBLE_R_TLV("Speaker Volume",
461*4882a593Smuzhiyun 		 WM8993_SPEAKER_VOLUME_LEFT, WM8993_SPEAKER_VOLUME_RIGHT,
462*4882a593Smuzhiyun 		 0, 63, 0, outpga_tlv),
463*4882a593Smuzhiyun SOC_DOUBLE_R("Speaker Switch",
464*4882a593Smuzhiyun 	     WM8993_SPEAKER_VOLUME_LEFT, WM8993_SPEAKER_VOLUME_RIGHT,
465*4882a593Smuzhiyun 	     6, 1, 0),
466*4882a593Smuzhiyun SOC_DOUBLE_R("Speaker ZC Switch",
467*4882a593Smuzhiyun 	     WM8993_SPEAKER_VOLUME_LEFT, WM8993_SPEAKER_VOLUME_RIGHT,
468*4882a593Smuzhiyun 	     7, 1, 0),
469*4882a593Smuzhiyun SOC_DOUBLE_TLV("Speaker Boost Volume", WM8993_SPKOUT_BOOST, 3, 0, 7, 0,
470*4882a593Smuzhiyun 	       spkboost_tlv),
471*4882a593Smuzhiyun SOC_ENUM("Speaker Reference", speaker_ref),
472*4882a593Smuzhiyun SOC_ENUM("Speaker Mode", speaker_mode),
473*4882a593Smuzhiyun 
474*4882a593Smuzhiyun SOC_DOUBLE_R_EXT_TLV("Headphone Volume",
475*4882a593Smuzhiyun 		     WM8993_LEFT_OUTPUT_VOLUME, WM8993_RIGHT_OUTPUT_VOLUME,
476*4882a593Smuzhiyun 		     0, 63, 0, snd_soc_get_volsw, wm8993_put_dc_servo,
477*4882a593Smuzhiyun 		     outpga_tlv),
478*4882a593Smuzhiyun 
479*4882a593Smuzhiyun SOC_DOUBLE_R("Headphone Switch", WM8993_LEFT_OUTPUT_VOLUME,
480*4882a593Smuzhiyun 	     WM8993_RIGHT_OUTPUT_VOLUME, 6, 1, 0),
481*4882a593Smuzhiyun SOC_DOUBLE_R("Headphone ZC Switch", WM8993_LEFT_OUTPUT_VOLUME,
482*4882a593Smuzhiyun 	     WM8993_RIGHT_OUTPUT_VOLUME, 7, 1, 0),
483*4882a593Smuzhiyun 
484*4882a593Smuzhiyun SOC_SINGLE("LINEOUT1N Switch", WM8993_LINE_OUTPUTS_VOLUME, 6, 1, 1),
485*4882a593Smuzhiyun SOC_SINGLE("LINEOUT1P Switch", WM8993_LINE_OUTPUTS_VOLUME, 5, 1, 1),
486*4882a593Smuzhiyun SOC_SINGLE_TLV("LINEOUT1 Volume", WM8993_LINE_OUTPUTS_VOLUME, 4, 1, 1,
487*4882a593Smuzhiyun 	       line_tlv),
488*4882a593Smuzhiyun 
489*4882a593Smuzhiyun SOC_SINGLE("LINEOUT2N Switch", WM8993_LINE_OUTPUTS_VOLUME, 2, 1, 1),
490*4882a593Smuzhiyun SOC_SINGLE("LINEOUT2P Switch", WM8993_LINE_OUTPUTS_VOLUME, 1, 1, 1),
491*4882a593Smuzhiyun SOC_SINGLE_TLV("LINEOUT2 Volume", WM8993_LINE_OUTPUTS_VOLUME, 0, 1, 1,
492*4882a593Smuzhiyun 	       line_tlv),
493*4882a593Smuzhiyun };
494*4882a593Smuzhiyun 
hp_supply_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)495*4882a593Smuzhiyun static int hp_supply_event(struct snd_soc_dapm_widget *w,
496*4882a593Smuzhiyun 			   struct snd_kcontrol *kcontrol, int event)
497*4882a593Smuzhiyun {
498*4882a593Smuzhiyun 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
499*4882a593Smuzhiyun 	struct wm_hubs_data *hubs = snd_soc_component_get_drvdata(component);
500*4882a593Smuzhiyun 
501*4882a593Smuzhiyun 	switch (event) {
502*4882a593Smuzhiyun 	case SND_SOC_DAPM_PRE_PMU:
503*4882a593Smuzhiyun 		switch (hubs->hp_startup_mode) {
504*4882a593Smuzhiyun 		case 0:
505*4882a593Smuzhiyun 			break;
506*4882a593Smuzhiyun 		case 1:
507*4882a593Smuzhiyun 			/* Enable the headphone amp */
508*4882a593Smuzhiyun 			snd_soc_component_update_bits(component, WM8993_POWER_MANAGEMENT_1,
509*4882a593Smuzhiyun 					    WM8993_HPOUT1L_ENA |
510*4882a593Smuzhiyun 					    WM8993_HPOUT1R_ENA,
511*4882a593Smuzhiyun 					    WM8993_HPOUT1L_ENA |
512*4882a593Smuzhiyun 					    WM8993_HPOUT1R_ENA);
513*4882a593Smuzhiyun 
514*4882a593Smuzhiyun 			/* Enable the second stage */
515*4882a593Smuzhiyun 			snd_soc_component_update_bits(component, WM8993_ANALOGUE_HP_0,
516*4882a593Smuzhiyun 					    WM8993_HPOUT1L_DLY |
517*4882a593Smuzhiyun 					    WM8993_HPOUT1R_DLY,
518*4882a593Smuzhiyun 					    WM8993_HPOUT1L_DLY |
519*4882a593Smuzhiyun 					    WM8993_HPOUT1R_DLY);
520*4882a593Smuzhiyun 			break;
521*4882a593Smuzhiyun 		default:
522*4882a593Smuzhiyun 			dev_err(component->dev, "Unknown HP startup mode %d\n",
523*4882a593Smuzhiyun 				hubs->hp_startup_mode);
524*4882a593Smuzhiyun 			break;
525*4882a593Smuzhiyun 		}
526*4882a593Smuzhiyun 		break;
527*4882a593Smuzhiyun 
528*4882a593Smuzhiyun 	case SND_SOC_DAPM_PRE_PMD:
529*4882a593Smuzhiyun 		snd_soc_component_update_bits(component, WM8993_CHARGE_PUMP_1,
530*4882a593Smuzhiyun 				    WM8993_CP_ENA, 0);
531*4882a593Smuzhiyun 		break;
532*4882a593Smuzhiyun 	}
533*4882a593Smuzhiyun 
534*4882a593Smuzhiyun 	return 0;
535*4882a593Smuzhiyun }
536*4882a593Smuzhiyun 
hp_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)537*4882a593Smuzhiyun static int hp_event(struct snd_soc_dapm_widget *w,
538*4882a593Smuzhiyun 		    struct snd_kcontrol *kcontrol, int event)
539*4882a593Smuzhiyun {
540*4882a593Smuzhiyun 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
541*4882a593Smuzhiyun 	unsigned int reg = snd_soc_component_read(component, WM8993_ANALOGUE_HP_0);
542*4882a593Smuzhiyun 
543*4882a593Smuzhiyun 	switch (event) {
544*4882a593Smuzhiyun 	case SND_SOC_DAPM_POST_PMU:
545*4882a593Smuzhiyun 		snd_soc_component_update_bits(component, WM8993_CHARGE_PUMP_1,
546*4882a593Smuzhiyun 				    WM8993_CP_ENA, WM8993_CP_ENA);
547*4882a593Smuzhiyun 
548*4882a593Smuzhiyun 		msleep(5);
549*4882a593Smuzhiyun 
550*4882a593Smuzhiyun 		snd_soc_component_update_bits(component, WM8993_POWER_MANAGEMENT_1,
551*4882a593Smuzhiyun 				    WM8993_HPOUT1L_ENA | WM8993_HPOUT1R_ENA,
552*4882a593Smuzhiyun 				    WM8993_HPOUT1L_ENA | WM8993_HPOUT1R_ENA);
553*4882a593Smuzhiyun 
554*4882a593Smuzhiyun 		reg |= WM8993_HPOUT1L_DLY | WM8993_HPOUT1R_DLY;
555*4882a593Smuzhiyun 		snd_soc_component_write(component, WM8993_ANALOGUE_HP_0, reg);
556*4882a593Smuzhiyun 
557*4882a593Smuzhiyun 		snd_soc_component_update_bits(component, WM8993_DC_SERVO_1,
558*4882a593Smuzhiyun 				    WM8993_DCS_TIMER_PERIOD_01_MASK, 0);
559*4882a593Smuzhiyun 
560*4882a593Smuzhiyun 		enable_dc_servo(component);
561*4882a593Smuzhiyun 
562*4882a593Smuzhiyun 		reg |= WM8993_HPOUT1R_OUTP | WM8993_HPOUT1R_RMV_SHORT |
563*4882a593Smuzhiyun 			WM8993_HPOUT1L_OUTP | WM8993_HPOUT1L_RMV_SHORT;
564*4882a593Smuzhiyun 		snd_soc_component_write(component, WM8993_ANALOGUE_HP_0, reg);
565*4882a593Smuzhiyun 		break;
566*4882a593Smuzhiyun 
567*4882a593Smuzhiyun 	case SND_SOC_DAPM_PRE_PMD:
568*4882a593Smuzhiyun 		snd_soc_component_update_bits(component, WM8993_ANALOGUE_HP_0,
569*4882a593Smuzhiyun 				    WM8993_HPOUT1L_OUTP |
570*4882a593Smuzhiyun 				    WM8993_HPOUT1R_OUTP |
571*4882a593Smuzhiyun 				    WM8993_HPOUT1L_RMV_SHORT |
572*4882a593Smuzhiyun 				    WM8993_HPOUT1R_RMV_SHORT, 0);
573*4882a593Smuzhiyun 
574*4882a593Smuzhiyun 		snd_soc_component_update_bits(component, WM8993_ANALOGUE_HP_0,
575*4882a593Smuzhiyun 				    WM8993_HPOUT1L_DLY |
576*4882a593Smuzhiyun 				    WM8993_HPOUT1R_DLY, 0);
577*4882a593Smuzhiyun 
578*4882a593Smuzhiyun 		snd_soc_component_write(component, WM8993_DC_SERVO_0, 0);
579*4882a593Smuzhiyun 
580*4882a593Smuzhiyun 		snd_soc_component_update_bits(component, WM8993_POWER_MANAGEMENT_1,
581*4882a593Smuzhiyun 				    WM8993_HPOUT1L_ENA | WM8993_HPOUT1R_ENA,
582*4882a593Smuzhiyun 				    0);
583*4882a593Smuzhiyun 		break;
584*4882a593Smuzhiyun 	}
585*4882a593Smuzhiyun 
586*4882a593Smuzhiyun 	return 0;
587*4882a593Smuzhiyun }
588*4882a593Smuzhiyun 
earpiece_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * control,int event)589*4882a593Smuzhiyun static int earpiece_event(struct snd_soc_dapm_widget *w,
590*4882a593Smuzhiyun 			  struct snd_kcontrol *control, int event)
591*4882a593Smuzhiyun {
592*4882a593Smuzhiyun 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
593*4882a593Smuzhiyun 	u16 reg = snd_soc_component_read(component, WM8993_ANTIPOP1) & ~WM8993_HPOUT2_IN_ENA;
594*4882a593Smuzhiyun 
595*4882a593Smuzhiyun 	switch (event) {
596*4882a593Smuzhiyun 	case SND_SOC_DAPM_PRE_PMU:
597*4882a593Smuzhiyun 		reg |= WM8993_HPOUT2_IN_ENA;
598*4882a593Smuzhiyun 		snd_soc_component_write(component, WM8993_ANTIPOP1, reg);
599*4882a593Smuzhiyun 		udelay(50);
600*4882a593Smuzhiyun 		break;
601*4882a593Smuzhiyun 
602*4882a593Smuzhiyun 	case SND_SOC_DAPM_POST_PMD:
603*4882a593Smuzhiyun 		snd_soc_component_write(component, WM8993_ANTIPOP1, reg);
604*4882a593Smuzhiyun 		break;
605*4882a593Smuzhiyun 
606*4882a593Smuzhiyun 	default:
607*4882a593Smuzhiyun 		WARN(1, "Invalid event %d\n", event);
608*4882a593Smuzhiyun 		break;
609*4882a593Smuzhiyun 	}
610*4882a593Smuzhiyun 
611*4882a593Smuzhiyun 	return 0;
612*4882a593Smuzhiyun }
613*4882a593Smuzhiyun 
lineout_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * control,int event)614*4882a593Smuzhiyun static int lineout_event(struct snd_soc_dapm_widget *w,
615*4882a593Smuzhiyun 			 struct snd_kcontrol *control, int event)
616*4882a593Smuzhiyun {
617*4882a593Smuzhiyun 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
618*4882a593Smuzhiyun 	struct wm_hubs_data *hubs = snd_soc_component_get_drvdata(component);
619*4882a593Smuzhiyun 	bool *flag;
620*4882a593Smuzhiyun 
621*4882a593Smuzhiyun 	switch (w->shift) {
622*4882a593Smuzhiyun 	case WM8993_LINEOUT1N_ENA_SHIFT:
623*4882a593Smuzhiyun 		flag = &hubs->lineout1n_ena;
624*4882a593Smuzhiyun 		break;
625*4882a593Smuzhiyun 	case WM8993_LINEOUT1P_ENA_SHIFT:
626*4882a593Smuzhiyun 		flag = &hubs->lineout1p_ena;
627*4882a593Smuzhiyun 		break;
628*4882a593Smuzhiyun 	case WM8993_LINEOUT2N_ENA_SHIFT:
629*4882a593Smuzhiyun 		flag = &hubs->lineout2n_ena;
630*4882a593Smuzhiyun 		break;
631*4882a593Smuzhiyun 	case WM8993_LINEOUT2P_ENA_SHIFT:
632*4882a593Smuzhiyun 		flag = &hubs->lineout2p_ena;
633*4882a593Smuzhiyun 		break;
634*4882a593Smuzhiyun 	default:
635*4882a593Smuzhiyun 		WARN(1, "Unknown line output");
636*4882a593Smuzhiyun 		return -EINVAL;
637*4882a593Smuzhiyun 	}
638*4882a593Smuzhiyun 
639*4882a593Smuzhiyun 	*flag = SND_SOC_DAPM_EVENT_ON(event);
640*4882a593Smuzhiyun 
641*4882a593Smuzhiyun 	return 0;
642*4882a593Smuzhiyun }
643*4882a593Smuzhiyun 
micbias_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)644*4882a593Smuzhiyun static int micbias_event(struct snd_soc_dapm_widget *w,
645*4882a593Smuzhiyun 			 struct snd_kcontrol *kcontrol, int event)
646*4882a593Smuzhiyun {
647*4882a593Smuzhiyun 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
648*4882a593Smuzhiyun 	struct wm_hubs_data *hubs = snd_soc_component_get_drvdata(component);
649*4882a593Smuzhiyun 
650*4882a593Smuzhiyun 	switch (w->shift) {
651*4882a593Smuzhiyun 	case WM8993_MICB1_ENA_SHIFT:
652*4882a593Smuzhiyun 		if (hubs->micb1_delay)
653*4882a593Smuzhiyun 			msleep(hubs->micb1_delay);
654*4882a593Smuzhiyun 		break;
655*4882a593Smuzhiyun 	case WM8993_MICB2_ENA_SHIFT:
656*4882a593Smuzhiyun 		if (hubs->micb2_delay)
657*4882a593Smuzhiyun 			msleep(hubs->micb2_delay);
658*4882a593Smuzhiyun 		break;
659*4882a593Smuzhiyun 	default:
660*4882a593Smuzhiyun 		return -EINVAL;
661*4882a593Smuzhiyun 	}
662*4882a593Smuzhiyun 
663*4882a593Smuzhiyun 	return 0;
664*4882a593Smuzhiyun }
665*4882a593Smuzhiyun 
wm_hubs_update_class_w(struct snd_soc_component * component)666*4882a593Smuzhiyun void wm_hubs_update_class_w(struct snd_soc_component *component)
667*4882a593Smuzhiyun {
668*4882a593Smuzhiyun 	struct wm_hubs_data *hubs = snd_soc_component_get_drvdata(component);
669*4882a593Smuzhiyun 	int enable = WM8993_CP_DYN_V | WM8993_CP_DYN_FREQ;
670*4882a593Smuzhiyun 
671*4882a593Smuzhiyun 	if (!wm_hubs_dac_hp_direct(component))
672*4882a593Smuzhiyun 		enable = false;
673*4882a593Smuzhiyun 
674*4882a593Smuzhiyun 	if (hubs->check_class_w_digital && !hubs->check_class_w_digital(component))
675*4882a593Smuzhiyun 		enable = false;
676*4882a593Smuzhiyun 
677*4882a593Smuzhiyun 	dev_vdbg(component->dev, "Class W %s\n", enable ? "enabled" : "disabled");
678*4882a593Smuzhiyun 
679*4882a593Smuzhiyun 	snd_soc_component_update_bits(component, WM8993_CLASS_W_0,
680*4882a593Smuzhiyun 			    WM8993_CP_DYN_V | WM8993_CP_DYN_FREQ, enable);
681*4882a593Smuzhiyun 
682*4882a593Smuzhiyun 	snd_soc_component_write(component, WM8993_LEFT_OUTPUT_VOLUME,
683*4882a593Smuzhiyun 		      snd_soc_component_read(component, WM8993_LEFT_OUTPUT_VOLUME));
684*4882a593Smuzhiyun 	snd_soc_component_write(component, WM8993_RIGHT_OUTPUT_VOLUME,
685*4882a593Smuzhiyun 		      snd_soc_component_read(component, WM8993_RIGHT_OUTPUT_VOLUME));
686*4882a593Smuzhiyun }
687*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(wm_hubs_update_class_w);
688*4882a593Smuzhiyun 
689*4882a593Smuzhiyun #define WM_HUBS_SINGLE_W(xname, reg, shift, max, invert) \
690*4882a593Smuzhiyun 	SOC_SINGLE_EXT(xname, reg, shift, max, invert, \
691*4882a593Smuzhiyun 		snd_soc_dapm_get_volsw, class_w_put_volsw)
692*4882a593Smuzhiyun 
class_w_put_volsw(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)693*4882a593Smuzhiyun static int class_w_put_volsw(struct snd_kcontrol *kcontrol,
694*4882a593Smuzhiyun 			      struct snd_ctl_elem_value *ucontrol)
695*4882a593Smuzhiyun {
696*4882a593Smuzhiyun 	struct snd_soc_component *component = snd_soc_dapm_kcontrol_component(kcontrol);
697*4882a593Smuzhiyun 	int ret;
698*4882a593Smuzhiyun 
699*4882a593Smuzhiyun 	ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
700*4882a593Smuzhiyun 
701*4882a593Smuzhiyun 	wm_hubs_update_class_w(component);
702*4882a593Smuzhiyun 
703*4882a593Smuzhiyun 	return ret;
704*4882a593Smuzhiyun }
705*4882a593Smuzhiyun 
706*4882a593Smuzhiyun #define WM_HUBS_ENUM_W(xname, xenum) \
707*4882a593Smuzhiyun {	.iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
708*4882a593Smuzhiyun 	.info = snd_soc_info_enum_double, \
709*4882a593Smuzhiyun 	.get = snd_soc_dapm_get_enum_double, \
710*4882a593Smuzhiyun 	.put = class_w_put_double, \
711*4882a593Smuzhiyun 	.private_value = (unsigned long)&xenum }
712*4882a593Smuzhiyun 
class_w_put_double(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)713*4882a593Smuzhiyun static int class_w_put_double(struct snd_kcontrol *kcontrol,
714*4882a593Smuzhiyun 			      struct snd_ctl_elem_value *ucontrol)
715*4882a593Smuzhiyun {
716*4882a593Smuzhiyun 	struct snd_soc_component *component = snd_soc_dapm_kcontrol_component(kcontrol);
717*4882a593Smuzhiyun 	int ret;
718*4882a593Smuzhiyun 
719*4882a593Smuzhiyun 	ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
720*4882a593Smuzhiyun 
721*4882a593Smuzhiyun 	wm_hubs_update_class_w(component);
722*4882a593Smuzhiyun 
723*4882a593Smuzhiyun 	return ret;
724*4882a593Smuzhiyun }
725*4882a593Smuzhiyun 
726*4882a593Smuzhiyun static const char *hp_mux_text[] = {
727*4882a593Smuzhiyun 	"Mixer",
728*4882a593Smuzhiyun 	"DAC",
729*4882a593Smuzhiyun };
730*4882a593Smuzhiyun 
731*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(hpl_enum,
732*4882a593Smuzhiyun 			    WM8993_OUTPUT_MIXER1, 8, hp_mux_text);
733*4882a593Smuzhiyun 
734*4882a593Smuzhiyun const struct snd_kcontrol_new wm_hubs_hpl_mux =
735*4882a593Smuzhiyun 	WM_HUBS_ENUM_W("Left Headphone Mux", hpl_enum);
736*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(wm_hubs_hpl_mux);
737*4882a593Smuzhiyun 
738*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(hpr_enum,
739*4882a593Smuzhiyun 			    WM8993_OUTPUT_MIXER2, 8, hp_mux_text);
740*4882a593Smuzhiyun 
741*4882a593Smuzhiyun const struct snd_kcontrol_new wm_hubs_hpr_mux =
742*4882a593Smuzhiyun 	WM_HUBS_ENUM_W("Right Headphone Mux", hpr_enum);
743*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(wm_hubs_hpr_mux);
744*4882a593Smuzhiyun 
745*4882a593Smuzhiyun static const struct snd_kcontrol_new in1l_pga[] = {
746*4882a593Smuzhiyun SOC_DAPM_SINGLE("IN1LP Switch", WM8993_INPUT_MIXER2, 5, 1, 0),
747*4882a593Smuzhiyun SOC_DAPM_SINGLE("IN1LN Switch", WM8993_INPUT_MIXER2, 4, 1, 0),
748*4882a593Smuzhiyun };
749*4882a593Smuzhiyun 
750*4882a593Smuzhiyun static const struct snd_kcontrol_new in1r_pga[] = {
751*4882a593Smuzhiyun SOC_DAPM_SINGLE("IN1RP Switch", WM8993_INPUT_MIXER2, 1, 1, 0),
752*4882a593Smuzhiyun SOC_DAPM_SINGLE("IN1RN Switch", WM8993_INPUT_MIXER2, 0, 1, 0),
753*4882a593Smuzhiyun };
754*4882a593Smuzhiyun 
755*4882a593Smuzhiyun static const struct snd_kcontrol_new in2l_pga[] = {
756*4882a593Smuzhiyun SOC_DAPM_SINGLE("IN2LP Switch", WM8993_INPUT_MIXER2, 7, 1, 0),
757*4882a593Smuzhiyun SOC_DAPM_SINGLE("IN2LN Switch", WM8993_INPUT_MIXER2, 6, 1, 0),
758*4882a593Smuzhiyun };
759*4882a593Smuzhiyun 
760*4882a593Smuzhiyun static const struct snd_kcontrol_new in2r_pga[] = {
761*4882a593Smuzhiyun SOC_DAPM_SINGLE("IN2RP Switch", WM8993_INPUT_MIXER2, 3, 1, 0),
762*4882a593Smuzhiyun SOC_DAPM_SINGLE("IN2RN Switch", WM8993_INPUT_MIXER2, 2, 1, 0),
763*4882a593Smuzhiyun };
764*4882a593Smuzhiyun 
765*4882a593Smuzhiyun static const struct snd_kcontrol_new mixinl[] = {
766*4882a593Smuzhiyun SOC_DAPM_SINGLE("IN2L Switch", WM8993_INPUT_MIXER3, 8, 1, 0),
767*4882a593Smuzhiyun SOC_DAPM_SINGLE("IN1L Switch", WM8993_INPUT_MIXER3, 5, 1, 0),
768*4882a593Smuzhiyun };
769*4882a593Smuzhiyun 
770*4882a593Smuzhiyun static const struct snd_kcontrol_new mixinr[] = {
771*4882a593Smuzhiyun SOC_DAPM_SINGLE("IN2R Switch", WM8993_INPUT_MIXER4, 8, 1, 0),
772*4882a593Smuzhiyun SOC_DAPM_SINGLE("IN1R Switch", WM8993_INPUT_MIXER4, 5, 1, 0),
773*4882a593Smuzhiyun };
774*4882a593Smuzhiyun 
775*4882a593Smuzhiyun static const struct snd_kcontrol_new left_output_mixer[] = {
776*4882a593Smuzhiyun WM_HUBS_SINGLE_W("Right Input Switch", WM8993_OUTPUT_MIXER1, 7, 1, 0),
777*4882a593Smuzhiyun WM_HUBS_SINGLE_W("Left Input Switch", WM8993_OUTPUT_MIXER1, 6, 1, 0),
778*4882a593Smuzhiyun WM_HUBS_SINGLE_W("IN2RN Switch", WM8993_OUTPUT_MIXER1, 5, 1, 0),
779*4882a593Smuzhiyun WM_HUBS_SINGLE_W("IN2LN Switch", WM8993_OUTPUT_MIXER1, 4, 1, 0),
780*4882a593Smuzhiyun WM_HUBS_SINGLE_W("IN2LP Switch", WM8993_OUTPUT_MIXER1, 1, 1, 0),
781*4882a593Smuzhiyun WM_HUBS_SINGLE_W("IN1R Switch", WM8993_OUTPUT_MIXER1, 3, 1, 0),
782*4882a593Smuzhiyun WM_HUBS_SINGLE_W("IN1L Switch", WM8993_OUTPUT_MIXER1, 2, 1, 0),
783*4882a593Smuzhiyun WM_HUBS_SINGLE_W("DAC Switch", WM8993_OUTPUT_MIXER1, 0, 1, 0),
784*4882a593Smuzhiyun };
785*4882a593Smuzhiyun 
786*4882a593Smuzhiyun static const struct snd_kcontrol_new right_output_mixer[] = {
787*4882a593Smuzhiyun WM_HUBS_SINGLE_W("Left Input Switch", WM8993_OUTPUT_MIXER2, 7, 1, 0),
788*4882a593Smuzhiyun WM_HUBS_SINGLE_W("Right Input Switch", WM8993_OUTPUT_MIXER2, 6, 1, 0),
789*4882a593Smuzhiyun WM_HUBS_SINGLE_W("IN2LN Switch", WM8993_OUTPUT_MIXER2, 5, 1, 0),
790*4882a593Smuzhiyun WM_HUBS_SINGLE_W("IN2RN Switch", WM8993_OUTPUT_MIXER2, 4, 1, 0),
791*4882a593Smuzhiyun WM_HUBS_SINGLE_W("IN1L Switch", WM8993_OUTPUT_MIXER2, 3, 1, 0),
792*4882a593Smuzhiyun WM_HUBS_SINGLE_W("IN1R Switch", WM8993_OUTPUT_MIXER2, 2, 1, 0),
793*4882a593Smuzhiyun WM_HUBS_SINGLE_W("IN2RP Switch", WM8993_OUTPUT_MIXER2, 1, 1, 0),
794*4882a593Smuzhiyun WM_HUBS_SINGLE_W("DAC Switch", WM8993_OUTPUT_MIXER2, 0, 1, 0),
795*4882a593Smuzhiyun };
796*4882a593Smuzhiyun 
797*4882a593Smuzhiyun static const struct snd_kcontrol_new earpiece_mixer[] = {
798*4882a593Smuzhiyun SOC_DAPM_SINGLE("Direct Voice Switch", WM8993_HPOUT2_MIXER, 5, 1, 0),
799*4882a593Smuzhiyun SOC_DAPM_SINGLE("Left Output Switch", WM8993_HPOUT2_MIXER, 4, 1, 0),
800*4882a593Smuzhiyun SOC_DAPM_SINGLE("Right Output Switch", WM8993_HPOUT2_MIXER, 3, 1, 0),
801*4882a593Smuzhiyun };
802*4882a593Smuzhiyun 
803*4882a593Smuzhiyun static const struct snd_kcontrol_new left_speaker_boost[] = {
804*4882a593Smuzhiyun SOC_DAPM_SINGLE("Direct Voice Switch", WM8993_SPKOUT_MIXERS, 5, 1, 0),
805*4882a593Smuzhiyun SOC_DAPM_SINGLE("SPKL Switch", WM8993_SPKOUT_MIXERS, 4, 1, 0),
806*4882a593Smuzhiyun SOC_DAPM_SINGLE("SPKR Switch", WM8993_SPKOUT_MIXERS, 3, 1, 0),
807*4882a593Smuzhiyun };
808*4882a593Smuzhiyun 
809*4882a593Smuzhiyun static const struct snd_kcontrol_new right_speaker_boost[] = {
810*4882a593Smuzhiyun SOC_DAPM_SINGLE("Direct Voice Switch", WM8993_SPKOUT_MIXERS, 2, 1, 0),
811*4882a593Smuzhiyun SOC_DAPM_SINGLE("SPKL Switch", WM8993_SPKOUT_MIXERS, 1, 1, 0),
812*4882a593Smuzhiyun SOC_DAPM_SINGLE("SPKR Switch", WM8993_SPKOUT_MIXERS, 0, 1, 0),
813*4882a593Smuzhiyun };
814*4882a593Smuzhiyun 
815*4882a593Smuzhiyun static const struct snd_kcontrol_new line1_mix[] = {
816*4882a593Smuzhiyun SOC_DAPM_SINGLE("IN1R Switch", WM8993_LINE_MIXER1, 2, 1, 0),
817*4882a593Smuzhiyun SOC_DAPM_SINGLE("IN1L Switch", WM8993_LINE_MIXER1, 1, 1, 0),
818*4882a593Smuzhiyun SOC_DAPM_SINGLE("Output Switch", WM8993_LINE_MIXER1, 0, 1, 0),
819*4882a593Smuzhiyun };
820*4882a593Smuzhiyun 
821*4882a593Smuzhiyun static const struct snd_kcontrol_new line1n_mix[] = {
822*4882a593Smuzhiyun SOC_DAPM_SINGLE("Left Output Switch", WM8993_LINE_MIXER1, 6, 1, 0),
823*4882a593Smuzhiyun SOC_DAPM_SINGLE("Right Output Switch", WM8993_LINE_MIXER1, 5, 1, 0),
824*4882a593Smuzhiyun };
825*4882a593Smuzhiyun 
826*4882a593Smuzhiyun static const struct snd_kcontrol_new line1p_mix[] = {
827*4882a593Smuzhiyun SOC_DAPM_SINGLE("Left Output Switch", WM8993_LINE_MIXER1, 0, 1, 0),
828*4882a593Smuzhiyun };
829*4882a593Smuzhiyun 
830*4882a593Smuzhiyun static const struct snd_kcontrol_new line2_mix[] = {
831*4882a593Smuzhiyun SOC_DAPM_SINGLE("IN1L Switch", WM8993_LINE_MIXER2, 2, 1, 0),
832*4882a593Smuzhiyun SOC_DAPM_SINGLE("IN1R Switch", WM8993_LINE_MIXER2, 1, 1, 0),
833*4882a593Smuzhiyun SOC_DAPM_SINGLE("Output Switch", WM8993_LINE_MIXER2, 0, 1, 0),
834*4882a593Smuzhiyun };
835*4882a593Smuzhiyun 
836*4882a593Smuzhiyun static const struct snd_kcontrol_new line2n_mix[] = {
837*4882a593Smuzhiyun SOC_DAPM_SINGLE("Left Output Switch", WM8993_LINE_MIXER2, 5, 1, 0),
838*4882a593Smuzhiyun SOC_DAPM_SINGLE("Right Output Switch", WM8993_LINE_MIXER2, 6, 1, 0),
839*4882a593Smuzhiyun };
840*4882a593Smuzhiyun 
841*4882a593Smuzhiyun static const struct snd_kcontrol_new line2p_mix[] = {
842*4882a593Smuzhiyun SOC_DAPM_SINGLE("Right Output Switch", WM8993_LINE_MIXER2, 0, 1, 0),
843*4882a593Smuzhiyun };
844*4882a593Smuzhiyun 
845*4882a593Smuzhiyun static const struct snd_soc_dapm_widget analogue_dapm_widgets[] = {
846*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("IN1LN"),
847*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("IN1LP"),
848*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("IN2LN"),
849*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("IN2LP:VXRN"),
850*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("IN1RN"),
851*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("IN1RP"),
852*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("IN2RN"),
853*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("IN2RP:VXRP"),
854*4882a593Smuzhiyun 
855*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("MICBIAS2", WM8993_POWER_MANAGEMENT_1, 5, 0,
856*4882a593Smuzhiyun 		    micbias_event, SND_SOC_DAPM_POST_PMU),
857*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("MICBIAS1", WM8993_POWER_MANAGEMENT_1, 4, 0,
858*4882a593Smuzhiyun 		    micbias_event, SND_SOC_DAPM_POST_PMU),
859*4882a593Smuzhiyun 
860*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("IN1L PGA", WM8993_POWER_MANAGEMENT_2, 6, 0,
861*4882a593Smuzhiyun 		   in1l_pga, ARRAY_SIZE(in1l_pga)),
862*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("IN1R PGA", WM8993_POWER_MANAGEMENT_2, 4, 0,
863*4882a593Smuzhiyun 		   in1r_pga, ARRAY_SIZE(in1r_pga)),
864*4882a593Smuzhiyun 
865*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("IN2L PGA", WM8993_POWER_MANAGEMENT_2, 7, 0,
866*4882a593Smuzhiyun 		   in2l_pga, ARRAY_SIZE(in2l_pga)),
867*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("IN2R PGA", WM8993_POWER_MANAGEMENT_2, 5, 0,
868*4882a593Smuzhiyun 		   in2r_pga, ARRAY_SIZE(in2r_pga)),
869*4882a593Smuzhiyun 
870*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("MIXINL", WM8993_POWER_MANAGEMENT_2, 9, 0,
871*4882a593Smuzhiyun 		   mixinl, ARRAY_SIZE(mixinl)),
872*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("MIXINR", WM8993_POWER_MANAGEMENT_2, 8, 0,
873*4882a593Smuzhiyun 		   mixinr, ARRAY_SIZE(mixinr)),
874*4882a593Smuzhiyun 
875*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("Left Output Mixer", WM8993_POWER_MANAGEMENT_3, 5, 0,
876*4882a593Smuzhiyun 		   left_output_mixer, ARRAY_SIZE(left_output_mixer)),
877*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("Right Output Mixer", WM8993_POWER_MANAGEMENT_3, 4, 0,
878*4882a593Smuzhiyun 		   right_output_mixer, ARRAY_SIZE(right_output_mixer)),
879*4882a593Smuzhiyun 
880*4882a593Smuzhiyun SND_SOC_DAPM_PGA("Left Output PGA", WM8993_POWER_MANAGEMENT_3, 7, 0, NULL, 0),
881*4882a593Smuzhiyun SND_SOC_DAPM_PGA("Right Output PGA", WM8993_POWER_MANAGEMENT_3, 6, 0, NULL, 0),
882*4882a593Smuzhiyun 
883*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("Headphone Supply", SND_SOC_NOPM, 0, 0, hp_supply_event,
884*4882a593Smuzhiyun 		    SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
885*4882a593Smuzhiyun SND_SOC_DAPM_OUT_DRV_E("Headphone PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
886*4882a593Smuzhiyun 		       hp_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
887*4882a593Smuzhiyun 
888*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("Earpiece Mixer", SND_SOC_NOPM, 0, 0,
889*4882a593Smuzhiyun 		   earpiece_mixer, ARRAY_SIZE(earpiece_mixer)),
890*4882a593Smuzhiyun SND_SOC_DAPM_PGA_E("Earpiece Driver", WM8993_POWER_MANAGEMENT_1, 11, 0,
891*4882a593Smuzhiyun 		   NULL, 0, earpiece_event,
892*4882a593Smuzhiyun 		   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
893*4882a593Smuzhiyun 
894*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("SPKL Boost", SND_SOC_NOPM, 0, 0,
895*4882a593Smuzhiyun 		   left_speaker_boost, ARRAY_SIZE(left_speaker_boost)),
896*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("SPKR Boost", SND_SOC_NOPM, 0, 0,
897*4882a593Smuzhiyun 		   right_speaker_boost, ARRAY_SIZE(right_speaker_boost)),
898*4882a593Smuzhiyun 
899*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("TSHUT", WM8993_POWER_MANAGEMENT_2, 14, 0, NULL, 0),
900*4882a593Smuzhiyun SND_SOC_DAPM_OUT_DRV("SPKL Driver", WM8993_POWER_MANAGEMENT_1, 12, 0,
901*4882a593Smuzhiyun 		     NULL, 0),
902*4882a593Smuzhiyun SND_SOC_DAPM_OUT_DRV("SPKR Driver", WM8993_POWER_MANAGEMENT_1, 13, 0,
903*4882a593Smuzhiyun 		     NULL, 0),
904*4882a593Smuzhiyun 
905*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("LINEOUT1 Mixer", SND_SOC_NOPM, 0, 0,
906*4882a593Smuzhiyun 		   line1_mix, ARRAY_SIZE(line1_mix)),
907*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("LINEOUT2 Mixer", SND_SOC_NOPM, 0, 0,
908*4882a593Smuzhiyun 		   line2_mix, ARRAY_SIZE(line2_mix)),
909*4882a593Smuzhiyun 
910*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("LINEOUT1N Mixer", SND_SOC_NOPM, 0, 0,
911*4882a593Smuzhiyun 		   line1n_mix, ARRAY_SIZE(line1n_mix)),
912*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("LINEOUT1P Mixer", SND_SOC_NOPM, 0, 0,
913*4882a593Smuzhiyun 		   line1p_mix, ARRAY_SIZE(line1p_mix)),
914*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("LINEOUT2N Mixer", SND_SOC_NOPM, 0, 0,
915*4882a593Smuzhiyun 		   line2n_mix, ARRAY_SIZE(line2n_mix)),
916*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("LINEOUT2P Mixer", SND_SOC_NOPM, 0, 0,
917*4882a593Smuzhiyun 		   line2p_mix, ARRAY_SIZE(line2p_mix)),
918*4882a593Smuzhiyun 
919*4882a593Smuzhiyun SND_SOC_DAPM_OUT_DRV_E("LINEOUT1N Driver", WM8993_POWER_MANAGEMENT_3, 13, 0,
920*4882a593Smuzhiyun 		       NULL, 0, lineout_event,
921*4882a593Smuzhiyun 		     SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
922*4882a593Smuzhiyun SND_SOC_DAPM_OUT_DRV_E("LINEOUT1P Driver", WM8993_POWER_MANAGEMENT_3, 12, 0,
923*4882a593Smuzhiyun 		       NULL, 0, lineout_event,
924*4882a593Smuzhiyun 		       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
925*4882a593Smuzhiyun SND_SOC_DAPM_OUT_DRV_E("LINEOUT2N Driver", WM8993_POWER_MANAGEMENT_3, 11, 0,
926*4882a593Smuzhiyun 		       NULL, 0, lineout_event,
927*4882a593Smuzhiyun 		       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
928*4882a593Smuzhiyun SND_SOC_DAPM_OUT_DRV_E("LINEOUT2P Driver", WM8993_POWER_MANAGEMENT_3, 10, 0,
929*4882a593Smuzhiyun 		       NULL, 0, lineout_event,
930*4882a593Smuzhiyun 		       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
931*4882a593Smuzhiyun 
932*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("SPKOUTLP"),
933*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("SPKOUTLN"),
934*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("SPKOUTRP"),
935*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("SPKOUTRN"),
936*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("HPOUT1L"),
937*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("HPOUT1R"),
938*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("HPOUT2P"),
939*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("HPOUT2N"),
940*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("LINEOUT1P"),
941*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("LINEOUT1N"),
942*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("LINEOUT2P"),
943*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("LINEOUT2N"),
944*4882a593Smuzhiyun };
945*4882a593Smuzhiyun 
946*4882a593Smuzhiyun static const struct snd_soc_dapm_route analogue_routes[] = {
947*4882a593Smuzhiyun 	{ "MICBIAS1", NULL, "CLK_SYS" },
948*4882a593Smuzhiyun 	{ "MICBIAS2", NULL, "CLK_SYS" },
949*4882a593Smuzhiyun 
950*4882a593Smuzhiyun 	{ "IN1L PGA", "IN1LP Switch", "IN1LP" },
951*4882a593Smuzhiyun 	{ "IN1L PGA", "IN1LN Switch", "IN1LN" },
952*4882a593Smuzhiyun 
953*4882a593Smuzhiyun 	{ "IN1L PGA", NULL, "VMID" },
954*4882a593Smuzhiyun 	{ "IN1R PGA", NULL, "VMID" },
955*4882a593Smuzhiyun 	{ "IN2L PGA", NULL, "VMID" },
956*4882a593Smuzhiyun 	{ "IN2R PGA", NULL, "VMID" },
957*4882a593Smuzhiyun 
958*4882a593Smuzhiyun 	{ "IN1R PGA", "IN1RP Switch", "IN1RP" },
959*4882a593Smuzhiyun 	{ "IN1R PGA", "IN1RN Switch", "IN1RN" },
960*4882a593Smuzhiyun 
961*4882a593Smuzhiyun 	{ "IN2L PGA", "IN2LP Switch", "IN2LP:VXRN" },
962*4882a593Smuzhiyun 	{ "IN2L PGA", "IN2LN Switch", "IN2LN" },
963*4882a593Smuzhiyun 
964*4882a593Smuzhiyun 	{ "IN2R PGA", "IN2RP Switch", "IN2RP:VXRP" },
965*4882a593Smuzhiyun 	{ "IN2R PGA", "IN2RN Switch", "IN2RN" },
966*4882a593Smuzhiyun 
967*4882a593Smuzhiyun 	{ "Direct Voice", NULL, "IN2LP:VXRN" },
968*4882a593Smuzhiyun 	{ "Direct Voice", NULL, "IN2RP:VXRP" },
969*4882a593Smuzhiyun 
970*4882a593Smuzhiyun 	{ "MIXINL", "IN1L Switch", "IN1L PGA" },
971*4882a593Smuzhiyun 	{ "MIXINL", "IN2L Switch", "IN2L PGA" },
972*4882a593Smuzhiyun 	{ "MIXINL", NULL, "Direct Voice" },
973*4882a593Smuzhiyun 	{ "MIXINL", NULL, "IN1LP" },
974*4882a593Smuzhiyun 	{ "MIXINL", NULL, "Left Output Mixer" },
975*4882a593Smuzhiyun 	{ "MIXINL", NULL, "VMID" },
976*4882a593Smuzhiyun 
977*4882a593Smuzhiyun 	{ "MIXINR", "IN1R Switch", "IN1R PGA" },
978*4882a593Smuzhiyun 	{ "MIXINR", "IN2R Switch", "IN2R PGA" },
979*4882a593Smuzhiyun 	{ "MIXINR", NULL, "Direct Voice" },
980*4882a593Smuzhiyun 	{ "MIXINR", NULL, "IN1RP" },
981*4882a593Smuzhiyun 	{ "MIXINR", NULL, "Right Output Mixer" },
982*4882a593Smuzhiyun 	{ "MIXINR", NULL, "VMID" },
983*4882a593Smuzhiyun 
984*4882a593Smuzhiyun 	{ "ADCL", NULL, "MIXINL" },
985*4882a593Smuzhiyun 	{ "ADCR", NULL, "MIXINR" },
986*4882a593Smuzhiyun 
987*4882a593Smuzhiyun 	{ "Left Output Mixer", "Left Input Switch", "MIXINL" },
988*4882a593Smuzhiyun 	{ "Left Output Mixer", "Right Input Switch", "MIXINR" },
989*4882a593Smuzhiyun 	{ "Left Output Mixer", "IN2RN Switch", "IN2RN" },
990*4882a593Smuzhiyun 	{ "Left Output Mixer", "IN2LN Switch", "IN2LN" },
991*4882a593Smuzhiyun 	{ "Left Output Mixer", "IN2LP Switch", "IN2LP:VXRN" },
992*4882a593Smuzhiyun 	{ "Left Output Mixer", "IN1L Switch", "IN1L PGA" },
993*4882a593Smuzhiyun 	{ "Left Output Mixer", "IN1R Switch", "IN1R PGA" },
994*4882a593Smuzhiyun 
995*4882a593Smuzhiyun 	{ "Right Output Mixer", "Left Input Switch", "MIXINL" },
996*4882a593Smuzhiyun 	{ "Right Output Mixer", "Right Input Switch", "MIXINR" },
997*4882a593Smuzhiyun 	{ "Right Output Mixer", "IN2LN Switch", "IN2LN" },
998*4882a593Smuzhiyun 	{ "Right Output Mixer", "IN2RN Switch", "IN2RN" },
999*4882a593Smuzhiyun 	{ "Right Output Mixer", "IN2RP Switch", "IN2RP:VXRP" },
1000*4882a593Smuzhiyun 	{ "Right Output Mixer", "IN1L Switch", "IN1L PGA" },
1001*4882a593Smuzhiyun 	{ "Right Output Mixer", "IN1R Switch", "IN1R PGA" },
1002*4882a593Smuzhiyun 
1003*4882a593Smuzhiyun 	{ "Left Output PGA", NULL, "Left Output Mixer" },
1004*4882a593Smuzhiyun 	{ "Left Output PGA", NULL, "TOCLK" },
1005*4882a593Smuzhiyun 
1006*4882a593Smuzhiyun 	{ "Right Output PGA", NULL, "Right Output Mixer" },
1007*4882a593Smuzhiyun 	{ "Right Output PGA", NULL, "TOCLK" },
1008*4882a593Smuzhiyun 
1009*4882a593Smuzhiyun 	{ "Earpiece Mixer", "Direct Voice Switch", "Direct Voice" },
1010*4882a593Smuzhiyun 	{ "Earpiece Mixer", "Left Output Switch", "Left Output PGA" },
1011*4882a593Smuzhiyun 	{ "Earpiece Mixer", "Right Output Switch", "Right Output PGA" },
1012*4882a593Smuzhiyun 
1013*4882a593Smuzhiyun 	{ "Earpiece Driver", NULL, "VMID" },
1014*4882a593Smuzhiyun 	{ "Earpiece Driver", NULL, "Earpiece Mixer" },
1015*4882a593Smuzhiyun 	{ "HPOUT2N", NULL, "Earpiece Driver" },
1016*4882a593Smuzhiyun 	{ "HPOUT2P", NULL, "Earpiece Driver" },
1017*4882a593Smuzhiyun 
1018*4882a593Smuzhiyun 	{ "SPKL", "Input Switch", "MIXINL" },
1019*4882a593Smuzhiyun 	{ "SPKL", "IN1LP Switch", "IN1LP" },
1020*4882a593Smuzhiyun 	{ "SPKL", "Output Switch", "Left Output PGA" },
1021*4882a593Smuzhiyun 	{ "SPKL", NULL, "TOCLK" },
1022*4882a593Smuzhiyun 
1023*4882a593Smuzhiyun 	{ "SPKR", "Input Switch", "MIXINR" },
1024*4882a593Smuzhiyun 	{ "SPKR", "IN1RP Switch", "IN1RP" },
1025*4882a593Smuzhiyun 	{ "SPKR", "Output Switch", "Right Output PGA" },
1026*4882a593Smuzhiyun 	{ "SPKR", NULL, "TOCLK" },
1027*4882a593Smuzhiyun 
1028*4882a593Smuzhiyun 	{ "SPKL Boost", "Direct Voice Switch", "Direct Voice" },
1029*4882a593Smuzhiyun 	{ "SPKL Boost", "SPKL Switch", "SPKL" },
1030*4882a593Smuzhiyun 	{ "SPKL Boost", "SPKR Switch", "SPKR" },
1031*4882a593Smuzhiyun 
1032*4882a593Smuzhiyun 	{ "SPKR Boost", "Direct Voice Switch", "Direct Voice" },
1033*4882a593Smuzhiyun 	{ "SPKR Boost", "SPKR Switch", "SPKR" },
1034*4882a593Smuzhiyun 	{ "SPKR Boost", "SPKL Switch", "SPKL" },
1035*4882a593Smuzhiyun 
1036*4882a593Smuzhiyun 	{ "SPKL Driver", NULL, "VMID" },
1037*4882a593Smuzhiyun 	{ "SPKL Driver", NULL, "SPKL Boost" },
1038*4882a593Smuzhiyun 	{ "SPKL Driver", NULL, "CLK_SYS" },
1039*4882a593Smuzhiyun 	{ "SPKL Driver", NULL, "TSHUT" },
1040*4882a593Smuzhiyun 
1041*4882a593Smuzhiyun 	{ "SPKR Driver", NULL, "VMID" },
1042*4882a593Smuzhiyun 	{ "SPKR Driver", NULL, "SPKR Boost" },
1043*4882a593Smuzhiyun 	{ "SPKR Driver", NULL, "CLK_SYS" },
1044*4882a593Smuzhiyun 	{ "SPKR Driver", NULL, "TSHUT" },
1045*4882a593Smuzhiyun 
1046*4882a593Smuzhiyun 	{ "SPKOUTLP", NULL, "SPKL Driver" },
1047*4882a593Smuzhiyun 	{ "SPKOUTLN", NULL, "SPKL Driver" },
1048*4882a593Smuzhiyun 	{ "SPKOUTRP", NULL, "SPKR Driver" },
1049*4882a593Smuzhiyun 	{ "SPKOUTRN", NULL, "SPKR Driver" },
1050*4882a593Smuzhiyun 
1051*4882a593Smuzhiyun 	{ "Left Headphone Mux", "Mixer", "Left Output PGA" },
1052*4882a593Smuzhiyun 	{ "Right Headphone Mux", "Mixer", "Right Output PGA" },
1053*4882a593Smuzhiyun 
1054*4882a593Smuzhiyun 	{ "Headphone PGA", NULL, "Left Headphone Mux" },
1055*4882a593Smuzhiyun 	{ "Headphone PGA", NULL, "Right Headphone Mux" },
1056*4882a593Smuzhiyun 	{ "Headphone PGA", NULL, "VMID" },
1057*4882a593Smuzhiyun 	{ "Headphone PGA", NULL, "CLK_SYS" },
1058*4882a593Smuzhiyun 	{ "Headphone PGA", NULL, "Headphone Supply" },
1059*4882a593Smuzhiyun 
1060*4882a593Smuzhiyun 	{ "HPOUT1L", NULL, "Headphone PGA" },
1061*4882a593Smuzhiyun 	{ "HPOUT1R", NULL, "Headphone PGA" },
1062*4882a593Smuzhiyun 
1063*4882a593Smuzhiyun 	{ "LINEOUT1N Driver", NULL, "VMID" },
1064*4882a593Smuzhiyun 	{ "LINEOUT1P Driver", NULL, "VMID" },
1065*4882a593Smuzhiyun 	{ "LINEOUT2N Driver", NULL, "VMID" },
1066*4882a593Smuzhiyun 	{ "LINEOUT2P Driver", NULL, "VMID" },
1067*4882a593Smuzhiyun 
1068*4882a593Smuzhiyun 	{ "LINEOUT1N", NULL, "LINEOUT1N Driver" },
1069*4882a593Smuzhiyun 	{ "LINEOUT1P", NULL, "LINEOUT1P Driver" },
1070*4882a593Smuzhiyun 	{ "LINEOUT2N", NULL, "LINEOUT2N Driver" },
1071*4882a593Smuzhiyun 	{ "LINEOUT2P", NULL, "LINEOUT2P Driver" },
1072*4882a593Smuzhiyun };
1073*4882a593Smuzhiyun 
1074*4882a593Smuzhiyun static const struct snd_soc_dapm_route lineout1_diff_routes[] = {
1075*4882a593Smuzhiyun 	{ "LINEOUT1 Mixer", "IN1L Switch", "IN1L PGA" },
1076*4882a593Smuzhiyun 	{ "LINEOUT1 Mixer", "IN1R Switch", "IN1R PGA" },
1077*4882a593Smuzhiyun 	{ "LINEOUT1 Mixer", "Output Switch", "Left Output PGA" },
1078*4882a593Smuzhiyun 
1079*4882a593Smuzhiyun 	{ "LINEOUT1N Driver", NULL, "LINEOUT1 Mixer" },
1080*4882a593Smuzhiyun 	{ "LINEOUT1P Driver", NULL, "LINEOUT1 Mixer" },
1081*4882a593Smuzhiyun };
1082*4882a593Smuzhiyun 
1083*4882a593Smuzhiyun static const struct snd_soc_dapm_route lineout1_se_routes[] = {
1084*4882a593Smuzhiyun 	{ "LINEOUT1N Mixer", "Left Output Switch", "Left Output PGA" },
1085*4882a593Smuzhiyun 	{ "LINEOUT1N Mixer", "Right Output Switch", "Right Output PGA" },
1086*4882a593Smuzhiyun 
1087*4882a593Smuzhiyun 	{ "LINEOUT1P Mixer", "Left Output Switch", "Left Output PGA" },
1088*4882a593Smuzhiyun 
1089*4882a593Smuzhiyun 	{ "LINEOUT1N Driver", NULL, "LINEOUT1N Mixer" },
1090*4882a593Smuzhiyun 	{ "LINEOUT1P Driver", NULL, "LINEOUT1P Mixer" },
1091*4882a593Smuzhiyun };
1092*4882a593Smuzhiyun 
1093*4882a593Smuzhiyun static const struct snd_soc_dapm_route lineout2_diff_routes[] = {
1094*4882a593Smuzhiyun 	{ "LINEOUT2 Mixer", "IN1L Switch", "IN1L PGA" },
1095*4882a593Smuzhiyun 	{ "LINEOUT2 Mixer", "IN1R Switch", "IN1R PGA" },
1096*4882a593Smuzhiyun 	{ "LINEOUT2 Mixer", "Output Switch", "Right Output PGA" },
1097*4882a593Smuzhiyun 
1098*4882a593Smuzhiyun 	{ "LINEOUT2N Driver", NULL, "LINEOUT2 Mixer" },
1099*4882a593Smuzhiyun 	{ "LINEOUT2P Driver", NULL, "LINEOUT2 Mixer" },
1100*4882a593Smuzhiyun };
1101*4882a593Smuzhiyun 
1102*4882a593Smuzhiyun static const struct snd_soc_dapm_route lineout2_se_routes[] = {
1103*4882a593Smuzhiyun 	{ "LINEOUT2N Mixer", "Left Output Switch", "Left Output PGA" },
1104*4882a593Smuzhiyun 	{ "LINEOUT2N Mixer", "Right Output Switch", "Right Output PGA" },
1105*4882a593Smuzhiyun 
1106*4882a593Smuzhiyun 	{ "LINEOUT2P Mixer", "Right Output Switch", "Right Output PGA" },
1107*4882a593Smuzhiyun 
1108*4882a593Smuzhiyun 	{ "LINEOUT2N Driver", NULL, "LINEOUT2N Mixer" },
1109*4882a593Smuzhiyun 	{ "LINEOUT2P Driver", NULL, "LINEOUT2P Mixer" },
1110*4882a593Smuzhiyun };
1111*4882a593Smuzhiyun 
wm_hubs_add_analogue_controls(struct snd_soc_component * component)1112*4882a593Smuzhiyun int wm_hubs_add_analogue_controls(struct snd_soc_component *component)
1113*4882a593Smuzhiyun {
1114*4882a593Smuzhiyun 	struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
1115*4882a593Smuzhiyun 
1116*4882a593Smuzhiyun 	/* Latch volume update bits & default ZC on */
1117*4882a593Smuzhiyun 	snd_soc_component_update_bits(component, WM8993_LEFT_LINE_INPUT_1_2_VOLUME,
1118*4882a593Smuzhiyun 			    WM8993_IN1_VU, WM8993_IN1_VU);
1119*4882a593Smuzhiyun 	snd_soc_component_update_bits(component, WM8993_RIGHT_LINE_INPUT_1_2_VOLUME,
1120*4882a593Smuzhiyun 			    WM8993_IN1_VU, WM8993_IN1_VU);
1121*4882a593Smuzhiyun 	snd_soc_component_update_bits(component, WM8993_LEFT_LINE_INPUT_3_4_VOLUME,
1122*4882a593Smuzhiyun 			    WM8993_IN2_VU, WM8993_IN2_VU);
1123*4882a593Smuzhiyun 	snd_soc_component_update_bits(component, WM8993_RIGHT_LINE_INPUT_3_4_VOLUME,
1124*4882a593Smuzhiyun 			    WM8993_IN2_VU, WM8993_IN2_VU);
1125*4882a593Smuzhiyun 
1126*4882a593Smuzhiyun 	snd_soc_component_update_bits(component, WM8993_SPEAKER_VOLUME_LEFT,
1127*4882a593Smuzhiyun 			    WM8993_SPKOUT_VU, WM8993_SPKOUT_VU);
1128*4882a593Smuzhiyun 	snd_soc_component_update_bits(component, WM8993_SPEAKER_VOLUME_RIGHT,
1129*4882a593Smuzhiyun 			    WM8993_SPKOUT_VU, WM8993_SPKOUT_VU);
1130*4882a593Smuzhiyun 
1131*4882a593Smuzhiyun 	snd_soc_component_update_bits(component, WM8993_LEFT_OUTPUT_VOLUME,
1132*4882a593Smuzhiyun 			    WM8993_HPOUT1_VU | WM8993_HPOUT1L_ZC,
1133*4882a593Smuzhiyun 			    WM8993_HPOUT1_VU | WM8993_HPOUT1L_ZC);
1134*4882a593Smuzhiyun 	snd_soc_component_update_bits(component, WM8993_RIGHT_OUTPUT_VOLUME,
1135*4882a593Smuzhiyun 			    WM8993_HPOUT1_VU | WM8993_HPOUT1R_ZC,
1136*4882a593Smuzhiyun 			    WM8993_HPOUT1_VU | WM8993_HPOUT1R_ZC);
1137*4882a593Smuzhiyun 
1138*4882a593Smuzhiyun 	snd_soc_component_update_bits(component, WM8993_LEFT_OPGA_VOLUME,
1139*4882a593Smuzhiyun 			    WM8993_MIXOUTL_ZC | WM8993_MIXOUT_VU,
1140*4882a593Smuzhiyun 			    WM8993_MIXOUTL_ZC | WM8993_MIXOUT_VU);
1141*4882a593Smuzhiyun 	snd_soc_component_update_bits(component, WM8993_RIGHT_OPGA_VOLUME,
1142*4882a593Smuzhiyun 			    WM8993_MIXOUTR_ZC | WM8993_MIXOUT_VU,
1143*4882a593Smuzhiyun 			    WM8993_MIXOUTR_ZC | WM8993_MIXOUT_VU);
1144*4882a593Smuzhiyun 
1145*4882a593Smuzhiyun 	snd_soc_add_component_controls(component, analogue_snd_controls,
1146*4882a593Smuzhiyun 			     ARRAY_SIZE(analogue_snd_controls));
1147*4882a593Smuzhiyun 
1148*4882a593Smuzhiyun 	snd_soc_dapm_new_controls(dapm, analogue_dapm_widgets,
1149*4882a593Smuzhiyun 				  ARRAY_SIZE(analogue_dapm_widgets));
1150*4882a593Smuzhiyun 	return 0;
1151*4882a593Smuzhiyun }
1152*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(wm_hubs_add_analogue_controls);
1153*4882a593Smuzhiyun 
wm_hubs_add_analogue_routes(struct snd_soc_component * component,int lineout1_diff,int lineout2_diff)1154*4882a593Smuzhiyun int wm_hubs_add_analogue_routes(struct snd_soc_component *component,
1155*4882a593Smuzhiyun 				int lineout1_diff, int lineout2_diff)
1156*4882a593Smuzhiyun {
1157*4882a593Smuzhiyun 	struct wm_hubs_data *hubs = snd_soc_component_get_drvdata(component);
1158*4882a593Smuzhiyun 	struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
1159*4882a593Smuzhiyun 
1160*4882a593Smuzhiyun 	hubs->component = component;
1161*4882a593Smuzhiyun 
1162*4882a593Smuzhiyun 	INIT_LIST_HEAD(&hubs->dcs_cache);
1163*4882a593Smuzhiyun 	init_completion(&hubs->dcs_done);
1164*4882a593Smuzhiyun 
1165*4882a593Smuzhiyun 	snd_soc_dapm_add_routes(dapm, analogue_routes,
1166*4882a593Smuzhiyun 				ARRAY_SIZE(analogue_routes));
1167*4882a593Smuzhiyun 
1168*4882a593Smuzhiyun 	if (lineout1_diff)
1169*4882a593Smuzhiyun 		snd_soc_dapm_add_routes(dapm,
1170*4882a593Smuzhiyun 					lineout1_diff_routes,
1171*4882a593Smuzhiyun 					ARRAY_SIZE(lineout1_diff_routes));
1172*4882a593Smuzhiyun 	else
1173*4882a593Smuzhiyun 		snd_soc_dapm_add_routes(dapm,
1174*4882a593Smuzhiyun 					lineout1_se_routes,
1175*4882a593Smuzhiyun 					ARRAY_SIZE(lineout1_se_routes));
1176*4882a593Smuzhiyun 
1177*4882a593Smuzhiyun 	if (lineout2_diff)
1178*4882a593Smuzhiyun 		snd_soc_dapm_add_routes(dapm,
1179*4882a593Smuzhiyun 					lineout2_diff_routes,
1180*4882a593Smuzhiyun 					ARRAY_SIZE(lineout2_diff_routes));
1181*4882a593Smuzhiyun 	else
1182*4882a593Smuzhiyun 		snd_soc_dapm_add_routes(dapm,
1183*4882a593Smuzhiyun 					lineout2_se_routes,
1184*4882a593Smuzhiyun 					ARRAY_SIZE(lineout2_se_routes));
1185*4882a593Smuzhiyun 
1186*4882a593Smuzhiyun 	return 0;
1187*4882a593Smuzhiyun }
1188*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(wm_hubs_add_analogue_routes);
1189*4882a593Smuzhiyun 
wm_hubs_handle_analogue_pdata(struct snd_soc_component * component,int lineout1_diff,int lineout2_diff,int lineout1fb,int lineout2fb,int jd_scthr,int jd_thr,int micbias1_delay,int micbias2_delay,int micbias1_lvl,int micbias2_lvl)1190*4882a593Smuzhiyun int wm_hubs_handle_analogue_pdata(struct snd_soc_component *component,
1191*4882a593Smuzhiyun 				  int lineout1_diff, int lineout2_diff,
1192*4882a593Smuzhiyun 				  int lineout1fb, int lineout2fb,
1193*4882a593Smuzhiyun 				  int jd_scthr, int jd_thr,
1194*4882a593Smuzhiyun 				  int micbias1_delay, int micbias2_delay,
1195*4882a593Smuzhiyun 				  int micbias1_lvl, int micbias2_lvl)
1196*4882a593Smuzhiyun {
1197*4882a593Smuzhiyun 	struct wm_hubs_data *hubs = snd_soc_component_get_drvdata(component);
1198*4882a593Smuzhiyun 
1199*4882a593Smuzhiyun 	hubs->lineout1_se = !lineout1_diff;
1200*4882a593Smuzhiyun 	hubs->lineout2_se = !lineout2_diff;
1201*4882a593Smuzhiyun 	hubs->micb1_delay = micbias1_delay;
1202*4882a593Smuzhiyun 	hubs->micb2_delay = micbias2_delay;
1203*4882a593Smuzhiyun 
1204*4882a593Smuzhiyun 	if (!lineout1_diff)
1205*4882a593Smuzhiyun 		snd_soc_component_update_bits(component, WM8993_LINE_MIXER1,
1206*4882a593Smuzhiyun 				    WM8993_LINEOUT1_MODE,
1207*4882a593Smuzhiyun 				    WM8993_LINEOUT1_MODE);
1208*4882a593Smuzhiyun 	if (!lineout2_diff)
1209*4882a593Smuzhiyun 		snd_soc_component_update_bits(component, WM8993_LINE_MIXER2,
1210*4882a593Smuzhiyun 				    WM8993_LINEOUT2_MODE,
1211*4882a593Smuzhiyun 				    WM8993_LINEOUT2_MODE);
1212*4882a593Smuzhiyun 
1213*4882a593Smuzhiyun 	if (!lineout1_diff && !lineout2_diff)
1214*4882a593Smuzhiyun 		snd_soc_component_update_bits(component, WM8993_ANTIPOP1,
1215*4882a593Smuzhiyun 				    WM8993_LINEOUT_VMID_BUF_ENA,
1216*4882a593Smuzhiyun 				    WM8993_LINEOUT_VMID_BUF_ENA);
1217*4882a593Smuzhiyun 
1218*4882a593Smuzhiyun 	if (lineout1fb)
1219*4882a593Smuzhiyun 		snd_soc_component_update_bits(component, WM8993_ADDITIONAL_CONTROL,
1220*4882a593Smuzhiyun 				    WM8993_LINEOUT1_FB, WM8993_LINEOUT1_FB);
1221*4882a593Smuzhiyun 
1222*4882a593Smuzhiyun 	if (lineout2fb)
1223*4882a593Smuzhiyun 		snd_soc_component_update_bits(component, WM8993_ADDITIONAL_CONTROL,
1224*4882a593Smuzhiyun 				    WM8993_LINEOUT2_FB, WM8993_LINEOUT2_FB);
1225*4882a593Smuzhiyun 
1226*4882a593Smuzhiyun 	if (!hubs->micd_scthr)
1227*4882a593Smuzhiyun 		return 0;
1228*4882a593Smuzhiyun 
1229*4882a593Smuzhiyun 	snd_soc_component_update_bits(component, WM8993_MICBIAS,
1230*4882a593Smuzhiyun 			    WM8993_JD_SCTHR_MASK | WM8993_JD_THR_MASK |
1231*4882a593Smuzhiyun 			    WM8993_MICB1_LVL | WM8993_MICB2_LVL,
1232*4882a593Smuzhiyun 			    jd_scthr << WM8993_JD_SCTHR_SHIFT |
1233*4882a593Smuzhiyun 			    jd_thr << WM8993_JD_THR_SHIFT |
1234*4882a593Smuzhiyun 			    micbias1_lvl |
1235*4882a593Smuzhiyun 			    micbias2_lvl << WM8993_MICB2_LVL_SHIFT);
1236*4882a593Smuzhiyun 
1237*4882a593Smuzhiyun 	return 0;
1238*4882a593Smuzhiyun }
1239*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(wm_hubs_handle_analogue_pdata);
1240*4882a593Smuzhiyun 
wm_hubs_vmid_ena(struct snd_soc_component * component)1241*4882a593Smuzhiyun void wm_hubs_vmid_ena(struct snd_soc_component *component)
1242*4882a593Smuzhiyun {
1243*4882a593Smuzhiyun 	struct wm_hubs_data *hubs = snd_soc_component_get_drvdata(component);
1244*4882a593Smuzhiyun 	int val = 0;
1245*4882a593Smuzhiyun 
1246*4882a593Smuzhiyun 	if (hubs->lineout1_se)
1247*4882a593Smuzhiyun 		val |= WM8993_LINEOUT1N_ENA | WM8993_LINEOUT1P_ENA;
1248*4882a593Smuzhiyun 
1249*4882a593Smuzhiyun 	if (hubs->lineout2_se)
1250*4882a593Smuzhiyun 		val |= WM8993_LINEOUT2N_ENA | WM8993_LINEOUT2P_ENA;
1251*4882a593Smuzhiyun 
1252*4882a593Smuzhiyun 	/* Enable the line outputs while we power up */
1253*4882a593Smuzhiyun 	snd_soc_component_update_bits(component, WM8993_POWER_MANAGEMENT_3, val, val);
1254*4882a593Smuzhiyun }
1255*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(wm_hubs_vmid_ena);
1256*4882a593Smuzhiyun 
wm_hubs_set_bias_level(struct snd_soc_component * component,enum snd_soc_bias_level level)1257*4882a593Smuzhiyun void wm_hubs_set_bias_level(struct snd_soc_component *component,
1258*4882a593Smuzhiyun 			    enum snd_soc_bias_level level)
1259*4882a593Smuzhiyun {
1260*4882a593Smuzhiyun 	struct wm_hubs_data *hubs = snd_soc_component_get_drvdata(component);
1261*4882a593Smuzhiyun 	int mask, val;
1262*4882a593Smuzhiyun 
1263*4882a593Smuzhiyun 	switch (level) {
1264*4882a593Smuzhiyun 	case SND_SOC_BIAS_STANDBY:
1265*4882a593Smuzhiyun 		/* Clamp the inputs to VMID while we ramp to charge caps */
1266*4882a593Smuzhiyun 		snd_soc_component_update_bits(component, WM8993_INPUTS_CLAMP_REG,
1267*4882a593Smuzhiyun 				    WM8993_INPUTS_CLAMP, WM8993_INPUTS_CLAMP);
1268*4882a593Smuzhiyun 		break;
1269*4882a593Smuzhiyun 
1270*4882a593Smuzhiyun 	case SND_SOC_BIAS_ON:
1271*4882a593Smuzhiyun 		/* Turn off any unneeded single ended outputs */
1272*4882a593Smuzhiyun 		val = 0;
1273*4882a593Smuzhiyun 		mask = 0;
1274*4882a593Smuzhiyun 
1275*4882a593Smuzhiyun 		if (hubs->lineout1_se)
1276*4882a593Smuzhiyun 			mask |= WM8993_LINEOUT1N_ENA | WM8993_LINEOUT1P_ENA;
1277*4882a593Smuzhiyun 
1278*4882a593Smuzhiyun 		if (hubs->lineout2_se)
1279*4882a593Smuzhiyun 			mask |= WM8993_LINEOUT2N_ENA | WM8993_LINEOUT2P_ENA;
1280*4882a593Smuzhiyun 
1281*4882a593Smuzhiyun 		if (hubs->lineout1_se && hubs->lineout1n_ena)
1282*4882a593Smuzhiyun 			val |= WM8993_LINEOUT1N_ENA;
1283*4882a593Smuzhiyun 
1284*4882a593Smuzhiyun 		if (hubs->lineout1_se && hubs->lineout1p_ena)
1285*4882a593Smuzhiyun 			val |= WM8993_LINEOUT1P_ENA;
1286*4882a593Smuzhiyun 
1287*4882a593Smuzhiyun 		if (hubs->lineout2_se && hubs->lineout2n_ena)
1288*4882a593Smuzhiyun 			val |= WM8993_LINEOUT2N_ENA;
1289*4882a593Smuzhiyun 
1290*4882a593Smuzhiyun 		if (hubs->lineout2_se && hubs->lineout2p_ena)
1291*4882a593Smuzhiyun 			val |= WM8993_LINEOUT2P_ENA;
1292*4882a593Smuzhiyun 
1293*4882a593Smuzhiyun 		snd_soc_component_update_bits(component, WM8993_POWER_MANAGEMENT_3,
1294*4882a593Smuzhiyun 				    mask, val);
1295*4882a593Smuzhiyun 
1296*4882a593Smuzhiyun 		/* Remove the input clamps */
1297*4882a593Smuzhiyun 		snd_soc_component_update_bits(component, WM8993_INPUTS_CLAMP_REG,
1298*4882a593Smuzhiyun 				    WM8993_INPUTS_CLAMP, 0);
1299*4882a593Smuzhiyun 		break;
1300*4882a593Smuzhiyun 
1301*4882a593Smuzhiyun 	default:
1302*4882a593Smuzhiyun 		break;
1303*4882a593Smuzhiyun 	}
1304*4882a593Smuzhiyun }
1305*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(wm_hubs_set_bias_level);
1306*4882a593Smuzhiyun 
1307*4882a593Smuzhiyun MODULE_DESCRIPTION("Shared support for Wolfson hubs products");
1308*4882a593Smuzhiyun MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
1309*4882a593Smuzhiyun MODULE_LICENSE("GPL");
1310