xref: /OK3568_Linux_fs/kernel/sound/soc/codecs/wm9713.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * wm9713.h  --  WM9713 Soc Audio driver
4*4882a593Smuzhiyun  */
5*4882a593Smuzhiyun 
6*4882a593Smuzhiyun #ifndef _WM9713_H
7*4882a593Smuzhiyun #define _WM9713_H
8*4882a593Smuzhiyun 
9*4882a593Smuzhiyun /* clock inputs */
10*4882a593Smuzhiyun #define WM9713_CLKA_PIN			0
11*4882a593Smuzhiyun #define WM9713_CLKB_PIN			1
12*4882a593Smuzhiyun 
13*4882a593Smuzhiyun /* clock divider ID's */
14*4882a593Smuzhiyun #define WM9713_PCMCLK_DIV		0
15*4882a593Smuzhiyun #define WM9713_CLKA_MULT		1
16*4882a593Smuzhiyun #define WM9713_CLKB_MULT		2
17*4882a593Smuzhiyun #define WM9713_HIFI_DIV			3
18*4882a593Smuzhiyun #define WM9713_PCMBCLK_DIV		4
19*4882a593Smuzhiyun #define WM9713_PCMCLK_PLL_DIV           5
20*4882a593Smuzhiyun #define WM9713_HIFI_PLL_DIV             6
21*4882a593Smuzhiyun 
22*4882a593Smuzhiyun /* Calculate the appropriate bit mask for the external PCM clock divider */
23*4882a593Smuzhiyun #define WM9713_PCMDIV(x)	((x - 1) << 8)
24*4882a593Smuzhiyun 
25*4882a593Smuzhiyun /* Calculate the appropriate bit mask for the external HiFi clock divider */
26*4882a593Smuzhiyun #define WM9713_HIFIDIV(x)	((x - 1) << 12)
27*4882a593Smuzhiyun 
28*4882a593Smuzhiyun /* MCLK clock mulitipliers */
29*4882a593Smuzhiyun #define WM9713_CLKA_X1		(0 << 1)
30*4882a593Smuzhiyun #define WM9713_CLKA_X2		(1 << 1)
31*4882a593Smuzhiyun #define WM9713_CLKB_X1		(0 << 2)
32*4882a593Smuzhiyun #define WM9713_CLKB_X2		(1 << 2)
33*4882a593Smuzhiyun 
34*4882a593Smuzhiyun /* MCLK clock MUX */
35*4882a593Smuzhiyun #define WM9713_CLK_MUX_A		(0 << 0)
36*4882a593Smuzhiyun #define WM9713_CLK_MUX_B		(1 << 0)
37*4882a593Smuzhiyun 
38*4882a593Smuzhiyun /* Voice DAI BCLK divider */
39*4882a593Smuzhiyun #define WM9713_PCMBCLK_DIV_1	(0 << 9)
40*4882a593Smuzhiyun #define WM9713_PCMBCLK_DIV_2	(1 << 9)
41*4882a593Smuzhiyun #define WM9713_PCMBCLK_DIV_4	(2 << 9)
42*4882a593Smuzhiyun #define WM9713_PCMBCLK_DIV_8	(3 << 9)
43*4882a593Smuzhiyun #define WM9713_PCMBCLK_DIV_16	(4 << 9)
44*4882a593Smuzhiyun 
45*4882a593Smuzhiyun #endif
46