1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * ALSA SoC WM9090 driver 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright 2009 Wolfson Microelectronics 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __WM9090_H 11*4882a593Smuzhiyun #define __WM9090_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* 14*4882a593Smuzhiyun * Register values. 15*4882a593Smuzhiyun */ 16*4882a593Smuzhiyun #define WM9090_SOFTWARE_RESET 0x00 17*4882a593Smuzhiyun #define WM9090_POWER_MANAGEMENT_1 0x01 18*4882a593Smuzhiyun #define WM9090_POWER_MANAGEMENT_2 0x02 19*4882a593Smuzhiyun #define WM9090_POWER_MANAGEMENT_3 0x03 20*4882a593Smuzhiyun #define WM9090_CLOCKING_1 0x06 21*4882a593Smuzhiyun #define WM9090_IN1_LINE_CONTROL 0x16 22*4882a593Smuzhiyun #define WM9090_IN2_LINE_CONTROL 0x17 23*4882a593Smuzhiyun #define WM9090_IN1_LINE_INPUT_A_VOLUME 0x18 24*4882a593Smuzhiyun #define WM9090_IN1_LINE_INPUT_B_VOLUME 0x19 25*4882a593Smuzhiyun #define WM9090_IN2_LINE_INPUT_A_VOLUME 0x1A 26*4882a593Smuzhiyun #define WM9090_IN2_LINE_INPUT_B_VOLUME 0x1B 27*4882a593Smuzhiyun #define WM9090_LEFT_OUTPUT_VOLUME 0x1C 28*4882a593Smuzhiyun #define WM9090_RIGHT_OUTPUT_VOLUME 0x1D 29*4882a593Smuzhiyun #define WM9090_SPKMIXL_ATTENUATION 0x22 30*4882a593Smuzhiyun #define WM9090_SPKOUT_MIXERS 0x24 31*4882a593Smuzhiyun #define WM9090_CLASSD3 0x25 32*4882a593Smuzhiyun #define WM9090_SPEAKER_VOLUME_LEFT 0x26 33*4882a593Smuzhiyun #define WM9090_OUTPUT_MIXER1 0x2D 34*4882a593Smuzhiyun #define WM9090_OUTPUT_MIXER2 0x2E 35*4882a593Smuzhiyun #define WM9090_OUTPUT_MIXER3 0x2F 36*4882a593Smuzhiyun #define WM9090_OUTPUT_MIXER4 0x30 37*4882a593Smuzhiyun #define WM9090_SPEAKER_MIXER 0x36 38*4882a593Smuzhiyun #define WM9090_ANTIPOP2 0x39 39*4882a593Smuzhiyun #define WM9090_WRITE_SEQUENCER_0 0x46 40*4882a593Smuzhiyun #define WM9090_WRITE_SEQUENCER_1 0x47 41*4882a593Smuzhiyun #define WM9090_WRITE_SEQUENCER_2 0x48 42*4882a593Smuzhiyun #define WM9090_WRITE_SEQUENCER_3 0x49 43*4882a593Smuzhiyun #define WM9090_WRITE_SEQUENCER_4 0x4A 44*4882a593Smuzhiyun #define WM9090_WRITE_SEQUENCER_5 0x4B 45*4882a593Smuzhiyun #define WM9090_CHARGE_PUMP_1 0x4C 46*4882a593Smuzhiyun #define WM9090_DC_SERVO_0 0x54 47*4882a593Smuzhiyun #define WM9090_DC_SERVO_1 0x55 48*4882a593Smuzhiyun #define WM9090_DC_SERVO_3 0x57 49*4882a593Smuzhiyun #define WM9090_DC_SERVO_READBACK_0 0x58 50*4882a593Smuzhiyun #define WM9090_DC_SERVO_READBACK_1 0x59 51*4882a593Smuzhiyun #define WM9090_DC_SERVO_READBACK_2 0x5A 52*4882a593Smuzhiyun #define WM9090_ANALOGUE_HP_0 0x60 53*4882a593Smuzhiyun #define WM9090_AGC_CONTROL_0 0x62 54*4882a593Smuzhiyun #define WM9090_AGC_CONTROL_1 0x63 55*4882a593Smuzhiyun #define WM9090_AGC_CONTROL_2 0x64 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun #define WM9090_REGISTER_COUNT 40 58*4882a593Smuzhiyun #define WM9090_MAX_REGISTER 0x64 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun /* 61*4882a593Smuzhiyun * Field Definitions. 62*4882a593Smuzhiyun */ 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun /* 65*4882a593Smuzhiyun * R0 (0x00) - Software Reset 66*4882a593Smuzhiyun */ 67*4882a593Smuzhiyun #define WM9090_SW_RESET_MASK 0xFFFF /* SW_RESET - [15:0] */ 68*4882a593Smuzhiyun #define WM9090_SW_RESET_SHIFT 0 /* SW_RESET - [15:0] */ 69*4882a593Smuzhiyun #define WM9090_SW_RESET_WIDTH 16 /* SW_RESET - [15:0] */ 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun /* 72*4882a593Smuzhiyun * R1 (0x01) - Power Management (1) 73*4882a593Smuzhiyun */ 74*4882a593Smuzhiyun #define WM9090_SPKOUTL_ENA 0x1000 /* SPKOUTL_ENA */ 75*4882a593Smuzhiyun #define WM9090_SPKOUTL_ENA_MASK 0x1000 /* SPKOUTL_ENA */ 76*4882a593Smuzhiyun #define WM9090_SPKOUTL_ENA_SHIFT 12 /* SPKOUTL_ENA */ 77*4882a593Smuzhiyun #define WM9090_SPKOUTL_ENA_WIDTH 1 /* SPKOUTL_ENA */ 78*4882a593Smuzhiyun #define WM9090_HPOUT1L_ENA 0x0200 /* HPOUT1L_ENA */ 79*4882a593Smuzhiyun #define WM9090_HPOUT1L_ENA_MASK 0x0200 /* HPOUT1L_ENA */ 80*4882a593Smuzhiyun #define WM9090_HPOUT1L_ENA_SHIFT 9 /* HPOUT1L_ENA */ 81*4882a593Smuzhiyun #define WM9090_HPOUT1L_ENA_WIDTH 1 /* HPOUT1L_ENA */ 82*4882a593Smuzhiyun #define WM9090_HPOUT1R_ENA 0x0100 /* HPOUT1R_ENA */ 83*4882a593Smuzhiyun #define WM9090_HPOUT1R_ENA_MASK 0x0100 /* HPOUT1R_ENA */ 84*4882a593Smuzhiyun #define WM9090_HPOUT1R_ENA_SHIFT 8 /* HPOUT1R_ENA */ 85*4882a593Smuzhiyun #define WM9090_HPOUT1R_ENA_WIDTH 1 /* HPOUT1R_ENA */ 86*4882a593Smuzhiyun #define WM9090_OSC_ENA 0x0008 /* OSC_ENA */ 87*4882a593Smuzhiyun #define WM9090_OSC_ENA_MASK 0x0008 /* OSC_ENA */ 88*4882a593Smuzhiyun #define WM9090_OSC_ENA_SHIFT 3 /* OSC_ENA */ 89*4882a593Smuzhiyun #define WM9090_OSC_ENA_WIDTH 1 /* OSC_ENA */ 90*4882a593Smuzhiyun #define WM9090_VMID_RES_MASK 0x0006 /* VMID_RES - [2:1] */ 91*4882a593Smuzhiyun #define WM9090_VMID_RES_SHIFT 1 /* VMID_RES - [2:1] */ 92*4882a593Smuzhiyun #define WM9090_VMID_RES_WIDTH 2 /* VMID_RES - [2:1] */ 93*4882a593Smuzhiyun #define WM9090_BIAS_ENA 0x0001 /* BIAS_ENA */ 94*4882a593Smuzhiyun #define WM9090_BIAS_ENA_MASK 0x0001 /* BIAS_ENA */ 95*4882a593Smuzhiyun #define WM9090_BIAS_ENA_SHIFT 0 /* BIAS_ENA */ 96*4882a593Smuzhiyun #define WM9090_BIAS_ENA_WIDTH 1 /* BIAS_ENA */ 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun /* 99*4882a593Smuzhiyun * R2 (0x02) - Power Management (2) 100*4882a593Smuzhiyun */ 101*4882a593Smuzhiyun #define WM9090_TSHUT 0x8000 /* TSHUT */ 102*4882a593Smuzhiyun #define WM9090_TSHUT_MASK 0x8000 /* TSHUT */ 103*4882a593Smuzhiyun #define WM9090_TSHUT_SHIFT 15 /* TSHUT */ 104*4882a593Smuzhiyun #define WM9090_TSHUT_WIDTH 1 /* TSHUT */ 105*4882a593Smuzhiyun #define WM9090_TSHUT_ENA 0x4000 /* TSHUT_ENA */ 106*4882a593Smuzhiyun #define WM9090_TSHUT_ENA_MASK 0x4000 /* TSHUT_ENA */ 107*4882a593Smuzhiyun #define WM9090_TSHUT_ENA_SHIFT 14 /* TSHUT_ENA */ 108*4882a593Smuzhiyun #define WM9090_TSHUT_ENA_WIDTH 1 /* TSHUT_ENA */ 109*4882a593Smuzhiyun #define WM9090_TSHUT_OPDIS 0x2000 /* TSHUT_OPDIS */ 110*4882a593Smuzhiyun #define WM9090_TSHUT_OPDIS_MASK 0x2000 /* TSHUT_OPDIS */ 111*4882a593Smuzhiyun #define WM9090_TSHUT_OPDIS_SHIFT 13 /* TSHUT_OPDIS */ 112*4882a593Smuzhiyun #define WM9090_TSHUT_OPDIS_WIDTH 1 /* TSHUT_OPDIS */ 113*4882a593Smuzhiyun #define WM9090_IN1A_ENA 0x0080 /* IN1A_ENA */ 114*4882a593Smuzhiyun #define WM9090_IN1A_ENA_MASK 0x0080 /* IN1A_ENA */ 115*4882a593Smuzhiyun #define WM9090_IN1A_ENA_SHIFT 7 /* IN1A_ENA */ 116*4882a593Smuzhiyun #define WM9090_IN1A_ENA_WIDTH 1 /* IN1A_ENA */ 117*4882a593Smuzhiyun #define WM9090_IN1B_ENA 0x0040 /* IN1B_ENA */ 118*4882a593Smuzhiyun #define WM9090_IN1B_ENA_MASK 0x0040 /* IN1B_ENA */ 119*4882a593Smuzhiyun #define WM9090_IN1B_ENA_SHIFT 6 /* IN1B_ENA */ 120*4882a593Smuzhiyun #define WM9090_IN1B_ENA_WIDTH 1 /* IN1B_ENA */ 121*4882a593Smuzhiyun #define WM9090_IN2A_ENA 0x0020 /* IN2A_ENA */ 122*4882a593Smuzhiyun #define WM9090_IN2A_ENA_MASK 0x0020 /* IN2A_ENA */ 123*4882a593Smuzhiyun #define WM9090_IN2A_ENA_SHIFT 5 /* IN2A_ENA */ 124*4882a593Smuzhiyun #define WM9090_IN2A_ENA_WIDTH 1 /* IN2A_ENA */ 125*4882a593Smuzhiyun #define WM9090_IN2B_ENA 0x0010 /* IN2B_ENA */ 126*4882a593Smuzhiyun #define WM9090_IN2B_ENA_MASK 0x0010 /* IN2B_ENA */ 127*4882a593Smuzhiyun #define WM9090_IN2B_ENA_SHIFT 4 /* IN2B_ENA */ 128*4882a593Smuzhiyun #define WM9090_IN2B_ENA_WIDTH 1 /* IN2B_ENA */ 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun /* 131*4882a593Smuzhiyun * R3 (0x03) - Power Management (3) 132*4882a593Smuzhiyun */ 133*4882a593Smuzhiyun #define WM9090_AGC_ENA 0x4000 /* AGC_ENA */ 134*4882a593Smuzhiyun #define WM9090_AGC_ENA_MASK 0x4000 /* AGC_ENA */ 135*4882a593Smuzhiyun #define WM9090_AGC_ENA_SHIFT 14 /* AGC_ENA */ 136*4882a593Smuzhiyun #define WM9090_AGC_ENA_WIDTH 1 /* AGC_ENA */ 137*4882a593Smuzhiyun #define WM9090_SPKLVOL_ENA 0x0100 /* SPKLVOL_ENA */ 138*4882a593Smuzhiyun #define WM9090_SPKLVOL_ENA_MASK 0x0100 /* SPKLVOL_ENA */ 139*4882a593Smuzhiyun #define WM9090_SPKLVOL_ENA_SHIFT 8 /* SPKLVOL_ENA */ 140*4882a593Smuzhiyun #define WM9090_SPKLVOL_ENA_WIDTH 1 /* SPKLVOL_ENA */ 141*4882a593Smuzhiyun #define WM9090_MIXOUTL_ENA 0x0020 /* MIXOUTL_ENA */ 142*4882a593Smuzhiyun #define WM9090_MIXOUTL_ENA_MASK 0x0020 /* MIXOUTL_ENA */ 143*4882a593Smuzhiyun #define WM9090_MIXOUTL_ENA_SHIFT 5 /* MIXOUTL_ENA */ 144*4882a593Smuzhiyun #define WM9090_MIXOUTL_ENA_WIDTH 1 /* MIXOUTL_ENA */ 145*4882a593Smuzhiyun #define WM9090_MIXOUTR_ENA 0x0010 /* MIXOUTR_ENA */ 146*4882a593Smuzhiyun #define WM9090_MIXOUTR_ENA_MASK 0x0010 /* MIXOUTR_ENA */ 147*4882a593Smuzhiyun #define WM9090_MIXOUTR_ENA_SHIFT 4 /* MIXOUTR_ENA */ 148*4882a593Smuzhiyun #define WM9090_MIXOUTR_ENA_WIDTH 1 /* MIXOUTR_ENA */ 149*4882a593Smuzhiyun #define WM9090_SPKMIX_ENA 0x0008 /* SPKMIX_ENA */ 150*4882a593Smuzhiyun #define WM9090_SPKMIX_ENA_MASK 0x0008 /* SPKMIX_ENA */ 151*4882a593Smuzhiyun #define WM9090_SPKMIX_ENA_SHIFT 3 /* SPKMIX_ENA */ 152*4882a593Smuzhiyun #define WM9090_SPKMIX_ENA_WIDTH 1 /* SPKMIX_ENA */ 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun /* 155*4882a593Smuzhiyun * R6 (0x06) - Clocking 1 156*4882a593Smuzhiyun */ 157*4882a593Smuzhiyun #define WM9090_TOCLK_RATE 0x8000 /* TOCLK_RATE */ 158*4882a593Smuzhiyun #define WM9090_TOCLK_RATE_MASK 0x8000 /* TOCLK_RATE */ 159*4882a593Smuzhiyun #define WM9090_TOCLK_RATE_SHIFT 15 /* TOCLK_RATE */ 160*4882a593Smuzhiyun #define WM9090_TOCLK_RATE_WIDTH 1 /* TOCLK_RATE */ 161*4882a593Smuzhiyun #define WM9090_TOCLK_ENA 0x4000 /* TOCLK_ENA */ 162*4882a593Smuzhiyun #define WM9090_TOCLK_ENA_MASK 0x4000 /* TOCLK_ENA */ 163*4882a593Smuzhiyun #define WM9090_TOCLK_ENA_SHIFT 14 /* TOCLK_ENA */ 164*4882a593Smuzhiyun #define WM9090_TOCLK_ENA_WIDTH 1 /* TOCLK_ENA */ 165*4882a593Smuzhiyun 166*4882a593Smuzhiyun /* 167*4882a593Smuzhiyun * R22 (0x16) - IN1 Line Control 168*4882a593Smuzhiyun */ 169*4882a593Smuzhiyun #define WM9090_IN1_DIFF 0x0002 /* IN1_DIFF */ 170*4882a593Smuzhiyun #define WM9090_IN1_DIFF_MASK 0x0002 /* IN1_DIFF */ 171*4882a593Smuzhiyun #define WM9090_IN1_DIFF_SHIFT 1 /* IN1_DIFF */ 172*4882a593Smuzhiyun #define WM9090_IN1_DIFF_WIDTH 1 /* IN1_DIFF */ 173*4882a593Smuzhiyun #define WM9090_IN1_CLAMP 0x0001 /* IN1_CLAMP */ 174*4882a593Smuzhiyun #define WM9090_IN1_CLAMP_MASK 0x0001 /* IN1_CLAMP */ 175*4882a593Smuzhiyun #define WM9090_IN1_CLAMP_SHIFT 0 /* IN1_CLAMP */ 176*4882a593Smuzhiyun #define WM9090_IN1_CLAMP_WIDTH 1 /* IN1_CLAMP */ 177*4882a593Smuzhiyun 178*4882a593Smuzhiyun /* 179*4882a593Smuzhiyun * R23 (0x17) - IN2 Line Control 180*4882a593Smuzhiyun */ 181*4882a593Smuzhiyun #define WM9090_IN2_DIFF 0x0002 /* IN2_DIFF */ 182*4882a593Smuzhiyun #define WM9090_IN2_DIFF_MASK 0x0002 /* IN2_DIFF */ 183*4882a593Smuzhiyun #define WM9090_IN2_DIFF_SHIFT 1 /* IN2_DIFF */ 184*4882a593Smuzhiyun #define WM9090_IN2_DIFF_WIDTH 1 /* IN2_DIFF */ 185*4882a593Smuzhiyun #define WM9090_IN2_CLAMP 0x0001 /* IN2_CLAMP */ 186*4882a593Smuzhiyun #define WM9090_IN2_CLAMP_MASK 0x0001 /* IN2_CLAMP */ 187*4882a593Smuzhiyun #define WM9090_IN2_CLAMP_SHIFT 0 /* IN2_CLAMP */ 188*4882a593Smuzhiyun #define WM9090_IN2_CLAMP_WIDTH 1 /* IN2_CLAMP */ 189*4882a593Smuzhiyun 190*4882a593Smuzhiyun /* 191*4882a593Smuzhiyun * R24 (0x18) - IN1 Line Input A Volume 192*4882a593Smuzhiyun */ 193*4882a593Smuzhiyun #define WM9090_IN1_VU 0x0100 /* IN1_VU */ 194*4882a593Smuzhiyun #define WM9090_IN1_VU_MASK 0x0100 /* IN1_VU */ 195*4882a593Smuzhiyun #define WM9090_IN1_VU_SHIFT 8 /* IN1_VU */ 196*4882a593Smuzhiyun #define WM9090_IN1_VU_WIDTH 1 /* IN1_VU */ 197*4882a593Smuzhiyun #define WM9090_IN1A_MUTE 0x0080 /* IN1A_MUTE */ 198*4882a593Smuzhiyun #define WM9090_IN1A_MUTE_MASK 0x0080 /* IN1A_MUTE */ 199*4882a593Smuzhiyun #define WM9090_IN1A_MUTE_SHIFT 7 /* IN1A_MUTE */ 200*4882a593Smuzhiyun #define WM9090_IN1A_MUTE_WIDTH 1 /* IN1A_MUTE */ 201*4882a593Smuzhiyun #define WM9090_IN1A_ZC 0x0040 /* IN1A_ZC */ 202*4882a593Smuzhiyun #define WM9090_IN1A_ZC_MASK 0x0040 /* IN1A_ZC */ 203*4882a593Smuzhiyun #define WM9090_IN1A_ZC_SHIFT 6 /* IN1A_ZC */ 204*4882a593Smuzhiyun #define WM9090_IN1A_ZC_WIDTH 1 /* IN1A_ZC */ 205*4882a593Smuzhiyun #define WM9090_IN1A_VOL_MASK 0x0007 /* IN1A_VOL - [2:0] */ 206*4882a593Smuzhiyun #define WM9090_IN1A_VOL_SHIFT 0 /* IN1A_VOL - [2:0] */ 207*4882a593Smuzhiyun #define WM9090_IN1A_VOL_WIDTH 3 /* IN1A_VOL - [2:0] */ 208*4882a593Smuzhiyun 209*4882a593Smuzhiyun /* 210*4882a593Smuzhiyun * R25 (0x19) - IN1 Line Input B Volume 211*4882a593Smuzhiyun */ 212*4882a593Smuzhiyun #define WM9090_IN1_VU 0x0100 /* IN1_VU */ 213*4882a593Smuzhiyun #define WM9090_IN1_VU_MASK 0x0100 /* IN1_VU */ 214*4882a593Smuzhiyun #define WM9090_IN1_VU_SHIFT 8 /* IN1_VU */ 215*4882a593Smuzhiyun #define WM9090_IN1_VU_WIDTH 1 /* IN1_VU */ 216*4882a593Smuzhiyun #define WM9090_IN1B_MUTE 0x0080 /* IN1B_MUTE */ 217*4882a593Smuzhiyun #define WM9090_IN1B_MUTE_MASK 0x0080 /* IN1B_MUTE */ 218*4882a593Smuzhiyun #define WM9090_IN1B_MUTE_SHIFT 7 /* IN1B_MUTE */ 219*4882a593Smuzhiyun #define WM9090_IN1B_MUTE_WIDTH 1 /* IN1B_MUTE */ 220*4882a593Smuzhiyun #define WM9090_IN1B_ZC 0x0040 /* IN1B_ZC */ 221*4882a593Smuzhiyun #define WM9090_IN1B_ZC_MASK 0x0040 /* IN1B_ZC */ 222*4882a593Smuzhiyun #define WM9090_IN1B_ZC_SHIFT 6 /* IN1B_ZC */ 223*4882a593Smuzhiyun #define WM9090_IN1B_ZC_WIDTH 1 /* IN1B_ZC */ 224*4882a593Smuzhiyun #define WM9090_IN1B_VOL_MASK 0x0007 /* IN1B_VOL - [2:0] */ 225*4882a593Smuzhiyun #define WM9090_IN1B_VOL_SHIFT 0 /* IN1B_VOL - [2:0] */ 226*4882a593Smuzhiyun #define WM9090_IN1B_VOL_WIDTH 3 /* IN1B_VOL - [2:0] */ 227*4882a593Smuzhiyun 228*4882a593Smuzhiyun /* 229*4882a593Smuzhiyun * R26 (0x1A) - IN2 Line Input A Volume 230*4882a593Smuzhiyun */ 231*4882a593Smuzhiyun #define WM9090_IN2_VU 0x0100 /* IN2_VU */ 232*4882a593Smuzhiyun #define WM9090_IN2_VU_MASK 0x0100 /* IN2_VU */ 233*4882a593Smuzhiyun #define WM9090_IN2_VU_SHIFT 8 /* IN2_VU */ 234*4882a593Smuzhiyun #define WM9090_IN2_VU_WIDTH 1 /* IN2_VU */ 235*4882a593Smuzhiyun #define WM9090_IN2A_MUTE 0x0080 /* IN2A_MUTE */ 236*4882a593Smuzhiyun #define WM9090_IN2A_MUTE_MASK 0x0080 /* IN2A_MUTE */ 237*4882a593Smuzhiyun #define WM9090_IN2A_MUTE_SHIFT 7 /* IN2A_MUTE */ 238*4882a593Smuzhiyun #define WM9090_IN2A_MUTE_WIDTH 1 /* IN2A_MUTE */ 239*4882a593Smuzhiyun #define WM9090_IN2A_ZC 0x0040 /* IN2A_ZC */ 240*4882a593Smuzhiyun #define WM9090_IN2A_ZC_MASK 0x0040 /* IN2A_ZC */ 241*4882a593Smuzhiyun #define WM9090_IN2A_ZC_SHIFT 6 /* IN2A_ZC */ 242*4882a593Smuzhiyun #define WM9090_IN2A_ZC_WIDTH 1 /* IN2A_ZC */ 243*4882a593Smuzhiyun #define WM9090_IN2A_VOL_MASK 0x0007 /* IN2A_VOL - [2:0] */ 244*4882a593Smuzhiyun #define WM9090_IN2A_VOL_SHIFT 0 /* IN2A_VOL - [2:0] */ 245*4882a593Smuzhiyun #define WM9090_IN2A_VOL_WIDTH 3 /* IN2A_VOL - [2:0] */ 246*4882a593Smuzhiyun 247*4882a593Smuzhiyun /* 248*4882a593Smuzhiyun * R27 (0x1B) - IN2 Line Input B Volume 249*4882a593Smuzhiyun */ 250*4882a593Smuzhiyun #define WM9090_IN2_VU 0x0100 /* IN2_VU */ 251*4882a593Smuzhiyun #define WM9090_IN2_VU_MASK 0x0100 /* IN2_VU */ 252*4882a593Smuzhiyun #define WM9090_IN2_VU_SHIFT 8 /* IN2_VU */ 253*4882a593Smuzhiyun #define WM9090_IN2_VU_WIDTH 1 /* IN2_VU */ 254*4882a593Smuzhiyun #define WM9090_IN2B_MUTE 0x0080 /* IN2B_MUTE */ 255*4882a593Smuzhiyun #define WM9090_IN2B_MUTE_MASK 0x0080 /* IN2B_MUTE */ 256*4882a593Smuzhiyun #define WM9090_IN2B_MUTE_SHIFT 7 /* IN2B_MUTE */ 257*4882a593Smuzhiyun #define WM9090_IN2B_MUTE_WIDTH 1 /* IN2B_MUTE */ 258*4882a593Smuzhiyun #define WM9090_IN2B_ZC 0x0040 /* IN2B_ZC */ 259*4882a593Smuzhiyun #define WM9090_IN2B_ZC_MASK 0x0040 /* IN2B_ZC */ 260*4882a593Smuzhiyun #define WM9090_IN2B_ZC_SHIFT 6 /* IN2B_ZC */ 261*4882a593Smuzhiyun #define WM9090_IN2B_ZC_WIDTH 1 /* IN2B_ZC */ 262*4882a593Smuzhiyun #define WM9090_IN2B_VOL_MASK 0x0007 /* IN2B_VOL - [2:0] */ 263*4882a593Smuzhiyun #define WM9090_IN2B_VOL_SHIFT 0 /* IN2B_VOL - [2:0] */ 264*4882a593Smuzhiyun #define WM9090_IN2B_VOL_WIDTH 3 /* IN2B_VOL - [2:0] */ 265*4882a593Smuzhiyun 266*4882a593Smuzhiyun /* 267*4882a593Smuzhiyun * R28 (0x1C) - Left Output Volume 268*4882a593Smuzhiyun */ 269*4882a593Smuzhiyun #define WM9090_HPOUT1_VU 0x0100 /* HPOUT1_VU */ 270*4882a593Smuzhiyun #define WM9090_HPOUT1_VU_MASK 0x0100 /* HPOUT1_VU */ 271*4882a593Smuzhiyun #define WM9090_HPOUT1_VU_SHIFT 8 /* HPOUT1_VU */ 272*4882a593Smuzhiyun #define WM9090_HPOUT1_VU_WIDTH 1 /* HPOUT1_VU */ 273*4882a593Smuzhiyun #define WM9090_HPOUT1L_ZC 0x0080 /* HPOUT1L_ZC */ 274*4882a593Smuzhiyun #define WM9090_HPOUT1L_ZC_MASK 0x0080 /* HPOUT1L_ZC */ 275*4882a593Smuzhiyun #define WM9090_HPOUT1L_ZC_SHIFT 7 /* HPOUT1L_ZC */ 276*4882a593Smuzhiyun #define WM9090_HPOUT1L_ZC_WIDTH 1 /* HPOUT1L_ZC */ 277*4882a593Smuzhiyun #define WM9090_HPOUT1L_MUTE 0x0040 /* HPOUT1L_MUTE */ 278*4882a593Smuzhiyun #define WM9090_HPOUT1L_MUTE_MASK 0x0040 /* HPOUT1L_MUTE */ 279*4882a593Smuzhiyun #define WM9090_HPOUT1L_MUTE_SHIFT 6 /* HPOUT1L_MUTE */ 280*4882a593Smuzhiyun #define WM9090_HPOUT1L_MUTE_WIDTH 1 /* HPOUT1L_MUTE */ 281*4882a593Smuzhiyun #define WM9090_HPOUT1L_VOL_MASK 0x003F /* HPOUT1L_VOL - [5:0] */ 282*4882a593Smuzhiyun #define WM9090_HPOUT1L_VOL_SHIFT 0 /* HPOUT1L_VOL - [5:0] */ 283*4882a593Smuzhiyun #define WM9090_HPOUT1L_VOL_WIDTH 6 /* HPOUT1L_VOL - [5:0] */ 284*4882a593Smuzhiyun 285*4882a593Smuzhiyun /* 286*4882a593Smuzhiyun * R29 (0x1D) - Right Output Volume 287*4882a593Smuzhiyun */ 288*4882a593Smuzhiyun #define WM9090_HPOUT1_VU 0x0100 /* HPOUT1_VU */ 289*4882a593Smuzhiyun #define WM9090_HPOUT1_VU_MASK 0x0100 /* HPOUT1_VU */ 290*4882a593Smuzhiyun #define WM9090_HPOUT1_VU_SHIFT 8 /* HPOUT1_VU */ 291*4882a593Smuzhiyun #define WM9090_HPOUT1_VU_WIDTH 1 /* HPOUT1_VU */ 292*4882a593Smuzhiyun #define WM9090_HPOUT1R_ZC 0x0080 /* HPOUT1R_ZC */ 293*4882a593Smuzhiyun #define WM9090_HPOUT1R_ZC_MASK 0x0080 /* HPOUT1R_ZC */ 294*4882a593Smuzhiyun #define WM9090_HPOUT1R_ZC_SHIFT 7 /* HPOUT1R_ZC */ 295*4882a593Smuzhiyun #define WM9090_HPOUT1R_ZC_WIDTH 1 /* HPOUT1R_ZC */ 296*4882a593Smuzhiyun #define WM9090_HPOUT1R_MUTE 0x0040 /* HPOUT1R_MUTE */ 297*4882a593Smuzhiyun #define WM9090_HPOUT1R_MUTE_MASK 0x0040 /* HPOUT1R_MUTE */ 298*4882a593Smuzhiyun #define WM9090_HPOUT1R_MUTE_SHIFT 6 /* HPOUT1R_MUTE */ 299*4882a593Smuzhiyun #define WM9090_HPOUT1R_MUTE_WIDTH 1 /* HPOUT1R_MUTE */ 300*4882a593Smuzhiyun #define WM9090_HPOUT1R_VOL_MASK 0x003F /* HPOUT1R_VOL - [5:0] */ 301*4882a593Smuzhiyun #define WM9090_HPOUT1R_VOL_SHIFT 0 /* HPOUT1R_VOL - [5:0] */ 302*4882a593Smuzhiyun #define WM9090_HPOUT1R_VOL_WIDTH 6 /* HPOUT1R_VOL - [5:0] */ 303*4882a593Smuzhiyun 304*4882a593Smuzhiyun /* 305*4882a593Smuzhiyun * R34 (0x22) - SPKMIXL Attenuation 306*4882a593Smuzhiyun */ 307*4882a593Smuzhiyun #define WM9090_SPKMIX_MUTE 0x0100 /* SPKMIX_MUTE */ 308*4882a593Smuzhiyun #define WM9090_SPKMIX_MUTE_MASK 0x0100 /* SPKMIX_MUTE */ 309*4882a593Smuzhiyun #define WM9090_SPKMIX_MUTE_SHIFT 8 /* SPKMIX_MUTE */ 310*4882a593Smuzhiyun #define WM9090_SPKMIX_MUTE_WIDTH 1 /* SPKMIX_MUTE */ 311*4882a593Smuzhiyun #define WM9090_IN1A_SPKMIX_VOL_MASK 0x00C0 /* IN1A_SPKMIX_VOL - [7:6] */ 312*4882a593Smuzhiyun #define WM9090_IN1A_SPKMIX_VOL_SHIFT 6 /* IN1A_SPKMIX_VOL - [7:6] */ 313*4882a593Smuzhiyun #define WM9090_IN1A_SPKMIX_VOL_WIDTH 2 /* IN1A_SPKMIX_VOL - [7:6] */ 314*4882a593Smuzhiyun #define WM9090_IN1B_SPKMIX_VOL_MASK 0x0030 /* IN1B_SPKMIX_VOL - [5:4] */ 315*4882a593Smuzhiyun #define WM9090_IN1B_SPKMIX_VOL_SHIFT 4 /* IN1B_SPKMIX_VOL - [5:4] */ 316*4882a593Smuzhiyun #define WM9090_IN1B_SPKMIX_VOL_WIDTH 2 /* IN1B_SPKMIX_VOL - [5:4] */ 317*4882a593Smuzhiyun #define WM9090_IN2A_SPKMIX_VOL_MASK 0x000C /* IN2A_SPKMIX_VOL - [3:2] */ 318*4882a593Smuzhiyun #define WM9090_IN2A_SPKMIX_VOL_SHIFT 2 /* IN2A_SPKMIX_VOL - [3:2] */ 319*4882a593Smuzhiyun #define WM9090_IN2A_SPKMIX_VOL_WIDTH 2 /* IN2A_SPKMIX_VOL - [3:2] */ 320*4882a593Smuzhiyun #define WM9090_IN2B_SPKMIX_VOL_MASK 0x0003 /* IN2B_SPKMIX_VOL - [1:0] */ 321*4882a593Smuzhiyun #define WM9090_IN2B_SPKMIX_VOL_SHIFT 0 /* IN2B_SPKMIX_VOL - [1:0] */ 322*4882a593Smuzhiyun #define WM9090_IN2B_SPKMIX_VOL_WIDTH 2 /* IN2B_SPKMIX_VOL - [1:0] */ 323*4882a593Smuzhiyun 324*4882a593Smuzhiyun /* 325*4882a593Smuzhiyun * R36 (0x24) - SPKOUT Mixers 326*4882a593Smuzhiyun */ 327*4882a593Smuzhiyun #define WM9090_SPKMIXL_TO_SPKOUTL 0x0010 /* SPKMIXL_TO_SPKOUTL */ 328*4882a593Smuzhiyun #define WM9090_SPKMIXL_TO_SPKOUTL_MASK 0x0010 /* SPKMIXL_TO_SPKOUTL */ 329*4882a593Smuzhiyun #define WM9090_SPKMIXL_TO_SPKOUTL_SHIFT 4 /* SPKMIXL_TO_SPKOUTL */ 330*4882a593Smuzhiyun #define WM9090_SPKMIXL_TO_SPKOUTL_WIDTH 1 /* SPKMIXL_TO_SPKOUTL */ 331*4882a593Smuzhiyun 332*4882a593Smuzhiyun /* 333*4882a593Smuzhiyun * R37 (0x25) - ClassD3 334*4882a593Smuzhiyun */ 335*4882a593Smuzhiyun #define WM9090_SPKOUTL_BOOST_MASK 0x0038 /* SPKOUTL_BOOST - [5:3] */ 336*4882a593Smuzhiyun #define WM9090_SPKOUTL_BOOST_SHIFT 3 /* SPKOUTL_BOOST - [5:3] */ 337*4882a593Smuzhiyun #define WM9090_SPKOUTL_BOOST_WIDTH 3 /* SPKOUTL_BOOST - [5:3] */ 338*4882a593Smuzhiyun 339*4882a593Smuzhiyun /* 340*4882a593Smuzhiyun * R38 (0x26) - Speaker Volume Left 341*4882a593Smuzhiyun */ 342*4882a593Smuzhiyun #define WM9090_SPKOUT_VU 0x0100 /* SPKOUT_VU */ 343*4882a593Smuzhiyun #define WM9090_SPKOUT_VU_MASK 0x0100 /* SPKOUT_VU */ 344*4882a593Smuzhiyun #define WM9090_SPKOUT_VU_SHIFT 8 /* SPKOUT_VU */ 345*4882a593Smuzhiyun #define WM9090_SPKOUT_VU_WIDTH 1 /* SPKOUT_VU */ 346*4882a593Smuzhiyun #define WM9090_SPKOUTL_ZC 0x0080 /* SPKOUTL_ZC */ 347*4882a593Smuzhiyun #define WM9090_SPKOUTL_ZC_MASK 0x0080 /* SPKOUTL_ZC */ 348*4882a593Smuzhiyun #define WM9090_SPKOUTL_ZC_SHIFT 7 /* SPKOUTL_ZC */ 349*4882a593Smuzhiyun #define WM9090_SPKOUTL_ZC_WIDTH 1 /* SPKOUTL_ZC */ 350*4882a593Smuzhiyun #define WM9090_SPKOUTL_MUTE 0x0040 /* SPKOUTL_MUTE */ 351*4882a593Smuzhiyun #define WM9090_SPKOUTL_MUTE_MASK 0x0040 /* SPKOUTL_MUTE */ 352*4882a593Smuzhiyun #define WM9090_SPKOUTL_MUTE_SHIFT 6 /* SPKOUTL_MUTE */ 353*4882a593Smuzhiyun #define WM9090_SPKOUTL_MUTE_WIDTH 1 /* SPKOUTL_MUTE */ 354*4882a593Smuzhiyun #define WM9090_SPKOUTL_VOL_MASK 0x003F /* SPKOUTL_VOL - [5:0] */ 355*4882a593Smuzhiyun #define WM9090_SPKOUTL_VOL_SHIFT 0 /* SPKOUTL_VOL - [5:0] */ 356*4882a593Smuzhiyun #define WM9090_SPKOUTL_VOL_WIDTH 6 /* SPKOUTL_VOL - [5:0] */ 357*4882a593Smuzhiyun 358*4882a593Smuzhiyun /* 359*4882a593Smuzhiyun * R45 (0x2D) - Output Mixer1 360*4882a593Smuzhiyun */ 361*4882a593Smuzhiyun #define WM9090_IN1A_TO_MIXOUTL 0x0040 /* IN1A_TO_MIXOUTL */ 362*4882a593Smuzhiyun #define WM9090_IN1A_TO_MIXOUTL_MASK 0x0040 /* IN1A_TO_MIXOUTL */ 363*4882a593Smuzhiyun #define WM9090_IN1A_TO_MIXOUTL_SHIFT 6 /* IN1A_TO_MIXOUTL */ 364*4882a593Smuzhiyun #define WM9090_IN1A_TO_MIXOUTL_WIDTH 1 /* IN1A_TO_MIXOUTL */ 365*4882a593Smuzhiyun #define WM9090_IN2A_TO_MIXOUTL 0x0004 /* IN2A_TO_MIXOUTL */ 366*4882a593Smuzhiyun #define WM9090_IN2A_TO_MIXOUTL_MASK 0x0004 /* IN2A_TO_MIXOUTL */ 367*4882a593Smuzhiyun #define WM9090_IN2A_TO_MIXOUTL_SHIFT 2 /* IN2A_TO_MIXOUTL */ 368*4882a593Smuzhiyun #define WM9090_IN2A_TO_MIXOUTL_WIDTH 1 /* IN2A_TO_MIXOUTL */ 369*4882a593Smuzhiyun 370*4882a593Smuzhiyun /* 371*4882a593Smuzhiyun * R46 (0x2E) - Output Mixer2 372*4882a593Smuzhiyun */ 373*4882a593Smuzhiyun #define WM9090_IN1A_TO_MIXOUTR 0x0040 /* IN1A_TO_MIXOUTR */ 374*4882a593Smuzhiyun #define WM9090_IN1A_TO_MIXOUTR_MASK 0x0040 /* IN1A_TO_MIXOUTR */ 375*4882a593Smuzhiyun #define WM9090_IN1A_TO_MIXOUTR_SHIFT 6 /* IN1A_TO_MIXOUTR */ 376*4882a593Smuzhiyun #define WM9090_IN1A_TO_MIXOUTR_WIDTH 1 /* IN1A_TO_MIXOUTR */ 377*4882a593Smuzhiyun #define WM9090_IN1B_TO_MIXOUTR 0x0010 /* IN1B_TO_MIXOUTR */ 378*4882a593Smuzhiyun #define WM9090_IN1B_TO_MIXOUTR_MASK 0x0010 /* IN1B_TO_MIXOUTR */ 379*4882a593Smuzhiyun #define WM9090_IN1B_TO_MIXOUTR_SHIFT 4 /* IN1B_TO_MIXOUTR */ 380*4882a593Smuzhiyun #define WM9090_IN1B_TO_MIXOUTR_WIDTH 1 /* IN1B_TO_MIXOUTR */ 381*4882a593Smuzhiyun #define WM9090_IN2A_TO_MIXOUTR 0x0004 /* IN2A_TO_MIXOUTR */ 382*4882a593Smuzhiyun #define WM9090_IN2A_TO_MIXOUTR_MASK 0x0004 /* IN2A_TO_MIXOUTR */ 383*4882a593Smuzhiyun #define WM9090_IN2A_TO_MIXOUTR_SHIFT 2 /* IN2A_TO_MIXOUTR */ 384*4882a593Smuzhiyun #define WM9090_IN2A_TO_MIXOUTR_WIDTH 1 /* IN2A_TO_MIXOUTR */ 385*4882a593Smuzhiyun #define WM9090_IN2B_TO_MIXOUTR 0x0001 /* IN2B_TO_MIXOUTR */ 386*4882a593Smuzhiyun #define WM9090_IN2B_TO_MIXOUTR_MASK 0x0001 /* IN2B_TO_MIXOUTR */ 387*4882a593Smuzhiyun #define WM9090_IN2B_TO_MIXOUTR_SHIFT 0 /* IN2B_TO_MIXOUTR */ 388*4882a593Smuzhiyun #define WM9090_IN2B_TO_MIXOUTR_WIDTH 1 /* IN2B_TO_MIXOUTR */ 389*4882a593Smuzhiyun 390*4882a593Smuzhiyun /* 391*4882a593Smuzhiyun * R47 (0x2F) - Output Mixer3 392*4882a593Smuzhiyun */ 393*4882a593Smuzhiyun #define WM9090_MIXOUTL_MUTE 0x0100 /* MIXOUTL_MUTE */ 394*4882a593Smuzhiyun #define WM9090_MIXOUTL_MUTE_MASK 0x0100 /* MIXOUTL_MUTE */ 395*4882a593Smuzhiyun #define WM9090_MIXOUTL_MUTE_SHIFT 8 /* MIXOUTL_MUTE */ 396*4882a593Smuzhiyun #define WM9090_MIXOUTL_MUTE_WIDTH 1 /* MIXOUTL_MUTE */ 397*4882a593Smuzhiyun #define WM9090_IN1A_MIXOUTL_VOL_MASK 0x00C0 /* IN1A_MIXOUTL_VOL - [7:6] */ 398*4882a593Smuzhiyun #define WM9090_IN1A_MIXOUTL_VOL_SHIFT 6 /* IN1A_MIXOUTL_VOL - [7:6] */ 399*4882a593Smuzhiyun #define WM9090_IN1A_MIXOUTL_VOL_WIDTH 2 /* IN1A_MIXOUTL_VOL - [7:6] */ 400*4882a593Smuzhiyun #define WM9090_IN2A_MIXOUTL_VOL_MASK 0x000C /* IN2A_MIXOUTL_VOL - [3:2] */ 401*4882a593Smuzhiyun #define WM9090_IN2A_MIXOUTL_VOL_SHIFT 2 /* IN2A_MIXOUTL_VOL - [3:2] */ 402*4882a593Smuzhiyun #define WM9090_IN2A_MIXOUTL_VOL_WIDTH 2 /* IN2A_MIXOUTL_VOL - [3:2] */ 403*4882a593Smuzhiyun 404*4882a593Smuzhiyun /* 405*4882a593Smuzhiyun * R48 (0x30) - Output Mixer4 406*4882a593Smuzhiyun */ 407*4882a593Smuzhiyun #define WM9090_MIXOUTR_MUTE 0x0100 /* MIXOUTR_MUTE */ 408*4882a593Smuzhiyun #define WM9090_MIXOUTR_MUTE_MASK 0x0100 /* MIXOUTR_MUTE */ 409*4882a593Smuzhiyun #define WM9090_MIXOUTR_MUTE_SHIFT 8 /* MIXOUTR_MUTE */ 410*4882a593Smuzhiyun #define WM9090_MIXOUTR_MUTE_WIDTH 1 /* MIXOUTR_MUTE */ 411*4882a593Smuzhiyun #define WM9090_IN1A_MIXOUTR_VOL_MASK 0x00C0 /* IN1A_MIXOUTR_VOL - [7:6] */ 412*4882a593Smuzhiyun #define WM9090_IN1A_MIXOUTR_VOL_SHIFT 6 /* IN1A_MIXOUTR_VOL - [7:6] */ 413*4882a593Smuzhiyun #define WM9090_IN1A_MIXOUTR_VOL_WIDTH 2 /* IN1A_MIXOUTR_VOL - [7:6] */ 414*4882a593Smuzhiyun #define WM9090_IN1B_MIXOUTR_VOL_MASK 0x0030 /* IN1B_MIXOUTR_VOL - [5:4] */ 415*4882a593Smuzhiyun #define WM9090_IN1B_MIXOUTR_VOL_SHIFT 4 /* IN1B_MIXOUTR_VOL - [5:4] */ 416*4882a593Smuzhiyun #define WM9090_IN1B_MIXOUTR_VOL_WIDTH 2 /* IN1B_MIXOUTR_VOL - [5:4] */ 417*4882a593Smuzhiyun #define WM9090_IN2A_MIXOUTR_VOL_MASK 0x000C /* IN2A_MIXOUTR_VOL - [3:2] */ 418*4882a593Smuzhiyun #define WM9090_IN2A_MIXOUTR_VOL_SHIFT 2 /* IN2A_MIXOUTR_VOL - [3:2] */ 419*4882a593Smuzhiyun #define WM9090_IN2A_MIXOUTR_VOL_WIDTH 2 /* IN2A_MIXOUTR_VOL - [3:2] */ 420*4882a593Smuzhiyun #define WM9090_IN2B_MIXOUTR_VOL_MASK 0x0003 /* IN2B_MIXOUTR_VOL - [1:0] */ 421*4882a593Smuzhiyun #define WM9090_IN2B_MIXOUTR_VOL_SHIFT 0 /* IN2B_MIXOUTR_VOL - [1:0] */ 422*4882a593Smuzhiyun #define WM9090_IN2B_MIXOUTR_VOL_WIDTH 2 /* IN2B_MIXOUTR_VOL - [1:0] */ 423*4882a593Smuzhiyun 424*4882a593Smuzhiyun /* 425*4882a593Smuzhiyun * R54 (0x36) - Speaker Mixer 426*4882a593Smuzhiyun */ 427*4882a593Smuzhiyun #define WM9090_IN1A_TO_SPKMIX 0x0040 /* IN1A_TO_SPKMIX */ 428*4882a593Smuzhiyun #define WM9090_IN1A_TO_SPKMIX_MASK 0x0040 /* IN1A_TO_SPKMIX */ 429*4882a593Smuzhiyun #define WM9090_IN1A_TO_SPKMIX_SHIFT 6 /* IN1A_TO_SPKMIX */ 430*4882a593Smuzhiyun #define WM9090_IN1A_TO_SPKMIX_WIDTH 1 /* IN1A_TO_SPKMIX */ 431*4882a593Smuzhiyun #define WM9090_IN1B_TO_SPKMIX 0x0010 /* IN1B_TO_SPKMIX */ 432*4882a593Smuzhiyun #define WM9090_IN1B_TO_SPKMIX_MASK 0x0010 /* IN1B_TO_SPKMIX */ 433*4882a593Smuzhiyun #define WM9090_IN1B_TO_SPKMIX_SHIFT 4 /* IN1B_TO_SPKMIX */ 434*4882a593Smuzhiyun #define WM9090_IN1B_TO_SPKMIX_WIDTH 1 /* IN1B_TO_SPKMIX */ 435*4882a593Smuzhiyun #define WM9090_IN2A_TO_SPKMIX 0x0004 /* IN2A_TO_SPKMIX */ 436*4882a593Smuzhiyun #define WM9090_IN2A_TO_SPKMIX_MASK 0x0004 /* IN2A_TO_SPKMIX */ 437*4882a593Smuzhiyun #define WM9090_IN2A_TO_SPKMIX_SHIFT 2 /* IN2A_TO_SPKMIX */ 438*4882a593Smuzhiyun #define WM9090_IN2A_TO_SPKMIX_WIDTH 1 /* IN2A_TO_SPKMIX */ 439*4882a593Smuzhiyun #define WM9090_IN2B_TO_SPKMIX 0x0001 /* IN2B_TO_SPKMIX */ 440*4882a593Smuzhiyun #define WM9090_IN2B_TO_SPKMIX_MASK 0x0001 /* IN2B_TO_SPKMIX */ 441*4882a593Smuzhiyun #define WM9090_IN2B_TO_SPKMIX_SHIFT 0 /* IN2B_TO_SPKMIX */ 442*4882a593Smuzhiyun #define WM9090_IN2B_TO_SPKMIX_WIDTH 1 /* IN2B_TO_SPKMIX */ 443*4882a593Smuzhiyun 444*4882a593Smuzhiyun /* 445*4882a593Smuzhiyun * R57 (0x39) - AntiPOP2 446*4882a593Smuzhiyun */ 447*4882a593Smuzhiyun #define WM9090_VMID_BUF_ENA 0x0008 /* VMID_BUF_ENA */ 448*4882a593Smuzhiyun #define WM9090_VMID_BUF_ENA_MASK 0x0008 /* VMID_BUF_ENA */ 449*4882a593Smuzhiyun #define WM9090_VMID_BUF_ENA_SHIFT 3 /* VMID_BUF_ENA */ 450*4882a593Smuzhiyun #define WM9090_VMID_BUF_ENA_WIDTH 1 /* VMID_BUF_ENA */ 451*4882a593Smuzhiyun #define WM9090_VMID_ENA 0x0001 /* VMID_ENA */ 452*4882a593Smuzhiyun #define WM9090_VMID_ENA_MASK 0x0001 /* VMID_ENA */ 453*4882a593Smuzhiyun #define WM9090_VMID_ENA_SHIFT 0 /* VMID_ENA */ 454*4882a593Smuzhiyun #define WM9090_VMID_ENA_WIDTH 1 /* VMID_ENA */ 455*4882a593Smuzhiyun 456*4882a593Smuzhiyun /* 457*4882a593Smuzhiyun * R70 (0x46) - Write Sequencer 0 458*4882a593Smuzhiyun */ 459*4882a593Smuzhiyun #define WM9090_WSEQ_ENA 0x0100 /* WSEQ_ENA */ 460*4882a593Smuzhiyun #define WM9090_WSEQ_ENA_MASK 0x0100 /* WSEQ_ENA */ 461*4882a593Smuzhiyun #define WM9090_WSEQ_ENA_SHIFT 8 /* WSEQ_ENA */ 462*4882a593Smuzhiyun #define WM9090_WSEQ_ENA_WIDTH 1 /* WSEQ_ENA */ 463*4882a593Smuzhiyun #define WM9090_WSEQ_WRITE_INDEX_MASK 0x000F /* WSEQ_WRITE_INDEX - [3:0] */ 464*4882a593Smuzhiyun #define WM9090_WSEQ_WRITE_INDEX_SHIFT 0 /* WSEQ_WRITE_INDEX - [3:0] */ 465*4882a593Smuzhiyun #define WM9090_WSEQ_WRITE_INDEX_WIDTH 4 /* WSEQ_WRITE_INDEX - [3:0] */ 466*4882a593Smuzhiyun 467*4882a593Smuzhiyun /* 468*4882a593Smuzhiyun * R71 (0x47) - Write Sequencer 1 469*4882a593Smuzhiyun */ 470*4882a593Smuzhiyun #define WM9090_WSEQ_DATA_WIDTH_MASK 0x7000 /* WSEQ_DATA_WIDTH - [14:12] */ 471*4882a593Smuzhiyun #define WM9090_WSEQ_DATA_WIDTH_SHIFT 12 /* WSEQ_DATA_WIDTH - [14:12] */ 472*4882a593Smuzhiyun #define WM9090_WSEQ_DATA_WIDTH_WIDTH 3 /* WSEQ_DATA_WIDTH - [14:12] */ 473*4882a593Smuzhiyun #define WM9090_WSEQ_DATA_START_MASK 0x0F00 /* WSEQ_DATA_START - [11:8] */ 474*4882a593Smuzhiyun #define WM9090_WSEQ_DATA_START_SHIFT 8 /* WSEQ_DATA_START - [11:8] */ 475*4882a593Smuzhiyun #define WM9090_WSEQ_DATA_START_WIDTH 4 /* WSEQ_DATA_START - [11:8] */ 476*4882a593Smuzhiyun #define WM9090_WSEQ_ADDR_MASK 0x00FF /* WSEQ_ADDR - [7:0] */ 477*4882a593Smuzhiyun #define WM9090_WSEQ_ADDR_SHIFT 0 /* WSEQ_ADDR - [7:0] */ 478*4882a593Smuzhiyun #define WM9090_WSEQ_ADDR_WIDTH 8 /* WSEQ_ADDR - [7:0] */ 479*4882a593Smuzhiyun 480*4882a593Smuzhiyun /* 481*4882a593Smuzhiyun * R72 (0x48) - Write Sequencer 2 482*4882a593Smuzhiyun */ 483*4882a593Smuzhiyun #define WM9090_WSEQ_EOS 0x4000 /* WSEQ_EOS */ 484*4882a593Smuzhiyun #define WM9090_WSEQ_EOS_MASK 0x4000 /* WSEQ_EOS */ 485*4882a593Smuzhiyun #define WM9090_WSEQ_EOS_SHIFT 14 /* WSEQ_EOS */ 486*4882a593Smuzhiyun #define WM9090_WSEQ_EOS_WIDTH 1 /* WSEQ_EOS */ 487*4882a593Smuzhiyun #define WM9090_WSEQ_DELAY_MASK 0x0F00 /* WSEQ_DELAY - [11:8] */ 488*4882a593Smuzhiyun #define WM9090_WSEQ_DELAY_SHIFT 8 /* WSEQ_DELAY - [11:8] */ 489*4882a593Smuzhiyun #define WM9090_WSEQ_DELAY_WIDTH 4 /* WSEQ_DELAY - [11:8] */ 490*4882a593Smuzhiyun #define WM9090_WSEQ_DATA_MASK 0x00FF /* WSEQ_DATA - [7:0] */ 491*4882a593Smuzhiyun #define WM9090_WSEQ_DATA_SHIFT 0 /* WSEQ_DATA - [7:0] */ 492*4882a593Smuzhiyun #define WM9090_WSEQ_DATA_WIDTH 8 /* WSEQ_DATA - [7:0] */ 493*4882a593Smuzhiyun 494*4882a593Smuzhiyun /* 495*4882a593Smuzhiyun * R73 (0x49) - Write Sequencer 3 496*4882a593Smuzhiyun */ 497*4882a593Smuzhiyun #define WM9090_WSEQ_ABORT 0x0200 /* WSEQ_ABORT */ 498*4882a593Smuzhiyun #define WM9090_WSEQ_ABORT_MASK 0x0200 /* WSEQ_ABORT */ 499*4882a593Smuzhiyun #define WM9090_WSEQ_ABORT_SHIFT 9 /* WSEQ_ABORT */ 500*4882a593Smuzhiyun #define WM9090_WSEQ_ABORT_WIDTH 1 /* WSEQ_ABORT */ 501*4882a593Smuzhiyun #define WM9090_WSEQ_START 0x0100 /* WSEQ_START */ 502*4882a593Smuzhiyun #define WM9090_WSEQ_START_MASK 0x0100 /* WSEQ_START */ 503*4882a593Smuzhiyun #define WM9090_WSEQ_START_SHIFT 8 /* WSEQ_START */ 504*4882a593Smuzhiyun #define WM9090_WSEQ_START_WIDTH 1 /* WSEQ_START */ 505*4882a593Smuzhiyun #define WM9090_WSEQ_START_INDEX_MASK 0x003F /* WSEQ_START_INDEX - [5:0] */ 506*4882a593Smuzhiyun #define WM9090_WSEQ_START_INDEX_SHIFT 0 /* WSEQ_START_INDEX - [5:0] */ 507*4882a593Smuzhiyun #define WM9090_WSEQ_START_INDEX_WIDTH 6 /* WSEQ_START_INDEX - [5:0] */ 508*4882a593Smuzhiyun 509*4882a593Smuzhiyun /* 510*4882a593Smuzhiyun * R74 (0x4A) - Write Sequencer 4 511*4882a593Smuzhiyun */ 512*4882a593Smuzhiyun #define WM9090_WSEQ_BUSY 0x0001 /* WSEQ_BUSY */ 513*4882a593Smuzhiyun #define WM9090_WSEQ_BUSY_MASK 0x0001 /* WSEQ_BUSY */ 514*4882a593Smuzhiyun #define WM9090_WSEQ_BUSY_SHIFT 0 /* WSEQ_BUSY */ 515*4882a593Smuzhiyun #define WM9090_WSEQ_BUSY_WIDTH 1 /* WSEQ_BUSY */ 516*4882a593Smuzhiyun 517*4882a593Smuzhiyun /* 518*4882a593Smuzhiyun * R75 (0x4B) - Write Sequencer 5 519*4882a593Smuzhiyun */ 520*4882a593Smuzhiyun #define WM9090_WSEQ_CURRENT_INDEX_MASK 0x003F /* WSEQ_CURRENT_INDEX - [5:0] */ 521*4882a593Smuzhiyun #define WM9090_WSEQ_CURRENT_INDEX_SHIFT 0 /* WSEQ_CURRENT_INDEX - [5:0] */ 522*4882a593Smuzhiyun #define WM9090_WSEQ_CURRENT_INDEX_WIDTH 6 /* WSEQ_CURRENT_INDEX - [5:0] */ 523*4882a593Smuzhiyun 524*4882a593Smuzhiyun /* 525*4882a593Smuzhiyun * R76 (0x4C) - Charge Pump 1 526*4882a593Smuzhiyun */ 527*4882a593Smuzhiyun #define WM9090_CP_ENA 0x8000 /* CP_ENA */ 528*4882a593Smuzhiyun #define WM9090_CP_ENA_MASK 0x8000 /* CP_ENA */ 529*4882a593Smuzhiyun #define WM9090_CP_ENA_SHIFT 15 /* CP_ENA */ 530*4882a593Smuzhiyun #define WM9090_CP_ENA_WIDTH 1 /* CP_ENA */ 531*4882a593Smuzhiyun 532*4882a593Smuzhiyun /* 533*4882a593Smuzhiyun * R84 (0x54) - DC Servo 0 534*4882a593Smuzhiyun */ 535*4882a593Smuzhiyun #define WM9090_DCS_TRIG_SINGLE_1 0x2000 /* DCS_TRIG_SINGLE_1 */ 536*4882a593Smuzhiyun #define WM9090_DCS_TRIG_SINGLE_1_MASK 0x2000 /* DCS_TRIG_SINGLE_1 */ 537*4882a593Smuzhiyun #define WM9090_DCS_TRIG_SINGLE_1_SHIFT 13 /* DCS_TRIG_SINGLE_1 */ 538*4882a593Smuzhiyun #define WM9090_DCS_TRIG_SINGLE_1_WIDTH 1 /* DCS_TRIG_SINGLE_1 */ 539*4882a593Smuzhiyun #define WM9090_DCS_TRIG_SINGLE_0 0x1000 /* DCS_TRIG_SINGLE_0 */ 540*4882a593Smuzhiyun #define WM9090_DCS_TRIG_SINGLE_0_MASK 0x1000 /* DCS_TRIG_SINGLE_0 */ 541*4882a593Smuzhiyun #define WM9090_DCS_TRIG_SINGLE_0_SHIFT 12 /* DCS_TRIG_SINGLE_0 */ 542*4882a593Smuzhiyun #define WM9090_DCS_TRIG_SINGLE_0_WIDTH 1 /* DCS_TRIG_SINGLE_0 */ 543*4882a593Smuzhiyun #define WM9090_DCS_TRIG_SERIES_1 0x0200 /* DCS_TRIG_SERIES_1 */ 544*4882a593Smuzhiyun #define WM9090_DCS_TRIG_SERIES_1_MASK 0x0200 /* DCS_TRIG_SERIES_1 */ 545*4882a593Smuzhiyun #define WM9090_DCS_TRIG_SERIES_1_SHIFT 9 /* DCS_TRIG_SERIES_1 */ 546*4882a593Smuzhiyun #define WM9090_DCS_TRIG_SERIES_1_WIDTH 1 /* DCS_TRIG_SERIES_1 */ 547*4882a593Smuzhiyun #define WM9090_DCS_TRIG_SERIES_0 0x0100 /* DCS_TRIG_SERIES_0 */ 548*4882a593Smuzhiyun #define WM9090_DCS_TRIG_SERIES_0_MASK 0x0100 /* DCS_TRIG_SERIES_0 */ 549*4882a593Smuzhiyun #define WM9090_DCS_TRIG_SERIES_0_SHIFT 8 /* DCS_TRIG_SERIES_0 */ 550*4882a593Smuzhiyun #define WM9090_DCS_TRIG_SERIES_0_WIDTH 1 /* DCS_TRIG_SERIES_0 */ 551*4882a593Smuzhiyun #define WM9090_DCS_TRIG_STARTUP_1 0x0020 /* DCS_TRIG_STARTUP_1 */ 552*4882a593Smuzhiyun #define WM9090_DCS_TRIG_STARTUP_1_MASK 0x0020 /* DCS_TRIG_STARTUP_1 */ 553*4882a593Smuzhiyun #define WM9090_DCS_TRIG_STARTUP_1_SHIFT 5 /* DCS_TRIG_STARTUP_1 */ 554*4882a593Smuzhiyun #define WM9090_DCS_TRIG_STARTUP_1_WIDTH 1 /* DCS_TRIG_STARTUP_1 */ 555*4882a593Smuzhiyun #define WM9090_DCS_TRIG_STARTUP_0 0x0010 /* DCS_TRIG_STARTUP_0 */ 556*4882a593Smuzhiyun #define WM9090_DCS_TRIG_STARTUP_0_MASK 0x0010 /* DCS_TRIG_STARTUP_0 */ 557*4882a593Smuzhiyun #define WM9090_DCS_TRIG_STARTUP_0_SHIFT 4 /* DCS_TRIG_STARTUP_0 */ 558*4882a593Smuzhiyun #define WM9090_DCS_TRIG_STARTUP_0_WIDTH 1 /* DCS_TRIG_STARTUP_0 */ 559*4882a593Smuzhiyun #define WM9090_DCS_TRIG_DAC_WR_1 0x0008 /* DCS_TRIG_DAC_WR_1 */ 560*4882a593Smuzhiyun #define WM9090_DCS_TRIG_DAC_WR_1_MASK 0x0008 /* DCS_TRIG_DAC_WR_1 */ 561*4882a593Smuzhiyun #define WM9090_DCS_TRIG_DAC_WR_1_SHIFT 3 /* DCS_TRIG_DAC_WR_1 */ 562*4882a593Smuzhiyun #define WM9090_DCS_TRIG_DAC_WR_1_WIDTH 1 /* DCS_TRIG_DAC_WR_1 */ 563*4882a593Smuzhiyun #define WM9090_DCS_TRIG_DAC_WR_0 0x0004 /* DCS_TRIG_DAC_WR_0 */ 564*4882a593Smuzhiyun #define WM9090_DCS_TRIG_DAC_WR_0_MASK 0x0004 /* DCS_TRIG_DAC_WR_0 */ 565*4882a593Smuzhiyun #define WM9090_DCS_TRIG_DAC_WR_0_SHIFT 2 /* DCS_TRIG_DAC_WR_0 */ 566*4882a593Smuzhiyun #define WM9090_DCS_TRIG_DAC_WR_0_WIDTH 1 /* DCS_TRIG_DAC_WR_0 */ 567*4882a593Smuzhiyun #define WM9090_DCS_ENA_CHAN_1 0x0002 /* DCS_ENA_CHAN_1 */ 568*4882a593Smuzhiyun #define WM9090_DCS_ENA_CHAN_1_MASK 0x0002 /* DCS_ENA_CHAN_1 */ 569*4882a593Smuzhiyun #define WM9090_DCS_ENA_CHAN_1_SHIFT 1 /* DCS_ENA_CHAN_1 */ 570*4882a593Smuzhiyun #define WM9090_DCS_ENA_CHAN_1_WIDTH 1 /* DCS_ENA_CHAN_1 */ 571*4882a593Smuzhiyun #define WM9090_DCS_ENA_CHAN_0 0x0001 /* DCS_ENA_CHAN_0 */ 572*4882a593Smuzhiyun #define WM9090_DCS_ENA_CHAN_0_MASK 0x0001 /* DCS_ENA_CHAN_0 */ 573*4882a593Smuzhiyun #define WM9090_DCS_ENA_CHAN_0_SHIFT 0 /* DCS_ENA_CHAN_0 */ 574*4882a593Smuzhiyun #define WM9090_DCS_ENA_CHAN_0_WIDTH 1 /* DCS_ENA_CHAN_0 */ 575*4882a593Smuzhiyun 576*4882a593Smuzhiyun /* 577*4882a593Smuzhiyun * R85 (0x55) - DC Servo 1 578*4882a593Smuzhiyun */ 579*4882a593Smuzhiyun #define WM9090_DCS_SERIES_NO_01_MASK 0x0FE0 /* DCS_SERIES_NO_01 - [11:5] */ 580*4882a593Smuzhiyun #define WM9090_DCS_SERIES_NO_01_SHIFT 5 /* DCS_SERIES_NO_01 - [11:5] */ 581*4882a593Smuzhiyun #define WM9090_DCS_SERIES_NO_01_WIDTH 7 /* DCS_SERIES_NO_01 - [11:5] */ 582*4882a593Smuzhiyun #define WM9090_DCS_TIMER_PERIOD_01_MASK 0x000F /* DCS_TIMER_PERIOD_01 - [3:0] */ 583*4882a593Smuzhiyun #define WM9090_DCS_TIMER_PERIOD_01_SHIFT 0 /* DCS_TIMER_PERIOD_01 - [3:0] */ 584*4882a593Smuzhiyun #define WM9090_DCS_TIMER_PERIOD_01_WIDTH 4 /* DCS_TIMER_PERIOD_01 - [3:0] */ 585*4882a593Smuzhiyun 586*4882a593Smuzhiyun /* 587*4882a593Smuzhiyun * R87 (0x57) - DC Servo 3 588*4882a593Smuzhiyun */ 589*4882a593Smuzhiyun #define WM9090_DCS_DAC_WR_VAL_1_MASK 0xFF00 /* DCS_DAC_WR_VAL_1 - [15:8] */ 590*4882a593Smuzhiyun #define WM9090_DCS_DAC_WR_VAL_1_SHIFT 8 /* DCS_DAC_WR_VAL_1 - [15:8] */ 591*4882a593Smuzhiyun #define WM9090_DCS_DAC_WR_VAL_1_WIDTH 8 /* DCS_DAC_WR_VAL_1 - [15:8] */ 592*4882a593Smuzhiyun #define WM9090_DCS_DAC_WR_VAL_0_MASK 0x00FF /* DCS_DAC_WR_VAL_0 - [7:0] */ 593*4882a593Smuzhiyun #define WM9090_DCS_DAC_WR_VAL_0_SHIFT 0 /* DCS_DAC_WR_VAL_0 - [7:0] */ 594*4882a593Smuzhiyun #define WM9090_DCS_DAC_WR_VAL_0_WIDTH 8 /* DCS_DAC_WR_VAL_0 - [7:0] */ 595*4882a593Smuzhiyun 596*4882a593Smuzhiyun /* 597*4882a593Smuzhiyun * R88 (0x58) - DC Servo Readback 0 598*4882a593Smuzhiyun */ 599*4882a593Smuzhiyun #define WM9090_DCS_CAL_COMPLETE_MASK 0x0300 /* DCS_CAL_COMPLETE - [9:8] */ 600*4882a593Smuzhiyun #define WM9090_DCS_CAL_COMPLETE_SHIFT 8 /* DCS_CAL_COMPLETE - [9:8] */ 601*4882a593Smuzhiyun #define WM9090_DCS_CAL_COMPLETE_WIDTH 2 /* DCS_CAL_COMPLETE - [9:8] */ 602*4882a593Smuzhiyun #define WM9090_DCS_DAC_WR_COMPLETE_MASK 0x0030 /* DCS_DAC_WR_COMPLETE - [5:4] */ 603*4882a593Smuzhiyun #define WM9090_DCS_DAC_WR_COMPLETE_SHIFT 4 /* DCS_DAC_WR_COMPLETE - [5:4] */ 604*4882a593Smuzhiyun #define WM9090_DCS_DAC_WR_COMPLETE_WIDTH 2 /* DCS_DAC_WR_COMPLETE - [5:4] */ 605*4882a593Smuzhiyun #define WM9090_DCS_STARTUP_COMPLETE_MASK 0x0003 /* DCS_STARTUP_COMPLETE - [1:0] */ 606*4882a593Smuzhiyun #define WM9090_DCS_STARTUP_COMPLETE_SHIFT 0 /* DCS_STARTUP_COMPLETE - [1:0] */ 607*4882a593Smuzhiyun #define WM9090_DCS_STARTUP_COMPLETE_WIDTH 2 /* DCS_STARTUP_COMPLETE - [1:0] */ 608*4882a593Smuzhiyun 609*4882a593Smuzhiyun /* 610*4882a593Smuzhiyun * R89 (0x59) - DC Servo Readback 1 611*4882a593Smuzhiyun */ 612*4882a593Smuzhiyun #define WM9090_DCS_DAC_WR_VAL_1_RD_MASK 0x00FF /* DCS_DAC_WR_VAL_1_RD - [7:0] */ 613*4882a593Smuzhiyun #define WM9090_DCS_DAC_WR_VAL_1_RD_SHIFT 0 /* DCS_DAC_WR_VAL_1_RD - [7:0] */ 614*4882a593Smuzhiyun #define WM9090_DCS_DAC_WR_VAL_1_RD_WIDTH 8 /* DCS_DAC_WR_VAL_1_RD - [7:0] */ 615*4882a593Smuzhiyun 616*4882a593Smuzhiyun /* 617*4882a593Smuzhiyun * R90 (0x5A) - DC Servo Readback 2 618*4882a593Smuzhiyun */ 619*4882a593Smuzhiyun #define WM9090_DCS_DAC_WR_VAL_0_RD_MASK 0x00FF /* DCS_DAC_WR_VAL_0_RD - [7:0] */ 620*4882a593Smuzhiyun #define WM9090_DCS_DAC_WR_VAL_0_RD_SHIFT 0 /* DCS_DAC_WR_VAL_0_RD - [7:0] */ 621*4882a593Smuzhiyun #define WM9090_DCS_DAC_WR_VAL_0_RD_WIDTH 8 /* DCS_DAC_WR_VAL_0_RD - [7:0] */ 622*4882a593Smuzhiyun 623*4882a593Smuzhiyun /* 624*4882a593Smuzhiyun * R96 (0x60) - Analogue HP 0 625*4882a593Smuzhiyun */ 626*4882a593Smuzhiyun #define WM9090_HPOUT1L_RMV_SHORT 0x0080 /* HPOUT1L_RMV_SHORT */ 627*4882a593Smuzhiyun #define WM9090_HPOUT1L_RMV_SHORT_MASK 0x0080 /* HPOUT1L_RMV_SHORT */ 628*4882a593Smuzhiyun #define WM9090_HPOUT1L_RMV_SHORT_SHIFT 7 /* HPOUT1L_RMV_SHORT */ 629*4882a593Smuzhiyun #define WM9090_HPOUT1L_RMV_SHORT_WIDTH 1 /* HPOUT1L_RMV_SHORT */ 630*4882a593Smuzhiyun #define WM9090_HPOUT1L_OUTP 0x0040 /* HPOUT1L_OUTP */ 631*4882a593Smuzhiyun #define WM9090_HPOUT1L_OUTP_MASK 0x0040 /* HPOUT1L_OUTP */ 632*4882a593Smuzhiyun #define WM9090_HPOUT1L_OUTP_SHIFT 6 /* HPOUT1L_OUTP */ 633*4882a593Smuzhiyun #define WM9090_HPOUT1L_OUTP_WIDTH 1 /* HPOUT1L_OUTP */ 634*4882a593Smuzhiyun #define WM9090_HPOUT1L_DLY 0x0020 /* HPOUT1L_DLY */ 635*4882a593Smuzhiyun #define WM9090_HPOUT1L_DLY_MASK 0x0020 /* HPOUT1L_DLY */ 636*4882a593Smuzhiyun #define WM9090_HPOUT1L_DLY_SHIFT 5 /* HPOUT1L_DLY */ 637*4882a593Smuzhiyun #define WM9090_HPOUT1L_DLY_WIDTH 1 /* HPOUT1L_DLY */ 638*4882a593Smuzhiyun #define WM9090_HPOUT1R_RMV_SHORT 0x0008 /* HPOUT1R_RMV_SHORT */ 639*4882a593Smuzhiyun #define WM9090_HPOUT1R_RMV_SHORT_MASK 0x0008 /* HPOUT1R_RMV_SHORT */ 640*4882a593Smuzhiyun #define WM9090_HPOUT1R_RMV_SHORT_SHIFT 3 /* HPOUT1R_RMV_SHORT */ 641*4882a593Smuzhiyun #define WM9090_HPOUT1R_RMV_SHORT_WIDTH 1 /* HPOUT1R_RMV_SHORT */ 642*4882a593Smuzhiyun #define WM9090_HPOUT1R_OUTP 0x0004 /* HPOUT1R_OUTP */ 643*4882a593Smuzhiyun #define WM9090_HPOUT1R_OUTP_MASK 0x0004 /* HPOUT1R_OUTP */ 644*4882a593Smuzhiyun #define WM9090_HPOUT1R_OUTP_SHIFT 2 /* HPOUT1R_OUTP */ 645*4882a593Smuzhiyun #define WM9090_HPOUT1R_OUTP_WIDTH 1 /* HPOUT1R_OUTP */ 646*4882a593Smuzhiyun #define WM9090_HPOUT1R_DLY 0x0002 /* HPOUT1R_DLY */ 647*4882a593Smuzhiyun #define WM9090_HPOUT1R_DLY_MASK 0x0002 /* HPOUT1R_DLY */ 648*4882a593Smuzhiyun #define WM9090_HPOUT1R_DLY_SHIFT 1 /* HPOUT1R_DLY */ 649*4882a593Smuzhiyun #define WM9090_HPOUT1R_DLY_WIDTH 1 /* HPOUT1R_DLY */ 650*4882a593Smuzhiyun 651*4882a593Smuzhiyun /* 652*4882a593Smuzhiyun * R98 (0x62) - AGC Control 0 653*4882a593Smuzhiyun */ 654*4882a593Smuzhiyun #define WM9090_AGC_CLIP_ENA 0x8000 /* AGC_CLIP_ENA */ 655*4882a593Smuzhiyun #define WM9090_AGC_CLIP_ENA_MASK 0x8000 /* AGC_CLIP_ENA */ 656*4882a593Smuzhiyun #define WM9090_AGC_CLIP_ENA_SHIFT 15 /* AGC_CLIP_ENA */ 657*4882a593Smuzhiyun #define WM9090_AGC_CLIP_ENA_WIDTH 1 /* AGC_CLIP_ENA */ 658*4882a593Smuzhiyun #define WM9090_AGC_CLIP_THR_MASK 0x0F00 /* AGC_CLIP_THR - [11:8] */ 659*4882a593Smuzhiyun #define WM9090_AGC_CLIP_THR_SHIFT 8 /* AGC_CLIP_THR - [11:8] */ 660*4882a593Smuzhiyun #define WM9090_AGC_CLIP_THR_WIDTH 4 /* AGC_CLIP_THR - [11:8] */ 661*4882a593Smuzhiyun #define WM9090_AGC_CLIP_ATK_MASK 0x0070 /* AGC_CLIP_ATK - [6:4] */ 662*4882a593Smuzhiyun #define WM9090_AGC_CLIP_ATK_SHIFT 4 /* AGC_CLIP_ATK - [6:4] */ 663*4882a593Smuzhiyun #define WM9090_AGC_CLIP_ATK_WIDTH 3 /* AGC_CLIP_ATK - [6:4] */ 664*4882a593Smuzhiyun #define WM9090_AGC_CLIP_DCY_MASK 0x0007 /* AGC_CLIP_DCY - [2:0] */ 665*4882a593Smuzhiyun #define WM9090_AGC_CLIP_DCY_SHIFT 0 /* AGC_CLIP_DCY - [2:0] */ 666*4882a593Smuzhiyun #define WM9090_AGC_CLIP_DCY_WIDTH 3 /* AGC_CLIP_DCY - [2:0] */ 667*4882a593Smuzhiyun 668*4882a593Smuzhiyun /* 669*4882a593Smuzhiyun * R99 (0x63) - AGC Control 1 670*4882a593Smuzhiyun */ 671*4882a593Smuzhiyun #define WM9090_AGC_PWR_ENA 0x8000 /* AGC_PWR_ENA */ 672*4882a593Smuzhiyun #define WM9090_AGC_PWR_ENA_MASK 0x8000 /* AGC_PWR_ENA */ 673*4882a593Smuzhiyun #define WM9090_AGC_PWR_ENA_SHIFT 15 /* AGC_PWR_ENA */ 674*4882a593Smuzhiyun #define WM9090_AGC_PWR_ENA_WIDTH 1 /* AGC_PWR_ENA */ 675*4882a593Smuzhiyun #define WM9090_AGC_PWR_AVG 0x1000 /* AGC_PWR_AVG */ 676*4882a593Smuzhiyun #define WM9090_AGC_PWR_AVG_MASK 0x1000 /* AGC_PWR_AVG */ 677*4882a593Smuzhiyun #define WM9090_AGC_PWR_AVG_SHIFT 12 /* AGC_PWR_AVG */ 678*4882a593Smuzhiyun #define WM9090_AGC_PWR_AVG_WIDTH 1 /* AGC_PWR_AVG */ 679*4882a593Smuzhiyun #define WM9090_AGC_PWR_THR_MASK 0x0F00 /* AGC_PWR_THR - [11:8] */ 680*4882a593Smuzhiyun #define WM9090_AGC_PWR_THR_SHIFT 8 /* AGC_PWR_THR - [11:8] */ 681*4882a593Smuzhiyun #define WM9090_AGC_PWR_THR_WIDTH 4 /* AGC_PWR_THR - [11:8] */ 682*4882a593Smuzhiyun #define WM9090_AGC_PWR_ATK_MASK 0x0070 /* AGC_PWR_ATK - [6:4] */ 683*4882a593Smuzhiyun #define WM9090_AGC_PWR_ATK_SHIFT 4 /* AGC_PWR_ATK - [6:4] */ 684*4882a593Smuzhiyun #define WM9090_AGC_PWR_ATK_WIDTH 3 /* AGC_PWR_ATK - [6:4] */ 685*4882a593Smuzhiyun #define WM9090_AGC_PWR_DCY_MASK 0x0007 /* AGC_PWR_DCY - [2:0] */ 686*4882a593Smuzhiyun #define WM9090_AGC_PWR_DCY_SHIFT 0 /* AGC_PWR_DCY - [2:0] */ 687*4882a593Smuzhiyun #define WM9090_AGC_PWR_DCY_WIDTH 3 /* AGC_PWR_DCY - [2:0] */ 688*4882a593Smuzhiyun 689*4882a593Smuzhiyun /* 690*4882a593Smuzhiyun * R100 (0x64) - AGC Control 2 691*4882a593Smuzhiyun */ 692*4882a593Smuzhiyun #define WM9090_AGC_RAMP 0x0100 /* AGC_RAMP */ 693*4882a593Smuzhiyun #define WM9090_AGC_RAMP_MASK 0x0100 /* AGC_RAMP */ 694*4882a593Smuzhiyun #define WM9090_AGC_RAMP_SHIFT 8 /* AGC_RAMP */ 695*4882a593Smuzhiyun #define WM9090_AGC_RAMP_WIDTH 1 /* AGC_RAMP */ 696*4882a593Smuzhiyun #define WM9090_AGC_MINGAIN_MASK 0x003F /* AGC_MINGAIN - [5:0] */ 697*4882a593Smuzhiyun #define WM9090_AGC_MINGAIN_SHIFT 0 /* AGC_MINGAIN - [5:0] */ 698*4882a593Smuzhiyun #define WM9090_AGC_MINGAIN_WIDTH 6 /* AGC_MINGAIN - [5:0] */ 699*4882a593Smuzhiyun 700*4882a593Smuzhiyun #endif 701