xref: /OK3568_Linux_fs/kernel/sound/soc/codecs/wm9090.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * ALSA SoC WM9090 driver
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright 2009-12 Wolfson Microelectronics
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
8*4882a593Smuzhiyun  */
9*4882a593Smuzhiyun 
10*4882a593Smuzhiyun #include <linux/module.h>
11*4882a593Smuzhiyun #include <linux/errno.h>
12*4882a593Smuzhiyun #include <linux/device.h>
13*4882a593Smuzhiyun #include <linux/i2c.h>
14*4882a593Smuzhiyun #include <linux/delay.h>
15*4882a593Smuzhiyun #include <linux/regmap.h>
16*4882a593Smuzhiyun #include <linux/slab.h>
17*4882a593Smuzhiyun #include <sound/initval.h>
18*4882a593Smuzhiyun #include <sound/soc.h>
19*4882a593Smuzhiyun #include <sound/tlv.h>
20*4882a593Smuzhiyun #include <sound/wm9090.h>
21*4882a593Smuzhiyun 
22*4882a593Smuzhiyun #include "wm9090.h"
23*4882a593Smuzhiyun 
24*4882a593Smuzhiyun static const struct reg_default wm9090_reg_defaults[] = {
25*4882a593Smuzhiyun 	{ 1,  0x0006 },     /* R1   - Power Management (1) */
26*4882a593Smuzhiyun 	{ 2,  0x6000 },     /* R2   - Power Management (2) */
27*4882a593Smuzhiyun 	{ 3,  0x0000 },     /* R3   - Power Management (3) */
28*4882a593Smuzhiyun 	{ 6,  0x01C0 },     /* R6   - Clocking 1 */
29*4882a593Smuzhiyun 	{ 22, 0x0003 },     /* R22  - IN1 Line Control */
30*4882a593Smuzhiyun 	{ 23, 0x0003 },     /* R23  - IN2 Line Control */
31*4882a593Smuzhiyun 	{ 24, 0x0083 },     /* R24  - IN1 Line Input A Volume */
32*4882a593Smuzhiyun 	{ 25, 0x0083 },     /* R25  - IN1  Line Input B Volume */
33*4882a593Smuzhiyun 	{ 26, 0x0083 },     /* R26  - IN2 Line Input A Volume */
34*4882a593Smuzhiyun 	{ 27, 0x0083 },     /* R27  - IN2 Line Input B Volume */
35*4882a593Smuzhiyun 	{ 28, 0x002D },     /* R28  - Left Output Volume */
36*4882a593Smuzhiyun 	{ 29, 0x002D },     /* R29  - Right Output Volume */
37*4882a593Smuzhiyun 	{ 34, 0x0100 },     /* R34  - SPKMIXL Attenuation */
38*4882a593Smuzhiyun 	{ 35, 0x0010 },     /* R36  - SPKOUT Mixers */
39*4882a593Smuzhiyun 	{ 37, 0x0140 },     /* R37  - ClassD3 */
40*4882a593Smuzhiyun 	{ 38, 0x0039 },     /* R38  - Speaker Volume Left */
41*4882a593Smuzhiyun 	{ 45, 0x0000 },     /* R45  - Output Mixer1 */
42*4882a593Smuzhiyun 	{ 46, 0x0000 },     /* R46  - Output Mixer2 */
43*4882a593Smuzhiyun 	{ 47, 0x0100 },     /* R47  - Output Mixer3 */
44*4882a593Smuzhiyun 	{ 48, 0x0100 },     /* R48  - Output Mixer4 */
45*4882a593Smuzhiyun 	{ 54, 0x0000 },     /* R54  - Speaker Mixer */
46*4882a593Smuzhiyun 	{ 57, 0x000D },     /* R57  - AntiPOP2 */
47*4882a593Smuzhiyun 	{ 70, 0x0000 },     /* R70  - Write Sequencer 0 */
48*4882a593Smuzhiyun 	{ 71, 0x0000 },     /* R71  - Write Sequencer 1 */
49*4882a593Smuzhiyun 	{ 72, 0x0000 },     /* R72  - Write Sequencer 2 */
50*4882a593Smuzhiyun 	{ 73, 0x0000 },     /* R73  - Write Sequencer 3 */
51*4882a593Smuzhiyun 	{ 74, 0x0000 },     /* R74  - Write Sequencer 4 */
52*4882a593Smuzhiyun 	{ 75, 0x0000 },     /* R75  - Write Sequencer 5 */
53*4882a593Smuzhiyun 	{ 76, 0x1F25 },     /* R76  - Charge Pump 1 */
54*4882a593Smuzhiyun 	{ 85, 0x054A },     /* R85  - DC Servo 1 */
55*4882a593Smuzhiyun 	{ 87, 0x0000 },     /* R87  - DC Servo 3 */
56*4882a593Smuzhiyun 	{ 96, 0x0100 },     /* R96  - Analogue HP 0 */
57*4882a593Smuzhiyun 	{ 98, 0x8640 },     /* R98  - AGC Control 0 */
58*4882a593Smuzhiyun 	{ 99, 0xC000 },     /* R99  - AGC Control 1 */
59*4882a593Smuzhiyun 	{ 100, 0x0200 },     /* R100 - AGC Control 2 */
60*4882a593Smuzhiyun };
61*4882a593Smuzhiyun 
62*4882a593Smuzhiyun /* This struct is used to save the context */
63*4882a593Smuzhiyun struct wm9090_priv {
64*4882a593Smuzhiyun 	struct wm9090_platform_data pdata;
65*4882a593Smuzhiyun 	struct regmap *regmap;
66*4882a593Smuzhiyun };
67*4882a593Smuzhiyun 
wm9090_volatile(struct device * dev,unsigned int reg)68*4882a593Smuzhiyun static bool wm9090_volatile(struct device *dev, unsigned int reg)
69*4882a593Smuzhiyun {
70*4882a593Smuzhiyun 	switch (reg) {
71*4882a593Smuzhiyun 	case WM9090_SOFTWARE_RESET:
72*4882a593Smuzhiyun 	case WM9090_DC_SERVO_0:
73*4882a593Smuzhiyun 	case WM9090_DC_SERVO_READBACK_0:
74*4882a593Smuzhiyun 	case WM9090_DC_SERVO_READBACK_1:
75*4882a593Smuzhiyun 	case WM9090_DC_SERVO_READBACK_2:
76*4882a593Smuzhiyun 		return true;
77*4882a593Smuzhiyun 
78*4882a593Smuzhiyun 	default:
79*4882a593Smuzhiyun 		return false;
80*4882a593Smuzhiyun 	}
81*4882a593Smuzhiyun }
82*4882a593Smuzhiyun 
wm9090_readable(struct device * dev,unsigned int reg)83*4882a593Smuzhiyun static bool wm9090_readable(struct device *dev, unsigned int reg)
84*4882a593Smuzhiyun {
85*4882a593Smuzhiyun 	switch (reg) {
86*4882a593Smuzhiyun 	case WM9090_SOFTWARE_RESET:
87*4882a593Smuzhiyun 	case WM9090_POWER_MANAGEMENT_1:
88*4882a593Smuzhiyun 	case WM9090_POWER_MANAGEMENT_2:
89*4882a593Smuzhiyun 	case WM9090_POWER_MANAGEMENT_3:
90*4882a593Smuzhiyun 	case WM9090_CLOCKING_1:
91*4882a593Smuzhiyun 	case WM9090_IN1_LINE_CONTROL:
92*4882a593Smuzhiyun 	case WM9090_IN2_LINE_CONTROL:
93*4882a593Smuzhiyun 	case WM9090_IN1_LINE_INPUT_A_VOLUME:
94*4882a593Smuzhiyun 	case WM9090_IN1_LINE_INPUT_B_VOLUME:
95*4882a593Smuzhiyun 	case WM9090_IN2_LINE_INPUT_A_VOLUME:
96*4882a593Smuzhiyun 	case WM9090_IN2_LINE_INPUT_B_VOLUME:
97*4882a593Smuzhiyun 	case WM9090_LEFT_OUTPUT_VOLUME:
98*4882a593Smuzhiyun 	case WM9090_RIGHT_OUTPUT_VOLUME:
99*4882a593Smuzhiyun 	case WM9090_SPKMIXL_ATTENUATION:
100*4882a593Smuzhiyun 	case WM9090_SPKOUT_MIXERS:
101*4882a593Smuzhiyun 	case WM9090_CLASSD3:
102*4882a593Smuzhiyun 	case WM9090_SPEAKER_VOLUME_LEFT:
103*4882a593Smuzhiyun 	case WM9090_OUTPUT_MIXER1:
104*4882a593Smuzhiyun 	case WM9090_OUTPUT_MIXER2:
105*4882a593Smuzhiyun 	case WM9090_OUTPUT_MIXER3:
106*4882a593Smuzhiyun 	case WM9090_OUTPUT_MIXER4:
107*4882a593Smuzhiyun 	case WM9090_SPEAKER_MIXER:
108*4882a593Smuzhiyun 	case WM9090_ANTIPOP2:
109*4882a593Smuzhiyun 	case WM9090_WRITE_SEQUENCER_0:
110*4882a593Smuzhiyun 	case WM9090_WRITE_SEQUENCER_1:
111*4882a593Smuzhiyun 	case WM9090_WRITE_SEQUENCER_2:
112*4882a593Smuzhiyun 	case WM9090_WRITE_SEQUENCER_3:
113*4882a593Smuzhiyun 	case WM9090_WRITE_SEQUENCER_4:
114*4882a593Smuzhiyun 	case WM9090_WRITE_SEQUENCER_5:
115*4882a593Smuzhiyun 	case WM9090_CHARGE_PUMP_1:
116*4882a593Smuzhiyun 	case WM9090_DC_SERVO_0:
117*4882a593Smuzhiyun 	case WM9090_DC_SERVO_1:
118*4882a593Smuzhiyun 	case WM9090_DC_SERVO_3:
119*4882a593Smuzhiyun 	case WM9090_DC_SERVO_READBACK_0:
120*4882a593Smuzhiyun 	case WM9090_DC_SERVO_READBACK_1:
121*4882a593Smuzhiyun 	case WM9090_DC_SERVO_READBACK_2:
122*4882a593Smuzhiyun 	case WM9090_ANALOGUE_HP_0:
123*4882a593Smuzhiyun 	case WM9090_AGC_CONTROL_0:
124*4882a593Smuzhiyun 	case WM9090_AGC_CONTROL_1:
125*4882a593Smuzhiyun 	case WM9090_AGC_CONTROL_2:
126*4882a593Smuzhiyun 		return true;
127*4882a593Smuzhiyun 
128*4882a593Smuzhiyun 	default:
129*4882a593Smuzhiyun 		return false;
130*4882a593Smuzhiyun 	}
131*4882a593Smuzhiyun }
132*4882a593Smuzhiyun 
wait_for_dc_servo(struct snd_soc_component * component)133*4882a593Smuzhiyun static void wait_for_dc_servo(struct snd_soc_component *component)
134*4882a593Smuzhiyun {
135*4882a593Smuzhiyun 	unsigned int reg;
136*4882a593Smuzhiyun 	int count = 0;
137*4882a593Smuzhiyun 
138*4882a593Smuzhiyun 	dev_dbg(component->dev, "Waiting for DC servo...\n");
139*4882a593Smuzhiyun 	do {
140*4882a593Smuzhiyun 		count++;
141*4882a593Smuzhiyun 		msleep(1);
142*4882a593Smuzhiyun 		reg = snd_soc_component_read(component, WM9090_DC_SERVO_READBACK_0);
143*4882a593Smuzhiyun 		dev_dbg(component->dev, "DC servo status: %x\n", reg);
144*4882a593Smuzhiyun 	} while ((reg & WM9090_DCS_CAL_COMPLETE_MASK)
145*4882a593Smuzhiyun 		 != WM9090_DCS_CAL_COMPLETE_MASK && count < 1000);
146*4882a593Smuzhiyun 
147*4882a593Smuzhiyun 	if ((reg & WM9090_DCS_CAL_COMPLETE_MASK)
148*4882a593Smuzhiyun 	    != WM9090_DCS_CAL_COMPLETE_MASK)
149*4882a593Smuzhiyun 		dev_err(component->dev, "Timed out waiting for DC Servo\n");
150*4882a593Smuzhiyun }
151*4882a593Smuzhiyun 
152*4882a593Smuzhiyun static const DECLARE_TLV_DB_RANGE(in_tlv,
153*4882a593Smuzhiyun 	0, 0, TLV_DB_SCALE_ITEM(-600, 0, 0),
154*4882a593Smuzhiyun 	1, 3, TLV_DB_SCALE_ITEM(-350, 350, 0),
155*4882a593Smuzhiyun 	4, 6, TLV_DB_SCALE_ITEM(600, 600, 0)
156*4882a593Smuzhiyun );
157*4882a593Smuzhiyun static const DECLARE_TLV_DB_RANGE(mix_tlv,
158*4882a593Smuzhiyun 	0, 2, TLV_DB_SCALE_ITEM(-1200, 300, 0),
159*4882a593Smuzhiyun 	3, 3, TLV_DB_SCALE_ITEM(0, 0, 0)
160*4882a593Smuzhiyun );
161*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
162*4882a593Smuzhiyun static const DECLARE_TLV_DB_RANGE(spkboost_tlv,
163*4882a593Smuzhiyun 	0, 6, TLV_DB_SCALE_ITEM(0, 150, 0),
164*4882a593Smuzhiyun 	7, 7, TLV_DB_SCALE_ITEM(1200, 0, 0)
165*4882a593Smuzhiyun );
166*4882a593Smuzhiyun 
167*4882a593Smuzhiyun static const struct snd_kcontrol_new wm9090_controls[] = {
168*4882a593Smuzhiyun SOC_SINGLE_TLV("IN1A Volume", WM9090_IN1_LINE_INPUT_A_VOLUME, 0, 6, 0,
169*4882a593Smuzhiyun 	       in_tlv),
170*4882a593Smuzhiyun SOC_SINGLE("IN1A Switch", WM9090_IN1_LINE_INPUT_A_VOLUME, 7, 1, 1),
171*4882a593Smuzhiyun SOC_SINGLE("IN1A ZC Switch", WM9090_IN1_LINE_INPUT_A_VOLUME, 6, 1, 0),
172*4882a593Smuzhiyun 
173*4882a593Smuzhiyun SOC_SINGLE_TLV("IN2A Volume", WM9090_IN2_LINE_INPUT_A_VOLUME, 0, 6, 0,
174*4882a593Smuzhiyun 	       in_tlv),
175*4882a593Smuzhiyun SOC_SINGLE("IN2A Switch", WM9090_IN2_LINE_INPUT_A_VOLUME, 7, 1, 1),
176*4882a593Smuzhiyun SOC_SINGLE("IN2A ZC Switch", WM9090_IN2_LINE_INPUT_A_VOLUME, 6, 1, 0),
177*4882a593Smuzhiyun 
178*4882a593Smuzhiyun SOC_SINGLE("MIXOUTL Switch", WM9090_OUTPUT_MIXER3, 8, 1, 1),
179*4882a593Smuzhiyun SOC_SINGLE_TLV("MIXOUTL IN1A Volume", WM9090_OUTPUT_MIXER3, 6, 3, 1,
180*4882a593Smuzhiyun 	       mix_tlv),
181*4882a593Smuzhiyun SOC_SINGLE_TLV("MIXOUTL IN2A Volume", WM9090_OUTPUT_MIXER3, 2, 3, 1,
182*4882a593Smuzhiyun 	       mix_tlv),
183*4882a593Smuzhiyun 
184*4882a593Smuzhiyun SOC_SINGLE("MIXOUTR Switch", WM9090_OUTPUT_MIXER4, 8, 1, 1),
185*4882a593Smuzhiyun SOC_SINGLE_TLV("MIXOUTR IN1A Volume", WM9090_OUTPUT_MIXER4, 6, 3, 1,
186*4882a593Smuzhiyun 	       mix_tlv),
187*4882a593Smuzhiyun SOC_SINGLE_TLV("MIXOUTR IN2A Volume", WM9090_OUTPUT_MIXER4, 2, 3, 1,
188*4882a593Smuzhiyun 	       mix_tlv),
189*4882a593Smuzhiyun 
190*4882a593Smuzhiyun SOC_SINGLE("SPKMIX Switch", WM9090_SPKMIXL_ATTENUATION, 8, 1, 1),
191*4882a593Smuzhiyun SOC_SINGLE_TLV("SPKMIX IN1A Volume", WM9090_SPKMIXL_ATTENUATION, 6, 3, 1,
192*4882a593Smuzhiyun 	       mix_tlv),
193*4882a593Smuzhiyun SOC_SINGLE_TLV("SPKMIX IN2A Volume", WM9090_SPKMIXL_ATTENUATION, 2, 3, 1,
194*4882a593Smuzhiyun 	       mix_tlv),
195*4882a593Smuzhiyun 
196*4882a593Smuzhiyun SOC_DOUBLE_R_TLV("Headphone Volume", WM9090_LEFT_OUTPUT_VOLUME,
197*4882a593Smuzhiyun 		 WM9090_RIGHT_OUTPUT_VOLUME, 0, 63, 0, out_tlv),
198*4882a593Smuzhiyun SOC_DOUBLE_R("Headphone Switch", WM9090_LEFT_OUTPUT_VOLUME,
199*4882a593Smuzhiyun 	     WM9090_RIGHT_OUTPUT_VOLUME, 6, 1, 1),
200*4882a593Smuzhiyun SOC_DOUBLE_R("Headphone ZC Switch", WM9090_LEFT_OUTPUT_VOLUME,
201*4882a593Smuzhiyun 	     WM9090_RIGHT_OUTPUT_VOLUME, 7, 1, 0),
202*4882a593Smuzhiyun 
203*4882a593Smuzhiyun SOC_SINGLE_TLV("Speaker Volume", WM9090_SPEAKER_VOLUME_LEFT, 0, 63, 0,
204*4882a593Smuzhiyun 	       out_tlv),
205*4882a593Smuzhiyun SOC_SINGLE("Speaker Switch", WM9090_SPEAKER_VOLUME_LEFT, 6, 1, 1),
206*4882a593Smuzhiyun SOC_SINGLE("Speaker ZC Switch", WM9090_SPEAKER_VOLUME_LEFT, 7, 1, 0),
207*4882a593Smuzhiyun SOC_SINGLE_TLV("Speaker Boost Volume", WM9090_CLASSD3, 3, 7, 0, spkboost_tlv),
208*4882a593Smuzhiyun };
209*4882a593Smuzhiyun 
210*4882a593Smuzhiyun static const struct snd_kcontrol_new wm9090_in1_se_controls[] = {
211*4882a593Smuzhiyun SOC_SINGLE_TLV("IN1B Volume", WM9090_IN1_LINE_INPUT_B_VOLUME, 0, 6, 0,
212*4882a593Smuzhiyun 	       in_tlv),
213*4882a593Smuzhiyun SOC_SINGLE("IN1B Switch", WM9090_IN1_LINE_INPUT_B_VOLUME, 7, 1, 1),
214*4882a593Smuzhiyun SOC_SINGLE("IN1B ZC Switch", WM9090_IN1_LINE_INPUT_B_VOLUME, 6, 1, 0),
215*4882a593Smuzhiyun 
216*4882a593Smuzhiyun SOC_SINGLE_TLV("SPKMIX IN1B Volume", WM9090_SPKMIXL_ATTENUATION, 4, 3, 1,
217*4882a593Smuzhiyun 	       mix_tlv),
218*4882a593Smuzhiyun SOC_SINGLE_TLV("MIXOUTL IN1B Volume", WM9090_OUTPUT_MIXER3, 4, 3, 1,
219*4882a593Smuzhiyun 	       mix_tlv),
220*4882a593Smuzhiyun SOC_SINGLE_TLV("MIXOUTR IN1B Volume", WM9090_OUTPUT_MIXER4, 4, 3, 1,
221*4882a593Smuzhiyun 	       mix_tlv),
222*4882a593Smuzhiyun };
223*4882a593Smuzhiyun 
224*4882a593Smuzhiyun static const struct snd_kcontrol_new wm9090_in2_se_controls[] = {
225*4882a593Smuzhiyun SOC_SINGLE_TLV("IN2B Volume", WM9090_IN2_LINE_INPUT_B_VOLUME, 0, 6, 0,
226*4882a593Smuzhiyun 	       in_tlv),
227*4882a593Smuzhiyun SOC_SINGLE("IN2B Switch", WM9090_IN2_LINE_INPUT_B_VOLUME, 7, 1, 1),
228*4882a593Smuzhiyun SOC_SINGLE("IN2B ZC Switch", WM9090_IN2_LINE_INPUT_B_VOLUME, 6, 1, 0),
229*4882a593Smuzhiyun 
230*4882a593Smuzhiyun SOC_SINGLE_TLV("SPKMIX IN2B Volume", WM9090_SPKMIXL_ATTENUATION, 0, 3, 1,
231*4882a593Smuzhiyun 	       mix_tlv),
232*4882a593Smuzhiyun SOC_SINGLE_TLV("MIXOUTL IN2B Volume", WM9090_OUTPUT_MIXER3, 0, 3, 1,
233*4882a593Smuzhiyun 	       mix_tlv),
234*4882a593Smuzhiyun SOC_SINGLE_TLV("MIXOUTR IN2B Volume", WM9090_OUTPUT_MIXER4, 0, 3, 1,
235*4882a593Smuzhiyun 	       mix_tlv),
236*4882a593Smuzhiyun };
237*4882a593Smuzhiyun 
hp_ev(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)238*4882a593Smuzhiyun static int hp_ev(struct snd_soc_dapm_widget *w,
239*4882a593Smuzhiyun 		 struct snd_kcontrol *kcontrol, int event)
240*4882a593Smuzhiyun {
241*4882a593Smuzhiyun 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
242*4882a593Smuzhiyun 	unsigned int reg = snd_soc_component_read(component, WM9090_ANALOGUE_HP_0);
243*4882a593Smuzhiyun 
244*4882a593Smuzhiyun 	switch (event) {
245*4882a593Smuzhiyun 	case SND_SOC_DAPM_POST_PMU:
246*4882a593Smuzhiyun 		snd_soc_component_update_bits(component, WM9090_CHARGE_PUMP_1,
247*4882a593Smuzhiyun 				    WM9090_CP_ENA, WM9090_CP_ENA);
248*4882a593Smuzhiyun 
249*4882a593Smuzhiyun 		msleep(5);
250*4882a593Smuzhiyun 
251*4882a593Smuzhiyun 		snd_soc_component_update_bits(component, WM9090_POWER_MANAGEMENT_1,
252*4882a593Smuzhiyun 				    WM9090_HPOUT1L_ENA | WM9090_HPOUT1R_ENA,
253*4882a593Smuzhiyun 				    WM9090_HPOUT1L_ENA | WM9090_HPOUT1R_ENA);
254*4882a593Smuzhiyun 
255*4882a593Smuzhiyun 		reg |= WM9090_HPOUT1L_DLY | WM9090_HPOUT1R_DLY;
256*4882a593Smuzhiyun 		snd_soc_component_write(component, WM9090_ANALOGUE_HP_0, reg);
257*4882a593Smuzhiyun 
258*4882a593Smuzhiyun 		/* Start the DC servo.  We don't currently use the
259*4882a593Smuzhiyun 		 * ability to save the state since we don't have full
260*4882a593Smuzhiyun 		 * control of the analogue paths and they can change
261*4882a593Smuzhiyun 		 * DC offsets; see the WM8904 driver for an example of
262*4882a593Smuzhiyun 		 * doing so.
263*4882a593Smuzhiyun 		 */
264*4882a593Smuzhiyun 		snd_soc_component_write(component, WM9090_DC_SERVO_0,
265*4882a593Smuzhiyun 			      WM9090_DCS_ENA_CHAN_0 |
266*4882a593Smuzhiyun 			      WM9090_DCS_ENA_CHAN_1 |
267*4882a593Smuzhiyun 			      WM9090_DCS_TRIG_STARTUP_1 |
268*4882a593Smuzhiyun 			      WM9090_DCS_TRIG_STARTUP_0);
269*4882a593Smuzhiyun 		wait_for_dc_servo(component);
270*4882a593Smuzhiyun 
271*4882a593Smuzhiyun 		reg |= WM9090_HPOUT1R_OUTP | WM9090_HPOUT1R_RMV_SHORT |
272*4882a593Smuzhiyun 			WM9090_HPOUT1L_OUTP | WM9090_HPOUT1L_RMV_SHORT;
273*4882a593Smuzhiyun 		snd_soc_component_write(component, WM9090_ANALOGUE_HP_0, reg);
274*4882a593Smuzhiyun 		break;
275*4882a593Smuzhiyun 
276*4882a593Smuzhiyun 	case SND_SOC_DAPM_PRE_PMD:
277*4882a593Smuzhiyun 		reg &= ~(WM9090_HPOUT1L_RMV_SHORT |
278*4882a593Smuzhiyun 			 WM9090_HPOUT1L_DLY |
279*4882a593Smuzhiyun 			 WM9090_HPOUT1L_OUTP |
280*4882a593Smuzhiyun 			 WM9090_HPOUT1R_RMV_SHORT |
281*4882a593Smuzhiyun 			 WM9090_HPOUT1R_DLY |
282*4882a593Smuzhiyun 			 WM9090_HPOUT1R_OUTP);
283*4882a593Smuzhiyun 
284*4882a593Smuzhiyun 		snd_soc_component_write(component, WM9090_ANALOGUE_HP_0, reg);
285*4882a593Smuzhiyun 
286*4882a593Smuzhiyun 		snd_soc_component_write(component, WM9090_DC_SERVO_0, 0);
287*4882a593Smuzhiyun 
288*4882a593Smuzhiyun 		snd_soc_component_update_bits(component, WM9090_POWER_MANAGEMENT_1,
289*4882a593Smuzhiyun 				    WM9090_HPOUT1L_ENA | WM9090_HPOUT1R_ENA,
290*4882a593Smuzhiyun 				    0);
291*4882a593Smuzhiyun 
292*4882a593Smuzhiyun 		snd_soc_component_update_bits(component, WM9090_CHARGE_PUMP_1,
293*4882a593Smuzhiyun 				    WM9090_CP_ENA, 0);
294*4882a593Smuzhiyun 		break;
295*4882a593Smuzhiyun 	}
296*4882a593Smuzhiyun 
297*4882a593Smuzhiyun 	return 0;
298*4882a593Smuzhiyun }
299*4882a593Smuzhiyun 
300*4882a593Smuzhiyun static const struct snd_kcontrol_new spkmix[] = {
301*4882a593Smuzhiyun SOC_DAPM_SINGLE("IN1A Switch", WM9090_SPEAKER_MIXER, 6, 1, 0),
302*4882a593Smuzhiyun SOC_DAPM_SINGLE("IN1B Switch", WM9090_SPEAKER_MIXER, 4, 1, 0),
303*4882a593Smuzhiyun SOC_DAPM_SINGLE("IN2A Switch", WM9090_SPEAKER_MIXER, 2, 1, 0),
304*4882a593Smuzhiyun SOC_DAPM_SINGLE("IN2B Switch", WM9090_SPEAKER_MIXER, 0, 1, 0),
305*4882a593Smuzhiyun };
306*4882a593Smuzhiyun 
307*4882a593Smuzhiyun static const struct snd_kcontrol_new spkout[] = {
308*4882a593Smuzhiyun SOC_DAPM_SINGLE("Mixer Switch", WM9090_SPKOUT_MIXERS, 4, 1, 0),
309*4882a593Smuzhiyun };
310*4882a593Smuzhiyun 
311*4882a593Smuzhiyun static const struct snd_kcontrol_new mixoutl[] = {
312*4882a593Smuzhiyun SOC_DAPM_SINGLE("IN1A Switch", WM9090_OUTPUT_MIXER1, 6, 1, 0),
313*4882a593Smuzhiyun SOC_DAPM_SINGLE("IN1B Switch", WM9090_OUTPUT_MIXER1, 4, 1, 0),
314*4882a593Smuzhiyun SOC_DAPM_SINGLE("IN2A Switch", WM9090_OUTPUT_MIXER1, 2, 1, 0),
315*4882a593Smuzhiyun SOC_DAPM_SINGLE("IN2B Switch", WM9090_OUTPUT_MIXER1, 0, 1, 0),
316*4882a593Smuzhiyun };
317*4882a593Smuzhiyun 
318*4882a593Smuzhiyun static const struct snd_kcontrol_new mixoutr[] = {
319*4882a593Smuzhiyun SOC_DAPM_SINGLE("IN1A Switch", WM9090_OUTPUT_MIXER2, 6, 1, 0),
320*4882a593Smuzhiyun SOC_DAPM_SINGLE("IN1B Switch", WM9090_OUTPUT_MIXER2, 4, 1, 0),
321*4882a593Smuzhiyun SOC_DAPM_SINGLE("IN2A Switch", WM9090_OUTPUT_MIXER2, 2, 1, 0),
322*4882a593Smuzhiyun SOC_DAPM_SINGLE("IN2B Switch", WM9090_OUTPUT_MIXER2, 0, 1, 0),
323*4882a593Smuzhiyun };
324*4882a593Smuzhiyun 
325*4882a593Smuzhiyun static const struct snd_soc_dapm_widget wm9090_dapm_widgets[] = {
326*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("IN1+"),
327*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("IN1-"),
328*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("IN2+"),
329*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("IN2-"),
330*4882a593Smuzhiyun 
331*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("OSC", WM9090_POWER_MANAGEMENT_1, 3, 0, NULL, 0),
332*4882a593Smuzhiyun 
333*4882a593Smuzhiyun SND_SOC_DAPM_PGA("IN1A PGA", WM9090_POWER_MANAGEMENT_2, 7, 0, NULL, 0),
334*4882a593Smuzhiyun SND_SOC_DAPM_PGA("IN1B PGA", WM9090_POWER_MANAGEMENT_2, 6, 0, NULL, 0),
335*4882a593Smuzhiyun SND_SOC_DAPM_PGA("IN2A PGA", WM9090_POWER_MANAGEMENT_2, 5, 0, NULL, 0),
336*4882a593Smuzhiyun SND_SOC_DAPM_PGA("IN2B PGA", WM9090_POWER_MANAGEMENT_2, 4, 0, NULL, 0),
337*4882a593Smuzhiyun 
338*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("SPKMIX", WM9090_POWER_MANAGEMENT_3, 3, 0,
339*4882a593Smuzhiyun 		   spkmix, ARRAY_SIZE(spkmix)),
340*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("MIXOUTL", WM9090_POWER_MANAGEMENT_3, 5, 0,
341*4882a593Smuzhiyun 		   mixoutl, ARRAY_SIZE(mixoutl)),
342*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("MIXOUTR", WM9090_POWER_MANAGEMENT_3, 4, 0,
343*4882a593Smuzhiyun 		   mixoutr, ARRAY_SIZE(mixoutr)),
344*4882a593Smuzhiyun 
345*4882a593Smuzhiyun SND_SOC_DAPM_PGA_E("HP PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
346*4882a593Smuzhiyun 		   hp_ev, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
347*4882a593Smuzhiyun 
348*4882a593Smuzhiyun SND_SOC_DAPM_PGA("SPKPGA", WM9090_POWER_MANAGEMENT_3, 8, 0, NULL, 0),
349*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("SPKOUT", WM9090_POWER_MANAGEMENT_1, 12, 0,
350*4882a593Smuzhiyun 		   spkout, ARRAY_SIZE(spkout)),
351*4882a593Smuzhiyun 
352*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("HPR"),
353*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("HPL"),
354*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("Speaker"),
355*4882a593Smuzhiyun };
356*4882a593Smuzhiyun 
357*4882a593Smuzhiyun static const struct snd_soc_dapm_route audio_map[] = {
358*4882a593Smuzhiyun 	{ "IN1A PGA", NULL, "IN1+" },
359*4882a593Smuzhiyun 	{ "IN2A PGA", NULL, "IN2+" },
360*4882a593Smuzhiyun 
361*4882a593Smuzhiyun 	{ "SPKMIX", "IN1A Switch", "IN1A PGA" },
362*4882a593Smuzhiyun 	{ "SPKMIX", "IN2A Switch", "IN2A PGA" },
363*4882a593Smuzhiyun 
364*4882a593Smuzhiyun 	{ "MIXOUTL", "IN1A Switch", "IN1A PGA" },
365*4882a593Smuzhiyun 	{ "MIXOUTL", "IN2A Switch", "IN2A PGA" },
366*4882a593Smuzhiyun 
367*4882a593Smuzhiyun 	{ "MIXOUTR", "IN1A Switch", "IN1A PGA" },
368*4882a593Smuzhiyun 	{ "MIXOUTR", "IN2A Switch", "IN2A PGA" },
369*4882a593Smuzhiyun 
370*4882a593Smuzhiyun 	{ "HP PGA", NULL, "OSC" },
371*4882a593Smuzhiyun 	{ "HP PGA", NULL, "MIXOUTL" },
372*4882a593Smuzhiyun 	{ "HP PGA", NULL, "MIXOUTR" },
373*4882a593Smuzhiyun 
374*4882a593Smuzhiyun 	{ "HPL", NULL, "HP PGA" },
375*4882a593Smuzhiyun 	{ "HPR", NULL, "HP PGA" },
376*4882a593Smuzhiyun 
377*4882a593Smuzhiyun 	{ "SPKPGA", NULL, "OSC" },
378*4882a593Smuzhiyun 	{ "SPKPGA", NULL, "SPKMIX" },
379*4882a593Smuzhiyun 
380*4882a593Smuzhiyun 	{ "SPKOUT", "Mixer Switch", "SPKPGA" },
381*4882a593Smuzhiyun 
382*4882a593Smuzhiyun 	{ "Speaker", NULL, "SPKOUT" },
383*4882a593Smuzhiyun };
384*4882a593Smuzhiyun 
385*4882a593Smuzhiyun static const struct snd_soc_dapm_route audio_map_in1_se[] = {
386*4882a593Smuzhiyun 	{ "IN1B PGA", NULL, "IN1-" },
387*4882a593Smuzhiyun 
388*4882a593Smuzhiyun 	{ "SPKMIX", "IN1B Switch", "IN1B PGA" },
389*4882a593Smuzhiyun 	{ "MIXOUTL", "IN1B Switch", "IN1B PGA" },
390*4882a593Smuzhiyun 	{ "MIXOUTR", "IN1B Switch", "IN1B PGA" },
391*4882a593Smuzhiyun };
392*4882a593Smuzhiyun 
393*4882a593Smuzhiyun static const struct snd_soc_dapm_route audio_map_in1_diff[] = {
394*4882a593Smuzhiyun 	{ "IN1A PGA", NULL, "IN1-" },
395*4882a593Smuzhiyun };
396*4882a593Smuzhiyun 
397*4882a593Smuzhiyun static const struct snd_soc_dapm_route audio_map_in2_se[] = {
398*4882a593Smuzhiyun 	{ "IN2B PGA", NULL, "IN2-" },
399*4882a593Smuzhiyun 
400*4882a593Smuzhiyun 	{ "SPKMIX", "IN2B Switch", "IN2B PGA" },
401*4882a593Smuzhiyun 	{ "MIXOUTL", "IN2B Switch", "IN2B PGA" },
402*4882a593Smuzhiyun 	{ "MIXOUTR", "IN2B Switch", "IN2B PGA" },
403*4882a593Smuzhiyun };
404*4882a593Smuzhiyun 
405*4882a593Smuzhiyun static const struct snd_soc_dapm_route audio_map_in2_diff[] = {
406*4882a593Smuzhiyun 	{ "IN2A PGA", NULL, "IN2-" },
407*4882a593Smuzhiyun };
408*4882a593Smuzhiyun 
wm9090_add_controls(struct snd_soc_component * component)409*4882a593Smuzhiyun static int wm9090_add_controls(struct snd_soc_component *component)
410*4882a593Smuzhiyun {
411*4882a593Smuzhiyun 	struct wm9090_priv *wm9090 = snd_soc_component_get_drvdata(component);
412*4882a593Smuzhiyun 	struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
413*4882a593Smuzhiyun 	int i;
414*4882a593Smuzhiyun 
415*4882a593Smuzhiyun 	snd_soc_dapm_new_controls(dapm, wm9090_dapm_widgets,
416*4882a593Smuzhiyun 				  ARRAY_SIZE(wm9090_dapm_widgets));
417*4882a593Smuzhiyun 
418*4882a593Smuzhiyun 	snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map));
419*4882a593Smuzhiyun 
420*4882a593Smuzhiyun 	snd_soc_add_component_controls(component, wm9090_controls,
421*4882a593Smuzhiyun 			     ARRAY_SIZE(wm9090_controls));
422*4882a593Smuzhiyun 
423*4882a593Smuzhiyun 	if (wm9090->pdata.lin1_diff) {
424*4882a593Smuzhiyun 		snd_soc_dapm_add_routes(dapm, audio_map_in1_diff,
425*4882a593Smuzhiyun 					ARRAY_SIZE(audio_map_in1_diff));
426*4882a593Smuzhiyun 	} else {
427*4882a593Smuzhiyun 		snd_soc_dapm_add_routes(dapm, audio_map_in1_se,
428*4882a593Smuzhiyun 					ARRAY_SIZE(audio_map_in1_se));
429*4882a593Smuzhiyun 		snd_soc_add_component_controls(component, wm9090_in1_se_controls,
430*4882a593Smuzhiyun 				     ARRAY_SIZE(wm9090_in1_se_controls));
431*4882a593Smuzhiyun 	}
432*4882a593Smuzhiyun 
433*4882a593Smuzhiyun 	if (wm9090->pdata.lin2_diff) {
434*4882a593Smuzhiyun 		snd_soc_dapm_add_routes(dapm, audio_map_in2_diff,
435*4882a593Smuzhiyun 					ARRAY_SIZE(audio_map_in2_diff));
436*4882a593Smuzhiyun 	} else {
437*4882a593Smuzhiyun 		snd_soc_dapm_add_routes(dapm, audio_map_in2_se,
438*4882a593Smuzhiyun 					ARRAY_SIZE(audio_map_in2_se));
439*4882a593Smuzhiyun 		snd_soc_add_component_controls(component, wm9090_in2_se_controls,
440*4882a593Smuzhiyun 				     ARRAY_SIZE(wm9090_in2_se_controls));
441*4882a593Smuzhiyun 	}
442*4882a593Smuzhiyun 
443*4882a593Smuzhiyun 	if (wm9090->pdata.agc_ena) {
444*4882a593Smuzhiyun 		for (i = 0; i < ARRAY_SIZE(wm9090->pdata.agc); i++)
445*4882a593Smuzhiyun 			snd_soc_component_write(component, WM9090_AGC_CONTROL_0 + i,
446*4882a593Smuzhiyun 				      wm9090->pdata.agc[i]);
447*4882a593Smuzhiyun 		snd_soc_component_update_bits(component, WM9090_POWER_MANAGEMENT_3,
448*4882a593Smuzhiyun 				    WM9090_AGC_ENA, WM9090_AGC_ENA);
449*4882a593Smuzhiyun 	} else {
450*4882a593Smuzhiyun 		snd_soc_component_update_bits(component, WM9090_POWER_MANAGEMENT_3,
451*4882a593Smuzhiyun 				    WM9090_AGC_ENA, 0);
452*4882a593Smuzhiyun 	}
453*4882a593Smuzhiyun 
454*4882a593Smuzhiyun 	return 0;
455*4882a593Smuzhiyun 
456*4882a593Smuzhiyun }
457*4882a593Smuzhiyun 
458*4882a593Smuzhiyun /*
459*4882a593Smuzhiyun  * The machine driver should call this from their set_bias_level; if there
460*4882a593Smuzhiyun  * isn't one then this can just be set as the set_bias_level function.
461*4882a593Smuzhiyun  */
wm9090_set_bias_level(struct snd_soc_component * component,enum snd_soc_bias_level level)462*4882a593Smuzhiyun static int wm9090_set_bias_level(struct snd_soc_component *component,
463*4882a593Smuzhiyun 				 enum snd_soc_bias_level level)
464*4882a593Smuzhiyun {
465*4882a593Smuzhiyun 	struct wm9090_priv *wm9090 = snd_soc_component_get_drvdata(component);
466*4882a593Smuzhiyun 
467*4882a593Smuzhiyun 	switch (level) {
468*4882a593Smuzhiyun 	case SND_SOC_BIAS_ON:
469*4882a593Smuzhiyun 		break;
470*4882a593Smuzhiyun 
471*4882a593Smuzhiyun 	case SND_SOC_BIAS_PREPARE:
472*4882a593Smuzhiyun 		snd_soc_component_update_bits(component, WM9090_ANTIPOP2, WM9090_VMID_ENA,
473*4882a593Smuzhiyun 				    WM9090_VMID_ENA);
474*4882a593Smuzhiyun 		snd_soc_component_update_bits(component, WM9090_POWER_MANAGEMENT_1,
475*4882a593Smuzhiyun 				    WM9090_BIAS_ENA |
476*4882a593Smuzhiyun 				    WM9090_VMID_RES_MASK,
477*4882a593Smuzhiyun 				    WM9090_BIAS_ENA |
478*4882a593Smuzhiyun 				    1 << WM9090_VMID_RES_SHIFT);
479*4882a593Smuzhiyun 		msleep(1);  /* Probably an overestimate */
480*4882a593Smuzhiyun 		break;
481*4882a593Smuzhiyun 
482*4882a593Smuzhiyun 	case SND_SOC_BIAS_STANDBY:
483*4882a593Smuzhiyun 		if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
484*4882a593Smuzhiyun 			/* Restore the register cache */
485*4882a593Smuzhiyun 			regcache_sync(wm9090->regmap);
486*4882a593Smuzhiyun 		}
487*4882a593Smuzhiyun 
488*4882a593Smuzhiyun 		/* We keep VMID off during standby since the combination of
489*4882a593Smuzhiyun 		 * ground referenced outputs and class D speaker mean that
490*4882a593Smuzhiyun 		 * latency is not an issue.
491*4882a593Smuzhiyun 		 */
492*4882a593Smuzhiyun 		snd_soc_component_update_bits(component, WM9090_POWER_MANAGEMENT_1,
493*4882a593Smuzhiyun 				    WM9090_BIAS_ENA | WM9090_VMID_RES_MASK, 0);
494*4882a593Smuzhiyun 		snd_soc_component_update_bits(component, WM9090_ANTIPOP2,
495*4882a593Smuzhiyun 				    WM9090_VMID_ENA, 0);
496*4882a593Smuzhiyun 		break;
497*4882a593Smuzhiyun 
498*4882a593Smuzhiyun 	case SND_SOC_BIAS_OFF:
499*4882a593Smuzhiyun 		break;
500*4882a593Smuzhiyun 	}
501*4882a593Smuzhiyun 
502*4882a593Smuzhiyun 	return 0;
503*4882a593Smuzhiyun }
504*4882a593Smuzhiyun 
wm9090_probe(struct snd_soc_component * component)505*4882a593Smuzhiyun static int wm9090_probe(struct snd_soc_component *component)
506*4882a593Smuzhiyun {
507*4882a593Smuzhiyun 	/* Configure some defaults; they will be written out when we
508*4882a593Smuzhiyun 	 * bring the bias up.
509*4882a593Smuzhiyun 	 */
510*4882a593Smuzhiyun 	snd_soc_component_update_bits(component, WM9090_IN1_LINE_INPUT_A_VOLUME,
511*4882a593Smuzhiyun 			    WM9090_IN1_VU | WM9090_IN1A_ZC,
512*4882a593Smuzhiyun 			    WM9090_IN1_VU | WM9090_IN1A_ZC);
513*4882a593Smuzhiyun 	snd_soc_component_update_bits(component, WM9090_IN1_LINE_INPUT_B_VOLUME,
514*4882a593Smuzhiyun 			    WM9090_IN1_VU | WM9090_IN1B_ZC,
515*4882a593Smuzhiyun 			    WM9090_IN1_VU | WM9090_IN1B_ZC);
516*4882a593Smuzhiyun 	snd_soc_component_update_bits(component, WM9090_IN2_LINE_INPUT_A_VOLUME,
517*4882a593Smuzhiyun 			    WM9090_IN2_VU | WM9090_IN2A_ZC,
518*4882a593Smuzhiyun 			    WM9090_IN2_VU | WM9090_IN2A_ZC);
519*4882a593Smuzhiyun 	snd_soc_component_update_bits(component, WM9090_IN2_LINE_INPUT_B_VOLUME,
520*4882a593Smuzhiyun 			    WM9090_IN2_VU | WM9090_IN2B_ZC,
521*4882a593Smuzhiyun 			    WM9090_IN2_VU | WM9090_IN2B_ZC);
522*4882a593Smuzhiyun 	snd_soc_component_update_bits(component, WM9090_SPEAKER_VOLUME_LEFT,
523*4882a593Smuzhiyun 			    WM9090_SPKOUT_VU | WM9090_SPKOUTL_ZC,
524*4882a593Smuzhiyun 			    WM9090_SPKOUT_VU | WM9090_SPKOUTL_ZC);
525*4882a593Smuzhiyun 	snd_soc_component_update_bits(component, WM9090_LEFT_OUTPUT_VOLUME,
526*4882a593Smuzhiyun 			    WM9090_HPOUT1_VU | WM9090_HPOUT1L_ZC,
527*4882a593Smuzhiyun 			    WM9090_HPOUT1_VU | WM9090_HPOUT1L_ZC);
528*4882a593Smuzhiyun 	snd_soc_component_update_bits(component, WM9090_RIGHT_OUTPUT_VOLUME,
529*4882a593Smuzhiyun 			    WM9090_HPOUT1_VU | WM9090_HPOUT1R_ZC,
530*4882a593Smuzhiyun 			    WM9090_HPOUT1_VU | WM9090_HPOUT1R_ZC);
531*4882a593Smuzhiyun 
532*4882a593Smuzhiyun 	snd_soc_component_update_bits(component, WM9090_CLOCKING_1,
533*4882a593Smuzhiyun 			    WM9090_TOCLK_ENA, WM9090_TOCLK_ENA);
534*4882a593Smuzhiyun 
535*4882a593Smuzhiyun 	wm9090_add_controls(component);
536*4882a593Smuzhiyun 
537*4882a593Smuzhiyun 	return 0;
538*4882a593Smuzhiyun }
539*4882a593Smuzhiyun 
540*4882a593Smuzhiyun static const struct snd_soc_component_driver soc_component_dev_wm9090 = {
541*4882a593Smuzhiyun 	.probe			= wm9090_probe,
542*4882a593Smuzhiyun 	.set_bias_level		= wm9090_set_bias_level,
543*4882a593Smuzhiyun 	.suspend_bias_off	= 1,
544*4882a593Smuzhiyun 	.idle_bias_on		= 1,
545*4882a593Smuzhiyun 	.use_pmdown_time	= 1,
546*4882a593Smuzhiyun 	.endianness		= 1,
547*4882a593Smuzhiyun 	.non_legacy_dai_naming	= 1,
548*4882a593Smuzhiyun };
549*4882a593Smuzhiyun 
550*4882a593Smuzhiyun static const struct regmap_config wm9090_regmap = {
551*4882a593Smuzhiyun 	.reg_bits = 8,
552*4882a593Smuzhiyun 	.val_bits = 16,
553*4882a593Smuzhiyun 
554*4882a593Smuzhiyun 	.max_register = WM9090_MAX_REGISTER,
555*4882a593Smuzhiyun 	.volatile_reg = wm9090_volatile,
556*4882a593Smuzhiyun 	.readable_reg = wm9090_readable,
557*4882a593Smuzhiyun 
558*4882a593Smuzhiyun 	.cache_type = REGCACHE_RBTREE,
559*4882a593Smuzhiyun 	.reg_defaults = wm9090_reg_defaults,
560*4882a593Smuzhiyun 	.num_reg_defaults = ARRAY_SIZE(wm9090_reg_defaults),
561*4882a593Smuzhiyun };
562*4882a593Smuzhiyun 
563*4882a593Smuzhiyun 
wm9090_i2c_probe(struct i2c_client * i2c,const struct i2c_device_id * id)564*4882a593Smuzhiyun static int wm9090_i2c_probe(struct i2c_client *i2c,
565*4882a593Smuzhiyun 			    const struct i2c_device_id *id)
566*4882a593Smuzhiyun {
567*4882a593Smuzhiyun 	struct wm9090_priv *wm9090;
568*4882a593Smuzhiyun 	unsigned int reg;
569*4882a593Smuzhiyun 	int ret;
570*4882a593Smuzhiyun 
571*4882a593Smuzhiyun 	wm9090 = devm_kzalloc(&i2c->dev, sizeof(*wm9090), GFP_KERNEL);
572*4882a593Smuzhiyun 	if (!wm9090)
573*4882a593Smuzhiyun 		return -ENOMEM;
574*4882a593Smuzhiyun 
575*4882a593Smuzhiyun 	wm9090->regmap = devm_regmap_init_i2c(i2c, &wm9090_regmap);
576*4882a593Smuzhiyun 	if (IS_ERR(wm9090->regmap)) {
577*4882a593Smuzhiyun 		ret = PTR_ERR(wm9090->regmap);
578*4882a593Smuzhiyun 		dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret);
579*4882a593Smuzhiyun 		return ret;
580*4882a593Smuzhiyun 	}
581*4882a593Smuzhiyun 
582*4882a593Smuzhiyun 	ret = regmap_read(wm9090->regmap, WM9090_SOFTWARE_RESET, &reg);
583*4882a593Smuzhiyun 	if (ret < 0)
584*4882a593Smuzhiyun 		return ret;
585*4882a593Smuzhiyun 
586*4882a593Smuzhiyun 	if (reg != 0x9093) {
587*4882a593Smuzhiyun 		dev_err(&i2c->dev, "Device is not a WM9090, ID=%x\n", reg);
588*4882a593Smuzhiyun 		return -ENODEV;
589*4882a593Smuzhiyun 	}
590*4882a593Smuzhiyun 
591*4882a593Smuzhiyun 	ret = regmap_write(wm9090->regmap, WM9090_SOFTWARE_RESET, 0);
592*4882a593Smuzhiyun 	if (ret < 0)
593*4882a593Smuzhiyun 		return ret;
594*4882a593Smuzhiyun 
595*4882a593Smuzhiyun 	if (i2c->dev.platform_data)
596*4882a593Smuzhiyun 		memcpy(&wm9090->pdata, i2c->dev.platform_data,
597*4882a593Smuzhiyun 		       sizeof(wm9090->pdata));
598*4882a593Smuzhiyun 
599*4882a593Smuzhiyun 	i2c_set_clientdata(i2c, wm9090);
600*4882a593Smuzhiyun 
601*4882a593Smuzhiyun 	ret =  devm_snd_soc_register_component(&i2c->dev,
602*4882a593Smuzhiyun 			&soc_component_dev_wm9090,  NULL, 0);
603*4882a593Smuzhiyun 	if (ret != 0) {
604*4882a593Smuzhiyun 		dev_err(&i2c->dev, "Failed to register CODEC: %d\n", ret);
605*4882a593Smuzhiyun 		return ret;
606*4882a593Smuzhiyun 	}
607*4882a593Smuzhiyun 
608*4882a593Smuzhiyun 	return 0;
609*4882a593Smuzhiyun }
610*4882a593Smuzhiyun 
611*4882a593Smuzhiyun static const struct i2c_device_id wm9090_id[] = {
612*4882a593Smuzhiyun 	{ "wm9090", 0 },
613*4882a593Smuzhiyun 	{ "wm9093", 0 },
614*4882a593Smuzhiyun 	{ }
615*4882a593Smuzhiyun };
616*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, wm9090_id);
617*4882a593Smuzhiyun 
618*4882a593Smuzhiyun static struct i2c_driver wm9090_i2c_driver = {
619*4882a593Smuzhiyun 	.driver = {
620*4882a593Smuzhiyun 		.name = "wm9090",
621*4882a593Smuzhiyun 	},
622*4882a593Smuzhiyun 	.probe = wm9090_i2c_probe,
623*4882a593Smuzhiyun 	.id_table = wm9090_id,
624*4882a593Smuzhiyun };
625*4882a593Smuzhiyun 
626*4882a593Smuzhiyun module_i2c_driver(wm9090_i2c_driver);
627*4882a593Smuzhiyun 
628*4882a593Smuzhiyun MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
629*4882a593Smuzhiyun MODULE_DESCRIPTION("WM9090 ASoC driver");
630*4882a593Smuzhiyun MODULE_LICENSE("GPL");
631