1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun #ifndef WM9081_H 3*4882a593Smuzhiyun #define WM9081_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun /* 6*4882a593Smuzhiyun * wm9081.c -- WM9081 ALSA SoC Audio driver 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Author: Mark Brown 9*4882a593Smuzhiyun * 10*4882a593Smuzhiyun * Copyright 2009 Wolfson Microelectronics plc 11*4882a593Smuzhiyun */ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #include <sound/soc.h> 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /* 16*4882a593Smuzhiyun * SYSCLK sources 17*4882a593Smuzhiyun */ 18*4882a593Smuzhiyun #define WM9081_SYSCLK_MCLK 1 /* Use MCLK without FLL */ 19*4882a593Smuzhiyun #define WM9081_SYSCLK_FLL_MCLK 2 /* Use MCLK, enabling FLL if required */ 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun /* 22*4882a593Smuzhiyun * Register values. 23*4882a593Smuzhiyun */ 24*4882a593Smuzhiyun #define WM9081_SOFTWARE_RESET 0x00 25*4882a593Smuzhiyun #define WM9081_ANALOGUE_LINEOUT 0x02 26*4882a593Smuzhiyun #define WM9081_ANALOGUE_SPEAKER_PGA 0x03 27*4882a593Smuzhiyun #define WM9081_VMID_CONTROL 0x04 28*4882a593Smuzhiyun #define WM9081_BIAS_CONTROL_1 0x05 29*4882a593Smuzhiyun #define WM9081_ANALOGUE_MIXER 0x07 30*4882a593Smuzhiyun #define WM9081_ANTI_POP_CONTROL 0x08 31*4882a593Smuzhiyun #define WM9081_ANALOGUE_SPEAKER_1 0x09 32*4882a593Smuzhiyun #define WM9081_ANALOGUE_SPEAKER_2 0x0A 33*4882a593Smuzhiyun #define WM9081_POWER_MANAGEMENT 0x0B 34*4882a593Smuzhiyun #define WM9081_CLOCK_CONTROL_1 0x0C 35*4882a593Smuzhiyun #define WM9081_CLOCK_CONTROL_2 0x0D 36*4882a593Smuzhiyun #define WM9081_CLOCK_CONTROL_3 0x0E 37*4882a593Smuzhiyun #define WM9081_FLL_CONTROL_1 0x10 38*4882a593Smuzhiyun #define WM9081_FLL_CONTROL_2 0x11 39*4882a593Smuzhiyun #define WM9081_FLL_CONTROL_3 0x12 40*4882a593Smuzhiyun #define WM9081_FLL_CONTROL_4 0x13 41*4882a593Smuzhiyun #define WM9081_FLL_CONTROL_5 0x14 42*4882a593Smuzhiyun #define WM9081_AUDIO_INTERFACE_1 0x16 43*4882a593Smuzhiyun #define WM9081_AUDIO_INTERFACE_2 0x17 44*4882a593Smuzhiyun #define WM9081_AUDIO_INTERFACE_3 0x18 45*4882a593Smuzhiyun #define WM9081_AUDIO_INTERFACE_4 0x19 46*4882a593Smuzhiyun #define WM9081_INTERRUPT_STATUS 0x1A 47*4882a593Smuzhiyun #define WM9081_INTERRUPT_STATUS_MASK 0x1B 48*4882a593Smuzhiyun #define WM9081_INTERRUPT_POLARITY 0x1C 49*4882a593Smuzhiyun #define WM9081_INTERRUPT_CONTROL 0x1D 50*4882a593Smuzhiyun #define WM9081_DAC_DIGITAL_1 0x1E 51*4882a593Smuzhiyun #define WM9081_DAC_DIGITAL_2 0x1F 52*4882a593Smuzhiyun #define WM9081_DRC_1 0x20 53*4882a593Smuzhiyun #define WM9081_DRC_2 0x21 54*4882a593Smuzhiyun #define WM9081_DRC_3 0x22 55*4882a593Smuzhiyun #define WM9081_DRC_4 0x23 56*4882a593Smuzhiyun #define WM9081_WRITE_SEQUENCER_1 0x26 57*4882a593Smuzhiyun #define WM9081_WRITE_SEQUENCER_2 0x27 58*4882a593Smuzhiyun #define WM9081_MW_SLAVE_1 0x28 59*4882a593Smuzhiyun #define WM9081_EQ_1 0x2A 60*4882a593Smuzhiyun #define WM9081_EQ_2 0x2B 61*4882a593Smuzhiyun #define WM9081_EQ_3 0x2C 62*4882a593Smuzhiyun #define WM9081_EQ_4 0x2D 63*4882a593Smuzhiyun #define WM9081_EQ_5 0x2E 64*4882a593Smuzhiyun #define WM9081_EQ_6 0x2F 65*4882a593Smuzhiyun #define WM9081_EQ_7 0x30 66*4882a593Smuzhiyun #define WM9081_EQ_8 0x31 67*4882a593Smuzhiyun #define WM9081_EQ_9 0x32 68*4882a593Smuzhiyun #define WM9081_EQ_10 0x33 69*4882a593Smuzhiyun #define WM9081_EQ_11 0x34 70*4882a593Smuzhiyun #define WM9081_EQ_12 0x35 71*4882a593Smuzhiyun #define WM9081_EQ_13 0x36 72*4882a593Smuzhiyun #define WM9081_EQ_14 0x37 73*4882a593Smuzhiyun #define WM9081_EQ_15 0x38 74*4882a593Smuzhiyun #define WM9081_EQ_16 0x39 75*4882a593Smuzhiyun #define WM9081_EQ_17 0x3A 76*4882a593Smuzhiyun #define WM9081_EQ_18 0x3B 77*4882a593Smuzhiyun #define WM9081_EQ_19 0x3C 78*4882a593Smuzhiyun #define WM9081_EQ_20 0x3D 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun #define WM9081_REGISTER_COUNT 55 81*4882a593Smuzhiyun #define WM9081_MAX_REGISTER 0x3D 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun /* 84*4882a593Smuzhiyun * Field Definitions. 85*4882a593Smuzhiyun */ 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun /* 88*4882a593Smuzhiyun * R0 (0x00) - Software Reset 89*4882a593Smuzhiyun */ 90*4882a593Smuzhiyun #define WM9081_SW_RST_DEV_ID1_MASK 0xFFFF /* SW_RST_DEV_ID1 - [15:0] */ 91*4882a593Smuzhiyun #define WM9081_SW_RST_DEV_ID1_SHIFT 0 /* SW_RST_DEV_ID1 - [15:0] */ 92*4882a593Smuzhiyun #define WM9081_SW_RST_DEV_ID1_WIDTH 16 /* SW_RST_DEV_ID1 - [15:0] */ 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun /* 95*4882a593Smuzhiyun * R2 (0x02) - Analogue Lineout 96*4882a593Smuzhiyun */ 97*4882a593Smuzhiyun #define WM9081_LINEOUT_MUTE 0x0080 /* LINEOUT_MUTE */ 98*4882a593Smuzhiyun #define WM9081_LINEOUT_MUTE_MASK 0x0080 /* LINEOUT_MUTE */ 99*4882a593Smuzhiyun #define WM9081_LINEOUT_MUTE_SHIFT 7 /* LINEOUT_MUTE */ 100*4882a593Smuzhiyun #define WM9081_LINEOUT_MUTE_WIDTH 1 /* LINEOUT_MUTE */ 101*4882a593Smuzhiyun #define WM9081_LINEOUTZC 0x0040 /* LINEOUTZC */ 102*4882a593Smuzhiyun #define WM9081_LINEOUTZC_MASK 0x0040 /* LINEOUTZC */ 103*4882a593Smuzhiyun #define WM9081_LINEOUTZC_SHIFT 6 /* LINEOUTZC */ 104*4882a593Smuzhiyun #define WM9081_LINEOUTZC_WIDTH 1 /* LINEOUTZC */ 105*4882a593Smuzhiyun #define WM9081_LINEOUT_VOL_MASK 0x003F /* LINEOUT_VOL - [5:0] */ 106*4882a593Smuzhiyun #define WM9081_LINEOUT_VOL_SHIFT 0 /* LINEOUT_VOL - [5:0] */ 107*4882a593Smuzhiyun #define WM9081_LINEOUT_VOL_WIDTH 6 /* LINEOUT_VOL - [5:0] */ 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun /* 110*4882a593Smuzhiyun * R3 (0x03) - Analogue Speaker PGA 111*4882a593Smuzhiyun */ 112*4882a593Smuzhiyun #define WM9081_SPKPGA_MUTE 0x0080 /* SPKPGA_MUTE */ 113*4882a593Smuzhiyun #define WM9081_SPKPGA_MUTE_MASK 0x0080 /* SPKPGA_MUTE */ 114*4882a593Smuzhiyun #define WM9081_SPKPGA_MUTE_SHIFT 7 /* SPKPGA_MUTE */ 115*4882a593Smuzhiyun #define WM9081_SPKPGA_MUTE_WIDTH 1 /* SPKPGA_MUTE */ 116*4882a593Smuzhiyun #define WM9081_SPKPGAZC 0x0040 /* SPKPGAZC */ 117*4882a593Smuzhiyun #define WM9081_SPKPGAZC_MASK 0x0040 /* SPKPGAZC */ 118*4882a593Smuzhiyun #define WM9081_SPKPGAZC_SHIFT 6 /* SPKPGAZC */ 119*4882a593Smuzhiyun #define WM9081_SPKPGAZC_WIDTH 1 /* SPKPGAZC */ 120*4882a593Smuzhiyun #define WM9081_SPKPGA_VOL_MASK 0x003F /* SPKPGA_VOL - [5:0] */ 121*4882a593Smuzhiyun #define WM9081_SPKPGA_VOL_SHIFT 0 /* SPKPGA_VOL - [5:0] */ 122*4882a593Smuzhiyun #define WM9081_SPKPGA_VOL_WIDTH 6 /* SPKPGA_VOL - [5:0] */ 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun /* 125*4882a593Smuzhiyun * R4 (0x04) - VMID Control 126*4882a593Smuzhiyun */ 127*4882a593Smuzhiyun #define WM9081_VMID_BUF_ENA 0x0020 /* VMID_BUF_ENA */ 128*4882a593Smuzhiyun #define WM9081_VMID_BUF_ENA_MASK 0x0020 /* VMID_BUF_ENA */ 129*4882a593Smuzhiyun #define WM9081_VMID_BUF_ENA_SHIFT 5 /* VMID_BUF_ENA */ 130*4882a593Smuzhiyun #define WM9081_VMID_BUF_ENA_WIDTH 1 /* VMID_BUF_ENA */ 131*4882a593Smuzhiyun #define WM9081_VMID_RAMP 0x0008 /* VMID_RAMP */ 132*4882a593Smuzhiyun #define WM9081_VMID_RAMP_MASK 0x0008 /* VMID_RAMP */ 133*4882a593Smuzhiyun #define WM9081_VMID_RAMP_SHIFT 3 /* VMID_RAMP */ 134*4882a593Smuzhiyun #define WM9081_VMID_RAMP_WIDTH 1 /* VMID_RAMP */ 135*4882a593Smuzhiyun #define WM9081_VMID_SEL_MASK 0x0006 /* VMID_SEL - [2:1] */ 136*4882a593Smuzhiyun #define WM9081_VMID_SEL_SHIFT 1 /* VMID_SEL - [2:1] */ 137*4882a593Smuzhiyun #define WM9081_VMID_SEL_WIDTH 2 /* VMID_SEL - [2:1] */ 138*4882a593Smuzhiyun #define WM9081_VMID_FAST_ST 0x0001 /* VMID_FAST_ST */ 139*4882a593Smuzhiyun #define WM9081_VMID_FAST_ST_MASK 0x0001 /* VMID_FAST_ST */ 140*4882a593Smuzhiyun #define WM9081_VMID_FAST_ST_SHIFT 0 /* VMID_FAST_ST */ 141*4882a593Smuzhiyun #define WM9081_VMID_FAST_ST_WIDTH 1 /* VMID_FAST_ST */ 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun /* 144*4882a593Smuzhiyun * R5 (0x05) - Bias Control 1 145*4882a593Smuzhiyun */ 146*4882a593Smuzhiyun #define WM9081_BIAS_SRC 0x0040 /* BIAS_SRC */ 147*4882a593Smuzhiyun #define WM9081_BIAS_SRC_MASK 0x0040 /* BIAS_SRC */ 148*4882a593Smuzhiyun #define WM9081_BIAS_SRC_SHIFT 6 /* BIAS_SRC */ 149*4882a593Smuzhiyun #define WM9081_BIAS_SRC_WIDTH 1 /* BIAS_SRC */ 150*4882a593Smuzhiyun #define WM9081_STBY_BIAS_LVL 0x0020 /* STBY_BIAS_LVL */ 151*4882a593Smuzhiyun #define WM9081_STBY_BIAS_LVL_MASK 0x0020 /* STBY_BIAS_LVL */ 152*4882a593Smuzhiyun #define WM9081_STBY_BIAS_LVL_SHIFT 5 /* STBY_BIAS_LVL */ 153*4882a593Smuzhiyun #define WM9081_STBY_BIAS_LVL_WIDTH 1 /* STBY_BIAS_LVL */ 154*4882a593Smuzhiyun #define WM9081_STBY_BIAS_ENA 0x0010 /* STBY_BIAS_ENA */ 155*4882a593Smuzhiyun #define WM9081_STBY_BIAS_ENA_MASK 0x0010 /* STBY_BIAS_ENA */ 156*4882a593Smuzhiyun #define WM9081_STBY_BIAS_ENA_SHIFT 4 /* STBY_BIAS_ENA */ 157*4882a593Smuzhiyun #define WM9081_STBY_BIAS_ENA_WIDTH 1 /* STBY_BIAS_ENA */ 158*4882a593Smuzhiyun #define WM9081_BIAS_LVL_MASK 0x000C /* BIAS_LVL - [3:2] */ 159*4882a593Smuzhiyun #define WM9081_BIAS_LVL_SHIFT 2 /* BIAS_LVL - [3:2] */ 160*4882a593Smuzhiyun #define WM9081_BIAS_LVL_WIDTH 2 /* BIAS_LVL - [3:2] */ 161*4882a593Smuzhiyun #define WM9081_BIAS_ENA 0x0002 /* BIAS_ENA */ 162*4882a593Smuzhiyun #define WM9081_BIAS_ENA_MASK 0x0002 /* BIAS_ENA */ 163*4882a593Smuzhiyun #define WM9081_BIAS_ENA_SHIFT 1 /* BIAS_ENA */ 164*4882a593Smuzhiyun #define WM9081_BIAS_ENA_WIDTH 1 /* BIAS_ENA */ 165*4882a593Smuzhiyun #define WM9081_STARTUP_BIAS_ENA 0x0001 /* STARTUP_BIAS_ENA */ 166*4882a593Smuzhiyun #define WM9081_STARTUP_BIAS_ENA_MASK 0x0001 /* STARTUP_BIAS_ENA */ 167*4882a593Smuzhiyun #define WM9081_STARTUP_BIAS_ENA_SHIFT 0 /* STARTUP_BIAS_ENA */ 168*4882a593Smuzhiyun #define WM9081_STARTUP_BIAS_ENA_WIDTH 1 /* STARTUP_BIAS_ENA */ 169*4882a593Smuzhiyun 170*4882a593Smuzhiyun /* 171*4882a593Smuzhiyun * R7 (0x07) - Analogue Mixer 172*4882a593Smuzhiyun */ 173*4882a593Smuzhiyun #define WM9081_DAC_SEL 0x0010 /* DAC_SEL */ 174*4882a593Smuzhiyun #define WM9081_DAC_SEL_MASK 0x0010 /* DAC_SEL */ 175*4882a593Smuzhiyun #define WM9081_DAC_SEL_SHIFT 4 /* DAC_SEL */ 176*4882a593Smuzhiyun #define WM9081_DAC_SEL_WIDTH 1 /* DAC_SEL */ 177*4882a593Smuzhiyun #define WM9081_IN2_VOL 0x0008 /* IN2_VOL */ 178*4882a593Smuzhiyun #define WM9081_IN2_VOL_MASK 0x0008 /* IN2_VOL */ 179*4882a593Smuzhiyun #define WM9081_IN2_VOL_SHIFT 3 /* IN2_VOL */ 180*4882a593Smuzhiyun #define WM9081_IN2_VOL_WIDTH 1 /* IN2_VOL */ 181*4882a593Smuzhiyun #define WM9081_IN2_ENA 0x0004 /* IN2_ENA */ 182*4882a593Smuzhiyun #define WM9081_IN2_ENA_MASK 0x0004 /* IN2_ENA */ 183*4882a593Smuzhiyun #define WM9081_IN2_ENA_SHIFT 2 /* IN2_ENA */ 184*4882a593Smuzhiyun #define WM9081_IN2_ENA_WIDTH 1 /* IN2_ENA */ 185*4882a593Smuzhiyun #define WM9081_IN1_VOL 0x0002 /* IN1_VOL */ 186*4882a593Smuzhiyun #define WM9081_IN1_VOL_MASK 0x0002 /* IN1_VOL */ 187*4882a593Smuzhiyun #define WM9081_IN1_VOL_SHIFT 1 /* IN1_VOL */ 188*4882a593Smuzhiyun #define WM9081_IN1_VOL_WIDTH 1 /* IN1_VOL */ 189*4882a593Smuzhiyun #define WM9081_IN1_ENA 0x0001 /* IN1_ENA */ 190*4882a593Smuzhiyun #define WM9081_IN1_ENA_MASK 0x0001 /* IN1_ENA */ 191*4882a593Smuzhiyun #define WM9081_IN1_ENA_SHIFT 0 /* IN1_ENA */ 192*4882a593Smuzhiyun #define WM9081_IN1_ENA_WIDTH 1 /* IN1_ENA */ 193*4882a593Smuzhiyun 194*4882a593Smuzhiyun /* 195*4882a593Smuzhiyun * R8 (0x08) - Anti Pop Control 196*4882a593Smuzhiyun */ 197*4882a593Smuzhiyun #define WM9081_LINEOUT_DISCH 0x0004 /* LINEOUT_DISCH */ 198*4882a593Smuzhiyun #define WM9081_LINEOUT_DISCH_MASK 0x0004 /* LINEOUT_DISCH */ 199*4882a593Smuzhiyun #define WM9081_LINEOUT_DISCH_SHIFT 2 /* LINEOUT_DISCH */ 200*4882a593Smuzhiyun #define WM9081_LINEOUT_DISCH_WIDTH 1 /* LINEOUT_DISCH */ 201*4882a593Smuzhiyun #define WM9081_LINEOUT_VROI 0x0002 /* LINEOUT_VROI */ 202*4882a593Smuzhiyun #define WM9081_LINEOUT_VROI_MASK 0x0002 /* LINEOUT_VROI */ 203*4882a593Smuzhiyun #define WM9081_LINEOUT_VROI_SHIFT 1 /* LINEOUT_VROI */ 204*4882a593Smuzhiyun #define WM9081_LINEOUT_VROI_WIDTH 1 /* LINEOUT_VROI */ 205*4882a593Smuzhiyun #define WM9081_LINEOUT_CLAMP 0x0001 /* LINEOUT_CLAMP */ 206*4882a593Smuzhiyun #define WM9081_LINEOUT_CLAMP_MASK 0x0001 /* LINEOUT_CLAMP */ 207*4882a593Smuzhiyun #define WM9081_LINEOUT_CLAMP_SHIFT 0 /* LINEOUT_CLAMP */ 208*4882a593Smuzhiyun #define WM9081_LINEOUT_CLAMP_WIDTH 1 /* LINEOUT_CLAMP */ 209*4882a593Smuzhiyun 210*4882a593Smuzhiyun /* 211*4882a593Smuzhiyun * R9 (0x09) - Analogue Speaker 1 212*4882a593Smuzhiyun */ 213*4882a593Smuzhiyun #define WM9081_SPK_DCGAIN_MASK 0x0038 /* SPK_DCGAIN - [5:3] */ 214*4882a593Smuzhiyun #define WM9081_SPK_DCGAIN_SHIFT 3 /* SPK_DCGAIN - [5:3] */ 215*4882a593Smuzhiyun #define WM9081_SPK_DCGAIN_WIDTH 3 /* SPK_DCGAIN - [5:3] */ 216*4882a593Smuzhiyun #define WM9081_SPK_ACGAIN_MASK 0x0007 /* SPK_ACGAIN - [2:0] */ 217*4882a593Smuzhiyun #define WM9081_SPK_ACGAIN_SHIFT 0 /* SPK_ACGAIN - [2:0] */ 218*4882a593Smuzhiyun #define WM9081_SPK_ACGAIN_WIDTH 3 /* SPK_ACGAIN - [2:0] */ 219*4882a593Smuzhiyun 220*4882a593Smuzhiyun /* 221*4882a593Smuzhiyun * R10 (0x0A) - Analogue Speaker 2 222*4882a593Smuzhiyun */ 223*4882a593Smuzhiyun #define WM9081_SPK_MODE 0x0040 /* SPK_MODE */ 224*4882a593Smuzhiyun #define WM9081_SPK_MODE_MASK 0x0040 /* SPK_MODE */ 225*4882a593Smuzhiyun #define WM9081_SPK_MODE_SHIFT 6 /* SPK_MODE */ 226*4882a593Smuzhiyun #define WM9081_SPK_MODE_WIDTH 1 /* SPK_MODE */ 227*4882a593Smuzhiyun #define WM9081_SPK_INV_MUTE 0x0010 /* SPK_INV_MUTE */ 228*4882a593Smuzhiyun #define WM9081_SPK_INV_MUTE_MASK 0x0010 /* SPK_INV_MUTE */ 229*4882a593Smuzhiyun #define WM9081_SPK_INV_MUTE_SHIFT 4 /* SPK_INV_MUTE */ 230*4882a593Smuzhiyun #define WM9081_SPK_INV_MUTE_WIDTH 1 /* SPK_INV_MUTE */ 231*4882a593Smuzhiyun #define WM9081_OUT_SPK_CTRL 0x0008 /* OUT_SPK_CTRL */ 232*4882a593Smuzhiyun #define WM9081_OUT_SPK_CTRL_MASK 0x0008 /* OUT_SPK_CTRL */ 233*4882a593Smuzhiyun #define WM9081_OUT_SPK_CTRL_SHIFT 3 /* OUT_SPK_CTRL */ 234*4882a593Smuzhiyun #define WM9081_OUT_SPK_CTRL_WIDTH 1 /* OUT_SPK_CTRL */ 235*4882a593Smuzhiyun 236*4882a593Smuzhiyun /* 237*4882a593Smuzhiyun * R11 (0x0B) - Power Management 238*4882a593Smuzhiyun */ 239*4882a593Smuzhiyun #define WM9081_TSHUT_ENA 0x0100 /* TSHUT_ENA */ 240*4882a593Smuzhiyun #define WM9081_TSHUT_ENA_MASK 0x0100 /* TSHUT_ENA */ 241*4882a593Smuzhiyun #define WM9081_TSHUT_ENA_SHIFT 8 /* TSHUT_ENA */ 242*4882a593Smuzhiyun #define WM9081_TSHUT_ENA_WIDTH 1 /* TSHUT_ENA */ 243*4882a593Smuzhiyun #define WM9081_TSENSE_ENA 0x0080 /* TSENSE_ENA */ 244*4882a593Smuzhiyun #define WM9081_TSENSE_ENA_MASK 0x0080 /* TSENSE_ENA */ 245*4882a593Smuzhiyun #define WM9081_TSENSE_ENA_SHIFT 7 /* TSENSE_ENA */ 246*4882a593Smuzhiyun #define WM9081_TSENSE_ENA_WIDTH 1 /* TSENSE_ENA */ 247*4882a593Smuzhiyun #define WM9081_TEMP_SHUT 0x0040 /* TEMP_SHUT */ 248*4882a593Smuzhiyun #define WM9081_TEMP_SHUT_MASK 0x0040 /* TEMP_SHUT */ 249*4882a593Smuzhiyun #define WM9081_TEMP_SHUT_SHIFT 6 /* TEMP_SHUT */ 250*4882a593Smuzhiyun #define WM9081_TEMP_SHUT_WIDTH 1 /* TEMP_SHUT */ 251*4882a593Smuzhiyun #define WM9081_LINEOUT_ENA 0x0010 /* LINEOUT_ENA */ 252*4882a593Smuzhiyun #define WM9081_LINEOUT_ENA_MASK 0x0010 /* LINEOUT_ENA */ 253*4882a593Smuzhiyun #define WM9081_LINEOUT_ENA_SHIFT 4 /* LINEOUT_ENA */ 254*4882a593Smuzhiyun #define WM9081_LINEOUT_ENA_WIDTH 1 /* LINEOUT_ENA */ 255*4882a593Smuzhiyun #define WM9081_SPKPGA_ENA 0x0004 /* SPKPGA_ENA */ 256*4882a593Smuzhiyun #define WM9081_SPKPGA_ENA_MASK 0x0004 /* SPKPGA_ENA */ 257*4882a593Smuzhiyun #define WM9081_SPKPGA_ENA_SHIFT 2 /* SPKPGA_ENA */ 258*4882a593Smuzhiyun #define WM9081_SPKPGA_ENA_WIDTH 1 /* SPKPGA_ENA */ 259*4882a593Smuzhiyun #define WM9081_SPK_ENA 0x0002 /* SPK_ENA */ 260*4882a593Smuzhiyun #define WM9081_SPK_ENA_MASK 0x0002 /* SPK_ENA */ 261*4882a593Smuzhiyun #define WM9081_SPK_ENA_SHIFT 1 /* SPK_ENA */ 262*4882a593Smuzhiyun #define WM9081_SPK_ENA_WIDTH 1 /* SPK_ENA */ 263*4882a593Smuzhiyun #define WM9081_DAC_ENA 0x0001 /* DAC_ENA */ 264*4882a593Smuzhiyun #define WM9081_DAC_ENA_MASK 0x0001 /* DAC_ENA */ 265*4882a593Smuzhiyun #define WM9081_DAC_ENA_SHIFT 0 /* DAC_ENA */ 266*4882a593Smuzhiyun #define WM9081_DAC_ENA_WIDTH 1 /* DAC_ENA */ 267*4882a593Smuzhiyun 268*4882a593Smuzhiyun /* 269*4882a593Smuzhiyun * R12 (0x0C) - Clock Control 1 270*4882a593Smuzhiyun */ 271*4882a593Smuzhiyun #define WM9081_CLK_OP_DIV_MASK 0x1C00 /* CLK_OP_DIV - [12:10] */ 272*4882a593Smuzhiyun #define WM9081_CLK_OP_DIV_SHIFT 10 /* CLK_OP_DIV - [12:10] */ 273*4882a593Smuzhiyun #define WM9081_CLK_OP_DIV_WIDTH 3 /* CLK_OP_DIV - [12:10] */ 274*4882a593Smuzhiyun #define WM9081_CLK_TO_DIV_MASK 0x0300 /* CLK_TO_DIV - [9:8] */ 275*4882a593Smuzhiyun #define WM9081_CLK_TO_DIV_SHIFT 8 /* CLK_TO_DIV - [9:8] */ 276*4882a593Smuzhiyun #define WM9081_CLK_TO_DIV_WIDTH 2 /* CLK_TO_DIV - [9:8] */ 277*4882a593Smuzhiyun #define WM9081_MCLKDIV2 0x0080 /* MCLKDIV2 */ 278*4882a593Smuzhiyun #define WM9081_MCLKDIV2_MASK 0x0080 /* MCLKDIV2 */ 279*4882a593Smuzhiyun #define WM9081_MCLKDIV2_SHIFT 7 /* MCLKDIV2 */ 280*4882a593Smuzhiyun #define WM9081_MCLKDIV2_WIDTH 1 /* MCLKDIV2 */ 281*4882a593Smuzhiyun 282*4882a593Smuzhiyun /* 283*4882a593Smuzhiyun * R13 (0x0D) - Clock Control 2 284*4882a593Smuzhiyun */ 285*4882a593Smuzhiyun #define WM9081_CLK_SYS_RATE_MASK 0x00F0 /* CLK_SYS_RATE - [7:4] */ 286*4882a593Smuzhiyun #define WM9081_CLK_SYS_RATE_SHIFT 4 /* CLK_SYS_RATE - [7:4] */ 287*4882a593Smuzhiyun #define WM9081_CLK_SYS_RATE_WIDTH 4 /* CLK_SYS_RATE - [7:4] */ 288*4882a593Smuzhiyun #define WM9081_SAMPLE_RATE_MASK 0x000F /* SAMPLE_RATE - [3:0] */ 289*4882a593Smuzhiyun #define WM9081_SAMPLE_RATE_SHIFT 0 /* SAMPLE_RATE - [3:0] */ 290*4882a593Smuzhiyun #define WM9081_SAMPLE_RATE_WIDTH 4 /* SAMPLE_RATE - [3:0] */ 291*4882a593Smuzhiyun 292*4882a593Smuzhiyun /* 293*4882a593Smuzhiyun * R14 (0x0E) - Clock Control 3 294*4882a593Smuzhiyun */ 295*4882a593Smuzhiyun #define WM9081_CLK_SRC_SEL 0x2000 /* CLK_SRC_SEL */ 296*4882a593Smuzhiyun #define WM9081_CLK_SRC_SEL_MASK 0x2000 /* CLK_SRC_SEL */ 297*4882a593Smuzhiyun #define WM9081_CLK_SRC_SEL_SHIFT 13 /* CLK_SRC_SEL */ 298*4882a593Smuzhiyun #define WM9081_CLK_SRC_SEL_WIDTH 1 /* CLK_SRC_SEL */ 299*4882a593Smuzhiyun #define WM9081_CLK_OP_ENA 0x0020 /* CLK_OP_ENA */ 300*4882a593Smuzhiyun #define WM9081_CLK_OP_ENA_MASK 0x0020 /* CLK_OP_ENA */ 301*4882a593Smuzhiyun #define WM9081_CLK_OP_ENA_SHIFT 5 /* CLK_OP_ENA */ 302*4882a593Smuzhiyun #define WM9081_CLK_OP_ENA_WIDTH 1 /* CLK_OP_ENA */ 303*4882a593Smuzhiyun #define WM9081_CLK_TO_ENA 0x0004 /* CLK_TO_ENA */ 304*4882a593Smuzhiyun #define WM9081_CLK_TO_ENA_MASK 0x0004 /* CLK_TO_ENA */ 305*4882a593Smuzhiyun #define WM9081_CLK_TO_ENA_SHIFT 2 /* CLK_TO_ENA */ 306*4882a593Smuzhiyun #define WM9081_CLK_TO_ENA_WIDTH 1 /* CLK_TO_ENA */ 307*4882a593Smuzhiyun #define WM9081_CLK_DSP_ENA 0x0002 /* CLK_DSP_ENA */ 308*4882a593Smuzhiyun #define WM9081_CLK_DSP_ENA_MASK 0x0002 /* CLK_DSP_ENA */ 309*4882a593Smuzhiyun #define WM9081_CLK_DSP_ENA_SHIFT 1 /* CLK_DSP_ENA */ 310*4882a593Smuzhiyun #define WM9081_CLK_DSP_ENA_WIDTH 1 /* CLK_DSP_ENA */ 311*4882a593Smuzhiyun #define WM9081_CLK_SYS_ENA 0x0001 /* CLK_SYS_ENA */ 312*4882a593Smuzhiyun #define WM9081_CLK_SYS_ENA_MASK 0x0001 /* CLK_SYS_ENA */ 313*4882a593Smuzhiyun #define WM9081_CLK_SYS_ENA_SHIFT 0 /* CLK_SYS_ENA */ 314*4882a593Smuzhiyun #define WM9081_CLK_SYS_ENA_WIDTH 1 /* CLK_SYS_ENA */ 315*4882a593Smuzhiyun 316*4882a593Smuzhiyun /* 317*4882a593Smuzhiyun * R16 (0x10) - FLL Control 1 318*4882a593Smuzhiyun */ 319*4882a593Smuzhiyun #define WM9081_FLL_HOLD 0x0008 /* FLL_HOLD */ 320*4882a593Smuzhiyun #define WM9081_FLL_HOLD_MASK 0x0008 /* FLL_HOLD */ 321*4882a593Smuzhiyun #define WM9081_FLL_HOLD_SHIFT 3 /* FLL_HOLD */ 322*4882a593Smuzhiyun #define WM9081_FLL_HOLD_WIDTH 1 /* FLL_HOLD */ 323*4882a593Smuzhiyun #define WM9081_FLL_FRAC 0x0004 /* FLL_FRAC */ 324*4882a593Smuzhiyun #define WM9081_FLL_FRAC_MASK 0x0004 /* FLL_FRAC */ 325*4882a593Smuzhiyun #define WM9081_FLL_FRAC_SHIFT 2 /* FLL_FRAC */ 326*4882a593Smuzhiyun #define WM9081_FLL_FRAC_WIDTH 1 /* FLL_FRAC */ 327*4882a593Smuzhiyun #define WM9081_FLL_ENA 0x0001 /* FLL_ENA */ 328*4882a593Smuzhiyun #define WM9081_FLL_ENA_MASK 0x0001 /* FLL_ENA */ 329*4882a593Smuzhiyun #define WM9081_FLL_ENA_SHIFT 0 /* FLL_ENA */ 330*4882a593Smuzhiyun #define WM9081_FLL_ENA_WIDTH 1 /* FLL_ENA */ 331*4882a593Smuzhiyun 332*4882a593Smuzhiyun /* 333*4882a593Smuzhiyun * R17 (0x11) - FLL Control 2 334*4882a593Smuzhiyun */ 335*4882a593Smuzhiyun #define WM9081_FLL_OUTDIV_MASK 0x0700 /* FLL_OUTDIV - [10:8] */ 336*4882a593Smuzhiyun #define WM9081_FLL_OUTDIV_SHIFT 8 /* FLL_OUTDIV - [10:8] */ 337*4882a593Smuzhiyun #define WM9081_FLL_OUTDIV_WIDTH 3 /* FLL_OUTDIV - [10:8] */ 338*4882a593Smuzhiyun #define WM9081_FLL_CTRL_RATE_MASK 0x0070 /* FLL_CTRL_RATE - [6:4] */ 339*4882a593Smuzhiyun #define WM9081_FLL_CTRL_RATE_SHIFT 4 /* FLL_CTRL_RATE - [6:4] */ 340*4882a593Smuzhiyun #define WM9081_FLL_CTRL_RATE_WIDTH 3 /* FLL_CTRL_RATE - [6:4] */ 341*4882a593Smuzhiyun #define WM9081_FLL_FRATIO_MASK 0x0007 /* FLL_FRATIO - [2:0] */ 342*4882a593Smuzhiyun #define WM9081_FLL_FRATIO_SHIFT 0 /* FLL_FRATIO - [2:0] */ 343*4882a593Smuzhiyun #define WM9081_FLL_FRATIO_WIDTH 3 /* FLL_FRATIO - [2:0] */ 344*4882a593Smuzhiyun 345*4882a593Smuzhiyun /* 346*4882a593Smuzhiyun * R18 (0x12) - FLL Control 3 347*4882a593Smuzhiyun */ 348*4882a593Smuzhiyun #define WM9081_FLL_K_MASK 0xFFFF /* FLL_K - [15:0] */ 349*4882a593Smuzhiyun #define WM9081_FLL_K_SHIFT 0 /* FLL_K - [15:0] */ 350*4882a593Smuzhiyun #define WM9081_FLL_K_WIDTH 16 /* FLL_K - [15:0] */ 351*4882a593Smuzhiyun 352*4882a593Smuzhiyun /* 353*4882a593Smuzhiyun * R19 (0x13) - FLL Control 4 354*4882a593Smuzhiyun */ 355*4882a593Smuzhiyun #define WM9081_FLL_N_MASK 0x7FE0 /* FLL_N - [14:5] */ 356*4882a593Smuzhiyun #define WM9081_FLL_N_SHIFT 5 /* FLL_N - [14:5] */ 357*4882a593Smuzhiyun #define WM9081_FLL_N_WIDTH 10 /* FLL_N - [14:5] */ 358*4882a593Smuzhiyun #define WM9081_FLL_GAIN_MASK 0x000F /* FLL_GAIN - [3:0] */ 359*4882a593Smuzhiyun #define WM9081_FLL_GAIN_SHIFT 0 /* FLL_GAIN - [3:0] */ 360*4882a593Smuzhiyun #define WM9081_FLL_GAIN_WIDTH 4 /* FLL_GAIN - [3:0] */ 361*4882a593Smuzhiyun 362*4882a593Smuzhiyun /* 363*4882a593Smuzhiyun * R20 (0x14) - FLL Control 5 364*4882a593Smuzhiyun */ 365*4882a593Smuzhiyun #define WM9081_FLL_CLK_REF_DIV_MASK 0x0018 /* FLL_CLK_REF_DIV - [4:3] */ 366*4882a593Smuzhiyun #define WM9081_FLL_CLK_REF_DIV_SHIFT 3 /* FLL_CLK_REF_DIV - [4:3] */ 367*4882a593Smuzhiyun #define WM9081_FLL_CLK_REF_DIV_WIDTH 2 /* FLL_CLK_REF_DIV - [4:3] */ 368*4882a593Smuzhiyun #define WM9081_FLL_CLK_SRC_MASK 0x0003 /* FLL_CLK_SRC - [1:0] */ 369*4882a593Smuzhiyun #define WM9081_FLL_CLK_SRC_SHIFT 0 /* FLL_CLK_SRC - [1:0] */ 370*4882a593Smuzhiyun #define WM9081_FLL_CLK_SRC_WIDTH 2 /* FLL_CLK_SRC - [1:0] */ 371*4882a593Smuzhiyun 372*4882a593Smuzhiyun /* 373*4882a593Smuzhiyun * R22 (0x16) - Audio Interface 1 374*4882a593Smuzhiyun */ 375*4882a593Smuzhiyun #define WM9081_AIFDAC_CHAN 0x0040 /* AIFDAC_CHAN */ 376*4882a593Smuzhiyun #define WM9081_AIFDAC_CHAN_MASK 0x0040 /* AIFDAC_CHAN */ 377*4882a593Smuzhiyun #define WM9081_AIFDAC_CHAN_SHIFT 6 /* AIFDAC_CHAN */ 378*4882a593Smuzhiyun #define WM9081_AIFDAC_CHAN_WIDTH 1 /* AIFDAC_CHAN */ 379*4882a593Smuzhiyun #define WM9081_AIFDAC_TDM_SLOT_MASK 0x0030 /* AIFDAC_TDM_SLOT - [5:4] */ 380*4882a593Smuzhiyun #define WM9081_AIFDAC_TDM_SLOT_SHIFT 4 /* AIFDAC_TDM_SLOT - [5:4] */ 381*4882a593Smuzhiyun #define WM9081_AIFDAC_TDM_SLOT_WIDTH 2 /* AIFDAC_TDM_SLOT - [5:4] */ 382*4882a593Smuzhiyun #define WM9081_AIFDAC_TDM_MODE_MASK 0x000C /* AIFDAC_TDM_MODE - [3:2] */ 383*4882a593Smuzhiyun #define WM9081_AIFDAC_TDM_MODE_SHIFT 2 /* AIFDAC_TDM_MODE - [3:2] */ 384*4882a593Smuzhiyun #define WM9081_AIFDAC_TDM_MODE_WIDTH 2 /* AIFDAC_TDM_MODE - [3:2] */ 385*4882a593Smuzhiyun #define WM9081_DAC_COMP 0x0002 /* DAC_COMP */ 386*4882a593Smuzhiyun #define WM9081_DAC_COMP_MASK 0x0002 /* DAC_COMP */ 387*4882a593Smuzhiyun #define WM9081_DAC_COMP_SHIFT 1 /* DAC_COMP */ 388*4882a593Smuzhiyun #define WM9081_DAC_COMP_WIDTH 1 /* DAC_COMP */ 389*4882a593Smuzhiyun #define WM9081_DAC_COMPMODE 0x0001 /* DAC_COMPMODE */ 390*4882a593Smuzhiyun #define WM9081_DAC_COMPMODE_MASK 0x0001 /* DAC_COMPMODE */ 391*4882a593Smuzhiyun #define WM9081_DAC_COMPMODE_SHIFT 0 /* DAC_COMPMODE */ 392*4882a593Smuzhiyun #define WM9081_DAC_COMPMODE_WIDTH 1 /* DAC_COMPMODE */ 393*4882a593Smuzhiyun 394*4882a593Smuzhiyun /* 395*4882a593Smuzhiyun * R23 (0x17) - Audio Interface 2 396*4882a593Smuzhiyun */ 397*4882a593Smuzhiyun #define WM9081_AIF_TRIS 0x0200 /* AIF_TRIS */ 398*4882a593Smuzhiyun #define WM9081_AIF_TRIS_MASK 0x0200 /* AIF_TRIS */ 399*4882a593Smuzhiyun #define WM9081_AIF_TRIS_SHIFT 9 /* AIF_TRIS */ 400*4882a593Smuzhiyun #define WM9081_AIF_TRIS_WIDTH 1 /* AIF_TRIS */ 401*4882a593Smuzhiyun #define WM9081_DAC_DAT_INV 0x0100 /* DAC_DAT_INV */ 402*4882a593Smuzhiyun #define WM9081_DAC_DAT_INV_MASK 0x0100 /* DAC_DAT_INV */ 403*4882a593Smuzhiyun #define WM9081_DAC_DAT_INV_SHIFT 8 /* DAC_DAT_INV */ 404*4882a593Smuzhiyun #define WM9081_DAC_DAT_INV_WIDTH 1 /* DAC_DAT_INV */ 405*4882a593Smuzhiyun #define WM9081_AIF_BCLK_INV 0x0080 /* AIF_BCLK_INV */ 406*4882a593Smuzhiyun #define WM9081_AIF_BCLK_INV_MASK 0x0080 /* AIF_BCLK_INV */ 407*4882a593Smuzhiyun #define WM9081_AIF_BCLK_INV_SHIFT 7 /* AIF_BCLK_INV */ 408*4882a593Smuzhiyun #define WM9081_AIF_BCLK_INV_WIDTH 1 /* AIF_BCLK_INV */ 409*4882a593Smuzhiyun #define WM9081_BCLK_DIR 0x0040 /* BCLK_DIR */ 410*4882a593Smuzhiyun #define WM9081_BCLK_DIR_MASK 0x0040 /* BCLK_DIR */ 411*4882a593Smuzhiyun #define WM9081_BCLK_DIR_SHIFT 6 /* BCLK_DIR */ 412*4882a593Smuzhiyun #define WM9081_BCLK_DIR_WIDTH 1 /* BCLK_DIR */ 413*4882a593Smuzhiyun #define WM9081_LRCLK_DIR 0x0020 /* LRCLK_DIR */ 414*4882a593Smuzhiyun #define WM9081_LRCLK_DIR_MASK 0x0020 /* LRCLK_DIR */ 415*4882a593Smuzhiyun #define WM9081_LRCLK_DIR_SHIFT 5 /* LRCLK_DIR */ 416*4882a593Smuzhiyun #define WM9081_LRCLK_DIR_WIDTH 1 /* LRCLK_DIR */ 417*4882a593Smuzhiyun #define WM9081_AIF_LRCLK_INV 0x0010 /* AIF_LRCLK_INV */ 418*4882a593Smuzhiyun #define WM9081_AIF_LRCLK_INV_MASK 0x0010 /* AIF_LRCLK_INV */ 419*4882a593Smuzhiyun #define WM9081_AIF_LRCLK_INV_SHIFT 4 /* AIF_LRCLK_INV */ 420*4882a593Smuzhiyun #define WM9081_AIF_LRCLK_INV_WIDTH 1 /* AIF_LRCLK_INV */ 421*4882a593Smuzhiyun #define WM9081_AIF_WL_MASK 0x000C /* AIF_WL - [3:2] */ 422*4882a593Smuzhiyun #define WM9081_AIF_WL_SHIFT 2 /* AIF_WL - [3:2] */ 423*4882a593Smuzhiyun #define WM9081_AIF_WL_WIDTH 2 /* AIF_WL - [3:2] */ 424*4882a593Smuzhiyun #define WM9081_AIF_FMT_MASK 0x0003 /* AIF_FMT - [1:0] */ 425*4882a593Smuzhiyun #define WM9081_AIF_FMT_SHIFT 0 /* AIF_FMT - [1:0] */ 426*4882a593Smuzhiyun #define WM9081_AIF_FMT_WIDTH 2 /* AIF_FMT - [1:0] */ 427*4882a593Smuzhiyun 428*4882a593Smuzhiyun /* 429*4882a593Smuzhiyun * R24 (0x18) - Audio Interface 3 430*4882a593Smuzhiyun */ 431*4882a593Smuzhiyun #define WM9081_BCLK_DIV_MASK 0x001F /* BCLK_DIV - [4:0] */ 432*4882a593Smuzhiyun #define WM9081_BCLK_DIV_SHIFT 0 /* BCLK_DIV - [4:0] */ 433*4882a593Smuzhiyun #define WM9081_BCLK_DIV_WIDTH 5 /* BCLK_DIV - [4:0] */ 434*4882a593Smuzhiyun 435*4882a593Smuzhiyun /* 436*4882a593Smuzhiyun * R25 (0x19) - Audio Interface 4 437*4882a593Smuzhiyun */ 438*4882a593Smuzhiyun #define WM9081_LRCLK_RATE_MASK 0x07FF /* LRCLK_RATE - [10:0] */ 439*4882a593Smuzhiyun #define WM9081_LRCLK_RATE_SHIFT 0 /* LRCLK_RATE - [10:0] */ 440*4882a593Smuzhiyun #define WM9081_LRCLK_RATE_WIDTH 11 /* LRCLK_RATE - [10:0] */ 441*4882a593Smuzhiyun 442*4882a593Smuzhiyun /* 443*4882a593Smuzhiyun * R26 (0x1A) - Interrupt Status 444*4882a593Smuzhiyun */ 445*4882a593Smuzhiyun #define WM9081_WSEQ_BUSY_EINT 0x0004 /* WSEQ_BUSY_EINT */ 446*4882a593Smuzhiyun #define WM9081_WSEQ_BUSY_EINT_MASK 0x0004 /* WSEQ_BUSY_EINT */ 447*4882a593Smuzhiyun #define WM9081_WSEQ_BUSY_EINT_SHIFT 2 /* WSEQ_BUSY_EINT */ 448*4882a593Smuzhiyun #define WM9081_WSEQ_BUSY_EINT_WIDTH 1 /* WSEQ_BUSY_EINT */ 449*4882a593Smuzhiyun #define WM9081_TSHUT_EINT 0x0001 /* TSHUT_EINT */ 450*4882a593Smuzhiyun #define WM9081_TSHUT_EINT_MASK 0x0001 /* TSHUT_EINT */ 451*4882a593Smuzhiyun #define WM9081_TSHUT_EINT_SHIFT 0 /* TSHUT_EINT */ 452*4882a593Smuzhiyun #define WM9081_TSHUT_EINT_WIDTH 1 /* TSHUT_EINT */ 453*4882a593Smuzhiyun 454*4882a593Smuzhiyun /* 455*4882a593Smuzhiyun * R27 (0x1B) - Interrupt Status Mask 456*4882a593Smuzhiyun */ 457*4882a593Smuzhiyun #define WM9081_IM_WSEQ_BUSY_EINT 0x0004 /* IM_WSEQ_BUSY_EINT */ 458*4882a593Smuzhiyun #define WM9081_IM_WSEQ_BUSY_EINT_MASK 0x0004 /* IM_WSEQ_BUSY_EINT */ 459*4882a593Smuzhiyun #define WM9081_IM_WSEQ_BUSY_EINT_SHIFT 2 /* IM_WSEQ_BUSY_EINT */ 460*4882a593Smuzhiyun #define WM9081_IM_WSEQ_BUSY_EINT_WIDTH 1 /* IM_WSEQ_BUSY_EINT */ 461*4882a593Smuzhiyun #define WM9081_IM_TSHUT_EINT 0x0001 /* IM_TSHUT_EINT */ 462*4882a593Smuzhiyun #define WM9081_IM_TSHUT_EINT_MASK 0x0001 /* IM_TSHUT_EINT */ 463*4882a593Smuzhiyun #define WM9081_IM_TSHUT_EINT_SHIFT 0 /* IM_TSHUT_EINT */ 464*4882a593Smuzhiyun #define WM9081_IM_TSHUT_EINT_WIDTH 1 /* IM_TSHUT_EINT */ 465*4882a593Smuzhiyun 466*4882a593Smuzhiyun /* 467*4882a593Smuzhiyun * R28 (0x1C) - Interrupt Polarity 468*4882a593Smuzhiyun */ 469*4882a593Smuzhiyun #define WM9081_TSHUT_INV 0x0001 /* TSHUT_INV */ 470*4882a593Smuzhiyun #define WM9081_TSHUT_INV_MASK 0x0001 /* TSHUT_INV */ 471*4882a593Smuzhiyun #define WM9081_TSHUT_INV_SHIFT 0 /* TSHUT_INV */ 472*4882a593Smuzhiyun #define WM9081_TSHUT_INV_WIDTH 1 /* TSHUT_INV */ 473*4882a593Smuzhiyun 474*4882a593Smuzhiyun /* 475*4882a593Smuzhiyun * R29 (0x1D) - Interrupt Control 476*4882a593Smuzhiyun */ 477*4882a593Smuzhiyun #define WM9081_IRQ_POL 0x8000 /* IRQ_POL */ 478*4882a593Smuzhiyun #define WM9081_IRQ_POL_MASK 0x8000 /* IRQ_POL */ 479*4882a593Smuzhiyun #define WM9081_IRQ_POL_SHIFT 15 /* IRQ_POL */ 480*4882a593Smuzhiyun #define WM9081_IRQ_POL_WIDTH 1 /* IRQ_POL */ 481*4882a593Smuzhiyun #define WM9081_IRQ_OP_CTRL 0x0001 /* IRQ_OP_CTRL */ 482*4882a593Smuzhiyun #define WM9081_IRQ_OP_CTRL_MASK 0x0001 /* IRQ_OP_CTRL */ 483*4882a593Smuzhiyun #define WM9081_IRQ_OP_CTRL_SHIFT 0 /* IRQ_OP_CTRL */ 484*4882a593Smuzhiyun #define WM9081_IRQ_OP_CTRL_WIDTH 1 /* IRQ_OP_CTRL */ 485*4882a593Smuzhiyun 486*4882a593Smuzhiyun /* 487*4882a593Smuzhiyun * R30 (0x1E) - DAC Digital 1 488*4882a593Smuzhiyun */ 489*4882a593Smuzhiyun #define WM9081_DAC_VOL_MASK 0x00FF /* DAC_VOL - [7:0] */ 490*4882a593Smuzhiyun #define WM9081_DAC_VOL_SHIFT 0 /* DAC_VOL - [7:0] */ 491*4882a593Smuzhiyun #define WM9081_DAC_VOL_WIDTH 8 /* DAC_VOL - [7:0] */ 492*4882a593Smuzhiyun 493*4882a593Smuzhiyun /* 494*4882a593Smuzhiyun * R31 (0x1F) - DAC Digital 2 495*4882a593Smuzhiyun */ 496*4882a593Smuzhiyun #define WM9081_DAC_MUTERATE 0x0400 /* DAC_MUTERATE */ 497*4882a593Smuzhiyun #define WM9081_DAC_MUTERATE_MASK 0x0400 /* DAC_MUTERATE */ 498*4882a593Smuzhiyun #define WM9081_DAC_MUTERATE_SHIFT 10 /* DAC_MUTERATE */ 499*4882a593Smuzhiyun #define WM9081_DAC_MUTERATE_WIDTH 1 /* DAC_MUTERATE */ 500*4882a593Smuzhiyun #define WM9081_DAC_MUTEMODE 0x0200 /* DAC_MUTEMODE */ 501*4882a593Smuzhiyun #define WM9081_DAC_MUTEMODE_MASK 0x0200 /* DAC_MUTEMODE */ 502*4882a593Smuzhiyun #define WM9081_DAC_MUTEMODE_SHIFT 9 /* DAC_MUTEMODE */ 503*4882a593Smuzhiyun #define WM9081_DAC_MUTEMODE_WIDTH 1 /* DAC_MUTEMODE */ 504*4882a593Smuzhiyun #define WM9081_DAC_MUTE 0x0008 /* DAC_MUTE */ 505*4882a593Smuzhiyun #define WM9081_DAC_MUTE_MASK 0x0008 /* DAC_MUTE */ 506*4882a593Smuzhiyun #define WM9081_DAC_MUTE_SHIFT 3 /* DAC_MUTE */ 507*4882a593Smuzhiyun #define WM9081_DAC_MUTE_WIDTH 1 /* DAC_MUTE */ 508*4882a593Smuzhiyun #define WM9081_DEEMPH_MASK 0x0006 /* DEEMPH - [2:1] */ 509*4882a593Smuzhiyun #define WM9081_DEEMPH_SHIFT 1 /* DEEMPH - [2:1] */ 510*4882a593Smuzhiyun #define WM9081_DEEMPH_WIDTH 2 /* DEEMPH - [2:1] */ 511*4882a593Smuzhiyun 512*4882a593Smuzhiyun /* 513*4882a593Smuzhiyun * R32 (0x20) - DRC 1 514*4882a593Smuzhiyun */ 515*4882a593Smuzhiyun #define WM9081_DRC_ENA 0x8000 /* DRC_ENA */ 516*4882a593Smuzhiyun #define WM9081_DRC_ENA_MASK 0x8000 /* DRC_ENA */ 517*4882a593Smuzhiyun #define WM9081_DRC_ENA_SHIFT 15 /* DRC_ENA */ 518*4882a593Smuzhiyun #define WM9081_DRC_ENA_WIDTH 1 /* DRC_ENA */ 519*4882a593Smuzhiyun #define WM9081_DRC_STARTUP_GAIN_MASK 0x07C0 /* DRC_STARTUP_GAIN - [10:6] */ 520*4882a593Smuzhiyun #define WM9081_DRC_STARTUP_GAIN_SHIFT 6 /* DRC_STARTUP_GAIN - [10:6] */ 521*4882a593Smuzhiyun #define WM9081_DRC_STARTUP_GAIN_WIDTH 5 /* DRC_STARTUP_GAIN - [10:6] */ 522*4882a593Smuzhiyun #define WM9081_DRC_FF_DLY 0x0020 /* DRC_FF_DLY */ 523*4882a593Smuzhiyun #define WM9081_DRC_FF_DLY_MASK 0x0020 /* DRC_FF_DLY */ 524*4882a593Smuzhiyun #define WM9081_DRC_FF_DLY_SHIFT 5 /* DRC_FF_DLY */ 525*4882a593Smuzhiyun #define WM9081_DRC_FF_DLY_WIDTH 1 /* DRC_FF_DLY */ 526*4882a593Smuzhiyun #define WM9081_DRC_QR 0x0004 /* DRC_QR */ 527*4882a593Smuzhiyun #define WM9081_DRC_QR_MASK 0x0004 /* DRC_QR */ 528*4882a593Smuzhiyun #define WM9081_DRC_QR_SHIFT 2 /* DRC_QR */ 529*4882a593Smuzhiyun #define WM9081_DRC_QR_WIDTH 1 /* DRC_QR */ 530*4882a593Smuzhiyun #define WM9081_DRC_ANTICLIP 0x0002 /* DRC_ANTICLIP */ 531*4882a593Smuzhiyun #define WM9081_DRC_ANTICLIP_MASK 0x0002 /* DRC_ANTICLIP */ 532*4882a593Smuzhiyun #define WM9081_DRC_ANTICLIP_SHIFT 1 /* DRC_ANTICLIP */ 533*4882a593Smuzhiyun #define WM9081_DRC_ANTICLIP_WIDTH 1 /* DRC_ANTICLIP */ 534*4882a593Smuzhiyun 535*4882a593Smuzhiyun /* 536*4882a593Smuzhiyun * R33 (0x21) - DRC 2 537*4882a593Smuzhiyun */ 538*4882a593Smuzhiyun #define WM9081_DRC_ATK_MASK 0xF000 /* DRC_ATK - [15:12] */ 539*4882a593Smuzhiyun #define WM9081_DRC_ATK_SHIFT 12 /* DRC_ATK - [15:12] */ 540*4882a593Smuzhiyun #define WM9081_DRC_ATK_WIDTH 4 /* DRC_ATK - [15:12] */ 541*4882a593Smuzhiyun #define WM9081_DRC_DCY_MASK 0x0F00 /* DRC_DCY - [11:8] */ 542*4882a593Smuzhiyun #define WM9081_DRC_DCY_SHIFT 8 /* DRC_DCY - [11:8] */ 543*4882a593Smuzhiyun #define WM9081_DRC_DCY_WIDTH 4 /* DRC_DCY - [11:8] */ 544*4882a593Smuzhiyun #define WM9081_DRC_QR_THR_MASK 0x00C0 /* DRC_QR_THR - [7:6] */ 545*4882a593Smuzhiyun #define WM9081_DRC_QR_THR_SHIFT 6 /* DRC_QR_THR - [7:6] */ 546*4882a593Smuzhiyun #define WM9081_DRC_QR_THR_WIDTH 2 /* DRC_QR_THR - [7:6] */ 547*4882a593Smuzhiyun #define WM9081_DRC_QR_DCY_MASK 0x0030 /* DRC_QR_DCY - [5:4] */ 548*4882a593Smuzhiyun #define WM9081_DRC_QR_DCY_SHIFT 4 /* DRC_QR_DCY - [5:4] */ 549*4882a593Smuzhiyun #define WM9081_DRC_QR_DCY_WIDTH 2 /* DRC_QR_DCY - [5:4] */ 550*4882a593Smuzhiyun #define WM9081_DRC_MINGAIN_MASK 0x000C /* DRC_MINGAIN - [3:2] */ 551*4882a593Smuzhiyun #define WM9081_DRC_MINGAIN_SHIFT 2 /* DRC_MINGAIN - [3:2] */ 552*4882a593Smuzhiyun #define WM9081_DRC_MINGAIN_WIDTH 2 /* DRC_MINGAIN - [3:2] */ 553*4882a593Smuzhiyun #define WM9081_DRC_MAXGAIN_MASK 0x0003 /* DRC_MAXGAIN - [1:0] */ 554*4882a593Smuzhiyun #define WM9081_DRC_MAXGAIN_SHIFT 0 /* DRC_MAXGAIN - [1:0] */ 555*4882a593Smuzhiyun #define WM9081_DRC_MAXGAIN_WIDTH 2 /* DRC_MAXGAIN - [1:0] */ 556*4882a593Smuzhiyun 557*4882a593Smuzhiyun /* 558*4882a593Smuzhiyun * R34 (0x22) - DRC 3 559*4882a593Smuzhiyun */ 560*4882a593Smuzhiyun #define WM9081_DRC_HI_COMP_MASK 0x0038 /* DRC_HI_COMP - [5:3] */ 561*4882a593Smuzhiyun #define WM9081_DRC_HI_COMP_SHIFT 3 /* DRC_HI_COMP - [5:3] */ 562*4882a593Smuzhiyun #define WM9081_DRC_HI_COMP_WIDTH 3 /* DRC_HI_COMP - [5:3] */ 563*4882a593Smuzhiyun #define WM9081_DRC_LO_COMP_MASK 0x0007 /* DRC_LO_COMP - [2:0] */ 564*4882a593Smuzhiyun #define WM9081_DRC_LO_COMP_SHIFT 0 /* DRC_LO_COMP - [2:0] */ 565*4882a593Smuzhiyun #define WM9081_DRC_LO_COMP_WIDTH 3 /* DRC_LO_COMP - [2:0] */ 566*4882a593Smuzhiyun 567*4882a593Smuzhiyun /* 568*4882a593Smuzhiyun * R35 (0x23) - DRC 4 569*4882a593Smuzhiyun */ 570*4882a593Smuzhiyun #define WM9081_DRC_KNEE_IP_MASK 0x07E0 /* DRC_KNEE_IP - [10:5] */ 571*4882a593Smuzhiyun #define WM9081_DRC_KNEE_IP_SHIFT 5 /* DRC_KNEE_IP - [10:5] */ 572*4882a593Smuzhiyun #define WM9081_DRC_KNEE_IP_WIDTH 6 /* DRC_KNEE_IP - [10:5] */ 573*4882a593Smuzhiyun #define WM9081_DRC_KNEE_OP_MASK 0x001F /* DRC_KNEE_OP - [4:0] */ 574*4882a593Smuzhiyun #define WM9081_DRC_KNEE_OP_SHIFT 0 /* DRC_KNEE_OP - [4:0] */ 575*4882a593Smuzhiyun #define WM9081_DRC_KNEE_OP_WIDTH 5 /* DRC_KNEE_OP - [4:0] */ 576*4882a593Smuzhiyun 577*4882a593Smuzhiyun /* 578*4882a593Smuzhiyun * R38 (0x26) - Write Sequencer 1 579*4882a593Smuzhiyun */ 580*4882a593Smuzhiyun #define WM9081_WSEQ_ENA 0x8000 /* WSEQ_ENA */ 581*4882a593Smuzhiyun #define WM9081_WSEQ_ENA_MASK 0x8000 /* WSEQ_ENA */ 582*4882a593Smuzhiyun #define WM9081_WSEQ_ENA_SHIFT 15 /* WSEQ_ENA */ 583*4882a593Smuzhiyun #define WM9081_WSEQ_ENA_WIDTH 1 /* WSEQ_ENA */ 584*4882a593Smuzhiyun #define WM9081_WSEQ_ABORT 0x0200 /* WSEQ_ABORT */ 585*4882a593Smuzhiyun #define WM9081_WSEQ_ABORT_MASK 0x0200 /* WSEQ_ABORT */ 586*4882a593Smuzhiyun #define WM9081_WSEQ_ABORT_SHIFT 9 /* WSEQ_ABORT */ 587*4882a593Smuzhiyun #define WM9081_WSEQ_ABORT_WIDTH 1 /* WSEQ_ABORT */ 588*4882a593Smuzhiyun #define WM9081_WSEQ_START 0x0100 /* WSEQ_START */ 589*4882a593Smuzhiyun #define WM9081_WSEQ_START_MASK 0x0100 /* WSEQ_START */ 590*4882a593Smuzhiyun #define WM9081_WSEQ_START_SHIFT 8 /* WSEQ_START */ 591*4882a593Smuzhiyun #define WM9081_WSEQ_START_WIDTH 1 /* WSEQ_START */ 592*4882a593Smuzhiyun #define WM9081_WSEQ_START_INDEX_MASK 0x007F /* WSEQ_START_INDEX - [6:0] */ 593*4882a593Smuzhiyun #define WM9081_WSEQ_START_INDEX_SHIFT 0 /* WSEQ_START_INDEX - [6:0] */ 594*4882a593Smuzhiyun #define WM9081_WSEQ_START_INDEX_WIDTH 7 /* WSEQ_START_INDEX - [6:0] */ 595*4882a593Smuzhiyun 596*4882a593Smuzhiyun /* 597*4882a593Smuzhiyun * R39 (0x27) - Write Sequencer 2 598*4882a593Smuzhiyun */ 599*4882a593Smuzhiyun #define WM9081_WSEQ_CURRENT_INDEX_MASK 0x07F0 /* WSEQ_CURRENT_INDEX - [10:4] */ 600*4882a593Smuzhiyun #define WM9081_WSEQ_CURRENT_INDEX_SHIFT 4 /* WSEQ_CURRENT_INDEX - [10:4] */ 601*4882a593Smuzhiyun #define WM9081_WSEQ_CURRENT_INDEX_WIDTH 7 /* WSEQ_CURRENT_INDEX - [10:4] */ 602*4882a593Smuzhiyun #define WM9081_WSEQ_BUSY 0x0001 /* WSEQ_BUSY */ 603*4882a593Smuzhiyun #define WM9081_WSEQ_BUSY_MASK 0x0001 /* WSEQ_BUSY */ 604*4882a593Smuzhiyun #define WM9081_WSEQ_BUSY_SHIFT 0 /* WSEQ_BUSY */ 605*4882a593Smuzhiyun #define WM9081_WSEQ_BUSY_WIDTH 1 /* WSEQ_BUSY */ 606*4882a593Smuzhiyun 607*4882a593Smuzhiyun /* 608*4882a593Smuzhiyun * R40 (0x28) - MW Slave 1 609*4882a593Smuzhiyun */ 610*4882a593Smuzhiyun #define WM9081_SPI_CFG 0x0020 /* SPI_CFG */ 611*4882a593Smuzhiyun #define WM9081_SPI_CFG_MASK 0x0020 /* SPI_CFG */ 612*4882a593Smuzhiyun #define WM9081_SPI_CFG_SHIFT 5 /* SPI_CFG */ 613*4882a593Smuzhiyun #define WM9081_SPI_CFG_WIDTH 1 /* SPI_CFG */ 614*4882a593Smuzhiyun #define WM9081_SPI_4WIRE 0x0010 /* SPI_4WIRE */ 615*4882a593Smuzhiyun #define WM9081_SPI_4WIRE_MASK 0x0010 /* SPI_4WIRE */ 616*4882a593Smuzhiyun #define WM9081_SPI_4WIRE_SHIFT 4 /* SPI_4WIRE */ 617*4882a593Smuzhiyun #define WM9081_SPI_4WIRE_WIDTH 1 /* SPI_4WIRE */ 618*4882a593Smuzhiyun #define WM9081_ARA_ENA 0x0008 /* ARA_ENA */ 619*4882a593Smuzhiyun #define WM9081_ARA_ENA_MASK 0x0008 /* ARA_ENA */ 620*4882a593Smuzhiyun #define WM9081_ARA_ENA_SHIFT 3 /* ARA_ENA */ 621*4882a593Smuzhiyun #define WM9081_ARA_ENA_WIDTH 1 /* ARA_ENA */ 622*4882a593Smuzhiyun #define WM9081_AUTO_INC 0x0002 /* AUTO_INC */ 623*4882a593Smuzhiyun #define WM9081_AUTO_INC_MASK 0x0002 /* AUTO_INC */ 624*4882a593Smuzhiyun #define WM9081_AUTO_INC_SHIFT 1 /* AUTO_INC */ 625*4882a593Smuzhiyun #define WM9081_AUTO_INC_WIDTH 1 /* AUTO_INC */ 626*4882a593Smuzhiyun 627*4882a593Smuzhiyun /* 628*4882a593Smuzhiyun * R42 (0x2A) - EQ 1 629*4882a593Smuzhiyun */ 630*4882a593Smuzhiyun #define WM9081_EQ_B1_GAIN_MASK 0xF800 /* EQ_B1_GAIN - [15:11] */ 631*4882a593Smuzhiyun #define WM9081_EQ_B1_GAIN_SHIFT 11 /* EQ_B1_GAIN - [15:11] */ 632*4882a593Smuzhiyun #define WM9081_EQ_B1_GAIN_WIDTH 5 /* EQ_B1_GAIN - [15:11] */ 633*4882a593Smuzhiyun #define WM9081_EQ_B2_GAIN_MASK 0x07C0 /* EQ_B2_GAIN - [10:6] */ 634*4882a593Smuzhiyun #define WM9081_EQ_B2_GAIN_SHIFT 6 /* EQ_B2_GAIN - [10:6] */ 635*4882a593Smuzhiyun #define WM9081_EQ_B2_GAIN_WIDTH 5 /* EQ_B2_GAIN - [10:6] */ 636*4882a593Smuzhiyun #define WM9081_EQ_B4_GAIN_MASK 0x003E /* EQ_B4_GAIN - [5:1] */ 637*4882a593Smuzhiyun #define WM9081_EQ_B4_GAIN_SHIFT 1 /* EQ_B4_GAIN - [5:1] */ 638*4882a593Smuzhiyun #define WM9081_EQ_B4_GAIN_WIDTH 5 /* EQ_B4_GAIN - [5:1] */ 639*4882a593Smuzhiyun #define WM9081_EQ_ENA 0x0001 /* EQ_ENA */ 640*4882a593Smuzhiyun #define WM9081_EQ_ENA_MASK 0x0001 /* EQ_ENA */ 641*4882a593Smuzhiyun #define WM9081_EQ_ENA_SHIFT 0 /* EQ_ENA */ 642*4882a593Smuzhiyun #define WM9081_EQ_ENA_WIDTH 1 /* EQ_ENA */ 643*4882a593Smuzhiyun 644*4882a593Smuzhiyun /* 645*4882a593Smuzhiyun * R43 (0x2B) - EQ 2 646*4882a593Smuzhiyun */ 647*4882a593Smuzhiyun #define WM9081_EQ_B3_GAIN_MASK 0xF800 /* EQ_B3_GAIN - [15:11] */ 648*4882a593Smuzhiyun #define WM9081_EQ_B3_GAIN_SHIFT 11 /* EQ_B3_GAIN - [15:11] */ 649*4882a593Smuzhiyun #define WM9081_EQ_B3_GAIN_WIDTH 5 /* EQ_B3_GAIN - [15:11] */ 650*4882a593Smuzhiyun #define WM9081_EQ_B5_GAIN_MASK 0x07C0 /* EQ_B5_GAIN - [10:6] */ 651*4882a593Smuzhiyun #define WM9081_EQ_B5_GAIN_SHIFT 6 /* EQ_B5_GAIN - [10:6] */ 652*4882a593Smuzhiyun #define WM9081_EQ_B5_GAIN_WIDTH 5 /* EQ_B5_GAIN - [10:6] */ 653*4882a593Smuzhiyun 654*4882a593Smuzhiyun /* 655*4882a593Smuzhiyun * R44 (0x2C) - EQ 3 656*4882a593Smuzhiyun */ 657*4882a593Smuzhiyun #define WM9081_EQ_B1_A_MASK 0xFFFF /* EQ_B1_A - [15:0] */ 658*4882a593Smuzhiyun #define WM9081_EQ_B1_A_SHIFT 0 /* EQ_B1_A - [15:0] */ 659*4882a593Smuzhiyun #define WM9081_EQ_B1_A_WIDTH 16 /* EQ_B1_A - [15:0] */ 660*4882a593Smuzhiyun 661*4882a593Smuzhiyun /* 662*4882a593Smuzhiyun * R45 (0x2D) - EQ 4 663*4882a593Smuzhiyun */ 664*4882a593Smuzhiyun #define WM9081_EQ_B1_B_MASK 0xFFFF /* EQ_B1_B - [15:0] */ 665*4882a593Smuzhiyun #define WM9081_EQ_B1_B_SHIFT 0 /* EQ_B1_B - [15:0] */ 666*4882a593Smuzhiyun #define WM9081_EQ_B1_B_WIDTH 16 /* EQ_B1_B - [15:0] */ 667*4882a593Smuzhiyun 668*4882a593Smuzhiyun /* 669*4882a593Smuzhiyun * R46 (0x2E) - EQ 5 670*4882a593Smuzhiyun */ 671*4882a593Smuzhiyun #define WM9081_EQ_B1_PG_MASK 0xFFFF /* EQ_B1_PG - [15:0] */ 672*4882a593Smuzhiyun #define WM9081_EQ_B1_PG_SHIFT 0 /* EQ_B1_PG - [15:0] */ 673*4882a593Smuzhiyun #define WM9081_EQ_B1_PG_WIDTH 16 /* EQ_B1_PG - [15:0] */ 674*4882a593Smuzhiyun 675*4882a593Smuzhiyun /* 676*4882a593Smuzhiyun * R47 (0x2F) - EQ 6 677*4882a593Smuzhiyun */ 678*4882a593Smuzhiyun #define WM9081_EQ_B2_A_MASK 0xFFFF /* EQ_B2_A - [15:0] */ 679*4882a593Smuzhiyun #define WM9081_EQ_B2_A_SHIFT 0 /* EQ_B2_A - [15:0] */ 680*4882a593Smuzhiyun #define WM9081_EQ_B2_A_WIDTH 16 /* EQ_B2_A - [15:0] */ 681*4882a593Smuzhiyun 682*4882a593Smuzhiyun /* 683*4882a593Smuzhiyun * R48 (0x30) - EQ 7 684*4882a593Smuzhiyun */ 685*4882a593Smuzhiyun #define WM9081_EQ_B2_B_MASK 0xFFFF /* EQ_B2_B - [15:0] */ 686*4882a593Smuzhiyun #define WM9081_EQ_B2_B_SHIFT 0 /* EQ_B2_B - [15:0] */ 687*4882a593Smuzhiyun #define WM9081_EQ_B2_B_WIDTH 16 /* EQ_B2_B - [15:0] */ 688*4882a593Smuzhiyun 689*4882a593Smuzhiyun /* 690*4882a593Smuzhiyun * R49 (0x31) - EQ 8 691*4882a593Smuzhiyun */ 692*4882a593Smuzhiyun #define WM9081_EQ_B2_C_MASK 0xFFFF /* EQ_B2_C - [15:0] */ 693*4882a593Smuzhiyun #define WM9081_EQ_B2_C_SHIFT 0 /* EQ_B2_C - [15:0] */ 694*4882a593Smuzhiyun #define WM9081_EQ_B2_C_WIDTH 16 /* EQ_B2_C - [15:0] */ 695*4882a593Smuzhiyun 696*4882a593Smuzhiyun /* 697*4882a593Smuzhiyun * R50 (0x32) - EQ 9 698*4882a593Smuzhiyun */ 699*4882a593Smuzhiyun #define WM9081_EQ_B2_PG_MASK 0xFFFF /* EQ_B2_PG - [15:0] */ 700*4882a593Smuzhiyun #define WM9081_EQ_B2_PG_SHIFT 0 /* EQ_B2_PG - [15:0] */ 701*4882a593Smuzhiyun #define WM9081_EQ_B2_PG_WIDTH 16 /* EQ_B2_PG - [15:0] */ 702*4882a593Smuzhiyun 703*4882a593Smuzhiyun /* 704*4882a593Smuzhiyun * R51 (0x33) - EQ 10 705*4882a593Smuzhiyun */ 706*4882a593Smuzhiyun #define WM9081_EQ_B4_A_MASK 0xFFFF /* EQ_B4_A - [15:0] */ 707*4882a593Smuzhiyun #define WM9081_EQ_B4_A_SHIFT 0 /* EQ_B4_A - [15:0] */ 708*4882a593Smuzhiyun #define WM9081_EQ_B4_A_WIDTH 16 /* EQ_B4_A - [15:0] */ 709*4882a593Smuzhiyun 710*4882a593Smuzhiyun /* 711*4882a593Smuzhiyun * R52 (0x34) - EQ 11 712*4882a593Smuzhiyun */ 713*4882a593Smuzhiyun #define WM9081_EQ_B4_B_MASK 0xFFFF /* EQ_B4_B - [15:0] */ 714*4882a593Smuzhiyun #define WM9081_EQ_B4_B_SHIFT 0 /* EQ_B4_B - [15:0] */ 715*4882a593Smuzhiyun #define WM9081_EQ_B4_B_WIDTH 16 /* EQ_B4_B - [15:0] */ 716*4882a593Smuzhiyun 717*4882a593Smuzhiyun /* 718*4882a593Smuzhiyun * R53 (0x35) - EQ 12 719*4882a593Smuzhiyun */ 720*4882a593Smuzhiyun #define WM9081_EQ_B4_C_MASK 0xFFFF /* EQ_B4_C - [15:0] */ 721*4882a593Smuzhiyun #define WM9081_EQ_B4_C_SHIFT 0 /* EQ_B4_C - [15:0] */ 722*4882a593Smuzhiyun #define WM9081_EQ_B4_C_WIDTH 16 /* EQ_B4_C - [15:0] */ 723*4882a593Smuzhiyun 724*4882a593Smuzhiyun /* 725*4882a593Smuzhiyun * R54 (0x36) - EQ 13 726*4882a593Smuzhiyun */ 727*4882a593Smuzhiyun #define WM9081_EQ_B4_PG_MASK 0xFFFF /* EQ_B4_PG - [15:0] */ 728*4882a593Smuzhiyun #define WM9081_EQ_B4_PG_SHIFT 0 /* EQ_B4_PG - [15:0] */ 729*4882a593Smuzhiyun #define WM9081_EQ_B4_PG_WIDTH 16 /* EQ_B4_PG - [15:0] */ 730*4882a593Smuzhiyun 731*4882a593Smuzhiyun /* 732*4882a593Smuzhiyun * R55 (0x37) - EQ 14 733*4882a593Smuzhiyun */ 734*4882a593Smuzhiyun #define WM9081_EQ_B3_A_MASK 0xFFFF /* EQ_B3_A - [15:0] */ 735*4882a593Smuzhiyun #define WM9081_EQ_B3_A_SHIFT 0 /* EQ_B3_A - [15:0] */ 736*4882a593Smuzhiyun #define WM9081_EQ_B3_A_WIDTH 16 /* EQ_B3_A - [15:0] */ 737*4882a593Smuzhiyun 738*4882a593Smuzhiyun /* 739*4882a593Smuzhiyun * R56 (0x38) - EQ 15 740*4882a593Smuzhiyun */ 741*4882a593Smuzhiyun #define WM9081_EQ_B3_B_MASK 0xFFFF /* EQ_B3_B - [15:0] */ 742*4882a593Smuzhiyun #define WM9081_EQ_B3_B_SHIFT 0 /* EQ_B3_B - [15:0] */ 743*4882a593Smuzhiyun #define WM9081_EQ_B3_B_WIDTH 16 /* EQ_B3_B - [15:0] */ 744*4882a593Smuzhiyun 745*4882a593Smuzhiyun /* 746*4882a593Smuzhiyun * R57 (0x39) - EQ 16 747*4882a593Smuzhiyun */ 748*4882a593Smuzhiyun #define WM9081_EQ_B3_C_MASK 0xFFFF /* EQ_B3_C - [15:0] */ 749*4882a593Smuzhiyun #define WM9081_EQ_B3_C_SHIFT 0 /* EQ_B3_C - [15:0] */ 750*4882a593Smuzhiyun #define WM9081_EQ_B3_C_WIDTH 16 /* EQ_B3_C - [15:0] */ 751*4882a593Smuzhiyun 752*4882a593Smuzhiyun /* 753*4882a593Smuzhiyun * R58 (0x3A) - EQ 17 754*4882a593Smuzhiyun */ 755*4882a593Smuzhiyun #define WM9081_EQ_B3_PG_MASK 0xFFFF /* EQ_B3_PG - [15:0] */ 756*4882a593Smuzhiyun #define WM9081_EQ_B3_PG_SHIFT 0 /* EQ_B3_PG - [15:0] */ 757*4882a593Smuzhiyun #define WM9081_EQ_B3_PG_WIDTH 16 /* EQ_B3_PG - [15:0] */ 758*4882a593Smuzhiyun 759*4882a593Smuzhiyun /* 760*4882a593Smuzhiyun * R59 (0x3B) - EQ 18 761*4882a593Smuzhiyun */ 762*4882a593Smuzhiyun #define WM9081_EQ_B5_A_MASK 0xFFFF /* EQ_B5_A - [15:0] */ 763*4882a593Smuzhiyun #define WM9081_EQ_B5_A_SHIFT 0 /* EQ_B5_A - [15:0] */ 764*4882a593Smuzhiyun #define WM9081_EQ_B5_A_WIDTH 16 /* EQ_B5_A - [15:0] */ 765*4882a593Smuzhiyun 766*4882a593Smuzhiyun /* 767*4882a593Smuzhiyun * R60 (0x3C) - EQ 19 768*4882a593Smuzhiyun */ 769*4882a593Smuzhiyun #define WM9081_EQ_B5_B_MASK 0xFFFF /* EQ_B5_B - [15:0] */ 770*4882a593Smuzhiyun #define WM9081_EQ_B5_B_SHIFT 0 /* EQ_B5_B - [15:0] */ 771*4882a593Smuzhiyun #define WM9081_EQ_B5_B_WIDTH 16 /* EQ_B5_B - [15:0] */ 772*4882a593Smuzhiyun 773*4882a593Smuzhiyun /* 774*4882a593Smuzhiyun * R61 (0x3D) - EQ 20 775*4882a593Smuzhiyun */ 776*4882a593Smuzhiyun #define WM9081_EQ_B5_PG_MASK 0xFFFF /* EQ_B5_PG - [15:0] */ 777*4882a593Smuzhiyun #define WM9081_EQ_B5_PG_SHIFT 0 /* EQ_B5_PG - [15:0] */ 778*4882a593Smuzhiyun #define WM9081_EQ_B5_PG_WIDTH 16 /* EQ_B5_PG - [15:0] */ 779*4882a593Smuzhiyun 780*4882a593Smuzhiyun 781*4882a593Smuzhiyun #endif 782