1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * wm8996.h - WM8996 audio codec interface 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright 2011 Wolfson Microelectronics PLC. 6*4882a593Smuzhiyun * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef _WM8996_H 10*4882a593Smuzhiyun #define _WM8996_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define WM8996_SYSCLK_MCLK1 1 13*4882a593Smuzhiyun #define WM8996_SYSCLK_MCLK2 2 14*4882a593Smuzhiyun #define WM8996_SYSCLK_FLL 3 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #define WM8996_FLL_MCLK1 1 17*4882a593Smuzhiyun #define WM8996_FLL_MCLK2 2 18*4882a593Smuzhiyun #define WM8996_FLL_DACLRCLK1 3 19*4882a593Smuzhiyun #define WM8996_FLL_BCLK1 4 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun typedef void (*wm8996_polarity_fn)(struct snd_soc_component *component, int polarity); 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun int wm8996_detect(struct snd_soc_component *component, struct snd_soc_jack *jack, 24*4882a593Smuzhiyun wm8996_polarity_fn polarity_cb); 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun /* 27*4882a593Smuzhiyun * Register values. 28*4882a593Smuzhiyun */ 29*4882a593Smuzhiyun #define WM8996_SOFTWARE_RESET 0x00 30*4882a593Smuzhiyun #define WM8996_POWER_MANAGEMENT_1 0x01 31*4882a593Smuzhiyun #define WM8996_POWER_MANAGEMENT_2 0x02 32*4882a593Smuzhiyun #define WM8996_POWER_MANAGEMENT_3 0x03 33*4882a593Smuzhiyun #define WM8996_POWER_MANAGEMENT_4 0x04 34*4882a593Smuzhiyun #define WM8996_POWER_MANAGEMENT_5 0x05 35*4882a593Smuzhiyun #define WM8996_POWER_MANAGEMENT_6 0x06 36*4882a593Smuzhiyun #define WM8996_POWER_MANAGEMENT_7 0x07 37*4882a593Smuzhiyun #define WM8996_POWER_MANAGEMENT_8 0x08 38*4882a593Smuzhiyun #define WM8996_LEFT_LINE_INPUT_VOLUME 0x10 39*4882a593Smuzhiyun #define WM8996_RIGHT_LINE_INPUT_VOLUME 0x11 40*4882a593Smuzhiyun #define WM8996_LINE_INPUT_CONTROL 0x12 41*4882a593Smuzhiyun #define WM8996_DAC1_HPOUT1_VOLUME 0x15 42*4882a593Smuzhiyun #define WM8996_DAC2_HPOUT2_VOLUME 0x16 43*4882a593Smuzhiyun #define WM8996_DAC1_LEFT_VOLUME 0x18 44*4882a593Smuzhiyun #define WM8996_DAC1_RIGHT_VOLUME 0x19 45*4882a593Smuzhiyun #define WM8996_DAC2_LEFT_VOLUME 0x1A 46*4882a593Smuzhiyun #define WM8996_DAC2_RIGHT_VOLUME 0x1B 47*4882a593Smuzhiyun #define WM8996_OUTPUT1_LEFT_VOLUME 0x1C 48*4882a593Smuzhiyun #define WM8996_OUTPUT1_RIGHT_VOLUME 0x1D 49*4882a593Smuzhiyun #define WM8996_OUTPUT2_LEFT_VOLUME 0x1E 50*4882a593Smuzhiyun #define WM8996_OUTPUT2_RIGHT_VOLUME 0x1F 51*4882a593Smuzhiyun #define WM8996_MICBIAS_1 0x20 52*4882a593Smuzhiyun #define WM8996_MICBIAS_2 0x21 53*4882a593Smuzhiyun #define WM8996_LDO_1 0x28 54*4882a593Smuzhiyun #define WM8996_LDO_2 0x29 55*4882a593Smuzhiyun #define WM8996_ACCESSORY_DETECT_MODE_1 0x30 56*4882a593Smuzhiyun #define WM8996_ACCESSORY_DETECT_MODE_2 0x31 57*4882a593Smuzhiyun #define WM8996_HEADPHONE_DETECT_1 0x34 58*4882a593Smuzhiyun #define WM8996_HEADPHONE_DETECT_2 0x35 59*4882a593Smuzhiyun #define WM8996_MIC_DETECT_1 0x38 60*4882a593Smuzhiyun #define WM8996_MIC_DETECT_2 0x39 61*4882a593Smuzhiyun #define WM8996_MIC_DETECT_3 0x3A 62*4882a593Smuzhiyun #define WM8996_CHARGE_PUMP_1 0x40 63*4882a593Smuzhiyun #define WM8996_CHARGE_PUMP_2 0x41 64*4882a593Smuzhiyun #define WM8996_DC_SERVO_1 0x50 65*4882a593Smuzhiyun #define WM8996_DC_SERVO_2 0x51 66*4882a593Smuzhiyun #define WM8996_DC_SERVO_3 0x52 67*4882a593Smuzhiyun #define WM8996_DC_SERVO_5 0x54 68*4882a593Smuzhiyun #define WM8996_DC_SERVO_6 0x55 69*4882a593Smuzhiyun #define WM8996_DC_SERVO_7 0x56 70*4882a593Smuzhiyun #define WM8996_DC_SERVO_READBACK_0 0x57 71*4882a593Smuzhiyun #define WM8996_ANALOGUE_HP_1 0x60 72*4882a593Smuzhiyun #define WM8996_ANALOGUE_HP_2 0x61 73*4882a593Smuzhiyun #define WM8996_CHIP_REVISION 0x100 74*4882a593Smuzhiyun #define WM8996_CONTROL_INTERFACE_1 0x101 75*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_CTRL_1 0x110 76*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_CTRL_2 0x111 77*4882a593Smuzhiyun #define WM8996_AIF_CLOCKING_1 0x200 78*4882a593Smuzhiyun #define WM8996_AIF_CLOCKING_2 0x201 79*4882a593Smuzhiyun #define WM8996_CLOCKING_1 0x208 80*4882a593Smuzhiyun #define WM8996_CLOCKING_2 0x209 81*4882a593Smuzhiyun #define WM8996_AIF_RATE 0x210 82*4882a593Smuzhiyun #define WM8996_FLL_CONTROL_1 0x220 83*4882a593Smuzhiyun #define WM8996_FLL_CONTROL_2 0x221 84*4882a593Smuzhiyun #define WM8996_FLL_CONTROL_3 0x222 85*4882a593Smuzhiyun #define WM8996_FLL_CONTROL_4 0x223 86*4882a593Smuzhiyun #define WM8996_FLL_CONTROL_5 0x224 87*4882a593Smuzhiyun #define WM8996_FLL_CONTROL_6 0x225 88*4882a593Smuzhiyun #define WM8996_FLL_EFS_1 0x226 89*4882a593Smuzhiyun #define WM8996_FLL_EFS_2 0x227 90*4882a593Smuzhiyun #define WM8996_AIF1_CONTROL 0x300 91*4882a593Smuzhiyun #define WM8996_AIF1_BCLK 0x301 92*4882a593Smuzhiyun #define WM8996_AIF1_TX_LRCLK_1 0x302 93*4882a593Smuzhiyun #define WM8996_AIF1_TX_LRCLK_2 0x303 94*4882a593Smuzhiyun #define WM8996_AIF1_RX_LRCLK_1 0x304 95*4882a593Smuzhiyun #define WM8996_AIF1_RX_LRCLK_2 0x305 96*4882a593Smuzhiyun #define WM8996_AIF1TX_DATA_CONFIGURATION_1 0x306 97*4882a593Smuzhiyun #define WM8996_AIF1TX_DATA_CONFIGURATION_2 0x307 98*4882a593Smuzhiyun #define WM8996_AIF1RX_DATA_CONFIGURATION 0x308 99*4882a593Smuzhiyun #define WM8996_AIF1TX_CHANNEL_0_CONFIGURATION 0x309 100*4882a593Smuzhiyun #define WM8996_AIF1TX_CHANNEL_1_CONFIGURATION 0x30A 101*4882a593Smuzhiyun #define WM8996_AIF1TX_CHANNEL_2_CONFIGURATION 0x30B 102*4882a593Smuzhiyun #define WM8996_AIF1TX_CHANNEL_3_CONFIGURATION 0x30C 103*4882a593Smuzhiyun #define WM8996_AIF1TX_CHANNEL_4_CONFIGURATION 0x30D 104*4882a593Smuzhiyun #define WM8996_AIF1TX_CHANNEL_5_CONFIGURATION 0x30E 105*4882a593Smuzhiyun #define WM8996_AIF1RX_CHANNEL_0_CONFIGURATION 0x30F 106*4882a593Smuzhiyun #define WM8996_AIF1RX_CHANNEL_1_CONFIGURATION 0x310 107*4882a593Smuzhiyun #define WM8996_AIF1RX_CHANNEL_2_CONFIGURATION 0x311 108*4882a593Smuzhiyun #define WM8996_AIF1RX_CHANNEL_3_CONFIGURATION 0x312 109*4882a593Smuzhiyun #define WM8996_AIF1RX_CHANNEL_4_CONFIGURATION 0x313 110*4882a593Smuzhiyun #define WM8996_AIF1RX_CHANNEL_5_CONFIGURATION 0x314 111*4882a593Smuzhiyun #define WM8996_AIF1RX_MONO_CONFIGURATION 0x315 112*4882a593Smuzhiyun #define WM8996_AIF1TX_TEST 0x31A 113*4882a593Smuzhiyun #define WM8996_AIF2_CONTROL 0x320 114*4882a593Smuzhiyun #define WM8996_AIF2_BCLK 0x321 115*4882a593Smuzhiyun #define WM8996_AIF2_TX_LRCLK_1 0x322 116*4882a593Smuzhiyun #define WM8996_AIF2_TX_LRCLK_2 0x323 117*4882a593Smuzhiyun #define WM8996_AIF2_RX_LRCLK_1 0x324 118*4882a593Smuzhiyun #define WM8996_AIF2_RX_LRCLK_2 0x325 119*4882a593Smuzhiyun #define WM8996_AIF2TX_DATA_CONFIGURATION_1 0x326 120*4882a593Smuzhiyun #define WM8996_AIF2TX_DATA_CONFIGURATION_2 0x327 121*4882a593Smuzhiyun #define WM8996_AIF2RX_DATA_CONFIGURATION 0x328 122*4882a593Smuzhiyun #define WM8996_AIF2TX_CHANNEL_0_CONFIGURATION 0x329 123*4882a593Smuzhiyun #define WM8996_AIF2TX_CHANNEL_1_CONFIGURATION 0x32A 124*4882a593Smuzhiyun #define WM8996_AIF2RX_CHANNEL_0_CONFIGURATION 0x32B 125*4882a593Smuzhiyun #define WM8996_AIF2RX_CHANNEL_1_CONFIGURATION 0x32C 126*4882a593Smuzhiyun #define WM8996_AIF2RX_MONO_CONFIGURATION 0x32D 127*4882a593Smuzhiyun #define WM8996_AIF2TX_TEST 0x32F 128*4882a593Smuzhiyun #define WM8996_DSP1_TX_LEFT_VOLUME 0x400 129*4882a593Smuzhiyun #define WM8996_DSP1_TX_RIGHT_VOLUME 0x401 130*4882a593Smuzhiyun #define WM8996_DSP1_RX_LEFT_VOLUME 0x402 131*4882a593Smuzhiyun #define WM8996_DSP1_RX_RIGHT_VOLUME 0x403 132*4882a593Smuzhiyun #define WM8996_DSP1_TX_FILTERS 0x410 133*4882a593Smuzhiyun #define WM8996_DSP1_RX_FILTERS_1 0x420 134*4882a593Smuzhiyun #define WM8996_DSP1_RX_FILTERS_2 0x421 135*4882a593Smuzhiyun #define WM8996_DSP1_DRC_1 0x440 136*4882a593Smuzhiyun #define WM8996_DSP1_DRC_2 0x441 137*4882a593Smuzhiyun #define WM8996_DSP1_DRC_3 0x442 138*4882a593Smuzhiyun #define WM8996_DSP1_DRC_4 0x443 139*4882a593Smuzhiyun #define WM8996_DSP1_DRC_5 0x444 140*4882a593Smuzhiyun #define WM8996_DSP1_RX_EQ_GAINS_1 0x480 141*4882a593Smuzhiyun #define WM8996_DSP1_RX_EQ_GAINS_2 0x481 142*4882a593Smuzhiyun #define WM8996_DSP1_RX_EQ_BAND_1_A 0x482 143*4882a593Smuzhiyun #define WM8996_DSP1_RX_EQ_BAND_1_B 0x483 144*4882a593Smuzhiyun #define WM8996_DSP1_RX_EQ_BAND_1_PG 0x484 145*4882a593Smuzhiyun #define WM8996_DSP1_RX_EQ_BAND_2_A 0x485 146*4882a593Smuzhiyun #define WM8996_DSP1_RX_EQ_BAND_2_B 0x486 147*4882a593Smuzhiyun #define WM8996_DSP1_RX_EQ_BAND_2_C 0x487 148*4882a593Smuzhiyun #define WM8996_DSP1_RX_EQ_BAND_2_PG 0x488 149*4882a593Smuzhiyun #define WM8996_DSP1_RX_EQ_BAND_3_A 0x489 150*4882a593Smuzhiyun #define WM8996_DSP1_RX_EQ_BAND_3_B 0x48A 151*4882a593Smuzhiyun #define WM8996_DSP1_RX_EQ_BAND_3_C 0x48B 152*4882a593Smuzhiyun #define WM8996_DSP1_RX_EQ_BAND_3_PG 0x48C 153*4882a593Smuzhiyun #define WM8996_DSP1_RX_EQ_BAND_4_A 0x48D 154*4882a593Smuzhiyun #define WM8996_DSP1_RX_EQ_BAND_4_B 0x48E 155*4882a593Smuzhiyun #define WM8996_DSP1_RX_EQ_BAND_4_C 0x48F 156*4882a593Smuzhiyun #define WM8996_DSP1_RX_EQ_BAND_4_PG 0x490 157*4882a593Smuzhiyun #define WM8996_DSP1_RX_EQ_BAND_5_A 0x491 158*4882a593Smuzhiyun #define WM8996_DSP1_RX_EQ_BAND_5_B 0x492 159*4882a593Smuzhiyun #define WM8996_DSP1_RX_EQ_BAND_5_PG 0x493 160*4882a593Smuzhiyun #define WM8996_DSP2_TX_LEFT_VOLUME 0x500 161*4882a593Smuzhiyun #define WM8996_DSP2_TX_RIGHT_VOLUME 0x501 162*4882a593Smuzhiyun #define WM8996_DSP2_RX_LEFT_VOLUME 0x502 163*4882a593Smuzhiyun #define WM8996_DSP2_RX_RIGHT_VOLUME 0x503 164*4882a593Smuzhiyun #define WM8996_DSP2_TX_FILTERS 0x510 165*4882a593Smuzhiyun #define WM8996_DSP2_RX_FILTERS_1 0x520 166*4882a593Smuzhiyun #define WM8996_DSP2_RX_FILTERS_2 0x521 167*4882a593Smuzhiyun #define WM8996_DSP2_DRC_1 0x540 168*4882a593Smuzhiyun #define WM8996_DSP2_DRC_2 0x541 169*4882a593Smuzhiyun #define WM8996_DSP2_DRC_3 0x542 170*4882a593Smuzhiyun #define WM8996_DSP2_DRC_4 0x543 171*4882a593Smuzhiyun #define WM8996_DSP2_DRC_5 0x544 172*4882a593Smuzhiyun #define WM8996_DSP2_RX_EQ_GAINS_1 0x580 173*4882a593Smuzhiyun #define WM8996_DSP2_RX_EQ_GAINS_2 0x581 174*4882a593Smuzhiyun #define WM8996_DSP2_RX_EQ_BAND_1_A 0x582 175*4882a593Smuzhiyun #define WM8996_DSP2_RX_EQ_BAND_1_B 0x583 176*4882a593Smuzhiyun #define WM8996_DSP2_RX_EQ_BAND_1_PG 0x584 177*4882a593Smuzhiyun #define WM8996_DSP2_RX_EQ_BAND_2_A 0x585 178*4882a593Smuzhiyun #define WM8996_DSP2_RX_EQ_BAND_2_B 0x586 179*4882a593Smuzhiyun #define WM8996_DSP2_RX_EQ_BAND_2_C 0x587 180*4882a593Smuzhiyun #define WM8996_DSP2_RX_EQ_BAND_2_PG 0x588 181*4882a593Smuzhiyun #define WM8996_DSP2_RX_EQ_BAND_3_A 0x589 182*4882a593Smuzhiyun #define WM8996_DSP2_RX_EQ_BAND_3_B 0x58A 183*4882a593Smuzhiyun #define WM8996_DSP2_RX_EQ_BAND_3_C 0x58B 184*4882a593Smuzhiyun #define WM8996_DSP2_RX_EQ_BAND_3_PG 0x58C 185*4882a593Smuzhiyun #define WM8996_DSP2_RX_EQ_BAND_4_A 0x58D 186*4882a593Smuzhiyun #define WM8996_DSP2_RX_EQ_BAND_4_B 0x58E 187*4882a593Smuzhiyun #define WM8996_DSP2_RX_EQ_BAND_4_C 0x58F 188*4882a593Smuzhiyun #define WM8996_DSP2_RX_EQ_BAND_4_PG 0x590 189*4882a593Smuzhiyun #define WM8996_DSP2_RX_EQ_BAND_5_A 0x591 190*4882a593Smuzhiyun #define WM8996_DSP2_RX_EQ_BAND_5_B 0x592 191*4882a593Smuzhiyun #define WM8996_DSP2_RX_EQ_BAND_5_PG 0x593 192*4882a593Smuzhiyun #define WM8996_DAC1_MIXER_VOLUMES 0x600 193*4882a593Smuzhiyun #define WM8996_DAC1_LEFT_MIXER_ROUTING 0x601 194*4882a593Smuzhiyun #define WM8996_DAC1_RIGHT_MIXER_ROUTING 0x602 195*4882a593Smuzhiyun #define WM8996_DAC2_MIXER_VOLUMES 0x603 196*4882a593Smuzhiyun #define WM8996_DAC2_LEFT_MIXER_ROUTING 0x604 197*4882a593Smuzhiyun #define WM8996_DAC2_RIGHT_MIXER_ROUTING 0x605 198*4882a593Smuzhiyun #define WM8996_DSP1_TX_LEFT_MIXER_ROUTING 0x606 199*4882a593Smuzhiyun #define WM8996_DSP1_TX_RIGHT_MIXER_ROUTING 0x607 200*4882a593Smuzhiyun #define WM8996_DSP2_TX_LEFT_MIXER_ROUTING 0x608 201*4882a593Smuzhiyun #define WM8996_DSP2_TX_RIGHT_MIXER_ROUTING 0x609 202*4882a593Smuzhiyun #define WM8996_DSP_TX_MIXER_SELECT 0x60A 203*4882a593Smuzhiyun #define WM8996_DAC_SOFTMUTE 0x610 204*4882a593Smuzhiyun #define WM8996_OVERSAMPLING 0x620 205*4882a593Smuzhiyun #define WM8996_SIDETONE 0x621 206*4882a593Smuzhiyun #define WM8996_GPIO_1 0x700 207*4882a593Smuzhiyun #define WM8996_GPIO_2 0x701 208*4882a593Smuzhiyun #define WM8996_GPIO_3 0x702 209*4882a593Smuzhiyun #define WM8996_GPIO_4 0x703 210*4882a593Smuzhiyun #define WM8996_GPIO_5 0x704 211*4882a593Smuzhiyun #define WM8996_PULL_CONTROL_1 0x720 212*4882a593Smuzhiyun #define WM8996_PULL_CONTROL_2 0x721 213*4882a593Smuzhiyun #define WM8996_INTERRUPT_STATUS_1 0x730 214*4882a593Smuzhiyun #define WM8996_INTERRUPT_STATUS_2 0x731 215*4882a593Smuzhiyun #define WM8996_INTERRUPT_RAW_STATUS_2 0x732 216*4882a593Smuzhiyun #define WM8996_INTERRUPT_STATUS_1_MASK 0x738 217*4882a593Smuzhiyun #define WM8996_INTERRUPT_STATUS_2_MASK 0x739 218*4882a593Smuzhiyun #define WM8996_INTERRUPT_CONTROL 0x740 219*4882a593Smuzhiyun #define WM8996_LEFT_PDM_SPEAKER 0x800 220*4882a593Smuzhiyun #define WM8996_RIGHT_PDM_SPEAKER 0x801 221*4882a593Smuzhiyun #define WM8996_PDM_SPEAKER_MUTE_SEQUENCE 0x802 222*4882a593Smuzhiyun #define WM8996_PDM_SPEAKER_VOLUME 0x803 223*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_0 0x3000 224*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_1 0x3001 225*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_2 0x3002 226*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_3 0x3003 227*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_4 0x3004 228*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_5 0x3005 229*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_6 0x3006 230*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_7 0x3007 231*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_8 0x3008 232*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_9 0x3009 233*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_10 0x300A 234*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_11 0x300B 235*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_12 0x300C 236*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_13 0x300D 237*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_14 0x300E 238*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_15 0x300F 239*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_16 0x3010 240*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_17 0x3011 241*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_18 0x3012 242*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_19 0x3013 243*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_20 0x3014 244*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_21 0x3015 245*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_22 0x3016 246*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_23 0x3017 247*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_24 0x3018 248*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_25 0x3019 249*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_26 0x301A 250*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_27 0x301B 251*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_28 0x301C 252*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_29 0x301D 253*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_30 0x301E 254*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_31 0x301F 255*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_32 0x3020 256*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_33 0x3021 257*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_34 0x3022 258*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_35 0x3023 259*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_36 0x3024 260*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_37 0x3025 261*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_38 0x3026 262*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_39 0x3027 263*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_40 0x3028 264*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_41 0x3029 265*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_42 0x302A 266*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_43 0x302B 267*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_44 0x302C 268*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_45 0x302D 269*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_46 0x302E 270*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_47 0x302F 271*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_48 0x3030 272*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_49 0x3031 273*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_50 0x3032 274*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_51 0x3033 275*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_52 0x3034 276*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_53 0x3035 277*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_54 0x3036 278*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_55 0x3037 279*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_56 0x3038 280*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_57 0x3039 281*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_58 0x303A 282*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_59 0x303B 283*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_60 0x303C 284*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_61 0x303D 285*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_62 0x303E 286*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_63 0x303F 287*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_64 0x3040 288*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_65 0x3041 289*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_66 0x3042 290*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_67 0x3043 291*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_68 0x3044 292*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_69 0x3045 293*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_70 0x3046 294*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_71 0x3047 295*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_72 0x3048 296*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_73 0x3049 297*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_74 0x304A 298*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_75 0x304B 299*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_76 0x304C 300*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_77 0x304D 301*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_78 0x304E 302*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_79 0x304F 303*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_80 0x3050 304*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_81 0x3051 305*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_82 0x3052 306*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_83 0x3053 307*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_84 0x3054 308*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_85 0x3055 309*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_86 0x3056 310*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_87 0x3057 311*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_88 0x3058 312*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_89 0x3059 313*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_90 0x305A 314*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_91 0x305B 315*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_92 0x305C 316*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_93 0x305D 317*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_94 0x305E 318*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_95 0x305F 319*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_96 0x3060 320*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_97 0x3061 321*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_98 0x3062 322*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_99 0x3063 323*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_100 0x3064 324*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_101 0x3065 325*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_102 0x3066 326*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_103 0x3067 327*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_104 0x3068 328*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_105 0x3069 329*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_106 0x306A 330*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_107 0x306B 331*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_108 0x306C 332*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_109 0x306D 333*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_110 0x306E 334*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_111 0x306F 335*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_112 0x3070 336*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_113 0x3071 337*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_114 0x3072 338*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_115 0x3073 339*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_116 0x3074 340*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_117 0x3075 341*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_118 0x3076 342*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_119 0x3077 343*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_120 0x3078 344*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_121 0x3079 345*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_122 0x307A 346*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_123 0x307B 347*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_124 0x307C 348*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_125 0x307D 349*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_126 0x307E 350*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_127 0x307F 351*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_128 0x3080 352*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_129 0x3081 353*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_130 0x3082 354*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_131 0x3083 355*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_132 0x3084 356*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_133 0x3085 357*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_134 0x3086 358*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_135 0x3087 359*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_136 0x3088 360*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_137 0x3089 361*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_138 0x308A 362*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_139 0x308B 363*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_140 0x308C 364*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_141 0x308D 365*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_142 0x308E 366*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_143 0x308F 367*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_144 0x3090 368*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_145 0x3091 369*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_146 0x3092 370*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_147 0x3093 371*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_148 0x3094 372*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_149 0x3095 373*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_150 0x3096 374*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_151 0x3097 375*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_152 0x3098 376*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_153 0x3099 377*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_154 0x309A 378*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_155 0x309B 379*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_156 0x309C 380*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_157 0x309D 381*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_158 0x309E 382*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_159 0x309F 383*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_160 0x30A0 384*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_161 0x30A1 385*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_162 0x30A2 386*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_163 0x30A3 387*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_164 0x30A4 388*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_165 0x30A5 389*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_166 0x30A6 390*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_167 0x30A7 391*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_168 0x30A8 392*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_169 0x30A9 393*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_170 0x30AA 394*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_171 0x30AB 395*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_172 0x30AC 396*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_173 0x30AD 397*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_174 0x30AE 398*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_175 0x30AF 399*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_176 0x30B0 400*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_177 0x30B1 401*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_178 0x30B2 402*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_179 0x30B3 403*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_180 0x30B4 404*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_181 0x30B5 405*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_182 0x30B6 406*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_183 0x30B7 407*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_184 0x30B8 408*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_185 0x30B9 409*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_186 0x30BA 410*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_187 0x30BB 411*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_188 0x30BC 412*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_189 0x30BD 413*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_190 0x30BE 414*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_191 0x30BF 415*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_192 0x30C0 416*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_193 0x30C1 417*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_194 0x30C2 418*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_195 0x30C3 419*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_196 0x30C4 420*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_197 0x30C5 421*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_198 0x30C6 422*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_199 0x30C7 423*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_200 0x30C8 424*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_201 0x30C9 425*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_202 0x30CA 426*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_203 0x30CB 427*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_204 0x30CC 428*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_205 0x30CD 429*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_206 0x30CE 430*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_207 0x30CF 431*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_208 0x30D0 432*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_209 0x30D1 433*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_210 0x30D2 434*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_211 0x30D3 435*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_212 0x30D4 436*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_213 0x30D5 437*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_214 0x30D6 438*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_215 0x30D7 439*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_216 0x30D8 440*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_217 0x30D9 441*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_218 0x30DA 442*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_219 0x30DB 443*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_220 0x30DC 444*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_221 0x30DD 445*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_222 0x30DE 446*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_223 0x30DF 447*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_224 0x30E0 448*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_225 0x30E1 449*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_226 0x30E2 450*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_227 0x30E3 451*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_228 0x30E4 452*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_229 0x30E5 453*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_230 0x30E6 454*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_231 0x30E7 455*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_232 0x30E8 456*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_233 0x30E9 457*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_234 0x30EA 458*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_235 0x30EB 459*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_236 0x30EC 460*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_237 0x30ED 461*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_238 0x30EE 462*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_239 0x30EF 463*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_240 0x30F0 464*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_241 0x30F1 465*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_242 0x30F2 466*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_243 0x30F3 467*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_244 0x30F4 468*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_245 0x30F5 469*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_246 0x30F6 470*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_247 0x30F7 471*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_248 0x30F8 472*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_249 0x30F9 473*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_250 0x30FA 474*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_251 0x30FB 475*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_252 0x30FC 476*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_253 0x30FD 477*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_254 0x30FE 478*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_255 0x30FF 479*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_256 0x3100 480*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_257 0x3101 481*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_258 0x3102 482*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_259 0x3103 483*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_260 0x3104 484*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_261 0x3105 485*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_262 0x3106 486*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_263 0x3107 487*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_264 0x3108 488*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_265 0x3109 489*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_266 0x310A 490*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_267 0x310B 491*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_268 0x310C 492*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_269 0x310D 493*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_270 0x310E 494*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_271 0x310F 495*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_272 0x3110 496*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_273 0x3111 497*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_274 0x3112 498*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_275 0x3113 499*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_276 0x3114 500*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_277 0x3115 501*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_278 0x3116 502*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_279 0x3117 503*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_280 0x3118 504*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_281 0x3119 505*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_282 0x311A 506*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_283 0x311B 507*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_284 0x311C 508*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_285 0x311D 509*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_286 0x311E 510*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_287 0x311F 511*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_288 0x3120 512*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_289 0x3121 513*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_290 0x3122 514*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_291 0x3123 515*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_292 0x3124 516*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_293 0x3125 517*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_294 0x3126 518*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_295 0x3127 519*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_296 0x3128 520*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_297 0x3129 521*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_298 0x312A 522*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_299 0x312B 523*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_300 0x312C 524*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_301 0x312D 525*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_302 0x312E 526*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_303 0x312F 527*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_304 0x3130 528*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_305 0x3131 529*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_306 0x3132 530*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_307 0x3133 531*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_308 0x3134 532*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_309 0x3135 533*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_310 0x3136 534*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_311 0x3137 535*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_312 0x3138 536*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_313 0x3139 537*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_314 0x313A 538*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_315 0x313B 539*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_316 0x313C 540*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_317 0x313D 541*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_318 0x313E 542*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_319 0x313F 543*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_320 0x3140 544*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_321 0x3141 545*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_322 0x3142 546*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_323 0x3143 547*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_324 0x3144 548*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_325 0x3145 549*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_326 0x3146 550*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_327 0x3147 551*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_328 0x3148 552*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_329 0x3149 553*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_330 0x314A 554*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_331 0x314B 555*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_332 0x314C 556*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_333 0x314D 557*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_334 0x314E 558*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_335 0x314F 559*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_336 0x3150 560*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_337 0x3151 561*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_338 0x3152 562*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_339 0x3153 563*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_340 0x3154 564*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_341 0x3155 565*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_342 0x3156 566*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_343 0x3157 567*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_344 0x3158 568*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_345 0x3159 569*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_346 0x315A 570*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_347 0x315B 571*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_348 0x315C 572*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_349 0x315D 573*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_350 0x315E 574*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_351 0x315F 575*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_352 0x3160 576*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_353 0x3161 577*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_354 0x3162 578*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_355 0x3163 579*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_356 0x3164 580*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_357 0x3165 581*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_358 0x3166 582*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_359 0x3167 583*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_360 0x3168 584*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_361 0x3169 585*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_362 0x316A 586*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_363 0x316B 587*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_364 0x316C 588*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_365 0x316D 589*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_366 0x316E 590*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_367 0x316F 591*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_368 0x3170 592*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_369 0x3171 593*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_370 0x3172 594*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_371 0x3173 595*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_372 0x3174 596*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_373 0x3175 597*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_374 0x3176 598*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_375 0x3177 599*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_376 0x3178 600*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_377 0x3179 601*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_378 0x317A 602*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_379 0x317B 603*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_380 0x317C 604*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_381 0x317D 605*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_382 0x317E 606*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_383 0x317F 607*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_384 0x3180 608*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_385 0x3181 609*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_386 0x3182 610*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_387 0x3183 611*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_388 0x3184 612*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_389 0x3185 613*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_390 0x3186 614*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_391 0x3187 615*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_392 0x3188 616*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_393 0x3189 617*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_394 0x318A 618*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_395 0x318B 619*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_396 0x318C 620*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_397 0x318D 621*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_398 0x318E 622*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_399 0x318F 623*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_400 0x3190 624*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_401 0x3191 625*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_402 0x3192 626*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_403 0x3193 627*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_404 0x3194 628*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_405 0x3195 629*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_406 0x3196 630*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_407 0x3197 631*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_408 0x3198 632*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_409 0x3199 633*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_410 0x319A 634*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_411 0x319B 635*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_412 0x319C 636*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_413 0x319D 637*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_414 0x319E 638*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_415 0x319F 639*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_416 0x31A0 640*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_417 0x31A1 641*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_418 0x31A2 642*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_419 0x31A3 643*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_420 0x31A4 644*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_421 0x31A5 645*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_422 0x31A6 646*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_423 0x31A7 647*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_424 0x31A8 648*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_425 0x31A9 649*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_426 0x31AA 650*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_427 0x31AB 651*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_428 0x31AC 652*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_429 0x31AD 653*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_430 0x31AE 654*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_431 0x31AF 655*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_432 0x31B0 656*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_433 0x31B1 657*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_434 0x31B2 658*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_435 0x31B3 659*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_436 0x31B4 660*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_437 0x31B5 661*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_438 0x31B6 662*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_439 0x31B7 663*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_440 0x31B8 664*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_441 0x31B9 665*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_442 0x31BA 666*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_443 0x31BB 667*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_444 0x31BC 668*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_445 0x31BD 669*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_446 0x31BE 670*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_447 0x31BF 671*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_448 0x31C0 672*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_449 0x31C1 673*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_450 0x31C2 674*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_451 0x31C3 675*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_452 0x31C4 676*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_453 0x31C5 677*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_454 0x31C6 678*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_455 0x31C7 679*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_456 0x31C8 680*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_457 0x31C9 681*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_458 0x31CA 682*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_459 0x31CB 683*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_460 0x31CC 684*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_461 0x31CD 685*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_462 0x31CE 686*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_463 0x31CF 687*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_464 0x31D0 688*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_465 0x31D1 689*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_466 0x31D2 690*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_467 0x31D3 691*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_468 0x31D4 692*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_469 0x31D5 693*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_470 0x31D6 694*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_471 0x31D7 695*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_472 0x31D8 696*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_473 0x31D9 697*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_474 0x31DA 698*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_475 0x31DB 699*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_476 0x31DC 700*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_477 0x31DD 701*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_478 0x31DE 702*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_479 0x31DF 703*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_480 0x31E0 704*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_481 0x31E1 705*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_482 0x31E2 706*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_483 0x31E3 707*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_484 0x31E4 708*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_485 0x31E5 709*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_486 0x31E6 710*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_487 0x31E7 711*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_488 0x31E8 712*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_489 0x31E9 713*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_490 0x31EA 714*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_491 0x31EB 715*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_492 0x31EC 716*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_493 0x31ED 717*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_494 0x31EE 718*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_495 0x31EF 719*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_496 0x31F0 720*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_497 0x31F1 721*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_498 0x31F2 722*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_499 0x31F3 723*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_500 0x31F4 724*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_501 0x31F5 725*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_502 0x31F6 726*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_503 0x31F7 727*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_504 0x31F8 728*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_505 0x31F9 729*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_506 0x31FA 730*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_507 0x31FB 731*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_508 0x31FC 732*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_509 0x31FD 733*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_510 0x31FE 734*4882a593Smuzhiyun #define WM8996_WRITE_SEQUENCER_511 0x31FF 735*4882a593Smuzhiyun 736*4882a593Smuzhiyun #define WM8996_REGISTER_COUNT 706 737*4882a593Smuzhiyun #define WM8996_MAX_REGISTER 0x31FF 738*4882a593Smuzhiyun 739*4882a593Smuzhiyun /* 740*4882a593Smuzhiyun * Field Definitions. 741*4882a593Smuzhiyun */ 742*4882a593Smuzhiyun 743*4882a593Smuzhiyun /* 744*4882a593Smuzhiyun * R0 (0x00) - Software Reset 745*4882a593Smuzhiyun */ 746*4882a593Smuzhiyun #define WM8996_SW_RESET_MASK 0xFFFF /* SW_RESET - [15:0] */ 747*4882a593Smuzhiyun #define WM8996_SW_RESET_SHIFT 0 /* SW_RESET - [15:0] */ 748*4882a593Smuzhiyun #define WM8996_SW_RESET_WIDTH 16 /* SW_RESET - [15:0] */ 749*4882a593Smuzhiyun 750*4882a593Smuzhiyun /* 751*4882a593Smuzhiyun * R1 (0x01) - Power Management (1) 752*4882a593Smuzhiyun */ 753*4882a593Smuzhiyun #define WM8996_MICB2_ENA 0x0200 /* MICB2_ENA */ 754*4882a593Smuzhiyun #define WM8996_MICB2_ENA_MASK 0x0200 /* MICB2_ENA */ 755*4882a593Smuzhiyun #define WM8996_MICB2_ENA_SHIFT 9 /* MICB2_ENA */ 756*4882a593Smuzhiyun #define WM8996_MICB2_ENA_WIDTH 1 /* MICB2_ENA */ 757*4882a593Smuzhiyun #define WM8996_MICB1_ENA 0x0100 /* MICB1_ENA */ 758*4882a593Smuzhiyun #define WM8996_MICB1_ENA_MASK 0x0100 /* MICB1_ENA */ 759*4882a593Smuzhiyun #define WM8996_MICB1_ENA_SHIFT 8 /* MICB1_ENA */ 760*4882a593Smuzhiyun #define WM8996_MICB1_ENA_WIDTH 1 /* MICB1_ENA */ 761*4882a593Smuzhiyun #define WM8996_HPOUT2L_ENA 0x0080 /* HPOUT2L_ENA */ 762*4882a593Smuzhiyun #define WM8996_HPOUT2L_ENA_MASK 0x0080 /* HPOUT2L_ENA */ 763*4882a593Smuzhiyun #define WM8996_HPOUT2L_ENA_SHIFT 7 /* HPOUT2L_ENA */ 764*4882a593Smuzhiyun #define WM8996_HPOUT2L_ENA_WIDTH 1 /* HPOUT2L_ENA */ 765*4882a593Smuzhiyun #define WM8996_HPOUT2R_ENA 0x0040 /* HPOUT2R_ENA */ 766*4882a593Smuzhiyun #define WM8996_HPOUT2R_ENA_MASK 0x0040 /* HPOUT2R_ENA */ 767*4882a593Smuzhiyun #define WM8996_HPOUT2R_ENA_SHIFT 6 /* HPOUT2R_ENA */ 768*4882a593Smuzhiyun #define WM8996_HPOUT2R_ENA_WIDTH 1 /* HPOUT2R_ENA */ 769*4882a593Smuzhiyun #define WM8996_HPOUT1L_ENA 0x0020 /* HPOUT1L_ENA */ 770*4882a593Smuzhiyun #define WM8996_HPOUT1L_ENA_MASK 0x0020 /* HPOUT1L_ENA */ 771*4882a593Smuzhiyun #define WM8996_HPOUT1L_ENA_SHIFT 5 /* HPOUT1L_ENA */ 772*4882a593Smuzhiyun #define WM8996_HPOUT1L_ENA_WIDTH 1 /* HPOUT1L_ENA */ 773*4882a593Smuzhiyun #define WM8996_HPOUT1R_ENA 0x0010 /* HPOUT1R_ENA */ 774*4882a593Smuzhiyun #define WM8996_HPOUT1R_ENA_MASK 0x0010 /* HPOUT1R_ENA */ 775*4882a593Smuzhiyun #define WM8996_HPOUT1R_ENA_SHIFT 4 /* HPOUT1R_ENA */ 776*4882a593Smuzhiyun #define WM8996_HPOUT1R_ENA_WIDTH 1 /* HPOUT1R_ENA */ 777*4882a593Smuzhiyun #define WM8996_BG_ENA 0x0001 /* BG_ENA */ 778*4882a593Smuzhiyun #define WM8996_BG_ENA_MASK 0x0001 /* BG_ENA */ 779*4882a593Smuzhiyun #define WM8996_BG_ENA_SHIFT 0 /* BG_ENA */ 780*4882a593Smuzhiyun #define WM8996_BG_ENA_WIDTH 1 /* BG_ENA */ 781*4882a593Smuzhiyun 782*4882a593Smuzhiyun /* 783*4882a593Smuzhiyun * R2 (0x02) - Power Management (2) 784*4882a593Smuzhiyun */ 785*4882a593Smuzhiyun #define WM8996_OPCLK_ENA 0x0800 /* OPCLK_ENA */ 786*4882a593Smuzhiyun #define WM8996_OPCLK_ENA_MASK 0x0800 /* OPCLK_ENA */ 787*4882a593Smuzhiyun #define WM8996_OPCLK_ENA_SHIFT 11 /* OPCLK_ENA */ 788*4882a593Smuzhiyun #define WM8996_OPCLK_ENA_WIDTH 1 /* OPCLK_ENA */ 789*4882a593Smuzhiyun #define WM8996_INL_ENA 0x0020 /* INL_ENA */ 790*4882a593Smuzhiyun #define WM8996_INL_ENA_MASK 0x0020 /* INL_ENA */ 791*4882a593Smuzhiyun #define WM8996_INL_ENA_SHIFT 5 /* INL_ENA */ 792*4882a593Smuzhiyun #define WM8996_INL_ENA_WIDTH 1 /* INL_ENA */ 793*4882a593Smuzhiyun #define WM8996_INR_ENA 0x0010 /* INR_ENA */ 794*4882a593Smuzhiyun #define WM8996_INR_ENA_MASK 0x0010 /* INR_ENA */ 795*4882a593Smuzhiyun #define WM8996_INR_ENA_SHIFT 4 /* INR_ENA */ 796*4882a593Smuzhiyun #define WM8996_INR_ENA_WIDTH 1 /* INR_ENA */ 797*4882a593Smuzhiyun #define WM8996_LDO2_ENA 0x0002 /* LDO2_ENA */ 798*4882a593Smuzhiyun #define WM8996_LDO2_ENA_MASK 0x0002 /* LDO2_ENA */ 799*4882a593Smuzhiyun #define WM8996_LDO2_ENA_SHIFT 1 /* LDO2_ENA */ 800*4882a593Smuzhiyun #define WM8996_LDO2_ENA_WIDTH 1 /* LDO2_ENA */ 801*4882a593Smuzhiyun 802*4882a593Smuzhiyun /* 803*4882a593Smuzhiyun * R3 (0x03) - Power Management (3) 804*4882a593Smuzhiyun */ 805*4882a593Smuzhiyun #define WM8996_DSP2RXL_ENA 0x0800 /* DSP2RXL_ENA */ 806*4882a593Smuzhiyun #define WM8996_DSP2RXL_ENA_MASK 0x0800 /* DSP2RXL_ENA */ 807*4882a593Smuzhiyun #define WM8996_DSP2RXL_ENA_SHIFT 11 /* DSP2RXL_ENA */ 808*4882a593Smuzhiyun #define WM8996_DSP2RXL_ENA_WIDTH 1 /* DSP2RXL_ENA */ 809*4882a593Smuzhiyun #define WM8996_DSP2RXR_ENA 0x0400 /* DSP2RXR_ENA */ 810*4882a593Smuzhiyun #define WM8996_DSP2RXR_ENA_MASK 0x0400 /* DSP2RXR_ENA */ 811*4882a593Smuzhiyun #define WM8996_DSP2RXR_ENA_SHIFT 10 /* DSP2RXR_ENA */ 812*4882a593Smuzhiyun #define WM8996_DSP2RXR_ENA_WIDTH 1 /* DSP2RXR_ENA */ 813*4882a593Smuzhiyun #define WM8996_DSP1RXL_ENA 0x0200 /* DSP1RXL_ENA */ 814*4882a593Smuzhiyun #define WM8996_DSP1RXL_ENA_MASK 0x0200 /* DSP1RXL_ENA */ 815*4882a593Smuzhiyun #define WM8996_DSP1RXL_ENA_SHIFT 9 /* DSP1RXL_ENA */ 816*4882a593Smuzhiyun #define WM8996_DSP1RXL_ENA_WIDTH 1 /* DSP1RXL_ENA */ 817*4882a593Smuzhiyun #define WM8996_DSP1RXR_ENA 0x0100 /* DSP1RXR_ENA */ 818*4882a593Smuzhiyun #define WM8996_DSP1RXR_ENA_MASK 0x0100 /* DSP1RXR_ENA */ 819*4882a593Smuzhiyun #define WM8996_DSP1RXR_ENA_SHIFT 8 /* DSP1RXR_ENA */ 820*4882a593Smuzhiyun #define WM8996_DSP1RXR_ENA_WIDTH 1 /* DSP1RXR_ENA */ 821*4882a593Smuzhiyun #define WM8996_DMIC2L_ENA 0x0020 /* DMIC2L_ENA */ 822*4882a593Smuzhiyun #define WM8996_DMIC2L_ENA_MASK 0x0020 /* DMIC2L_ENA */ 823*4882a593Smuzhiyun #define WM8996_DMIC2L_ENA_SHIFT 5 /* DMIC2L_ENA */ 824*4882a593Smuzhiyun #define WM8996_DMIC2L_ENA_WIDTH 1 /* DMIC2L_ENA */ 825*4882a593Smuzhiyun #define WM8996_DMIC2R_ENA 0x0010 /* DMIC2R_ENA */ 826*4882a593Smuzhiyun #define WM8996_DMIC2R_ENA_MASK 0x0010 /* DMIC2R_ENA */ 827*4882a593Smuzhiyun #define WM8996_DMIC2R_ENA_SHIFT 4 /* DMIC2R_ENA */ 828*4882a593Smuzhiyun #define WM8996_DMIC2R_ENA_WIDTH 1 /* DMIC2R_ENA */ 829*4882a593Smuzhiyun #define WM8996_DMIC1L_ENA 0x0008 /* DMIC1L_ENA */ 830*4882a593Smuzhiyun #define WM8996_DMIC1L_ENA_MASK 0x0008 /* DMIC1L_ENA */ 831*4882a593Smuzhiyun #define WM8996_DMIC1L_ENA_SHIFT 3 /* DMIC1L_ENA */ 832*4882a593Smuzhiyun #define WM8996_DMIC1L_ENA_WIDTH 1 /* DMIC1L_ENA */ 833*4882a593Smuzhiyun #define WM8996_DMIC1R_ENA 0x0004 /* DMIC1R_ENA */ 834*4882a593Smuzhiyun #define WM8996_DMIC1R_ENA_MASK 0x0004 /* DMIC1R_ENA */ 835*4882a593Smuzhiyun #define WM8996_DMIC1R_ENA_SHIFT 2 /* DMIC1R_ENA */ 836*4882a593Smuzhiyun #define WM8996_DMIC1R_ENA_WIDTH 1 /* DMIC1R_ENA */ 837*4882a593Smuzhiyun #define WM8996_ADCL_ENA 0x0002 /* ADCL_ENA */ 838*4882a593Smuzhiyun #define WM8996_ADCL_ENA_MASK 0x0002 /* ADCL_ENA */ 839*4882a593Smuzhiyun #define WM8996_ADCL_ENA_SHIFT 1 /* ADCL_ENA */ 840*4882a593Smuzhiyun #define WM8996_ADCL_ENA_WIDTH 1 /* ADCL_ENA */ 841*4882a593Smuzhiyun #define WM8996_ADCR_ENA 0x0001 /* ADCR_ENA */ 842*4882a593Smuzhiyun #define WM8996_ADCR_ENA_MASK 0x0001 /* ADCR_ENA */ 843*4882a593Smuzhiyun #define WM8996_ADCR_ENA_SHIFT 0 /* ADCR_ENA */ 844*4882a593Smuzhiyun #define WM8996_ADCR_ENA_WIDTH 1 /* ADCR_ENA */ 845*4882a593Smuzhiyun 846*4882a593Smuzhiyun /* 847*4882a593Smuzhiyun * R4 (0x04) - Power Management (4) 848*4882a593Smuzhiyun */ 849*4882a593Smuzhiyun #define WM8996_AIF2RX_CHAN1_ENA 0x0200 /* AIF2RX_CHAN1_ENA */ 850*4882a593Smuzhiyun #define WM8996_AIF2RX_CHAN1_ENA_MASK 0x0200 /* AIF2RX_CHAN1_ENA */ 851*4882a593Smuzhiyun #define WM8996_AIF2RX_CHAN1_ENA_SHIFT 9 /* AIF2RX_CHAN1_ENA */ 852*4882a593Smuzhiyun #define WM8996_AIF2RX_CHAN1_ENA_WIDTH 1 /* AIF2RX_CHAN1_ENA */ 853*4882a593Smuzhiyun #define WM8996_AIF2RX_CHAN0_ENA 0x0100 /* AIF2RX_CHAN0_ENA */ 854*4882a593Smuzhiyun #define WM8996_AIF2RX_CHAN0_ENA_MASK 0x0100 /* AIF2RX_CHAN0_ENA */ 855*4882a593Smuzhiyun #define WM8996_AIF2RX_CHAN0_ENA_SHIFT 8 /* AIF2RX_CHAN0_ENA */ 856*4882a593Smuzhiyun #define WM8996_AIF2RX_CHAN0_ENA_WIDTH 1 /* AIF2RX_CHAN0_ENA */ 857*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN5_ENA 0x0020 /* AIF1RX_CHAN5_ENA */ 858*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN5_ENA_MASK 0x0020 /* AIF1RX_CHAN5_ENA */ 859*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN5_ENA_SHIFT 5 /* AIF1RX_CHAN5_ENA */ 860*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN5_ENA_WIDTH 1 /* AIF1RX_CHAN5_ENA */ 861*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN4_ENA 0x0010 /* AIF1RX_CHAN4_ENA */ 862*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN4_ENA_MASK 0x0010 /* AIF1RX_CHAN4_ENA */ 863*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN4_ENA_SHIFT 4 /* AIF1RX_CHAN4_ENA */ 864*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN4_ENA_WIDTH 1 /* AIF1RX_CHAN4_ENA */ 865*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN3_ENA 0x0008 /* AIF1RX_CHAN3_ENA */ 866*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN3_ENA_MASK 0x0008 /* AIF1RX_CHAN3_ENA */ 867*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN3_ENA_SHIFT 3 /* AIF1RX_CHAN3_ENA */ 868*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN3_ENA_WIDTH 1 /* AIF1RX_CHAN3_ENA */ 869*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN2_ENA 0x0004 /* AIF1RX_CHAN2_ENA */ 870*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN2_ENA_MASK 0x0004 /* AIF1RX_CHAN2_ENA */ 871*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN2_ENA_SHIFT 2 /* AIF1RX_CHAN2_ENA */ 872*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN2_ENA_WIDTH 1 /* AIF1RX_CHAN2_ENA */ 873*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN1_ENA 0x0002 /* AIF1RX_CHAN1_ENA */ 874*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN1_ENA_MASK 0x0002 /* AIF1RX_CHAN1_ENA */ 875*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN1_ENA_SHIFT 1 /* AIF1RX_CHAN1_ENA */ 876*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN1_ENA_WIDTH 1 /* AIF1RX_CHAN1_ENA */ 877*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN0_ENA 0x0001 /* AIF1RX_CHAN0_ENA */ 878*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN0_ENA_MASK 0x0001 /* AIF1RX_CHAN0_ENA */ 879*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN0_ENA_SHIFT 0 /* AIF1RX_CHAN0_ENA */ 880*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN0_ENA_WIDTH 1 /* AIF1RX_CHAN0_ENA */ 881*4882a593Smuzhiyun 882*4882a593Smuzhiyun /* 883*4882a593Smuzhiyun * R5 (0x05) - Power Management (5) 884*4882a593Smuzhiyun */ 885*4882a593Smuzhiyun #define WM8996_DSP2TXL_ENA 0x0800 /* DSP2TXL_ENA */ 886*4882a593Smuzhiyun #define WM8996_DSP2TXL_ENA_MASK 0x0800 /* DSP2TXL_ENA */ 887*4882a593Smuzhiyun #define WM8996_DSP2TXL_ENA_SHIFT 11 /* DSP2TXL_ENA */ 888*4882a593Smuzhiyun #define WM8996_DSP2TXL_ENA_WIDTH 1 /* DSP2TXL_ENA */ 889*4882a593Smuzhiyun #define WM8996_DSP2TXR_ENA 0x0400 /* DSP2TXR_ENA */ 890*4882a593Smuzhiyun #define WM8996_DSP2TXR_ENA_MASK 0x0400 /* DSP2TXR_ENA */ 891*4882a593Smuzhiyun #define WM8996_DSP2TXR_ENA_SHIFT 10 /* DSP2TXR_ENA */ 892*4882a593Smuzhiyun #define WM8996_DSP2TXR_ENA_WIDTH 1 /* DSP2TXR_ENA */ 893*4882a593Smuzhiyun #define WM8996_DSP1TXL_ENA 0x0200 /* DSP1TXL_ENA */ 894*4882a593Smuzhiyun #define WM8996_DSP1TXL_ENA_MASK 0x0200 /* DSP1TXL_ENA */ 895*4882a593Smuzhiyun #define WM8996_DSP1TXL_ENA_SHIFT 9 /* DSP1TXL_ENA */ 896*4882a593Smuzhiyun #define WM8996_DSP1TXL_ENA_WIDTH 1 /* DSP1TXL_ENA */ 897*4882a593Smuzhiyun #define WM8996_DSP1TXR_ENA 0x0100 /* DSP1TXR_ENA */ 898*4882a593Smuzhiyun #define WM8996_DSP1TXR_ENA_MASK 0x0100 /* DSP1TXR_ENA */ 899*4882a593Smuzhiyun #define WM8996_DSP1TXR_ENA_SHIFT 8 /* DSP1TXR_ENA */ 900*4882a593Smuzhiyun #define WM8996_DSP1TXR_ENA_WIDTH 1 /* DSP1TXR_ENA */ 901*4882a593Smuzhiyun #define WM8996_DAC2L_ENA 0x0008 /* DAC2L_ENA */ 902*4882a593Smuzhiyun #define WM8996_DAC2L_ENA_MASK 0x0008 /* DAC2L_ENA */ 903*4882a593Smuzhiyun #define WM8996_DAC2L_ENA_SHIFT 3 /* DAC2L_ENA */ 904*4882a593Smuzhiyun #define WM8996_DAC2L_ENA_WIDTH 1 /* DAC2L_ENA */ 905*4882a593Smuzhiyun #define WM8996_DAC2R_ENA 0x0004 /* DAC2R_ENA */ 906*4882a593Smuzhiyun #define WM8996_DAC2R_ENA_MASK 0x0004 /* DAC2R_ENA */ 907*4882a593Smuzhiyun #define WM8996_DAC2R_ENA_SHIFT 2 /* DAC2R_ENA */ 908*4882a593Smuzhiyun #define WM8996_DAC2R_ENA_WIDTH 1 /* DAC2R_ENA */ 909*4882a593Smuzhiyun #define WM8996_DAC1L_ENA 0x0002 /* DAC1L_ENA */ 910*4882a593Smuzhiyun #define WM8996_DAC1L_ENA_MASK 0x0002 /* DAC1L_ENA */ 911*4882a593Smuzhiyun #define WM8996_DAC1L_ENA_SHIFT 1 /* DAC1L_ENA */ 912*4882a593Smuzhiyun #define WM8996_DAC1L_ENA_WIDTH 1 /* DAC1L_ENA */ 913*4882a593Smuzhiyun #define WM8996_DAC1R_ENA 0x0001 /* DAC1R_ENA */ 914*4882a593Smuzhiyun #define WM8996_DAC1R_ENA_MASK 0x0001 /* DAC1R_ENA */ 915*4882a593Smuzhiyun #define WM8996_DAC1R_ENA_SHIFT 0 /* DAC1R_ENA */ 916*4882a593Smuzhiyun #define WM8996_DAC1R_ENA_WIDTH 1 /* DAC1R_ENA */ 917*4882a593Smuzhiyun 918*4882a593Smuzhiyun /* 919*4882a593Smuzhiyun * R6 (0x06) - Power Management (6) 920*4882a593Smuzhiyun */ 921*4882a593Smuzhiyun #define WM8996_AIF2TX_CHAN1_ENA 0x0200 /* AIF2TX_CHAN1_ENA */ 922*4882a593Smuzhiyun #define WM8996_AIF2TX_CHAN1_ENA_MASK 0x0200 /* AIF2TX_CHAN1_ENA */ 923*4882a593Smuzhiyun #define WM8996_AIF2TX_CHAN1_ENA_SHIFT 9 /* AIF2TX_CHAN1_ENA */ 924*4882a593Smuzhiyun #define WM8996_AIF2TX_CHAN1_ENA_WIDTH 1 /* AIF2TX_CHAN1_ENA */ 925*4882a593Smuzhiyun #define WM8996_AIF2TX_CHAN0_ENA 0x0100 /* AIF2TX_CHAN0_ENA */ 926*4882a593Smuzhiyun #define WM8996_AIF2TX_CHAN0_ENA_MASK 0x0100 /* AIF2TX_CHAN0_ENA */ 927*4882a593Smuzhiyun #define WM8996_AIF2TX_CHAN0_ENA_SHIFT 8 /* AIF2TX_CHAN0_ENA */ 928*4882a593Smuzhiyun #define WM8996_AIF2TX_CHAN0_ENA_WIDTH 1 /* AIF2TX_CHAN0_ENA */ 929*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN5_ENA 0x0020 /* AIF1TX_CHAN5_ENA */ 930*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN5_ENA_MASK 0x0020 /* AIF1TX_CHAN5_ENA */ 931*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN5_ENA_SHIFT 5 /* AIF1TX_CHAN5_ENA */ 932*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN5_ENA_WIDTH 1 /* AIF1TX_CHAN5_ENA */ 933*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN4_ENA 0x0010 /* AIF1TX_CHAN4_ENA */ 934*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN4_ENA_MASK 0x0010 /* AIF1TX_CHAN4_ENA */ 935*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN4_ENA_SHIFT 4 /* AIF1TX_CHAN4_ENA */ 936*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN4_ENA_WIDTH 1 /* AIF1TX_CHAN4_ENA */ 937*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN3_ENA 0x0008 /* AIF1TX_CHAN3_ENA */ 938*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN3_ENA_MASK 0x0008 /* AIF1TX_CHAN3_ENA */ 939*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN3_ENA_SHIFT 3 /* AIF1TX_CHAN3_ENA */ 940*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN3_ENA_WIDTH 1 /* AIF1TX_CHAN3_ENA */ 941*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN2_ENA 0x0004 /* AIF1TX_CHAN2_ENA */ 942*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN2_ENA_MASK 0x0004 /* AIF1TX_CHAN2_ENA */ 943*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN2_ENA_SHIFT 2 /* AIF1TX_CHAN2_ENA */ 944*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN2_ENA_WIDTH 1 /* AIF1TX_CHAN2_ENA */ 945*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN1_ENA 0x0002 /* AIF1TX_CHAN1_ENA */ 946*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN1_ENA_MASK 0x0002 /* AIF1TX_CHAN1_ENA */ 947*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN1_ENA_SHIFT 1 /* AIF1TX_CHAN1_ENA */ 948*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN1_ENA_WIDTH 1 /* AIF1TX_CHAN1_ENA */ 949*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN0_ENA 0x0001 /* AIF1TX_CHAN0_ENA */ 950*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN0_ENA_MASK 0x0001 /* AIF1TX_CHAN0_ENA */ 951*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN0_ENA_SHIFT 0 /* AIF1TX_CHAN0_ENA */ 952*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN0_ENA_WIDTH 1 /* AIF1TX_CHAN0_ENA */ 953*4882a593Smuzhiyun 954*4882a593Smuzhiyun /* 955*4882a593Smuzhiyun * R7 (0x07) - Power Management (7) 956*4882a593Smuzhiyun */ 957*4882a593Smuzhiyun #define WM8996_DMIC2_FN 0x0200 /* DMIC2_FN */ 958*4882a593Smuzhiyun #define WM8996_DMIC2_FN_MASK 0x0200 /* DMIC2_FN */ 959*4882a593Smuzhiyun #define WM8996_DMIC2_FN_SHIFT 9 /* DMIC2_FN */ 960*4882a593Smuzhiyun #define WM8996_DMIC2_FN_WIDTH 1 /* DMIC2_FN */ 961*4882a593Smuzhiyun #define WM8996_DMIC1_FN 0x0100 /* DMIC1_FN */ 962*4882a593Smuzhiyun #define WM8996_DMIC1_FN_MASK 0x0100 /* DMIC1_FN */ 963*4882a593Smuzhiyun #define WM8996_DMIC1_FN_SHIFT 8 /* DMIC1_FN */ 964*4882a593Smuzhiyun #define WM8996_DMIC1_FN_WIDTH 1 /* DMIC1_FN */ 965*4882a593Smuzhiyun #define WM8996_ADC_DMIC_DSP2R_ENA 0x0080 /* ADC_DMIC_DSP2R_ENA */ 966*4882a593Smuzhiyun #define WM8996_ADC_DMIC_DSP2R_ENA_MASK 0x0080 /* ADC_DMIC_DSP2R_ENA */ 967*4882a593Smuzhiyun #define WM8996_ADC_DMIC_DSP2R_ENA_SHIFT 7 /* ADC_DMIC_DSP2R_ENA */ 968*4882a593Smuzhiyun #define WM8996_ADC_DMIC_DSP2R_ENA_WIDTH 1 /* ADC_DMIC_DSP2R_ENA */ 969*4882a593Smuzhiyun #define WM8996_ADC_DMIC_DSP2L_ENA 0x0040 /* ADC_DMIC_DSP2L_ENA */ 970*4882a593Smuzhiyun #define WM8996_ADC_DMIC_DSP2L_ENA_MASK 0x0040 /* ADC_DMIC_DSP2L_ENA */ 971*4882a593Smuzhiyun #define WM8996_ADC_DMIC_DSP2L_ENA_SHIFT 6 /* ADC_DMIC_DSP2L_ENA */ 972*4882a593Smuzhiyun #define WM8996_ADC_DMIC_DSP2L_ENA_WIDTH 1 /* ADC_DMIC_DSP2L_ENA */ 973*4882a593Smuzhiyun #define WM8996_ADC_DMIC_SRC2_MASK 0x0030 /* ADC_DMIC_SRC2 - [5:4] */ 974*4882a593Smuzhiyun #define WM8996_ADC_DMIC_SRC2_SHIFT 4 /* ADC_DMIC_SRC2 - [5:4] */ 975*4882a593Smuzhiyun #define WM8996_ADC_DMIC_SRC2_WIDTH 2 /* ADC_DMIC_SRC2 - [5:4] */ 976*4882a593Smuzhiyun #define WM8996_ADC_DMIC_DSP1R_ENA 0x0008 /* ADC_DMIC_DSP1R_ENA */ 977*4882a593Smuzhiyun #define WM8996_ADC_DMIC_DSP1R_ENA_MASK 0x0008 /* ADC_DMIC_DSP1R_ENA */ 978*4882a593Smuzhiyun #define WM8996_ADC_DMIC_DSP1R_ENA_SHIFT 3 /* ADC_DMIC_DSP1R_ENA */ 979*4882a593Smuzhiyun #define WM8996_ADC_DMIC_DSP1R_ENA_WIDTH 1 /* ADC_DMIC_DSP1R_ENA */ 980*4882a593Smuzhiyun #define WM8996_ADC_DMIC_DSP1L_ENA 0x0004 /* ADC_DMIC_DSP1L_ENA */ 981*4882a593Smuzhiyun #define WM8996_ADC_DMIC_DSP1L_ENA_MASK 0x0004 /* ADC_DMIC_DSP1L_ENA */ 982*4882a593Smuzhiyun #define WM8996_ADC_DMIC_DSP1L_ENA_SHIFT 2 /* ADC_DMIC_DSP1L_ENA */ 983*4882a593Smuzhiyun #define WM8996_ADC_DMIC_DSP1L_ENA_WIDTH 1 /* ADC_DMIC_DSP1L_ENA */ 984*4882a593Smuzhiyun #define WM8996_ADC_DMIC_SRC1_MASK 0x0003 /* ADC_DMIC_SRC1 - [1:0] */ 985*4882a593Smuzhiyun #define WM8996_ADC_DMIC_SRC1_SHIFT 0 /* ADC_DMIC_SRC1 - [1:0] */ 986*4882a593Smuzhiyun #define WM8996_ADC_DMIC_SRC1_WIDTH 2 /* ADC_DMIC_SRC1 - [1:0] */ 987*4882a593Smuzhiyun 988*4882a593Smuzhiyun /* 989*4882a593Smuzhiyun * R8 (0x08) - Power Management (8) 990*4882a593Smuzhiyun */ 991*4882a593Smuzhiyun #define WM8996_AIF2TX_SRC_MASK 0x00C0 /* AIF2TX_SRC - [7:6] */ 992*4882a593Smuzhiyun #define WM8996_AIF2TX_SRC_SHIFT 6 /* AIF2TX_SRC - [7:6] */ 993*4882a593Smuzhiyun #define WM8996_AIF2TX_SRC_WIDTH 2 /* AIF2TX_SRC - [7:6] */ 994*4882a593Smuzhiyun #define WM8996_DSP2RX_SRC 0x0010 /* DSP2RX_SRC */ 995*4882a593Smuzhiyun #define WM8996_DSP2RX_SRC_MASK 0x0010 /* DSP2RX_SRC */ 996*4882a593Smuzhiyun #define WM8996_DSP2RX_SRC_SHIFT 4 /* DSP2RX_SRC */ 997*4882a593Smuzhiyun #define WM8996_DSP2RX_SRC_WIDTH 1 /* DSP2RX_SRC */ 998*4882a593Smuzhiyun #define WM8996_DSP1RX_SRC 0x0001 /* DSP1RX_SRC */ 999*4882a593Smuzhiyun #define WM8996_DSP1RX_SRC_MASK 0x0001 /* DSP1RX_SRC */ 1000*4882a593Smuzhiyun #define WM8996_DSP1RX_SRC_SHIFT 0 /* DSP1RX_SRC */ 1001*4882a593Smuzhiyun #define WM8996_DSP1RX_SRC_WIDTH 1 /* DSP1RX_SRC */ 1002*4882a593Smuzhiyun 1003*4882a593Smuzhiyun /* 1004*4882a593Smuzhiyun * R16 (0x10) - Left Line Input Volume 1005*4882a593Smuzhiyun */ 1006*4882a593Smuzhiyun #define WM8996_IN1_VU 0x0080 /* IN1_VU */ 1007*4882a593Smuzhiyun #define WM8996_IN1_VU_MASK 0x0080 /* IN1_VU */ 1008*4882a593Smuzhiyun #define WM8996_IN1_VU_SHIFT 7 /* IN1_VU */ 1009*4882a593Smuzhiyun #define WM8996_IN1_VU_WIDTH 1 /* IN1_VU */ 1010*4882a593Smuzhiyun #define WM8996_IN1L_ZC 0x0020 /* IN1L_ZC */ 1011*4882a593Smuzhiyun #define WM8996_IN1L_ZC_MASK 0x0020 /* IN1L_ZC */ 1012*4882a593Smuzhiyun #define WM8996_IN1L_ZC_SHIFT 5 /* IN1L_ZC */ 1013*4882a593Smuzhiyun #define WM8996_IN1L_ZC_WIDTH 1 /* IN1L_ZC */ 1014*4882a593Smuzhiyun #define WM8996_IN1L_VOL_MASK 0x001F /* IN1L_VOL - [4:0] */ 1015*4882a593Smuzhiyun #define WM8996_IN1L_VOL_SHIFT 0 /* IN1L_VOL - [4:0] */ 1016*4882a593Smuzhiyun #define WM8996_IN1L_VOL_WIDTH 5 /* IN1L_VOL - [4:0] */ 1017*4882a593Smuzhiyun 1018*4882a593Smuzhiyun /* 1019*4882a593Smuzhiyun * R17 (0x11) - Right Line Input Volume 1020*4882a593Smuzhiyun */ 1021*4882a593Smuzhiyun #define WM8996_IN1_VU 0x0080 /* IN1_VU */ 1022*4882a593Smuzhiyun #define WM8996_IN1_VU_MASK 0x0080 /* IN1_VU */ 1023*4882a593Smuzhiyun #define WM8996_IN1_VU_SHIFT 7 /* IN1_VU */ 1024*4882a593Smuzhiyun #define WM8996_IN1_VU_WIDTH 1 /* IN1_VU */ 1025*4882a593Smuzhiyun #define WM8996_IN1R_ZC 0x0020 /* IN1R_ZC */ 1026*4882a593Smuzhiyun #define WM8996_IN1R_ZC_MASK 0x0020 /* IN1R_ZC */ 1027*4882a593Smuzhiyun #define WM8996_IN1R_ZC_SHIFT 5 /* IN1R_ZC */ 1028*4882a593Smuzhiyun #define WM8996_IN1R_ZC_WIDTH 1 /* IN1R_ZC */ 1029*4882a593Smuzhiyun #define WM8996_IN1R_VOL_MASK 0x001F /* IN1R_VOL - [4:0] */ 1030*4882a593Smuzhiyun #define WM8996_IN1R_VOL_SHIFT 0 /* IN1R_VOL - [4:0] */ 1031*4882a593Smuzhiyun #define WM8996_IN1R_VOL_WIDTH 5 /* IN1R_VOL - [4:0] */ 1032*4882a593Smuzhiyun 1033*4882a593Smuzhiyun /* 1034*4882a593Smuzhiyun * R18 (0x12) - Line Input Control 1035*4882a593Smuzhiyun */ 1036*4882a593Smuzhiyun #define WM8996_INL_MODE_MASK 0x000C /* INL_MODE - [3:2] */ 1037*4882a593Smuzhiyun #define WM8996_INL_MODE_SHIFT 2 /* INL_MODE - [3:2] */ 1038*4882a593Smuzhiyun #define WM8996_INL_MODE_WIDTH 2 /* INL_MODE - [3:2] */ 1039*4882a593Smuzhiyun #define WM8996_INR_MODE_MASK 0x0003 /* INR_MODE - [1:0] */ 1040*4882a593Smuzhiyun #define WM8996_INR_MODE_SHIFT 0 /* INR_MODE - [1:0] */ 1041*4882a593Smuzhiyun #define WM8996_INR_MODE_WIDTH 2 /* INR_MODE - [1:0] */ 1042*4882a593Smuzhiyun 1043*4882a593Smuzhiyun /* 1044*4882a593Smuzhiyun * R21 (0x15) - DAC1 HPOUT1 Volume 1045*4882a593Smuzhiyun */ 1046*4882a593Smuzhiyun #define WM8996_DAC1R_HPOUT1R_VOL_MASK 0x00F0 /* DAC1R_HPOUT1R_VOL - [7:4] */ 1047*4882a593Smuzhiyun #define WM8996_DAC1R_HPOUT1R_VOL_SHIFT 4 /* DAC1R_HPOUT1R_VOL - [7:4] */ 1048*4882a593Smuzhiyun #define WM8996_DAC1R_HPOUT1R_VOL_WIDTH 4 /* DAC1R_HPOUT1R_VOL - [7:4] */ 1049*4882a593Smuzhiyun #define WM8996_DAC1L_HPOUT1L_VOL_MASK 0x000F /* DAC1L_HPOUT1L_VOL - [3:0] */ 1050*4882a593Smuzhiyun #define WM8996_DAC1L_HPOUT1L_VOL_SHIFT 0 /* DAC1L_HPOUT1L_VOL - [3:0] */ 1051*4882a593Smuzhiyun #define WM8996_DAC1L_HPOUT1L_VOL_WIDTH 4 /* DAC1L_HPOUT1L_VOL - [3:0] */ 1052*4882a593Smuzhiyun 1053*4882a593Smuzhiyun /* 1054*4882a593Smuzhiyun * R22 (0x16) - DAC2 HPOUT2 Volume 1055*4882a593Smuzhiyun */ 1056*4882a593Smuzhiyun #define WM8996_DAC2R_HPOUT2R_VOL_MASK 0x00F0 /* DAC2R_HPOUT2R_VOL - [7:4] */ 1057*4882a593Smuzhiyun #define WM8996_DAC2R_HPOUT2R_VOL_SHIFT 4 /* DAC2R_HPOUT2R_VOL - [7:4] */ 1058*4882a593Smuzhiyun #define WM8996_DAC2R_HPOUT2R_VOL_WIDTH 4 /* DAC2R_HPOUT2R_VOL - [7:4] */ 1059*4882a593Smuzhiyun #define WM8996_DAC2L_HPOUT2L_VOL_MASK 0x000F /* DAC2L_HPOUT2L_VOL - [3:0] */ 1060*4882a593Smuzhiyun #define WM8996_DAC2L_HPOUT2L_VOL_SHIFT 0 /* DAC2L_HPOUT2L_VOL - [3:0] */ 1061*4882a593Smuzhiyun #define WM8996_DAC2L_HPOUT2L_VOL_WIDTH 4 /* DAC2L_HPOUT2L_VOL - [3:0] */ 1062*4882a593Smuzhiyun 1063*4882a593Smuzhiyun /* 1064*4882a593Smuzhiyun * R24 (0x18) - DAC1 Left Volume 1065*4882a593Smuzhiyun */ 1066*4882a593Smuzhiyun #define WM8996_DAC1L_MUTE 0x0200 /* DAC1L_MUTE */ 1067*4882a593Smuzhiyun #define WM8996_DAC1L_MUTE_MASK 0x0200 /* DAC1L_MUTE */ 1068*4882a593Smuzhiyun #define WM8996_DAC1L_MUTE_SHIFT 9 /* DAC1L_MUTE */ 1069*4882a593Smuzhiyun #define WM8996_DAC1L_MUTE_WIDTH 1 /* DAC1L_MUTE */ 1070*4882a593Smuzhiyun #define WM8996_DAC1_VU 0x0100 /* DAC1_VU */ 1071*4882a593Smuzhiyun #define WM8996_DAC1_VU_MASK 0x0100 /* DAC1_VU */ 1072*4882a593Smuzhiyun #define WM8996_DAC1_VU_SHIFT 8 /* DAC1_VU */ 1073*4882a593Smuzhiyun #define WM8996_DAC1_VU_WIDTH 1 /* DAC1_VU */ 1074*4882a593Smuzhiyun #define WM8996_DAC1L_VOL_MASK 0x00FF /* DAC1L_VOL - [7:0] */ 1075*4882a593Smuzhiyun #define WM8996_DAC1L_VOL_SHIFT 0 /* DAC1L_VOL - [7:0] */ 1076*4882a593Smuzhiyun #define WM8996_DAC1L_VOL_WIDTH 8 /* DAC1L_VOL - [7:0] */ 1077*4882a593Smuzhiyun 1078*4882a593Smuzhiyun /* 1079*4882a593Smuzhiyun * R25 (0x19) - DAC1 Right Volume 1080*4882a593Smuzhiyun */ 1081*4882a593Smuzhiyun #define WM8996_DAC1R_MUTE 0x0200 /* DAC1R_MUTE */ 1082*4882a593Smuzhiyun #define WM8996_DAC1R_MUTE_MASK 0x0200 /* DAC1R_MUTE */ 1083*4882a593Smuzhiyun #define WM8996_DAC1R_MUTE_SHIFT 9 /* DAC1R_MUTE */ 1084*4882a593Smuzhiyun #define WM8996_DAC1R_MUTE_WIDTH 1 /* DAC1R_MUTE */ 1085*4882a593Smuzhiyun #define WM8996_DAC1_VU 0x0100 /* DAC1_VU */ 1086*4882a593Smuzhiyun #define WM8996_DAC1_VU_MASK 0x0100 /* DAC1_VU */ 1087*4882a593Smuzhiyun #define WM8996_DAC1_VU_SHIFT 8 /* DAC1_VU */ 1088*4882a593Smuzhiyun #define WM8996_DAC1_VU_WIDTH 1 /* DAC1_VU */ 1089*4882a593Smuzhiyun #define WM8996_DAC1R_VOL_MASK 0x00FF /* DAC1R_VOL - [7:0] */ 1090*4882a593Smuzhiyun #define WM8996_DAC1R_VOL_SHIFT 0 /* DAC1R_VOL - [7:0] */ 1091*4882a593Smuzhiyun #define WM8996_DAC1R_VOL_WIDTH 8 /* DAC1R_VOL - [7:0] */ 1092*4882a593Smuzhiyun 1093*4882a593Smuzhiyun /* 1094*4882a593Smuzhiyun * R26 (0x1A) - DAC2 Left Volume 1095*4882a593Smuzhiyun */ 1096*4882a593Smuzhiyun #define WM8996_DAC2L_MUTE 0x0200 /* DAC2L_MUTE */ 1097*4882a593Smuzhiyun #define WM8996_DAC2L_MUTE_MASK 0x0200 /* DAC2L_MUTE */ 1098*4882a593Smuzhiyun #define WM8996_DAC2L_MUTE_SHIFT 9 /* DAC2L_MUTE */ 1099*4882a593Smuzhiyun #define WM8996_DAC2L_MUTE_WIDTH 1 /* DAC2L_MUTE */ 1100*4882a593Smuzhiyun #define WM8996_DAC2_VU 0x0100 /* DAC2_VU */ 1101*4882a593Smuzhiyun #define WM8996_DAC2_VU_MASK 0x0100 /* DAC2_VU */ 1102*4882a593Smuzhiyun #define WM8996_DAC2_VU_SHIFT 8 /* DAC2_VU */ 1103*4882a593Smuzhiyun #define WM8996_DAC2_VU_WIDTH 1 /* DAC2_VU */ 1104*4882a593Smuzhiyun #define WM8996_DAC2L_VOL_MASK 0x00FF /* DAC2L_VOL - [7:0] */ 1105*4882a593Smuzhiyun #define WM8996_DAC2L_VOL_SHIFT 0 /* DAC2L_VOL - [7:0] */ 1106*4882a593Smuzhiyun #define WM8996_DAC2L_VOL_WIDTH 8 /* DAC2L_VOL - [7:0] */ 1107*4882a593Smuzhiyun 1108*4882a593Smuzhiyun /* 1109*4882a593Smuzhiyun * R27 (0x1B) - DAC2 Right Volume 1110*4882a593Smuzhiyun */ 1111*4882a593Smuzhiyun #define WM8996_DAC2R_MUTE 0x0200 /* DAC2R_MUTE */ 1112*4882a593Smuzhiyun #define WM8996_DAC2R_MUTE_MASK 0x0200 /* DAC2R_MUTE */ 1113*4882a593Smuzhiyun #define WM8996_DAC2R_MUTE_SHIFT 9 /* DAC2R_MUTE */ 1114*4882a593Smuzhiyun #define WM8996_DAC2R_MUTE_WIDTH 1 /* DAC2R_MUTE */ 1115*4882a593Smuzhiyun #define WM8996_DAC2_VU 0x0100 /* DAC2_VU */ 1116*4882a593Smuzhiyun #define WM8996_DAC2_VU_MASK 0x0100 /* DAC2_VU */ 1117*4882a593Smuzhiyun #define WM8996_DAC2_VU_SHIFT 8 /* DAC2_VU */ 1118*4882a593Smuzhiyun #define WM8996_DAC2_VU_WIDTH 1 /* DAC2_VU */ 1119*4882a593Smuzhiyun #define WM8996_DAC2R_VOL_MASK 0x00FF /* DAC2R_VOL - [7:0] */ 1120*4882a593Smuzhiyun #define WM8996_DAC2R_VOL_SHIFT 0 /* DAC2R_VOL - [7:0] */ 1121*4882a593Smuzhiyun #define WM8996_DAC2R_VOL_WIDTH 8 /* DAC2R_VOL - [7:0] */ 1122*4882a593Smuzhiyun 1123*4882a593Smuzhiyun /* 1124*4882a593Smuzhiyun * R28 (0x1C) - Output1 Left Volume 1125*4882a593Smuzhiyun */ 1126*4882a593Smuzhiyun #define WM8996_DAC1_VU 0x0100 /* DAC1_VU */ 1127*4882a593Smuzhiyun #define WM8996_DAC1_VU_MASK 0x0100 /* DAC1_VU */ 1128*4882a593Smuzhiyun #define WM8996_DAC1_VU_SHIFT 8 /* DAC1_VU */ 1129*4882a593Smuzhiyun #define WM8996_DAC1_VU_WIDTH 1 /* DAC1_VU */ 1130*4882a593Smuzhiyun #define WM8996_HPOUT1L_ZC 0x0080 /* HPOUT1L_ZC */ 1131*4882a593Smuzhiyun #define WM8996_HPOUT1L_ZC_MASK 0x0080 /* HPOUT1L_ZC */ 1132*4882a593Smuzhiyun #define WM8996_HPOUT1L_ZC_SHIFT 7 /* HPOUT1L_ZC */ 1133*4882a593Smuzhiyun #define WM8996_HPOUT1L_ZC_WIDTH 1 /* HPOUT1L_ZC */ 1134*4882a593Smuzhiyun #define WM8996_HPOUT1L_VOL_MASK 0x000F /* HPOUT1L_VOL - [3:0] */ 1135*4882a593Smuzhiyun #define WM8996_HPOUT1L_VOL_SHIFT 0 /* HPOUT1L_VOL - [3:0] */ 1136*4882a593Smuzhiyun #define WM8996_HPOUT1L_VOL_WIDTH 4 /* HPOUT1L_VOL - [3:0] */ 1137*4882a593Smuzhiyun 1138*4882a593Smuzhiyun /* 1139*4882a593Smuzhiyun * R29 (0x1D) - Output1 Right Volume 1140*4882a593Smuzhiyun */ 1141*4882a593Smuzhiyun #define WM8996_DAC1_VU 0x0100 /* DAC1_VU */ 1142*4882a593Smuzhiyun #define WM8996_DAC1_VU_MASK 0x0100 /* DAC1_VU */ 1143*4882a593Smuzhiyun #define WM8996_DAC1_VU_SHIFT 8 /* DAC1_VU */ 1144*4882a593Smuzhiyun #define WM8996_DAC1_VU_WIDTH 1 /* DAC1_VU */ 1145*4882a593Smuzhiyun #define WM8996_HPOUT1R_ZC 0x0080 /* HPOUT1R_ZC */ 1146*4882a593Smuzhiyun #define WM8996_HPOUT1R_ZC_MASK 0x0080 /* HPOUT1R_ZC */ 1147*4882a593Smuzhiyun #define WM8996_HPOUT1R_ZC_SHIFT 7 /* HPOUT1R_ZC */ 1148*4882a593Smuzhiyun #define WM8996_HPOUT1R_ZC_WIDTH 1 /* HPOUT1R_ZC */ 1149*4882a593Smuzhiyun #define WM8996_HPOUT1R_VOL_MASK 0x000F /* HPOUT1R_VOL - [3:0] */ 1150*4882a593Smuzhiyun #define WM8996_HPOUT1R_VOL_SHIFT 0 /* HPOUT1R_VOL - [3:0] */ 1151*4882a593Smuzhiyun #define WM8996_HPOUT1R_VOL_WIDTH 4 /* HPOUT1R_VOL - [3:0] */ 1152*4882a593Smuzhiyun 1153*4882a593Smuzhiyun /* 1154*4882a593Smuzhiyun * R30 (0x1E) - Output2 Left Volume 1155*4882a593Smuzhiyun */ 1156*4882a593Smuzhiyun #define WM8996_DAC2_VU 0x0100 /* DAC2_VU */ 1157*4882a593Smuzhiyun #define WM8996_DAC2_VU_MASK 0x0100 /* DAC2_VU */ 1158*4882a593Smuzhiyun #define WM8996_DAC2_VU_SHIFT 8 /* DAC2_VU */ 1159*4882a593Smuzhiyun #define WM8996_DAC2_VU_WIDTH 1 /* DAC2_VU */ 1160*4882a593Smuzhiyun #define WM8996_HPOUT2L_ZC 0x0080 /* HPOUT2L_ZC */ 1161*4882a593Smuzhiyun #define WM8996_HPOUT2L_ZC_MASK 0x0080 /* HPOUT2L_ZC */ 1162*4882a593Smuzhiyun #define WM8996_HPOUT2L_ZC_SHIFT 7 /* HPOUT2L_ZC */ 1163*4882a593Smuzhiyun #define WM8996_HPOUT2L_ZC_WIDTH 1 /* HPOUT2L_ZC */ 1164*4882a593Smuzhiyun #define WM8996_HPOUT2L_VOL_MASK 0x000F /* HPOUT2L_VOL - [3:0] */ 1165*4882a593Smuzhiyun #define WM8996_HPOUT2L_VOL_SHIFT 0 /* HPOUT2L_VOL - [3:0] */ 1166*4882a593Smuzhiyun #define WM8996_HPOUT2L_VOL_WIDTH 4 /* HPOUT2L_VOL - [3:0] */ 1167*4882a593Smuzhiyun 1168*4882a593Smuzhiyun /* 1169*4882a593Smuzhiyun * R31 (0x1F) - Output2 Right Volume 1170*4882a593Smuzhiyun */ 1171*4882a593Smuzhiyun #define WM8996_DAC2_VU 0x0100 /* DAC2_VU */ 1172*4882a593Smuzhiyun #define WM8996_DAC2_VU_MASK 0x0100 /* DAC2_VU */ 1173*4882a593Smuzhiyun #define WM8996_DAC2_VU_SHIFT 8 /* DAC2_VU */ 1174*4882a593Smuzhiyun #define WM8996_DAC2_VU_WIDTH 1 /* DAC2_VU */ 1175*4882a593Smuzhiyun #define WM8996_HPOUT2R_ZC 0x0080 /* HPOUT2R_ZC */ 1176*4882a593Smuzhiyun #define WM8996_HPOUT2R_ZC_MASK 0x0080 /* HPOUT2R_ZC */ 1177*4882a593Smuzhiyun #define WM8996_HPOUT2R_ZC_SHIFT 7 /* HPOUT2R_ZC */ 1178*4882a593Smuzhiyun #define WM8996_HPOUT2R_ZC_WIDTH 1 /* HPOUT2R_ZC */ 1179*4882a593Smuzhiyun #define WM8996_HPOUT2R_VOL_MASK 0x000F /* HPOUT2R_VOL - [3:0] */ 1180*4882a593Smuzhiyun #define WM8996_HPOUT2R_VOL_SHIFT 0 /* HPOUT2R_VOL - [3:0] */ 1181*4882a593Smuzhiyun #define WM8996_HPOUT2R_VOL_WIDTH 4 /* HPOUT2R_VOL - [3:0] */ 1182*4882a593Smuzhiyun 1183*4882a593Smuzhiyun /* 1184*4882a593Smuzhiyun * R32 (0x20) - MICBIAS (1) 1185*4882a593Smuzhiyun */ 1186*4882a593Smuzhiyun #define WM8996_MICB1_RATE 0x0020 /* MICB1_RATE */ 1187*4882a593Smuzhiyun #define WM8996_MICB1_RATE_MASK 0x0020 /* MICB1_RATE */ 1188*4882a593Smuzhiyun #define WM8996_MICB1_RATE_SHIFT 5 /* MICB1_RATE */ 1189*4882a593Smuzhiyun #define WM8996_MICB1_RATE_WIDTH 1 /* MICB1_RATE */ 1190*4882a593Smuzhiyun #define WM8996_MICB1_MODE 0x0010 /* MICB1_MODE */ 1191*4882a593Smuzhiyun #define WM8996_MICB1_MODE_MASK 0x0010 /* MICB1_MODE */ 1192*4882a593Smuzhiyun #define WM8996_MICB1_MODE_SHIFT 4 /* MICB1_MODE */ 1193*4882a593Smuzhiyun #define WM8996_MICB1_MODE_WIDTH 1 /* MICB1_MODE */ 1194*4882a593Smuzhiyun #define WM8996_MICB1_LVL_MASK 0x000E /* MICB1_LVL - [3:1] */ 1195*4882a593Smuzhiyun #define WM8996_MICB1_LVL_SHIFT 1 /* MICB1_LVL - [3:1] */ 1196*4882a593Smuzhiyun #define WM8996_MICB1_LVL_WIDTH 3 /* MICB1_LVL - [3:1] */ 1197*4882a593Smuzhiyun #define WM8996_MICB1_DISCH 0x0001 /* MICB1_DISCH */ 1198*4882a593Smuzhiyun #define WM8996_MICB1_DISCH_MASK 0x0001 /* MICB1_DISCH */ 1199*4882a593Smuzhiyun #define WM8996_MICB1_DISCH_SHIFT 0 /* MICB1_DISCH */ 1200*4882a593Smuzhiyun #define WM8996_MICB1_DISCH_WIDTH 1 /* MICB1_DISCH */ 1201*4882a593Smuzhiyun 1202*4882a593Smuzhiyun /* 1203*4882a593Smuzhiyun * R33 (0x21) - MICBIAS (2) 1204*4882a593Smuzhiyun */ 1205*4882a593Smuzhiyun #define WM8996_MICB2_RATE 0x0020 /* MICB2_RATE */ 1206*4882a593Smuzhiyun #define WM8996_MICB2_RATE_MASK 0x0020 /* MICB2_RATE */ 1207*4882a593Smuzhiyun #define WM8996_MICB2_RATE_SHIFT 5 /* MICB2_RATE */ 1208*4882a593Smuzhiyun #define WM8996_MICB2_RATE_WIDTH 1 /* MICB2_RATE */ 1209*4882a593Smuzhiyun #define WM8996_MICB2_MODE 0x0010 /* MICB2_MODE */ 1210*4882a593Smuzhiyun #define WM8996_MICB2_MODE_MASK 0x0010 /* MICB2_MODE */ 1211*4882a593Smuzhiyun #define WM8996_MICB2_MODE_SHIFT 4 /* MICB2_MODE */ 1212*4882a593Smuzhiyun #define WM8996_MICB2_MODE_WIDTH 1 /* MICB2_MODE */ 1213*4882a593Smuzhiyun #define WM8996_MICB2_LVL_MASK 0x000E /* MICB2_LVL - [3:1] */ 1214*4882a593Smuzhiyun #define WM8996_MICB2_LVL_SHIFT 1 /* MICB2_LVL - [3:1] */ 1215*4882a593Smuzhiyun #define WM8996_MICB2_LVL_WIDTH 3 /* MICB2_LVL - [3:1] */ 1216*4882a593Smuzhiyun #define WM8996_MICB2_DISCH 0x0001 /* MICB2_DISCH */ 1217*4882a593Smuzhiyun #define WM8996_MICB2_DISCH_MASK 0x0001 /* MICB2_DISCH */ 1218*4882a593Smuzhiyun #define WM8996_MICB2_DISCH_SHIFT 0 /* MICB2_DISCH */ 1219*4882a593Smuzhiyun #define WM8996_MICB2_DISCH_WIDTH 1 /* MICB2_DISCH */ 1220*4882a593Smuzhiyun 1221*4882a593Smuzhiyun /* 1222*4882a593Smuzhiyun * R40 (0x28) - LDO 1 1223*4882a593Smuzhiyun */ 1224*4882a593Smuzhiyun #define WM8996_LDO1_MODE 0x0020 /* LDO1_MODE */ 1225*4882a593Smuzhiyun #define WM8996_LDO1_MODE_MASK 0x0020 /* LDO1_MODE */ 1226*4882a593Smuzhiyun #define WM8996_LDO1_MODE_SHIFT 5 /* LDO1_MODE */ 1227*4882a593Smuzhiyun #define WM8996_LDO1_MODE_WIDTH 1 /* LDO1_MODE */ 1228*4882a593Smuzhiyun #define WM8996_LDO1_VSEL_MASK 0x0006 /* LDO1_VSEL - [2:1] */ 1229*4882a593Smuzhiyun #define WM8996_LDO1_VSEL_SHIFT 1 /* LDO1_VSEL - [2:1] */ 1230*4882a593Smuzhiyun #define WM8996_LDO1_VSEL_WIDTH 2 /* LDO1_VSEL - [2:1] */ 1231*4882a593Smuzhiyun #define WM8996_LDO1_DISCH 0x0001 /* LDO1_DISCH */ 1232*4882a593Smuzhiyun #define WM8996_LDO1_DISCH_MASK 0x0001 /* LDO1_DISCH */ 1233*4882a593Smuzhiyun #define WM8996_LDO1_DISCH_SHIFT 0 /* LDO1_DISCH */ 1234*4882a593Smuzhiyun #define WM8996_LDO1_DISCH_WIDTH 1 /* LDO1_DISCH */ 1235*4882a593Smuzhiyun 1236*4882a593Smuzhiyun /* 1237*4882a593Smuzhiyun * R41 (0x29) - LDO 2 1238*4882a593Smuzhiyun */ 1239*4882a593Smuzhiyun #define WM8996_LDO2_MODE 0x0020 /* LDO2_MODE */ 1240*4882a593Smuzhiyun #define WM8996_LDO2_MODE_MASK 0x0020 /* LDO2_MODE */ 1241*4882a593Smuzhiyun #define WM8996_LDO2_MODE_SHIFT 5 /* LDO2_MODE */ 1242*4882a593Smuzhiyun #define WM8996_LDO2_MODE_WIDTH 1 /* LDO2_MODE */ 1243*4882a593Smuzhiyun #define WM8996_LDO2_VSEL_MASK 0x001E /* LDO2_VSEL - [4:1] */ 1244*4882a593Smuzhiyun #define WM8996_LDO2_VSEL_SHIFT 1 /* LDO2_VSEL - [4:1] */ 1245*4882a593Smuzhiyun #define WM8996_LDO2_VSEL_WIDTH 4 /* LDO2_VSEL - [4:1] */ 1246*4882a593Smuzhiyun #define WM8996_LDO2_DISCH 0x0001 /* LDO2_DISCH */ 1247*4882a593Smuzhiyun #define WM8996_LDO2_DISCH_MASK 0x0001 /* LDO2_DISCH */ 1248*4882a593Smuzhiyun #define WM8996_LDO2_DISCH_SHIFT 0 /* LDO2_DISCH */ 1249*4882a593Smuzhiyun #define WM8996_LDO2_DISCH_WIDTH 1 /* LDO2_DISCH */ 1250*4882a593Smuzhiyun 1251*4882a593Smuzhiyun /* 1252*4882a593Smuzhiyun * R48 (0x30) - Accessory Detect Mode 1 1253*4882a593Smuzhiyun */ 1254*4882a593Smuzhiyun #define WM8996_JD_MODE_MASK 0x0003 /* JD_MODE - [1:0] */ 1255*4882a593Smuzhiyun #define WM8996_JD_MODE_SHIFT 0 /* JD_MODE - [1:0] */ 1256*4882a593Smuzhiyun #define WM8996_JD_MODE_WIDTH 2 /* JD_MODE - [1:0] */ 1257*4882a593Smuzhiyun 1258*4882a593Smuzhiyun /* 1259*4882a593Smuzhiyun * R49 (0x31) - Accessory Detect Mode 2 1260*4882a593Smuzhiyun */ 1261*4882a593Smuzhiyun #define WM8996_HPOUT1FB_SRC 0x0004 /* HPOUT1FB_SRC */ 1262*4882a593Smuzhiyun #define WM8996_HPOUT1FB_SRC_MASK 0x0004 /* HPOUT1FB_SRC */ 1263*4882a593Smuzhiyun #define WM8996_HPOUT1FB_SRC_SHIFT 2 /* HPOUT1FB_SRC */ 1264*4882a593Smuzhiyun #define WM8996_HPOUT1FB_SRC_WIDTH 1 /* HPOUT1FB_SRC */ 1265*4882a593Smuzhiyun #define WM8996_MICD_SRC 0x0002 /* MICD_SRC */ 1266*4882a593Smuzhiyun #define WM8996_MICD_SRC_MASK 0x0002 /* MICD_SRC */ 1267*4882a593Smuzhiyun #define WM8996_MICD_SRC_SHIFT 1 /* MICD_SRC */ 1268*4882a593Smuzhiyun #define WM8996_MICD_SRC_WIDTH 1 /* MICD_SRC */ 1269*4882a593Smuzhiyun #define WM8996_MICD_BIAS_SRC 0x0001 /* MICD_BIAS_SRC */ 1270*4882a593Smuzhiyun #define WM8996_MICD_BIAS_SRC_MASK 0x0001 /* MICD_BIAS_SRC */ 1271*4882a593Smuzhiyun #define WM8996_MICD_BIAS_SRC_SHIFT 0 /* MICD_BIAS_SRC */ 1272*4882a593Smuzhiyun #define WM8996_MICD_BIAS_SRC_WIDTH 1 /* MICD_BIAS_SRC */ 1273*4882a593Smuzhiyun 1274*4882a593Smuzhiyun /* 1275*4882a593Smuzhiyun * R52 (0x34) - Headphone Detect 1 1276*4882a593Smuzhiyun */ 1277*4882a593Smuzhiyun #define WM8996_HP_HOLDTIME_MASK 0x00E0 /* HP_HOLDTIME - [7:5] */ 1278*4882a593Smuzhiyun #define WM8996_HP_HOLDTIME_SHIFT 5 /* HP_HOLDTIME - [7:5] */ 1279*4882a593Smuzhiyun #define WM8996_HP_HOLDTIME_WIDTH 3 /* HP_HOLDTIME - [7:5] */ 1280*4882a593Smuzhiyun #define WM8996_HP_CLK_DIV_MASK 0x0018 /* HP_CLK_DIV - [4:3] */ 1281*4882a593Smuzhiyun #define WM8996_HP_CLK_DIV_SHIFT 3 /* HP_CLK_DIV - [4:3] */ 1282*4882a593Smuzhiyun #define WM8996_HP_CLK_DIV_WIDTH 2 /* HP_CLK_DIV - [4:3] */ 1283*4882a593Smuzhiyun #define WM8996_HP_STEP_SIZE 0x0002 /* HP_STEP_SIZE */ 1284*4882a593Smuzhiyun #define WM8996_HP_STEP_SIZE_MASK 0x0002 /* HP_STEP_SIZE */ 1285*4882a593Smuzhiyun #define WM8996_HP_STEP_SIZE_SHIFT 1 /* HP_STEP_SIZE */ 1286*4882a593Smuzhiyun #define WM8996_HP_STEP_SIZE_WIDTH 1 /* HP_STEP_SIZE */ 1287*4882a593Smuzhiyun #define WM8996_HP_POLL 0x0001 /* HP_POLL */ 1288*4882a593Smuzhiyun #define WM8996_HP_POLL_MASK 0x0001 /* HP_POLL */ 1289*4882a593Smuzhiyun #define WM8996_HP_POLL_SHIFT 0 /* HP_POLL */ 1290*4882a593Smuzhiyun #define WM8996_HP_POLL_WIDTH 1 /* HP_POLL */ 1291*4882a593Smuzhiyun 1292*4882a593Smuzhiyun /* 1293*4882a593Smuzhiyun * R53 (0x35) - Headphone Detect 2 1294*4882a593Smuzhiyun */ 1295*4882a593Smuzhiyun #define WM8996_HP_DONE 0x0080 /* HP_DONE */ 1296*4882a593Smuzhiyun #define WM8996_HP_DONE_MASK 0x0080 /* HP_DONE */ 1297*4882a593Smuzhiyun #define WM8996_HP_DONE_SHIFT 7 /* HP_DONE */ 1298*4882a593Smuzhiyun #define WM8996_HP_DONE_WIDTH 1 /* HP_DONE */ 1299*4882a593Smuzhiyun #define WM8996_HP_LVL_MASK 0x007F /* HP_LVL - [6:0] */ 1300*4882a593Smuzhiyun #define WM8996_HP_LVL_SHIFT 0 /* HP_LVL - [6:0] */ 1301*4882a593Smuzhiyun #define WM8996_HP_LVL_WIDTH 7 /* HP_LVL - [6:0] */ 1302*4882a593Smuzhiyun 1303*4882a593Smuzhiyun /* 1304*4882a593Smuzhiyun * R56 (0x38) - Mic Detect 1 1305*4882a593Smuzhiyun */ 1306*4882a593Smuzhiyun #define WM8996_MICD_BIAS_STARTTIME_MASK 0xF000 /* MICD_BIAS_STARTTIME - [15:12] */ 1307*4882a593Smuzhiyun #define WM8996_MICD_BIAS_STARTTIME_SHIFT 12 /* MICD_BIAS_STARTTIME - [15:12] */ 1308*4882a593Smuzhiyun #define WM8996_MICD_BIAS_STARTTIME_WIDTH 4 /* MICD_BIAS_STARTTIME - [15:12] */ 1309*4882a593Smuzhiyun #define WM8996_MICD_RATE_MASK 0x0F00 /* MICD_RATE - [11:8] */ 1310*4882a593Smuzhiyun #define WM8996_MICD_RATE_SHIFT 8 /* MICD_RATE - [11:8] */ 1311*4882a593Smuzhiyun #define WM8996_MICD_RATE_WIDTH 4 /* MICD_RATE - [11:8] */ 1312*4882a593Smuzhiyun #define WM8996_MICD_DBTIME 0x0002 /* MICD_DBTIME */ 1313*4882a593Smuzhiyun #define WM8996_MICD_DBTIME_MASK 0x0002 /* MICD_DBTIME */ 1314*4882a593Smuzhiyun #define WM8996_MICD_DBTIME_SHIFT 1 /* MICD_DBTIME */ 1315*4882a593Smuzhiyun #define WM8996_MICD_DBTIME_WIDTH 1 /* MICD_DBTIME */ 1316*4882a593Smuzhiyun #define WM8996_MICD_ENA 0x0001 /* MICD_ENA */ 1317*4882a593Smuzhiyun #define WM8996_MICD_ENA_MASK 0x0001 /* MICD_ENA */ 1318*4882a593Smuzhiyun #define WM8996_MICD_ENA_SHIFT 0 /* MICD_ENA */ 1319*4882a593Smuzhiyun #define WM8996_MICD_ENA_WIDTH 1 /* MICD_ENA */ 1320*4882a593Smuzhiyun 1321*4882a593Smuzhiyun /* 1322*4882a593Smuzhiyun * R57 (0x39) - Mic Detect 2 1323*4882a593Smuzhiyun */ 1324*4882a593Smuzhiyun #define WM8996_MICD_LVL_SEL_MASK 0x00FF /* MICD_LVL_SEL - [7:0] */ 1325*4882a593Smuzhiyun #define WM8996_MICD_LVL_SEL_SHIFT 0 /* MICD_LVL_SEL - [7:0] */ 1326*4882a593Smuzhiyun #define WM8996_MICD_LVL_SEL_WIDTH 8 /* MICD_LVL_SEL - [7:0] */ 1327*4882a593Smuzhiyun 1328*4882a593Smuzhiyun /* 1329*4882a593Smuzhiyun * R58 (0x3A) - Mic Detect 3 1330*4882a593Smuzhiyun */ 1331*4882a593Smuzhiyun #define WM8996_MICD_LVL_MASK 0x07FC /* MICD_LVL - [10:2] */ 1332*4882a593Smuzhiyun #define WM8996_MICD_LVL_SHIFT 2 /* MICD_LVL - [10:2] */ 1333*4882a593Smuzhiyun #define WM8996_MICD_LVL_WIDTH 9 /* MICD_LVL - [10:2] */ 1334*4882a593Smuzhiyun #define WM8996_MICD_VALID 0x0002 /* MICD_VALID */ 1335*4882a593Smuzhiyun #define WM8996_MICD_VALID_MASK 0x0002 /* MICD_VALID */ 1336*4882a593Smuzhiyun #define WM8996_MICD_VALID_SHIFT 1 /* MICD_VALID */ 1337*4882a593Smuzhiyun #define WM8996_MICD_VALID_WIDTH 1 /* MICD_VALID */ 1338*4882a593Smuzhiyun #define WM8996_MICD_STS 0x0001 /* MICD_STS */ 1339*4882a593Smuzhiyun #define WM8996_MICD_STS_MASK 0x0001 /* MICD_STS */ 1340*4882a593Smuzhiyun #define WM8996_MICD_STS_SHIFT 0 /* MICD_STS */ 1341*4882a593Smuzhiyun #define WM8996_MICD_STS_WIDTH 1 /* MICD_STS */ 1342*4882a593Smuzhiyun 1343*4882a593Smuzhiyun /* 1344*4882a593Smuzhiyun * R64 (0x40) - Charge Pump (1) 1345*4882a593Smuzhiyun */ 1346*4882a593Smuzhiyun #define WM8996_CP_ENA 0x8000 /* CP_ENA */ 1347*4882a593Smuzhiyun #define WM8996_CP_ENA_MASK 0x8000 /* CP_ENA */ 1348*4882a593Smuzhiyun #define WM8996_CP_ENA_SHIFT 15 /* CP_ENA */ 1349*4882a593Smuzhiyun #define WM8996_CP_ENA_WIDTH 1 /* CP_ENA */ 1350*4882a593Smuzhiyun 1351*4882a593Smuzhiyun /* 1352*4882a593Smuzhiyun * R65 (0x41) - Charge Pump (2) 1353*4882a593Smuzhiyun */ 1354*4882a593Smuzhiyun #define WM8996_CP_DISCH 0x8000 /* CP_DISCH */ 1355*4882a593Smuzhiyun #define WM8996_CP_DISCH_MASK 0x8000 /* CP_DISCH */ 1356*4882a593Smuzhiyun #define WM8996_CP_DISCH_SHIFT 15 /* CP_DISCH */ 1357*4882a593Smuzhiyun #define WM8996_CP_DISCH_WIDTH 1 /* CP_DISCH */ 1358*4882a593Smuzhiyun 1359*4882a593Smuzhiyun /* 1360*4882a593Smuzhiyun * R80 (0x50) - DC Servo (1) 1361*4882a593Smuzhiyun */ 1362*4882a593Smuzhiyun #define WM8996_DCS_ENA_CHAN_3 0x0008 /* DCS_ENA_CHAN_3 */ 1363*4882a593Smuzhiyun #define WM8996_DCS_ENA_CHAN_3_MASK 0x0008 /* DCS_ENA_CHAN_3 */ 1364*4882a593Smuzhiyun #define WM8996_DCS_ENA_CHAN_3_SHIFT 3 /* DCS_ENA_CHAN_3 */ 1365*4882a593Smuzhiyun #define WM8996_DCS_ENA_CHAN_3_WIDTH 1 /* DCS_ENA_CHAN_3 */ 1366*4882a593Smuzhiyun #define WM8996_DCS_ENA_CHAN_2 0x0004 /* DCS_ENA_CHAN_2 */ 1367*4882a593Smuzhiyun #define WM8996_DCS_ENA_CHAN_2_MASK 0x0004 /* DCS_ENA_CHAN_2 */ 1368*4882a593Smuzhiyun #define WM8996_DCS_ENA_CHAN_2_SHIFT 2 /* DCS_ENA_CHAN_2 */ 1369*4882a593Smuzhiyun #define WM8996_DCS_ENA_CHAN_2_WIDTH 1 /* DCS_ENA_CHAN_2 */ 1370*4882a593Smuzhiyun #define WM8996_DCS_ENA_CHAN_1 0x0002 /* DCS_ENA_CHAN_1 */ 1371*4882a593Smuzhiyun #define WM8996_DCS_ENA_CHAN_1_MASK 0x0002 /* DCS_ENA_CHAN_1 */ 1372*4882a593Smuzhiyun #define WM8996_DCS_ENA_CHAN_1_SHIFT 1 /* DCS_ENA_CHAN_1 */ 1373*4882a593Smuzhiyun #define WM8996_DCS_ENA_CHAN_1_WIDTH 1 /* DCS_ENA_CHAN_1 */ 1374*4882a593Smuzhiyun #define WM8996_DCS_ENA_CHAN_0 0x0001 /* DCS_ENA_CHAN_0 */ 1375*4882a593Smuzhiyun #define WM8996_DCS_ENA_CHAN_0_MASK 0x0001 /* DCS_ENA_CHAN_0 */ 1376*4882a593Smuzhiyun #define WM8996_DCS_ENA_CHAN_0_SHIFT 0 /* DCS_ENA_CHAN_0 */ 1377*4882a593Smuzhiyun #define WM8996_DCS_ENA_CHAN_0_WIDTH 1 /* DCS_ENA_CHAN_0 */ 1378*4882a593Smuzhiyun 1379*4882a593Smuzhiyun /* 1380*4882a593Smuzhiyun * R81 (0x51) - DC Servo (2) 1381*4882a593Smuzhiyun */ 1382*4882a593Smuzhiyun #define WM8996_DCS_TRIG_SINGLE_3 0x8000 /* DCS_TRIG_SINGLE_3 */ 1383*4882a593Smuzhiyun #define WM8996_DCS_TRIG_SINGLE_3_MASK 0x8000 /* DCS_TRIG_SINGLE_3 */ 1384*4882a593Smuzhiyun #define WM8996_DCS_TRIG_SINGLE_3_SHIFT 15 /* DCS_TRIG_SINGLE_3 */ 1385*4882a593Smuzhiyun #define WM8996_DCS_TRIG_SINGLE_3_WIDTH 1 /* DCS_TRIG_SINGLE_3 */ 1386*4882a593Smuzhiyun #define WM8996_DCS_TRIG_SINGLE_2 0x4000 /* DCS_TRIG_SINGLE_2 */ 1387*4882a593Smuzhiyun #define WM8996_DCS_TRIG_SINGLE_2_MASK 0x4000 /* DCS_TRIG_SINGLE_2 */ 1388*4882a593Smuzhiyun #define WM8996_DCS_TRIG_SINGLE_2_SHIFT 14 /* DCS_TRIG_SINGLE_2 */ 1389*4882a593Smuzhiyun #define WM8996_DCS_TRIG_SINGLE_2_WIDTH 1 /* DCS_TRIG_SINGLE_2 */ 1390*4882a593Smuzhiyun #define WM8996_DCS_TRIG_SINGLE_1 0x2000 /* DCS_TRIG_SINGLE_1 */ 1391*4882a593Smuzhiyun #define WM8996_DCS_TRIG_SINGLE_1_MASK 0x2000 /* DCS_TRIG_SINGLE_1 */ 1392*4882a593Smuzhiyun #define WM8996_DCS_TRIG_SINGLE_1_SHIFT 13 /* DCS_TRIG_SINGLE_1 */ 1393*4882a593Smuzhiyun #define WM8996_DCS_TRIG_SINGLE_1_WIDTH 1 /* DCS_TRIG_SINGLE_1 */ 1394*4882a593Smuzhiyun #define WM8996_DCS_TRIG_SINGLE_0 0x1000 /* DCS_TRIG_SINGLE_0 */ 1395*4882a593Smuzhiyun #define WM8996_DCS_TRIG_SINGLE_0_MASK 0x1000 /* DCS_TRIG_SINGLE_0 */ 1396*4882a593Smuzhiyun #define WM8996_DCS_TRIG_SINGLE_0_SHIFT 12 /* DCS_TRIG_SINGLE_0 */ 1397*4882a593Smuzhiyun #define WM8996_DCS_TRIG_SINGLE_0_WIDTH 1 /* DCS_TRIG_SINGLE_0 */ 1398*4882a593Smuzhiyun #define WM8996_DCS_TRIG_SERIES_3 0x0800 /* DCS_TRIG_SERIES_3 */ 1399*4882a593Smuzhiyun #define WM8996_DCS_TRIG_SERIES_3_MASK 0x0800 /* DCS_TRIG_SERIES_3 */ 1400*4882a593Smuzhiyun #define WM8996_DCS_TRIG_SERIES_3_SHIFT 11 /* DCS_TRIG_SERIES_3 */ 1401*4882a593Smuzhiyun #define WM8996_DCS_TRIG_SERIES_3_WIDTH 1 /* DCS_TRIG_SERIES_3 */ 1402*4882a593Smuzhiyun #define WM8996_DCS_TRIG_SERIES_2 0x0400 /* DCS_TRIG_SERIES_2 */ 1403*4882a593Smuzhiyun #define WM8996_DCS_TRIG_SERIES_2_MASK 0x0400 /* DCS_TRIG_SERIES_2 */ 1404*4882a593Smuzhiyun #define WM8996_DCS_TRIG_SERIES_2_SHIFT 10 /* DCS_TRIG_SERIES_2 */ 1405*4882a593Smuzhiyun #define WM8996_DCS_TRIG_SERIES_2_WIDTH 1 /* DCS_TRIG_SERIES_2 */ 1406*4882a593Smuzhiyun #define WM8996_DCS_TRIG_SERIES_1 0x0200 /* DCS_TRIG_SERIES_1 */ 1407*4882a593Smuzhiyun #define WM8996_DCS_TRIG_SERIES_1_MASK 0x0200 /* DCS_TRIG_SERIES_1 */ 1408*4882a593Smuzhiyun #define WM8996_DCS_TRIG_SERIES_1_SHIFT 9 /* DCS_TRIG_SERIES_1 */ 1409*4882a593Smuzhiyun #define WM8996_DCS_TRIG_SERIES_1_WIDTH 1 /* DCS_TRIG_SERIES_1 */ 1410*4882a593Smuzhiyun #define WM8996_DCS_TRIG_SERIES_0 0x0100 /* DCS_TRIG_SERIES_0 */ 1411*4882a593Smuzhiyun #define WM8996_DCS_TRIG_SERIES_0_MASK 0x0100 /* DCS_TRIG_SERIES_0 */ 1412*4882a593Smuzhiyun #define WM8996_DCS_TRIG_SERIES_0_SHIFT 8 /* DCS_TRIG_SERIES_0 */ 1413*4882a593Smuzhiyun #define WM8996_DCS_TRIG_SERIES_0_WIDTH 1 /* DCS_TRIG_SERIES_0 */ 1414*4882a593Smuzhiyun #define WM8996_DCS_TRIG_STARTUP_3 0x0080 /* DCS_TRIG_STARTUP_3 */ 1415*4882a593Smuzhiyun #define WM8996_DCS_TRIG_STARTUP_3_MASK 0x0080 /* DCS_TRIG_STARTUP_3 */ 1416*4882a593Smuzhiyun #define WM8996_DCS_TRIG_STARTUP_3_SHIFT 7 /* DCS_TRIG_STARTUP_3 */ 1417*4882a593Smuzhiyun #define WM8996_DCS_TRIG_STARTUP_3_WIDTH 1 /* DCS_TRIG_STARTUP_3 */ 1418*4882a593Smuzhiyun #define WM8996_DCS_TRIG_STARTUP_2 0x0040 /* DCS_TRIG_STARTUP_2 */ 1419*4882a593Smuzhiyun #define WM8996_DCS_TRIG_STARTUP_2_MASK 0x0040 /* DCS_TRIG_STARTUP_2 */ 1420*4882a593Smuzhiyun #define WM8996_DCS_TRIG_STARTUP_2_SHIFT 6 /* DCS_TRIG_STARTUP_2 */ 1421*4882a593Smuzhiyun #define WM8996_DCS_TRIG_STARTUP_2_WIDTH 1 /* DCS_TRIG_STARTUP_2 */ 1422*4882a593Smuzhiyun #define WM8996_DCS_TRIG_STARTUP_1 0x0020 /* DCS_TRIG_STARTUP_1 */ 1423*4882a593Smuzhiyun #define WM8996_DCS_TRIG_STARTUP_1_MASK 0x0020 /* DCS_TRIG_STARTUP_1 */ 1424*4882a593Smuzhiyun #define WM8996_DCS_TRIG_STARTUP_1_SHIFT 5 /* DCS_TRIG_STARTUP_1 */ 1425*4882a593Smuzhiyun #define WM8996_DCS_TRIG_STARTUP_1_WIDTH 1 /* DCS_TRIG_STARTUP_1 */ 1426*4882a593Smuzhiyun #define WM8996_DCS_TRIG_STARTUP_0 0x0010 /* DCS_TRIG_STARTUP_0 */ 1427*4882a593Smuzhiyun #define WM8996_DCS_TRIG_STARTUP_0_MASK 0x0010 /* DCS_TRIG_STARTUP_0 */ 1428*4882a593Smuzhiyun #define WM8996_DCS_TRIG_STARTUP_0_SHIFT 4 /* DCS_TRIG_STARTUP_0 */ 1429*4882a593Smuzhiyun #define WM8996_DCS_TRIG_STARTUP_0_WIDTH 1 /* DCS_TRIG_STARTUP_0 */ 1430*4882a593Smuzhiyun #define WM8996_DCS_TRIG_DAC_WR_3 0x0008 /* DCS_TRIG_DAC_WR_3 */ 1431*4882a593Smuzhiyun #define WM8996_DCS_TRIG_DAC_WR_3_MASK 0x0008 /* DCS_TRIG_DAC_WR_3 */ 1432*4882a593Smuzhiyun #define WM8996_DCS_TRIG_DAC_WR_3_SHIFT 3 /* DCS_TRIG_DAC_WR_3 */ 1433*4882a593Smuzhiyun #define WM8996_DCS_TRIG_DAC_WR_3_WIDTH 1 /* DCS_TRIG_DAC_WR_3 */ 1434*4882a593Smuzhiyun #define WM8996_DCS_TRIG_DAC_WR_2 0x0004 /* DCS_TRIG_DAC_WR_2 */ 1435*4882a593Smuzhiyun #define WM8996_DCS_TRIG_DAC_WR_2_MASK 0x0004 /* DCS_TRIG_DAC_WR_2 */ 1436*4882a593Smuzhiyun #define WM8996_DCS_TRIG_DAC_WR_2_SHIFT 2 /* DCS_TRIG_DAC_WR_2 */ 1437*4882a593Smuzhiyun #define WM8996_DCS_TRIG_DAC_WR_2_WIDTH 1 /* DCS_TRIG_DAC_WR_2 */ 1438*4882a593Smuzhiyun #define WM8996_DCS_TRIG_DAC_WR_1 0x0002 /* DCS_TRIG_DAC_WR_1 */ 1439*4882a593Smuzhiyun #define WM8996_DCS_TRIG_DAC_WR_1_MASK 0x0002 /* DCS_TRIG_DAC_WR_1 */ 1440*4882a593Smuzhiyun #define WM8996_DCS_TRIG_DAC_WR_1_SHIFT 1 /* DCS_TRIG_DAC_WR_1 */ 1441*4882a593Smuzhiyun #define WM8996_DCS_TRIG_DAC_WR_1_WIDTH 1 /* DCS_TRIG_DAC_WR_1 */ 1442*4882a593Smuzhiyun #define WM8996_DCS_TRIG_DAC_WR_0 0x0001 /* DCS_TRIG_DAC_WR_0 */ 1443*4882a593Smuzhiyun #define WM8996_DCS_TRIG_DAC_WR_0_MASK 0x0001 /* DCS_TRIG_DAC_WR_0 */ 1444*4882a593Smuzhiyun #define WM8996_DCS_TRIG_DAC_WR_0_SHIFT 0 /* DCS_TRIG_DAC_WR_0 */ 1445*4882a593Smuzhiyun #define WM8996_DCS_TRIG_DAC_WR_0_WIDTH 1 /* DCS_TRIG_DAC_WR_0 */ 1446*4882a593Smuzhiyun 1447*4882a593Smuzhiyun /* 1448*4882a593Smuzhiyun * R82 (0x52) - DC Servo (3) 1449*4882a593Smuzhiyun */ 1450*4882a593Smuzhiyun #define WM8996_DCS_TIMER_PERIOD_23_MASK 0x0F00 /* DCS_TIMER_PERIOD_23 - [11:8] */ 1451*4882a593Smuzhiyun #define WM8996_DCS_TIMER_PERIOD_23_SHIFT 8 /* DCS_TIMER_PERIOD_23 - [11:8] */ 1452*4882a593Smuzhiyun #define WM8996_DCS_TIMER_PERIOD_23_WIDTH 4 /* DCS_TIMER_PERIOD_23 - [11:8] */ 1453*4882a593Smuzhiyun #define WM8996_DCS_TIMER_PERIOD_01_MASK 0x000F /* DCS_TIMER_PERIOD_01 - [3:0] */ 1454*4882a593Smuzhiyun #define WM8996_DCS_TIMER_PERIOD_01_SHIFT 0 /* DCS_TIMER_PERIOD_01 - [3:0] */ 1455*4882a593Smuzhiyun #define WM8996_DCS_TIMER_PERIOD_01_WIDTH 4 /* DCS_TIMER_PERIOD_01 - [3:0] */ 1456*4882a593Smuzhiyun 1457*4882a593Smuzhiyun /* 1458*4882a593Smuzhiyun * R84 (0x54) - DC Servo (5) 1459*4882a593Smuzhiyun */ 1460*4882a593Smuzhiyun #define WM8996_DCS_SERIES_NO_23_MASK 0x7F00 /* DCS_SERIES_NO_23 - [14:8] */ 1461*4882a593Smuzhiyun #define WM8996_DCS_SERIES_NO_23_SHIFT 8 /* DCS_SERIES_NO_23 - [14:8] */ 1462*4882a593Smuzhiyun #define WM8996_DCS_SERIES_NO_23_WIDTH 7 /* DCS_SERIES_NO_23 - [14:8] */ 1463*4882a593Smuzhiyun #define WM8996_DCS_SERIES_NO_01_MASK 0x007F /* DCS_SERIES_NO_01 - [6:0] */ 1464*4882a593Smuzhiyun #define WM8996_DCS_SERIES_NO_01_SHIFT 0 /* DCS_SERIES_NO_01 - [6:0] */ 1465*4882a593Smuzhiyun #define WM8996_DCS_SERIES_NO_01_WIDTH 7 /* DCS_SERIES_NO_01 - [6:0] */ 1466*4882a593Smuzhiyun 1467*4882a593Smuzhiyun /* 1468*4882a593Smuzhiyun * R85 (0x55) - DC Servo (6) 1469*4882a593Smuzhiyun */ 1470*4882a593Smuzhiyun #define WM8996_DCS_DAC_WR_VAL_3_MASK 0xFF00 /* DCS_DAC_WR_VAL_3 - [15:8] */ 1471*4882a593Smuzhiyun #define WM8996_DCS_DAC_WR_VAL_3_SHIFT 8 /* DCS_DAC_WR_VAL_3 - [15:8] */ 1472*4882a593Smuzhiyun #define WM8996_DCS_DAC_WR_VAL_3_WIDTH 8 /* DCS_DAC_WR_VAL_3 - [15:8] */ 1473*4882a593Smuzhiyun #define WM8996_DCS_DAC_WR_VAL_2_MASK 0x00FF /* DCS_DAC_WR_VAL_2 - [7:0] */ 1474*4882a593Smuzhiyun #define WM8996_DCS_DAC_WR_VAL_2_SHIFT 0 /* DCS_DAC_WR_VAL_2 - [7:0] */ 1475*4882a593Smuzhiyun #define WM8996_DCS_DAC_WR_VAL_2_WIDTH 8 /* DCS_DAC_WR_VAL_2 - [7:0] */ 1476*4882a593Smuzhiyun 1477*4882a593Smuzhiyun /* 1478*4882a593Smuzhiyun * R86 (0x56) - DC Servo (7) 1479*4882a593Smuzhiyun */ 1480*4882a593Smuzhiyun #define WM8996_DCS_DAC_WR_VAL_1_MASK 0xFF00 /* DCS_DAC_WR_VAL_1 - [15:8] */ 1481*4882a593Smuzhiyun #define WM8996_DCS_DAC_WR_VAL_1_SHIFT 8 /* DCS_DAC_WR_VAL_1 - [15:8] */ 1482*4882a593Smuzhiyun #define WM8996_DCS_DAC_WR_VAL_1_WIDTH 8 /* DCS_DAC_WR_VAL_1 - [15:8] */ 1483*4882a593Smuzhiyun #define WM8996_DCS_DAC_WR_VAL_0_MASK 0x00FF /* DCS_DAC_WR_VAL_0 - [7:0] */ 1484*4882a593Smuzhiyun #define WM8996_DCS_DAC_WR_VAL_0_SHIFT 0 /* DCS_DAC_WR_VAL_0 - [7:0] */ 1485*4882a593Smuzhiyun #define WM8996_DCS_DAC_WR_VAL_0_WIDTH 8 /* DCS_DAC_WR_VAL_0 - [7:0] */ 1486*4882a593Smuzhiyun 1487*4882a593Smuzhiyun /* 1488*4882a593Smuzhiyun * R87 (0x57) - DC Servo Readback 0 1489*4882a593Smuzhiyun */ 1490*4882a593Smuzhiyun #define WM8996_DCS_CAL_COMPLETE_MASK 0x0F00 /* DCS_CAL_COMPLETE - [11:8] */ 1491*4882a593Smuzhiyun #define WM8996_DCS_CAL_COMPLETE_SHIFT 8 /* DCS_CAL_COMPLETE - [11:8] */ 1492*4882a593Smuzhiyun #define WM8996_DCS_CAL_COMPLETE_WIDTH 4 /* DCS_CAL_COMPLETE - [11:8] */ 1493*4882a593Smuzhiyun #define WM8996_DCS_DAC_WR_COMPLETE_MASK 0x00F0 /* DCS_DAC_WR_COMPLETE - [7:4] */ 1494*4882a593Smuzhiyun #define WM8996_DCS_DAC_WR_COMPLETE_SHIFT 4 /* DCS_DAC_WR_COMPLETE - [7:4] */ 1495*4882a593Smuzhiyun #define WM8996_DCS_DAC_WR_COMPLETE_WIDTH 4 /* DCS_DAC_WR_COMPLETE - [7:4] */ 1496*4882a593Smuzhiyun #define WM8996_DCS_STARTUP_COMPLETE_MASK 0x000F /* DCS_STARTUP_COMPLETE - [3:0] */ 1497*4882a593Smuzhiyun #define WM8996_DCS_STARTUP_COMPLETE_SHIFT 0 /* DCS_STARTUP_COMPLETE - [3:0] */ 1498*4882a593Smuzhiyun #define WM8996_DCS_STARTUP_COMPLETE_WIDTH 4 /* DCS_STARTUP_COMPLETE - [3:0] */ 1499*4882a593Smuzhiyun 1500*4882a593Smuzhiyun /* 1501*4882a593Smuzhiyun * R96 (0x60) - Analogue HP (1) 1502*4882a593Smuzhiyun */ 1503*4882a593Smuzhiyun #define WM8996_HPOUT1L_RMV_SHORT 0x0080 /* HPOUT1L_RMV_SHORT */ 1504*4882a593Smuzhiyun #define WM8996_HPOUT1L_RMV_SHORT_MASK 0x0080 /* HPOUT1L_RMV_SHORT */ 1505*4882a593Smuzhiyun #define WM8996_HPOUT1L_RMV_SHORT_SHIFT 7 /* HPOUT1L_RMV_SHORT */ 1506*4882a593Smuzhiyun #define WM8996_HPOUT1L_RMV_SHORT_WIDTH 1 /* HPOUT1L_RMV_SHORT */ 1507*4882a593Smuzhiyun #define WM8996_HPOUT1L_OUTP 0x0040 /* HPOUT1L_OUTP */ 1508*4882a593Smuzhiyun #define WM8996_HPOUT1L_OUTP_MASK 0x0040 /* HPOUT1L_OUTP */ 1509*4882a593Smuzhiyun #define WM8996_HPOUT1L_OUTP_SHIFT 6 /* HPOUT1L_OUTP */ 1510*4882a593Smuzhiyun #define WM8996_HPOUT1L_OUTP_WIDTH 1 /* HPOUT1L_OUTP */ 1511*4882a593Smuzhiyun #define WM8996_HPOUT1L_DLY 0x0020 /* HPOUT1L_DLY */ 1512*4882a593Smuzhiyun #define WM8996_HPOUT1L_DLY_MASK 0x0020 /* HPOUT1L_DLY */ 1513*4882a593Smuzhiyun #define WM8996_HPOUT1L_DLY_SHIFT 5 /* HPOUT1L_DLY */ 1514*4882a593Smuzhiyun #define WM8996_HPOUT1L_DLY_WIDTH 1 /* HPOUT1L_DLY */ 1515*4882a593Smuzhiyun #define WM8996_HPOUT1R_RMV_SHORT 0x0008 /* HPOUT1R_RMV_SHORT */ 1516*4882a593Smuzhiyun #define WM8996_HPOUT1R_RMV_SHORT_MASK 0x0008 /* HPOUT1R_RMV_SHORT */ 1517*4882a593Smuzhiyun #define WM8996_HPOUT1R_RMV_SHORT_SHIFT 3 /* HPOUT1R_RMV_SHORT */ 1518*4882a593Smuzhiyun #define WM8996_HPOUT1R_RMV_SHORT_WIDTH 1 /* HPOUT1R_RMV_SHORT */ 1519*4882a593Smuzhiyun #define WM8996_HPOUT1R_OUTP 0x0004 /* HPOUT1R_OUTP */ 1520*4882a593Smuzhiyun #define WM8996_HPOUT1R_OUTP_MASK 0x0004 /* HPOUT1R_OUTP */ 1521*4882a593Smuzhiyun #define WM8996_HPOUT1R_OUTP_SHIFT 2 /* HPOUT1R_OUTP */ 1522*4882a593Smuzhiyun #define WM8996_HPOUT1R_OUTP_WIDTH 1 /* HPOUT1R_OUTP */ 1523*4882a593Smuzhiyun #define WM8996_HPOUT1R_DLY 0x0002 /* HPOUT1R_DLY */ 1524*4882a593Smuzhiyun #define WM8996_HPOUT1R_DLY_MASK 0x0002 /* HPOUT1R_DLY */ 1525*4882a593Smuzhiyun #define WM8996_HPOUT1R_DLY_SHIFT 1 /* HPOUT1R_DLY */ 1526*4882a593Smuzhiyun #define WM8996_HPOUT1R_DLY_WIDTH 1 /* HPOUT1R_DLY */ 1527*4882a593Smuzhiyun 1528*4882a593Smuzhiyun /* 1529*4882a593Smuzhiyun * R97 (0x61) - Analogue HP (2) 1530*4882a593Smuzhiyun */ 1531*4882a593Smuzhiyun #define WM8996_HPOUT2L_RMV_SHORT 0x0080 /* HPOUT2L_RMV_SHORT */ 1532*4882a593Smuzhiyun #define WM8996_HPOUT2L_RMV_SHORT_MASK 0x0080 /* HPOUT2L_RMV_SHORT */ 1533*4882a593Smuzhiyun #define WM8996_HPOUT2L_RMV_SHORT_SHIFT 7 /* HPOUT2L_RMV_SHORT */ 1534*4882a593Smuzhiyun #define WM8996_HPOUT2L_RMV_SHORT_WIDTH 1 /* HPOUT2L_RMV_SHORT */ 1535*4882a593Smuzhiyun #define WM8996_HPOUT2L_OUTP 0x0040 /* HPOUT2L_OUTP */ 1536*4882a593Smuzhiyun #define WM8996_HPOUT2L_OUTP_MASK 0x0040 /* HPOUT2L_OUTP */ 1537*4882a593Smuzhiyun #define WM8996_HPOUT2L_OUTP_SHIFT 6 /* HPOUT2L_OUTP */ 1538*4882a593Smuzhiyun #define WM8996_HPOUT2L_OUTP_WIDTH 1 /* HPOUT2L_OUTP */ 1539*4882a593Smuzhiyun #define WM8996_HPOUT2L_DLY 0x0020 /* HPOUT2L_DLY */ 1540*4882a593Smuzhiyun #define WM8996_HPOUT2L_DLY_MASK 0x0020 /* HPOUT2L_DLY */ 1541*4882a593Smuzhiyun #define WM8996_HPOUT2L_DLY_SHIFT 5 /* HPOUT2L_DLY */ 1542*4882a593Smuzhiyun #define WM8996_HPOUT2L_DLY_WIDTH 1 /* HPOUT2L_DLY */ 1543*4882a593Smuzhiyun #define WM8996_HPOUT2R_RMV_SHORT 0x0008 /* HPOUT2R_RMV_SHORT */ 1544*4882a593Smuzhiyun #define WM8996_HPOUT2R_RMV_SHORT_MASK 0x0008 /* HPOUT2R_RMV_SHORT */ 1545*4882a593Smuzhiyun #define WM8996_HPOUT2R_RMV_SHORT_SHIFT 3 /* HPOUT2R_RMV_SHORT */ 1546*4882a593Smuzhiyun #define WM8996_HPOUT2R_RMV_SHORT_WIDTH 1 /* HPOUT2R_RMV_SHORT */ 1547*4882a593Smuzhiyun #define WM8996_HPOUT2R_OUTP 0x0004 /* HPOUT2R_OUTP */ 1548*4882a593Smuzhiyun #define WM8996_HPOUT2R_OUTP_MASK 0x0004 /* HPOUT2R_OUTP */ 1549*4882a593Smuzhiyun #define WM8996_HPOUT2R_OUTP_SHIFT 2 /* HPOUT2R_OUTP */ 1550*4882a593Smuzhiyun #define WM8996_HPOUT2R_OUTP_WIDTH 1 /* HPOUT2R_OUTP */ 1551*4882a593Smuzhiyun #define WM8996_HPOUT2R_DLY 0x0002 /* HPOUT2R_DLY */ 1552*4882a593Smuzhiyun #define WM8996_HPOUT2R_DLY_MASK 0x0002 /* HPOUT2R_DLY */ 1553*4882a593Smuzhiyun #define WM8996_HPOUT2R_DLY_SHIFT 1 /* HPOUT2R_DLY */ 1554*4882a593Smuzhiyun #define WM8996_HPOUT2R_DLY_WIDTH 1 /* HPOUT2R_DLY */ 1555*4882a593Smuzhiyun 1556*4882a593Smuzhiyun /* 1557*4882a593Smuzhiyun * R256 (0x100) - Chip Revision 1558*4882a593Smuzhiyun */ 1559*4882a593Smuzhiyun #define WM8996_CHIP_REV_MASK 0x000F /* CHIP_REV - [3:0] */ 1560*4882a593Smuzhiyun #define WM8996_CHIP_REV_SHIFT 0 /* CHIP_REV - [3:0] */ 1561*4882a593Smuzhiyun #define WM8996_CHIP_REV_WIDTH 4 /* CHIP_REV - [3:0] */ 1562*4882a593Smuzhiyun 1563*4882a593Smuzhiyun /* 1564*4882a593Smuzhiyun * R257 (0x101) - Control Interface (1) 1565*4882a593Smuzhiyun */ 1566*4882a593Smuzhiyun #define WM8996_REG_SYNC 0x8000 /* REG_SYNC */ 1567*4882a593Smuzhiyun #define WM8996_REG_SYNC_MASK 0x8000 /* REG_SYNC */ 1568*4882a593Smuzhiyun #define WM8996_REG_SYNC_SHIFT 15 /* REG_SYNC */ 1569*4882a593Smuzhiyun #define WM8996_REG_SYNC_WIDTH 1 /* REG_SYNC */ 1570*4882a593Smuzhiyun #define WM8996_AUTO_INC 0x0004 /* AUTO_INC */ 1571*4882a593Smuzhiyun #define WM8996_AUTO_INC_MASK 0x0004 /* AUTO_INC */ 1572*4882a593Smuzhiyun #define WM8996_AUTO_INC_SHIFT 2 /* AUTO_INC */ 1573*4882a593Smuzhiyun #define WM8996_AUTO_INC_WIDTH 1 /* AUTO_INC */ 1574*4882a593Smuzhiyun 1575*4882a593Smuzhiyun /* 1576*4882a593Smuzhiyun * R272 (0x110) - Write Sequencer Ctrl (1) 1577*4882a593Smuzhiyun */ 1578*4882a593Smuzhiyun #define WM8996_WSEQ_ENA 0x8000 /* WSEQ_ENA */ 1579*4882a593Smuzhiyun #define WM8996_WSEQ_ENA_MASK 0x8000 /* WSEQ_ENA */ 1580*4882a593Smuzhiyun #define WM8996_WSEQ_ENA_SHIFT 15 /* WSEQ_ENA */ 1581*4882a593Smuzhiyun #define WM8996_WSEQ_ENA_WIDTH 1 /* WSEQ_ENA */ 1582*4882a593Smuzhiyun #define WM8996_WSEQ_ABORT 0x0200 /* WSEQ_ABORT */ 1583*4882a593Smuzhiyun #define WM8996_WSEQ_ABORT_MASK 0x0200 /* WSEQ_ABORT */ 1584*4882a593Smuzhiyun #define WM8996_WSEQ_ABORT_SHIFT 9 /* WSEQ_ABORT */ 1585*4882a593Smuzhiyun #define WM8996_WSEQ_ABORT_WIDTH 1 /* WSEQ_ABORT */ 1586*4882a593Smuzhiyun #define WM8996_WSEQ_START 0x0100 /* WSEQ_START */ 1587*4882a593Smuzhiyun #define WM8996_WSEQ_START_MASK 0x0100 /* WSEQ_START */ 1588*4882a593Smuzhiyun #define WM8996_WSEQ_START_SHIFT 8 /* WSEQ_START */ 1589*4882a593Smuzhiyun #define WM8996_WSEQ_START_WIDTH 1 /* WSEQ_START */ 1590*4882a593Smuzhiyun #define WM8996_WSEQ_START_INDEX_MASK 0x007F /* WSEQ_START_INDEX - [6:0] */ 1591*4882a593Smuzhiyun #define WM8996_WSEQ_START_INDEX_SHIFT 0 /* WSEQ_START_INDEX - [6:0] */ 1592*4882a593Smuzhiyun #define WM8996_WSEQ_START_INDEX_WIDTH 7 /* WSEQ_START_INDEX - [6:0] */ 1593*4882a593Smuzhiyun 1594*4882a593Smuzhiyun /* 1595*4882a593Smuzhiyun * R273 (0x111) - Write Sequencer Ctrl (2) 1596*4882a593Smuzhiyun */ 1597*4882a593Smuzhiyun #define WM8996_WSEQ_BUSY 0x0100 /* WSEQ_BUSY */ 1598*4882a593Smuzhiyun #define WM8996_WSEQ_BUSY_MASK 0x0100 /* WSEQ_BUSY */ 1599*4882a593Smuzhiyun #define WM8996_WSEQ_BUSY_SHIFT 8 /* WSEQ_BUSY */ 1600*4882a593Smuzhiyun #define WM8996_WSEQ_BUSY_WIDTH 1 /* WSEQ_BUSY */ 1601*4882a593Smuzhiyun #define WM8996_WSEQ_CURRENT_INDEX_MASK 0x007F /* WSEQ_CURRENT_INDEX - [6:0] */ 1602*4882a593Smuzhiyun #define WM8996_WSEQ_CURRENT_INDEX_SHIFT 0 /* WSEQ_CURRENT_INDEX - [6:0] */ 1603*4882a593Smuzhiyun #define WM8996_WSEQ_CURRENT_INDEX_WIDTH 7 /* WSEQ_CURRENT_INDEX - [6:0] */ 1604*4882a593Smuzhiyun 1605*4882a593Smuzhiyun /* 1606*4882a593Smuzhiyun * R512 (0x200) - AIF Clocking (1) 1607*4882a593Smuzhiyun */ 1608*4882a593Smuzhiyun #define WM8996_SYSCLK_SRC_MASK 0x0018 /* SYSCLK_SRC - [4:3] */ 1609*4882a593Smuzhiyun #define WM8996_SYSCLK_SRC_SHIFT 3 /* SYSCLK_SRC - [4:3] */ 1610*4882a593Smuzhiyun #define WM8996_SYSCLK_SRC_WIDTH 2 /* SYSCLK_SRC - [4:3] */ 1611*4882a593Smuzhiyun #define WM8996_SYSCLK_INV 0x0004 /* SYSCLK_INV */ 1612*4882a593Smuzhiyun #define WM8996_SYSCLK_INV_MASK 0x0004 /* SYSCLK_INV */ 1613*4882a593Smuzhiyun #define WM8996_SYSCLK_INV_SHIFT 2 /* SYSCLK_INV */ 1614*4882a593Smuzhiyun #define WM8996_SYSCLK_INV_WIDTH 1 /* SYSCLK_INV */ 1615*4882a593Smuzhiyun #define WM8996_SYSCLK_DIV 0x0002 /* SYSCLK_DIV */ 1616*4882a593Smuzhiyun #define WM8996_SYSCLK_DIV_MASK 0x0002 /* SYSCLK_DIV */ 1617*4882a593Smuzhiyun #define WM8996_SYSCLK_DIV_SHIFT 1 /* SYSCLK_DIV */ 1618*4882a593Smuzhiyun #define WM8996_SYSCLK_DIV_WIDTH 1 /* SYSCLK_DIV */ 1619*4882a593Smuzhiyun #define WM8996_SYSCLK_ENA 0x0001 /* SYSCLK_ENA */ 1620*4882a593Smuzhiyun #define WM8996_SYSCLK_ENA_MASK 0x0001 /* SYSCLK_ENA */ 1621*4882a593Smuzhiyun #define WM8996_SYSCLK_ENA_SHIFT 0 /* SYSCLK_ENA */ 1622*4882a593Smuzhiyun #define WM8996_SYSCLK_ENA_WIDTH 1 /* SYSCLK_ENA */ 1623*4882a593Smuzhiyun 1624*4882a593Smuzhiyun /* 1625*4882a593Smuzhiyun * R513 (0x201) - AIF Clocking (2) 1626*4882a593Smuzhiyun */ 1627*4882a593Smuzhiyun #define WM8996_DSP2_DIV_MASK 0x0018 /* DSP2_DIV - [4:3] */ 1628*4882a593Smuzhiyun #define WM8996_DSP2_DIV_SHIFT 3 /* DSP2_DIV - [4:3] */ 1629*4882a593Smuzhiyun #define WM8996_DSP2_DIV_WIDTH 2 /* DSP2_DIV - [4:3] */ 1630*4882a593Smuzhiyun #define WM8996_DSP1_DIV_MASK 0x0003 /* DSP1_DIV - [1:0] */ 1631*4882a593Smuzhiyun #define WM8996_DSP1_DIV_SHIFT 0 /* DSP1_DIV - [1:0] */ 1632*4882a593Smuzhiyun #define WM8996_DSP1_DIV_WIDTH 2 /* DSP1_DIV - [1:0] */ 1633*4882a593Smuzhiyun 1634*4882a593Smuzhiyun /* 1635*4882a593Smuzhiyun * R520 (0x208) - Clocking (1) 1636*4882a593Smuzhiyun */ 1637*4882a593Smuzhiyun #define WM8996_LFCLK_ENA 0x0020 /* LFCLK_ENA */ 1638*4882a593Smuzhiyun #define WM8996_LFCLK_ENA_MASK 0x0020 /* LFCLK_ENA */ 1639*4882a593Smuzhiyun #define WM8996_LFCLK_ENA_SHIFT 5 /* LFCLK_ENA */ 1640*4882a593Smuzhiyun #define WM8996_LFCLK_ENA_WIDTH 1 /* LFCLK_ENA */ 1641*4882a593Smuzhiyun #define WM8996_TOCLK_ENA 0x0010 /* TOCLK_ENA */ 1642*4882a593Smuzhiyun #define WM8996_TOCLK_ENA_MASK 0x0010 /* TOCLK_ENA */ 1643*4882a593Smuzhiyun #define WM8996_TOCLK_ENA_SHIFT 4 /* TOCLK_ENA */ 1644*4882a593Smuzhiyun #define WM8996_TOCLK_ENA_WIDTH 1 /* TOCLK_ENA */ 1645*4882a593Smuzhiyun #define WM8996_AIFCLK_ENA 0x0004 /* AIFCLK_ENA */ 1646*4882a593Smuzhiyun #define WM8996_AIFCLK_ENA_MASK 0x0004 /* AIFCLK_ENA */ 1647*4882a593Smuzhiyun #define WM8996_AIFCLK_ENA_SHIFT 2 /* AIFCLK_ENA */ 1648*4882a593Smuzhiyun #define WM8996_AIFCLK_ENA_WIDTH 1 /* AIFCLK_ENA */ 1649*4882a593Smuzhiyun #define WM8996_SYSDSPCLK_ENA 0x0002 /* SYSDSPCLK_ENA */ 1650*4882a593Smuzhiyun #define WM8996_SYSDSPCLK_ENA_MASK 0x0002 /* SYSDSPCLK_ENA */ 1651*4882a593Smuzhiyun #define WM8996_SYSDSPCLK_ENA_SHIFT 1 /* SYSDSPCLK_ENA */ 1652*4882a593Smuzhiyun #define WM8996_SYSDSPCLK_ENA_WIDTH 1 /* SYSDSPCLK_ENA */ 1653*4882a593Smuzhiyun 1654*4882a593Smuzhiyun /* 1655*4882a593Smuzhiyun * R521 (0x209) - Clocking (2) 1656*4882a593Smuzhiyun */ 1657*4882a593Smuzhiyun #define WM8996_TOCLK_DIV_MASK 0x0700 /* TOCLK_DIV - [10:8] */ 1658*4882a593Smuzhiyun #define WM8996_TOCLK_DIV_SHIFT 8 /* TOCLK_DIV - [10:8] */ 1659*4882a593Smuzhiyun #define WM8996_TOCLK_DIV_WIDTH 3 /* TOCLK_DIV - [10:8] */ 1660*4882a593Smuzhiyun #define WM8996_DBCLK_DIV_MASK 0x00F0 /* DBCLK_DIV - [7:4] */ 1661*4882a593Smuzhiyun #define WM8996_DBCLK_DIV_SHIFT 4 /* DBCLK_DIV - [7:4] */ 1662*4882a593Smuzhiyun #define WM8996_DBCLK_DIV_WIDTH 4 /* DBCLK_DIV - [7:4] */ 1663*4882a593Smuzhiyun #define WM8996_OPCLK_DIV_MASK 0x0007 /* OPCLK_DIV - [2:0] */ 1664*4882a593Smuzhiyun #define WM8996_OPCLK_DIV_SHIFT 0 /* OPCLK_DIV - [2:0] */ 1665*4882a593Smuzhiyun #define WM8996_OPCLK_DIV_WIDTH 3 /* OPCLK_DIV - [2:0] */ 1666*4882a593Smuzhiyun 1667*4882a593Smuzhiyun /* 1668*4882a593Smuzhiyun * R528 (0x210) - AIF Rate 1669*4882a593Smuzhiyun */ 1670*4882a593Smuzhiyun #define WM8996_SYSCLK_RATE 0x0001 /* SYSCLK_RATE */ 1671*4882a593Smuzhiyun #define WM8996_SYSCLK_RATE_MASK 0x0001 /* SYSCLK_RATE */ 1672*4882a593Smuzhiyun #define WM8996_SYSCLK_RATE_SHIFT 0 /* SYSCLK_RATE */ 1673*4882a593Smuzhiyun #define WM8996_SYSCLK_RATE_WIDTH 1 /* SYSCLK_RATE */ 1674*4882a593Smuzhiyun 1675*4882a593Smuzhiyun /* 1676*4882a593Smuzhiyun * R544 (0x220) - FLL Control (1) 1677*4882a593Smuzhiyun */ 1678*4882a593Smuzhiyun #define WM8996_FLL_OSC_ENA 0x0002 /* FLL_OSC_ENA */ 1679*4882a593Smuzhiyun #define WM8996_FLL_OSC_ENA_MASK 0x0002 /* FLL_OSC_ENA */ 1680*4882a593Smuzhiyun #define WM8996_FLL_OSC_ENA_SHIFT 1 /* FLL_OSC_ENA */ 1681*4882a593Smuzhiyun #define WM8996_FLL_OSC_ENA_WIDTH 1 /* FLL_OSC_ENA */ 1682*4882a593Smuzhiyun #define WM8996_FLL_ENA 0x0001 /* FLL_ENA */ 1683*4882a593Smuzhiyun #define WM8996_FLL_ENA_MASK 0x0001 /* FLL_ENA */ 1684*4882a593Smuzhiyun #define WM8996_FLL_ENA_SHIFT 0 /* FLL_ENA */ 1685*4882a593Smuzhiyun #define WM8996_FLL_ENA_WIDTH 1 /* FLL_ENA */ 1686*4882a593Smuzhiyun 1687*4882a593Smuzhiyun /* 1688*4882a593Smuzhiyun * R545 (0x221) - FLL Control (2) 1689*4882a593Smuzhiyun */ 1690*4882a593Smuzhiyun #define WM8996_FLL_OUTDIV_MASK 0x3F00 /* FLL_OUTDIV - [13:8] */ 1691*4882a593Smuzhiyun #define WM8996_FLL_OUTDIV_SHIFT 8 /* FLL_OUTDIV - [13:8] */ 1692*4882a593Smuzhiyun #define WM8996_FLL_OUTDIV_WIDTH 6 /* FLL_OUTDIV - [13:8] */ 1693*4882a593Smuzhiyun #define WM8996_FLL_FRATIO_MASK 0x0007 /* FLL_FRATIO - [2:0] */ 1694*4882a593Smuzhiyun #define WM8996_FLL_FRATIO_SHIFT 0 /* FLL_FRATIO - [2:0] */ 1695*4882a593Smuzhiyun #define WM8996_FLL_FRATIO_WIDTH 3 /* FLL_FRATIO - [2:0] */ 1696*4882a593Smuzhiyun 1697*4882a593Smuzhiyun /* 1698*4882a593Smuzhiyun * R546 (0x222) - FLL Control (3) 1699*4882a593Smuzhiyun */ 1700*4882a593Smuzhiyun #define WM8996_FLL_THETA_MASK 0xFFFF /* FLL_THETA - [15:0] */ 1701*4882a593Smuzhiyun #define WM8996_FLL_THETA_SHIFT 0 /* FLL_THETA - [15:0] */ 1702*4882a593Smuzhiyun #define WM8996_FLL_THETA_WIDTH 16 /* FLL_THETA - [15:0] */ 1703*4882a593Smuzhiyun 1704*4882a593Smuzhiyun /* 1705*4882a593Smuzhiyun * R547 (0x223) - FLL Control (4) 1706*4882a593Smuzhiyun */ 1707*4882a593Smuzhiyun #define WM8996_FLL_N_MASK 0x7FE0 /* FLL_N - [14:5] */ 1708*4882a593Smuzhiyun #define WM8996_FLL_N_SHIFT 5 /* FLL_N - [14:5] */ 1709*4882a593Smuzhiyun #define WM8996_FLL_N_WIDTH 10 /* FLL_N - [14:5] */ 1710*4882a593Smuzhiyun #define WM8996_FLL_LOOP_GAIN_MASK 0x000F /* FLL_LOOP_GAIN - [3:0] */ 1711*4882a593Smuzhiyun #define WM8996_FLL_LOOP_GAIN_SHIFT 0 /* FLL_LOOP_GAIN - [3:0] */ 1712*4882a593Smuzhiyun #define WM8996_FLL_LOOP_GAIN_WIDTH 4 /* FLL_LOOP_GAIN - [3:0] */ 1713*4882a593Smuzhiyun 1714*4882a593Smuzhiyun /* 1715*4882a593Smuzhiyun * R548 (0x224) - FLL Control (5) 1716*4882a593Smuzhiyun */ 1717*4882a593Smuzhiyun #define WM8996_FLL_FRC_NCO_VAL_MASK 0x1F80 /* FLL_FRC_NCO_VAL - [12:7] */ 1718*4882a593Smuzhiyun #define WM8996_FLL_FRC_NCO_VAL_SHIFT 7 /* FLL_FRC_NCO_VAL - [12:7] */ 1719*4882a593Smuzhiyun #define WM8996_FLL_FRC_NCO_VAL_WIDTH 6 /* FLL_FRC_NCO_VAL - [12:7] */ 1720*4882a593Smuzhiyun #define WM8996_FLL_FRC_NCO 0x0040 /* FLL_FRC_NCO */ 1721*4882a593Smuzhiyun #define WM8996_FLL_FRC_NCO_MASK 0x0040 /* FLL_FRC_NCO */ 1722*4882a593Smuzhiyun #define WM8996_FLL_FRC_NCO_SHIFT 6 /* FLL_FRC_NCO */ 1723*4882a593Smuzhiyun #define WM8996_FLL_FRC_NCO_WIDTH 1 /* FLL_FRC_NCO */ 1724*4882a593Smuzhiyun #define WM8996_FLL_REFCLK_DIV_MASK 0x0018 /* FLL_REFCLK_DIV - [4:3] */ 1725*4882a593Smuzhiyun #define WM8996_FLL_REFCLK_DIV_SHIFT 3 /* FLL_REFCLK_DIV - [4:3] */ 1726*4882a593Smuzhiyun #define WM8996_FLL_REFCLK_DIV_WIDTH 2 /* FLL_REFCLK_DIV - [4:3] */ 1727*4882a593Smuzhiyun #define WM8996_FLL_REF_FREQ 0x0004 /* FLL_REF_FREQ */ 1728*4882a593Smuzhiyun #define WM8996_FLL_REF_FREQ_MASK 0x0004 /* FLL_REF_FREQ */ 1729*4882a593Smuzhiyun #define WM8996_FLL_REF_FREQ_SHIFT 2 /* FLL_REF_FREQ */ 1730*4882a593Smuzhiyun #define WM8996_FLL_REF_FREQ_WIDTH 1 /* FLL_REF_FREQ */ 1731*4882a593Smuzhiyun #define WM8996_FLL_REFCLK_SRC_MASK 0x0003 /* FLL_REFCLK_SRC - [1:0] */ 1732*4882a593Smuzhiyun #define WM8996_FLL_REFCLK_SRC_SHIFT 0 /* FLL_REFCLK_SRC - [1:0] */ 1733*4882a593Smuzhiyun #define WM8996_FLL_REFCLK_SRC_WIDTH 2 /* FLL_REFCLK_SRC - [1:0] */ 1734*4882a593Smuzhiyun 1735*4882a593Smuzhiyun /* 1736*4882a593Smuzhiyun * R549 (0x225) - FLL Control (6) 1737*4882a593Smuzhiyun */ 1738*4882a593Smuzhiyun #define WM8996_FLL_REFCLK_SRC_STS_MASK 0x000C /* FLL_REFCLK_SRC_STS - [3:2] */ 1739*4882a593Smuzhiyun #define WM8996_FLL_REFCLK_SRC_STS_SHIFT 2 /* FLL_REFCLK_SRC_STS - [3:2] */ 1740*4882a593Smuzhiyun #define WM8996_FLL_REFCLK_SRC_STS_WIDTH 2 /* FLL_REFCLK_SRC_STS - [3:2] */ 1741*4882a593Smuzhiyun #define WM8996_FLL_SWITCH_CLK 0x0001 /* FLL_SWITCH_CLK */ 1742*4882a593Smuzhiyun #define WM8996_FLL_SWITCH_CLK_MASK 0x0001 /* FLL_SWITCH_CLK */ 1743*4882a593Smuzhiyun #define WM8996_FLL_SWITCH_CLK_SHIFT 0 /* FLL_SWITCH_CLK */ 1744*4882a593Smuzhiyun #define WM8996_FLL_SWITCH_CLK_WIDTH 1 /* FLL_SWITCH_CLK */ 1745*4882a593Smuzhiyun 1746*4882a593Smuzhiyun /* 1747*4882a593Smuzhiyun * R550 (0x226) - FLL EFS 1 1748*4882a593Smuzhiyun */ 1749*4882a593Smuzhiyun #define WM8996_FLL_LAMBDA_MASK 0xFFFF /* FLL_LAMBDA - [15:0] */ 1750*4882a593Smuzhiyun #define WM8996_FLL_LAMBDA_SHIFT 0 /* FLL_LAMBDA - [15:0] */ 1751*4882a593Smuzhiyun #define WM8996_FLL_LAMBDA_WIDTH 16 /* FLL_LAMBDA - [15:0] */ 1752*4882a593Smuzhiyun 1753*4882a593Smuzhiyun /* 1754*4882a593Smuzhiyun * R551 (0x227) - FLL EFS 2 1755*4882a593Smuzhiyun */ 1756*4882a593Smuzhiyun #define WM8996_FLL_LFSR_SEL_MASK 0x0006 /* FLL_LFSR_SEL - [2:1] */ 1757*4882a593Smuzhiyun #define WM8996_FLL_LFSR_SEL_SHIFT 1 /* FLL_LFSR_SEL - [2:1] */ 1758*4882a593Smuzhiyun #define WM8996_FLL_LFSR_SEL_WIDTH 2 /* FLL_LFSR_SEL - [2:1] */ 1759*4882a593Smuzhiyun #define WM8996_FLL_EFS_ENA 0x0001 /* FLL_EFS_ENA */ 1760*4882a593Smuzhiyun #define WM8996_FLL_EFS_ENA_MASK 0x0001 /* FLL_EFS_ENA */ 1761*4882a593Smuzhiyun #define WM8996_FLL_EFS_ENA_SHIFT 0 /* FLL_EFS_ENA */ 1762*4882a593Smuzhiyun #define WM8996_FLL_EFS_ENA_WIDTH 1 /* FLL_EFS_ENA */ 1763*4882a593Smuzhiyun 1764*4882a593Smuzhiyun /* 1765*4882a593Smuzhiyun * R768 (0x300) - AIF1 Control 1766*4882a593Smuzhiyun */ 1767*4882a593Smuzhiyun #define WM8996_AIF1_TRI 0x0004 /* AIF1_TRI */ 1768*4882a593Smuzhiyun #define WM8996_AIF1_TRI_MASK 0x0004 /* AIF1_TRI */ 1769*4882a593Smuzhiyun #define WM8996_AIF1_TRI_SHIFT 2 /* AIF1_TRI */ 1770*4882a593Smuzhiyun #define WM8996_AIF1_TRI_WIDTH 1 /* AIF1_TRI */ 1771*4882a593Smuzhiyun #define WM8996_AIF1_FMT_MASK 0x0003 /* AIF1_FMT - [1:0] */ 1772*4882a593Smuzhiyun #define WM8996_AIF1_FMT_SHIFT 0 /* AIF1_FMT - [1:0] */ 1773*4882a593Smuzhiyun #define WM8996_AIF1_FMT_WIDTH 2 /* AIF1_FMT - [1:0] */ 1774*4882a593Smuzhiyun 1775*4882a593Smuzhiyun /* 1776*4882a593Smuzhiyun * R769 (0x301) - AIF1 BCLK 1777*4882a593Smuzhiyun */ 1778*4882a593Smuzhiyun #define WM8996_AIF1_BCLK_INV 0x0400 /* AIF1_BCLK_INV */ 1779*4882a593Smuzhiyun #define WM8996_AIF1_BCLK_INV_MASK 0x0400 /* AIF1_BCLK_INV */ 1780*4882a593Smuzhiyun #define WM8996_AIF1_BCLK_INV_SHIFT 10 /* AIF1_BCLK_INV */ 1781*4882a593Smuzhiyun #define WM8996_AIF1_BCLK_INV_WIDTH 1 /* AIF1_BCLK_INV */ 1782*4882a593Smuzhiyun #define WM8996_AIF1_BCLK_FRC 0x0200 /* AIF1_BCLK_FRC */ 1783*4882a593Smuzhiyun #define WM8996_AIF1_BCLK_FRC_MASK 0x0200 /* AIF1_BCLK_FRC */ 1784*4882a593Smuzhiyun #define WM8996_AIF1_BCLK_FRC_SHIFT 9 /* AIF1_BCLK_FRC */ 1785*4882a593Smuzhiyun #define WM8996_AIF1_BCLK_FRC_WIDTH 1 /* AIF1_BCLK_FRC */ 1786*4882a593Smuzhiyun #define WM8996_AIF1_BCLK_MSTR 0x0100 /* AIF1_BCLK_MSTR */ 1787*4882a593Smuzhiyun #define WM8996_AIF1_BCLK_MSTR_MASK 0x0100 /* AIF1_BCLK_MSTR */ 1788*4882a593Smuzhiyun #define WM8996_AIF1_BCLK_MSTR_SHIFT 8 /* AIF1_BCLK_MSTR */ 1789*4882a593Smuzhiyun #define WM8996_AIF1_BCLK_MSTR_WIDTH 1 /* AIF1_BCLK_MSTR */ 1790*4882a593Smuzhiyun #define WM8996_AIF1_BCLK_DIV_MASK 0x000F /* AIF1_BCLK_DIV - [3:0] */ 1791*4882a593Smuzhiyun #define WM8996_AIF1_BCLK_DIV_SHIFT 0 /* AIF1_BCLK_DIV - [3:0] */ 1792*4882a593Smuzhiyun #define WM8996_AIF1_BCLK_DIV_WIDTH 4 /* AIF1_BCLK_DIV - [3:0] */ 1793*4882a593Smuzhiyun 1794*4882a593Smuzhiyun /* 1795*4882a593Smuzhiyun * R770 (0x302) - AIF1 TX LRCLK(1) 1796*4882a593Smuzhiyun */ 1797*4882a593Smuzhiyun #define WM8996_AIF1TX_RATE_MASK 0x07FF /* AIF1TX_RATE - [10:0] */ 1798*4882a593Smuzhiyun #define WM8996_AIF1TX_RATE_SHIFT 0 /* AIF1TX_RATE - [10:0] */ 1799*4882a593Smuzhiyun #define WM8996_AIF1TX_RATE_WIDTH 11 /* AIF1TX_RATE - [10:0] */ 1800*4882a593Smuzhiyun 1801*4882a593Smuzhiyun /* 1802*4882a593Smuzhiyun * R771 (0x303) - AIF1 TX LRCLK(2) 1803*4882a593Smuzhiyun */ 1804*4882a593Smuzhiyun #define WM8996_AIF1TX_LRCLK_MODE 0x0008 /* AIF1TX_LRCLK_MODE */ 1805*4882a593Smuzhiyun #define WM8996_AIF1TX_LRCLK_MODE_MASK 0x0008 /* AIF1TX_LRCLK_MODE */ 1806*4882a593Smuzhiyun #define WM8996_AIF1TX_LRCLK_MODE_SHIFT 3 /* AIF1TX_LRCLK_MODE */ 1807*4882a593Smuzhiyun #define WM8996_AIF1TX_LRCLK_MODE_WIDTH 1 /* AIF1TX_LRCLK_MODE */ 1808*4882a593Smuzhiyun #define WM8996_AIF1TX_LRCLK_INV 0x0004 /* AIF1TX_LRCLK_INV */ 1809*4882a593Smuzhiyun #define WM8996_AIF1TX_LRCLK_INV_MASK 0x0004 /* AIF1TX_LRCLK_INV */ 1810*4882a593Smuzhiyun #define WM8996_AIF1TX_LRCLK_INV_SHIFT 2 /* AIF1TX_LRCLK_INV */ 1811*4882a593Smuzhiyun #define WM8996_AIF1TX_LRCLK_INV_WIDTH 1 /* AIF1TX_LRCLK_INV */ 1812*4882a593Smuzhiyun #define WM8996_AIF1TX_LRCLK_FRC 0x0002 /* AIF1TX_LRCLK_FRC */ 1813*4882a593Smuzhiyun #define WM8996_AIF1TX_LRCLK_FRC_MASK 0x0002 /* AIF1TX_LRCLK_FRC */ 1814*4882a593Smuzhiyun #define WM8996_AIF1TX_LRCLK_FRC_SHIFT 1 /* AIF1TX_LRCLK_FRC */ 1815*4882a593Smuzhiyun #define WM8996_AIF1TX_LRCLK_FRC_WIDTH 1 /* AIF1TX_LRCLK_FRC */ 1816*4882a593Smuzhiyun #define WM8996_AIF1TX_LRCLK_MSTR 0x0001 /* AIF1TX_LRCLK_MSTR */ 1817*4882a593Smuzhiyun #define WM8996_AIF1TX_LRCLK_MSTR_MASK 0x0001 /* AIF1TX_LRCLK_MSTR */ 1818*4882a593Smuzhiyun #define WM8996_AIF1TX_LRCLK_MSTR_SHIFT 0 /* AIF1TX_LRCLK_MSTR */ 1819*4882a593Smuzhiyun #define WM8996_AIF1TX_LRCLK_MSTR_WIDTH 1 /* AIF1TX_LRCLK_MSTR */ 1820*4882a593Smuzhiyun 1821*4882a593Smuzhiyun /* 1822*4882a593Smuzhiyun * R772 (0x304) - AIF1 RX LRCLK(1) 1823*4882a593Smuzhiyun */ 1824*4882a593Smuzhiyun #define WM8996_AIF1RX_RATE_MASK 0x07FF /* AIF1RX_RATE - [10:0] */ 1825*4882a593Smuzhiyun #define WM8996_AIF1RX_RATE_SHIFT 0 /* AIF1RX_RATE - [10:0] */ 1826*4882a593Smuzhiyun #define WM8996_AIF1RX_RATE_WIDTH 11 /* AIF1RX_RATE - [10:0] */ 1827*4882a593Smuzhiyun 1828*4882a593Smuzhiyun /* 1829*4882a593Smuzhiyun * R773 (0x305) - AIF1 RX LRCLK(2) 1830*4882a593Smuzhiyun */ 1831*4882a593Smuzhiyun #define WM8996_AIF1RX_LRCLK_INV 0x0004 /* AIF1RX_LRCLK_INV */ 1832*4882a593Smuzhiyun #define WM8996_AIF1RX_LRCLK_INV_MASK 0x0004 /* AIF1RX_LRCLK_INV */ 1833*4882a593Smuzhiyun #define WM8996_AIF1RX_LRCLK_INV_SHIFT 2 /* AIF1RX_LRCLK_INV */ 1834*4882a593Smuzhiyun #define WM8996_AIF1RX_LRCLK_INV_WIDTH 1 /* AIF1RX_LRCLK_INV */ 1835*4882a593Smuzhiyun #define WM8996_AIF1RX_LRCLK_FRC 0x0002 /* AIF1RX_LRCLK_FRC */ 1836*4882a593Smuzhiyun #define WM8996_AIF1RX_LRCLK_FRC_MASK 0x0002 /* AIF1RX_LRCLK_FRC */ 1837*4882a593Smuzhiyun #define WM8996_AIF1RX_LRCLK_FRC_SHIFT 1 /* AIF1RX_LRCLK_FRC */ 1838*4882a593Smuzhiyun #define WM8996_AIF1RX_LRCLK_FRC_WIDTH 1 /* AIF1RX_LRCLK_FRC */ 1839*4882a593Smuzhiyun #define WM8996_AIF1RX_LRCLK_MSTR 0x0001 /* AIF1RX_LRCLK_MSTR */ 1840*4882a593Smuzhiyun #define WM8996_AIF1RX_LRCLK_MSTR_MASK 0x0001 /* AIF1RX_LRCLK_MSTR */ 1841*4882a593Smuzhiyun #define WM8996_AIF1RX_LRCLK_MSTR_SHIFT 0 /* AIF1RX_LRCLK_MSTR */ 1842*4882a593Smuzhiyun #define WM8996_AIF1RX_LRCLK_MSTR_WIDTH 1 /* AIF1RX_LRCLK_MSTR */ 1843*4882a593Smuzhiyun 1844*4882a593Smuzhiyun /* 1845*4882a593Smuzhiyun * R774 (0x306) - AIF1TX Data Configuration (1) 1846*4882a593Smuzhiyun */ 1847*4882a593Smuzhiyun #define WM8996_AIF1TX_WL_MASK 0xFF00 /* AIF1TX_WL - [15:8] */ 1848*4882a593Smuzhiyun #define WM8996_AIF1TX_WL_SHIFT 8 /* AIF1TX_WL - [15:8] */ 1849*4882a593Smuzhiyun #define WM8996_AIF1TX_WL_WIDTH 8 /* AIF1TX_WL - [15:8] */ 1850*4882a593Smuzhiyun #define WM8996_AIF1TX_SLOT_LEN_MASK 0x00FF /* AIF1TX_SLOT_LEN - [7:0] */ 1851*4882a593Smuzhiyun #define WM8996_AIF1TX_SLOT_LEN_SHIFT 0 /* AIF1TX_SLOT_LEN - [7:0] */ 1852*4882a593Smuzhiyun #define WM8996_AIF1TX_SLOT_LEN_WIDTH 8 /* AIF1TX_SLOT_LEN - [7:0] */ 1853*4882a593Smuzhiyun 1854*4882a593Smuzhiyun /* 1855*4882a593Smuzhiyun * R775 (0x307) - AIF1TX Data Configuration (2) 1856*4882a593Smuzhiyun */ 1857*4882a593Smuzhiyun #define WM8996_AIF1TX_DAT_TRI 0x0001 /* AIF1TX_DAT_TRI */ 1858*4882a593Smuzhiyun #define WM8996_AIF1TX_DAT_TRI_MASK 0x0001 /* AIF1TX_DAT_TRI */ 1859*4882a593Smuzhiyun #define WM8996_AIF1TX_DAT_TRI_SHIFT 0 /* AIF1TX_DAT_TRI */ 1860*4882a593Smuzhiyun #define WM8996_AIF1TX_DAT_TRI_WIDTH 1 /* AIF1TX_DAT_TRI */ 1861*4882a593Smuzhiyun 1862*4882a593Smuzhiyun /* 1863*4882a593Smuzhiyun * R776 (0x308) - AIF1RX Data Configuration 1864*4882a593Smuzhiyun */ 1865*4882a593Smuzhiyun #define WM8996_AIF1RX_WL_MASK 0xFF00 /* AIF1RX_WL - [15:8] */ 1866*4882a593Smuzhiyun #define WM8996_AIF1RX_WL_SHIFT 8 /* AIF1RX_WL - [15:8] */ 1867*4882a593Smuzhiyun #define WM8996_AIF1RX_WL_WIDTH 8 /* AIF1RX_WL - [15:8] */ 1868*4882a593Smuzhiyun #define WM8996_AIF1RX_SLOT_LEN_MASK 0x00FF /* AIF1RX_SLOT_LEN - [7:0] */ 1869*4882a593Smuzhiyun #define WM8996_AIF1RX_SLOT_LEN_SHIFT 0 /* AIF1RX_SLOT_LEN - [7:0] */ 1870*4882a593Smuzhiyun #define WM8996_AIF1RX_SLOT_LEN_WIDTH 8 /* AIF1RX_SLOT_LEN - [7:0] */ 1871*4882a593Smuzhiyun 1872*4882a593Smuzhiyun /* 1873*4882a593Smuzhiyun * R777 (0x309) - AIF1TX Channel 0 Configuration 1874*4882a593Smuzhiyun */ 1875*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN0_DAT_INV 0x8000 /* AIF1TX_CHAN0_DAT_INV */ 1876*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN0_DAT_INV_MASK 0x8000 /* AIF1TX_CHAN0_DAT_INV */ 1877*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN0_DAT_INV_SHIFT 15 /* AIF1TX_CHAN0_DAT_INV */ 1878*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN0_DAT_INV_WIDTH 1 /* AIF1TX_CHAN0_DAT_INV */ 1879*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN0_SPACING_MASK 0x7E00 /* AIF1TX_CHAN0_SPACING - [14:9] */ 1880*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN0_SPACING_SHIFT 9 /* AIF1TX_CHAN0_SPACING - [14:9] */ 1881*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN0_SPACING_WIDTH 6 /* AIF1TX_CHAN0_SPACING - [14:9] */ 1882*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN0_SLOTS_MASK 0x01C0 /* AIF1TX_CHAN0_SLOTS - [8:6] */ 1883*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN0_SLOTS_SHIFT 6 /* AIF1TX_CHAN0_SLOTS - [8:6] */ 1884*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN0_SLOTS_WIDTH 3 /* AIF1TX_CHAN0_SLOTS - [8:6] */ 1885*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN0_START_SLOT_MASK 0x003F /* AIF1TX_CHAN0_START_SLOT - [5:0] */ 1886*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN0_START_SLOT_SHIFT 0 /* AIF1TX_CHAN0_START_SLOT - [5:0] */ 1887*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN0_START_SLOT_WIDTH 6 /* AIF1TX_CHAN0_START_SLOT - [5:0] */ 1888*4882a593Smuzhiyun 1889*4882a593Smuzhiyun /* 1890*4882a593Smuzhiyun * R778 (0x30A) - AIF1TX Channel 1 Configuration 1891*4882a593Smuzhiyun */ 1892*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN1_DAT_INV 0x8000 /* AIF1TX_CHAN1_DAT_INV */ 1893*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN1_DAT_INV_MASK 0x8000 /* AIF1TX_CHAN1_DAT_INV */ 1894*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN1_DAT_INV_SHIFT 15 /* AIF1TX_CHAN1_DAT_INV */ 1895*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN1_DAT_INV_WIDTH 1 /* AIF1TX_CHAN1_DAT_INV */ 1896*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN1_SPACING_MASK 0x7E00 /* AIF1TX_CHAN1_SPACING - [14:9] */ 1897*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN1_SPACING_SHIFT 9 /* AIF1TX_CHAN1_SPACING - [14:9] */ 1898*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN1_SPACING_WIDTH 6 /* AIF1TX_CHAN1_SPACING - [14:9] */ 1899*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN1_SLOTS_MASK 0x01C0 /* AIF1TX_CHAN1_SLOTS - [8:6] */ 1900*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN1_SLOTS_SHIFT 6 /* AIF1TX_CHAN1_SLOTS - [8:6] */ 1901*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN1_SLOTS_WIDTH 3 /* AIF1TX_CHAN1_SLOTS - [8:6] */ 1902*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN1_START_SLOT_MASK 0x003F /* AIF1TX_CHAN1_START_SLOT - [5:0] */ 1903*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN1_START_SLOT_SHIFT 0 /* AIF1TX_CHAN1_START_SLOT - [5:0] */ 1904*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN1_START_SLOT_WIDTH 6 /* AIF1TX_CHAN1_START_SLOT - [5:0] */ 1905*4882a593Smuzhiyun 1906*4882a593Smuzhiyun /* 1907*4882a593Smuzhiyun * R779 (0x30B) - AIF1TX Channel 2 Configuration 1908*4882a593Smuzhiyun */ 1909*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN2_DAT_INV 0x8000 /* AIF1TX_CHAN2_DAT_INV */ 1910*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN2_DAT_INV_MASK 0x8000 /* AIF1TX_CHAN2_DAT_INV */ 1911*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN2_DAT_INV_SHIFT 15 /* AIF1TX_CHAN2_DAT_INV */ 1912*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN2_DAT_INV_WIDTH 1 /* AIF1TX_CHAN2_DAT_INV */ 1913*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN2_SPACING_MASK 0x7E00 /* AIF1TX_CHAN2_SPACING - [14:9] */ 1914*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN2_SPACING_SHIFT 9 /* AIF1TX_CHAN2_SPACING - [14:9] */ 1915*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN2_SPACING_WIDTH 6 /* AIF1TX_CHAN2_SPACING - [14:9] */ 1916*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN2_SLOTS_MASK 0x01C0 /* AIF1TX_CHAN2_SLOTS - [8:6] */ 1917*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN2_SLOTS_SHIFT 6 /* AIF1TX_CHAN2_SLOTS - [8:6] */ 1918*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN2_SLOTS_WIDTH 3 /* AIF1TX_CHAN2_SLOTS - [8:6] */ 1919*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN2_START_SLOT_MASK 0x003F /* AIF1TX_CHAN2_START_SLOT - [5:0] */ 1920*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN2_START_SLOT_SHIFT 0 /* AIF1TX_CHAN2_START_SLOT - [5:0] */ 1921*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN2_START_SLOT_WIDTH 6 /* AIF1TX_CHAN2_START_SLOT - [5:0] */ 1922*4882a593Smuzhiyun 1923*4882a593Smuzhiyun /* 1924*4882a593Smuzhiyun * R780 (0x30C) - AIF1TX Channel 3 Configuration 1925*4882a593Smuzhiyun */ 1926*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN3_DAT_INV 0x8000 /* AIF1TX_CHAN3_DAT_INV */ 1927*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN3_DAT_INV_MASK 0x8000 /* AIF1TX_CHAN3_DAT_INV */ 1928*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN3_DAT_INV_SHIFT 15 /* AIF1TX_CHAN3_DAT_INV */ 1929*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN3_DAT_INV_WIDTH 1 /* AIF1TX_CHAN3_DAT_INV */ 1930*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN3_SPACING_MASK 0x7E00 /* AIF1TX_CHAN3_SPACING - [14:9] */ 1931*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN3_SPACING_SHIFT 9 /* AIF1TX_CHAN3_SPACING - [14:9] */ 1932*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN3_SPACING_WIDTH 6 /* AIF1TX_CHAN3_SPACING - [14:9] */ 1933*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN3_SLOTS_MASK 0x01C0 /* AIF1TX_CHAN3_SLOTS - [8:6] */ 1934*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN3_SLOTS_SHIFT 6 /* AIF1TX_CHAN3_SLOTS - [8:6] */ 1935*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN3_SLOTS_WIDTH 3 /* AIF1TX_CHAN3_SLOTS - [8:6] */ 1936*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN3_START_SLOT_MASK 0x003F /* AIF1TX_CHAN3_START_SLOT - [5:0] */ 1937*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN3_START_SLOT_SHIFT 0 /* AIF1TX_CHAN3_START_SLOT - [5:0] */ 1938*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN3_START_SLOT_WIDTH 6 /* AIF1TX_CHAN3_START_SLOT - [5:0] */ 1939*4882a593Smuzhiyun 1940*4882a593Smuzhiyun /* 1941*4882a593Smuzhiyun * R781 (0x30D) - AIF1TX Channel 4 Configuration 1942*4882a593Smuzhiyun */ 1943*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN4_DAT_INV 0x8000 /* AIF1TX_CHAN4_DAT_INV */ 1944*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN4_DAT_INV_MASK 0x8000 /* AIF1TX_CHAN4_DAT_INV */ 1945*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN4_DAT_INV_SHIFT 15 /* AIF1TX_CHAN4_DAT_INV */ 1946*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN4_DAT_INV_WIDTH 1 /* AIF1TX_CHAN4_DAT_INV */ 1947*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN4_SPACING_MASK 0x7E00 /* AIF1TX_CHAN4_SPACING - [14:9] */ 1948*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN4_SPACING_SHIFT 9 /* AIF1TX_CHAN4_SPACING - [14:9] */ 1949*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN4_SPACING_WIDTH 6 /* AIF1TX_CHAN4_SPACING - [14:9] */ 1950*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN4_SLOTS_MASK 0x01C0 /* AIF1TX_CHAN4_SLOTS - [8:6] */ 1951*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN4_SLOTS_SHIFT 6 /* AIF1TX_CHAN4_SLOTS - [8:6] */ 1952*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN4_SLOTS_WIDTH 3 /* AIF1TX_CHAN4_SLOTS - [8:6] */ 1953*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN4_START_SLOT_MASK 0x003F /* AIF1TX_CHAN4_START_SLOT - [5:0] */ 1954*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN4_START_SLOT_SHIFT 0 /* AIF1TX_CHAN4_START_SLOT - [5:0] */ 1955*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN4_START_SLOT_WIDTH 6 /* AIF1TX_CHAN4_START_SLOT - [5:0] */ 1956*4882a593Smuzhiyun 1957*4882a593Smuzhiyun /* 1958*4882a593Smuzhiyun * R782 (0x30E) - AIF1TX Channel 5 Configuration 1959*4882a593Smuzhiyun */ 1960*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN5_DAT_INV 0x8000 /* AIF1TX_CHAN5_DAT_INV */ 1961*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN5_DAT_INV_MASK 0x8000 /* AIF1TX_CHAN5_DAT_INV */ 1962*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN5_DAT_INV_SHIFT 15 /* AIF1TX_CHAN5_DAT_INV */ 1963*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN5_DAT_INV_WIDTH 1 /* AIF1TX_CHAN5_DAT_INV */ 1964*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN5_SPACING_MASK 0x7E00 /* AIF1TX_CHAN5_SPACING - [14:9] */ 1965*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN5_SPACING_SHIFT 9 /* AIF1TX_CHAN5_SPACING - [14:9] */ 1966*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN5_SPACING_WIDTH 6 /* AIF1TX_CHAN5_SPACING - [14:9] */ 1967*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN5_SLOTS_MASK 0x01C0 /* AIF1TX_CHAN5_SLOTS - [8:6] */ 1968*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN5_SLOTS_SHIFT 6 /* AIF1TX_CHAN5_SLOTS - [8:6] */ 1969*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN5_SLOTS_WIDTH 3 /* AIF1TX_CHAN5_SLOTS - [8:6] */ 1970*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN5_START_SLOT_MASK 0x003F /* AIF1TX_CHAN5_START_SLOT - [5:0] */ 1971*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN5_START_SLOT_SHIFT 0 /* AIF1TX_CHAN5_START_SLOT - [5:0] */ 1972*4882a593Smuzhiyun #define WM8996_AIF1TX_CHAN5_START_SLOT_WIDTH 6 /* AIF1TX_CHAN5_START_SLOT - [5:0] */ 1973*4882a593Smuzhiyun 1974*4882a593Smuzhiyun /* 1975*4882a593Smuzhiyun * R783 (0x30F) - AIF1RX Channel 0 Configuration 1976*4882a593Smuzhiyun */ 1977*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN0_DAT_INV 0x8000 /* AIF1RX_CHAN0_DAT_INV */ 1978*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN0_DAT_INV_MASK 0x8000 /* AIF1RX_CHAN0_DAT_INV */ 1979*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN0_DAT_INV_SHIFT 15 /* AIF1RX_CHAN0_DAT_INV */ 1980*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN0_DAT_INV_WIDTH 1 /* AIF1RX_CHAN0_DAT_INV */ 1981*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN0_SPACING_MASK 0x7E00 /* AIF1RX_CHAN0_SPACING - [14:9] */ 1982*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN0_SPACING_SHIFT 9 /* AIF1RX_CHAN0_SPACING - [14:9] */ 1983*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN0_SPACING_WIDTH 6 /* AIF1RX_CHAN0_SPACING - [14:9] */ 1984*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN0_SLOTS_MASK 0x01C0 /* AIF1RX_CHAN0_SLOTS - [8:6] */ 1985*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN0_SLOTS_SHIFT 6 /* AIF1RX_CHAN0_SLOTS - [8:6] */ 1986*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN0_SLOTS_WIDTH 3 /* AIF1RX_CHAN0_SLOTS - [8:6] */ 1987*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN0_START_SLOT_MASK 0x003F /* AIF1RX_CHAN0_START_SLOT - [5:0] */ 1988*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN0_START_SLOT_SHIFT 0 /* AIF1RX_CHAN0_START_SLOT - [5:0] */ 1989*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN0_START_SLOT_WIDTH 6 /* AIF1RX_CHAN0_START_SLOT - [5:0] */ 1990*4882a593Smuzhiyun 1991*4882a593Smuzhiyun /* 1992*4882a593Smuzhiyun * R784 (0x310) - AIF1RX Channel 1 Configuration 1993*4882a593Smuzhiyun */ 1994*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN1_DAT_INV 0x8000 /* AIF1RX_CHAN1_DAT_INV */ 1995*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN1_DAT_INV_MASK 0x8000 /* AIF1RX_CHAN1_DAT_INV */ 1996*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN1_DAT_INV_SHIFT 15 /* AIF1RX_CHAN1_DAT_INV */ 1997*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN1_DAT_INV_WIDTH 1 /* AIF1RX_CHAN1_DAT_INV */ 1998*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN1_SPACING_MASK 0x7E00 /* AIF1RX_CHAN1_SPACING - [14:9] */ 1999*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN1_SPACING_SHIFT 9 /* AIF1RX_CHAN1_SPACING - [14:9] */ 2000*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN1_SPACING_WIDTH 6 /* AIF1RX_CHAN1_SPACING - [14:9] */ 2001*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN1_SLOTS_MASK 0x01C0 /* AIF1RX_CHAN1_SLOTS - [8:6] */ 2002*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN1_SLOTS_SHIFT 6 /* AIF1RX_CHAN1_SLOTS - [8:6] */ 2003*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN1_SLOTS_WIDTH 3 /* AIF1RX_CHAN1_SLOTS - [8:6] */ 2004*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN1_START_SLOT_MASK 0x003F /* AIF1RX_CHAN1_START_SLOT - [5:0] */ 2005*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN1_START_SLOT_SHIFT 0 /* AIF1RX_CHAN1_START_SLOT - [5:0] */ 2006*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN1_START_SLOT_WIDTH 6 /* AIF1RX_CHAN1_START_SLOT - [5:0] */ 2007*4882a593Smuzhiyun 2008*4882a593Smuzhiyun /* 2009*4882a593Smuzhiyun * R785 (0x311) - AIF1RX Channel 2 Configuration 2010*4882a593Smuzhiyun */ 2011*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN2_DAT_INV 0x8000 /* AIF1RX_CHAN2_DAT_INV */ 2012*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN2_DAT_INV_MASK 0x8000 /* AIF1RX_CHAN2_DAT_INV */ 2013*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN2_DAT_INV_SHIFT 15 /* AIF1RX_CHAN2_DAT_INV */ 2014*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN2_DAT_INV_WIDTH 1 /* AIF1RX_CHAN2_DAT_INV */ 2015*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN2_SPACING_MASK 0x7E00 /* AIF1RX_CHAN2_SPACING - [14:9] */ 2016*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN2_SPACING_SHIFT 9 /* AIF1RX_CHAN2_SPACING - [14:9] */ 2017*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN2_SPACING_WIDTH 6 /* AIF1RX_CHAN2_SPACING - [14:9] */ 2018*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN2_SLOTS_MASK 0x01C0 /* AIF1RX_CHAN2_SLOTS - [8:6] */ 2019*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN2_SLOTS_SHIFT 6 /* AIF1RX_CHAN2_SLOTS - [8:6] */ 2020*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN2_SLOTS_WIDTH 3 /* AIF1RX_CHAN2_SLOTS - [8:6] */ 2021*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN2_START_SLOT_MASK 0x003F /* AIF1RX_CHAN2_START_SLOT - [5:0] */ 2022*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN2_START_SLOT_SHIFT 0 /* AIF1RX_CHAN2_START_SLOT - [5:0] */ 2023*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN2_START_SLOT_WIDTH 6 /* AIF1RX_CHAN2_START_SLOT - [5:0] */ 2024*4882a593Smuzhiyun 2025*4882a593Smuzhiyun /* 2026*4882a593Smuzhiyun * R786 (0x312) - AIF1RX Channel 3 Configuration 2027*4882a593Smuzhiyun */ 2028*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN3_DAT_INV 0x8000 /* AIF1RX_CHAN3_DAT_INV */ 2029*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN3_DAT_INV_MASK 0x8000 /* AIF1RX_CHAN3_DAT_INV */ 2030*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN3_DAT_INV_SHIFT 15 /* AIF1RX_CHAN3_DAT_INV */ 2031*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN3_DAT_INV_WIDTH 1 /* AIF1RX_CHAN3_DAT_INV */ 2032*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN3_SPACING_MASK 0x7E00 /* AIF1RX_CHAN3_SPACING - [14:9] */ 2033*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN3_SPACING_SHIFT 9 /* AIF1RX_CHAN3_SPACING - [14:9] */ 2034*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN3_SPACING_WIDTH 6 /* AIF1RX_CHAN3_SPACING - [14:9] */ 2035*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN3_SLOTS_MASK 0x01C0 /* AIF1RX_CHAN3_SLOTS - [8:6] */ 2036*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN3_SLOTS_SHIFT 6 /* AIF1RX_CHAN3_SLOTS - [8:6] */ 2037*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN3_SLOTS_WIDTH 3 /* AIF1RX_CHAN3_SLOTS - [8:6] */ 2038*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN3_START_SLOT_MASK 0x003F /* AIF1RX_CHAN3_START_SLOT - [5:0] */ 2039*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN3_START_SLOT_SHIFT 0 /* AIF1RX_CHAN3_START_SLOT - [5:0] */ 2040*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN3_START_SLOT_WIDTH 6 /* AIF1RX_CHAN3_START_SLOT - [5:0] */ 2041*4882a593Smuzhiyun 2042*4882a593Smuzhiyun /* 2043*4882a593Smuzhiyun * R787 (0x313) - AIF1RX Channel 4 Configuration 2044*4882a593Smuzhiyun */ 2045*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN4_DAT_INV 0x8000 /* AIF1RX_CHAN4_DAT_INV */ 2046*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN4_DAT_INV_MASK 0x8000 /* AIF1RX_CHAN4_DAT_INV */ 2047*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN4_DAT_INV_SHIFT 15 /* AIF1RX_CHAN4_DAT_INV */ 2048*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN4_DAT_INV_WIDTH 1 /* AIF1RX_CHAN4_DAT_INV */ 2049*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN4_SPACING_MASK 0x7E00 /* AIF1RX_CHAN4_SPACING - [14:9] */ 2050*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN4_SPACING_SHIFT 9 /* AIF1RX_CHAN4_SPACING - [14:9] */ 2051*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN4_SPACING_WIDTH 6 /* AIF1RX_CHAN4_SPACING - [14:9] */ 2052*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN4_SLOTS_MASK 0x01C0 /* AIF1RX_CHAN4_SLOTS - [8:6] */ 2053*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN4_SLOTS_SHIFT 6 /* AIF1RX_CHAN4_SLOTS - [8:6] */ 2054*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN4_SLOTS_WIDTH 3 /* AIF1RX_CHAN4_SLOTS - [8:6] */ 2055*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN4_START_SLOT_MASK 0x003F /* AIF1RX_CHAN4_START_SLOT - [5:0] */ 2056*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN4_START_SLOT_SHIFT 0 /* AIF1RX_CHAN4_START_SLOT - [5:0] */ 2057*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN4_START_SLOT_WIDTH 6 /* AIF1RX_CHAN4_START_SLOT - [5:0] */ 2058*4882a593Smuzhiyun 2059*4882a593Smuzhiyun /* 2060*4882a593Smuzhiyun * R788 (0x314) - AIF1RX Channel 5 Configuration 2061*4882a593Smuzhiyun */ 2062*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN5_DAT_INV 0x8000 /* AIF1RX_CHAN5_DAT_INV */ 2063*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN5_DAT_INV_MASK 0x8000 /* AIF1RX_CHAN5_DAT_INV */ 2064*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN5_DAT_INV_SHIFT 15 /* AIF1RX_CHAN5_DAT_INV */ 2065*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN5_DAT_INV_WIDTH 1 /* AIF1RX_CHAN5_DAT_INV */ 2066*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN5_SPACING_MASK 0x7E00 /* AIF1RX_CHAN5_SPACING - [14:9] */ 2067*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN5_SPACING_SHIFT 9 /* AIF1RX_CHAN5_SPACING - [14:9] */ 2068*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN5_SPACING_WIDTH 6 /* AIF1RX_CHAN5_SPACING - [14:9] */ 2069*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN5_SLOTS_MASK 0x01C0 /* AIF1RX_CHAN5_SLOTS - [8:6] */ 2070*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN5_SLOTS_SHIFT 6 /* AIF1RX_CHAN5_SLOTS - [8:6] */ 2071*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN5_SLOTS_WIDTH 3 /* AIF1RX_CHAN5_SLOTS - [8:6] */ 2072*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN5_START_SLOT_MASK 0x003F /* AIF1RX_CHAN5_START_SLOT - [5:0] */ 2073*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN5_START_SLOT_SHIFT 0 /* AIF1RX_CHAN5_START_SLOT - [5:0] */ 2074*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN5_START_SLOT_WIDTH 6 /* AIF1RX_CHAN5_START_SLOT - [5:0] */ 2075*4882a593Smuzhiyun 2076*4882a593Smuzhiyun /* 2077*4882a593Smuzhiyun * R789 (0x315) - AIF1RX Mono Configuration 2078*4882a593Smuzhiyun */ 2079*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN4_MONO_MODE 0x0004 /* AIF1RX_CHAN4_MONO_MODE */ 2080*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN4_MONO_MODE_MASK 0x0004 /* AIF1RX_CHAN4_MONO_MODE */ 2081*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN4_MONO_MODE_SHIFT 2 /* AIF1RX_CHAN4_MONO_MODE */ 2082*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN4_MONO_MODE_WIDTH 1 /* AIF1RX_CHAN4_MONO_MODE */ 2083*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN2_MONO_MODE 0x0002 /* AIF1RX_CHAN2_MONO_MODE */ 2084*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN2_MONO_MODE_MASK 0x0002 /* AIF1RX_CHAN2_MONO_MODE */ 2085*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN2_MONO_MODE_SHIFT 1 /* AIF1RX_CHAN2_MONO_MODE */ 2086*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN2_MONO_MODE_WIDTH 1 /* AIF1RX_CHAN2_MONO_MODE */ 2087*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN0_MONO_MODE 0x0001 /* AIF1RX_CHAN0_MONO_MODE */ 2088*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN0_MONO_MODE_MASK 0x0001 /* AIF1RX_CHAN0_MONO_MODE */ 2089*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN0_MONO_MODE_SHIFT 0 /* AIF1RX_CHAN0_MONO_MODE */ 2090*4882a593Smuzhiyun #define WM8996_AIF1RX_CHAN0_MONO_MODE_WIDTH 1 /* AIF1RX_CHAN0_MONO_MODE */ 2091*4882a593Smuzhiyun 2092*4882a593Smuzhiyun /* 2093*4882a593Smuzhiyun * R794 (0x31A) - AIF1TX Test 2094*4882a593Smuzhiyun */ 2095*4882a593Smuzhiyun #define WM8996_AIF1TX45_DITHER_ENA 0x0004 /* AIF1TX45_DITHER_ENA */ 2096*4882a593Smuzhiyun #define WM8996_AIF1TX45_DITHER_ENA_MASK 0x0004 /* AIF1TX45_DITHER_ENA */ 2097*4882a593Smuzhiyun #define WM8996_AIF1TX45_DITHER_ENA_SHIFT 2 /* AIF1TX45_DITHER_ENA */ 2098*4882a593Smuzhiyun #define WM8996_AIF1TX45_DITHER_ENA_WIDTH 1 /* AIF1TX45_DITHER_ENA */ 2099*4882a593Smuzhiyun #define WM8996_AIF1TX23_DITHER_ENA 0x0002 /* AIF1TX23_DITHER_ENA */ 2100*4882a593Smuzhiyun #define WM8996_AIF1TX23_DITHER_ENA_MASK 0x0002 /* AIF1TX23_DITHER_ENA */ 2101*4882a593Smuzhiyun #define WM8996_AIF1TX23_DITHER_ENA_SHIFT 1 /* AIF1TX23_DITHER_ENA */ 2102*4882a593Smuzhiyun #define WM8996_AIF1TX23_DITHER_ENA_WIDTH 1 /* AIF1TX23_DITHER_ENA */ 2103*4882a593Smuzhiyun #define WM8996_AIF1TX01_DITHER_ENA 0x0001 /* AIF1TX01_DITHER_ENA */ 2104*4882a593Smuzhiyun #define WM8996_AIF1TX01_DITHER_ENA_MASK 0x0001 /* AIF1TX01_DITHER_ENA */ 2105*4882a593Smuzhiyun #define WM8996_AIF1TX01_DITHER_ENA_SHIFT 0 /* AIF1TX01_DITHER_ENA */ 2106*4882a593Smuzhiyun #define WM8996_AIF1TX01_DITHER_ENA_WIDTH 1 /* AIF1TX01_DITHER_ENA */ 2107*4882a593Smuzhiyun 2108*4882a593Smuzhiyun /* 2109*4882a593Smuzhiyun * R800 (0x320) - AIF2 Control 2110*4882a593Smuzhiyun */ 2111*4882a593Smuzhiyun #define WM8996_AIF2_TRI 0x0004 /* AIF2_TRI */ 2112*4882a593Smuzhiyun #define WM8996_AIF2_TRI_MASK 0x0004 /* AIF2_TRI */ 2113*4882a593Smuzhiyun #define WM8996_AIF2_TRI_SHIFT 2 /* AIF2_TRI */ 2114*4882a593Smuzhiyun #define WM8996_AIF2_TRI_WIDTH 1 /* AIF2_TRI */ 2115*4882a593Smuzhiyun #define WM8996_AIF2_FMT_MASK 0x0003 /* AIF2_FMT - [1:0] */ 2116*4882a593Smuzhiyun #define WM8996_AIF2_FMT_SHIFT 0 /* AIF2_FMT - [1:0] */ 2117*4882a593Smuzhiyun #define WM8996_AIF2_FMT_WIDTH 2 /* AIF2_FMT - [1:0] */ 2118*4882a593Smuzhiyun 2119*4882a593Smuzhiyun /* 2120*4882a593Smuzhiyun * R801 (0x321) - AIF2 BCLK 2121*4882a593Smuzhiyun */ 2122*4882a593Smuzhiyun #define WM8996_AIF2_BCLK_INV 0x0400 /* AIF2_BCLK_INV */ 2123*4882a593Smuzhiyun #define WM8996_AIF2_BCLK_INV_MASK 0x0400 /* AIF2_BCLK_INV */ 2124*4882a593Smuzhiyun #define WM8996_AIF2_BCLK_INV_SHIFT 10 /* AIF2_BCLK_INV */ 2125*4882a593Smuzhiyun #define WM8996_AIF2_BCLK_INV_WIDTH 1 /* AIF2_BCLK_INV */ 2126*4882a593Smuzhiyun #define WM8996_AIF2_BCLK_FRC 0x0200 /* AIF2_BCLK_FRC */ 2127*4882a593Smuzhiyun #define WM8996_AIF2_BCLK_FRC_MASK 0x0200 /* AIF2_BCLK_FRC */ 2128*4882a593Smuzhiyun #define WM8996_AIF2_BCLK_FRC_SHIFT 9 /* AIF2_BCLK_FRC */ 2129*4882a593Smuzhiyun #define WM8996_AIF2_BCLK_FRC_WIDTH 1 /* AIF2_BCLK_FRC */ 2130*4882a593Smuzhiyun #define WM8996_AIF2_BCLK_MSTR 0x0100 /* AIF2_BCLK_MSTR */ 2131*4882a593Smuzhiyun #define WM8996_AIF2_BCLK_MSTR_MASK 0x0100 /* AIF2_BCLK_MSTR */ 2132*4882a593Smuzhiyun #define WM8996_AIF2_BCLK_MSTR_SHIFT 8 /* AIF2_BCLK_MSTR */ 2133*4882a593Smuzhiyun #define WM8996_AIF2_BCLK_MSTR_WIDTH 1 /* AIF2_BCLK_MSTR */ 2134*4882a593Smuzhiyun #define WM8996_AIF2_BCLK_DIV_MASK 0x000F /* AIF2_BCLK_DIV - [3:0] */ 2135*4882a593Smuzhiyun #define WM8996_AIF2_BCLK_DIV_SHIFT 0 /* AIF2_BCLK_DIV - [3:0] */ 2136*4882a593Smuzhiyun #define WM8996_AIF2_BCLK_DIV_WIDTH 4 /* AIF2_BCLK_DIV - [3:0] */ 2137*4882a593Smuzhiyun 2138*4882a593Smuzhiyun /* 2139*4882a593Smuzhiyun * R802 (0x322) - AIF2 TX LRCLK(1) 2140*4882a593Smuzhiyun */ 2141*4882a593Smuzhiyun #define WM8996_AIF2TX_RATE_MASK 0x07FF /* AIF2TX_RATE - [10:0] */ 2142*4882a593Smuzhiyun #define WM8996_AIF2TX_RATE_SHIFT 0 /* AIF2TX_RATE - [10:0] */ 2143*4882a593Smuzhiyun #define WM8996_AIF2TX_RATE_WIDTH 11 /* AIF2TX_RATE - [10:0] */ 2144*4882a593Smuzhiyun 2145*4882a593Smuzhiyun /* 2146*4882a593Smuzhiyun * R803 (0x323) - AIF2 TX LRCLK(2) 2147*4882a593Smuzhiyun */ 2148*4882a593Smuzhiyun #define WM8996_AIF2TX_LRCLK_MODE 0x0008 /* AIF2TX_LRCLK_MODE */ 2149*4882a593Smuzhiyun #define WM8996_AIF2TX_LRCLK_MODE_MASK 0x0008 /* AIF2TX_LRCLK_MODE */ 2150*4882a593Smuzhiyun #define WM8996_AIF2TX_LRCLK_MODE_SHIFT 3 /* AIF2TX_LRCLK_MODE */ 2151*4882a593Smuzhiyun #define WM8996_AIF2TX_LRCLK_MODE_WIDTH 1 /* AIF2TX_LRCLK_MODE */ 2152*4882a593Smuzhiyun #define WM8996_AIF2TX_LRCLK_INV 0x0004 /* AIF2TX_LRCLK_INV */ 2153*4882a593Smuzhiyun #define WM8996_AIF2TX_LRCLK_INV_MASK 0x0004 /* AIF2TX_LRCLK_INV */ 2154*4882a593Smuzhiyun #define WM8996_AIF2TX_LRCLK_INV_SHIFT 2 /* AIF2TX_LRCLK_INV */ 2155*4882a593Smuzhiyun #define WM8996_AIF2TX_LRCLK_INV_WIDTH 1 /* AIF2TX_LRCLK_INV */ 2156*4882a593Smuzhiyun #define WM8996_AIF2TX_LRCLK_FRC 0x0002 /* AIF2TX_LRCLK_FRC */ 2157*4882a593Smuzhiyun #define WM8996_AIF2TX_LRCLK_FRC_MASK 0x0002 /* AIF2TX_LRCLK_FRC */ 2158*4882a593Smuzhiyun #define WM8996_AIF2TX_LRCLK_FRC_SHIFT 1 /* AIF2TX_LRCLK_FRC */ 2159*4882a593Smuzhiyun #define WM8996_AIF2TX_LRCLK_FRC_WIDTH 1 /* AIF2TX_LRCLK_FRC */ 2160*4882a593Smuzhiyun #define WM8996_AIF2TX_LRCLK_MSTR 0x0001 /* AIF2TX_LRCLK_MSTR */ 2161*4882a593Smuzhiyun #define WM8996_AIF2TX_LRCLK_MSTR_MASK 0x0001 /* AIF2TX_LRCLK_MSTR */ 2162*4882a593Smuzhiyun #define WM8996_AIF2TX_LRCLK_MSTR_SHIFT 0 /* AIF2TX_LRCLK_MSTR */ 2163*4882a593Smuzhiyun #define WM8996_AIF2TX_LRCLK_MSTR_WIDTH 1 /* AIF2TX_LRCLK_MSTR */ 2164*4882a593Smuzhiyun 2165*4882a593Smuzhiyun /* 2166*4882a593Smuzhiyun * R804 (0x324) - AIF2 RX LRCLK(1) 2167*4882a593Smuzhiyun */ 2168*4882a593Smuzhiyun #define WM8996_AIF2RX_RATE_MASK 0x07FF /* AIF2RX_RATE - [10:0] */ 2169*4882a593Smuzhiyun #define WM8996_AIF2RX_RATE_SHIFT 0 /* AIF2RX_RATE - [10:0] */ 2170*4882a593Smuzhiyun #define WM8996_AIF2RX_RATE_WIDTH 11 /* AIF2RX_RATE - [10:0] */ 2171*4882a593Smuzhiyun 2172*4882a593Smuzhiyun /* 2173*4882a593Smuzhiyun * R805 (0x325) - AIF2 RX LRCLK(2) 2174*4882a593Smuzhiyun */ 2175*4882a593Smuzhiyun #define WM8996_AIF2RX_LRCLK_INV 0x0004 /* AIF2RX_LRCLK_INV */ 2176*4882a593Smuzhiyun #define WM8996_AIF2RX_LRCLK_INV_MASK 0x0004 /* AIF2RX_LRCLK_INV */ 2177*4882a593Smuzhiyun #define WM8996_AIF2RX_LRCLK_INV_SHIFT 2 /* AIF2RX_LRCLK_INV */ 2178*4882a593Smuzhiyun #define WM8996_AIF2RX_LRCLK_INV_WIDTH 1 /* AIF2RX_LRCLK_INV */ 2179*4882a593Smuzhiyun #define WM8996_AIF2RX_LRCLK_FRC 0x0002 /* AIF2RX_LRCLK_FRC */ 2180*4882a593Smuzhiyun #define WM8996_AIF2RX_LRCLK_FRC_MASK 0x0002 /* AIF2RX_LRCLK_FRC */ 2181*4882a593Smuzhiyun #define WM8996_AIF2RX_LRCLK_FRC_SHIFT 1 /* AIF2RX_LRCLK_FRC */ 2182*4882a593Smuzhiyun #define WM8996_AIF2RX_LRCLK_FRC_WIDTH 1 /* AIF2RX_LRCLK_FRC */ 2183*4882a593Smuzhiyun #define WM8996_AIF2RX_LRCLK_MSTR 0x0001 /* AIF2RX_LRCLK_MSTR */ 2184*4882a593Smuzhiyun #define WM8996_AIF2RX_LRCLK_MSTR_MASK 0x0001 /* AIF2RX_LRCLK_MSTR */ 2185*4882a593Smuzhiyun #define WM8996_AIF2RX_LRCLK_MSTR_SHIFT 0 /* AIF2RX_LRCLK_MSTR */ 2186*4882a593Smuzhiyun #define WM8996_AIF2RX_LRCLK_MSTR_WIDTH 1 /* AIF2RX_LRCLK_MSTR */ 2187*4882a593Smuzhiyun 2188*4882a593Smuzhiyun /* 2189*4882a593Smuzhiyun * R806 (0x326) - AIF2TX Data Configuration (1) 2190*4882a593Smuzhiyun */ 2191*4882a593Smuzhiyun #define WM8996_AIF2TX_WL_MASK 0xFF00 /* AIF2TX_WL - [15:8] */ 2192*4882a593Smuzhiyun #define WM8996_AIF2TX_WL_SHIFT 8 /* AIF2TX_WL - [15:8] */ 2193*4882a593Smuzhiyun #define WM8996_AIF2TX_WL_WIDTH 8 /* AIF2TX_WL - [15:8] */ 2194*4882a593Smuzhiyun #define WM8996_AIF2TX_SLOT_LEN_MASK 0x00FF /* AIF2TX_SLOT_LEN - [7:0] */ 2195*4882a593Smuzhiyun #define WM8996_AIF2TX_SLOT_LEN_SHIFT 0 /* AIF2TX_SLOT_LEN - [7:0] */ 2196*4882a593Smuzhiyun #define WM8996_AIF2TX_SLOT_LEN_WIDTH 8 /* AIF2TX_SLOT_LEN - [7:0] */ 2197*4882a593Smuzhiyun 2198*4882a593Smuzhiyun /* 2199*4882a593Smuzhiyun * R807 (0x327) - AIF2TX Data Configuration (2) 2200*4882a593Smuzhiyun */ 2201*4882a593Smuzhiyun #define WM8996_AIF2TX_DAT_TRI 0x0001 /* AIF2TX_DAT_TRI */ 2202*4882a593Smuzhiyun #define WM8996_AIF2TX_DAT_TRI_MASK 0x0001 /* AIF2TX_DAT_TRI */ 2203*4882a593Smuzhiyun #define WM8996_AIF2TX_DAT_TRI_SHIFT 0 /* AIF2TX_DAT_TRI */ 2204*4882a593Smuzhiyun #define WM8996_AIF2TX_DAT_TRI_WIDTH 1 /* AIF2TX_DAT_TRI */ 2205*4882a593Smuzhiyun 2206*4882a593Smuzhiyun /* 2207*4882a593Smuzhiyun * R808 (0x328) - AIF2RX Data Configuration 2208*4882a593Smuzhiyun */ 2209*4882a593Smuzhiyun #define WM8996_AIF2RX_WL_MASK 0xFF00 /* AIF2RX_WL - [15:8] */ 2210*4882a593Smuzhiyun #define WM8996_AIF2RX_WL_SHIFT 8 /* AIF2RX_WL - [15:8] */ 2211*4882a593Smuzhiyun #define WM8996_AIF2RX_WL_WIDTH 8 /* AIF2RX_WL - [15:8] */ 2212*4882a593Smuzhiyun #define WM8996_AIF2RX_SLOT_LEN_MASK 0x00FF /* AIF2RX_SLOT_LEN - [7:0] */ 2213*4882a593Smuzhiyun #define WM8996_AIF2RX_SLOT_LEN_SHIFT 0 /* AIF2RX_SLOT_LEN - [7:0] */ 2214*4882a593Smuzhiyun #define WM8996_AIF2RX_SLOT_LEN_WIDTH 8 /* AIF2RX_SLOT_LEN - [7:0] */ 2215*4882a593Smuzhiyun 2216*4882a593Smuzhiyun /* 2217*4882a593Smuzhiyun * R809 (0x329) - AIF2TX Channel 0 Configuration 2218*4882a593Smuzhiyun */ 2219*4882a593Smuzhiyun #define WM8996_AIF2TX_CHAN0_DAT_INV 0x8000 /* AIF2TX_CHAN0_DAT_INV */ 2220*4882a593Smuzhiyun #define WM8996_AIF2TX_CHAN0_DAT_INV_MASK 0x8000 /* AIF2TX_CHAN0_DAT_INV */ 2221*4882a593Smuzhiyun #define WM8996_AIF2TX_CHAN0_DAT_INV_SHIFT 15 /* AIF2TX_CHAN0_DAT_INV */ 2222*4882a593Smuzhiyun #define WM8996_AIF2TX_CHAN0_DAT_INV_WIDTH 1 /* AIF2TX_CHAN0_DAT_INV */ 2223*4882a593Smuzhiyun #define WM8996_AIF2TX_CHAN0_SPACING_MASK 0x7E00 /* AIF2TX_CHAN0_SPACING - [14:9] */ 2224*4882a593Smuzhiyun #define WM8996_AIF2TX_CHAN0_SPACING_SHIFT 9 /* AIF2TX_CHAN0_SPACING - [14:9] */ 2225*4882a593Smuzhiyun #define WM8996_AIF2TX_CHAN0_SPACING_WIDTH 6 /* AIF2TX_CHAN0_SPACING - [14:9] */ 2226*4882a593Smuzhiyun #define WM8996_AIF2TX_CHAN0_SLOTS_MASK 0x01C0 /* AIF2TX_CHAN0_SLOTS - [8:6] */ 2227*4882a593Smuzhiyun #define WM8996_AIF2TX_CHAN0_SLOTS_SHIFT 6 /* AIF2TX_CHAN0_SLOTS - [8:6] */ 2228*4882a593Smuzhiyun #define WM8996_AIF2TX_CHAN0_SLOTS_WIDTH 3 /* AIF2TX_CHAN0_SLOTS - [8:6] */ 2229*4882a593Smuzhiyun #define WM8996_AIF2TX_CHAN0_START_SLOT_MASK 0x003F /* AIF2TX_CHAN0_START_SLOT - [5:0] */ 2230*4882a593Smuzhiyun #define WM8996_AIF2TX_CHAN0_START_SLOT_SHIFT 0 /* AIF2TX_CHAN0_START_SLOT - [5:0] */ 2231*4882a593Smuzhiyun #define WM8996_AIF2TX_CHAN0_START_SLOT_WIDTH 6 /* AIF2TX_CHAN0_START_SLOT - [5:0] */ 2232*4882a593Smuzhiyun 2233*4882a593Smuzhiyun /* 2234*4882a593Smuzhiyun * R810 (0x32A) - AIF2TX Channel 1 Configuration 2235*4882a593Smuzhiyun */ 2236*4882a593Smuzhiyun #define WM8996_AIF2TX_CHAN1_DAT_INV 0x8000 /* AIF2TX_CHAN1_DAT_INV */ 2237*4882a593Smuzhiyun #define WM8996_AIF2TX_CHAN1_DAT_INV_MASK 0x8000 /* AIF2TX_CHAN1_DAT_INV */ 2238*4882a593Smuzhiyun #define WM8996_AIF2TX_CHAN1_DAT_INV_SHIFT 15 /* AIF2TX_CHAN1_DAT_INV */ 2239*4882a593Smuzhiyun #define WM8996_AIF2TX_CHAN1_DAT_INV_WIDTH 1 /* AIF2TX_CHAN1_DAT_INV */ 2240*4882a593Smuzhiyun #define WM8996_AIF2TX_CHAN1_SPACING_MASK 0x7E00 /* AIF2TX_CHAN1_SPACING - [14:9] */ 2241*4882a593Smuzhiyun #define WM8996_AIF2TX_CHAN1_SPACING_SHIFT 9 /* AIF2TX_CHAN1_SPACING - [14:9] */ 2242*4882a593Smuzhiyun #define WM8996_AIF2TX_CHAN1_SPACING_WIDTH 6 /* AIF2TX_CHAN1_SPACING - [14:9] */ 2243*4882a593Smuzhiyun #define WM8996_AIF2TX_CHAN1_SLOTS_MASK 0x01C0 /* AIF2TX_CHAN1_SLOTS - [8:6] */ 2244*4882a593Smuzhiyun #define WM8996_AIF2TX_CHAN1_SLOTS_SHIFT 6 /* AIF2TX_CHAN1_SLOTS - [8:6] */ 2245*4882a593Smuzhiyun #define WM8996_AIF2TX_CHAN1_SLOTS_WIDTH 3 /* AIF2TX_CHAN1_SLOTS - [8:6] */ 2246*4882a593Smuzhiyun #define WM8996_AIF2TX_CHAN1_START_SLOT_MASK 0x003F /* AIF2TX_CHAN1_START_SLOT - [5:0] */ 2247*4882a593Smuzhiyun #define WM8996_AIF2TX_CHAN1_START_SLOT_SHIFT 0 /* AIF2TX_CHAN1_START_SLOT - [5:0] */ 2248*4882a593Smuzhiyun #define WM8996_AIF2TX_CHAN1_START_SLOT_WIDTH 6 /* AIF2TX_CHAN1_START_SLOT - [5:0] */ 2249*4882a593Smuzhiyun 2250*4882a593Smuzhiyun /* 2251*4882a593Smuzhiyun * R811 (0x32B) - AIF2RX Channel 0 Configuration 2252*4882a593Smuzhiyun */ 2253*4882a593Smuzhiyun #define WM8996_AIF2RX_CHAN0_DAT_INV 0x8000 /* AIF2RX_CHAN0_DAT_INV */ 2254*4882a593Smuzhiyun #define WM8996_AIF2RX_CHAN0_DAT_INV_MASK 0x8000 /* AIF2RX_CHAN0_DAT_INV */ 2255*4882a593Smuzhiyun #define WM8996_AIF2RX_CHAN0_DAT_INV_SHIFT 15 /* AIF2RX_CHAN0_DAT_INV */ 2256*4882a593Smuzhiyun #define WM8996_AIF2RX_CHAN0_DAT_INV_WIDTH 1 /* AIF2RX_CHAN0_DAT_INV */ 2257*4882a593Smuzhiyun #define WM8996_AIF2RX_CHAN0_SPACING_MASK 0x7E00 /* AIF2RX_CHAN0_SPACING - [14:9] */ 2258*4882a593Smuzhiyun #define WM8996_AIF2RX_CHAN0_SPACING_SHIFT 9 /* AIF2RX_CHAN0_SPACING - [14:9] */ 2259*4882a593Smuzhiyun #define WM8996_AIF2RX_CHAN0_SPACING_WIDTH 6 /* AIF2RX_CHAN0_SPACING - [14:9] */ 2260*4882a593Smuzhiyun #define WM8996_AIF2RX_CHAN0_SLOTS_MASK 0x01C0 /* AIF2RX_CHAN0_SLOTS - [8:6] */ 2261*4882a593Smuzhiyun #define WM8996_AIF2RX_CHAN0_SLOTS_SHIFT 6 /* AIF2RX_CHAN0_SLOTS - [8:6] */ 2262*4882a593Smuzhiyun #define WM8996_AIF2RX_CHAN0_SLOTS_WIDTH 3 /* AIF2RX_CHAN0_SLOTS - [8:6] */ 2263*4882a593Smuzhiyun #define WM8996_AIF2RX_CHAN0_START_SLOT_MASK 0x003F /* AIF2RX_CHAN0_START_SLOT - [5:0] */ 2264*4882a593Smuzhiyun #define WM8996_AIF2RX_CHAN0_START_SLOT_SHIFT 0 /* AIF2RX_CHAN0_START_SLOT - [5:0] */ 2265*4882a593Smuzhiyun #define WM8996_AIF2RX_CHAN0_START_SLOT_WIDTH 6 /* AIF2RX_CHAN0_START_SLOT - [5:0] */ 2266*4882a593Smuzhiyun 2267*4882a593Smuzhiyun /* 2268*4882a593Smuzhiyun * R812 (0x32C) - AIF2RX Channel 1 Configuration 2269*4882a593Smuzhiyun */ 2270*4882a593Smuzhiyun #define WM8996_AIF2RX_CHAN1_DAT_INV 0x8000 /* AIF2RX_CHAN1_DAT_INV */ 2271*4882a593Smuzhiyun #define WM8996_AIF2RX_CHAN1_DAT_INV_MASK 0x8000 /* AIF2RX_CHAN1_DAT_INV */ 2272*4882a593Smuzhiyun #define WM8996_AIF2RX_CHAN1_DAT_INV_SHIFT 15 /* AIF2RX_CHAN1_DAT_INV */ 2273*4882a593Smuzhiyun #define WM8996_AIF2RX_CHAN1_DAT_INV_WIDTH 1 /* AIF2RX_CHAN1_DAT_INV */ 2274*4882a593Smuzhiyun #define WM8996_AIF2RX_CHAN1_SPACING_MASK 0x7E00 /* AIF2RX_CHAN1_SPACING - [14:9] */ 2275*4882a593Smuzhiyun #define WM8996_AIF2RX_CHAN1_SPACING_SHIFT 9 /* AIF2RX_CHAN1_SPACING - [14:9] */ 2276*4882a593Smuzhiyun #define WM8996_AIF2RX_CHAN1_SPACING_WIDTH 6 /* AIF2RX_CHAN1_SPACING - [14:9] */ 2277*4882a593Smuzhiyun #define WM8996_AIF2RX_CHAN1_SLOTS_MASK 0x01C0 /* AIF2RX_CHAN1_SLOTS - [8:6] */ 2278*4882a593Smuzhiyun #define WM8996_AIF2RX_CHAN1_SLOTS_SHIFT 6 /* AIF2RX_CHAN1_SLOTS - [8:6] */ 2279*4882a593Smuzhiyun #define WM8996_AIF2RX_CHAN1_SLOTS_WIDTH 3 /* AIF2RX_CHAN1_SLOTS - [8:6] */ 2280*4882a593Smuzhiyun #define WM8996_AIF2RX_CHAN1_START_SLOT_MASK 0x003F /* AIF2RX_CHAN1_START_SLOT - [5:0] */ 2281*4882a593Smuzhiyun #define WM8996_AIF2RX_CHAN1_START_SLOT_SHIFT 0 /* AIF2RX_CHAN1_START_SLOT - [5:0] */ 2282*4882a593Smuzhiyun #define WM8996_AIF2RX_CHAN1_START_SLOT_WIDTH 6 /* AIF2RX_CHAN1_START_SLOT - [5:0] */ 2283*4882a593Smuzhiyun 2284*4882a593Smuzhiyun /* 2285*4882a593Smuzhiyun * R813 (0x32D) - AIF2RX Mono Configuration 2286*4882a593Smuzhiyun */ 2287*4882a593Smuzhiyun #define WM8996_AIF2RX_CHAN0_MONO_MODE 0x0001 /* AIF2RX_CHAN0_MONO_MODE */ 2288*4882a593Smuzhiyun #define WM8996_AIF2RX_CHAN0_MONO_MODE_MASK 0x0001 /* AIF2RX_CHAN0_MONO_MODE */ 2289*4882a593Smuzhiyun #define WM8996_AIF2RX_CHAN0_MONO_MODE_SHIFT 0 /* AIF2RX_CHAN0_MONO_MODE */ 2290*4882a593Smuzhiyun #define WM8996_AIF2RX_CHAN0_MONO_MODE_WIDTH 1 /* AIF2RX_CHAN0_MONO_MODE */ 2291*4882a593Smuzhiyun 2292*4882a593Smuzhiyun /* 2293*4882a593Smuzhiyun * R815 (0x32F) - AIF2TX Test 2294*4882a593Smuzhiyun */ 2295*4882a593Smuzhiyun #define WM8996_AIF2TX_DITHER_ENA 0x0001 /* AIF2TX_DITHER_ENA */ 2296*4882a593Smuzhiyun #define WM8996_AIF2TX_DITHER_ENA_MASK 0x0001 /* AIF2TX_DITHER_ENA */ 2297*4882a593Smuzhiyun #define WM8996_AIF2TX_DITHER_ENA_SHIFT 0 /* AIF2TX_DITHER_ENA */ 2298*4882a593Smuzhiyun #define WM8996_AIF2TX_DITHER_ENA_WIDTH 1 /* AIF2TX_DITHER_ENA */ 2299*4882a593Smuzhiyun 2300*4882a593Smuzhiyun /* 2301*4882a593Smuzhiyun * R1024 (0x400) - DSP1 TX Left Volume 2302*4882a593Smuzhiyun */ 2303*4882a593Smuzhiyun #define WM8996_DSP1TX_VU 0x0100 /* DSP1TX_VU */ 2304*4882a593Smuzhiyun #define WM8996_DSP1TX_VU_MASK 0x0100 /* DSP1TX_VU */ 2305*4882a593Smuzhiyun #define WM8996_DSP1TX_VU_SHIFT 8 /* DSP1TX_VU */ 2306*4882a593Smuzhiyun #define WM8996_DSP1TX_VU_WIDTH 1 /* DSP1TX_VU */ 2307*4882a593Smuzhiyun #define WM8996_DSP1TXL_VOL_MASK 0x00FF /* DSP1TXL_VOL - [7:0] */ 2308*4882a593Smuzhiyun #define WM8996_DSP1TXL_VOL_SHIFT 0 /* DSP1TXL_VOL - [7:0] */ 2309*4882a593Smuzhiyun #define WM8996_DSP1TXL_VOL_WIDTH 8 /* DSP1TXL_VOL - [7:0] */ 2310*4882a593Smuzhiyun 2311*4882a593Smuzhiyun /* 2312*4882a593Smuzhiyun * R1025 (0x401) - DSP1 TX Right Volume 2313*4882a593Smuzhiyun */ 2314*4882a593Smuzhiyun #define WM8996_DSP1TX_VU 0x0100 /* DSP1TX_VU */ 2315*4882a593Smuzhiyun #define WM8996_DSP1TX_VU_MASK 0x0100 /* DSP1TX_VU */ 2316*4882a593Smuzhiyun #define WM8996_DSP1TX_VU_SHIFT 8 /* DSP1TX_VU */ 2317*4882a593Smuzhiyun #define WM8996_DSP1TX_VU_WIDTH 1 /* DSP1TX_VU */ 2318*4882a593Smuzhiyun #define WM8996_DSP1TXR_VOL_MASK 0x00FF /* DSP1TXR_VOL - [7:0] */ 2319*4882a593Smuzhiyun #define WM8996_DSP1TXR_VOL_SHIFT 0 /* DSP1TXR_VOL - [7:0] */ 2320*4882a593Smuzhiyun #define WM8996_DSP1TXR_VOL_WIDTH 8 /* DSP1TXR_VOL - [7:0] */ 2321*4882a593Smuzhiyun 2322*4882a593Smuzhiyun /* 2323*4882a593Smuzhiyun * R1026 (0x402) - DSP1 RX Left Volume 2324*4882a593Smuzhiyun */ 2325*4882a593Smuzhiyun #define WM8996_DSP1RX_VU 0x0100 /* DSP1RX_VU */ 2326*4882a593Smuzhiyun #define WM8996_DSP1RX_VU_MASK 0x0100 /* DSP1RX_VU */ 2327*4882a593Smuzhiyun #define WM8996_DSP1RX_VU_SHIFT 8 /* DSP1RX_VU */ 2328*4882a593Smuzhiyun #define WM8996_DSP1RX_VU_WIDTH 1 /* DSP1RX_VU */ 2329*4882a593Smuzhiyun #define WM8996_DSP1RXL_VOL_MASK 0x00FF /* DSP1RXL_VOL - [7:0] */ 2330*4882a593Smuzhiyun #define WM8996_DSP1RXL_VOL_SHIFT 0 /* DSP1RXL_VOL - [7:0] */ 2331*4882a593Smuzhiyun #define WM8996_DSP1RXL_VOL_WIDTH 8 /* DSP1RXL_VOL - [7:0] */ 2332*4882a593Smuzhiyun 2333*4882a593Smuzhiyun /* 2334*4882a593Smuzhiyun * R1027 (0x403) - DSP1 RX Right Volume 2335*4882a593Smuzhiyun */ 2336*4882a593Smuzhiyun #define WM8996_DSP1RX_VU 0x0100 /* DSP1RX_VU */ 2337*4882a593Smuzhiyun #define WM8996_DSP1RX_VU_MASK 0x0100 /* DSP1RX_VU */ 2338*4882a593Smuzhiyun #define WM8996_DSP1RX_VU_SHIFT 8 /* DSP1RX_VU */ 2339*4882a593Smuzhiyun #define WM8996_DSP1RX_VU_WIDTH 1 /* DSP1RX_VU */ 2340*4882a593Smuzhiyun #define WM8996_DSP1RXR_VOL_MASK 0x00FF /* DSP1RXR_VOL - [7:0] */ 2341*4882a593Smuzhiyun #define WM8996_DSP1RXR_VOL_SHIFT 0 /* DSP1RXR_VOL - [7:0] */ 2342*4882a593Smuzhiyun #define WM8996_DSP1RXR_VOL_WIDTH 8 /* DSP1RXR_VOL - [7:0] */ 2343*4882a593Smuzhiyun 2344*4882a593Smuzhiyun /* 2345*4882a593Smuzhiyun * R1040 (0x410) - DSP1 TX Filters 2346*4882a593Smuzhiyun */ 2347*4882a593Smuzhiyun #define WM8996_DSP1TX_NF 0x2000 /* DSP1TX_NF */ 2348*4882a593Smuzhiyun #define WM8996_DSP1TX_NF_MASK 0x2000 /* DSP1TX_NF */ 2349*4882a593Smuzhiyun #define WM8996_DSP1TX_NF_SHIFT 13 /* DSP1TX_NF */ 2350*4882a593Smuzhiyun #define WM8996_DSP1TX_NF_WIDTH 1 /* DSP1TX_NF */ 2351*4882a593Smuzhiyun #define WM8996_DSP1TXL_HPF 0x1000 /* DSP1TXL_HPF */ 2352*4882a593Smuzhiyun #define WM8996_DSP1TXL_HPF_MASK 0x1000 /* DSP1TXL_HPF */ 2353*4882a593Smuzhiyun #define WM8996_DSP1TXL_HPF_SHIFT 12 /* DSP1TXL_HPF */ 2354*4882a593Smuzhiyun #define WM8996_DSP1TXL_HPF_WIDTH 1 /* DSP1TXL_HPF */ 2355*4882a593Smuzhiyun #define WM8996_DSP1TXR_HPF 0x0800 /* DSP1TXR_HPF */ 2356*4882a593Smuzhiyun #define WM8996_DSP1TXR_HPF_MASK 0x0800 /* DSP1TXR_HPF */ 2357*4882a593Smuzhiyun #define WM8996_DSP1TXR_HPF_SHIFT 11 /* DSP1TXR_HPF */ 2358*4882a593Smuzhiyun #define WM8996_DSP1TXR_HPF_WIDTH 1 /* DSP1TXR_HPF */ 2359*4882a593Smuzhiyun #define WM8996_DSP1TX_HPF_MODE_MASK 0x0018 /* DSP1TX_HPF_MODE - [4:3] */ 2360*4882a593Smuzhiyun #define WM8996_DSP1TX_HPF_MODE_SHIFT 3 /* DSP1TX_HPF_MODE - [4:3] */ 2361*4882a593Smuzhiyun #define WM8996_DSP1TX_HPF_MODE_WIDTH 2 /* DSP1TX_HPF_MODE - [4:3] */ 2362*4882a593Smuzhiyun #define WM8996_DSP1TX_HPF_CUT_MASK 0x0007 /* DSP1TX_HPF_CUT - [2:0] */ 2363*4882a593Smuzhiyun #define WM8996_DSP1TX_HPF_CUT_SHIFT 0 /* DSP1TX_HPF_CUT - [2:0] */ 2364*4882a593Smuzhiyun #define WM8996_DSP1TX_HPF_CUT_WIDTH 3 /* DSP1TX_HPF_CUT - [2:0] */ 2365*4882a593Smuzhiyun 2366*4882a593Smuzhiyun /* 2367*4882a593Smuzhiyun * R1056 (0x420) - DSP1 RX Filters (1) 2368*4882a593Smuzhiyun */ 2369*4882a593Smuzhiyun #define WM8996_DSP1RX_MUTE 0x0200 /* DSP1RX_MUTE */ 2370*4882a593Smuzhiyun #define WM8996_DSP1RX_MUTE_MASK 0x0200 /* DSP1RX_MUTE */ 2371*4882a593Smuzhiyun #define WM8996_DSP1RX_MUTE_SHIFT 9 /* DSP1RX_MUTE */ 2372*4882a593Smuzhiyun #define WM8996_DSP1RX_MUTE_WIDTH 1 /* DSP1RX_MUTE */ 2373*4882a593Smuzhiyun #define WM8996_DSP1RX_MONO 0x0080 /* DSP1RX_MONO */ 2374*4882a593Smuzhiyun #define WM8996_DSP1RX_MONO_MASK 0x0080 /* DSP1RX_MONO */ 2375*4882a593Smuzhiyun #define WM8996_DSP1RX_MONO_SHIFT 7 /* DSP1RX_MONO */ 2376*4882a593Smuzhiyun #define WM8996_DSP1RX_MONO_WIDTH 1 /* DSP1RX_MONO */ 2377*4882a593Smuzhiyun #define WM8996_DSP1RX_MUTERATE 0x0020 /* DSP1RX_MUTERATE */ 2378*4882a593Smuzhiyun #define WM8996_DSP1RX_MUTERATE_MASK 0x0020 /* DSP1RX_MUTERATE */ 2379*4882a593Smuzhiyun #define WM8996_DSP1RX_MUTERATE_SHIFT 5 /* DSP1RX_MUTERATE */ 2380*4882a593Smuzhiyun #define WM8996_DSP1RX_MUTERATE_WIDTH 1 /* DSP1RX_MUTERATE */ 2381*4882a593Smuzhiyun #define WM8996_DSP1RX_UNMUTE_RAMP 0x0010 /* DSP1RX_UNMUTE_RAMP */ 2382*4882a593Smuzhiyun #define WM8996_DSP1RX_UNMUTE_RAMP_MASK 0x0010 /* DSP1RX_UNMUTE_RAMP */ 2383*4882a593Smuzhiyun #define WM8996_DSP1RX_UNMUTE_RAMP_SHIFT 4 /* DSP1RX_UNMUTE_RAMP */ 2384*4882a593Smuzhiyun #define WM8996_DSP1RX_UNMUTE_RAMP_WIDTH 1 /* DSP1RX_UNMUTE_RAMP */ 2385*4882a593Smuzhiyun 2386*4882a593Smuzhiyun /* 2387*4882a593Smuzhiyun * R1057 (0x421) - DSP1 RX Filters (2) 2388*4882a593Smuzhiyun */ 2389*4882a593Smuzhiyun #define WM8996_DSP1RX_3D_GAIN_MASK 0x3E00 /* DSP1RX_3D_GAIN - [13:9] */ 2390*4882a593Smuzhiyun #define WM8996_DSP1RX_3D_GAIN_SHIFT 9 /* DSP1RX_3D_GAIN - [13:9] */ 2391*4882a593Smuzhiyun #define WM8996_DSP1RX_3D_GAIN_WIDTH 5 /* DSP1RX_3D_GAIN - [13:9] */ 2392*4882a593Smuzhiyun #define WM8996_DSP1RX_3D_ENA 0x0100 /* DSP1RX_3D_ENA */ 2393*4882a593Smuzhiyun #define WM8996_DSP1RX_3D_ENA_MASK 0x0100 /* DSP1RX_3D_ENA */ 2394*4882a593Smuzhiyun #define WM8996_DSP1RX_3D_ENA_SHIFT 8 /* DSP1RX_3D_ENA */ 2395*4882a593Smuzhiyun #define WM8996_DSP1RX_3D_ENA_WIDTH 1 /* DSP1RX_3D_ENA */ 2396*4882a593Smuzhiyun 2397*4882a593Smuzhiyun /* 2398*4882a593Smuzhiyun * R1088 (0x440) - DSP1 DRC (1) 2399*4882a593Smuzhiyun */ 2400*4882a593Smuzhiyun #define WM8996_DSP1DRC_SIG_DET_RMS_MASK 0xF800 /* DSP1DRC_SIG_DET_RMS - [15:11] */ 2401*4882a593Smuzhiyun #define WM8996_DSP1DRC_SIG_DET_RMS_SHIFT 11 /* DSP1DRC_SIG_DET_RMS - [15:11] */ 2402*4882a593Smuzhiyun #define WM8996_DSP1DRC_SIG_DET_RMS_WIDTH 5 /* DSP1DRC_SIG_DET_RMS - [15:11] */ 2403*4882a593Smuzhiyun #define WM8996_DSP1DRC_SIG_DET_PK_MASK 0x0600 /* DSP1DRC_SIG_DET_PK - [10:9] */ 2404*4882a593Smuzhiyun #define WM8996_DSP1DRC_SIG_DET_PK_SHIFT 9 /* DSP1DRC_SIG_DET_PK - [10:9] */ 2405*4882a593Smuzhiyun #define WM8996_DSP1DRC_SIG_DET_PK_WIDTH 2 /* DSP1DRC_SIG_DET_PK - [10:9] */ 2406*4882a593Smuzhiyun #define WM8996_DSP1DRC_NG_ENA 0x0100 /* DSP1DRC_NG_ENA */ 2407*4882a593Smuzhiyun #define WM8996_DSP1DRC_NG_ENA_MASK 0x0100 /* DSP1DRC_NG_ENA */ 2408*4882a593Smuzhiyun #define WM8996_DSP1DRC_NG_ENA_SHIFT 8 /* DSP1DRC_NG_ENA */ 2409*4882a593Smuzhiyun #define WM8996_DSP1DRC_NG_ENA_WIDTH 1 /* DSP1DRC_NG_ENA */ 2410*4882a593Smuzhiyun #define WM8996_DSP1DRC_SIG_DET_MODE 0x0080 /* DSP1DRC_SIG_DET_MODE */ 2411*4882a593Smuzhiyun #define WM8996_DSP1DRC_SIG_DET_MODE_MASK 0x0080 /* DSP1DRC_SIG_DET_MODE */ 2412*4882a593Smuzhiyun #define WM8996_DSP1DRC_SIG_DET_MODE_SHIFT 7 /* DSP1DRC_SIG_DET_MODE */ 2413*4882a593Smuzhiyun #define WM8996_DSP1DRC_SIG_DET_MODE_WIDTH 1 /* DSP1DRC_SIG_DET_MODE */ 2414*4882a593Smuzhiyun #define WM8996_DSP1DRC_SIG_DET 0x0040 /* DSP1DRC_SIG_DET */ 2415*4882a593Smuzhiyun #define WM8996_DSP1DRC_SIG_DET_MASK 0x0040 /* DSP1DRC_SIG_DET */ 2416*4882a593Smuzhiyun #define WM8996_DSP1DRC_SIG_DET_SHIFT 6 /* DSP1DRC_SIG_DET */ 2417*4882a593Smuzhiyun #define WM8996_DSP1DRC_SIG_DET_WIDTH 1 /* DSP1DRC_SIG_DET */ 2418*4882a593Smuzhiyun #define WM8996_DSP1DRC_KNEE2_OP_ENA 0x0020 /* DSP1DRC_KNEE2_OP_ENA */ 2419*4882a593Smuzhiyun #define WM8996_DSP1DRC_KNEE2_OP_ENA_MASK 0x0020 /* DSP1DRC_KNEE2_OP_ENA */ 2420*4882a593Smuzhiyun #define WM8996_DSP1DRC_KNEE2_OP_ENA_SHIFT 5 /* DSP1DRC_KNEE2_OP_ENA */ 2421*4882a593Smuzhiyun #define WM8996_DSP1DRC_KNEE2_OP_ENA_WIDTH 1 /* DSP1DRC_KNEE2_OP_ENA */ 2422*4882a593Smuzhiyun #define WM8996_DSP1DRC_QR 0x0010 /* DSP1DRC_QR */ 2423*4882a593Smuzhiyun #define WM8996_DSP1DRC_QR_MASK 0x0010 /* DSP1DRC_QR */ 2424*4882a593Smuzhiyun #define WM8996_DSP1DRC_QR_SHIFT 4 /* DSP1DRC_QR */ 2425*4882a593Smuzhiyun #define WM8996_DSP1DRC_QR_WIDTH 1 /* DSP1DRC_QR */ 2426*4882a593Smuzhiyun #define WM8996_DSP1DRC_ANTICLIP 0x0008 /* DSP1DRC_ANTICLIP */ 2427*4882a593Smuzhiyun #define WM8996_DSP1DRC_ANTICLIP_MASK 0x0008 /* DSP1DRC_ANTICLIP */ 2428*4882a593Smuzhiyun #define WM8996_DSP1DRC_ANTICLIP_SHIFT 3 /* DSP1DRC_ANTICLIP */ 2429*4882a593Smuzhiyun #define WM8996_DSP1DRC_ANTICLIP_WIDTH 1 /* DSP1DRC_ANTICLIP */ 2430*4882a593Smuzhiyun #define WM8996_DSP1RX_DRC_ENA 0x0004 /* DSP1RX_DRC_ENA */ 2431*4882a593Smuzhiyun #define WM8996_DSP1RX_DRC_ENA_MASK 0x0004 /* DSP1RX_DRC_ENA */ 2432*4882a593Smuzhiyun #define WM8996_DSP1RX_DRC_ENA_SHIFT 2 /* DSP1RX_DRC_ENA */ 2433*4882a593Smuzhiyun #define WM8996_DSP1RX_DRC_ENA_WIDTH 1 /* DSP1RX_DRC_ENA */ 2434*4882a593Smuzhiyun #define WM8996_DSP1TXL_DRC_ENA 0x0002 /* DSP1TXL_DRC_ENA */ 2435*4882a593Smuzhiyun #define WM8996_DSP1TXL_DRC_ENA_MASK 0x0002 /* DSP1TXL_DRC_ENA */ 2436*4882a593Smuzhiyun #define WM8996_DSP1TXL_DRC_ENA_SHIFT 1 /* DSP1TXL_DRC_ENA */ 2437*4882a593Smuzhiyun #define WM8996_DSP1TXL_DRC_ENA_WIDTH 1 /* DSP1TXL_DRC_ENA */ 2438*4882a593Smuzhiyun #define WM8996_DSP1TXR_DRC_ENA 0x0001 /* DSP1TXR_DRC_ENA */ 2439*4882a593Smuzhiyun #define WM8996_DSP1TXR_DRC_ENA_MASK 0x0001 /* DSP1TXR_DRC_ENA */ 2440*4882a593Smuzhiyun #define WM8996_DSP1TXR_DRC_ENA_SHIFT 0 /* DSP1TXR_DRC_ENA */ 2441*4882a593Smuzhiyun #define WM8996_DSP1TXR_DRC_ENA_WIDTH 1 /* DSP1TXR_DRC_ENA */ 2442*4882a593Smuzhiyun 2443*4882a593Smuzhiyun /* 2444*4882a593Smuzhiyun * R1089 (0x441) - DSP1 DRC (2) 2445*4882a593Smuzhiyun */ 2446*4882a593Smuzhiyun #define WM8996_DSP1DRC_ATK_MASK 0x1E00 /* DSP1DRC_ATK - [12:9] */ 2447*4882a593Smuzhiyun #define WM8996_DSP1DRC_ATK_SHIFT 9 /* DSP1DRC_ATK - [12:9] */ 2448*4882a593Smuzhiyun #define WM8996_DSP1DRC_ATK_WIDTH 4 /* DSP1DRC_ATK - [12:9] */ 2449*4882a593Smuzhiyun #define WM8996_DSP1DRC_DCY_MASK 0x01E0 /* DSP1DRC_DCY - [8:5] */ 2450*4882a593Smuzhiyun #define WM8996_DSP1DRC_DCY_SHIFT 5 /* DSP1DRC_DCY - [8:5] */ 2451*4882a593Smuzhiyun #define WM8996_DSP1DRC_DCY_WIDTH 4 /* DSP1DRC_DCY - [8:5] */ 2452*4882a593Smuzhiyun #define WM8996_DSP1DRC_MINGAIN_MASK 0x001C /* DSP1DRC_MINGAIN - [4:2] */ 2453*4882a593Smuzhiyun #define WM8996_DSP1DRC_MINGAIN_SHIFT 2 /* DSP1DRC_MINGAIN - [4:2] */ 2454*4882a593Smuzhiyun #define WM8996_DSP1DRC_MINGAIN_WIDTH 3 /* DSP1DRC_MINGAIN - [4:2] */ 2455*4882a593Smuzhiyun #define WM8996_DSP1DRC_MAXGAIN_MASK 0x0003 /* DSP1DRC_MAXGAIN - [1:0] */ 2456*4882a593Smuzhiyun #define WM8996_DSP1DRC_MAXGAIN_SHIFT 0 /* DSP1DRC_MAXGAIN - [1:0] */ 2457*4882a593Smuzhiyun #define WM8996_DSP1DRC_MAXGAIN_WIDTH 2 /* DSP1DRC_MAXGAIN - [1:0] */ 2458*4882a593Smuzhiyun 2459*4882a593Smuzhiyun /* 2460*4882a593Smuzhiyun * R1090 (0x442) - DSP1 DRC (3) 2461*4882a593Smuzhiyun */ 2462*4882a593Smuzhiyun #define WM8996_DSP1DRC_NG_MINGAIN_MASK 0xF000 /* DSP1DRC_NG_MINGAIN - [15:12] */ 2463*4882a593Smuzhiyun #define WM8996_DSP1DRC_NG_MINGAIN_SHIFT 12 /* DSP1DRC_NG_MINGAIN - [15:12] */ 2464*4882a593Smuzhiyun #define WM8996_DSP1DRC_NG_MINGAIN_WIDTH 4 /* DSP1DRC_NG_MINGAIN - [15:12] */ 2465*4882a593Smuzhiyun #define WM8996_DSP1DRC_NG_EXP_MASK 0x0C00 /* DSP1DRC_NG_EXP - [11:10] */ 2466*4882a593Smuzhiyun #define WM8996_DSP1DRC_NG_EXP_SHIFT 10 /* DSP1DRC_NG_EXP - [11:10] */ 2467*4882a593Smuzhiyun #define WM8996_DSP1DRC_NG_EXP_WIDTH 2 /* DSP1DRC_NG_EXP - [11:10] */ 2468*4882a593Smuzhiyun #define WM8996_DSP1DRC_QR_THR_MASK 0x0300 /* DSP1DRC_QR_THR - [9:8] */ 2469*4882a593Smuzhiyun #define WM8996_DSP1DRC_QR_THR_SHIFT 8 /* DSP1DRC_QR_THR - [9:8] */ 2470*4882a593Smuzhiyun #define WM8996_DSP1DRC_QR_THR_WIDTH 2 /* DSP1DRC_QR_THR - [9:8] */ 2471*4882a593Smuzhiyun #define WM8996_DSP1DRC_QR_DCY_MASK 0x00C0 /* DSP1DRC_QR_DCY - [7:6] */ 2472*4882a593Smuzhiyun #define WM8996_DSP1DRC_QR_DCY_SHIFT 6 /* DSP1DRC_QR_DCY - [7:6] */ 2473*4882a593Smuzhiyun #define WM8996_DSP1DRC_QR_DCY_WIDTH 2 /* DSP1DRC_QR_DCY - [7:6] */ 2474*4882a593Smuzhiyun #define WM8996_DSP1DRC_HI_COMP_MASK 0x0038 /* DSP1DRC_HI_COMP - [5:3] */ 2475*4882a593Smuzhiyun #define WM8996_DSP1DRC_HI_COMP_SHIFT 3 /* DSP1DRC_HI_COMP - [5:3] */ 2476*4882a593Smuzhiyun #define WM8996_DSP1DRC_HI_COMP_WIDTH 3 /* DSP1DRC_HI_COMP - [5:3] */ 2477*4882a593Smuzhiyun #define WM8996_DSP1DRC_LO_COMP_MASK 0x0007 /* DSP1DRC_LO_COMP - [2:0] */ 2478*4882a593Smuzhiyun #define WM8996_DSP1DRC_LO_COMP_SHIFT 0 /* DSP1DRC_LO_COMP - [2:0] */ 2479*4882a593Smuzhiyun #define WM8996_DSP1DRC_LO_COMP_WIDTH 3 /* DSP1DRC_LO_COMP - [2:0] */ 2480*4882a593Smuzhiyun 2481*4882a593Smuzhiyun /* 2482*4882a593Smuzhiyun * R1091 (0x443) - DSP1 DRC (4) 2483*4882a593Smuzhiyun */ 2484*4882a593Smuzhiyun #define WM8996_DSP1DRC_KNEE_IP_MASK 0x07E0 /* DSP1DRC_KNEE_IP - [10:5] */ 2485*4882a593Smuzhiyun #define WM8996_DSP1DRC_KNEE_IP_SHIFT 5 /* DSP1DRC_KNEE_IP - [10:5] */ 2486*4882a593Smuzhiyun #define WM8996_DSP1DRC_KNEE_IP_WIDTH 6 /* DSP1DRC_KNEE_IP - [10:5] */ 2487*4882a593Smuzhiyun #define WM8996_DSP1DRC_KNEE_OP_MASK 0x001F /* DSP1DRC_KNEE_OP - [4:0] */ 2488*4882a593Smuzhiyun #define WM8996_DSP1DRC_KNEE_OP_SHIFT 0 /* DSP1DRC_KNEE_OP - [4:0] */ 2489*4882a593Smuzhiyun #define WM8996_DSP1DRC_KNEE_OP_WIDTH 5 /* DSP1DRC_KNEE_OP - [4:0] */ 2490*4882a593Smuzhiyun 2491*4882a593Smuzhiyun /* 2492*4882a593Smuzhiyun * R1092 (0x444) - DSP1 DRC (5) 2493*4882a593Smuzhiyun */ 2494*4882a593Smuzhiyun #define WM8996_DSP1DRC_KNEE2_IP_MASK 0x03E0 /* DSP1DRC_KNEE2_IP - [9:5] */ 2495*4882a593Smuzhiyun #define WM8996_DSP1DRC_KNEE2_IP_SHIFT 5 /* DSP1DRC_KNEE2_IP - [9:5] */ 2496*4882a593Smuzhiyun #define WM8996_DSP1DRC_KNEE2_IP_WIDTH 5 /* DSP1DRC_KNEE2_IP - [9:5] */ 2497*4882a593Smuzhiyun #define WM8996_DSP1DRC_KNEE2_OP_MASK 0x001F /* DSP1DRC_KNEE2_OP - [4:0] */ 2498*4882a593Smuzhiyun #define WM8996_DSP1DRC_KNEE2_OP_SHIFT 0 /* DSP1DRC_KNEE2_OP - [4:0] */ 2499*4882a593Smuzhiyun #define WM8996_DSP1DRC_KNEE2_OP_WIDTH 5 /* DSP1DRC_KNEE2_OP - [4:0] */ 2500*4882a593Smuzhiyun 2501*4882a593Smuzhiyun /* 2502*4882a593Smuzhiyun * R1152 (0x480) - DSP1 RX EQ Gains (1) 2503*4882a593Smuzhiyun */ 2504*4882a593Smuzhiyun #define WM8996_DSP1RX_EQ_B1_GAIN_MASK 0xF800 /* DSP1RX_EQ_B1_GAIN - [15:11] */ 2505*4882a593Smuzhiyun #define WM8996_DSP1RX_EQ_B1_GAIN_SHIFT 11 /* DSP1RX_EQ_B1_GAIN - [15:11] */ 2506*4882a593Smuzhiyun #define WM8996_DSP1RX_EQ_B1_GAIN_WIDTH 5 /* DSP1RX_EQ_B1_GAIN - [15:11] */ 2507*4882a593Smuzhiyun #define WM8996_DSP1RX_EQ_B2_GAIN_MASK 0x07C0 /* DSP1RX_EQ_B2_GAIN - [10:6] */ 2508*4882a593Smuzhiyun #define WM8996_DSP1RX_EQ_B2_GAIN_SHIFT 6 /* DSP1RX_EQ_B2_GAIN - [10:6] */ 2509*4882a593Smuzhiyun #define WM8996_DSP1RX_EQ_B2_GAIN_WIDTH 5 /* DSP1RX_EQ_B2_GAIN - [10:6] */ 2510*4882a593Smuzhiyun #define WM8996_DSP1RX_EQ_B3_GAIN_MASK 0x003E /* DSP1RX_EQ_B3_GAIN - [5:1] */ 2511*4882a593Smuzhiyun #define WM8996_DSP1RX_EQ_B3_GAIN_SHIFT 1 /* DSP1RX_EQ_B3_GAIN - [5:1] */ 2512*4882a593Smuzhiyun #define WM8996_DSP1RX_EQ_B3_GAIN_WIDTH 5 /* DSP1RX_EQ_B3_GAIN - [5:1] */ 2513*4882a593Smuzhiyun #define WM8996_DSP1RX_EQ_ENA 0x0001 /* DSP1RX_EQ_ENA */ 2514*4882a593Smuzhiyun #define WM8996_DSP1RX_EQ_ENA_MASK 0x0001 /* DSP1RX_EQ_ENA */ 2515*4882a593Smuzhiyun #define WM8996_DSP1RX_EQ_ENA_SHIFT 0 /* DSP1RX_EQ_ENA */ 2516*4882a593Smuzhiyun #define WM8996_DSP1RX_EQ_ENA_WIDTH 1 /* DSP1RX_EQ_ENA */ 2517*4882a593Smuzhiyun 2518*4882a593Smuzhiyun /* 2519*4882a593Smuzhiyun * R1153 (0x481) - DSP1 RX EQ Gains (2) 2520*4882a593Smuzhiyun */ 2521*4882a593Smuzhiyun #define WM8996_DSP1RX_EQ_B4_GAIN_MASK 0xF800 /* DSP1RX_EQ_B4_GAIN - [15:11] */ 2522*4882a593Smuzhiyun #define WM8996_DSP1RX_EQ_B4_GAIN_SHIFT 11 /* DSP1RX_EQ_B4_GAIN - [15:11] */ 2523*4882a593Smuzhiyun #define WM8996_DSP1RX_EQ_B4_GAIN_WIDTH 5 /* DSP1RX_EQ_B4_GAIN - [15:11] */ 2524*4882a593Smuzhiyun #define WM8996_DSP1RX_EQ_B5_GAIN_MASK 0x07C0 /* DSP1RX_EQ_B5_GAIN - [10:6] */ 2525*4882a593Smuzhiyun #define WM8996_DSP1RX_EQ_B5_GAIN_SHIFT 6 /* DSP1RX_EQ_B5_GAIN - [10:6] */ 2526*4882a593Smuzhiyun #define WM8996_DSP1RX_EQ_B5_GAIN_WIDTH 5 /* DSP1RX_EQ_B5_GAIN - [10:6] */ 2527*4882a593Smuzhiyun 2528*4882a593Smuzhiyun /* 2529*4882a593Smuzhiyun * R1154 (0x482) - DSP1 RX EQ Band 1 A 2530*4882a593Smuzhiyun */ 2531*4882a593Smuzhiyun #define WM8996_DSP1RX_EQ_B1_A_MASK 0xFFFF /* DSP1RX_EQ_B1_A - [15:0] */ 2532*4882a593Smuzhiyun #define WM8996_DSP1RX_EQ_B1_A_SHIFT 0 /* DSP1RX_EQ_B1_A - [15:0] */ 2533*4882a593Smuzhiyun #define WM8996_DSP1RX_EQ_B1_A_WIDTH 16 /* DSP1RX_EQ_B1_A - [15:0] */ 2534*4882a593Smuzhiyun 2535*4882a593Smuzhiyun /* 2536*4882a593Smuzhiyun * R1155 (0x483) - DSP1 RX EQ Band 1 B 2537*4882a593Smuzhiyun */ 2538*4882a593Smuzhiyun #define WM8996_DSP1RX_EQ_B1_B_MASK 0xFFFF /* DSP1RX_EQ_B1_B - [15:0] */ 2539*4882a593Smuzhiyun #define WM8996_DSP1RX_EQ_B1_B_SHIFT 0 /* DSP1RX_EQ_B1_B - [15:0] */ 2540*4882a593Smuzhiyun #define WM8996_DSP1RX_EQ_B1_B_WIDTH 16 /* DSP1RX_EQ_B1_B - [15:0] */ 2541*4882a593Smuzhiyun 2542*4882a593Smuzhiyun /* 2543*4882a593Smuzhiyun * R1156 (0x484) - DSP1 RX EQ Band 1 PG 2544*4882a593Smuzhiyun */ 2545*4882a593Smuzhiyun #define WM8996_DSP1RX_EQ_B1_PG_MASK 0xFFFF /* DSP1RX_EQ_B1_PG - [15:0] */ 2546*4882a593Smuzhiyun #define WM8996_DSP1RX_EQ_B1_PG_SHIFT 0 /* DSP1RX_EQ_B1_PG - [15:0] */ 2547*4882a593Smuzhiyun #define WM8996_DSP1RX_EQ_B1_PG_WIDTH 16 /* DSP1RX_EQ_B1_PG - [15:0] */ 2548*4882a593Smuzhiyun 2549*4882a593Smuzhiyun /* 2550*4882a593Smuzhiyun * R1157 (0x485) - DSP1 RX EQ Band 2 A 2551*4882a593Smuzhiyun */ 2552*4882a593Smuzhiyun #define WM8996_DSP1RX_EQ_B2_A_MASK 0xFFFF /* DSP1RX_EQ_B2_A - [15:0] */ 2553*4882a593Smuzhiyun #define WM8996_DSP1RX_EQ_B2_A_SHIFT 0 /* DSP1RX_EQ_B2_A - [15:0] */ 2554*4882a593Smuzhiyun #define WM8996_DSP1RX_EQ_B2_A_WIDTH 16 /* DSP1RX_EQ_B2_A - [15:0] */ 2555*4882a593Smuzhiyun 2556*4882a593Smuzhiyun /* 2557*4882a593Smuzhiyun * R1158 (0x486) - DSP1 RX EQ Band 2 B 2558*4882a593Smuzhiyun */ 2559*4882a593Smuzhiyun #define WM8996_DSP1RX_EQ_B2_B_MASK 0xFFFF /* DSP1RX_EQ_B2_B - [15:0] */ 2560*4882a593Smuzhiyun #define WM8996_DSP1RX_EQ_B2_B_SHIFT 0 /* DSP1RX_EQ_B2_B - [15:0] */ 2561*4882a593Smuzhiyun #define WM8996_DSP1RX_EQ_B2_B_WIDTH 16 /* DSP1RX_EQ_B2_B - [15:0] */ 2562*4882a593Smuzhiyun 2563*4882a593Smuzhiyun /* 2564*4882a593Smuzhiyun * R1159 (0x487) - DSP1 RX EQ Band 2 C 2565*4882a593Smuzhiyun */ 2566*4882a593Smuzhiyun #define WM8996_DSP1RX_EQ_B2_C_MASK 0xFFFF /* DSP1RX_EQ_B2_C - [15:0] */ 2567*4882a593Smuzhiyun #define WM8996_DSP1RX_EQ_B2_C_SHIFT 0 /* DSP1RX_EQ_B2_C - [15:0] */ 2568*4882a593Smuzhiyun #define WM8996_DSP1RX_EQ_B2_C_WIDTH 16 /* DSP1RX_EQ_B2_C - [15:0] */ 2569*4882a593Smuzhiyun 2570*4882a593Smuzhiyun /* 2571*4882a593Smuzhiyun * R1160 (0x488) - DSP1 RX EQ Band 2 PG 2572*4882a593Smuzhiyun */ 2573*4882a593Smuzhiyun #define WM8996_DSP1RX_EQ_B2_PG_MASK 0xFFFF /* DSP1RX_EQ_B2_PG - [15:0] */ 2574*4882a593Smuzhiyun #define WM8996_DSP1RX_EQ_B2_PG_SHIFT 0 /* DSP1RX_EQ_B2_PG - [15:0] */ 2575*4882a593Smuzhiyun #define WM8996_DSP1RX_EQ_B2_PG_WIDTH 16 /* DSP1RX_EQ_B2_PG - [15:0] */ 2576*4882a593Smuzhiyun 2577*4882a593Smuzhiyun /* 2578*4882a593Smuzhiyun * R1161 (0x489) - DSP1 RX EQ Band 3 A 2579*4882a593Smuzhiyun */ 2580*4882a593Smuzhiyun #define WM8996_DSP1RX_EQ_B3_A_MASK 0xFFFF /* DSP1RX_EQ_B3_A - [15:0] */ 2581*4882a593Smuzhiyun #define WM8996_DSP1RX_EQ_B3_A_SHIFT 0 /* DSP1RX_EQ_B3_A - [15:0] */ 2582*4882a593Smuzhiyun #define WM8996_DSP1RX_EQ_B3_A_WIDTH 16 /* DSP1RX_EQ_B3_A - [15:0] */ 2583*4882a593Smuzhiyun 2584*4882a593Smuzhiyun /* 2585*4882a593Smuzhiyun * R1162 (0x48A) - DSP1 RX EQ Band 3 B 2586*4882a593Smuzhiyun */ 2587*4882a593Smuzhiyun #define WM8996_DSP1RX_EQ_B3_B_MASK 0xFFFF /* DSP1RX_EQ_B3_B - [15:0] */ 2588*4882a593Smuzhiyun #define WM8996_DSP1RX_EQ_B3_B_SHIFT 0 /* DSP1RX_EQ_B3_B - [15:0] */ 2589*4882a593Smuzhiyun #define WM8996_DSP1RX_EQ_B3_B_WIDTH 16 /* DSP1RX_EQ_B3_B - [15:0] */ 2590*4882a593Smuzhiyun 2591*4882a593Smuzhiyun /* 2592*4882a593Smuzhiyun * R1163 (0x48B) - DSP1 RX EQ Band 3 C 2593*4882a593Smuzhiyun */ 2594*4882a593Smuzhiyun #define WM8996_DSP1RX_EQ_B3_C_MASK 0xFFFF /* DSP1RX_EQ_B3_C - [15:0] */ 2595*4882a593Smuzhiyun #define WM8996_DSP1RX_EQ_B3_C_SHIFT 0 /* DSP1RX_EQ_B3_C - [15:0] */ 2596*4882a593Smuzhiyun #define WM8996_DSP1RX_EQ_B3_C_WIDTH 16 /* DSP1RX_EQ_B3_C - [15:0] */ 2597*4882a593Smuzhiyun 2598*4882a593Smuzhiyun /* 2599*4882a593Smuzhiyun * R1164 (0x48C) - DSP1 RX EQ Band 3 PG 2600*4882a593Smuzhiyun */ 2601*4882a593Smuzhiyun #define WM8996_DSP1RX_EQ_B3_PG_MASK 0xFFFF /* DSP1RX_EQ_B3_PG - [15:0] */ 2602*4882a593Smuzhiyun #define WM8996_DSP1RX_EQ_B3_PG_SHIFT 0 /* DSP1RX_EQ_B3_PG - [15:0] */ 2603*4882a593Smuzhiyun #define WM8996_DSP1RX_EQ_B3_PG_WIDTH 16 /* DSP1RX_EQ_B3_PG - [15:0] */ 2604*4882a593Smuzhiyun 2605*4882a593Smuzhiyun /* 2606*4882a593Smuzhiyun * R1165 (0x48D) - DSP1 RX EQ Band 4 A 2607*4882a593Smuzhiyun */ 2608*4882a593Smuzhiyun #define WM8996_DSP1RX_EQ_B4_A_MASK 0xFFFF /* DSP1RX_EQ_B4_A - [15:0] */ 2609*4882a593Smuzhiyun #define WM8996_DSP1RX_EQ_B4_A_SHIFT 0 /* DSP1RX_EQ_B4_A - [15:0] */ 2610*4882a593Smuzhiyun #define WM8996_DSP1RX_EQ_B4_A_WIDTH 16 /* DSP1RX_EQ_B4_A - [15:0] */ 2611*4882a593Smuzhiyun 2612*4882a593Smuzhiyun /* 2613*4882a593Smuzhiyun * R1166 (0x48E) - DSP1 RX EQ Band 4 B 2614*4882a593Smuzhiyun */ 2615*4882a593Smuzhiyun #define WM8996_DSP1RX_EQ_B4_B_MASK 0xFFFF /* DSP1RX_EQ_B4_B - [15:0] */ 2616*4882a593Smuzhiyun #define WM8996_DSP1RX_EQ_B4_B_SHIFT 0 /* DSP1RX_EQ_B4_B - [15:0] */ 2617*4882a593Smuzhiyun #define WM8996_DSP1RX_EQ_B4_B_WIDTH 16 /* DSP1RX_EQ_B4_B - [15:0] */ 2618*4882a593Smuzhiyun 2619*4882a593Smuzhiyun /* 2620*4882a593Smuzhiyun * R1167 (0x48F) - DSP1 RX EQ Band 4 C 2621*4882a593Smuzhiyun */ 2622*4882a593Smuzhiyun #define WM8996_DSP1RX_EQ_B4_C_MASK 0xFFFF /* DSP1RX_EQ_B4_C - [15:0] */ 2623*4882a593Smuzhiyun #define WM8996_DSP1RX_EQ_B4_C_SHIFT 0 /* DSP1RX_EQ_B4_C - [15:0] */ 2624*4882a593Smuzhiyun #define WM8996_DSP1RX_EQ_B4_C_WIDTH 16 /* DSP1RX_EQ_B4_C - [15:0] */ 2625*4882a593Smuzhiyun 2626*4882a593Smuzhiyun /* 2627*4882a593Smuzhiyun * R1168 (0x490) - DSP1 RX EQ Band 4 PG 2628*4882a593Smuzhiyun */ 2629*4882a593Smuzhiyun #define WM8996_DSP1RX_EQ_B4_PG_MASK 0xFFFF /* DSP1RX_EQ_B4_PG - [15:0] */ 2630*4882a593Smuzhiyun #define WM8996_DSP1RX_EQ_B4_PG_SHIFT 0 /* DSP1RX_EQ_B4_PG - [15:0] */ 2631*4882a593Smuzhiyun #define WM8996_DSP1RX_EQ_B4_PG_WIDTH 16 /* DSP1RX_EQ_B4_PG - [15:0] */ 2632*4882a593Smuzhiyun 2633*4882a593Smuzhiyun /* 2634*4882a593Smuzhiyun * R1169 (0x491) - DSP1 RX EQ Band 5 A 2635*4882a593Smuzhiyun */ 2636*4882a593Smuzhiyun #define WM8996_DSP1RX_EQ_B5_A_MASK 0xFFFF /* DSP1RX_EQ_B5_A - [15:0] */ 2637*4882a593Smuzhiyun #define WM8996_DSP1RX_EQ_B5_A_SHIFT 0 /* DSP1RX_EQ_B5_A - [15:0] */ 2638*4882a593Smuzhiyun #define WM8996_DSP1RX_EQ_B5_A_WIDTH 16 /* DSP1RX_EQ_B5_A - [15:0] */ 2639*4882a593Smuzhiyun 2640*4882a593Smuzhiyun /* 2641*4882a593Smuzhiyun * R1170 (0x492) - DSP1 RX EQ Band 5 B 2642*4882a593Smuzhiyun */ 2643*4882a593Smuzhiyun #define WM8996_DSP1RX_EQ_B5_B_MASK 0xFFFF /* DSP1RX_EQ_B5_B - [15:0] */ 2644*4882a593Smuzhiyun #define WM8996_DSP1RX_EQ_B5_B_SHIFT 0 /* DSP1RX_EQ_B5_B - [15:0] */ 2645*4882a593Smuzhiyun #define WM8996_DSP1RX_EQ_B5_B_WIDTH 16 /* DSP1RX_EQ_B5_B - [15:0] */ 2646*4882a593Smuzhiyun 2647*4882a593Smuzhiyun /* 2648*4882a593Smuzhiyun * R1171 (0x493) - DSP1 RX EQ Band 5 PG 2649*4882a593Smuzhiyun */ 2650*4882a593Smuzhiyun #define WM8996_DSP1RX_EQ_B5_PG_MASK 0xFFFF /* DSP1RX_EQ_B5_PG - [15:0] */ 2651*4882a593Smuzhiyun #define WM8996_DSP1RX_EQ_B5_PG_SHIFT 0 /* DSP1RX_EQ_B5_PG - [15:0] */ 2652*4882a593Smuzhiyun #define WM8996_DSP1RX_EQ_B5_PG_WIDTH 16 /* DSP1RX_EQ_B5_PG - [15:0] */ 2653*4882a593Smuzhiyun 2654*4882a593Smuzhiyun /* 2655*4882a593Smuzhiyun * R1280 (0x500) - DSP2 TX Left Volume 2656*4882a593Smuzhiyun */ 2657*4882a593Smuzhiyun #define WM8996_DSP2TX_VU 0x0100 /* DSP2TX_VU */ 2658*4882a593Smuzhiyun #define WM8996_DSP2TX_VU_MASK 0x0100 /* DSP2TX_VU */ 2659*4882a593Smuzhiyun #define WM8996_DSP2TX_VU_SHIFT 8 /* DSP2TX_VU */ 2660*4882a593Smuzhiyun #define WM8996_DSP2TX_VU_WIDTH 1 /* DSP2TX_VU */ 2661*4882a593Smuzhiyun #define WM8996_DSP2TXL_VOL_MASK 0x00FF /* DSP2TXL_VOL - [7:0] */ 2662*4882a593Smuzhiyun #define WM8996_DSP2TXL_VOL_SHIFT 0 /* DSP2TXL_VOL - [7:0] */ 2663*4882a593Smuzhiyun #define WM8996_DSP2TXL_VOL_WIDTH 8 /* DSP2TXL_VOL - [7:0] */ 2664*4882a593Smuzhiyun 2665*4882a593Smuzhiyun /* 2666*4882a593Smuzhiyun * R1281 (0x501) - DSP2 TX Right Volume 2667*4882a593Smuzhiyun */ 2668*4882a593Smuzhiyun #define WM8996_DSP2TX_VU 0x0100 /* DSP2TX_VU */ 2669*4882a593Smuzhiyun #define WM8996_DSP2TX_VU_MASK 0x0100 /* DSP2TX_VU */ 2670*4882a593Smuzhiyun #define WM8996_DSP2TX_VU_SHIFT 8 /* DSP2TX_VU */ 2671*4882a593Smuzhiyun #define WM8996_DSP2TX_VU_WIDTH 1 /* DSP2TX_VU */ 2672*4882a593Smuzhiyun #define WM8996_DSP2TXR_VOL_MASK 0x00FF /* DSP2TXR_VOL - [7:0] */ 2673*4882a593Smuzhiyun #define WM8996_DSP2TXR_VOL_SHIFT 0 /* DSP2TXR_VOL - [7:0] */ 2674*4882a593Smuzhiyun #define WM8996_DSP2TXR_VOL_WIDTH 8 /* DSP2TXR_VOL - [7:0] */ 2675*4882a593Smuzhiyun 2676*4882a593Smuzhiyun /* 2677*4882a593Smuzhiyun * R1282 (0x502) - DSP2 RX Left Volume 2678*4882a593Smuzhiyun */ 2679*4882a593Smuzhiyun #define WM8996_DSP2RX_VU 0x0100 /* DSP2RX_VU */ 2680*4882a593Smuzhiyun #define WM8996_DSP2RX_VU_MASK 0x0100 /* DSP2RX_VU */ 2681*4882a593Smuzhiyun #define WM8996_DSP2RX_VU_SHIFT 8 /* DSP2RX_VU */ 2682*4882a593Smuzhiyun #define WM8996_DSP2RX_VU_WIDTH 1 /* DSP2RX_VU */ 2683*4882a593Smuzhiyun #define WM8996_DSP2RXL_VOL_MASK 0x00FF /* DSP2RXL_VOL - [7:0] */ 2684*4882a593Smuzhiyun #define WM8996_DSP2RXL_VOL_SHIFT 0 /* DSP2RXL_VOL - [7:0] */ 2685*4882a593Smuzhiyun #define WM8996_DSP2RXL_VOL_WIDTH 8 /* DSP2RXL_VOL - [7:0] */ 2686*4882a593Smuzhiyun 2687*4882a593Smuzhiyun /* 2688*4882a593Smuzhiyun * R1283 (0x503) - DSP2 RX Right Volume 2689*4882a593Smuzhiyun */ 2690*4882a593Smuzhiyun #define WM8996_DSP2RX_VU 0x0100 /* DSP2RX_VU */ 2691*4882a593Smuzhiyun #define WM8996_DSP2RX_VU_MASK 0x0100 /* DSP2RX_VU */ 2692*4882a593Smuzhiyun #define WM8996_DSP2RX_VU_SHIFT 8 /* DSP2RX_VU */ 2693*4882a593Smuzhiyun #define WM8996_DSP2RX_VU_WIDTH 1 /* DSP2RX_VU */ 2694*4882a593Smuzhiyun #define WM8996_DSP2RXR_VOL_MASK 0x00FF /* DSP2RXR_VOL - [7:0] */ 2695*4882a593Smuzhiyun #define WM8996_DSP2RXR_VOL_SHIFT 0 /* DSP2RXR_VOL - [7:0] */ 2696*4882a593Smuzhiyun #define WM8996_DSP2RXR_VOL_WIDTH 8 /* DSP2RXR_VOL - [7:0] */ 2697*4882a593Smuzhiyun 2698*4882a593Smuzhiyun /* 2699*4882a593Smuzhiyun * R1296 (0x510) - DSP2 TX Filters 2700*4882a593Smuzhiyun */ 2701*4882a593Smuzhiyun #define WM8996_DSP2TX_NF 0x2000 /* DSP2TX_NF */ 2702*4882a593Smuzhiyun #define WM8996_DSP2TX_NF_MASK 0x2000 /* DSP2TX_NF */ 2703*4882a593Smuzhiyun #define WM8996_DSP2TX_NF_SHIFT 13 /* DSP2TX_NF */ 2704*4882a593Smuzhiyun #define WM8996_DSP2TX_NF_WIDTH 1 /* DSP2TX_NF */ 2705*4882a593Smuzhiyun #define WM8996_DSP2TXL_HPF 0x1000 /* DSP2TXL_HPF */ 2706*4882a593Smuzhiyun #define WM8996_DSP2TXL_HPF_MASK 0x1000 /* DSP2TXL_HPF */ 2707*4882a593Smuzhiyun #define WM8996_DSP2TXL_HPF_SHIFT 12 /* DSP2TXL_HPF */ 2708*4882a593Smuzhiyun #define WM8996_DSP2TXL_HPF_WIDTH 1 /* DSP2TXL_HPF */ 2709*4882a593Smuzhiyun #define WM8996_DSP2TXR_HPF 0x0800 /* DSP2TXR_HPF */ 2710*4882a593Smuzhiyun #define WM8996_DSP2TXR_HPF_MASK 0x0800 /* DSP2TXR_HPF */ 2711*4882a593Smuzhiyun #define WM8996_DSP2TXR_HPF_SHIFT 11 /* DSP2TXR_HPF */ 2712*4882a593Smuzhiyun #define WM8996_DSP2TXR_HPF_WIDTH 1 /* DSP2TXR_HPF */ 2713*4882a593Smuzhiyun #define WM8996_DSP2TX_HPF_MODE_MASK 0x0018 /* DSP2TX_HPF_MODE - [4:3] */ 2714*4882a593Smuzhiyun #define WM8996_DSP2TX_HPF_MODE_SHIFT 3 /* DSP2TX_HPF_MODE - [4:3] */ 2715*4882a593Smuzhiyun #define WM8996_DSP2TX_HPF_MODE_WIDTH 2 /* DSP2TX_HPF_MODE - [4:3] */ 2716*4882a593Smuzhiyun #define WM8996_DSP2TX_HPF_CUT_MASK 0x0007 /* DSP2TX_HPF_CUT - [2:0] */ 2717*4882a593Smuzhiyun #define WM8996_DSP2TX_HPF_CUT_SHIFT 0 /* DSP2TX_HPF_CUT - [2:0] */ 2718*4882a593Smuzhiyun #define WM8996_DSP2TX_HPF_CUT_WIDTH 3 /* DSP2TX_HPF_CUT - [2:0] */ 2719*4882a593Smuzhiyun 2720*4882a593Smuzhiyun /* 2721*4882a593Smuzhiyun * R1312 (0x520) - DSP2 RX Filters (1) 2722*4882a593Smuzhiyun */ 2723*4882a593Smuzhiyun #define WM8996_DSP2RX_MUTE 0x0200 /* DSP2RX_MUTE */ 2724*4882a593Smuzhiyun #define WM8996_DSP2RX_MUTE_MASK 0x0200 /* DSP2RX_MUTE */ 2725*4882a593Smuzhiyun #define WM8996_DSP2RX_MUTE_SHIFT 9 /* DSP2RX_MUTE */ 2726*4882a593Smuzhiyun #define WM8996_DSP2RX_MUTE_WIDTH 1 /* DSP2RX_MUTE */ 2727*4882a593Smuzhiyun #define WM8996_DSP2RX_MONO 0x0080 /* DSP2RX_MONO */ 2728*4882a593Smuzhiyun #define WM8996_DSP2RX_MONO_MASK 0x0080 /* DSP2RX_MONO */ 2729*4882a593Smuzhiyun #define WM8996_DSP2RX_MONO_SHIFT 7 /* DSP2RX_MONO */ 2730*4882a593Smuzhiyun #define WM8996_DSP2RX_MONO_WIDTH 1 /* DSP2RX_MONO */ 2731*4882a593Smuzhiyun #define WM8996_DSP2RX_MUTERATE 0x0020 /* DSP2RX_MUTERATE */ 2732*4882a593Smuzhiyun #define WM8996_DSP2RX_MUTERATE_MASK 0x0020 /* DSP2RX_MUTERATE */ 2733*4882a593Smuzhiyun #define WM8996_DSP2RX_MUTERATE_SHIFT 5 /* DSP2RX_MUTERATE */ 2734*4882a593Smuzhiyun #define WM8996_DSP2RX_MUTERATE_WIDTH 1 /* DSP2RX_MUTERATE */ 2735*4882a593Smuzhiyun #define WM8996_DSP2RX_UNMUTE_RAMP 0x0010 /* DSP2RX_UNMUTE_RAMP */ 2736*4882a593Smuzhiyun #define WM8996_DSP2RX_UNMUTE_RAMP_MASK 0x0010 /* DSP2RX_UNMUTE_RAMP */ 2737*4882a593Smuzhiyun #define WM8996_DSP2RX_UNMUTE_RAMP_SHIFT 4 /* DSP2RX_UNMUTE_RAMP */ 2738*4882a593Smuzhiyun #define WM8996_DSP2RX_UNMUTE_RAMP_WIDTH 1 /* DSP2RX_UNMUTE_RAMP */ 2739*4882a593Smuzhiyun 2740*4882a593Smuzhiyun /* 2741*4882a593Smuzhiyun * R1313 (0x521) - DSP2 RX Filters (2) 2742*4882a593Smuzhiyun */ 2743*4882a593Smuzhiyun #define WM8996_DSP2RX_3D_GAIN_MASK 0x3E00 /* DSP2RX_3D_GAIN - [13:9] */ 2744*4882a593Smuzhiyun #define WM8996_DSP2RX_3D_GAIN_SHIFT 9 /* DSP2RX_3D_GAIN - [13:9] */ 2745*4882a593Smuzhiyun #define WM8996_DSP2RX_3D_GAIN_WIDTH 5 /* DSP2RX_3D_GAIN - [13:9] */ 2746*4882a593Smuzhiyun #define WM8996_DSP2RX_3D_ENA 0x0100 /* DSP2RX_3D_ENA */ 2747*4882a593Smuzhiyun #define WM8996_DSP2RX_3D_ENA_MASK 0x0100 /* DSP2RX_3D_ENA */ 2748*4882a593Smuzhiyun #define WM8996_DSP2RX_3D_ENA_SHIFT 8 /* DSP2RX_3D_ENA */ 2749*4882a593Smuzhiyun #define WM8996_DSP2RX_3D_ENA_WIDTH 1 /* DSP2RX_3D_ENA */ 2750*4882a593Smuzhiyun 2751*4882a593Smuzhiyun /* 2752*4882a593Smuzhiyun * R1344 (0x540) - DSP2 DRC (1) 2753*4882a593Smuzhiyun */ 2754*4882a593Smuzhiyun #define WM8996_DSP2DRC_SIG_DET_RMS_MASK 0xF800 /* DSP2DRC_SIG_DET_RMS - [15:11] */ 2755*4882a593Smuzhiyun #define WM8996_DSP2DRC_SIG_DET_RMS_SHIFT 11 /* DSP2DRC_SIG_DET_RMS - [15:11] */ 2756*4882a593Smuzhiyun #define WM8996_DSP2DRC_SIG_DET_RMS_WIDTH 5 /* DSP2DRC_SIG_DET_RMS - [15:11] */ 2757*4882a593Smuzhiyun #define WM8996_DSP2DRC_SIG_DET_PK_MASK 0x0600 /* DSP2DRC_SIG_DET_PK - [10:9] */ 2758*4882a593Smuzhiyun #define WM8996_DSP2DRC_SIG_DET_PK_SHIFT 9 /* DSP2DRC_SIG_DET_PK - [10:9] */ 2759*4882a593Smuzhiyun #define WM8996_DSP2DRC_SIG_DET_PK_WIDTH 2 /* DSP2DRC_SIG_DET_PK - [10:9] */ 2760*4882a593Smuzhiyun #define WM8996_DSP2DRC_NG_ENA 0x0100 /* DSP2DRC_NG_ENA */ 2761*4882a593Smuzhiyun #define WM8996_DSP2DRC_NG_ENA_MASK 0x0100 /* DSP2DRC_NG_ENA */ 2762*4882a593Smuzhiyun #define WM8996_DSP2DRC_NG_ENA_SHIFT 8 /* DSP2DRC_NG_ENA */ 2763*4882a593Smuzhiyun #define WM8996_DSP2DRC_NG_ENA_WIDTH 1 /* DSP2DRC_NG_ENA */ 2764*4882a593Smuzhiyun #define WM8996_DSP2DRC_SIG_DET_MODE 0x0080 /* DSP2DRC_SIG_DET_MODE */ 2765*4882a593Smuzhiyun #define WM8996_DSP2DRC_SIG_DET_MODE_MASK 0x0080 /* DSP2DRC_SIG_DET_MODE */ 2766*4882a593Smuzhiyun #define WM8996_DSP2DRC_SIG_DET_MODE_SHIFT 7 /* DSP2DRC_SIG_DET_MODE */ 2767*4882a593Smuzhiyun #define WM8996_DSP2DRC_SIG_DET_MODE_WIDTH 1 /* DSP2DRC_SIG_DET_MODE */ 2768*4882a593Smuzhiyun #define WM8996_DSP2DRC_SIG_DET 0x0040 /* DSP2DRC_SIG_DET */ 2769*4882a593Smuzhiyun #define WM8996_DSP2DRC_SIG_DET_MASK 0x0040 /* DSP2DRC_SIG_DET */ 2770*4882a593Smuzhiyun #define WM8996_DSP2DRC_SIG_DET_SHIFT 6 /* DSP2DRC_SIG_DET */ 2771*4882a593Smuzhiyun #define WM8996_DSP2DRC_SIG_DET_WIDTH 1 /* DSP2DRC_SIG_DET */ 2772*4882a593Smuzhiyun #define WM8996_DSP2DRC_KNEE2_OP_ENA 0x0020 /* DSP2DRC_KNEE2_OP_ENA */ 2773*4882a593Smuzhiyun #define WM8996_DSP2DRC_KNEE2_OP_ENA_MASK 0x0020 /* DSP2DRC_KNEE2_OP_ENA */ 2774*4882a593Smuzhiyun #define WM8996_DSP2DRC_KNEE2_OP_ENA_SHIFT 5 /* DSP2DRC_KNEE2_OP_ENA */ 2775*4882a593Smuzhiyun #define WM8996_DSP2DRC_KNEE2_OP_ENA_WIDTH 1 /* DSP2DRC_KNEE2_OP_ENA */ 2776*4882a593Smuzhiyun #define WM8996_DSP2DRC_QR 0x0010 /* DSP2DRC_QR */ 2777*4882a593Smuzhiyun #define WM8996_DSP2DRC_QR_MASK 0x0010 /* DSP2DRC_QR */ 2778*4882a593Smuzhiyun #define WM8996_DSP2DRC_QR_SHIFT 4 /* DSP2DRC_QR */ 2779*4882a593Smuzhiyun #define WM8996_DSP2DRC_QR_WIDTH 1 /* DSP2DRC_QR */ 2780*4882a593Smuzhiyun #define WM8996_DSP2DRC_ANTICLIP 0x0008 /* DSP2DRC_ANTICLIP */ 2781*4882a593Smuzhiyun #define WM8996_DSP2DRC_ANTICLIP_MASK 0x0008 /* DSP2DRC_ANTICLIP */ 2782*4882a593Smuzhiyun #define WM8996_DSP2DRC_ANTICLIP_SHIFT 3 /* DSP2DRC_ANTICLIP */ 2783*4882a593Smuzhiyun #define WM8996_DSP2DRC_ANTICLIP_WIDTH 1 /* DSP2DRC_ANTICLIP */ 2784*4882a593Smuzhiyun #define WM8996_DSP2RX_DRC_ENA 0x0004 /* DSP2RX_DRC_ENA */ 2785*4882a593Smuzhiyun #define WM8996_DSP2RX_DRC_ENA_MASK 0x0004 /* DSP2RX_DRC_ENA */ 2786*4882a593Smuzhiyun #define WM8996_DSP2RX_DRC_ENA_SHIFT 2 /* DSP2RX_DRC_ENA */ 2787*4882a593Smuzhiyun #define WM8996_DSP2RX_DRC_ENA_WIDTH 1 /* DSP2RX_DRC_ENA */ 2788*4882a593Smuzhiyun #define WM8996_DSP2TXL_DRC_ENA 0x0002 /* DSP2TXL_DRC_ENA */ 2789*4882a593Smuzhiyun #define WM8996_DSP2TXL_DRC_ENA_MASK 0x0002 /* DSP2TXL_DRC_ENA */ 2790*4882a593Smuzhiyun #define WM8996_DSP2TXL_DRC_ENA_SHIFT 1 /* DSP2TXL_DRC_ENA */ 2791*4882a593Smuzhiyun #define WM8996_DSP2TXL_DRC_ENA_WIDTH 1 /* DSP2TXL_DRC_ENA */ 2792*4882a593Smuzhiyun #define WM8996_DSP2TXR_DRC_ENA 0x0001 /* DSP2TXR_DRC_ENA */ 2793*4882a593Smuzhiyun #define WM8996_DSP2TXR_DRC_ENA_MASK 0x0001 /* DSP2TXR_DRC_ENA */ 2794*4882a593Smuzhiyun #define WM8996_DSP2TXR_DRC_ENA_SHIFT 0 /* DSP2TXR_DRC_ENA */ 2795*4882a593Smuzhiyun #define WM8996_DSP2TXR_DRC_ENA_WIDTH 1 /* DSP2TXR_DRC_ENA */ 2796*4882a593Smuzhiyun 2797*4882a593Smuzhiyun /* 2798*4882a593Smuzhiyun * R1345 (0x541) - DSP2 DRC (2) 2799*4882a593Smuzhiyun */ 2800*4882a593Smuzhiyun #define WM8996_DSP2DRC_ATK_MASK 0x1E00 /* DSP2DRC_ATK - [12:9] */ 2801*4882a593Smuzhiyun #define WM8996_DSP2DRC_ATK_SHIFT 9 /* DSP2DRC_ATK - [12:9] */ 2802*4882a593Smuzhiyun #define WM8996_DSP2DRC_ATK_WIDTH 4 /* DSP2DRC_ATK - [12:9] */ 2803*4882a593Smuzhiyun #define WM8996_DSP2DRC_DCY_MASK 0x01E0 /* DSP2DRC_DCY - [8:5] */ 2804*4882a593Smuzhiyun #define WM8996_DSP2DRC_DCY_SHIFT 5 /* DSP2DRC_DCY - [8:5] */ 2805*4882a593Smuzhiyun #define WM8996_DSP2DRC_DCY_WIDTH 4 /* DSP2DRC_DCY - [8:5] */ 2806*4882a593Smuzhiyun #define WM8996_DSP2DRC_MINGAIN_MASK 0x001C /* DSP2DRC_MINGAIN - [4:2] */ 2807*4882a593Smuzhiyun #define WM8996_DSP2DRC_MINGAIN_SHIFT 2 /* DSP2DRC_MINGAIN - [4:2] */ 2808*4882a593Smuzhiyun #define WM8996_DSP2DRC_MINGAIN_WIDTH 3 /* DSP2DRC_MINGAIN - [4:2] */ 2809*4882a593Smuzhiyun #define WM8996_DSP2DRC_MAXGAIN_MASK 0x0003 /* DSP2DRC_MAXGAIN - [1:0] */ 2810*4882a593Smuzhiyun #define WM8996_DSP2DRC_MAXGAIN_SHIFT 0 /* DSP2DRC_MAXGAIN - [1:0] */ 2811*4882a593Smuzhiyun #define WM8996_DSP2DRC_MAXGAIN_WIDTH 2 /* DSP2DRC_MAXGAIN - [1:0] */ 2812*4882a593Smuzhiyun 2813*4882a593Smuzhiyun /* 2814*4882a593Smuzhiyun * R1346 (0x542) - DSP2 DRC (3) 2815*4882a593Smuzhiyun */ 2816*4882a593Smuzhiyun #define WM8996_DSP2DRC_NG_MINGAIN_MASK 0xF000 /* DSP2DRC_NG_MINGAIN - [15:12] */ 2817*4882a593Smuzhiyun #define WM8996_DSP2DRC_NG_MINGAIN_SHIFT 12 /* DSP2DRC_NG_MINGAIN - [15:12] */ 2818*4882a593Smuzhiyun #define WM8996_DSP2DRC_NG_MINGAIN_WIDTH 4 /* DSP2DRC_NG_MINGAIN - [15:12] */ 2819*4882a593Smuzhiyun #define WM8996_DSP2DRC_NG_EXP_MASK 0x0C00 /* DSP2DRC_NG_EXP - [11:10] */ 2820*4882a593Smuzhiyun #define WM8996_DSP2DRC_NG_EXP_SHIFT 10 /* DSP2DRC_NG_EXP - [11:10] */ 2821*4882a593Smuzhiyun #define WM8996_DSP2DRC_NG_EXP_WIDTH 2 /* DSP2DRC_NG_EXP - [11:10] */ 2822*4882a593Smuzhiyun #define WM8996_DSP2DRC_QR_THR_MASK 0x0300 /* DSP2DRC_QR_THR - [9:8] */ 2823*4882a593Smuzhiyun #define WM8996_DSP2DRC_QR_THR_SHIFT 8 /* DSP2DRC_QR_THR - [9:8] */ 2824*4882a593Smuzhiyun #define WM8996_DSP2DRC_QR_THR_WIDTH 2 /* DSP2DRC_QR_THR - [9:8] */ 2825*4882a593Smuzhiyun #define WM8996_DSP2DRC_QR_DCY_MASK 0x00C0 /* DSP2DRC_QR_DCY - [7:6] */ 2826*4882a593Smuzhiyun #define WM8996_DSP2DRC_QR_DCY_SHIFT 6 /* DSP2DRC_QR_DCY - [7:6] */ 2827*4882a593Smuzhiyun #define WM8996_DSP2DRC_QR_DCY_WIDTH 2 /* DSP2DRC_QR_DCY - [7:6] */ 2828*4882a593Smuzhiyun #define WM8996_DSP2DRC_HI_COMP_MASK 0x0038 /* DSP2DRC_HI_COMP - [5:3] */ 2829*4882a593Smuzhiyun #define WM8996_DSP2DRC_HI_COMP_SHIFT 3 /* DSP2DRC_HI_COMP - [5:3] */ 2830*4882a593Smuzhiyun #define WM8996_DSP2DRC_HI_COMP_WIDTH 3 /* DSP2DRC_HI_COMP - [5:3] */ 2831*4882a593Smuzhiyun #define WM8996_DSP2DRC_LO_COMP_MASK 0x0007 /* DSP2DRC_LO_COMP - [2:0] */ 2832*4882a593Smuzhiyun #define WM8996_DSP2DRC_LO_COMP_SHIFT 0 /* DSP2DRC_LO_COMP - [2:0] */ 2833*4882a593Smuzhiyun #define WM8996_DSP2DRC_LO_COMP_WIDTH 3 /* DSP2DRC_LO_COMP - [2:0] */ 2834*4882a593Smuzhiyun 2835*4882a593Smuzhiyun /* 2836*4882a593Smuzhiyun * R1347 (0x543) - DSP2 DRC (4) 2837*4882a593Smuzhiyun */ 2838*4882a593Smuzhiyun #define WM8996_DSP2DRC_KNEE_IP_MASK 0x07E0 /* DSP2DRC_KNEE_IP - [10:5] */ 2839*4882a593Smuzhiyun #define WM8996_DSP2DRC_KNEE_IP_SHIFT 5 /* DSP2DRC_KNEE_IP - [10:5] */ 2840*4882a593Smuzhiyun #define WM8996_DSP2DRC_KNEE_IP_WIDTH 6 /* DSP2DRC_KNEE_IP - [10:5] */ 2841*4882a593Smuzhiyun #define WM8996_DSP2DRC_KNEE_OP_MASK 0x001F /* DSP2DRC_KNEE_OP - [4:0] */ 2842*4882a593Smuzhiyun #define WM8996_DSP2DRC_KNEE_OP_SHIFT 0 /* DSP2DRC_KNEE_OP - [4:0] */ 2843*4882a593Smuzhiyun #define WM8996_DSP2DRC_KNEE_OP_WIDTH 5 /* DSP2DRC_KNEE_OP - [4:0] */ 2844*4882a593Smuzhiyun 2845*4882a593Smuzhiyun /* 2846*4882a593Smuzhiyun * R1348 (0x544) - DSP2 DRC (5) 2847*4882a593Smuzhiyun */ 2848*4882a593Smuzhiyun #define WM8996_DSP2DRC_KNEE2_IP_MASK 0x03E0 /* DSP2DRC_KNEE2_IP - [9:5] */ 2849*4882a593Smuzhiyun #define WM8996_DSP2DRC_KNEE2_IP_SHIFT 5 /* DSP2DRC_KNEE2_IP - [9:5] */ 2850*4882a593Smuzhiyun #define WM8996_DSP2DRC_KNEE2_IP_WIDTH 5 /* DSP2DRC_KNEE2_IP - [9:5] */ 2851*4882a593Smuzhiyun #define WM8996_DSP2DRC_KNEE2_OP_MASK 0x001F /* DSP2DRC_KNEE2_OP - [4:0] */ 2852*4882a593Smuzhiyun #define WM8996_DSP2DRC_KNEE2_OP_SHIFT 0 /* DSP2DRC_KNEE2_OP - [4:0] */ 2853*4882a593Smuzhiyun #define WM8996_DSP2DRC_KNEE2_OP_WIDTH 5 /* DSP2DRC_KNEE2_OP - [4:0] */ 2854*4882a593Smuzhiyun 2855*4882a593Smuzhiyun /* 2856*4882a593Smuzhiyun * R1408 (0x580) - DSP2 RX EQ Gains (1) 2857*4882a593Smuzhiyun */ 2858*4882a593Smuzhiyun #define WM8996_DSP2RX_EQ_B1_GAIN_MASK 0xF800 /* DSP2RX_EQ_B1_GAIN - [15:11] */ 2859*4882a593Smuzhiyun #define WM8996_DSP2RX_EQ_B1_GAIN_SHIFT 11 /* DSP2RX_EQ_B1_GAIN - [15:11] */ 2860*4882a593Smuzhiyun #define WM8996_DSP2RX_EQ_B1_GAIN_WIDTH 5 /* DSP2RX_EQ_B1_GAIN - [15:11] */ 2861*4882a593Smuzhiyun #define WM8996_DSP2RX_EQ_B2_GAIN_MASK 0x07C0 /* DSP2RX_EQ_B2_GAIN - [10:6] */ 2862*4882a593Smuzhiyun #define WM8996_DSP2RX_EQ_B2_GAIN_SHIFT 6 /* DSP2RX_EQ_B2_GAIN - [10:6] */ 2863*4882a593Smuzhiyun #define WM8996_DSP2RX_EQ_B2_GAIN_WIDTH 5 /* DSP2RX_EQ_B2_GAIN - [10:6] */ 2864*4882a593Smuzhiyun #define WM8996_DSP2RX_EQ_B3_GAIN_MASK 0x003E /* DSP2RX_EQ_B3_GAIN - [5:1] */ 2865*4882a593Smuzhiyun #define WM8996_DSP2RX_EQ_B3_GAIN_SHIFT 1 /* DSP2RX_EQ_B3_GAIN - [5:1] */ 2866*4882a593Smuzhiyun #define WM8996_DSP2RX_EQ_B3_GAIN_WIDTH 5 /* DSP2RX_EQ_B3_GAIN - [5:1] */ 2867*4882a593Smuzhiyun #define WM8996_DSP2RX_EQ_ENA 0x0001 /* DSP2RX_EQ_ENA */ 2868*4882a593Smuzhiyun #define WM8996_DSP2RX_EQ_ENA_MASK 0x0001 /* DSP2RX_EQ_ENA */ 2869*4882a593Smuzhiyun #define WM8996_DSP2RX_EQ_ENA_SHIFT 0 /* DSP2RX_EQ_ENA */ 2870*4882a593Smuzhiyun #define WM8996_DSP2RX_EQ_ENA_WIDTH 1 /* DSP2RX_EQ_ENA */ 2871*4882a593Smuzhiyun 2872*4882a593Smuzhiyun /* 2873*4882a593Smuzhiyun * R1409 (0x581) - DSP2 RX EQ Gains (2) 2874*4882a593Smuzhiyun */ 2875*4882a593Smuzhiyun #define WM8996_DSP2RX_EQ_B4_GAIN_MASK 0xF800 /* DSP2RX_EQ_B4_GAIN - [15:11] */ 2876*4882a593Smuzhiyun #define WM8996_DSP2RX_EQ_B4_GAIN_SHIFT 11 /* DSP2RX_EQ_B4_GAIN - [15:11] */ 2877*4882a593Smuzhiyun #define WM8996_DSP2RX_EQ_B4_GAIN_WIDTH 5 /* DSP2RX_EQ_B4_GAIN - [15:11] */ 2878*4882a593Smuzhiyun #define WM8996_DSP2RX_EQ_B5_GAIN_MASK 0x07C0 /* DSP2RX_EQ_B5_GAIN - [10:6] */ 2879*4882a593Smuzhiyun #define WM8996_DSP2RX_EQ_B5_GAIN_SHIFT 6 /* DSP2RX_EQ_B5_GAIN - [10:6] */ 2880*4882a593Smuzhiyun #define WM8996_DSP2RX_EQ_B5_GAIN_WIDTH 5 /* DSP2RX_EQ_B5_GAIN - [10:6] */ 2881*4882a593Smuzhiyun 2882*4882a593Smuzhiyun /* 2883*4882a593Smuzhiyun * R1410 (0x582) - DSP2 RX EQ Band 1 A 2884*4882a593Smuzhiyun */ 2885*4882a593Smuzhiyun #define WM8996_DSP2RX_EQ_B1_A_MASK 0xFFFF /* DSP2RX_EQ_B1_A - [15:0] */ 2886*4882a593Smuzhiyun #define WM8996_DSP2RX_EQ_B1_A_SHIFT 0 /* DSP2RX_EQ_B1_A - [15:0] */ 2887*4882a593Smuzhiyun #define WM8996_DSP2RX_EQ_B1_A_WIDTH 16 /* DSP2RX_EQ_B1_A - [15:0] */ 2888*4882a593Smuzhiyun 2889*4882a593Smuzhiyun /* 2890*4882a593Smuzhiyun * R1411 (0x583) - DSP2 RX EQ Band 1 B 2891*4882a593Smuzhiyun */ 2892*4882a593Smuzhiyun #define WM8996_DSP2RX_EQ_B1_B_MASK 0xFFFF /* DSP2RX_EQ_B1_B - [15:0] */ 2893*4882a593Smuzhiyun #define WM8996_DSP2RX_EQ_B1_B_SHIFT 0 /* DSP2RX_EQ_B1_B - [15:0] */ 2894*4882a593Smuzhiyun #define WM8996_DSP2RX_EQ_B1_B_WIDTH 16 /* DSP2RX_EQ_B1_B - [15:0] */ 2895*4882a593Smuzhiyun 2896*4882a593Smuzhiyun /* 2897*4882a593Smuzhiyun * R1412 (0x584) - DSP2 RX EQ Band 1 PG 2898*4882a593Smuzhiyun */ 2899*4882a593Smuzhiyun #define WM8996_DSP2RX_EQ_B1_PG_MASK 0xFFFF /* DSP2RX_EQ_B1_PG - [15:0] */ 2900*4882a593Smuzhiyun #define WM8996_DSP2RX_EQ_B1_PG_SHIFT 0 /* DSP2RX_EQ_B1_PG - [15:0] */ 2901*4882a593Smuzhiyun #define WM8996_DSP2RX_EQ_B1_PG_WIDTH 16 /* DSP2RX_EQ_B1_PG - [15:0] */ 2902*4882a593Smuzhiyun 2903*4882a593Smuzhiyun /* 2904*4882a593Smuzhiyun * R1413 (0x585) - DSP2 RX EQ Band 2 A 2905*4882a593Smuzhiyun */ 2906*4882a593Smuzhiyun #define WM8996_DSP2RX_EQ_B2_A_MASK 0xFFFF /* DSP2RX_EQ_B2_A - [15:0] */ 2907*4882a593Smuzhiyun #define WM8996_DSP2RX_EQ_B2_A_SHIFT 0 /* DSP2RX_EQ_B2_A - [15:0] */ 2908*4882a593Smuzhiyun #define WM8996_DSP2RX_EQ_B2_A_WIDTH 16 /* DSP2RX_EQ_B2_A - [15:0] */ 2909*4882a593Smuzhiyun 2910*4882a593Smuzhiyun /* 2911*4882a593Smuzhiyun * R1414 (0x586) - DSP2 RX EQ Band 2 B 2912*4882a593Smuzhiyun */ 2913*4882a593Smuzhiyun #define WM8996_DSP2RX_EQ_B2_B_MASK 0xFFFF /* DSP2RX_EQ_B2_B - [15:0] */ 2914*4882a593Smuzhiyun #define WM8996_DSP2RX_EQ_B2_B_SHIFT 0 /* DSP2RX_EQ_B2_B - [15:0] */ 2915*4882a593Smuzhiyun #define WM8996_DSP2RX_EQ_B2_B_WIDTH 16 /* DSP2RX_EQ_B2_B - [15:0] */ 2916*4882a593Smuzhiyun 2917*4882a593Smuzhiyun /* 2918*4882a593Smuzhiyun * R1415 (0x587) - DSP2 RX EQ Band 2 C 2919*4882a593Smuzhiyun */ 2920*4882a593Smuzhiyun #define WM8996_DSP2RX_EQ_B2_C_MASK 0xFFFF /* DSP2RX_EQ_B2_C - [15:0] */ 2921*4882a593Smuzhiyun #define WM8996_DSP2RX_EQ_B2_C_SHIFT 0 /* DSP2RX_EQ_B2_C - [15:0] */ 2922*4882a593Smuzhiyun #define WM8996_DSP2RX_EQ_B2_C_WIDTH 16 /* DSP2RX_EQ_B2_C - [15:0] */ 2923*4882a593Smuzhiyun 2924*4882a593Smuzhiyun /* 2925*4882a593Smuzhiyun * R1416 (0x588) - DSP2 RX EQ Band 2 PG 2926*4882a593Smuzhiyun */ 2927*4882a593Smuzhiyun #define WM8996_DSP2RX_EQ_B2_PG_MASK 0xFFFF /* DSP2RX_EQ_B2_PG - [15:0] */ 2928*4882a593Smuzhiyun #define WM8996_DSP2RX_EQ_B2_PG_SHIFT 0 /* DSP2RX_EQ_B2_PG - [15:0] */ 2929*4882a593Smuzhiyun #define WM8996_DSP2RX_EQ_B2_PG_WIDTH 16 /* DSP2RX_EQ_B2_PG - [15:0] */ 2930*4882a593Smuzhiyun 2931*4882a593Smuzhiyun /* 2932*4882a593Smuzhiyun * R1417 (0x589) - DSP2 RX EQ Band 3 A 2933*4882a593Smuzhiyun */ 2934*4882a593Smuzhiyun #define WM8996_DSP2RX_EQ_B3_A_MASK 0xFFFF /* DSP2RX_EQ_B3_A - [15:0] */ 2935*4882a593Smuzhiyun #define WM8996_DSP2RX_EQ_B3_A_SHIFT 0 /* DSP2RX_EQ_B3_A - [15:0] */ 2936*4882a593Smuzhiyun #define WM8996_DSP2RX_EQ_B3_A_WIDTH 16 /* DSP2RX_EQ_B3_A - [15:0] */ 2937*4882a593Smuzhiyun 2938*4882a593Smuzhiyun /* 2939*4882a593Smuzhiyun * R1418 (0x58A) - DSP2 RX EQ Band 3 B 2940*4882a593Smuzhiyun */ 2941*4882a593Smuzhiyun #define WM8996_DSP2RX_EQ_B3_B_MASK 0xFFFF /* DSP2RX_EQ_B3_B - [15:0] */ 2942*4882a593Smuzhiyun #define WM8996_DSP2RX_EQ_B3_B_SHIFT 0 /* DSP2RX_EQ_B3_B - [15:0] */ 2943*4882a593Smuzhiyun #define WM8996_DSP2RX_EQ_B3_B_WIDTH 16 /* DSP2RX_EQ_B3_B - [15:0] */ 2944*4882a593Smuzhiyun 2945*4882a593Smuzhiyun /* 2946*4882a593Smuzhiyun * R1419 (0x58B) - DSP2 RX EQ Band 3 C 2947*4882a593Smuzhiyun */ 2948*4882a593Smuzhiyun #define WM8996_DSP2RX_EQ_B3_C_MASK 0xFFFF /* DSP2RX_EQ_B3_C - [15:0] */ 2949*4882a593Smuzhiyun #define WM8996_DSP2RX_EQ_B3_C_SHIFT 0 /* DSP2RX_EQ_B3_C - [15:0] */ 2950*4882a593Smuzhiyun #define WM8996_DSP2RX_EQ_B3_C_WIDTH 16 /* DSP2RX_EQ_B3_C - [15:0] */ 2951*4882a593Smuzhiyun 2952*4882a593Smuzhiyun /* 2953*4882a593Smuzhiyun * R1420 (0x58C) - DSP2 RX EQ Band 3 PG 2954*4882a593Smuzhiyun */ 2955*4882a593Smuzhiyun #define WM8996_DSP2RX_EQ_B3_PG_MASK 0xFFFF /* DSP2RX_EQ_B3_PG - [15:0] */ 2956*4882a593Smuzhiyun #define WM8996_DSP2RX_EQ_B3_PG_SHIFT 0 /* DSP2RX_EQ_B3_PG - [15:0] */ 2957*4882a593Smuzhiyun #define WM8996_DSP2RX_EQ_B3_PG_WIDTH 16 /* DSP2RX_EQ_B3_PG - [15:0] */ 2958*4882a593Smuzhiyun 2959*4882a593Smuzhiyun /* 2960*4882a593Smuzhiyun * R1421 (0x58D) - DSP2 RX EQ Band 4 A 2961*4882a593Smuzhiyun */ 2962*4882a593Smuzhiyun #define WM8996_DSP2RX_EQ_B4_A_MASK 0xFFFF /* DSP2RX_EQ_B4_A - [15:0] */ 2963*4882a593Smuzhiyun #define WM8996_DSP2RX_EQ_B4_A_SHIFT 0 /* DSP2RX_EQ_B4_A - [15:0] */ 2964*4882a593Smuzhiyun #define WM8996_DSP2RX_EQ_B4_A_WIDTH 16 /* DSP2RX_EQ_B4_A - [15:0] */ 2965*4882a593Smuzhiyun 2966*4882a593Smuzhiyun /* 2967*4882a593Smuzhiyun * R1422 (0x58E) - DSP2 RX EQ Band 4 B 2968*4882a593Smuzhiyun */ 2969*4882a593Smuzhiyun #define WM8996_DSP2RX_EQ_B4_B_MASK 0xFFFF /* DSP2RX_EQ_B4_B - [15:0] */ 2970*4882a593Smuzhiyun #define WM8996_DSP2RX_EQ_B4_B_SHIFT 0 /* DSP2RX_EQ_B4_B - [15:0] */ 2971*4882a593Smuzhiyun #define WM8996_DSP2RX_EQ_B4_B_WIDTH 16 /* DSP2RX_EQ_B4_B - [15:0] */ 2972*4882a593Smuzhiyun 2973*4882a593Smuzhiyun /* 2974*4882a593Smuzhiyun * R1423 (0x58F) - DSP2 RX EQ Band 4 C 2975*4882a593Smuzhiyun */ 2976*4882a593Smuzhiyun #define WM8996_DSP2RX_EQ_B4_C_MASK 0xFFFF /* DSP2RX_EQ_B4_C - [15:0] */ 2977*4882a593Smuzhiyun #define WM8996_DSP2RX_EQ_B4_C_SHIFT 0 /* DSP2RX_EQ_B4_C - [15:0] */ 2978*4882a593Smuzhiyun #define WM8996_DSP2RX_EQ_B4_C_WIDTH 16 /* DSP2RX_EQ_B4_C - [15:0] */ 2979*4882a593Smuzhiyun 2980*4882a593Smuzhiyun /* 2981*4882a593Smuzhiyun * R1424 (0x590) - DSP2 RX EQ Band 4 PG 2982*4882a593Smuzhiyun */ 2983*4882a593Smuzhiyun #define WM8996_DSP2RX_EQ_B4_PG_MASK 0xFFFF /* DSP2RX_EQ_B4_PG - [15:0] */ 2984*4882a593Smuzhiyun #define WM8996_DSP2RX_EQ_B4_PG_SHIFT 0 /* DSP2RX_EQ_B4_PG - [15:0] */ 2985*4882a593Smuzhiyun #define WM8996_DSP2RX_EQ_B4_PG_WIDTH 16 /* DSP2RX_EQ_B4_PG - [15:0] */ 2986*4882a593Smuzhiyun 2987*4882a593Smuzhiyun /* 2988*4882a593Smuzhiyun * R1425 (0x591) - DSP2 RX EQ Band 5 A 2989*4882a593Smuzhiyun */ 2990*4882a593Smuzhiyun #define WM8996_DSP2RX_EQ_B5_A_MASK 0xFFFF /* DSP2RX_EQ_B5_A - [15:0] */ 2991*4882a593Smuzhiyun #define WM8996_DSP2RX_EQ_B5_A_SHIFT 0 /* DSP2RX_EQ_B5_A - [15:0] */ 2992*4882a593Smuzhiyun #define WM8996_DSP2RX_EQ_B5_A_WIDTH 16 /* DSP2RX_EQ_B5_A - [15:0] */ 2993*4882a593Smuzhiyun 2994*4882a593Smuzhiyun /* 2995*4882a593Smuzhiyun * R1426 (0x592) - DSP2 RX EQ Band 5 B 2996*4882a593Smuzhiyun */ 2997*4882a593Smuzhiyun #define WM8996_DSP2RX_EQ_B5_B_MASK 0xFFFF /* DSP2RX_EQ_B5_B - [15:0] */ 2998*4882a593Smuzhiyun #define WM8996_DSP2RX_EQ_B5_B_SHIFT 0 /* DSP2RX_EQ_B5_B - [15:0] */ 2999*4882a593Smuzhiyun #define WM8996_DSP2RX_EQ_B5_B_WIDTH 16 /* DSP2RX_EQ_B5_B - [15:0] */ 3000*4882a593Smuzhiyun 3001*4882a593Smuzhiyun /* 3002*4882a593Smuzhiyun * R1427 (0x593) - DSP2 RX EQ Band 5 PG 3003*4882a593Smuzhiyun */ 3004*4882a593Smuzhiyun #define WM8996_DSP2RX_EQ_B5_PG_MASK 0xFFFF /* DSP2RX_EQ_B5_PG - [15:0] */ 3005*4882a593Smuzhiyun #define WM8996_DSP2RX_EQ_B5_PG_SHIFT 0 /* DSP2RX_EQ_B5_PG - [15:0] */ 3006*4882a593Smuzhiyun #define WM8996_DSP2RX_EQ_B5_PG_WIDTH 16 /* DSP2RX_EQ_B5_PG - [15:0] */ 3007*4882a593Smuzhiyun 3008*4882a593Smuzhiyun /* 3009*4882a593Smuzhiyun * R1536 (0x600) - DAC1 Mixer Volumes 3010*4882a593Smuzhiyun */ 3011*4882a593Smuzhiyun #define WM8996_ADCR_DAC1_VOL_MASK 0x03E0 /* ADCR_DAC1_VOL - [9:5] */ 3012*4882a593Smuzhiyun #define WM8996_ADCR_DAC1_VOL_SHIFT 5 /* ADCR_DAC1_VOL - [9:5] */ 3013*4882a593Smuzhiyun #define WM8996_ADCR_DAC1_VOL_WIDTH 5 /* ADCR_DAC1_VOL - [9:5] */ 3014*4882a593Smuzhiyun #define WM8996_ADCL_DAC1_VOL_MASK 0x001F /* ADCL_DAC1_VOL - [4:0] */ 3015*4882a593Smuzhiyun #define WM8996_ADCL_DAC1_VOL_SHIFT 0 /* ADCL_DAC1_VOL - [4:0] */ 3016*4882a593Smuzhiyun #define WM8996_ADCL_DAC1_VOL_WIDTH 5 /* ADCL_DAC1_VOL - [4:0] */ 3017*4882a593Smuzhiyun 3018*4882a593Smuzhiyun /* 3019*4882a593Smuzhiyun * R1537 (0x601) - DAC1 Left Mixer Routing 3020*4882a593Smuzhiyun */ 3021*4882a593Smuzhiyun #define WM8996_ADCR_TO_DAC1L 0x0020 /* ADCR_TO_DAC1L */ 3022*4882a593Smuzhiyun #define WM8996_ADCR_TO_DAC1L_MASK 0x0020 /* ADCR_TO_DAC1L */ 3023*4882a593Smuzhiyun #define WM8996_ADCR_TO_DAC1L_SHIFT 5 /* ADCR_TO_DAC1L */ 3024*4882a593Smuzhiyun #define WM8996_ADCR_TO_DAC1L_WIDTH 1 /* ADCR_TO_DAC1L */ 3025*4882a593Smuzhiyun #define WM8996_ADCL_TO_DAC1L 0x0010 /* ADCL_TO_DAC1L */ 3026*4882a593Smuzhiyun #define WM8996_ADCL_TO_DAC1L_MASK 0x0010 /* ADCL_TO_DAC1L */ 3027*4882a593Smuzhiyun #define WM8996_ADCL_TO_DAC1L_SHIFT 4 /* ADCL_TO_DAC1L */ 3028*4882a593Smuzhiyun #define WM8996_ADCL_TO_DAC1L_WIDTH 1 /* ADCL_TO_DAC1L */ 3029*4882a593Smuzhiyun #define WM8996_DSP2RXL_TO_DAC1L 0x0002 /* DSP2RXL_TO_DAC1L */ 3030*4882a593Smuzhiyun #define WM8996_DSP2RXL_TO_DAC1L_MASK 0x0002 /* DSP2RXL_TO_DAC1L */ 3031*4882a593Smuzhiyun #define WM8996_DSP2RXL_TO_DAC1L_SHIFT 1 /* DSP2RXL_TO_DAC1L */ 3032*4882a593Smuzhiyun #define WM8996_DSP2RXL_TO_DAC1L_WIDTH 1 /* DSP2RXL_TO_DAC1L */ 3033*4882a593Smuzhiyun #define WM8996_DSP1RXL_TO_DAC1L 0x0001 /* DSP1RXL_TO_DAC1L */ 3034*4882a593Smuzhiyun #define WM8996_DSP1RXL_TO_DAC1L_MASK 0x0001 /* DSP1RXL_TO_DAC1L */ 3035*4882a593Smuzhiyun #define WM8996_DSP1RXL_TO_DAC1L_SHIFT 0 /* DSP1RXL_TO_DAC1L */ 3036*4882a593Smuzhiyun #define WM8996_DSP1RXL_TO_DAC1L_WIDTH 1 /* DSP1RXL_TO_DAC1L */ 3037*4882a593Smuzhiyun 3038*4882a593Smuzhiyun /* 3039*4882a593Smuzhiyun * R1538 (0x602) - DAC1 Right Mixer Routing 3040*4882a593Smuzhiyun */ 3041*4882a593Smuzhiyun #define WM8996_ADCR_TO_DAC1R 0x0020 /* ADCR_TO_DAC1R */ 3042*4882a593Smuzhiyun #define WM8996_ADCR_TO_DAC1R_MASK 0x0020 /* ADCR_TO_DAC1R */ 3043*4882a593Smuzhiyun #define WM8996_ADCR_TO_DAC1R_SHIFT 5 /* ADCR_TO_DAC1R */ 3044*4882a593Smuzhiyun #define WM8996_ADCR_TO_DAC1R_WIDTH 1 /* ADCR_TO_DAC1R */ 3045*4882a593Smuzhiyun #define WM8996_ADCL_TO_DAC1R 0x0010 /* ADCL_TO_DAC1R */ 3046*4882a593Smuzhiyun #define WM8996_ADCL_TO_DAC1R_MASK 0x0010 /* ADCL_TO_DAC1R */ 3047*4882a593Smuzhiyun #define WM8996_ADCL_TO_DAC1R_SHIFT 4 /* ADCL_TO_DAC1R */ 3048*4882a593Smuzhiyun #define WM8996_ADCL_TO_DAC1R_WIDTH 1 /* ADCL_TO_DAC1R */ 3049*4882a593Smuzhiyun #define WM8996_DSP2RXR_TO_DAC1R 0x0002 /* DSP2RXR_TO_DAC1R */ 3050*4882a593Smuzhiyun #define WM8996_DSP2RXR_TO_DAC1R_MASK 0x0002 /* DSP2RXR_TO_DAC1R */ 3051*4882a593Smuzhiyun #define WM8996_DSP2RXR_TO_DAC1R_SHIFT 1 /* DSP2RXR_TO_DAC1R */ 3052*4882a593Smuzhiyun #define WM8996_DSP2RXR_TO_DAC1R_WIDTH 1 /* DSP2RXR_TO_DAC1R */ 3053*4882a593Smuzhiyun #define WM8996_DSP1RXR_TO_DAC1R 0x0001 /* DSP1RXR_TO_DAC1R */ 3054*4882a593Smuzhiyun #define WM8996_DSP1RXR_TO_DAC1R_MASK 0x0001 /* DSP1RXR_TO_DAC1R */ 3055*4882a593Smuzhiyun #define WM8996_DSP1RXR_TO_DAC1R_SHIFT 0 /* DSP1RXR_TO_DAC1R */ 3056*4882a593Smuzhiyun #define WM8996_DSP1RXR_TO_DAC1R_WIDTH 1 /* DSP1RXR_TO_DAC1R */ 3057*4882a593Smuzhiyun 3058*4882a593Smuzhiyun /* 3059*4882a593Smuzhiyun * R1539 (0x603) - DAC2 Mixer Volumes 3060*4882a593Smuzhiyun */ 3061*4882a593Smuzhiyun #define WM8996_ADCR_DAC2_VOL_MASK 0x03E0 /* ADCR_DAC2_VOL - [9:5] */ 3062*4882a593Smuzhiyun #define WM8996_ADCR_DAC2_VOL_SHIFT 5 /* ADCR_DAC2_VOL - [9:5] */ 3063*4882a593Smuzhiyun #define WM8996_ADCR_DAC2_VOL_WIDTH 5 /* ADCR_DAC2_VOL - [9:5] */ 3064*4882a593Smuzhiyun #define WM8996_ADCL_DAC2_VOL_MASK 0x001F /* ADCL_DAC2_VOL - [4:0] */ 3065*4882a593Smuzhiyun #define WM8996_ADCL_DAC2_VOL_SHIFT 0 /* ADCL_DAC2_VOL - [4:0] */ 3066*4882a593Smuzhiyun #define WM8996_ADCL_DAC2_VOL_WIDTH 5 /* ADCL_DAC2_VOL - [4:0] */ 3067*4882a593Smuzhiyun 3068*4882a593Smuzhiyun /* 3069*4882a593Smuzhiyun * R1540 (0x604) - DAC2 Left Mixer Routing 3070*4882a593Smuzhiyun */ 3071*4882a593Smuzhiyun #define WM8996_ADCR_TO_DAC2L 0x0020 /* ADCR_TO_DAC2L */ 3072*4882a593Smuzhiyun #define WM8996_ADCR_TO_DAC2L_MASK 0x0020 /* ADCR_TO_DAC2L */ 3073*4882a593Smuzhiyun #define WM8996_ADCR_TO_DAC2L_SHIFT 5 /* ADCR_TO_DAC2L */ 3074*4882a593Smuzhiyun #define WM8996_ADCR_TO_DAC2L_WIDTH 1 /* ADCR_TO_DAC2L */ 3075*4882a593Smuzhiyun #define WM8996_ADCL_TO_DAC2L 0x0010 /* ADCL_TO_DAC2L */ 3076*4882a593Smuzhiyun #define WM8996_ADCL_TO_DAC2L_MASK 0x0010 /* ADCL_TO_DAC2L */ 3077*4882a593Smuzhiyun #define WM8996_ADCL_TO_DAC2L_SHIFT 4 /* ADCL_TO_DAC2L */ 3078*4882a593Smuzhiyun #define WM8996_ADCL_TO_DAC2L_WIDTH 1 /* ADCL_TO_DAC2L */ 3079*4882a593Smuzhiyun #define WM8996_DSP2RXL_TO_DAC2L 0x0002 /* DSP2RXL_TO_DAC2L */ 3080*4882a593Smuzhiyun #define WM8996_DSP2RXL_TO_DAC2L_MASK 0x0002 /* DSP2RXL_TO_DAC2L */ 3081*4882a593Smuzhiyun #define WM8996_DSP2RXL_TO_DAC2L_SHIFT 1 /* DSP2RXL_TO_DAC2L */ 3082*4882a593Smuzhiyun #define WM8996_DSP2RXL_TO_DAC2L_WIDTH 1 /* DSP2RXL_TO_DAC2L */ 3083*4882a593Smuzhiyun #define WM8996_DSP1RXL_TO_DAC2L 0x0001 /* DSP1RXL_TO_DAC2L */ 3084*4882a593Smuzhiyun #define WM8996_DSP1RXL_TO_DAC2L_MASK 0x0001 /* DSP1RXL_TO_DAC2L */ 3085*4882a593Smuzhiyun #define WM8996_DSP1RXL_TO_DAC2L_SHIFT 0 /* DSP1RXL_TO_DAC2L */ 3086*4882a593Smuzhiyun #define WM8996_DSP1RXL_TO_DAC2L_WIDTH 1 /* DSP1RXL_TO_DAC2L */ 3087*4882a593Smuzhiyun 3088*4882a593Smuzhiyun /* 3089*4882a593Smuzhiyun * R1541 (0x605) - DAC2 Right Mixer Routing 3090*4882a593Smuzhiyun */ 3091*4882a593Smuzhiyun #define WM8996_ADCR_TO_DAC2R 0x0020 /* ADCR_TO_DAC2R */ 3092*4882a593Smuzhiyun #define WM8996_ADCR_TO_DAC2R_MASK 0x0020 /* ADCR_TO_DAC2R */ 3093*4882a593Smuzhiyun #define WM8996_ADCR_TO_DAC2R_SHIFT 5 /* ADCR_TO_DAC2R */ 3094*4882a593Smuzhiyun #define WM8996_ADCR_TO_DAC2R_WIDTH 1 /* ADCR_TO_DAC2R */ 3095*4882a593Smuzhiyun #define WM8996_ADCL_TO_DAC2R 0x0010 /* ADCL_TO_DAC2R */ 3096*4882a593Smuzhiyun #define WM8996_ADCL_TO_DAC2R_MASK 0x0010 /* ADCL_TO_DAC2R */ 3097*4882a593Smuzhiyun #define WM8996_ADCL_TO_DAC2R_SHIFT 4 /* ADCL_TO_DAC2R */ 3098*4882a593Smuzhiyun #define WM8996_ADCL_TO_DAC2R_WIDTH 1 /* ADCL_TO_DAC2R */ 3099*4882a593Smuzhiyun #define WM8996_DSP2RXR_TO_DAC2R 0x0002 /* DSP2RXR_TO_DAC2R */ 3100*4882a593Smuzhiyun #define WM8996_DSP2RXR_TO_DAC2R_MASK 0x0002 /* DSP2RXR_TO_DAC2R */ 3101*4882a593Smuzhiyun #define WM8996_DSP2RXR_TO_DAC2R_SHIFT 1 /* DSP2RXR_TO_DAC2R */ 3102*4882a593Smuzhiyun #define WM8996_DSP2RXR_TO_DAC2R_WIDTH 1 /* DSP2RXR_TO_DAC2R */ 3103*4882a593Smuzhiyun #define WM8996_DSP1RXR_TO_DAC2R 0x0001 /* DSP1RXR_TO_DAC2R */ 3104*4882a593Smuzhiyun #define WM8996_DSP1RXR_TO_DAC2R_MASK 0x0001 /* DSP1RXR_TO_DAC2R */ 3105*4882a593Smuzhiyun #define WM8996_DSP1RXR_TO_DAC2R_SHIFT 0 /* DSP1RXR_TO_DAC2R */ 3106*4882a593Smuzhiyun #define WM8996_DSP1RXR_TO_DAC2R_WIDTH 1 /* DSP1RXR_TO_DAC2R */ 3107*4882a593Smuzhiyun 3108*4882a593Smuzhiyun /* 3109*4882a593Smuzhiyun * R1542 (0x606) - DSP1 TX Left Mixer Routing 3110*4882a593Smuzhiyun */ 3111*4882a593Smuzhiyun #define WM8996_ADC1L_TO_DSP1TXL 0x0002 /* ADC1L_TO_DSP1TXL */ 3112*4882a593Smuzhiyun #define WM8996_ADC1L_TO_DSP1TXL_MASK 0x0002 /* ADC1L_TO_DSP1TXL */ 3113*4882a593Smuzhiyun #define WM8996_ADC1L_TO_DSP1TXL_SHIFT 1 /* ADC1L_TO_DSP1TXL */ 3114*4882a593Smuzhiyun #define WM8996_ADC1L_TO_DSP1TXL_WIDTH 1 /* ADC1L_TO_DSP1TXL */ 3115*4882a593Smuzhiyun #define WM8996_DACL_TO_DSP1TXL 0x0001 /* DACL_TO_DSP1TXL */ 3116*4882a593Smuzhiyun #define WM8996_DACL_TO_DSP1TXL_MASK 0x0001 /* DACL_TO_DSP1TXL */ 3117*4882a593Smuzhiyun #define WM8996_DACL_TO_DSP1TXL_SHIFT 0 /* DACL_TO_DSP1TXL */ 3118*4882a593Smuzhiyun #define WM8996_DACL_TO_DSP1TXL_WIDTH 1 /* DACL_TO_DSP1TXL */ 3119*4882a593Smuzhiyun 3120*4882a593Smuzhiyun /* 3121*4882a593Smuzhiyun * R1543 (0x607) - DSP1 TX Right Mixer Routing 3122*4882a593Smuzhiyun */ 3123*4882a593Smuzhiyun #define WM8996_ADC1R_TO_DSP1TXR 0x0002 /* ADC1R_TO_DSP1TXR */ 3124*4882a593Smuzhiyun #define WM8996_ADC1R_TO_DSP1TXR_MASK 0x0002 /* ADC1R_TO_DSP1TXR */ 3125*4882a593Smuzhiyun #define WM8996_ADC1R_TO_DSP1TXR_SHIFT 1 /* ADC1R_TO_DSP1TXR */ 3126*4882a593Smuzhiyun #define WM8996_ADC1R_TO_DSP1TXR_WIDTH 1 /* ADC1R_TO_DSP1TXR */ 3127*4882a593Smuzhiyun #define WM8996_DACR_TO_DSP1TXR 0x0001 /* DACR_TO_DSP1TXR */ 3128*4882a593Smuzhiyun #define WM8996_DACR_TO_DSP1TXR_MASK 0x0001 /* DACR_TO_DSP1TXR */ 3129*4882a593Smuzhiyun #define WM8996_DACR_TO_DSP1TXR_SHIFT 0 /* DACR_TO_DSP1TXR */ 3130*4882a593Smuzhiyun #define WM8996_DACR_TO_DSP1TXR_WIDTH 1 /* DACR_TO_DSP1TXR */ 3131*4882a593Smuzhiyun 3132*4882a593Smuzhiyun /* 3133*4882a593Smuzhiyun * R1544 (0x608) - DSP2 TX Left Mixer Routing 3134*4882a593Smuzhiyun */ 3135*4882a593Smuzhiyun #define WM8996_ADC2L_TO_DSP2TXL 0x0002 /* ADC2L_TO_DSP2TXL */ 3136*4882a593Smuzhiyun #define WM8996_ADC2L_TO_DSP2TXL_MASK 0x0002 /* ADC2L_TO_DSP2TXL */ 3137*4882a593Smuzhiyun #define WM8996_ADC2L_TO_DSP2TXL_SHIFT 1 /* ADC2L_TO_DSP2TXL */ 3138*4882a593Smuzhiyun #define WM8996_ADC2L_TO_DSP2TXL_WIDTH 1 /* ADC2L_TO_DSP2TXL */ 3139*4882a593Smuzhiyun #define WM8996_DACL_TO_DSP2TXL 0x0001 /* DACL_TO_DSP2TXL */ 3140*4882a593Smuzhiyun #define WM8996_DACL_TO_DSP2TXL_MASK 0x0001 /* DACL_TO_DSP2TXL */ 3141*4882a593Smuzhiyun #define WM8996_DACL_TO_DSP2TXL_SHIFT 0 /* DACL_TO_DSP2TXL */ 3142*4882a593Smuzhiyun #define WM8996_DACL_TO_DSP2TXL_WIDTH 1 /* DACL_TO_DSP2TXL */ 3143*4882a593Smuzhiyun 3144*4882a593Smuzhiyun /* 3145*4882a593Smuzhiyun * R1545 (0x609) - DSP2 TX Right Mixer Routing 3146*4882a593Smuzhiyun */ 3147*4882a593Smuzhiyun #define WM8996_ADC2R_TO_DSP2TXR 0x0002 /* ADC2R_TO_DSP2TXR */ 3148*4882a593Smuzhiyun #define WM8996_ADC2R_TO_DSP2TXR_MASK 0x0002 /* ADC2R_TO_DSP2TXR */ 3149*4882a593Smuzhiyun #define WM8996_ADC2R_TO_DSP2TXR_SHIFT 1 /* ADC2R_TO_DSP2TXR */ 3150*4882a593Smuzhiyun #define WM8996_ADC2R_TO_DSP2TXR_WIDTH 1 /* ADC2R_TO_DSP2TXR */ 3151*4882a593Smuzhiyun #define WM8996_DACR_TO_DSP2TXR 0x0001 /* DACR_TO_DSP2TXR */ 3152*4882a593Smuzhiyun #define WM8996_DACR_TO_DSP2TXR_MASK 0x0001 /* DACR_TO_DSP2TXR */ 3153*4882a593Smuzhiyun #define WM8996_DACR_TO_DSP2TXR_SHIFT 0 /* DACR_TO_DSP2TXR */ 3154*4882a593Smuzhiyun #define WM8996_DACR_TO_DSP2TXR_WIDTH 1 /* DACR_TO_DSP2TXR */ 3155*4882a593Smuzhiyun 3156*4882a593Smuzhiyun /* 3157*4882a593Smuzhiyun * R1546 (0x60A) - DSP TX Mixer Select 3158*4882a593Smuzhiyun */ 3159*4882a593Smuzhiyun #define WM8996_DAC_TO_DSPTX_SRC 0x0001 /* DAC_TO_DSPTX_SRC */ 3160*4882a593Smuzhiyun #define WM8996_DAC_TO_DSPTX_SRC_MASK 0x0001 /* DAC_TO_DSPTX_SRC */ 3161*4882a593Smuzhiyun #define WM8996_DAC_TO_DSPTX_SRC_SHIFT 0 /* DAC_TO_DSPTX_SRC */ 3162*4882a593Smuzhiyun #define WM8996_DAC_TO_DSPTX_SRC_WIDTH 1 /* DAC_TO_DSPTX_SRC */ 3163*4882a593Smuzhiyun 3164*4882a593Smuzhiyun /* 3165*4882a593Smuzhiyun * R1552 (0x610) - DAC Softmute 3166*4882a593Smuzhiyun */ 3167*4882a593Smuzhiyun #define WM8996_DAC_SOFTMUTEMODE 0x0002 /* DAC_SOFTMUTEMODE */ 3168*4882a593Smuzhiyun #define WM8996_DAC_SOFTMUTEMODE_MASK 0x0002 /* DAC_SOFTMUTEMODE */ 3169*4882a593Smuzhiyun #define WM8996_DAC_SOFTMUTEMODE_SHIFT 1 /* DAC_SOFTMUTEMODE */ 3170*4882a593Smuzhiyun #define WM8996_DAC_SOFTMUTEMODE_WIDTH 1 /* DAC_SOFTMUTEMODE */ 3171*4882a593Smuzhiyun #define WM8996_DAC_MUTERATE 0x0001 /* DAC_MUTERATE */ 3172*4882a593Smuzhiyun #define WM8996_DAC_MUTERATE_MASK 0x0001 /* DAC_MUTERATE */ 3173*4882a593Smuzhiyun #define WM8996_DAC_MUTERATE_SHIFT 0 /* DAC_MUTERATE */ 3174*4882a593Smuzhiyun #define WM8996_DAC_MUTERATE_WIDTH 1 /* DAC_MUTERATE */ 3175*4882a593Smuzhiyun 3176*4882a593Smuzhiyun /* 3177*4882a593Smuzhiyun * R1568 (0x620) - Oversampling 3178*4882a593Smuzhiyun */ 3179*4882a593Smuzhiyun #define WM8996_SPK_OSR128 0x0008 /* SPK_OSR128 */ 3180*4882a593Smuzhiyun #define WM8996_SPK_OSR128_MASK 0x0008 /* SPK_OSR128 */ 3181*4882a593Smuzhiyun #define WM8996_SPK_OSR128_SHIFT 3 /* SPK_OSR128 */ 3182*4882a593Smuzhiyun #define WM8996_SPK_OSR128_WIDTH 1 /* SPK_OSR128 */ 3183*4882a593Smuzhiyun #define WM8996_DMIC_OSR64 0x0004 /* DMIC_OSR64 */ 3184*4882a593Smuzhiyun #define WM8996_DMIC_OSR64_MASK 0x0004 /* DMIC_OSR64 */ 3185*4882a593Smuzhiyun #define WM8996_DMIC_OSR64_SHIFT 2 /* DMIC_OSR64 */ 3186*4882a593Smuzhiyun #define WM8996_DMIC_OSR64_WIDTH 1 /* DMIC_OSR64 */ 3187*4882a593Smuzhiyun #define WM8996_ADC_OSR128 0x0002 /* ADC_OSR128 */ 3188*4882a593Smuzhiyun #define WM8996_ADC_OSR128_MASK 0x0002 /* ADC_OSR128 */ 3189*4882a593Smuzhiyun #define WM8996_ADC_OSR128_SHIFT 1 /* ADC_OSR128 */ 3190*4882a593Smuzhiyun #define WM8996_ADC_OSR128_WIDTH 1 /* ADC_OSR128 */ 3191*4882a593Smuzhiyun #define WM8996_DAC_OSR128 0x0001 /* DAC_OSR128 */ 3192*4882a593Smuzhiyun #define WM8996_DAC_OSR128_MASK 0x0001 /* DAC_OSR128 */ 3193*4882a593Smuzhiyun #define WM8996_DAC_OSR128_SHIFT 0 /* DAC_OSR128 */ 3194*4882a593Smuzhiyun #define WM8996_DAC_OSR128_WIDTH 1 /* DAC_OSR128 */ 3195*4882a593Smuzhiyun 3196*4882a593Smuzhiyun /* 3197*4882a593Smuzhiyun * R1569 (0x621) - Sidetone 3198*4882a593Smuzhiyun */ 3199*4882a593Smuzhiyun #define WM8996_ST_LPF 0x1000 /* ST_LPF */ 3200*4882a593Smuzhiyun #define WM8996_ST_LPF_MASK 0x1000 /* ST_LPF */ 3201*4882a593Smuzhiyun #define WM8996_ST_LPF_SHIFT 12 /* ST_LPF */ 3202*4882a593Smuzhiyun #define WM8996_ST_LPF_WIDTH 1 /* ST_LPF */ 3203*4882a593Smuzhiyun #define WM8996_ST_HPF_CUT_MASK 0x0380 /* ST_HPF_CUT - [9:7] */ 3204*4882a593Smuzhiyun #define WM8996_ST_HPF_CUT_SHIFT 7 /* ST_HPF_CUT - [9:7] */ 3205*4882a593Smuzhiyun #define WM8996_ST_HPF_CUT_WIDTH 3 /* ST_HPF_CUT - [9:7] */ 3206*4882a593Smuzhiyun #define WM8996_ST_HPF 0x0040 /* ST_HPF */ 3207*4882a593Smuzhiyun #define WM8996_ST_HPF_MASK 0x0040 /* ST_HPF */ 3208*4882a593Smuzhiyun #define WM8996_ST_HPF_SHIFT 6 /* ST_HPF */ 3209*4882a593Smuzhiyun #define WM8996_ST_HPF_WIDTH 1 /* ST_HPF */ 3210*4882a593Smuzhiyun #define WM8996_STR_SEL 0x0002 /* STR_SEL */ 3211*4882a593Smuzhiyun #define WM8996_STR_SEL_MASK 0x0002 /* STR_SEL */ 3212*4882a593Smuzhiyun #define WM8996_STR_SEL_SHIFT 1 /* STR_SEL */ 3213*4882a593Smuzhiyun #define WM8996_STR_SEL_WIDTH 1 /* STR_SEL */ 3214*4882a593Smuzhiyun #define WM8996_STL_SEL 0x0001 /* STL_SEL */ 3215*4882a593Smuzhiyun #define WM8996_STL_SEL_MASK 0x0001 /* STL_SEL */ 3216*4882a593Smuzhiyun #define WM8996_STL_SEL_SHIFT 0 /* STL_SEL */ 3217*4882a593Smuzhiyun #define WM8996_STL_SEL_WIDTH 1 /* STL_SEL */ 3218*4882a593Smuzhiyun 3219*4882a593Smuzhiyun /* 3220*4882a593Smuzhiyun * R1792 (0x700) - GPIO 1 3221*4882a593Smuzhiyun */ 3222*4882a593Smuzhiyun #define WM8996_GP1_DIR 0x8000 /* GP1_DIR */ 3223*4882a593Smuzhiyun #define WM8996_GP1_DIR_MASK 0x8000 /* GP1_DIR */ 3224*4882a593Smuzhiyun #define WM8996_GP1_DIR_SHIFT 15 /* GP1_DIR */ 3225*4882a593Smuzhiyun #define WM8996_GP1_DIR_WIDTH 1 /* GP1_DIR */ 3226*4882a593Smuzhiyun #define WM8996_GP1_PU 0x4000 /* GP1_PU */ 3227*4882a593Smuzhiyun #define WM8996_GP1_PU_MASK 0x4000 /* GP1_PU */ 3228*4882a593Smuzhiyun #define WM8996_GP1_PU_SHIFT 14 /* GP1_PU */ 3229*4882a593Smuzhiyun #define WM8996_GP1_PU_WIDTH 1 /* GP1_PU */ 3230*4882a593Smuzhiyun #define WM8996_GP1_PD 0x2000 /* GP1_PD */ 3231*4882a593Smuzhiyun #define WM8996_GP1_PD_MASK 0x2000 /* GP1_PD */ 3232*4882a593Smuzhiyun #define WM8996_GP1_PD_SHIFT 13 /* GP1_PD */ 3233*4882a593Smuzhiyun #define WM8996_GP1_PD_WIDTH 1 /* GP1_PD */ 3234*4882a593Smuzhiyun #define WM8996_GP1_POL 0x0400 /* GP1_POL */ 3235*4882a593Smuzhiyun #define WM8996_GP1_POL_MASK 0x0400 /* GP1_POL */ 3236*4882a593Smuzhiyun #define WM8996_GP1_POL_SHIFT 10 /* GP1_POL */ 3237*4882a593Smuzhiyun #define WM8996_GP1_POL_WIDTH 1 /* GP1_POL */ 3238*4882a593Smuzhiyun #define WM8996_GP1_OP_CFG 0x0200 /* GP1_OP_CFG */ 3239*4882a593Smuzhiyun #define WM8996_GP1_OP_CFG_MASK 0x0200 /* GP1_OP_CFG */ 3240*4882a593Smuzhiyun #define WM8996_GP1_OP_CFG_SHIFT 9 /* GP1_OP_CFG */ 3241*4882a593Smuzhiyun #define WM8996_GP1_OP_CFG_WIDTH 1 /* GP1_OP_CFG */ 3242*4882a593Smuzhiyun #define WM8996_GP1_DB 0x0100 /* GP1_DB */ 3243*4882a593Smuzhiyun #define WM8996_GP1_DB_MASK 0x0100 /* GP1_DB */ 3244*4882a593Smuzhiyun #define WM8996_GP1_DB_SHIFT 8 /* GP1_DB */ 3245*4882a593Smuzhiyun #define WM8996_GP1_DB_WIDTH 1 /* GP1_DB */ 3246*4882a593Smuzhiyun #define WM8996_GP1_LVL 0x0040 /* GP1_LVL */ 3247*4882a593Smuzhiyun #define WM8996_GP1_LVL_MASK 0x0040 /* GP1_LVL */ 3248*4882a593Smuzhiyun #define WM8996_GP1_LVL_SHIFT 6 /* GP1_LVL */ 3249*4882a593Smuzhiyun #define WM8996_GP1_LVL_WIDTH 1 /* GP1_LVL */ 3250*4882a593Smuzhiyun #define WM8996_GP1_FN_MASK 0x000F /* GP1_FN - [3:0] */ 3251*4882a593Smuzhiyun #define WM8996_GP1_FN_SHIFT 0 /* GP1_FN - [3:0] */ 3252*4882a593Smuzhiyun #define WM8996_GP1_FN_WIDTH 4 /* GP1_FN - [3:0] */ 3253*4882a593Smuzhiyun 3254*4882a593Smuzhiyun /* 3255*4882a593Smuzhiyun * R1793 (0x701) - GPIO 2 3256*4882a593Smuzhiyun */ 3257*4882a593Smuzhiyun #define WM8996_GP2_DIR 0x8000 /* GP2_DIR */ 3258*4882a593Smuzhiyun #define WM8996_GP2_DIR_MASK 0x8000 /* GP2_DIR */ 3259*4882a593Smuzhiyun #define WM8996_GP2_DIR_SHIFT 15 /* GP2_DIR */ 3260*4882a593Smuzhiyun #define WM8996_GP2_DIR_WIDTH 1 /* GP2_DIR */ 3261*4882a593Smuzhiyun #define WM8996_GP2_PU 0x4000 /* GP2_PU */ 3262*4882a593Smuzhiyun #define WM8996_GP2_PU_MASK 0x4000 /* GP2_PU */ 3263*4882a593Smuzhiyun #define WM8996_GP2_PU_SHIFT 14 /* GP2_PU */ 3264*4882a593Smuzhiyun #define WM8996_GP2_PU_WIDTH 1 /* GP2_PU */ 3265*4882a593Smuzhiyun #define WM8996_GP2_PD 0x2000 /* GP2_PD */ 3266*4882a593Smuzhiyun #define WM8996_GP2_PD_MASK 0x2000 /* GP2_PD */ 3267*4882a593Smuzhiyun #define WM8996_GP2_PD_SHIFT 13 /* GP2_PD */ 3268*4882a593Smuzhiyun #define WM8996_GP2_PD_WIDTH 1 /* GP2_PD */ 3269*4882a593Smuzhiyun #define WM8996_GP2_POL 0x0400 /* GP2_POL */ 3270*4882a593Smuzhiyun #define WM8996_GP2_POL_MASK 0x0400 /* GP2_POL */ 3271*4882a593Smuzhiyun #define WM8996_GP2_POL_SHIFT 10 /* GP2_POL */ 3272*4882a593Smuzhiyun #define WM8996_GP2_POL_WIDTH 1 /* GP2_POL */ 3273*4882a593Smuzhiyun #define WM8996_GP2_OP_CFG 0x0200 /* GP2_OP_CFG */ 3274*4882a593Smuzhiyun #define WM8996_GP2_OP_CFG_MASK 0x0200 /* GP2_OP_CFG */ 3275*4882a593Smuzhiyun #define WM8996_GP2_OP_CFG_SHIFT 9 /* GP2_OP_CFG */ 3276*4882a593Smuzhiyun #define WM8996_GP2_OP_CFG_WIDTH 1 /* GP2_OP_CFG */ 3277*4882a593Smuzhiyun #define WM8996_GP2_DB 0x0100 /* GP2_DB */ 3278*4882a593Smuzhiyun #define WM8996_GP2_DB_MASK 0x0100 /* GP2_DB */ 3279*4882a593Smuzhiyun #define WM8996_GP2_DB_SHIFT 8 /* GP2_DB */ 3280*4882a593Smuzhiyun #define WM8996_GP2_DB_WIDTH 1 /* GP2_DB */ 3281*4882a593Smuzhiyun #define WM8996_GP2_LVL 0x0040 /* GP2_LVL */ 3282*4882a593Smuzhiyun #define WM8996_GP2_LVL_MASK 0x0040 /* GP2_LVL */ 3283*4882a593Smuzhiyun #define WM8996_GP2_LVL_SHIFT 6 /* GP2_LVL */ 3284*4882a593Smuzhiyun #define WM8996_GP2_LVL_WIDTH 1 /* GP2_LVL */ 3285*4882a593Smuzhiyun #define WM8996_GP2_FN_MASK 0x000F /* GP2_FN - [3:0] */ 3286*4882a593Smuzhiyun #define WM8996_GP2_FN_SHIFT 0 /* GP2_FN - [3:0] */ 3287*4882a593Smuzhiyun #define WM8996_GP2_FN_WIDTH 4 /* GP2_FN - [3:0] */ 3288*4882a593Smuzhiyun 3289*4882a593Smuzhiyun /* 3290*4882a593Smuzhiyun * R1794 (0x702) - GPIO 3 3291*4882a593Smuzhiyun */ 3292*4882a593Smuzhiyun #define WM8996_GP3_DIR 0x8000 /* GP3_DIR */ 3293*4882a593Smuzhiyun #define WM8996_GP3_DIR_MASK 0x8000 /* GP3_DIR */ 3294*4882a593Smuzhiyun #define WM8996_GP3_DIR_SHIFT 15 /* GP3_DIR */ 3295*4882a593Smuzhiyun #define WM8996_GP3_DIR_WIDTH 1 /* GP3_DIR */ 3296*4882a593Smuzhiyun #define WM8996_GP3_PU 0x4000 /* GP3_PU */ 3297*4882a593Smuzhiyun #define WM8996_GP3_PU_MASK 0x4000 /* GP3_PU */ 3298*4882a593Smuzhiyun #define WM8996_GP3_PU_SHIFT 14 /* GP3_PU */ 3299*4882a593Smuzhiyun #define WM8996_GP3_PU_WIDTH 1 /* GP3_PU */ 3300*4882a593Smuzhiyun #define WM8996_GP3_PD 0x2000 /* GP3_PD */ 3301*4882a593Smuzhiyun #define WM8996_GP3_PD_MASK 0x2000 /* GP3_PD */ 3302*4882a593Smuzhiyun #define WM8996_GP3_PD_SHIFT 13 /* GP3_PD */ 3303*4882a593Smuzhiyun #define WM8996_GP3_PD_WIDTH 1 /* GP3_PD */ 3304*4882a593Smuzhiyun #define WM8996_GP3_POL 0x0400 /* GP3_POL */ 3305*4882a593Smuzhiyun #define WM8996_GP3_POL_MASK 0x0400 /* GP3_POL */ 3306*4882a593Smuzhiyun #define WM8996_GP3_POL_SHIFT 10 /* GP3_POL */ 3307*4882a593Smuzhiyun #define WM8996_GP3_POL_WIDTH 1 /* GP3_POL */ 3308*4882a593Smuzhiyun #define WM8996_GP3_OP_CFG 0x0200 /* GP3_OP_CFG */ 3309*4882a593Smuzhiyun #define WM8996_GP3_OP_CFG_MASK 0x0200 /* GP3_OP_CFG */ 3310*4882a593Smuzhiyun #define WM8996_GP3_OP_CFG_SHIFT 9 /* GP3_OP_CFG */ 3311*4882a593Smuzhiyun #define WM8996_GP3_OP_CFG_WIDTH 1 /* GP3_OP_CFG */ 3312*4882a593Smuzhiyun #define WM8996_GP3_DB 0x0100 /* GP3_DB */ 3313*4882a593Smuzhiyun #define WM8996_GP3_DB_MASK 0x0100 /* GP3_DB */ 3314*4882a593Smuzhiyun #define WM8996_GP3_DB_SHIFT 8 /* GP3_DB */ 3315*4882a593Smuzhiyun #define WM8996_GP3_DB_WIDTH 1 /* GP3_DB */ 3316*4882a593Smuzhiyun #define WM8996_GP3_LVL 0x0040 /* GP3_LVL */ 3317*4882a593Smuzhiyun #define WM8996_GP3_LVL_MASK 0x0040 /* GP3_LVL */ 3318*4882a593Smuzhiyun #define WM8996_GP3_LVL_SHIFT 6 /* GP3_LVL */ 3319*4882a593Smuzhiyun #define WM8996_GP3_LVL_WIDTH 1 /* GP3_LVL */ 3320*4882a593Smuzhiyun #define WM8996_GP3_FN_MASK 0x000F /* GP3_FN - [3:0] */ 3321*4882a593Smuzhiyun #define WM8996_GP3_FN_SHIFT 0 /* GP3_FN - [3:0] */ 3322*4882a593Smuzhiyun #define WM8996_GP3_FN_WIDTH 4 /* GP3_FN - [3:0] */ 3323*4882a593Smuzhiyun 3324*4882a593Smuzhiyun /* 3325*4882a593Smuzhiyun * R1795 (0x703) - GPIO 4 3326*4882a593Smuzhiyun */ 3327*4882a593Smuzhiyun #define WM8996_GP4_DIR 0x8000 /* GP4_DIR */ 3328*4882a593Smuzhiyun #define WM8996_GP4_DIR_MASK 0x8000 /* GP4_DIR */ 3329*4882a593Smuzhiyun #define WM8996_GP4_DIR_SHIFT 15 /* GP4_DIR */ 3330*4882a593Smuzhiyun #define WM8996_GP4_DIR_WIDTH 1 /* GP4_DIR */ 3331*4882a593Smuzhiyun #define WM8996_GP4_PU 0x4000 /* GP4_PU */ 3332*4882a593Smuzhiyun #define WM8996_GP4_PU_MASK 0x4000 /* GP4_PU */ 3333*4882a593Smuzhiyun #define WM8996_GP4_PU_SHIFT 14 /* GP4_PU */ 3334*4882a593Smuzhiyun #define WM8996_GP4_PU_WIDTH 1 /* GP4_PU */ 3335*4882a593Smuzhiyun #define WM8996_GP4_PD 0x2000 /* GP4_PD */ 3336*4882a593Smuzhiyun #define WM8996_GP4_PD_MASK 0x2000 /* GP4_PD */ 3337*4882a593Smuzhiyun #define WM8996_GP4_PD_SHIFT 13 /* GP4_PD */ 3338*4882a593Smuzhiyun #define WM8996_GP4_PD_WIDTH 1 /* GP4_PD */ 3339*4882a593Smuzhiyun #define WM8996_GP4_POL 0x0400 /* GP4_POL */ 3340*4882a593Smuzhiyun #define WM8996_GP4_POL_MASK 0x0400 /* GP4_POL */ 3341*4882a593Smuzhiyun #define WM8996_GP4_POL_SHIFT 10 /* GP4_POL */ 3342*4882a593Smuzhiyun #define WM8996_GP4_POL_WIDTH 1 /* GP4_POL */ 3343*4882a593Smuzhiyun #define WM8996_GP4_OP_CFG 0x0200 /* GP4_OP_CFG */ 3344*4882a593Smuzhiyun #define WM8996_GP4_OP_CFG_MASK 0x0200 /* GP4_OP_CFG */ 3345*4882a593Smuzhiyun #define WM8996_GP4_OP_CFG_SHIFT 9 /* GP4_OP_CFG */ 3346*4882a593Smuzhiyun #define WM8996_GP4_OP_CFG_WIDTH 1 /* GP4_OP_CFG */ 3347*4882a593Smuzhiyun #define WM8996_GP4_DB 0x0100 /* GP4_DB */ 3348*4882a593Smuzhiyun #define WM8996_GP4_DB_MASK 0x0100 /* GP4_DB */ 3349*4882a593Smuzhiyun #define WM8996_GP4_DB_SHIFT 8 /* GP4_DB */ 3350*4882a593Smuzhiyun #define WM8996_GP4_DB_WIDTH 1 /* GP4_DB */ 3351*4882a593Smuzhiyun #define WM8996_GP4_LVL 0x0040 /* GP4_LVL */ 3352*4882a593Smuzhiyun #define WM8996_GP4_LVL_MASK 0x0040 /* GP4_LVL */ 3353*4882a593Smuzhiyun #define WM8996_GP4_LVL_SHIFT 6 /* GP4_LVL */ 3354*4882a593Smuzhiyun #define WM8996_GP4_LVL_WIDTH 1 /* GP4_LVL */ 3355*4882a593Smuzhiyun #define WM8996_GP4_FN_MASK 0x000F /* GP4_FN - [3:0] */ 3356*4882a593Smuzhiyun #define WM8996_GP4_FN_SHIFT 0 /* GP4_FN - [3:0] */ 3357*4882a593Smuzhiyun #define WM8996_GP4_FN_WIDTH 4 /* GP4_FN - [3:0] */ 3358*4882a593Smuzhiyun 3359*4882a593Smuzhiyun /* 3360*4882a593Smuzhiyun * R1796 (0x704) - GPIO 5 3361*4882a593Smuzhiyun */ 3362*4882a593Smuzhiyun #define WM8996_GP5_DIR 0x8000 /* GP5_DIR */ 3363*4882a593Smuzhiyun #define WM8996_GP5_DIR_MASK 0x8000 /* GP5_DIR */ 3364*4882a593Smuzhiyun #define WM8996_GP5_DIR_SHIFT 15 /* GP5_DIR */ 3365*4882a593Smuzhiyun #define WM8996_GP5_DIR_WIDTH 1 /* GP5_DIR */ 3366*4882a593Smuzhiyun #define WM8996_GP5_PU 0x4000 /* GP5_PU */ 3367*4882a593Smuzhiyun #define WM8996_GP5_PU_MASK 0x4000 /* GP5_PU */ 3368*4882a593Smuzhiyun #define WM8996_GP5_PU_SHIFT 14 /* GP5_PU */ 3369*4882a593Smuzhiyun #define WM8996_GP5_PU_WIDTH 1 /* GP5_PU */ 3370*4882a593Smuzhiyun #define WM8996_GP5_PD 0x2000 /* GP5_PD */ 3371*4882a593Smuzhiyun #define WM8996_GP5_PD_MASK 0x2000 /* GP5_PD */ 3372*4882a593Smuzhiyun #define WM8996_GP5_PD_SHIFT 13 /* GP5_PD */ 3373*4882a593Smuzhiyun #define WM8996_GP5_PD_WIDTH 1 /* GP5_PD */ 3374*4882a593Smuzhiyun #define WM8996_GP5_POL 0x0400 /* GP5_POL */ 3375*4882a593Smuzhiyun #define WM8996_GP5_POL_MASK 0x0400 /* GP5_POL */ 3376*4882a593Smuzhiyun #define WM8996_GP5_POL_SHIFT 10 /* GP5_POL */ 3377*4882a593Smuzhiyun #define WM8996_GP5_POL_WIDTH 1 /* GP5_POL */ 3378*4882a593Smuzhiyun #define WM8996_GP5_OP_CFG 0x0200 /* GP5_OP_CFG */ 3379*4882a593Smuzhiyun #define WM8996_GP5_OP_CFG_MASK 0x0200 /* GP5_OP_CFG */ 3380*4882a593Smuzhiyun #define WM8996_GP5_OP_CFG_SHIFT 9 /* GP5_OP_CFG */ 3381*4882a593Smuzhiyun #define WM8996_GP5_OP_CFG_WIDTH 1 /* GP5_OP_CFG */ 3382*4882a593Smuzhiyun #define WM8996_GP5_DB 0x0100 /* GP5_DB */ 3383*4882a593Smuzhiyun #define WM8996_GP5_DB_MASK 0x0100 /* GP5_DB */ 3384*4882a593Smuzhiyun #define WM8996_GP5_DB_SHIFT 8 /* GP5_DB */ 3385*4882a593Smuzhiyun #define WM8996_GP5_DB_WIDTH 1 /* GP5_DB */ 3386*4882a593Smuzhiyun #define WM8996_GP5_LVL 0x0040 /* GP5_LVL */ 3387*4882a593Smuzhiyun #define WM8996_GP5_LVL_MASK 0x0040 /* GP5_LVL */ 3388*4882a593Smuzhiyun #define WM8996_GP5_LVL_SHIFT 6 /* GP5_LVL */ 3389*4882a593Smuzhiyun #define WM8996_GP5_LVL_WIDTH 1 /* GP5_LVL */ 3390*4882a593Smuzhiyun #define WM8996_GP5_FN_MASK 0x000F /* GP5_FN - [3:0] */ 3391*4882a593Smuzhiyun #define WM8996_GP5_FN_SHIFT 0 /* GP5_FN - [3:0] */ 3392*4882a593Smuzhiyun #define WM8996_GP5_FN_WIDTH 4 /* GP5_FN - [3:0] */ 3393*4882a593Smuzhiyun 3394*4882a593Smuzhiyun /* 3395*4882a593Smuzhiyun * R1824 (0x720) - Pull Control (1) 3396*4882a593Smuzhiyun */ 3397*4882a593Smuzhiyun #define WM8996_DMICDAT2_PD 0x1000 /* DMICDAT2_PD */ 3398*4882a593Smuzhiyun #define WM8996_DMICDAT2_PD_MASK 0x1000 /* DMICDAT2_PD */ 3399*4882a593Smuzhiyun #define WM8996_DMICDAT2_PD_SHIFT 12 /* DMICDAT2_PD */ 3400*4882a593Smuzhiyun #define WM8996_DMICDAT2_PD_WIDTH 1 /* DMICDAT2_PD */ 3401*4882a593Smuzhiyun #define WM8996_DMICDAT1_PD 0x0400 /* DMICDAT1_PD */ 3402*4882a593Smuzhiyun #define WM8996_DMICDAT1_PD_MASK 0x0400 /* DMICDAT1_PD */ 3403*4882a593Smuzhiyun #define WM8996_DMICDAT1_PD_SHIFT 10 /* DMICDAT1_PD */ 3404*4882a593Smuzhiyun #define WM8996_DMICDAT1_PD_WIDTH 1 /* DMICDAT1_PD */ 3405*4882a593Smuzhiyun #define WM8996_MCLK2_PU 0x0200 /* MCLK2_PU */ 3406*4882a593Smuzhiyun #define WM8996_MCLK2_PU_MASK 0x0200 /* MCLK2_PU */ 3407*4882a593Smuzhiyun #define WM8996_MCLK2_PU_SHIFT 9 /* MCLK2_PU */ 3408*4882a593Smuzhiyun #define WM8996_MCLK2_PU_WIDTH 1 /* MCLK2_PU */ 3409*4882a593Smuzhiyun #define WM8996_MCLK2_PD 0x0100 /* MCLK2_PD */ 3410*4882a593Smuzhiyun #define WM8996_MCLK2_PD_MASK 0x0100 /* MCLK2_PD */ 3411*4882a593Smuzhiyun #define WM8996_MCLK2_PD_SHIFT 8 /* MCLK2_PD */ 3412*4882a593Smuzhiyun #define WM8996_MCLK2_PD_WIDTH 1 /* MCLK2_PD */ 3413*4882a593Smuzhiyun #define WM8996_MCLK1_PU 0x0080 /* MCLK1_PU */ 3414*4882a593Smuzhiyun #define WM8996_MCLK1_PU_MASK 0x0080 /* MCLK1_PU */ 3415*4882a593Smuzhiyun #define WM8996_MCLK1_PU_SHIFT 7 /* MCLK1_PU */ 3416*4882a593Smuzhiyun #define WM8996_MCLK1_PU_WIDTH 1 /* MCLK1_PU */ 3417*4882a593Smuzhiyun #define WM8996_MCLK1_PD 0x0040 /* MCLK1_PD */ 3418*4882a593Smuzhiyun #define WM8996_MCLK1_PD_MASK 0x0040 /* MCLK1_PD */ 3419*4882a593Smuzhiyun #define WM8996_MCLK1_PD_SHIFT 6 /* MCLK1_PD */ 3420*4882a593Smuzhiyun #define WM8996_MCLK1_PD_WIDTH 1 /* MCLK1_PD */ 3421*4882a593Smuzhiyun #define WM8996_DACDAT1_PU 0x0020 /* DACDAT1_PU */ 3422*4882a593Smuzhiyun #define WM8996_DACDAT1_PU_MASK 0x0020 /* DACDAT1_PU */ 3423*4882a593Smuzhiyun #define WM8996_DACDAT1_PU_SHIFT 5 /* DACDAT1_PU */ 3424*4882a593Smuzhiyun #define WM8996_DACDAT1_PU_WIDTH 1 /* DACDAT1_PU */ 3425*4882a593Smuzhiyun #define WM8996_DACDAT1_PD 0x0010 /* DACDAT1_PD */ 3426*4882a593Smuzhiyun #define WM8996_DACDAT1_PD_MASK 0x0010 /* DACDAT1_PD */ 3427*4882a593Smuzhiyun #define WM8996_DACDAT1_PD_SHIFT 4 /* DACDAT1_PD */ 3428*4882a593Smuzhiyun #define WM8996_DACDAT1_PD_WIDTH 1 /* DACDAT1_PD */ 3429*4882a593Smuzhiyun #define WM8996_DACLRCLK1_PU 0x0008 /* DACLRCLK1_PU */ 3430*4882a593Smuzhiyun #define WM8996_DACLRCLK1_PU_MASK 0x0008 /* DACLRCLK1_PU */ 3431*4882a593Smuzhiyun #define WM8996_DACLRCLK1_PU_SHIFT 3 /* DACLRCLK1_PU */ 3432*4882a593Smuzhiyun #define WM8996_DACLRCLK1_PU_WIDTH 1 /* DACLRCLK1_PU */ 3433*4882a593Smuzhiyun #define WM8996_DACLRCLK1_PD 0x0004 /* DACLRCLK1_PD */ 3434*4882a593Smuzhiyun #define WM8996_DACLRCLK1_PD_MASK 0x0004 /* DACLRCLK1_PD */ 3435*4882a593Smuzhiyun #define WM8996_DACLRCLK1_PD_SHIFT 2 /* DACLRCLK1_PD */ 3436*4882a593Smuzhiyun #define WM8996_DACLRCLK1_PD_WIDTH 1 /* DACLRCLK1_PD */ 3437*4882a593Smuzhiyun #define WM8996_BCLK1_PU 0x0002 /* BCLK1_PU */ 3438*4882a593Smuzhiyun #define WM8996_BCLK1_PU_MASK 0x0002 /* BCLK1_PU */ 3439*4882a593Smuzhiyun #define WM8996_BCLK1_PU_SHIFT 1 /* BCLK1_PU */ 3440*4882a593Smuzhiyun #define WM8996_BCLK1_PU_WIDTH 1 /* BCLK1_PU */ 3441*4882a593Smuzhiyun #define WM8996_BCLK1_PD 0x0001 /* BCLK1_PD */ 3442*4882a593Smuzhiyun #define WM8996_BCLK1_PD_MASK 0x0001 /* BCLK1_PD */ 3443*4882a593Smuzhiyun #define WM8996_BCLK1_PD_SHIFT 0 /* BCLK1_PD */ 3444*4882a593Smuzhiyun #define WM8996_BCLK1_PD_WIDTH 1 /* BCLK1_PD */ 3445*4882a593Smuzhiyun 3446*4882a593Smuzhiyun /* 3447*4882a593Smuzhiyun * R1825 (0x721) - Pull Control (2) 3448*4882a593Smuzhiyun */ 3449*4882a593Smuzhiyun #define WM8996_LDO1ENA_PD 0x0100 /* LDO1ENA_PD */ 3450*4882a593Smuzhiyun #define WM8996_LDO1ENA_PD_MASK 0x0100 /* LDO1ENA_PD */ 3451*4882a593Smuzhiyun #define WM8996_LDO1ENA_PD_SHIFT 8 /* LDO1ENA_PD */ 3452*4882a593Smuzhiyun #define WM8996_LDO1ENA_PD_WIDTH 1 /* LDO1ENA_PD */ 3453*4882a593Smuzhiyun #define WM8996_ADDR_PD 0x0040 /* ADDR_PD */ 3454*4882a593Smuzhiyun #define WM8996_ADDR_PD_MASK 0x0040 /* ADDR_PD */ 3455*4882a593Smuzhiyun #define WM8996_ADDR_PD_SHIFT 6 /* ADDR_PD */ 3456*4882a593Smuzhiyun #define WM8996_ADDR_PD_WIDTH 1 /* ADDR_PD */ 3457*4882a593Smuzhiyun #define WM8996_DACDAT2_PU 0x0020 /* DACDAT2_PU */ 3458*4882a593Smuzhiyun #define WM8996_DACDAT2_PU_MASK 0x0020 /* DACDAT2_PU */ 3459*4882a593Smuzhiyun #define WM8996_DACDAT2_PU_SHIFT 5 /* DACDAT2_PU */ 3460*4882a593Smuzhiyun #define WM8996_DACDAT2_PU_WIDTH 1 /* DACDAT2_PU */ 3461*4882a593Smuzhiyun #define WM8996_DACDAT2_PD 0x0010 /* DACDAT2_PD */ 3462*4882a593Smuzhiyun #define WM8996_DACDAT2_PD_MASK 0x0010 /* DACDAT2_PD */ 3463*4882a593Smuzhiyun #define WM8996_DACDAT2_PD_SHIFT 4 /* DACDAT2_PD */ 3464*4882a593Smuzhiyun #define WM8996_DACDAT2_PD_WIDTH 1 /* DACDAT2_PD */ 3465*4882a593Smuzhiyun #define WM8996_DACLRCLK2_PU 0x0008 /* DACLRCLK2_PU */ 3466*4882a593Smuzhiyun #define WM8996_DACLRCLK2_PU_MASK 0x0008 /* DACLRCLK2_PU */ 3467*4882a593Smuzhiyun #define WM8996_DACLRCLK2_PU_SHIFT 3 /* DACLRCLK2_PU */ 3468*4882a593Smuzhiyun #define WM8996_DACLRCLK2_PU_WIDTH 1 /* DACLRCLK2_PU */ 3469*4882a593Smuzhiyun #define WM8996_DACLRCLK2_PD 0x0004 /* DACLRCLK2_PD */ 3470*4882a593Smuzhiyun #define WM8996_DACLRCLK2_PD_MASK 0x0004 /* DACLRCLK2_PD */ 3471*4882a593Smuzhiyun #define WM8996_DACLRCLK2_PD_SHIFT 2 /* DACLRCLK2_PD */ 3472*4882a593Smuzhiyun #define WM8996_DACLRCLK2_PD_WIDTH 1 /* DACLRCLK2_PD */ 3473*4882a593Smuzhiyun #define WM8996_BCLK2_PU 0x0002 /* BCLK2_PU */ 3474*4882a593Smuzhiyun #define WM8996_BCLK2_PU_MASK 0x0002 /* BCLK2_PU */ 3475*4882a593Smuzhiyun #define WM8996_BCLK2_PU_SHIFT 1 /* BCLK2_PU */ 3476*4882a593Smuzhiyun #define WM8996_BCLK2_PU_WIDTH 1 /* BCLK2_PU */ 3477*4882a593Smuzhiyun #define WM8996_BCLK2_PD 0x0001 /* BCLK2_PD */ 3478*4882a593Smuzhiyun #define WM8996_BCLK2_PD_MASK 0x0001 /* BCLK2_PD */ 3479*4882a593Smuzhiyun #define WM8996_BCLK2_PD_SHIFT 0 /* BCLK2_PD */ 3480*4882a593Smuzhiyun #define WM8996_BCLK2_PD_WIDTH 1 /* BCLK2_PD */ 3481*4882a593Smuzhiyun 3482*4882a593Smuzhiyun /* 3483*4882a593Smuzhiyun * R1840 (0x730) - Interrupt Status 1 3484*4882a593Smuzhiyun */ 3485*4882a593Smuzhiyun #define WM8996_GP5_EINT 0x0010 /* GP5_EINT */ 3486*4882a593Smuzhiyun #define WM8996_GP5_EINT_MASK 0x0010 /* GP5_EINT */ 3487*4882a593Smuzhiyun #define WM8996_GP5_EINT_SHIFT 4 /* GP5_EINT */ 3488*4882a593Smuzhiyun #define WM8996_GP5_EINT_WIDTH 1 /* GP5_EINT */ 3489*4882a593Smuzhiyun #define WM8996_GP4_EINT 0x0008 /* GP4_EINT */ 3490*4882a593Smuzhiyun #define WM8996_GP4_EINT_MASK 0x0008 /* GP4_EINT */ 3491*4882a593Smuzhiyun #define WM8996_GP4_EINT_SHIFT 3 /* GP4_EINT */ 3492*4882a593Smuzhiyun #define WM8996_GP4_EINT_WIDTH 1 /* GP4_EINT */ 3493*4882a593Smuzhiyun #define WM8996_GP3_EINT 0x0004 /* GP3_EINT */ 3494*4882a593Smuzhiyun #define WM8996_GP3_EINT_MASK 0x0004 /* GP3_EINT */ 3495*4882a593Smuzhiyun #define WM8996_GP3_EINT_SHIFT 2 /* GP3_EINT */ 3496*4882a593Smuzhiyun #define WM8996_GP3_EINT_WIDTH 1 /* GP3_EINT */ 3497*4882a593Smuzhiyun #define WM8996_GP2_EINT 0x0002 /* GP2_EINT */ 3498*4882a593Smuzhiyun #define WM8996_GP2_EINT_MASK 0x0002 /* GP2_EINT */ 3499*4882a593Smuzhiyun #define WM8996_GP2_EINT_SHIFT 1 /* GP2_EINT */ 3500*4882a593Smuzhiyun #define WM8996_GP2_EINT_WIDTH 1 /* GP2_EINT */ 3501*4882a593Smuzhiyun #define WM8996_GP1_EINT 0x0001 /* GP1_EINT */ 3502*4882a593Smuzhiyun #define WM8996_GP1_EINT_MASK 0x0001 /* GP1_EINT */ 3503*4882a593Smuzhiyun #define WM8996_GP1_EINT_SHIFT 0 /* GP1_EINT */ 3504*4882a593Smuzhiyun #define WM8996_GP1_EINT_WIDTH 1 /* GP1_EINT */ 3505*4882a593Smuzhiyun 3506*4882a593Smuzhiyun /* 3507*4882a593Smuzhiyun * R1841 (0x731) - Interrupt Status 2 3508*4882a593Smuzhiyun */ 3509*4882a593Smuzhiyun #define WM8996_DCS_DONE_23_EINT 0x1000 /* DCS_DONE_23_EINT */ 3510*4882a593Smuzhiyun #define WM8996_DCS_DONE_23_EINT_MASK 0x1000 /* DCS_DONE_23_EINT */ 3511*4882a593Smuzhiyun #define WM8996_DCS_DONE_23_EINT_SHIFT 12 /* DCS_DONE_23_EINT */ 3512*4882a593Smuzhiyun #define WM8996_DCS_DONE_23_EINT_WIDTH 1 /* DCS_DONE_23_EINT */ 3513*4882a593Smuzhiyun #define WM8996_DCS_DONE_01_EINT 0x0800 /* DCS_DONE_01_EINT */ 3514*4882a593Smuzhiyun #define WM8996_DCS_DONE_01_EINT_MASK 0x0800 /* DCS_DONE_01_EINT */ 3515*4882a593Smuzhiyun #define WM8996_DCS_DONE_01_EINT_SHIFT 11 /* DCS_DONE_01_EINT */ 3516*4882a593Smuzhiyun #define WM8996_DCS_DONE_01_EINT_WIDTH 1 /* DCS_DONE_01_EINT */ 3517*4882a593Smuzhiyun #define WM8996_WSEQ_DONE_EINT 0x0400 /* WSEQ_DONE_EINT */ 3518*4882a593Smuzhiyun #define WM8996_WSEQ_DONE_EINT_MASK 0x0400 /* WSEQ_DONE_EINT */ 3519*4882a593Smuzhiyun #define WM8996_WSEQ_DONE_EINT_SHIFT 10 /* WSEQ_DONE_EINT */ 3520*4882a593Smuzhiyun #define WM8996_WSEQ_DONE_EINT_WIDTH 1 /* WSEQ_DONE_EINT */ 3521*4882a593Smuzhiyun #define WM8996_FIFOS_ERR_EINT 0x0200 /* FIFOS_ERR_EINT */ 3522*4882a593Smuzhiyun #define WM8996_FIFOS_ERR_EINT_MASK 0x0200 /* FIFOS_ERR_EINT */ 3523*4882a593Smuzhiyun #define WM8996_FIFOS_ERR_EINT_SHIFT 9 /* FIFOS_ERR_EINT */ 3524*4882a593Smuzhiyun #define WM8996_FIFOS_ERR_EINT_WIDTH 1 /* FIFOS_ERR_EINT */ 3525*4882a593Smuzhiyun #define WM8996_DSP2DRC_SIG_DET_EINT 0x0080 /* DSP2DRC_SIG_DET_EINT */ 3526*4882a593Smuzhiyun #define WM8996_DSP2DRC_SIG_DET_EINT_MASK 0x0080 /* DSP2DRC_SIG_DET_EINT */ 3527*4882a593Smuzhiyun #define WM8996_DSP2DRC_SIG_DET_EINT_SHIFT 7 /* DSP2DRC_SIG_DET_EINT */ 3528*4882a593Smuzhiyun #define WM8996_DSP2DRC_SIG_DET_EINT_WIDTH 1 /* DSP2DRC_SIG_DET_EINT */ 3529*4882a593Smuzhiyun #define WM8996_DSP1DRC_SIG_DET_EINT 0x0040 /* DSP1DRC_SIG_DET_EINT */ 3530*4882a593Smuzhiyun #define WM8996_DSP1DRC_SIG_DET_EINT_MASK 0x0040 /* DSP1DRC_SIG_DET_EINT */ 3531*4882a593Smuzhiyun #define WM8996_DSP1DRC_SIG_DET_EINT_SHIFT 6 /* DSP1DRC_SIG_DET_EINT */ 3532*4882a593Smuzhiyun #define WM8996_DSP1DRC_SIG_DET_EINT_WIDTH 1 /* DSP1DRC_SIG_DET_EINT */ 3533*4882a593Smuzhiyun #define WM8996_FLL_SW_CLK_DONE_EINT 0x0008 /* FLL_SW_CLK_DONE_EINT */ 3534*4882a593Smuzhiyun #define WM8996_FLL_SW_CLK_DONE_EINT_MASK 0x0008 /* FLL_SW_CLK_DONE_EINT */ 3535*4882a593Smuzhiyun #define WM8996_FLL_SW_CLK_DONE_EINT_SHIFT 3 /* FLL_SW_CLK_DONE_EINT */ 3536*4882a593Smuzhiyun #define WM8996_FLL_SW_CLK_DONE_EINT_WIDTH 1 /* FLL_SW_CLK_DONE_EINT */ 3537*4882a593Smuzhiyun #define WM8996_FLL_LOCK_EINT 0x0004 /* FLL_LOCK_EINT */ 3538*4882a593Smuzhiyun #define WM8996_FLL_LOCK_EINT_MASK 0x0004 /* FLL_LOCK_EINT */ 3539*4882a593Smuzhiyun #define WM8996_FLL_LOCK_EINT_SHIFT 2 /* FLL_LOCK_EINT */ 3540*4882a593Smuzhiyun #define WM8996_FLL_LOCK_EINT_WIDTH 1 /* FLL_LOCK_EINT */ 3541*4882a593Smuzhiyun #define WM8996_HP_DONE_EINT 0x0002 /* HP_DONE_EINT */ 3542*4882a593Smuzhiyun #define WM8996_HP_DONE_EINT_MASK 0x0002 /* HP_DONE_EINT */ 3543*4882a593Smuzhiyun #define WM8996_HP_DONE_EINT_SHIFT 1 /* HP_DONE_EINT */ 3544*4882a593Smuzhiyun #define WM8996_HP_DONE_EINT_WIDTH 1 /* HP_DONE_EINT */ 3545*4882a593Smuzhiyun #define WM8996_MICD_EINT 0x0001 /* MICD_EINT */ 3546*4882a593Smuzhiyun #define WM8996_MICD_EINT_MASK 0x0001 /* MICD_EINT */ 3547*4882a593Smuzhiyun #define WM8996_MICD_EINT_SHIFT 0 /* MICD_EINT */ 3548*4882a593Smuzhiyun #define WM8996_MICD_EINT_WIDTH 1 /* MICD_EINT */ 3549*4882a593Smuzhiyun 3550*4882a593Smuzhiyun /* 3551*4882a593Smuzhiyun * R1842 (0x732) - Interrupt Raw Status 2 3552*4882a593Smuzhiyun */ 3553*4882a593Smuzhiyun #define WM8996_DCS_DONE_23_STS 0x1000 /* DCS_DONE_23_STS */ 3554*4882a593Smuzhiyun #define WM8996_DCS_DONE_23_STS_MASK 0x1000 /* DCS_DONE_23_STS */ 3555*4882a593Smuzhiyun #define WM8996_DCS_DONE_23_STS_SHIFT 12 /* DCS_DONE_23_STS */ 3556*4882a593Smuzhiyun #define WM8996_DCS_DONE_23_STS_WIDTH 1 /* DCS_DONE_23_STS */ 3557*4882a593Smuzhiyun #define WM8996_DCS_DONE_01_STS 0x0800 /* DCS_DONE_01_STS */ 3558*4882a593Smuzhiyun #define WM8996_DCS_DONE_01_STS_MASK 0x0800 /* DCS_DONE_01_STS */ 3559*4882a593Smuzhiyun #define WM8996_DCS_DONE_01_STS_SHIFT 11 /* DCS_DONE_01_STS */ 3560*4882a593Smuzhiyun #define WM8996_DCS_DONE_01_STS_WIDTH 1 /* DCS_DONE_01_STS */ 3561*4882a593Smuzhiyun #define WM8996_WSEQ_DONE_STS 0x0400 /* WSEQ_DONE_STS */ 3562*4882a593Smuzhiyun #define WM8996_WSEQ_DONE_STS_MASK 0x0400 /* WSEQ_DONE_STS */ 3563*4882a593Smuzhiyun #define WM8996_WSEQ_DONE_STS_SHIFT 10 /* WSEQ_DONE_STS */ 3564*4882a593Smuzhiyun #define WM8996_WSEQ_DONE_STS_WIDTH 1 /* WSEQ_DONE_STS */ 3565*4882a593Smuzhiyun #define WM8996_FIFOS_ERR_STS 0x0200 /* FIFOS_ERR_STS */ 3566*4882a593Smuzhiyun #define WM8996_FIFOS_ERR_STS_MASK 0x0200 /* FIFOS_ERR_STS */ 3567*4882a593Smuzhiyun #define WM8996_FIFOS_ERR_STS_SHIFT 9 /* FIFOS_ERR_STS */ 3568*4882a593Smuzhiyun #define WM8996_FIFOS_ERR_STS_WIDTH 1 /* FIFOS_ERR_STS */ 3569*4882a593Smuzhiyun #define WM8996_DSP2DRC_SIG_DET_STS 0x0080 /* DSP2DRC_SIG_DET_STS */ 3570*4882a593Smuzhiyun #define WM8996_DSP2DRC_SIG_DET_STS_MASK 0x0080 /* DSP2DRC_SIG_DET_STS */ 3571*4882a593Smuzhiyun #define WM8996_DSP2DRC_SIG_DET_STS_SHIFT 7 /* DSP2DRC_SIG_DET_STS */ 3572*4882a593Smuzhiyun #define WM8996_DSP2DRC_SIG_DET_STS_WIDTH 1 /* DSP2DRC_SIG_DET_STS */ 3573*4882a593Smuzhiyun #define WM8996_DSP1DRC_SIG_DET_STS 0x0040 /* DSP1DRC_SIG_DET_STS */ 3574*4882a593Smuzhiyun #define WM8996_DSP1DRC_SIG_DET_STS_MASK 0x0040 /* DSP1DRC_SIG_DET_STS */ 3575*4882a593Smuzhiyun #define WM8996_DSP1DRC_SIG_DET_STS_SHIFT 6 /* DSP1DRC_SIG_DET_STS */ 3576*4882a593Smuzhiyun #define WM8996_DSP1DRC_SIG_DET_STS_WIDTH 1 /* DSP1DRC_SIG_DET_STS */ 3577*4882a593Smuzhiyun #define WM8996_FLL_LOCK_STS 0x0004 /* FLL_LOCK_STS */ 3578*4882a593Smuzhiyun #define WM8996_FLL_LOCK_STS_MASK 0x0004 /* FLL_LOCK_STS */ 3579*4882a593Smuzhiyun #define WM8996_FLL_LOCK_STS_SHIFT 2 /* FLL_LOCK_STS */ 3580*4882a593Smuzhiyun #define WM8996_FLL_LOCK_STS_WIDTH 1 /* FLL_LOCK_STS */ 3581*4882a593Smuzhiyun 3582*4882a593Smuzhiyun /* 3583*4882a593Smuzhiyun * R1848 (0x738) - Interrupt Status 1 Mask 3584*4882a593Smuzhiyun */ 3585*4882a593Smuzhiyun #define WM8996_IM_GP5_EINT 0x0010 /* IM_GP5_EINT */ 3586*4882a593Smuzhiyun #define WM8996_IM_GP5_EINT_MASK 0x0010 /* IM_GP5_EINT */ 3587*4882a593Smuzhiyun #define WM8996_IM_GP5_EINT_SHIFT 4 /* IM_GP5_EINT */ 3588*4882a593Smuzhiyun #define WM8996_IM_GP5_EINT_WIDTH 1 /* IM_GP5_EINT */ 3589*4882a593Smuzhiyun #define WM8996_IM_GP4_EINT 0x0008 /* IM_GP4_EINT */ 3590*4882a593Smuzhiyun #define WM8996_IM_GP4_EINT_MASK 0x0008 /* IM_GP4_EINT */ 3591*4882a593Smuzhiyun #define WM8996_IM_GP4_EINT_SHIFT 3 /* IM_GP4_EINT */ 3592*4882a593Smuzhiyun #define WM8996_IM_GP4_EINT_WIDTH 1 /* IM_GP4_EINT */ 3593*4882a593Smuzhiyun #define WM8996_IM_GP3_EINT 0x0004 /* IM_GP3_EINT */ 3594*4882a593Smuzhiyun #define WM8996_IM_GP3_EINT_MASK 0x0004 /* IM_GP3_EINT */ 3595*4882a593Smuzhiyun #define WM8996_IM_GP3_EINT_SHIFT 2 /* IM_GP3_EINT */ 3596*4882a593Smuzhiyun #define WM8996_IM_GP3_EINT_WIDTH 1 /* IM_GP3_EINT */ 3597*4882a593Smuzhiyun #define WM8996_IM_GP2_EINT 0x0002 /* IM_GP2_EINT */ 3598*4882a593Smuzhiyun #define WM8996_IM_GP2_EINT_MASK 0x0002 /* IM_GP2_EINT */ 3599*4882a593Smuzhiyun #define WM8996_IM_GP2_EINT_SHIFT 1 /* IM_GP2_EINT */ 3600*4882a593Smuzhiyun #define WM8996_IM_GP2_EINT_WIDTH 1 /* IM_GP2_EINT */ 3601*4882a593Smuzhiyun #define WM8996_IM_GP1_EINT 0x0001 /* IM_GP1_EINT */ 3602*4882a593Smuzhiyun #define WM8996_IM_GP1_EINT_MASK 0x0001 /* IM_GP1_EINT */ 3603*4882a593Smuzhiyun #define WM8996_IM_GP1_EINT_SHIFT 0 /* IM_GP1_EINT */ 3604*4882a593Smuzhiyun #define WM8996_IM_GP1_EINT_WIDTH 1 /* IM_GP1_EINT */ 3605*4882a593Smuzhiyun 3606*4882a593Smuzhiyun /* 3607*4882a593Smuzhiyun * R1849 (0x739) - Interrupt Status 2 Mask 3608*4882a593Smuzhiyun */ 3609*4882a593Smuzhiyun #define WM8996_IM_DCS_DONE_23_EINT 0x1000 /* IM_DCS_DONE_23_EINT */ 3610*4882a593Smuzhiyun #define WM8996_IM_DCS_DONE_23_EINT_MASK 0x1000 /* IM_DCS_DONE_23_EINT */ 3611*4882a593Smuzhiyun #define WM8996_IM_DCS_DONE_23_EINT_SHIFT 12 /* IM_DCS_DONE_23_EINT */ 3612*4882a593Smuzhiyun #define WM8996_IM_DCS_DONE_23_EINT_WIDTH 1 /* IM_DCS_DONE_23_EINT */ 3613*4882a593Smuzhiyun #define WM8996_IM_DCS_DONE_01_EINT 0x0800 /* IM_DCS_DONE_01_EINT */ 3614*4882a593Smuzhiyun #define WM8996_IM_DCS_DONE_01_EINT_MASK 0x0800 /* IM_DCS_DONE_01_EINT */ 3615*4882a593Smuzhiyun #define WM8996_IM_DCS_DONE_01_EINT_SHIFT 11 /* IM_DCS_DONE_01_EINT */ 3616*4882a593Smuzhiyun #define WM8996_IM_DCS_DONE_01_EINT_WIDTH 1 /* IM_DCS_DONE_01_EINT */ 3617*4882a593Smuzhiyun #define WM8996_IM_WSEQ_DONE_EINT 0x0400 /* IM_WSEQ_DONE_EINT */ 3618*4882a593Smuzhiyun #define WM8996_IM_WSEQ_DONE_EINT_MASK 0x0400 /* IM_WSEQ_DONE_EINT */ 3619*4882a593Smuzhiyun #define WM8996_IM_WSEQ_DONE_EINT_SHIFT 10 /* IM_WSEQ_DONE_EINT */ 3620*4882a593Smuzhiyun #define WM8996_IM_WSEQ_DONE_EINT_WIDTH 1 /* IM_WSEQ_DONE_EINT */ 3621*4882a593Smuzhiyun #define WM8996_IM_FIFOS_ERR_EINT 0x0200 /* IM_FIFOS_ERR_EINT */ 3622*4882a593Smuzhiyun #define WM8996_IM_FIFOS_ERR_EINT_MASK 0x0200 /* IM_FIFOS_ERR_EINT */ 3623*4882a593Smuzhiyun #define WM8996_IM_FIFOS_ERR_EINT_SHIFT 9 /* IM_FIFOS_ERR_EINT */ 3624*4882a593Smuzhiyun #define WM8996_IM_FIFOS_ERR_EINT_WIDTH 1 /* IM_FIFOS_ERR_EINT */ 3625*4882a593Smuzhiyun #define WM8996_IM_DSP2DRC_SIG_DET_EINT 0x0080 /* IM_DSP2DRC_SIG_DET_EINT */ 3626*4882a593Smuzhiyun #define WM8996_IM_DSP2DRC_SIG_DET_EINT_MASK 0x0080 /* IM_DSP2DRC_SIG_DET_EINT */ 3627*4882a593Smuzhiyun #define WM8996_IM_DSP2DRC_SIG_DET_EINT_SHIFT 7 /* IM_DSP2DRC_SIG_DET_EINT */ 3628*4882a593Smuzhiyun #define WM8996_IM_DSP2DRC_SIG_DET_EINT_WIDTH 1 /* IM_DSP2DRC_SIG_DET_EINT */ 3629*4882a593Smuzhiyun #define WM8996_IM_DSP1DRC_SIG_DET_EINT 0x0040 /* IM_DSP1DRC_SIG_DET_EINT */ 3630*4882a593Smuzhiyun #define WM8996_IM_DSP1DRC_SIG_DET_EINT_MASK 0x0040 /* IM_DSP1DRC_SIG_DET_EINT */ 3631*4882a593Smuzhiyun #define WM8996_IM_DSP1DRC_SIG_DET_EINT_SHIFT 6 /* IM_DSP1DRC_SIG_DET_EINT */ 3632*4882a593Smuzhiyun #define WM8996_IM_DSP1DRC_SIG_DET_EINT_WIDTH 1 /* IM_DSP1DRC_SIG_DET_EINT */ 3633*4882a593Smuzhiyun #define WM8996_IM_FLL_SW_CLK_DONE_EINT 0x0008 /* IM_FLL_SW_CLK_DONE_EINT */ 3634*4882a593Smuzhiyun #define WM8996_IM_FLL_SW_CLK_DONE_EINT_MASK 0x0008 /* IM_FLL_SW_CLK_DONE_EINT */ 3635*4882a593Smuzhiyun #define WM8996_IM_FLL_SW_CLK_DONE_EINT_SHIFT 3 /* IM_FLL_SW_CLK_DONE_EINT */ 3636*4882a593Smuzhiyun #define WM8996_IM_FLL_SW_CLK_DONE_EINT_WIDTH 1 /* IM_FLL_SW_CLK_DONE_EINT */ 3637*4882a593Smuzhiyun #define WM8996_IM_FLL_LOCK_EINT 0x0004 /* IM_FLL_LOCK_EINT */ 3638*4882a593Smuzhiyun #define WM8996_IM_FLL_LOCK_EINT_MASK 0x0004 /* IM_FLL_LOCK_EINT */ 3639*4882a593Smuzhiyun #define WM8996_IM_FLL_LOCK_EINT_SHIFT 2 /* IM_FLL_LOCK_EINT */ 3640*4882a593Smuzhiyun #define WM8996_IM_FLL_LOCK_EINT_WIDTH 1 /* IM_FLL_LOCK_EINT */ 3641*4882a593Smuzhiyun #define WM8996_IM_HP_DONE_EINT 0x0002 /* IM_HP_DONE_EINT */ 3642*4882a593Smuzhiyun #define WM8996_IM_HP_DONE_EINT_MASK 0x0002 /* IM_HP_DONE_EINT */ 3643*4882a593Smuzhiyun #define WM8996_IM_HP_DONE_EINT_SHIFT 1 /* IM_HP_DONE_EINT */ 3644*4882a593Smuzhiyun #define WM8996_IM_HP_DONE_EINT_WIDTH 1 /* IM_HP_DONE_EINT */ 3645*4882a593Smuzhiyun #define WM8996_IM_MICD_EINT 0x0001 /* IM_MICD_EINT */ 3646*4882a593Smuzhiyun #define WM8996_IM_MICD_EINT_MASK 0x0001 /* IM_MICD_EINT */ 3647*4882a593Smuzhiyun #define WM8996_IM_MICD_EINT_SHIFT 0 /* IM_MICD_EINT */ 3648*4882a593Smuzhiyun #define WM8996_IM_MICD_EINT_WIDTH 1 /* IM_MICD_EINT */ 3649*4882a593Smuzhiyun 3650*4882a593Smuzhiyun /* 3651*4882a593Smuzhiyun * R1856 (0x740) - Interrupt Control 3652*4882a593Smuzhiyun */ 3653*4882a593Smuzhiyun #define WM8996_IM_IRQ 0x0001 /* IM_IRQ */ 3654*4882a593Smuzhiyun #define WM8996_IM_IRQ_MASK 0x0001 /* IM_IRQ */ 3655*4882a593Smuzhiyun #define WM8996_IM_IRQ_SHIFT 0 /* IM_IRQ */ 3656*4882a593Smuzhiyun #define WM8996_IM_IRQ_WIDTH 1 /* IM_IRQ */ 3657*4882a593Smuzhiyun 3658*4882a593Smuzhiyun /* 3659*4882a593Smuzhiyun * R2048 (0x800) - Left PDM Speaker 3660*4882a593Smuzhiyun */ 3661*4882a593Smuzhiyun #define WM8996_SPKL_ENA 0x0010 /* SPKL_ENA */ 3662*4882a593Smuzhiyun #define WM8996_SPKL_ENA_MASK 0x0010 /* SPKL_ENA */ 3663*4882a593Smuzhiyun #define WM8996_SPKL_ENA_SHIFT 4 /* SPKL_ENA */ 3664*4882a593Smuzhiyun #define WM8996_SPKL_ENA_WIDTH 1 /* SPKL_ENA */ 3665*4882a593Smuzhiyun #define WM8996_SPKL_MUTE 0x0008 /* SPKL_MUTE */ 3666*4882a593Smuzhiyun #define WM8996_SPKL_MUTE_MASK 0x0008 /* SPKL_MUTE */ 3667*4882a593Smuzhiyun #define WM8996_SPKL_MUTE_SHIFT 3 /* SPKL_MUTE */ 3668*4882a593Smuzhiyun #define WM8996_SPKL_MUTE_WIDTH 1 /* SPKL_MUTE */ 3669*4882a593Smuzhiyun #define WM8996_SPKL_MUTE_ZC 0x0004 /* SPKL_MUTE_ZC */ 3670*4882a593Smuzhiyun #define WM8996_SPKL_MUTE_ZC_MASK 0x0004 /* SPKL_MUTE_ZC */ 3671*4882a593Smuzhiyun #define WM8996_SPKL_MUTE_ZC_SHIFT 2 /* SPKL_MUTE_ZC */ 3672*4882a593Smuzhiyun #define WM8996_SPKL_MUTE_ZC_WIDTH 1 /* SPKL_MUTE_ZC */ 3673*4882a593Smuzhiyun #define WM8996_SPKL_SRC_MASK 0x0003 /* SPKL_SRC - [1:0] */ 3674*4882a593Smuzhiyun #define WM8996_SPKL_SRC_SHIFT 0 /* SPKL_SRC - [1:0] */ 3675*4882a593Smuzhiyun #define WM8996_SPKL_SRC_WIDTH 2 /* SPKL_SRC - [1:0] */ 3676*4882a593Smuzhiyun 3677*4882a593Smuzhiyun /* 3678*4882a593Smuzhiyun * R2049 (0x801) - Right PDM Speaker 3679*4882a593Smuzhiyun */ 3680*4882a593Smuzhiyun #define WM8996_SPKR_ENA 0x0010 /* SPKR_ENA */ 3681*4882a593Smuzhiyun #define WM8996_SPKR_ENA_MASK 0x0010 /* SPKR_ENA */ 3682*4882a593Smuzhiyun #define WM8996_SPKR_ENA_SHIFT 4 /* SPKR_ENA */ 3683*4882a593Smuzhiyun #define WM8996_SPKR_ENA_WIDTH 1 /* SPKR_ENA */ 3684*4882a593Smuzhiyun #define WM8996_SPKR_MUTE 0x0008 /* SPKR_MUTE */ 3685*4882a593Smuzhiyun #define WM8996_SPKR_MUTE_MASK 0x0008 /* SPKR_MUTE */ 3686*4882a593Smuzhiyun #define WM8996_SPKR_MUTE_SHIFT 3 /* SPKR_MUTE */ 3687*4882a593Smuzhiyun #define WM8996_SPKR_MUTE_WIDTH 1 /* SPKR_MUTE */ 3688*4882a593Smuzhiyun #define WM8996_SPKR_MUTE_ZC 0x0004 /* SPKR_MUTE_ZC */ 3689*4882a593Smuzhiyun #define WM8996_SPKR_MUTE_ZC_MASK 0x0004 /* SPKR_MUTE_ZC */ 3690*4882a593Smuzhiyun #define WM8996_SPKR_MUTE_ZC_SHIFT 2 /* SPKR_MUTE_ZC */ 3691*4882a593Smuzhiyun #define WM8996_SPKR_MUTE_ZC_WIDTH 1 /* SPKR_MUTE_ZC */ 3692*4882a593Smuzhiyun #define WM8996_SPKR_SRC_MASK 0x0003 /* SPKR_SRC - [1:0] */ 3693*4882a593Smuzhiyun #define WM8996_SPKR_SRC_SHIFT 0 /* SPKR_SRC - [1:0] */ 3694*4882a593Smuzhiyun #define WM8996_SPKR_SRC_WIDTH 2 /* SPKR_SRC - [1:0] */ 3695*4882a593Smuzhiyun 3696*4882a593Smuzhiyun /* 3697*4882a593Smuzhiyun * R2050 (0x802) - PDM Speaker Mute Sequence 3698*4882a593Smuzhiyun */ 3699*4882a593Smuzhiyun #define WM8996_SPK_MUTE_ENDIAN 0x0100 /* SPK_MUTE_ENDIAN */ 3700*4882a593Smuzhiyun #define WM8996_SPK_MUTE_ENDIAN_MASK 0x0100 /* SPK_MUTE_ENDIAN */ 3701*4882a593Smuzhiyun #define WM8996_SPK_MUTE_ENDIAN_SHIFT 8 /* SPK_MUTE_ENDIAN */ 3702*4882a593Smuzhiyun #define WM8996_SPK_MUTE_ENDIAN_WIDTH 1 /* SPK_MUTE_ENDIAN */ 3703*4882a593Smuzhiyun #define WM8996_SPK_MUTE_SEQ1_MASK 0x00FF /* SPK_MUTE_SEQ1 - [7:0] */ 3704*4882a593Smuzhiyun #define WM8996_SPK_MUTE_SEQ1_SHIFT 0 /* SPK_MUTE_SEQ1 - [7:0] */ 3705*4882a593Smuzhiyun #define WM8996_SPK_MUTE_SEQ1_WIDTH 8 /* SPK_MUTE_SEQ1 - [7:0] */ 3706*4882a593Smuzhiyun 3707*4882a593Smuzhiyun /* 3708*4882a593Smuzhiyun * R2051 (0x803) - PDM Speaker Volume 3709*4882a593Smuzhiyun */ 3710*4882a593Smuzhiyun #define WM8996_SPKR_VOL_MASK 0x00F0 /* SPKR_VOL - [7:4] */ 3711*4882a593Smuzhiyun #define WM8996_SPKR_VOL_SHIFT 4 /* SPKR_VOL - [7:4] */ 3712*4882a593Smuzhiyun #define WM8996_SPKR_VOL_WIDTH 4 /* SPKR_VOL - [7:4] */ 3713*4882a593Smuzhiyun #define WM8996_SPKL_VOL_MASK 0x000F /* SPKL_VOL - [3:0] */ 3714*4882a593Smuzhiyun #define WM8996_SPKL_VOL_SHIFT 0 /* SPKL_VOL - [3:0] */ 3715*4882a593Smuzhiyun #define WM8996_SPKL_VOL_WIDTH 4 /* SPKL_VOL - [3:0] */ 3716*4882a593Smuzhiyun 3717*4882a593Smuzhiyun #endif 3718