1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * wm8995.h -- WM8995 ALSA SoC Audio driver 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright 2010 Wolfson Microelectronics plc 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Author: Dimitris Papastamos <dp@opensource.wolfsonmicro.com> 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef _WM8995_H 11*4882a593Smuzhiyun #define _WM8995_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #include <asm/types.h> 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /* 16*4882a593Smuzhiyun * Register values. 17*4882a593Smuzhiyun */ 18*4882a593Smuzhiyun #define WM8995_SOFTWARE_RESET 0x00 19*4882a593Smuzhiyun #define WM8995_POWER_MANAGEMENT_1 0x01 20*4882a593Smuzhiyun #define WM8995_POWER_MANAGEMENT_2 0x02 21*4882a593Smuzhiyun #define WM8995_POWER_MANAGEMENT_3 0x03 22*4882a593Smuzhiyun #define WM8995_POWER_MANAGEMENT_4 0x04 23*4882a593Smuzhiyun #define WM8995_POWER_MANAGEMENT_5 0x05 24*4882a593Smuzhiyun #define WM8995_LEFT_LINE_INPUT_1_VOLUME 0x10 25*4882a593Smuzhiyun #define WM8995_RIGHT_LINE_INPUT_1_VOLUME 0x11 26*4882a593Smuzhiyun #define WM8995_LEFT_LINE_INPUT_CONTROL 0x12 27*4882a593Smuzhiyun #define WM8995_DAC1_LEFT_VOLUME 0x18 28*4882a593Smuzhiyun #define WM8995_DAC1_RIGHT_VOLUME 0x19 29*4882a593Smuzhiyun #define WM8995_DAC2_LEFT_VOLUME 0x1A 30*4882a593Smuzhiyun #define WM8995_DAC2_RIGHT_VOLUME 0x1B 31*4882a593Smuzhiyun #define WM8995_OUTPUT_VOLUME_ZC_1 0x1C 32*4882a593Smuzhiyun #define WM8995_MICBIAS_1 0x20 33*4882a593Smuzhiyun #define WM8995_MICBIAS_2 0x21 34*4882a593Smuzhiyun #define WM8995_LDO_1 0x28 35*4882a593Smuzhiyun #define WM8995_LDO_2 0x29 36*4882a593Smuzhiyun #define WM8995_ACCESSORY_DETECT_MODE1 0x30 37*4882a593Smuzhiyun #define WM8995_ACCESSORY_DETECT_MODE2 0x31 38*4882a593Smuzhiyun #define WM8995_HEADPHONE_DETECT1 0x34 39*4882a593Smuzhiyun #define WM8995_HEADPHONE_DETECT2 0x35 40*4882a593Smuzhiyun #define WM8995_MIC_DETECT_1 0x38 41*4882a593Smuzhiyun #define WM8995_MIC_DETECT_2 0x39 42*4882a593Smuzhiyun #define WM8995_CHARGE_PUMP_1 0x40 43*4882a593Smuzhiyun #define WM8995_CLASS_W_1 0x45 44*4882a593Smuzhiyun #define WM8995_DC_SERVO_1 0x50 45*4882a593Smuzhiyun #define WM8995_DC_SERVO_2 0x51 46*4882a593Smuzhiyun #define WM8995_DC_SERVO_3 0x52 47*4882a593Smuzhiyun #define WM8995_DC_SERVO_5 0x54 48*4882a593Smuzhiyun #define WM8995_DC_SERVO_6 0x55 49*4882a593Smuzhiyun #define WM8995_DC_SERVO_7 0x56 50*4882a593Smuzhiyun #define WM8995_DC_SERVO_READBACK_0 0x57 51*4882a593Smuzhiyun #define WM8995_ANALOGUE_HP_1 0x60 52*4882a593Smuzhiyun #define WM8995_ANALOGUE_HP_2 0x61 53*4882a593Smuzhiyun #define WM8995_CHIP_REVISION 0x100 54*4882a593Smuzhiyun #define WM8995_CONTROL_INTERFACE_1 0x101 55*4882a593Smuzhiyun #define WM8995_CONTROL_INTERFACE_2 0x102 56*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_CTRL_1 0x110 57*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_CTRL_2 0x111 58*4882a593Smuzhiyun #define WM8995_AIF1_CLOCKING_1 0x200 59*4882a593Smuzhiyun #define WM8995_AIF1_CLOCKING_2 0x201 60*4882a593Smuzhiyun #define WM8995_AIF2_CLOCKING_1 0x204 61*4882a593Smuzhiyun #define WM8995_AIF2_CLOCKING_2 0x205 62*4882a593Smuzhiyun #define WM8995_CLOCKING_1 0x208 63*4882a593Smuzhiyun #define WM8995_CLOCKING_2 0x209 64*4882a593Smuzhiyun #define WM8995_AIF1_RATE 0x210 65*4882a593Smuzhiyun #define WM8995_AIF2_RATE 0x211 66*4882a593Smuzhiyun #define WM8995_RATE_STATUS 0x212 67*4882a593Smuzhiyun #define WM8995_FLL1_CONTROL_1 0x220 68*4882a593Smuzhiyun #define WM8995_FLL1_CONTROL_2 0x221 69*4882a593Smuzhiyun #define WM8995_FLL1_CONTROL_3 0x222 70*4882a593Smuzhiyun #define WM8995_FLL1_CONTROL_4 0x223 71*4882a593Smuzhiyun #define WM8995_FLL1_CONTROL_5 0x224 72*4882a593Smuzhiyun #define WM8995_FLL2_CONTROL_1 0x240 73*4882a593Smuzhiyun #define WM8995_FLL2_CONTROL_2 0x241 74*4882a593Smuzhiyun #define WM8995_FLL2_CONTROL_3 0x242 75*4882a593Smuzhiyun #define WM8995_FLL2_CONTROL_4 0x243 76*4882a593Smuzhiyun #define WM8995_FLL2_CONTROL_5 0x244 77*4882a593Smuzhiyun #define WM8995_AIF1_CONTROL_1 0x300 78*4882a593Smuzhiyun #define WM8995_AIF1_CONTROL_2 0x301 79*4882a593Smuzhiyun #define WM8995_AIF1_MASTER_SLAVE 0x302 80*4882a593Smuzhiyun #define WM8995_AIF1_BCLK 0x303 81*4882a593Smuzhiyun #define WM8995_AIF1ADC_LRCLK 0x304 82*4882a593Smuzhiyun #define WM8995_AIF1DAC_LRCLK 0x305 83*4882a593Smuzhiyun #define WM8995_AIF1DAC_DATA 0x306 84*4882a593Smuzhiyun #define WM8995_AIF1ADC_DATA 0x307 85*4882a593Smuzhiyun #define WM8995_AIF2_CONTROL_1 0x310 86*4882a593Smuzhiyun #define WM8995_AIF2_CONTROL_2 0x311 87*4882a593Smuzhiyun #define WM8995_AIF2_MASTER_SLAVE 0x312 88*4882a593Smuzhiyun #define WM8995_AIF2_BCLK 0x313 89*4882a593Smuzhiyun #define WM8995_AIF2ADC_LRCLK 0x314 90*4882a593Smuzhiyun #define WM8995_AIF2DAC_LRCLK 0x315 91*4882a593Smuzhiyun #define WM8995_AIF2DAC_DATA 0x316 92*4882a593Smuzhiyun #define WM8995_AIF2ADC_DATA 0x317 93*4882a593Smuzhiyun #define WM8995_AIF1_ADC1_LEFT_VOLUME 0x400 94*4882a593Smuzhiyun #define WM8995_AIF1_ADC1_RIGHT_VOLUME 0x401 95*4882a593Smuzhiyun #define WM8995_AIF1_DAC1_LEFT_VOLUME 0x402 96*4882a593Smuzhiyun #define WM8995_AIF1_DAC1_RIGHT_VOLUME 0x403 97*4882a593Smuzhiyun #define WM8995_AIF1_ADC2_LEFT_VOLUME 0x404 98*4882a593Smuzhiyun #define WM8995_AIF1_ADC2_RIGHT_VOLUME 0x405 99*4882a593Smuzhiyun #define WM8995_AIF1_DAC2_LEFT_VOLUME 0x406 100*4882a593Smuzhiyun #define WM8995_AIF1_DAC2_RIGHT_VOLUME 0x407 101*4882a593Smuzhiyun #define WM8995_AIF1_ADC1_FILTERS 0x410 102*4882a593Smuzhiyun #define WM8995_AIF1_ADC2_FILTERS 0x411 103*4882a593Smuzhiyun #define WM8995_AIF1_DAC1_FILTERS_1 0x420 104*4882a593Smuzhiyun #define WM8995_AIF1_DAC1_FILTERS_2 0x421 105*4882a593Smuzhiyun #define WM8995_AIF1_DAC2_FILTERS_1 0x422 106*4882a593Smuzhiyun #define WM8995_AIF1_DAC2_FILTERS_2 0x423 107*4882a593Smuzhiyun #define WM8995_AIF1_DRC1_1 0x440 108*4882a593Smuzhiyun #define WM8995_AIF1_DRC1_2 0x441 109*4882a593Smuzhiyun #define WM8995_AIF1_DRC1_3 0x442 110*4882a593Smuzhiyun #define WM8995_AIF1_DRC1_4 0x443 111*4882a593Smuzhiyun #define WM8995_AIF1_DRC1_5 0x444 112*4882a593Smuzhiyun #define WM8995_AIF1_DRC2_1 0x450 113*4882a593Smuzhiyun #define WM8995_AIF1_DRC2_2 0x451 114*4882a593Smuzhiyun #define WM8995_AIF1_DRC2_3 0x452 115*4882a593Smuzhiyun #define WM8995_AIF1_DRC2_4 0x453 116*4882a593Smuzhiyun #define WM8995_AIF1_DRC2_5 0x454 117*4882a593Smuzhiyun #define WM8995_AIF1_DAC1_EQ_GAINS_1 0x480 118*4882a593Smuzhiyun #define WM8995_AIF1_DAC1_EQ_GAINS_2 0x481 119*4882a593Smuzhiyun #define WM8995_AIF1_DAC1_EQ_BAND_1_A 0x482 120*4882a593Smuzhiyun #define WM8995_AIF1_DAC1_EQ_BAND_1_B 0x483 121*4882a593Smuzhiyun #define WM8995_AIF1_DAC1_EQ_BAND_1_PG 0x484 122*4882a593Smuzhiyun #define WM8995_AIF1_DAC1_EQ_BAND_2_A 0x485 123*4882a593Smuzhiyun #define WM8995_AIF1_DAC1_EQ_BAND_2_B 0x486 124*4882a593Smuzhiyun #define WM8995_AIF1_DAC1_EQ_BAND_2_C 0x487 125*4882a593Smuzhiyun #define WM8995_AIF1_DAC1_EQ_BAND_2_PG 0x488 126*4882a593Smuzhiyun #define WM8995_AIF1_DAC1_EQ_BAND_3_A 0x489 127*4882a593Smuzhiyun #define WM8995_AIF1_DAC1_EQ_BAND_3_B 0x48A 128*4882a593Smuzhiyun #define WM8995_AIF1_DAC1_EQ_BAND_3_C 0x48B 129*4882a593Smuzhiyun #define WM8995_AIF1_DAC1_EQ_BAND_3_PG 0x48C 130*4882a593Smuzhiyun #define WM8995_AIF1_DAC1_EQ_BAND_4_A 0x48D 131*4882a593Smuzhiyun #define WM8995_AIF1_DAC1_EQ_BAND_4_B 0x48E 132*4882a593Smuzhiyun #define WM8995_AIF1_DAC1_EQ_BAND_4_C 0x48F 133*4882a593Smuzhiyun #define WM8995_AIF1_DAC1_EQ_BAND_4_PG 0x490 134*4882a593Smuzhiyun #define WM8995_AIF1_DAC1_EQ_BAND_5_A 0x491 135*4882a593Smuzhiyun #define WM8995_AIF1_DAC1_EQ_BAND_5_B 0x492 136*4882a593Smuzhiyun #define WM8995_AIF1_DAC1_EQ_BAND_5_PG 0x493 137*4882a593Smuzhiyun #define WM8995_AIF1_DAC2_EQ_GAINS_1 0x4A0 138*4882a593Smuzhiyun #define WM8995_AIF1_DAC2_EQ_GAINS_2 0x4A1 139*4882a593Smuzhiyun #define WM8995_AIF1_DAC2_EQ_BAND_1_A 0x4A2 140*4882a593Smuzhiyun #define WM8995_AIF1_DAC2_EQ_BAND_1_B 0x4A3 141*4882a593Smuzhiyun #define WM8995_AIF1_DAC2_EQ_BAND_1_PG 0x4A4 142*4882a593Smuzhiyun #define WM8995_AIF1_DAC2_EQ_BAND_2_A 0x4A5 143*4882a593Smuzhiyun #define WM8995_AIF1_DAC2_EQ_BAND_2_B 0x4A6 144*4882a593Smuzhiyun #define WM8995_AIF1_DAC2_EQ_BAND_2_C 0x4A7 145*4882a593Smuzhiyun #define WM8995_AIF1_DAC2_EQ_BAND_2_PG 0x4A8 146*4882a593Smuzhiyun #define WM8995_AIF1_DAC2_EQ_BAND_3_A 0x4A9 147*4882a593Smuzhiyun #define WM8995_AIF1_DAC2_EQ_BAND_3_B 0x4AA 148*4882a593Smuzhiyun #define WM8995_AIF1_DAC2_EQ_BAND_3_C 0x4AB 149*4882a593Smuzhiyun #define WM8995_AIF1_DAC2_EQ_BAND_3_PG 0x4AC 150*4882a593Smuzhiyun #define WM8995_AIF1_DAC2_EQ_BAND_4_A 0x4AD 151*4882a593Smuzhiyun #define WM8995_AIF1_DAC2_EQ_BAND_4_B 0x4AE 152*4882a593Smuzhiyun #define WM8995_AIF1_DAC2_EQ_BAND_4_C 0x4AF 153*4882a593Smuzhiyun #define WM8995_AIF1_DAC2_EQ_BAND_4_PG 0x4B0 154*4882a593Smuzhiyun #define WM8995_AIF1_DAC2_EQ_BAND_5_A 0x4B1 155*4882a593Smuzhiyun #define WM8995_AIF1_DAC2_EQ_BAND_5_B 0x4B2 156*4882a593Smuzhiyun #define WM8995_AIF1_DAC2_EQ_BAND_5_PG 0x4B3 157*4882a593Smuzhiyun #define WM8995_AIF2_ADC_LEFT_VOLUME 0x500 158*4882a593Smuzhiyun #define WM8995_AIF2_ADC_RIGHT_VOLUME 0x501 159*4882a593Smuzhiyun #define WM8995_AIF2_DAC_LEFT_VOLUME 0x502 160*4882a593Smuzhiyun #define WM8995_AIF2_DAC_RIGHT_VOLUME 0x503 161*4882a593Smuzhiyun #define WM8995_AIF2_ADC_FILTERS 0x510 162*4882a593Smuzhiyun #define WM8995_AIF2_DAC_FILTERS_1 0x520 163*4882a593Smuzhiyun #define WM8995_AIF2_DAC_FILTERS_2 0x521 164*4882a593Smuzhiyun #define WM8995_AIF2_DRC_1 0x540 165*4882a593Smuzhiyun #define WM8995_AIF2_DRC_2 0x541 166*4882a593Smuzhiyun #define WM8995_AIF2_DRC_3 0x542 167*4882a593Smuzhiyun #define WM8995_AIF2_DRC_4 0x543 168*4882a593Smuzhiyun #define WM8995_AIF2_DRC_5 0x544 169*4882a593Smuzhiyun #define WM8995_AIF2_EQ_GAINS_1 0x580 170*4882a593Smuzhiyun #define WM8995_AIF2_EQ_GAINS_2 0x581 171*4882a593Smuzhiyun #define WM8995_AIF2_EQ_BAND_1_A 0x582 172*4882a593Smuzhiyun #define WM8995_AIF2_EQ_BAND_1_B 0x583 173*4882a593Smuzhiyun #define WM8995_AIF2_EQ_BAND_1_PG 0x584 174*4882a593Smuzhiyun #define WM8995_AIF2_EQ_BAND_2_A 0x585 175*4882a593Smuzhiyun #define WM8995_AIF2_EQ_BAND_2_B 0x586 176*4882a593Smuzhiyun #define WM8995_AIF2_EQ_BAND_2_C 0x587 177*4882a593Smuzhiyun #define WM8995_AIF2_EQ_BAND_2_PG 0x588 178*4882a593Smuzhiyun #define WM8995_AIF2_EQ_BAND_3_A 0x589 179*4882a593Smuzhiyun #define WM8995_AIF2_EQ_BAND_3_B 0x58A 180*4882a593Smuzhiyun #define WM8995_AIF2_EQ_BAND_3_C 0x58B 181*4882a593Smuzhiyun #define WM8995_AIF2_EQ_BAND_3_PG 0x58C 182*4882a593Smuzhiyun #define WM8995_AIF2_EQ_BAND_4_A 0x58D 183*4882a593Smuzhiyun #define WM8995_AIF2_EQ_BAND_4_B 0x58E 184*4882a593Smuzhiyun #define WM8995_AIF2_EQ_BAND_4_C 0x58F 185*4882a593Smuzhiyun #define WM8995_AIF2_EQ_BAND_4_PG 0x590 186*4882a593Smuzhiyun #define WM8995_AIF2_EQ_BAND_5_A 0x591 187*4882a593Smuzhiyun #define WM8995_AIF2_EQ_BAND_5_B 0x592 188*4882a593Smuzhiyun #define WM8995_AIF2_EQ_BAND_5_PG 0x593 189*4882a593Smuzhiyun #define WM8995_DAC1_MIXER_VOLUMES 0x600 190*4882a593Smuzhiyun #define WM8995_DAC1_LEFT_MIXER_ROUTING 0x601 191*4882a593Smuzhiyun #define WM8995_DAC1_RIGHT_MIXER_ROUTING 0x602 192*4882a593Smuzhiyun #define WM8995_DAC2_MIXER_VOLUMES 0x603 193*4882a593Smuzhiyun #define WM8995_DAC2_LEFT_MIXER_ROUTING 0x604 194*4882a593Smuzhiyun #define WM8995_DAC2_RIGHT_MIXER_ROUTING 0x605 195*4882a593Smuzhiyun #define WM8995_AIF1_ADC1_LEFT_MIXER_ROUTING 0x606 196*4882a593Smuzhiyun #define WM8995_AIF1_ADC1_RIGHT_MIXER_ROUTING 0x607 197*4882a593Smuzhiyun #define WM8995_AIF1_ADC2_LEFT_MIXER_ROUTING 0x608 198*4882a593Smuzhiyun #define WM8995_AIF1_ADC2_RIGHT_MIXER_ROUTING 0x609 199*4882a593Smuzhiyun #define WM8995_DAC_SOFTMUTE 0x610 200*4882a593Smuzhiyun #define WM8995_OVERSAMPLING 0x620 201*4882a593Smuzhiyun #define WM8995_SIDETONE 0x621 202*4882a593Smuzhiyun #define WM8995_GPIO_1 0x700 203*4882a593Smuzhiyun #define WM8995_GPIO_2 0x701 204*4882a593Smuzhiyun #define WM8995_GPIO_3 0x702 205*4882a593Smuzhiyun #define WM8995_GPIO_4 0x703 206*4882a593Smuzhiyun #define WM8995_GPIO_5 0x704 207*4882a593Smuzhiyun #define WM8995_GPIO_6 0x705 208*4882a593Smuzhiyun #define WM8995_GPIO_7 0x706 209*4882a593Smuzhiyun #define WM8995_GPIO_8 0x707 210*4882a593Smuzhiyun #define WM8995_GPIO_9 0x708 211*4882a593Smuzhiyun #define WM8995_GPIO_10 0x709 212*4882a593Smuzhiyun #define WM8995_GPIO_11 0x70A 213*4882a593Smuzhiyun #define WM8995_GPIO_12 0x70B 214*4882a593Smuzhiyun #define WM8995_GPIO_13 0x70C 215*4882a593Smuzhiyun #define WM8995_GPIO_14 0x70D 216*4882a593Smuzhiyun #define WM8995_PULL_CONTROL_1 0x720 217*4882a593Smuzhiyun #define WM8995_PULL_CONTROL_2 0x721 218*4882a593Smuzhiyun #define WM8995_INTERRUPT_STATUS_1 0x730 219*4882a593Smuzhiyun #define WM8995_INTERRUPT_STATUS_2 0x731 220*4882a593Smuzhiyun #define WM8995_INTERRUPT_RAW_STATUS_2 0x732 221*4882a593Smuzhiyun #define WM8995_INTERRUPT_STATUS_1_MASK 0x738 222*4882a593Smuzhiyun #define WM8995_INTERRUPT_STATUS_2_MASK 0x739 223*4882a593Smuzhiyun #define WM8995_INTERRUPT_CONTROL 0x740 224*4882a593Smuzhiyun #define WM8995_LEFT_PDM_SPEAKER_1 0x800 225*4882a593Smuzhiyun #define WM8995_RIGHT_PDM_SPEAKER_1 0x801 226*4882a593Smuzhiyun #define WM8995_PDM_SPEAKER_1_MUTE_SEQUENCE 0x802 227*4882a593Smuzhiyun #define WM8995_LEFT_PDM_SPEAKER_2 0x808 228*4882a593Smuzhiyun #define WM8995_RIGHT_PDM_SPEAKER_2 0x809 229*4882a593Smuzhiyun #define WM8995_PDM_SPEAKER_2_MUTE_SEQUENCE 0x80A 230*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_0 0x3000 231*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_1 0x3001 232*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_2 0x3002 233*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_3 0x3003 234*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_4 0x3004 235*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_5 0x3005 236*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_6 0x3006 237*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_7 0x3007 238*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_8 0x3008 239*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_9 0x3009 240*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_10 0x300A 241*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_11 0x300B 242*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_12 0x300C 243*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_13 0x300D 244*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_14 0x300E 245*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_15 0x300F 246*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_16 0x3010 247*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_17 0x3011 248*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_18 0x3012 249*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_19 0x3013 250*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_20 0x3014 251*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_21 0x3015 252*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_22 0x3016 253*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_23 0x3017 254*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_24 0x3018 255*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_25 0x3019 256*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_26 0x301A 257*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_27 0x301B 258*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_28 0x301C 259*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_29 0x301D 260*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_30 0x301E 261*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_31 0x301F 262*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_32 0x3020 263*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_33 0x3021 264*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_34 0x3022 265*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_35 0x3023 266*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_36 0x3024 267*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_37 0x3025 268*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_38 0x3026 269*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_39 0x3027 270*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_40 0x3028 271*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_41 0x3029 272*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_42 0x302A 273*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_43 0x302B 274*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_44 0x302C 275*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_45 0x302D 276*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_46 0x302E 277*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_47 0x302F 278*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_48 0x3030 279*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_49 0x3031 280*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_50 0x3032 281*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_51 0x3033 282*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_52 0x3034 283*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_53 0x3035 284*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_54 0x3036 285*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_55 0x3037 286*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_56 0x3038 287*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_57 0x3039 288*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_58 0x303A 289*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_59 0x303B 290*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_60 0x303C 291*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_61 0x303D 292*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_62 0x303E 293*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_63 0x303F 294*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_64 0x3040 295*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_65 0x3041 296*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_66 0x3042 297*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_67 0x3043 298*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_68 0x3044 299*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_69 0x3045 300*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_70 0x3046 301*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_71 0x3047 302*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_72 0x3048 303*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_73 0x3049 304*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_74 0x304A 305*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_75 0x304B 306*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_76 0x304C 307*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_77 0x304D 308*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_78 0x304E 309*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_79 0x304F 310*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_80 0x3050 311*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_81 0x3051 312*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_82 0x3052 313*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_83 0x3053 314*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_84 0x3054 315*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_85 0x3055 316*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_86 0x3056 317*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_87 0x3057 318*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_88 0x3058 319*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_89 0x3059 320*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_90 0x305A 321*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_91 0x305B 322*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_92 0x305C 323*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_93 0x305D 324*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_94 0x305E 325*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_95 0x305F 326*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_96 0x3060 327*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_97 0x3061 328*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_98 0x3062 329*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_99 0x3063 330*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_100 0x3064 331*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_101 0x3065 332*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_102 0x3066 333*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_103 0x3067 334*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_104 0x3068 335*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_105 0x3069 336*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_106 0x306A 337*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_107 0x306B 338*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_108 0x306C 339*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_109 0x306D 340*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_110 0x306E 341*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_111 0x306F 342*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_112 0x3070 343*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_113 0x3071 344*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_114 0x3072 345*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_115 0x3073 346*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_116 0x3074 347*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_117 0x3075 348*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_118 0x3076 349*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_119 0x3077 350*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_120 0x3078 351*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_121 0x3079 352*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_122 0x307A 353*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_123 0x307B 354*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_124 0x307C 355*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_125 0x307D 356*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_126 0x307E 357*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_127 0x307F 358*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_128 0x3080 359*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_129 0x3081 360*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_130 0x3082 361*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_131 0x3083 362*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_132 0x3084 363*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_133 0x3085 364*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_134 0x3086 365*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_135 0x3087 366*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_136 0x3088 367*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_137 0x3089 368*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_138 0x308A 369*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_139 0x308B 370*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_140 0x308C 371*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_141 0x308D 372*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_142 0x308E 373*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_143 0x308F 374*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_144 0x3090 375*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_145 0x3091 376*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_146 0x3092 377*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_147 0x3093 378*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_148 0x3094 379*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_149 0x3095 380*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_150 0x3096 381*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_151 0x3097 382*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_152 0x3098 383*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_153 0x3099 384*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_154 0x309A 385*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_155 0x309B 386*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_156 0x309C 387*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_157 0x309D 388*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_158 0x309E 389*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_159 0x309F 390*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_160 0x30A0 391*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_161 0x30A1 392*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_162 0x30A2 393*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_163 0x30A3 394*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_164 0x30A4 395*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_165 0x30A5 396*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_166 0x30A6 397*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_167 0x30A7 398*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_168 0x30A8 399*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_169 0x30A9 400*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_170 0x30AA 401*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_171 0x30AB 402*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_172 0x30AC 403*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_173 0x30AD 404*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_174 0x30AE 405*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_175 0x30AF 406*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_176 0x30B0 407*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_177 0x30B1 408*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_178 0x30B2 409*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_179 0x30B3 410*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_180 0x30B4 411*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_181 0x30B5 412*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_182 0x30B6 413*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_183 0x30B7 414*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_184 0x30B8 415*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_185 0x30B9 416*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_186 0x30BA 417*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_187 0x30BB 418*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_188 0x30BC 419*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_189 0x30BD 420*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_190 0x30BE 421*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_191 0x30BF 422*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_192 0x30C0 423*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_193 0x30C1 424*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_194 0x30C2 425*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_195 0x30C3 426*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_196 0x30C4 427*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_197 0x30C5 428*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_198 0x30C6 429*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_199 0x30C7 430*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_200 0x30C8 431*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_201 0x30C9 432*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_202 0x30CA 433*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_203 0x30CB 434*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_204 0x30CC 435*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_205 0x30CD 436*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_206 0x30CE 437*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_207 0x30CF 438*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_208 0x30D0 439*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_209 0x30D1 440*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_210 0x30D2 441*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_211 0x30D3 442*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_212 0x30D4 443*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_213 0x30D5 444*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_214 0x30D6 445*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_215 0x30D7 446*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_216 0x30D8 447*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_217 0x30D9 448*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_218 0x30DA 449*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_219 0x30DB 450*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_220 0x30DC 451*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_221 0x30DD 452*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_222 0x30DE 453*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_223 0x30DF 454*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_224 0x30E0 455*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_225 0x30E1 456*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_226 0x30E2 457*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_227 0x30E3 458*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_228 0x30E4 459*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_229 0x30E5 460*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_230 0x30E6 461*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_231 0x30E7 462*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_232 0x30E8 463*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_233 0x30E9 464*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_234 0x30EA 465*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_235 0x30EB 466*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_236 0x30EC 467*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_237 0x30ED 468*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_238 0x30EE 469*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_239 0x30EF 470*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_240 0x30F0 471*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_241 0x30F1 472*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_242 0x30F2 473*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_243 0x30F3 474*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_244 0x30F4 475*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_245 0x30F5 476*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_246 0x30F6 477*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_247 0x30F7 478*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_248 0x30F8 479*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_249 0x30F9 480*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_250 0x30FA 481*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_251 0x30FB 482*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_252 0x30FC 483*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_253 0x30FD 484*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_254 0x30FE 485*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_255 0x30FF 486*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_256 0x3100 487*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_257 0x3101 488*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_258 0x3102 489*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_259 0x3103 490*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_260 0x3104 491*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_261 0x3105 492*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_262 0x3106 493*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_263 0x3107 494*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_264 0x3108 495*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_265 0x3109 496*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_266 0x310A 497*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_267 0x310B 498*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_268 0x310C 499*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_269 0x310D 500*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_270 0x310E 501*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_271 0x310F 502*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_272 0x3110 503*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_273 0x3111 504*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_274 0x3112 505*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_275 0x3113 506*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_276 0x3114 507*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_277 0x3115 508*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_278 0x3116 509*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_279 0x3117 510*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_280 0x3118 511*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_281 0x3119 512*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_282 0x311A 513*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_283 0x311B 514*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_284 0x311C 515*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_285 0x311D 516*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_286 0x311E 517*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_287 0x311F 518*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_288 0x3120 519*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_289 0x3121 520*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_290 0x3122 521*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_291 0x3123 522*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_292 0x3124 523*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_293 0x3125 524*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_294 0x3126 525*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_295 0x3127 526*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_296 0x3128 527*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_297 0x3129 528*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_298 0x312A 529*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_299 0x312B 530*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_300 0x312C 531*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_301 0x312D 532*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_302 0x312E 533*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_303 0x312F 534*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_304 0x3130 535*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_305 0x3131 536*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_306 0x3132 537*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_307 0x3133 538*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_308 0x3134 539*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_309 0x3135 540*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_310 0x3136 541*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_311 0x3137 542*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_312 0x3138 543*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_313 0x3139 544*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_314 0x313A 545*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_315 0x313B 546*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_316 0x313C 547*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_317 0x313D 548*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_318 0x313E 549*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_319 0x313F 550*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_320 0x3140 551*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_321 0x3141 552*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_322 0x3142 553*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_323 0x3143 554*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_324 0x3144 555*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_325 0x3145 556*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_326 0x3146 557*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_327 0x3147 558*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_328 0x3148 559*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_329 0x3149 560*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_330 0x314A 561*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_331 0x314B 562*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_332 0x314C 563*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_333 0x314D 564*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_334 0x314E 565*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_335 0x314F 566*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_336 0x3150 567*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_337 0x3151 568*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_338 0x3152 569*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_339 0x3153 570*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_340 0x3154 571*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_341 0x3155 572*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_342 0x3156 573*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_343 0x3157 574*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_344 0x3158 575*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_345 0x3159 576*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_346 0x315A 577*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_347 0x315B 578*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_348 0x315C 579*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_349 0x315D 580*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_350 0x315E 581*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_351 0x315F 582*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_352 0x3160 583*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_353 0x3161 584*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_354 0x3162 585*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_355 0x3163 586*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_356 0x3164 587*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_357 0x3165 588*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_358 0x3166 589*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_359 0x3167 590*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_360 0x3168 591*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_361 0x3169 592*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_362 0x316A 593*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_363 0x316B 594*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_364 0x316C 595*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_365 0x316D 596*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_366 0x316E 597*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_367 0x316F 598*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_368 0x3170 599*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_369 0x3171 600*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_370 0x3172 601*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_371 0x3173 602*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_372 0x3174 603*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_373 0x3175 604*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_374 0x3176 605*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_375 0x3177 606*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_376 0x3178 607*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_377 0x3179 608*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_378 0x317A 609*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_379 0x317B 610*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_380 0x317C 611*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_381 0x317D 612*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_382 0x317E 613*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_383 0x317F 614*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_384 0x3180 615*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_385 0x3181 616*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_386 0x3182 617*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_387 0x3183 618*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_388 0x3184 619*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_389 0x3185 620*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_390 0x3186 621*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_391 0x3187 622*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_392 0x3188 623*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_393 0x3189 624*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_394 0x318A 625*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_395 0x318B 626*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_396 0x318C 627*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_397 0x318D 628*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_398 0x318E 629*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_399 0x318F 630*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_400 0x3190 631*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_401 0x3191 632*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_402 0x3192 633*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_403 0x3193 634*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_404 0x3194 635*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_405 0x3195 636*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_406 0x3196 637*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_407 0x3197 638*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_408 0x3198 639*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_409 0x3199 640*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_410 0x319A 641*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_411 0x319B 642*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_412 0x319C 643*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_413 0x319D 644*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_414 0x319E 645*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_415 0x319F 646*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_416 0x31A0 647*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_417 0x31A1 648*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_418 0x31A2 649*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_419 0x31A3 650*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_420 0x31A4 651*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_421 0x31A5 652*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_422 0x31A6 653*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_423 0x31A7 654*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_424 0x31A8 655*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_425 0x31A9 656*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_426 0x31AA 657*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_427 0x31AB 658*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_428 0x31AC 659*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_429 0x31AD 660*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_430 0x31AE 661*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_431 0x31AF 662*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_432 0x31B0 663*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_433 0x31B1 664*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_434 0x31B2 665*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_435 0x31B3 666*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_436 0x31B4 667*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_437 0x31B5 668*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_438 0x31B6 669*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_439 0x31B7 670*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_440 0x31B8 671*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_441 0x31B9 672*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_442 0x31BA 673*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_443 0x31BB 674*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_444 0x31BC 675*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_445 0x31BD 676*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_446 0x31BE 677*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_447 0x31BF 678*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_448 0x31C0 679*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_449 0x31C1 680*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_450 0x31C2 681*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_451 0x31C3 682*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_452 0x31C4 683*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_453 0x31C5 684*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_454 0x31C6 685*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_455 0x31C7 686*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_456 0x31C8 687*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_457 0x31C9 688*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_458 0x31CA 689*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_459 0x31CB 690*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_460 0x31CC 691*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_461 0x31CD 692*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_462 0x31CE 693*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_463 0x31CF 694*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_464 0x31D0 695*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_465 0x31D1 696*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_466 0x31D2 697*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_467 0x31D3 698*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_468 0x31D4 699*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_469 0x31D5 700*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_470 0x31D6 701*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_471 0x31D7 702*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_472 0x31D8 703*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_473 0x31D9 704*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_474 0x31DA 705*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_475 0x31DB 706*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_476 0x31DC 707*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_477 0x31DD 708*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_478 0x31DE 709*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_479 0x31DF 710*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_480 0x31E0 711*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_481 0x31E1 712*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_482 0x31E2 713*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_483 0x31E3 714*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_484 0x31E4 715*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_485 0x31E5 716*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_486 0x31E6 717*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_487 0x31E7 718*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_488 0x31E8 719*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_489 0x31E9 720*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_490 0x31EA 721*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_491 0x31EB 722*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_492 0x31EC 723*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_493 0x31ED 724*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_494 0x31EE 725*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_495 0x31EF 726*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_496 0x31F0 727*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_497 0x31F1 728*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_498 0x31F2 729*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_499 0x31F3 730*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_500 0x31F4 731*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_501 0x31F5 732*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_502 0x31F6 733*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_503 0x31F7 734*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_504 0x31F8 735*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_505 0x31F9 736*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_506 0x31FA 737*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_507 0x31FB 738*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_508 0x31FC 739*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_509 0x31FD 740*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_510 0x31FE 741*4882a593Smuzhiyun #define WM8995_WRITE_SEQUENCER_511 0x31FF 742*4882a593Smuzhiyun 743*4882a593Smuzhiyun #define WM8995_REGISTER_COUNT 725 744*4882a593Smuzhiyun #define WM8995_MAX_REGISTER 0x31FF 745*4882a593Smuzhiyun 746*4882a593Smuzhiyun #define WM8995_MAX_CACHED_REGISTER WM8995_MAX_REGISTER 747*4882a593Smuzhiyun 748*4882a593Smuzhiyun /* 749*4882a593Smuzhiyun * Field Definitions. 750*4882a593Smuzhiyun */ 751*4882a593Smuzhiyun 752*4882a593Smuzhiyun /* 753*4882a593Smuzhiyun * R0 (0x00) - Software Reset 754*4882a593Smuzhiyun */ 755*4882a593Smuzhiyun #define WM8995_SW_RESET_MASK 0xFFFF /* SW_RESET - [15:0] */ 756*4882a593Smuzhiyun #define WM8995_SW_RESET_SHIFT 0 /* SW_RESET - [15:0] */ 757*4882a593Smuzhiyun #define WM8995_SW_RESET_WIDTH 16 /* SW_RESET - [15:0] */ 758*4882a593Smuzhiyun 759*4882a593Smuzhiyun /* 760*4882a593Smuzhiyun * R1 (0x01) - Power Management (1) 761*4882a593Smuzhiyun */ 762*4882a593Smuzhiyun #define WM8995_MICB2_ENA 0x0200 /* MICB2_ENA */ 763*4882a593Smuzhiyun #define WM8995_MICB2_ENA_MASK 0x0200 /* MICB2_ENA */ 764*4882a593Smuzhiyun #define WM8995_MICB2_ENA_SHIFT 9 /* MICB2_ENA */ 765*4882a593Smuzhiyun #define WM8995_MICB2_ENA_WIDTH 1 /* MICB2_ENA */ 766*4882a593Smuzhiyun #define WM8995_MICB1_ENA 0x0100 /* MICB1_ENA */ 767*4882a593Smuzhiyun #define WM8995_MICB1_ENA_MASK 0x0100 /* MICB1_ENA */ 768*4882a593Smuzhiyun #define WM8995_MICB1_ENA_SHIFT 8 /* MICB1_ENA */ 769*4882a593Smuzhiyun #define WM8995_MICB1_ENA_WIDTH 1 /* MICB1_ENA */ 770*4882a593Smuzhiyun #define WM8995_HPOUT2L_ENA 0x0080 /* HPOUT2L_ENA */ 771*4882a593Smuzhiyun #define WM8995_HPOUT2L_ENA_MASK 0x0080 /* HPOUT2L_ENA */ 772*4882a593Smuzhiyun #define WM8995_HPOUT2L_ENA_SHIFT 7 /* HPOUT2L_ENA */ 773*4882a593Smuzhiyun #define WM8995_HPOUT2L_ENA_WIDTH 1 /* HPOUT2L_ENA */ 774*4882a593Smuzhiyun #define WM8995_HPOUT2R_ENA 0x0040 /* HPOUT2R_ENA */ 775*4882a593Smuzhiyun #define WM8995_HPOUT2R_ENA_MASK 0x0040 /* HPOUT2R_ENA */ 776*4882a593Smuzhiyun #define WM8995_HPOUT2R_ENA_SHIFT 6 /* HPOUT2R_ENA */ 777*4882a593Smuzhiyun #define WM8995_HPOUT2R_ENA_WIDTH 1 /* HPOUT2R_ENA */ 778*4882a593Smuzhiyun #define WM8995_HPOUT1L_ENA 0x0020 /* HPOUT1L_ENA */ 779*4882a593Smuzhiyun #define WM8995_HPOUT1L_ENA_MASK 0x0020 /* HPOUT1L_ENA */ 780*4882a593Smuzhiyun #define WM8995_HPOUT1L_ENA_SHIFT 5 /* HPOUT1L_ENA */ 781*4882a593Smuzhiyun #define WM8995_HPOUT1L_ENA_WIDTH 1 /* HPOUT1L_ENA */ 782*4882a593Smuzhiyun #define WM8995_HPOUT1R_ENA 0x0010 /* HPOUT1R_ENA */ 783*4882a593Smuzhiyun #define WM8995_HPOUT1R_ENA_MASK 0x0010 /* HPOUT1R_ENA */ 784*4882a593Smuzhiyun #define WM8995_HPOUT1R_ENA_SHIFT 4 /* HPOUT1R_ENA */ 785*4882a593Smuzhiyun #define WM8995_HPOUT1R_ENA_WIDTH 1 /* HPOUT1R_ENA */ 786*4882a593Smuzhiyun #define WM8995_BG_ENA 0x0001 /* BG_ENA */ 787*4882a593Smuzhiyun #define WM8995_BG_ENA_MASK 0x0001 /* BG_ENA */ 788*4882a593Smuzhiyun #define WM8995_BG_ENA_SHIFT 0 /* BG_ENA */ 789*4882a593Smuzhiyun #define WM8995_BG_ENA_WIDTH 1 /* BG_ENA */ 790*4882a593Smuzhiyun 791*4882a593Smuzhiyun /* 792*4882a593Smuzhiyun * R2 (0x02) - Power Management (2) 793*4882a593Smuzhiyun */ 794*4882a593Smuzhiyun #define WM8995_OPCLK_ENA 0x0800 /* OPCLK_ENA */ 795*4882a593Smuzhiyun #define WM8995_OPCLK_ENA_MASK 0x0800 /* OPCLK_ENA */ 796*4882a593Smuzhiyun #define WM8995_OPCLK_ENA_SHIFT 11 /* OPCLK_ENA */ 797*4882a593Smuzhiyun #define WM8995_OPCLK_ENA_WIDTH 1 /* OPCLK_ENA */ 798*4882a593Smuzhiyun #define WM8995_IN1L_ENA 0x0020 /* IN1L_ENA */ 799*4882a593Smuzhiyun #define WM8995_IN1L_ENA_MASK 0x0020 /* IN1L_ENA */ 800*4882a593Smuzhiyun #define WM8995_IN1L_ENA_SHIFT 5 /* IN1L_ENA */ 801*4882a593Smuzhiyun #define WM8995_IN1L_ENA_WIDTH 1 /* IN1L_ENA */ 802*4882a593Smuzhiyun #define WM8995_IN1R_ENA 0x0010 /* IN1R_ENA */ 803*4882a593Smuzhiyun #define WM8995_IN1R_ENA_MASK 0x0010 /* IN1R_ENA */ 804*4882a593Smuzhiyun #define WM8995_IN1R_ENA_SHIFT 4 /* IN1R_ENA */ 805*4882a593Smuzhiyun #define WM8995_IN1R_ENA_WIDTH 1 /* IN1R_ENA */ 806*4882a593Smuzhiyun #define WM8995_LDO2_ENA 0x0002 /* LDO2_ENA */ 807*4882a593Smuzhiyun #define WM8995_LDO2_ENA_MASK 0x0002 /* LDO2_ENA */ 808*4882a593Smuzhiyun #define WM8995_LDO2_ENA_SHIFT 1 /* LDO2_ENA */ 809*4882a593Smuzhiyun #define WM8995_LDO2_ENA_WIDTH 1 /* LDO2_ENA */ 810*4882a593Smuzhiyun 811*4882a593Smuzhiyun /* 812*4882a593Smuzhiyun * R3 (0x03) - Power Management (3) 813*4882a593Smuzhiyun */ 814*4882a593Smuzhiyun #define WM8995_AIF2ADCL_ENA 0x2000 /* AIF2ADCL_ENA */ 815*4882a593Smuzhiyun #define WM8995_AIF2ADCL_ENA_MASK 0x2000 /* AIF2ADCL_ENA */ 816*4882a593Smuzhiyun #define WM8995_AIF2ADCL_ENA_SHIFT 13 /* AIF2ADCL_ENA */ 817*4882a593Smuzhiyun #define WM8995_AIF2ADCL_ENA_WIDTH 1 /* AIF2ADCL_ENA */ 818*4882a593Smuzhiyun #define WM8995_AIF2ADCR_ENA 0x1000 /* AIF2ADCR_ENA */ 819*4882a593Smuzhiyun #define WM8995_AIF2ADCR_ENA_MASK 0x1000 /* AIF2ADCR_ENA */ 820*4882a593Smuzhiyun #define WM8995_AIF2ADCR_ENA_SHIFT 12 /* AIF2ADCR_ENA */ 821*4882a593Smuzhiyun #define WM8995_AIF2ADCR_ENA_WIDTH 1 /* AIF2ADCR_ENA */ 822*4882a593Smuzhiyun #define WM8995_AIF1ADC2L_ENA 0x0800 /* AIF1ADC2L_ENA */ 823*4882a593Smuzhiyun #define WM8995_AIF1ADC2L_ENA_MASK 0x0800 /* AIF1ADC2L_ENA */ 824*4882a593Smuzhiyun #define WM8995_AIF1ADC2L_ENA_SHIFT 11 /* AIF1ADC2L_ENA */ 825*4882a593Smuzhiyun #define WM8995_AIF1ADC2L_ENA_WIDTH 1 /* AIF1ADC2L_ENA */ 826*4882a593Smuzhiyun #define WM8995_AIF1ADC2R_ENA 0x0400 /* AIF1ADC2R_ENA */ 827*4882a593Smuzhiyun #define WM8995_AIF1ADC2R_ENA_MASK 0x0400 /* AIF1ADC2R_ENA */ 828*4882a593Smuzhiyun #define WM8995_AIF1ADC2R_ENA_SHIFT 10 /* AIF1ADC2R_ENA */ 829*4882a593Smuzhiyun #define WM8995_AIF1ADC2R_ENA_WIDTH 1 /* AIF1ADC2R_ENA */ 830*4882a593Smuzhiyun #define WM8995_AIF1ADC1L_ENA 0x0200 /* AIF1ADC1L_ENA */ 831*4882a593Smuzhiyun #define WM8995_AIF1ADC1L_ENA_MASK 0x0200 /* AIF1ADC1L_ENA */ 832*4882a593Smuzhiyun #define WM8995_AIF1ADC1L_ENA_SHIFT 9 /* AIF1ADC1L_ENA */ 833*4882a593Smuzhiyun #define WM8995_AIF1ADC1L_ENA_WIDTH 1 /* AIF1ADC1L_ENA */ 834*4882a593Smuzhiyun #define WM8995_AIF1ADC1R_ENA 0x0100 /* AIF1ADC1R_ENA */ 835*4882a593Smuzhiyun #define WM8995_AIF1ADC1R_ENA_MASK 0x0100 /* AIF1ADC1R_ENA */ 836*4882a593Smuzhiyun #define WM8995_AIF1ADC1R_ENA_SHIFT 8 /* AIF1ADC1R_ENA */ 837*4882a593Smuzhiyun #define WM8995_AIF1ADC1R_ENA_WIDTH 1 /* AIF1ADC1R_ENA */ 838*4882a593Smuzhiyun #define WM8995_DMIC3L_ENA 0x0080 /* DMIC3L_ENA */ 839*4882a593Smuzhiyun #define WM8995_DMIC3L_ENA_MASK 0x0080 /* DMIC3L_ENA */ 840*4882a593Smuzhiyun #define WM8995_DMIC3L_ENA_SHIFT 7 /* DMIC3L_ENA */ 841*4882a593Smuzhiyun #define WM8995_DMIC3L_ENA_WIDTH 1 /* DMIC3L_ENA */ 842*4882a593Smuzhiyun #define WM8995_DMIC3R_ENA 0x0040 /* DMIC3R_ENA */ 843*4882a593Smuzhiyun #define WM8995_DMIC3R_ENA_MASK 0x0040 /* DMIC3R_ENA */ 844*4882a593Smuzhiyun #define WM8995_DMIC3R_ENA_SHIFT 6 /* DMIC3R_ENA */ 845*4882a593Smuzhiyun #define WM8995_DMIC3R_ENA_WIDTH 1 /* DMIC3R_ENA */ 846*4882a593Smuzhiyun #define WM8995_DMIC2L_ENA 0x0020 /* DMIC2L_ENA */ 847*4882a593Smuzhiyun #define WM8995_DMIC2L_ENA_MASK 0x0020 /* DMIC2L_ENA */ 848*4882a593Smuzhiyun #define WM8995_DMIC2L_ENA_SHIFT 5 /* DMIC2L_ENA */ 849*4882a593Smuzhiyun #define WM8995_DMIC2L_ENA_WIDTH 1 /* DMIC2L_ENA */ 850*4882a593Smuzhiyun #define WM8995_DMIC2R_ENA 0x0010 /* DMIC2R_ENA */ 851*4882a593Smuzhiyun #define WM8995_DMIC2R_ENA_MASK 0x0010 /* DMIC2R_ENA */ 852*4882a593Smuzhiyun #define WM8995_DMIC2R_ENA_SHIFT 4 /* DMIC2R_ENA */ 853*4882a593Smuzhiyun #define WM8995_DMIC2R_ENA_WIDTH 1 /* DMIC2R_ENA */ 854*4882a593Smuzhiyun #define WM8995_DMIC1L_ENA 0x0008 /* DMIC1L_ENA */ 855*4882a593Smuzhiyun #define WM8995_DMIC1L_ENA_MASK 0x0008 /* DMIC1L_ENA */ 856*4882a593Smuzhiyun #define WM8995_DMIC1L_ENA_SHIFT 3 /* DMIC1L_ENA */ 857*4882a593Smuzhiyun #define WM8995_DMIC1L_ENA_WIDTH 1 /* DMIC1L_ENA */ 858*4882a593Smuzhiyun #define WM8995_DMIC1R_ENA 0x0004 /* DMIC1R_ENA */ 859*4882a593Smuzhiyun #define WM8995_DMIC1R_ENA_MASK 0x0004 /* DMIC1R_ENA */ 860*4882a593Smuzhiyun #define WM8995_DMIC1R_ENA_SHIFT 2 /* DMIC1R_ENA */ 861*4882a593Smuzhiyun #define WM8995_DMIC1R_ENA_WIDTH 1 /* DMIC1R_ENA */ 862*4882a593Smuzhiyun #define WM8995_ADCL_ENA 0x0002 /* ADCL_ENA */ 863*4882a593Smuzhiyun #define WM8995_ADCL_ENA_MASK 0x0002 /* ADCL_ENA */ 864*4882a593Smuzhiyun #define WM8995_ADCL_ENA_SHIFT 1 /* ADCL_ENA */ 865*4882a593Smuzhiyun #define WM8995_ADCL_ENA_WIDTH 1 /* ADCL_ENA */ 866*4882a593Smuzhiyun #define WM8995_ADCR_ENA 0x0001 /* ADCR_ENA */ 867*4882a593Smuzhiyun #define WM8995_ADCR_ENA_MASK 0x0001 /* ADCR_ENA */ 868*4882a593Smuzhiyun #define WM8995_ADCR_ENA_SHIFT 0 /* ADCR_ENA */ 869*4882a593Smuzhiyun #define WM8995_ADCR_ENA_WIDTH 1 /* ADCR_ENA */ 870*4882a593Smuzhiyun 871*4882a593Smuzhiyun /* 872*4882a593Smuzhiyun * R4 (0x04) - Power Management (4) 873*4882a593Smuzhiyun */ 874*4882a593Smuzhiyun #define WM8995_AIF2DACL_ENA 0x2000 /* AIF2DACL_ENA */ 875*4882a593Smuzhiyun #define WM8995_AIF2DACL_ENA_MASK 0x2000 /* AIF2DACL_ENA */ 876*4882a593Smuzhiyun #define WM8995_AIF2DACL_ENA_SHIFT 13 /* AIF2DACL_ENA */ 877*4882a593Smuzhiyun #define WM8995_AIF2DACL_ENA_WIDTH 1 /* AIF2DACL_ENA */ 878*4882a593Smuzhiyun #define WM8995_AIF2DACR_ENA 0x1000 /* AIF2DACR_ENA */ 879*4882a593Smuzhiyun #define WM8995_AIF2DACR_ENA_MASK 0x1000 /* AIF2DACR_ENA */ 880*4882a593Smuzhiyun #define WM8995_AIF2DACR_ENA_SHIFT 12 /* AIF2DACR_ENA */ 881*4882a593Smuzhiyun #define WM8995_AIF2DACR_ENA_WIDTH 1 /* AIF2DACR_ENA */ 882*4882a593Smuzhiyun #define WM8995_AIF1DAC2L_ENA 0x0800 /* AIF1DAC2L_ENA */ 883*4882a593Smuzhiyun #define WM8995_AIF1DAC2L_ENA_MASK 0x0800 /* AIF1DAC2L_ENA */ 884*4882a593Smuzhiyun #define WM8995_AIF1DAC2L_ENA_SHIFT 11 /* AIF1DAC2L_ENA */ 885*4882a593Smuzhiyun #define WM8995_AIF1DAC2L_ENA_WIDTH 1 /* AIF1DAC2L_ENA */ 886*4882a593Smuzhiyun #define WM8995_AIF1DAC2R_ENA 0x0400 /* AIF1DAC2R_ENA */ 887*4882a593Smuzhiyun #define WM8995_AIF1DAC2R_ENA_MASK 0x0400 /* AIF1DAC2R_ENA */ 888*4882a593Smuzhiyun #define WM8995_AIF1DAC2R_ENA_SHIFT 10 /* AIF1DAC2R_ENA */ 889*4882a593Smuzhiyun #define WM8995_AIF1DAC2R_ENA_WIDTH 1 /* AIF1DAC2R_ENA */ 890*4882a593Smuzhiyun #define WM8995_AIF1DAC1L_ENA 0x0200 /* AIF1DAC1L_ENA */ 891*4882a593Smuzhiyun #define WM8995_AIF1DAC1L_ENA_MASK 0x0200 /* AIF1DAC1L_ENA */ 892*4882a593Smuzhiyun #define WM8995_AIF1DAC1L_ENA_SHIFT 9 /* AIF1DAC1L_ENA */ 893*4882a593Smuzhiyun #define WM8995_AIF1DAC1L_ENA_WIDTH 1 /* AIF1DAC1L_ENA */ 894*4882a593Smuzhiyun #define WM8995_AIF1DAC1R_ENA 0x0100 /* AIF1DAC1R_ENA */ 895*4882a593Smuzhiyun #define WM8995_AIF1DAC1R_ENA_MASK 0x0100 /* AIF1DAC1R_ENA */ 896*4882a593Smuzhiyun #define WM8995_AIF1DAC1R_ENA_SHIFT 8 /* AIF1DAC1R_ENA */ 897*4882a593Smuzhiyun #define WM8995_AIF1DAC1R_ENA_WIDTH 1 /* AIF1DAC1R_ENA */ 898*4882a593Smuzhiyun #define WM8995_DAC2L_ENA 0x0008 /* DAC2L_ENA */ 899*4882a593Smuzhiyun #define WM8995_DAC2L_ENA_MASK 0x0008 /* DAC2L_ENA */ 900*4882a593Smuzhiyun #define WM8995_DAC2L_ENA_SHIFT 3 /* DAC2L_ENA */ 901*4882a593Smuzhiyun #define WM8995_DAC2L_ENA_WIDTH 1 /* DAC2L_ENA */ 902*4882a593Smuzhiyun #define WM8995_DAC2R_ENA 0x0004 /* DAC2R_ENA */ 903*4882a593Smuzhiyun #define WM8995_DAC2R_ENA_MASK 0x0004 /* DAC2R_ENA */ 904*4882a593Smuzhiyun #define WM8995_DAC2R_ENA_SHIFT 2 /* DAC2R_ENA */ 905*4882a593Smuzhiyun #define WM8995_DAC2R_ENA_WIDTH 1 /* DAC2R_ENA */ 906*4882a593Smuzhiyun #define WM8995_DAC1L_ENA 0x0002 /* DAC1L_ENA */ 907*4882a593Smuzhiyun #define WM8995_DAC1L_ENA_MASK 0x0002 /* DAC1L_ENA */ 908*4882a593Smuzhiyun #define WM8995_DAC1L_ENA_SHIFT 1 /* DAC1L_ENA */ 909*4882a593Smuzhiyun #define WM8995_DAC1L_ENA_WIDTH 1 /* DAC1L_ENA */ 910*4882a593Smuzhiyun #define WM8995_DAC1R_ENA 0x0001 /* DAC1R_ENA */ 911*4882a593Smuzhiyun #define WM8995_DAC1R_ENA_MASK 0x0001 /* DAC1R_ENA */ 912*4882a593Smuzhiyun #define WM8995_DAC1R_ENA_SHIFT 0 /* DAC1R_ENA */ 913*4882a593Smuzhiyun #define WM8995_DAC1R_ENA_WIDTH 1 /* DAC1R_ENA */ 914*4882a593Smuzhiyun 915*4882a593Smuzhiyun /* 916*4882a593Smuzhiyun * R5 (0x05) - Power Management (5) 917*4882a593Smuzhiyun */ 918*4882a593Smuzhiyun #define WM8995_DMIC_SRC2_MASK 0x0300 /* DMIC_SRC2 - [9:8] */ 919*4882a593Smuzhiyun #define WM8995_DMIC_SRC2_SHIFT 8 /* DMIC_SRC2 - [9:8] */ 920*4882a593Smuzhiyun #define WM8995_DMIC_SRC2_WIDTH 2 /* DMIC_SRC2 - [9:8] */ 921*4882a593Smuzhiyun #define WM8995_DMIC_SRC1_MASK 0x00C0 /* DMIC_SRC1 - [7:6] */ 922*4882a593Smuzhiyun #define WM8995_DMIC_SRC1_SHIFT 6 /* DMIC_SRC1 - [7:6] */ 923*4882a593Smuzhiyun #define WM8995_DMIC_SRC1_WIDTH 2 /* DMIC_SRC1 - [7:6] */ 924*4882a593Smuzhiyun #define WM8995_AIF3_TRI 0x0020 /* AIF3_TRI */ 925*4882a593Smuzhiyun #define WM8995_AIF3_TRI_MASK 0x0020 /* AIF3_TRI */ 926*4882a593Smuzhiyun #define WM8995_AIF3_TRI_SHIFT 5 /* AIF3_TRI */ 927*4882a593Smuzhiyun #define WM8995_AIF3_TRI_WIDTH 1 /* AIF3_TRI */ 928*4882a593Smuzhiyun #define WM8995_AIF3_ADCDAT_SRC_MASK 0x0018 /* AIF3_ADCDAT_SRC - [4:3] */ 929*4882a593Smuzhiyun #define WM8995_AIF3_ADCDAT_SRC_SHIFT 3 /* AIF3_ADCDAT_SRC - [4:3] */ 930*4882a593Smuzhiyun #define WM8995_AIF3_ADCDAT_SRC_WIDTH 2 /* AIF3_ADCDAT_SRC - [4:3] */ 931*4882a593Smuzhiyun #define WM8995_AIF2_ADCDAT_SRC 0x0004 /* AIF2_ADCDAT_SRC */ 932*4882a593Smuzhiyun #define WM8995_AIF2_ADCDAT_SRC_MASK 0x0004 /* AIF2_ADCDAT_SRC */ 933*4882a593Smuzhiyun #define WM8995_AIF2_ADCDAT_SRC_SHIFT 2 /* AIF2_ADCDAT_SRC */ 934*4882a593Smuzhiyun #define WM8995_AIF2_ADCDAT_SRC_WIDTH 1 /* AIF2_ADCDAT_SRC */ 935*4882a593Smuzhiyun #define WM8995_AIF2_DACDAT_SRC 0x0002 /* AIF2_DACDAT_SRC */ 936*4882a593Smuzhiyun #define WM8995_AIF2_DACDAT_SRC_MASK 0x0002 /* AIF2_DACDAT_SRC */ 937*4882a593Smuzhiyun #define WM8995_AIF2_DACDAT_SRC_SHIFT 1 /* AIF2_DACDAT_SRC */ 938*4882a593Smuzhiyun #define WM8995_AIF2_DACDAT_SRC_WIDTH 1 /* AIF2_DACDAT_SRC */ 939*4882a593Smuzhiyun #define WM8995_AIF1_DACDAT_SRC 0x0001 /* AIF1_DACDAT_SRC */ 940*4882a593Smuzhiyun #define WM8995_AIF1_DACDAT_SRC_MASK 0x0001 /* AIF1_DACDAT_SRC */ 941*4882a593Smuzhiyun #define WM8995_AIF1_DACDAT_SRC_SHIFT 0 /* AIF1_DACDAT_SRC */ 942*4882a593Smuzhiyun #define WM8995_AIF1_DACDAT_SRC_WIDTH 1 /* AIF1_DACDAT_SRC */ 943*4882a593Smuzhiyun 944*4882a593Smuzhiyun /* 945*4882a593Smuzhiyun * R16 (0x10) - Left Line Input 1 Volume 946*4882a593Smuzhiyun */ 947*4882a593Smuzhiyun #define WM8995_IN1_VU 0x0080 /* IN1_VU */ 948*4882a593Smuzhiyun #define WM8995_IN1_VU_MASK 0x0080 /* IN1_VU */ 949*4882a593Smuzhiyun #define WM8995_IN1_VU_SHIFT 7 /* IN1_VU */ 950*4882a593Smuzhiyun #define WM8995_IN1_VU_WIDTH 1 /* IN1_VU */ 951*4882a593Smuzhiyun #define WM8995_IN1L_ZC 0x0020 /* IN1L_ZC */ 952*4882a593Smuzhiyun #define WM8995_IN1L_ZC_MASK 0x0020 /* IN1L_ZC */ 953*4882a593Smuzhiyun #define WM8995_IN1L_ZC_SHIFT 5 /* IN1L_ZC */ 954*4882a593Smuzhiyun #define WM8995_IN1L_ZC_WIDTH 1 /* IN1L_ZC */ 955*4882a593Smuzhiyun #define WM8995_IN1L_VOL_MASK 0x001F /* IN1L_VOL - [4:0] */ 956*4882a593Smuzhiyun #define WM8995_IN1L_VOL_SHIFT 0 /* IN1L_VOL - [4:0] */ 957*4882a593Smuzhiyun #define WM8995_IN1L_VOL_WIDTH 5 /* IN1L_VOL - [4:0] */ 958*4882a593Smuzhiyun 959*4882a593Smuzhiyun /* 960*4882a593Smuzhiyun * R17 (0x11) - Right Line Input 1 Volume 961*4882a593Smuzhiyun */ 962*4882a593Smuzhiyun #define WM8995_IN1_VU 0x0080 /* IN1_VU */ 963*4882a593Smuzhiyun #define WM8995_IN1_VU_MASK 0x0080 /* IN1_VU */ 964*4882a593Smuzhiyun #define WM8995_IN1_VU_SHIFT 7 /* IN1_VU */ 965*4882a593Smuzhiyun #define WM8995_IN1_VU_WIDTH 1 /* IN1_VU */ 966*4882a593Smuzhiyun #define WM8995_IN1R_ZC 0x0020 /* IN1R_ZC */ 967*4882a593Smuzhiyun #define WM8995_IN1R_ZC_MASK 0x0020 /* IN1R_ZC */ 968*4882a593Smuzhiyun #define WM8995_IN1R_ZC_SHIFT 5 /* IN1R_ZC */ 969*4882a593Smuzhiyun #define WM8995_IN1R_ZC_WIDTH 1 /* IN1R_ZC */ 970*4882a593Smuzhiyun #define WM8995_IN1R_VOL_MASK 0x001F /* IN1R_VOL - [4:0] */ 971*4882a593Smuzhiyun #define WM8995_IN1R_VOL_SHIFT 0 /* IN1R_VOL - [4:0] */ 972*4882a593Smuzhiyun #define WM8995_IN1R_VOL_WIDTH 5 /* IN1R_VOL - [4:0] */ 973*4882a593Smuzhiyun 974*4882a593Smuzhiyun /* 975*4882a593Smuzhiyun * R18 (0x12) - Left Line Input Control 976*4882a593Smuzhiyun */ 977*4882a593Smuzhiyun #define WM8995_IN1L_BOOST_MASK 0x0030 /* IN1L_BOOST - [5:4] */ 978*4882a593Smuzhiyun #define WM8995_IN1L_BOOST_SHIFT 4 /* IN1L_BOOST - [5:4] */ 979*4882a593Smuzhiyun #define WM8995_IN1L_BOOST_WIDTH 2 /* IN1L_BOOST - [5:4] */ 980*4882a593Smuzhiyun #define WM8995_IN1L_MODE_MASK 0x000C /* IN1L_MODE - [3:2] */ 981*4882a593Smuzhiyun #define WM8995_IN1L_MODE_SHIFT 2 /* IN1L_MODE - [3:2] */ 982*4882a593Smuzhiyun #define WM8995_IN1L_MODE_WIDTH 2 /* IN1L_MODE - [3:2] */ 983*4882a593Smuzhiyun #define WM8995_IN1R_MODE_MASK 0x0003 /* IN1R_MODE - [1:0] */ 984*4882a593Smuzhiyun #define WM8995_IN1R_MODE_SHIFT 0 /* IN1R_MODE - [1:0] */ 985*4882a593Smuzhiyun #define WM8995_IN1R_MODE_WIDTH 2 /* IN1R_MODE - [1:0] */ 986*4882a593Smuzhiyun 987*4882a593Smuzhiyun /* 988*4882a593Smuzhiyun * R24 (0x18) - DAC1 Left Volume 989*4882a593Smuzhiyun */ 990*4882a593Smuzhiyun #define WM8995_DAC1L_MUTE 0x0200 /* DAC1L_MUTE */ 991*4882a593Smuzhiyun #define WM8995_DAC1L_MUTE_MASK 0x0200 /* DAC1L_MUTE */ 992*4882a593Smuzhiyun #define WM8995_DAC1L_MUTE_SHIFT 9 /* DAC1L_MUTE */ 993*4882a593Smuzhiyun #define WM8995_DAC1L_MUTE_WIDTH 1 /* DAC1L_MUTE */ 994*4882a593Smuzhiyun #define WM8995_DAC1_VU 0x0100 /* DAC1_VU */ 995*4882a593Smuzhiyun #define WM8995_DAC1_VU_MASK 0x0100 /* DAC1_VU */ 996*4882a593Smuzhiyun #define WM8995_DAC1_VU_SHIFT 8 /* DAC1_VU */ 997*4882a593Smuzhiyun #define WM8995_DAC1_VU_WIDTH 1 /* DAC1_VU */ 998*4882a593Smuzhiyun #define WM8995_DAC1L_VOL_MASK 0x00FF /* DAC1L_VOL - [7:0] */ 999*4882a593Smuzhiyun #define WM8995_DAC1L_VOL_SHIFT 0 /* DAC1L_VOL - [7:0] */ 1000*4882a593Smuzhiyun #define WM8995_DAC1L_VOL_WIDTH 8 /* DAC1L_VOL - [7:0] */ 1001*4882a593Smuzhiyun 1002*4882a593Smuzhiyun /* 1003*4882a593Smuzhiyun * R25 (0x19) - DAC1 Right Volume 1004*4882a593Smuzhiyun */ 1005*4882a593Smuzhiyun #define WM8995_DAC1R_MUTE 0x0200 /* DAC1R_MUTE */ 1006*4882a593Smuzhiyun #define WM8995_DAC1R_MUTE_MASK 0x0200 /* DAC1R_MUTE */ 1007*4882a593Smuzhiyun #define WM8995_DAC1R_MUTE_SHIFT 9 /* DAC1R_MUTE */ 1008*4882a593Smuzhiyun #define WM8995_DAC1R_MUTE_WIDTH 1 /* DAC1R_MUTE */ 1009*4882a593Smuzhiyun #define WM8995_DAC1_VU 0x0100 /* DAC1_VU */ 1010*4882a593Smuzhiyun #define WM8995_DAC1_VU_MASK 0x0100 /* DAC1_VU */ 1011*4882a593Smuzhiyun #define WM8995_DAC1_VU_SHIFT 8 /* DAC1_VU */ 1012*4882a593Smuzhiyun #define WM8995_DAC1_VU_WIDTH 1 /* DAC1_VU */ 1013*4882a593Smuzhiyun #define WM8995_DAC1R_VOL_MASK 0x00FF /* DAC1R_VOL - [7:0] */ 1014*4882a593Smuzhiyun #define WM8995_DAC1R_VOL_SHIFT 0 /* DAC1R_VOL - [7:0] */ 1015*4882a593Smuzhiyun #define WM8995_DAC1R_VOL_WIDTH 8 /* DAC1R_VOL - [7:0] */ 1016*4882a593Smuzhiyun 1017*4882a593Smuzhiyun /* 1018*4882a593Smuzhiyun * R26 (0x1A) - DAC2 Left Volume 1019*4882a593Smuzhiyun */ 1020*4882a593Smuzhiyun #define WM8995_DAC2L_MUTE 0x0200 /* DAC2L_MUTE */ 1021*4882a593Smuzhiyun #define WM8995_DAC2L_MUTE_MASK 0x0200 /* DAC2L_MUTE */ 1022*4882a593Smuzhiyun #define WM8995_DAC2L_MUTE_SHIFT 9 /* DAC2L_MUTE */ 1023*4882a593Smuzhiyun #define WM8995_DAC2L_MUTE_WIDTH 1 /* DAC2L_MUTE */ 1024*4882a593Smuzhiyun #define WM8995_DAC2_VU 0x0100 /* DAC2_VU */ 1025*4882a593Smuzhiyun #define WM8995_DAC2_VU_MASK 0x0100 /* DAC2_VU */ 1026*4882a593Smuzhiyun #define WM8995_DAC2_VU_SHIFT 8 /* DAC2_VU */ 1027*4882a593Smuzhiyun #define WM8995_DAC2_VU_WIDTH 1 /* DAC2_VU */ 1028*4882a593Smuzhiyun #define WM8995_DAC2L_VOL_MASK 0x00FF /* DAC2L_VOL - [7:0] */ 1029*4882a593Smuzhiyun #define WM8995_DAC2L_VOL_SHIFT 0 /* DAC2L_VOL - [7:0] */ 1030*4882a593Smuzhiyun #define WM8995_DAC2L_VOL_WIDTH 8 /* DAC2L_VOL - [7:0] */ 1031*4882a593Smuzhiyun 1032*4882a593Smuzhiyun /* 1033*4882a593Smuzhiyun * R27 (0x1B) - DAC2 Right Volume 1034*4882a593Smuzhiyun */ 1035*4882a593Smuzhiyun #define WM8995_DAC2R_MUTE 0x0200 /* DAC2R_MUTE */ 1036*4882a593Smuzhiyun #define WM8995_DAC2R_MUTE_MASK 0x0200 /* DAC2R_MUTE */ 1037*4882a593Smuzhiyun #define WM8995_DAC2R_MUTE_SHIFT 9 /* DAC2R_MUTE */ 1038*4882a593Smuzhiyun #define WM8995_DAC2R_MUTE_WIDTH 1 /* DAC2R_MUTE */ 1039*4882a593Smuzhiyun #define WM8995_DAC2_VU 0x0100 /* DAC2_VU */ 1040*4882a593Smuzhiyun #define WM8995_DAC2_VU_MASK 0x0100 /* DAC2_VU */ 1041*4882a593Smuzhiyun #define WM8995_DAC2_VU_SHIFT 8 /* DAC2_VU */ 1042*4882a593Smuzhiyun #define WM8995_DAC2_VU_WIDTH 1 /* DAC2_VU */ 1043*4882a593Smuzhiyun #define WM8995_DAC2R_VOL_MASK 0x00FF /* DAC2R_VOL - [7:0] */ 1044*4882a593Smuzhiyun #define WM8995_DAC2R_VOL_SHIFT 0 /* DAC2R_VOL - [7:0] */ 1045*4882a593Smuzhiyun #define WM8995_DAC2R_VOL_WIDTH 8 /* DAC2R_VOL - [7:0] */ 1046*4882a593Smuzhiyun 1047*4882a593Smuzhiyun /* 1048*4882a593Smuzhiyun * R28 (0x1C) - Output Volume ZC (1) 1049*4882a593Smuzhiyun */ 1050*4882a593Smuzhiyun #define WM8995_HPOUT2L_ZC 0x0008 /* HPOUT2L_ZC */ 1051*4882a593Smuzhiyun #define WM8995_HPOUT2L_ZC_MASK 0x0008 /* HPOUT2L_ZC */ 1052*4882a593Smuzhiyun #define WM8995_HPOUT2L_ZC_SHIFT 3 /* HPOUT2L_ZC */ 1053*4882a593Smuzhiyun #define WM8995_HPOUT2L_ZC_WIDTH 1 /* HPOUT2L_ZC */ 1054*4882a593Smuzhiyun #define WM8995_HPOUT2R_ZC 0x0004 /* HPOUT2R_ZC */ 1055*4882a593Smuzhiyun #define WM8995_HPOUT2R_ZC_MASK 0x0004 /* HPOUT2R_ZC */ 1056*4882a593Smuzhiyun #define WM8995_HPOUT2R_ZC_SHIFT 2 /* HPOUT2R_ZC */ 1057*4882a593Smuzhiyun #define WM8995_HPOUT2R_ZC_WIDTH 1 /* HPOUT2R_ZC */ 1058*4882a593Smuzhiyun #define WM8995_HPOUT1L_ZC 0x0002 /* HPOUT1L_ZC */ 1059*4882a593Smuzhiyun #define WM8995_HPOUT1L_ZC_MASK 0x0002 /* HPOUT1L_ZC */ 1060*4882a593Smuzhiyun #define WM8995_HPOUT1L_ZC_SHIFT 1 /* HPOUT1L_ZC */ 1061*4882a593Smuzhiyun #define WM8995_HPOUT1L_ZC_WIDTH 1 /* HPOUT1L_ZC */ 1062*4882a593Smuzhiyun #define WM8995_HPOUT1R_ZC 0x0001 /* HPOUT1R_ZC */ 1063*4882a593Smuzhiyun #define WM8995_HPOUT1R_ZC_MASK 0x0001 /* HPOUT1R_ZC */ 1064*4882a593Smuzhiyun #define WM8995_HPOUT1R_ZC_SHIFT 0 /* HPOUT1R_ZC */ 1065*4882a593Smuzhiyun #define WM8995_HPOUT1R_ZC_WIDTH 1 /* HPOUT1R_ZC */ 1066*4882a593Smuzhiyun 1067*4882a593Smuzhiyun /* 1068*4882a593Smuzhiyun * R32 (0x20) - MICBIAS (1) 1069*4882a593Smuzhiyun */ 1070*4882a593Smuzhiyun #define WM8995_MICB1_MODE 0x0008 /* MICB1_MODE */ 1071*4882a593Smuzhiyun #define WM8995_MICB1_MODE_MASK 0x0008 /* MICB1_MODE */ 1072*4882a593Smuzhiyun #define WM8995_MICB1_MODE_SHIFT 3 /* MICB1_MODE */ 1073*4882a593Smuzhiyun #define WM8995_MICB1_MODE_WIDTH 1 /* MICB1_MODE */ 1074*4882a593Smuzhiyun #define WM8995_MICB1_LVL_MASK 0x0006 /* MICB1_LVL - [2:1] */ 1075*4882a593Smuzhiyun #define WM8995_MICB1_LVL_SHIFT 1 /* MICB1_LVL - [2:1] */ 1076*4882a593Smuzhiyun #define WM8995_MICB1_LVL_WIDTH 2 /* MICB1_LVL - [2:1] */ 1077*4882a593Smuzhiyun #define WM8995_MICB1_DISCH 0x0001 /* MICB1_DISCH */ 1078*4882a593Smuzhiyun #define WM8995_MICB1_DISCH_MASK 0x0001 /* MICB1_DISCH */ 1079*4882a593Smuzhiyun #define WM8995_MICB1_DISCH_SHIFT 0 /* MICB1_DISCH */ 1080*4882a593Smuzhiyun #define WM8995_MICB1_DISCH_WIDTH 1 /* MICB1_DISCH */ 1081*4882a593Smuzhiyun 1082*4882a593Smuzhiyun /* 1083*4882a593Smuzhiyun * R33 (0x21) - MICBIAS (2) 1084*4882a593Smuzhiyun */ 1085*4882a593Smuzhiyun #define WM8995_MICB2_MODE 0x0008 /* MICB2_MODE */ 1086*4882a593Smuzhiyun #define WM8995_MICB2_MODE_MASK 0x0008 /* MICB2_MODE */ 1087*4882a593Smuzhiyun #define WM8995_MICB2_MODE_SHIFT 3 /* MICB2_MODE */ 1088*4882a593Smuzhiyun #define WM8995_MICB2_MODE_WIDTH 1 /* MICB2_MODE */ 1089*4882a593Smuzhiyun #define WM8995_MICB2_LVL_MASK 0x0006 /* MICB2_LVL - [2:1] */ 1090*4882a593Smuzhiyun #define WM8995_MICB2_LVL_SHIFT 1 /* MICB2_LVL - [2:1] */ 1091*4882a593Smuzhiyun #define WM8995_MICB2_LVL_WIDTH 2 /* MICB2_LVL - [2:1] */ 1092*4882a593Smuzhiyun #define WM8995_MICB2_DISCH 0x0001 /* MICB2_DISCH */ 1093*4882a593Smuzhiyun #define WM8995_MICB2_DISCH_MASK 0x0001 /* MICB2_DISCH */ 1094*4882a593Smuzhiyun #define WM8995_MICB2_DISCH_SHIFT 0 /* MICB2_DISCH */ 1095*4882a593Smuzhiyun #define WM8995_MICB2_DISCH_WIDTH 1 /* MICB2_DISCH */ 1096*4882a593Smuzhiyun 1097*4882a593Smuzhiyun /* 1098*4882a593Smuzhiyun * R40 (0x28) - LDO 1 1099*4882a593Smuzhiyun */ 1100*4882a593Smuzhiyun #define WM8995_LDO1_MODE 0x0020 /* LDO1_MODE */ 1101*4882a593Smuzhiyun #define WM8995_LDO1_MODE_MASK 0x0020 /* LDO1_MODE */ 1102*4882a593Smuzhiyun #define WM8995_LDO1_MODE_SHIFT 5 /* LDO1_MODE */ 1103*4882a593Smuzhiyun #define WM8995_LDO1_MODE_WIDTH 1 /* LDO1_MODE */ 1104*4882a593Smuzhiyun #define WM8995_LDO1_VSEL_MASK 0x0006 /* LDO1_VSEL - [2:1] */ 1105*4882a593Smuzhiyun #define WM8995_LDO1_VSEL_SHIFT 1 /* LDO1_VSEL - [2:1] */ 1106*4882a593Smuzhiyun #define WM8995_LDO1_VSEL_WIDTH 2 /* LDO1_VSEL - [2:1] */ 1107*4882a593Smuzhiyun #define WM8995_LDO1_DISCH 0x0001 /* LDO1_DISCH */ 1108*4882a593Smuzhiyun #define WM8995_LDO1_DISCH_MASK 0x0001 /* LDO1_DISCH */ 1109*4882a593Smuzhiyun #define WM8995_LDO1_DISCH_SHIFT 0 /* LDO1_DISCH */ 1110*4882a593Smuzhiyun #define WM8995_LDO1_DISCH_WIDTH 1 /* LDO1_DISCH */ 1111*4882a593Smuzhiyun 1112*4882a593Smuzhiyun /* 1113*4882a593Smuzhiyun * R41 (0x29) - LDO 2 1114*4882a593Smuzhiyun */ 1115*4882a593Smuzhiyun #define WM8995_LDO2_MODE 0x0020 /* LDO2_MODE */ 1116*4882a593Smuzhiyun #define WM8995_LDO2_MODE_MASK 0x0020 /* LDO2_MODE */ 1117*4882a593Smuzhiyun #define WM8995_LDO2_MODE_SHIFT 5 /* LDO2_MODE */ 1118*4882a593Smuzhiyun #define WM8995_LDO2_MODE_WIDTH 1 /* LDO2_MODE */ 1119*4882a593Smuzhiyun #define WM8995_LDO2_VSEL_MASK 0x001E /* LDO2_VSEL - [4:1] */ 1120*4882a593Smuzhiyun #define WM8995_LDO2_VSEL_SHIFT 1 /* LDO2_VSEL - [4:1] */ 1121*4882a593Smuzhiyun #define WM8995_LDO2_VSEL_WIDTH 4 /* LDO2_VSEL - [4:1] */ 1122*4882a593Smuzhiyun #define WM8995_LDO2_DISCH 0x0001 /* LDO2_DISCH */ 1123*4882a593Smuzhiyun #define WM8995_LDO2_DISCH_MASK 0x0001 /* LDO2_DISCH */ 1124*4882a593Smuzhiyun #define WM8995_LDO2_DISCH_SHIFT 0 /* LDO2_DISCH */ 1125*4882a593Smuzhiyun #define WM8995_LDO2_DISCH_WIDTH 1 /* LDO2_DISCH */ 1126*4882a593Smuzhiyun 1127*4882a593Smuzhiyun /* 1128*4882a593Smuzhiyun * R48 (0x30) - Accessory Detect Mode1 1129*4882a593Smuzhiyun */ 1130*4882a593Smuzhiyun #define WM8995_JD_MODE_MASK 0x0003 /* JD_MODE - [1:0] */ 1131*4882a593Smuzhiyun #define WM8995_JD_MODE_SHIFT 0 /* JD_MODE - [1:0] */ 1132*4882a593Smuzhiyun #define WM8995_JD_MODE_WIDTH 2 /* JD_MODE - [1:0] */ 1133*4882a593Smuzhiyun 1134*4882a593Smuzhiyun /* 1135*4882a593Smuzhiyun * R49 (0x31) - Accessory Detect Mode2 1136*4882a593Smuzhiyun */ 1137*4882a593Smuzhiyun #define WM8995_VID_ENA 0x0001 /* VID_ENA */ 1138*4882a593Smuzhiyun #define WM8995_VID_ENA_MASK 0x0001 /* VID_ENA */ 1139*4882a593Smuzhiyun #define WM8995_VID_ENA_SHIFT 0 /* VID_ENA */ 1140*4882a593Smuzhiyun #define WM8995_VID_ENA_WIDTH 1 /* VID_ENA */ 1141*4882a593Smuzhiyun 1142*4882a593Smuzhiyun /* 1143*4882a593Smuzhiyun * R52 (0x34) - Headphone Detect1 1144*4882a593Smuzhiyun */ 1145*4882a593Smuzhiyun #define WM8995_HP_RAMPRATE 0x0002 /* HP_RAMPRATE */ 1146*4882a593Smuzhiyun #define WM8995_HP_RAMPRATE_MASK 0x0002 /* HP_RAMPRATE */ 1147*4882a593Smuzhiyun #define WM8995_HP_RAMPRATE_SHIFT 1 /* HP_RAMPRATE */ 1148*4882a593Smuzhiyun #define WM8995_HP_RAMPRATE_WIDTH 1 /* HP_RAMPRATE */ 1149*4882a593Smuzhiyun #define WM8995_HP_POLL 0x0001 /* HP_POLL */ 1150*4882a593Smuzhiyun #define WM8995_HP_POLL_MASK 0x0001 /* HP_POLL */ 1151*4882a593Smuzhiyun #define WM8995_HP_POLL_SHIFT 0 /* HP_POLL */ 1152*4882a593Smuzhiyun #define WM8995_HP_POLL_WIDTH 1 /* HP_POLL */ 1153*4882a593Smuzhiyun 1154*4882a593Smuzhiyun /* 1155*4882a593Smuzhiyun * R53 (0x35) - Headphone Detect2 1156*4882a593Smuzhiyun */ 1157*4882a593Smuzhiyun #define WM8995_HP_DONE 0x0080 /* HP_DONE */ 1158*4882a593Smuzhiyun #define WM8995_HP_DONE_MASK 0x0080 /* HP_DONE */ 1159*4882a593Smuzhiyun #define WM8995_HP_DONE_SHIFT 7 /* HP_DONE */ 1160*4882a593Smuzhiyun #define WM8995_HP_DONE_WIDTH 1 /* HP_DONE */ 1161*4882a593Smuzhiyun #define WM8995_HP_LVL_MASK 0x007F /* HP_LVL - [6:0] */ 1162*4882a593Smuzhiyun #define WM8995_HP_LVL_SHIFT 0 /* HP_LVL - [6:0] */ 1163*4882a593Smuzhiyun #define WM8995_HP_LVL_WIDTH 7 /* HP_LVL - [6:0] */ 1164*4882a593Smuzhiyun 1165*4882a593Smuzhiyun /* 1166*4882a593Smuzhiyun * R56 (0x38) - Mic Detect (1) 1167*4882a593Smuzhiyun */ 1168*4882a593Smuzhiyun #define WM8995_MICD_RATE_MASK 0x7800 /* MICD_RATE - [14:11] */ 1169*4882a593Smuzhiyun #define WM8995_MICD_RATE_SHIFT 11 /* MICD_RATE - [14:11] */ 1170*4882a593Smuzhiyun #define WM8995_MICD_RATE_WIDTH 4 /* MICD_RATE - [14:11] */ 1171*4882a593Smuzhiyun #define WM8995_MICD_LVL_SEL_MASK 0x01F8 /* MICD_LVL_SEL - [8:3] */ 1172*4882a593Smuzhiyun #define WM8995_MICD_LVL_SEL_SHIFT 3 /* MICD_LVL_SEL - [8:3] */ 1173*4882a593Smuzhiyun #define WM8995_MICD_LVL_SEL_WIDTH 6 /* MICD_LVL_SEL - [8:3] */ 1174*4882a593Smuzhiyun #define WM8995_MICD_DBTIME 0x0002 /* MICD_DBTIME */ 1175*4882a593Smuzhiyun #define WM8995_MICD_DBTIME_MASK 0x0002 /* MICD_DBTIME */ 1176*4882a593Smuzhiyun #define WM8995_MICD_DBTIME_SHIFT 1 /* MICD_DBTIME */ 1177*4882a593Smuzhiyun #define WM8995_MICD_DBTIME_WIDTH 1 /* MICD_DBTIME */ 1178*4882a593Smuzhiyun #define WM8995_MICD_ENA 0x0001 /* MICD_ENA */ 1179*4882a593Smuzhiyun #define WM8995_MICD_ENA_MASK 0x0001 /* MICD_ENA */ 1180*4882a593Smuzhiyun #define WM8995_MICD_ENA_SHIFT 0 /* MICD_ENA */ 1181*4882a593Smuzhiyun #define WM8995_MICD_ENA_WIDTH 1 /* MICD_ENA */ 1182*4882a593Smuzhiyun 1183*4882a593Smuzhiyun /* 1184*4882a593Smuzhiyun * R57 (0x39) - Mic Detect (2) 1185*4882a593Smuzhiyun */ 1186*4882a593Smuzhiyun #define WM8995_MICD_LVL_MASK 0x01FC /* MICD_LVL - [8:2] */ 1187*4882a593Smuzhiyun #define WM8995_MICD_LVL_SHIFT 2 /* MICD_LVL - [8:2] */ 1188*4882a593Smuzhiyun #define WM8995_MICD_LVL_WIDTH 7 /* MICD_LVL - [8:2] */ 1189*4882a593Smuzhiyun #define WM8995_MICD_VALID 0x0002 /* MICD_VALID */ 1190*4882a593Smuzhiyun #define WM8995_MICD_VALID_MASK 0x0002 /* MICD_VALID */ 1191*4882a593Smuzhiyun #define WM8995_MICD_VALID_SHIFT 1 /* MICD_VALID */ 1192*4882a593Smuzhiyun #define WM8995_MICD_VALID_WIDTH 1 /* MICD_VALID */ 1193*4882a593Smuzhiyun #define WM8995_MICD_STS 0x0001 /* MICD_STS */ 1194*4882a593Smuzhiyun #define WM8995_MICD_STS_MASK 0x0001 /* MICD_STS */ 1195*4882a593Smuzhiyun #define WM8995_MICD_STS_SHIFT 0 /* MICD_STS */ 1196*4882a593Smuzhiyun #define WM8995_MICD_STS_WIDTH 1 /* MICD_STS */ 1197*4882a593Smuzhiyun 1198*4882a593Smuzhiyun /* 1199*4882a593Smuzhiyun * R64 (0x40) - Charge Pump (1) 1200*4882a593Smuzhiyun */ 1201*4882a593Smuzhiyun #define WM8995_CP_ENA 0x8000 /* CP_ENA */ 1202*4882a593Smuzhiyun #define WM8995_CP_ENA_MASK 0x8000 /* CP_ENA */ 1203*4882a593Smuzhiyun #define WM8995_CP_ENA_SHIFT 15 /* CP_ENA */ 1204*4882a593Smuzhiyun #define WM8995_CP_ENA_WIDTH 1 /* CP_ENA */ 1205*4882a593Smuzhiyun 1206*4882a593Smuzhiyun /* 1207*4882a593Smuzhiyun * R69 (0x45) - Class W (1) 1208*4882a593Smuzhiyun */ 1209*4882a593Smuzhiyun #define WM8995_CP_DYN_SRC_SEL_MASK 0x0300 /* CP_DYN_SRC_SEL - [9:8] */ 1210*4882a593Smuzhiyun #define WM8995_CP_DYN_SRC_SEL_SHIFT 8 /* CP_DYN_SRC_SEL - [9:8] */ 1211*4882a593Smuzhiyun #define WM8995_CP_DYN_SRC_SEL_WIDTH 2 /* CP_DYN_SRC_SEL - [9:8] */ 1212*4882a593Smuzhiyun #define WM8995_CP_DYN_PWR 0x0001 /* CP_DYN_PWR */ 1213*4882a593Smuzhiyun #define WM8995_CP_DYN_PWR_MASK 0x0001 /* CP_DYN_PWR */ 1214*4882a593Smuzhiyun #define WM8995_CP_DYN_PWR_SHIFT 0 /* CP_DYN_PWR */ 1215*4882a593Smuzhiyun #define WM8995_CP_DYN_PWR_WIDTH 1 /* CP_DYN_PWR */ 1216*4882a593Smuzhiyun 1217*4882a593Smuzhiyun /* 1218*4882a593Smuzhiyun * R80 (0x50) - DC Servo (1) 1219*4882a593Smuzhiyun */ 1220*4882a593Smuzhiyun #define WM8995_DCS_ENA_CHAN_3 0x0008 /* DCS_ENA_CHAN_3 */ 1221*4882a593Smuzhiyun #define WM8995_DCS_ENA_CHAN_3_MASK 0x0008 /* DCS_ENA_CHAN_3 */ 1222*4882a593Smuzhiyun #define WM8995_DCS_ENA_CHAN_3_SHIFT 3 /* DCS_ENA_CHAN_3 */ 1223*4882a593Smuzhiyun #define WM8995_DCS_ENA_CHAN_3_WIDTH 1 /* DCS_ENA_CHAN_3 */ 1224*4882a593Smuzhiyun #define WM8995_DCS_ENA_CHAN_2 0x0004 /* DCS_ENA_CHAN_2 */ 1225*4882a593Smuzhiyun #define WM8995_DCS_ENA_CHAN_2_MASK 0x0004 /* DCS_ENA_CHAN_2 */ 1226*4882a593Smuzhiyun #define WM8995_DCS_ENA_CHAN_2_SHIFT 2 /* DCS_ENA_CHAN_2 */ 1227*4882a593Smuzhiyun #define WM8995_DCS_ENA_CHAN_2_WIDTH 1 /* DCS_ENA_CHAN_2 */ 1228*4882a593Smuzhiyun #define WM8995_DCS_ENA_CHAN_1 0x0002 /* DCS_ENA_CHAN_1 */ 1229*4882a593Smuzhiyun #define WM8995_DCS_ENA_CHAN_1_MASK 0x0002 /* DCS_ENA_CHAN_1 */ 1230*4882a593Smuzhiyun #define WM8995_DCS_ENA_CHAN_1_SHIFT 1 /* DCS_ENA_CHAN_1 */ 1231*4882a593Smuzhiyun #define WM8995_DCS_ENA_CHAN_1_WIDTH 1 /* DCS_ENA_CHAN_1 */ 1232*4882a593Smuzhiyun #define WM8995_DCS_ENA_CHAN_0 0x0001 /* DCS_ENA_CHAN_0 */ 1233*4882a593Smuzhiyun #define WM8995_DCS_ENA_CHAN_0_MASK 0x0001 /* DCS_ENA_CHAN_0 */ 1234*4882a593Smuzhiyun #define WM8995_DCS_ENA_CHAN_0_SHIFT 0 /* DCS_ENA_CHAN_0 */ 1235*4882a593Smuzhiyun #define WM8995_DCS_ENA_CHAN_0_WIDTH 1 /* DCS_ENA_CHAN_0 */ 1236*4882a593Smuzhiyun 1237*4882a593Smuzhiyun /* 1238*4882a593Smuzhiyun * R81 (0x51) - DC Servo (2) 1239*4882a593Smuzhiyun */ 1240*4882a593Smuzhiyun #define WM8995_DCS_TRIG_SINGLE_3 0x8000 /* DCS_TRIG_SINGLE_3 */ 1241*4882a593Smuzhiyun #define WM8995_DCS_TRIG_SINGLE_3_MASK 0x8000 /* DCS_TRIG_SINGLE_3 */ 1242*4882a593Smuzhiyun #define WM8995_DCS_TRIG_SINGLE_3_SHIFT 15 /* DCS_TRIG_SINGLE_3 */ 1243*4882a593Smuzhiyun #define WM8995_DCS_TRIG_SINGLE_3_WIDTH 1 /* DCS_TRIG_SINGLE_3 */ 1244*4882a593Smuzhiyun #define WM8995_DCS_TRIG_SINGLE_2 0x4000 /* DCS_TRIG_SINGLE_2 */ 1245*4882a593Smuzhiyun #define WM8995_DCS_TRIG_SINGLE_2_MASK 0x4000 /* DCS_TRIG_SINGLE_2 */ 1246*4882a593Smuzhiyun #define WM8995_DCS_TRIG_SINGLE_2_SHIFT 14 /* DCS_TRIG_SINGLE_2 */ 1247*4882a593Smuzhiyun #define WM8995_DCS_TRIG_SINGLE_2_WIDTH 1 /* DCS_TRIG_SINGLE_2 */ 1248*4882a593Smuzhiyun #define WM8995_DCS_TRIG_SINGLE_1 0x2000 /* DCS_TRIG_SINGLE_1 */ 1249*4882a593Smuzhiyun #define WM8995_DCS_TRIG_SINGLE_1_MASK 0x2000 /* DCS_TRIG_SINGLE_1 */ 1250*4882a593Smuzhiyun #define WM8995_DCS_TRIG_SINGLE_1_SHIFT 13 /* DCS_TRIG_SINGLE_1 */ 1251*4882a593Smuzhiyun #define WM8995_DCS_TRIG_SINGLE_1_WIDTH 1 /* DCS_TRIG_SINGLE_1 */ 1252*4882a593Smuzhiyun #define WM8995_DCS_TRIG_SINGLE_0 0x1000 /* DCS_TRIG_SINGLE_0 */ 1253*4882a593Smuzhiyun #define WM8995_DCS_TRIG_SINGLE_0_MASK 0x1000 /* DCS_TRIG_SINGLE_0 */ 1254*4882a593Smuzhiyun #define WM8995_DCS_TRIG_SINGLE_0_SHIFT 12 /* DCS_TRIG_SINGLE_0 */ 1255*4882a593Smuzhiyun #define WM8995_DCS_TRIG_SINGLE_0_WIDTH 1 /* DCS_TRIG_SINGLE_0 */ 1256*4882a593Smuzhiyun #define WM8995_DCS_TRIG_SERIES_3 0x0800 /* DCS_TRIG_SERIES_3 */ 1257*4882a593Smuzhiyun #define WM8995_DCS_TRIG_SERIES_3_MASK 0x0800 /* DCS_TRIG_SERIES_3 */ 1258*4882a593Smuzhiyun #define WM8995_DCS_TRIG_SERIES_3_SHIFT 11 /* DCS_TRIG_SERIES_3 */ 1259*4882a593Smuzhiyun #define WM8995_DCS_TRIG_SERIES_3_WIDTH 1 /* DCS_TRIG_SERIES_3 */ 1260*4882a593Smuzhiyun #define WM8995_DCS_TRIG_SERIES_2 0x0400 /* DCS_TRIG_SERIES_2 */ 1261*4882a593Smuzhiyun #define WM8995_DCS_TRIG_SERIES_2_MASK 0x0400 /* DCS_TRIG_SERIES_2 */ 1262*4882a593Smuzhiyun #define WM8995_DCS_TRIG_SERIES_2_SHIFT 10 /* DCS_TRIG_SERIES_2 */ 1263*4882a593Smuzhiyun #define WM8995_DCS_TRIG_SERIES_2_WIDTH 1 /* DCS_TRIG_SERIES_2 */ 1264*4882a593Smuzhiyun #define WM8995_DCS_TRIG_SERIES_1 0x0200 /* DCS_TRIG_SERIES_1 */ 1265*4882a593Smuzhiyun #define WM8995_DCS_TRIG_SERIES_1_MASK 0x0200 /* DCS_TRIG_SERIES_1 */ 1266*4882a593Smuzhiyun #define WM8995_DCS_TRIG_SERIES_1_SHIFT 9 /* DCS_TRIG_SERIES_1 */ 1267*4882a593Smuzhiyun #define WM8995_DCS_TRIG_SERIES_1_WIDTH 1 /* DCS_TRIG_SERIES_1 */ 1268*4882a593Smuzhiyun #define WM8995_DCS_TRIG_SERIES_0 0x0100 /* DCS_TRIG_SERIES_0 */ 1269*4882a593Smuzhiyun #define WM8995_DCS_TRIG_SERIES_0_MASK 0x0100 /* DCS_TRIG_SERIES_0 */ 1270*4882a593Smuzhiyun #define WM8995_DCS_TRIG_SERIES_0_SHIFT 8 /* DCS_TRIG_SERIES_0 */ 1271*4882a593Smuzhiyun #define WM8995_DCS_TRIG_SERIES_0_WIDTH 1 /* DCS_TRIG_SERIES_0 */ 1272*4882a593Smuzhiyun #define WM8995_DCS_TRIG_STARTUP_3 0x0080 /* DCS_TRIG_STARTUP_3 */ 1273*4882a593Smuzhiyun #define WM8995_DCS_TRIG_STARTUP_3_MASK 0x0080 /* DCS_TRIG_STARTUP_3 */ 1274*4882a593Smuzhiyun #define WM8995_DCS_TRIG_STARTUP_3_SHIFT 7 /* DCS_TRIG_STARTUP_3 */ 1275*4882a593Smuzhiyun #define WM8995_DCS_TRIG_STARTUP_3_WIDTH 1 /* DCS_TRIG_STARTUP_3 */ 1276*4882a593Smuzhiyun #define WM8995_DCS_TRIG_STARTUP_2 0x0040 /* DCS_TRIG_STARTUP_2 */ 1277*4882a593Smuzhiyun #define WM8995_DCS_TRIG_STARTUP_2_MASK 0x0040 /* DCS_TRIG_STARTUP_2 */ 1278*4882a593Smuzhiyun #define WM8995_DCS_TRIG_STARTUP_2_SHIFT 6 /* DCS_TRIG_STARTUP_2 */ 1279*4882a593Smuzhiyun #define WM8995_DCS_TRIG_STARTUP_2_WIDTH 1 /* DCS_TRIG_STARTUP_2 */ 1280*4882a593Smuzhiyun #define WM8995_DCS_TRIG_STARTUP_1 0x0020 /* DCS_TRIG_STARTUP_1 */ 1281*4882a593Smuzhiyun #define WM8995_DCS_TRIG_STARTUP_1_MASK 0x0020 /* DCS_TRIG_STARTUP_1 */ 1282*4882a593Smuzhiyun #define WM8995_DCS_TRIG_STARTUP_1_SHIFT 5 /* DCS_TRIG_STARTUP_1 */ 1283*4882a593Smuzhiyun #define WM8995_DCS_TRIG_STARTUP_1_WIDTH 1 /* DCS_TRIG_STARTUP_1 */ 1284*4882a593Smuzhiyun #define WM8995_DCS_TRIG_STARTUP_0 0x0010 /* DCS_TRIG_STARTUP_0 */ 1285*4882a593Smuzhiyun #define WM8995_DCS_TRIG_STARTUP_0_MASK 0x0010 /* DCS_TRIG_STARTUP_0 */ 1286*4882a593Smuzhiyun #define WM8995_DCS_TRIG_STARTUP_0_SHIFT 4 /* DCS_TRIG_STARTUP_0 */ 1287*4882a593Smuzhiyun #define WM8995_DCS_TRIG_STARTUP_0_WIDTH 1 /* DCS_TRIG_STARTUP_0 */ 1288*4882a593Smuzhiyun #define WM8995_DCS_TRIG_DAC_WR_3 0x0008 /* DCS_TRIG_DAC_WR_3 */ 1289*4882a593Smuzhiyun #define WM8995_DCS_TRIG_DAC_WR_3_MASK 0x0008 /* DCS_TRIG_DAC_WR_3 */ 1290*4882a593Smuzhiyun #define WM8995_DCS_TRIG_DAC_WR_3_SHIFT 3 /* DCS_TRIG_DAC_WR_3 */ 1291*4882a593Smuzhiyun #define WM8995_DCS_TRIG_DAC_WR_3_WIDTH 1 /* DCS_TRIG_DAC_WR_3 */ 1292*4882a593Smuzhiyun #define WM8995_DCS_TRIG_DAC_WR_2 0x0004 /* DCS_TRIG_DAC_WR_2 */ 1293*4882a593Smuzhiyun #define WM8995_DCS_TRIG_DAC_WR_2_MASK 0x0004 /* DCS_TRIG_DAC_WR_2 */ 1294*4882a593Smuzhiyun #define WM8995_DCS_TRIG_DAC_WR_2_SHIFT 2 /* DCS_TRIG_DAC_WR_2 */ 1295*4882a593Smuzhiyun #define WM8995_DCS_TRIG_DAC_WR_2_WIDTH 1 /* DCS_TRIG_DAC_WR_2 */ 1296*4882a593Smuzhiyun #define WM8995_DCS_TRIG_DAC_WR_1 0x0002 /* DCS_TRIG_DAC_WR_1 */ 1297*4882a593Smuzhiyun #define WM8995_DCS_TRIG_DAC_WR_1_MASK 0x0002 /* DCS_TRIG_DAC_WR_1 */ 1298*4882a593Smuzhiyun #define WM8995_DCS_TRIG_DAC_WR_1_SHIFT 1 /* DCS_TRIG_DAC_WR_1 */ 1299*4882a593Smuzhiyun #define WM8995_DCS_TRIG_DAC_WR_1_WIDTH 1 /* DCS_TRIG_DAC_WR_1 */ 1300*4882a593Smuzhiyun #define WM8995_DCS_TRIG_DAC_WR_0 0x0001 /* DCS_TRIG_DAC_WR_0 */ 1301*4882a593Smuzhiyun #define WM8995_DCS_TRIG_DAC_WR_0_MASK 0x0001 /* DCS_TRIG_DAC_WR_0 */ 1302*4882a593Smuzhiyun #define WM8995_DCS_TRIG_DAC_WR_0_SHIFT 0 /* DCS_TRIG_DAC_WR_0 */ 1303*4882a593Smuzhiyun #define WM8995_DCS_TRIG_DAC_WR_0_WIDTH 1 /* DCS_TRIG_DAC_WR_0 */ 1304*4882a593Smuzhiyun 1305*4882a593Smuzhiyun /* 1306*4882a593Smuzhiyun * R82 (0x52) - DC Servo (3) 1307*4882a593Smuzhiyun */ 1308*4882a593Smuzhiyun #define WM8995_DCS_TIMER_PERIOD_23_MASK 0x0F00 /* DCS_TIMER_PERIOD_23 - [11:8] */ 1309*4882a593Smuzhiyun #define WM8995_DCS_TIMER_PERIOD_23_SHIFT 8 /* DCS_TIMER_PERIOD_23 - [11:8] */ 1310*4882a593Smuzhiyun #define WM8995_DCS_TIMER_PERIOD_23_WIDTH 4 /* DCS_TIMER_PERIOD_23 - [11:8] */ 1311*4882a593Smuzhiyun #define WM8995_DCS_TIMER_PERIOD_01_MASK 0x000F /* DCS_TIMER_PERIOD_01 - [3:0] */ 1312*4882a593Smuzhiyun #define WM8995_DCS_TIMER_PERIOD_01_SHIFT 0 /* DCS_TIMER_PERIOD_01 - [3:0] */ 1313*4882a593Smuzhiyun #define WM8995_DCS_TIMER_PERIOD_01_WIDTH 4 /* DCS_TIMER_PERIOD_01 - [3:0] */ 1314*4882a593Smuzhiyun 1315*4882a593Smuzhiyun /* 1316*4882a593Smuzhiyun * R84 (0x54) - DC Servo (5) 1317*4882a593Smuzhiyun */ 1318*4882a593Smuzhiyun #define WM8995_DCS_SERIES_NO_23_MASK 0x7F00 /* DCS_SERIES_NO_23 - [14:8] */ 1319*4882a593Smuzhiyun #define WM8995_DCS_SERIES_NO_23_SHIFT 8 /* DCS_SERIES_NO_23 - [14:8] */ 1320*4882a593Smuzhiyun #define WM8995_DCS_SERIES_NO_23_WIDTH 7 /* DCS_SERIES_NO_23 - [14:8] */ 1321*4882a593Smuzhiyun #define WM8995_DCS_SERIES_NO_01_MASK 0x007F /* DCS_SERIES_NO_01 - [6:0] */ 1322*4882a593Smuzhiyun #define WM8995_DCS_SERIES_NO_01_SHIFT 0 /* DCS_SERIES_NO_01 - [6:0] */ 1323*4882a593Smuzhiyun #define WM8995_DCS_SERIES_NO_01_WIDTH 7 /* DCS_SERIES_NO_01 - [6:0] */ 1324*4882a593Smuzhiyun 1325*4882a593Smuzhiyun /* 1326*4882a593Smuzhiyun * R85 (0x55) - DC Servo (6) 1327*4882a593Smuzhiyun */ 1328*4882a593Smuzhiyun #define WM8995_DCS_DAC_WR_VAL_3_MASK 0xFF00 /* DCS_DAC_WR_VAL_3 - [15:8] */ 1329*4882a593Smuzhiyun #define WM8995_DCS_DAC_WR_VAL_3_SHIFT 8 /* DCS_DAC_WR_VAL_3 - [15:8] */ 1330*4882a593Smuzhiyun #define WM8995_DCS_DAC_WR_VAL_3_WIDTH 8 /* DCS_DAC_WR_VAL_3 - [15:8] */ 1331*4882a593Smuzhiyun #define WM8995_DCS_DAC_WR_VAL_2_MASK 0x00FF /* DCS_DAC_WR_VAL_2 - [7:0] */ 1332*4882a593Smuzhiyun #define WM8995_DCS_DAC_WR_VAL_2_SHIFT 0 /* DCS_DAC_WR_VAL_2 - [7:0] */ 1333*4882a593Smuzhiyun #define WM8995_DCS_DAC_WR_VAL_2_WIDTH 8 /* DCS_DAC_WR_VAL_2 - [7:0] */ 1334*4882a593Smuzhiyun 1335*4882a593Smuzhiyun /* 1336*4882a593Smuzhiyun * R86 (0x56) - DC Servo (7) 1337*4882a593Smuzhiyun */ 1338*4882a593Smuzhiyun #define WM8995_DCS_DAC_WR_VAL_1_MASK 0xFF00 /* DCS_DAC_WR_VAL_1 - [15:8] */ 1339*4882a593Smuzhiyun #define WM8995_DCS_DAC_WR_VAL_1_SHIFT 8 /* DCS_DAC_WR_VAL_1 - [15:8] */ 1340*4882a593Smuzhiyun #define WM8995_DCS_DAC_WR_VAL_1_WIDTH 8 /* DCS_DAC_WR_VAL_1 - [15:8] */ 1341*4882a593Smuzhiyun #define WM8995_DCS_DAC_WR_VAL_0_MASK 0x00FF /* DCS_DAC_WR_VAL_0 - [7:0] */ 1342*4882a593Smuzhiyun #define WM8995_DCS_DAC_WR_VAL_0_SHIFT 0 /* DCS_DAC_WR_VAL_0 - [7:0] */ 1343*4882a593Smuzhiyun #define WM8995_DCS_DAC_WR_VAL_0_WIDTH 8 /* DCS_DAC_WR_VAL_0 - [7:0] */ 1344*4882a593Smuzhiyun 1345*4882a593Smuzhiyun /* 1346*4882a593Smuzhiyun * R87 (0x57) - DC Servo Readback 0 1347*4882a593Smuzhiyun */ 1348*4882a593Smuzhiyun #define WM8995_DCS_CAL_COMPLETE_MASK 0x0F00 /* DCS_CAL_COMPLETE - [11:8] */ 1349*4882a593Smuzhiyun #define WM8995_DCS_CAL_COMPLETE_SHIFT 8 /* DCS_CAL_COMPLETE - [11:8] */ 1350*4882a593Smuzhiyun #define WM8995_DCS_CAL_COMPLETE_WIDTH 4 /* DCS_CAL_COMPLETE - [11:8] */ 1351*4882a593Smuzhiyun #define WM8995_DCS_DAC_WR_COMPLETE_MASK 0x00F0 /* DCS_DAC_WR_COMPLETE - [7:4] */ 1352*4882a593Smuzhiyun #define WM8995_DCS_DAC_WR_COMPLETE_SHIFT 4 /* DCS_DAC_WR_COMPLETE - [7:4] */ 1353*4882a593Smuzhiyun #define WM8995_DCS_DAC_WR_COMPLETE_WIDTH 4 /* DCS_DAC_WR_COMPLETE - [7:4] */ 1354*4882a593Smuzhiyun #define WM8995_DCS_STARTUP_COMPLETE_MASK 0x000F /* DCS_STARTUP_COMPLETE - [3:0] */ 1355*4882a593Smuzhiyun #define WM8995_DCS_STARTUP_COMPLETE_SHIFT 0 /* DCS_STARTUP_COMPLETE - [3:0] */ 1356*4882a593Smuzhiyun #define WM8995_DCS_STARTUP_COMPLETE_WIDTH 4 /* DCS_STARTUP_COMPLETE - [3:0] */ 1357*4882a593Smuzhiyun 1358*4882a593Smuzhiyun /* 1359*4882a593Smuzhiyun * R96 (0x60) - Analogue HP (1) 1360*4882a593Smuzhiyun */ 1361*4882a593Smuzhiyun #define WM8995_HPOUT1L_RMV_SHORT 0x0080 /* HPOUT1L_RMV_SHORT */ 1362*4882a593Smuzhiyun #define WM8995_HPOUT1L_RMV_SHORT_MASK 0x0080 /* HPOUT1L_RMV_SHORT */ 1363*4882a593Smuzhiyun #define WM8995_HPOUT1L_RMV_SHORT_SHIFT 7 /* HPOUT1L_RMV_SHORT */ 1364*4882a593Smuzhiyun #define WM8995_HPOUT1L_RMV_SHORT_WIDTH 1 /* HPOUT1L_RMV_SHORT */ 1365*4882a593Smuzhiyun #define WM8995_HPOUT1L_OUTP 0x0040 /* HPOUT1L_OUTP */ 1366*4882a593Smuzhiyun #define WM8995_HPOUT1L_OUTP_MASK 0x0040 /* HPOUT1L_OUTP */ 1367*4882a593Smuzhiyun #define WM8995_HPOUT1L_OUTP_SHIFT 6 /* HPOUT1L_OUTP */ 1368*4882a593Smuzhiyun #define WM8995_HPOUT1L_OUTP_WIDTH 1 /* HPOUT1L_OUTP */ 1369*4882a593Smuzhiyun #define WM8995_HPOUT1L_DLY 0x0020 /* HPOUT1L_DLY */ 1370*4882a593Smuzhiyun #define WM8995_HPOUT1L_DLY_MASK 0x0020 /* HPOUT1L_DLY */ 1371*4882a593Smuzhiyun #define WM8995_HPOUT1L_DLY_SHIFT 5 /* HPOUT1L_DLY */ 1372*4882a593Smuzhiyun #define WM8995_HPOUT1L_DLY_WIDTH 1 /* HPOUT1L_DLY */ 1373*4882a593Smuzhiyun #define WM8995_HPOUT1R_RMV_SHORT 0x0008 /* HPOUT1R_RMV_SHORT */ 1374*4882a593Smuzhiyun #define WM8995_HPOUT1R_RMV_SHORT_MASK 0x0008 /* HPOUT1R_RMV_SHORT */ 1375*4882a593Smuzhiyun #define WM8995_HPOUT1R_RMV_SHORT_SHIFT 3 /* HPOUT1R_RMV_SHORT */ 1376*4882a593Smuzhiyun #define WM8995_HPOUT1R_RMV_SHORT_WIDTH 1 /* HPOUT1R_RMV_SHORT */ 1377*4882a593Smuzhiyun #define WM8995_HPOUT1R_OUTP 0x0004 /* HPOUT1R_OUTP */ 1378*4882a593Smuzhiyun #define WM8995_HPOUT1R_OUTP_MASK 0x0004 /* HPOUT1R_OUTP */ 1379*4882a593Smuzhiyun #define WM8995_HPOUT1R_OUTP_SHIFT 2 /* HPOUT1R_OUTP */ 1380*4882a593Smuzhiyun #define WM8995_HPOUT1R_OUTP_WIDTH 1 /* HPOUT1R_OUTP */ 1381*4882a593Smuzhiyun #define WM8995_HPOUT1R_DLY 0x0002 /* HPOUT1R_DLY */ 1382*4882a593Smuzhiyun #define WM8995_HPOUT1R_DLY_MASK 0x0002 /* HPOUT1R_DLY */ 1383*4882a593Smuzhiyun #define WM8995_HPOUT1R_DLY_SHIFT 1 /* HPOUT1R_DLY */ 1384*4882a593Smuzhiyun #define WM8995_HPOUT1R_DLY_WIDTH 1 /* HPOUT1R_DLY */ 1385*4882a593Smuzhiyun 1386*4882a593Smuzhiyun /* 1387*4882a593Smuzhiyun * R97 (0x61) - Analogue HP (2) 1388*4882a593Smuzhiyun */ 1389*4882a593Smuzhiyun #define WM8995_HPOUT2L_RMV_SHORT 0x0080 /* HPOUT2L_RMV_SHORT */ 1390*4882a593Smuzhiyun #define WM8995_HPOUT2L_RMV_SHORT_MASK 0x0080 /* HPOUT2L_RMV_SHORT */ 1391*4882a593Smuzhiyun #define WM8995_HPOUT2L_RMV_SHORT_SHIFT 7 /* HPOUT2L_RMV_SHORT */ 1392*4882a593Smuzhiyun #define WM8995_HPOUT2L_RMV_SHORT_WIDTH 1 /* HPOUT2L_RMV_SHORT */ 1393*4882a593Smuzhiyun #define WM8995_HPOUT2L_OUTP 0x0040 /* HPOUT2L_OUTP */ 1394*4882a593Smuzhiyun #define WM8995_HPOUT2L_OUTP_MASK 0x0040 /* HPOUT2L_OUTP */ 1395*4882a593Smuzhiyun #define WM8995_HPOUT2L_OUTP_SHIFT 6 /* HPOUT2L_OUTP */ 1396*4882a593Smuzhiyun #define WM8995_HPOUT2L_OUTP_WIDTH 1 /* HPOUT2L_OUTP */ 1397*4882a593Smuzhiyun #define WM8995_HPOUT2L_DLY 0x0020 /* HPOUT2L_DLY */ 1398*4882a593Smuzhiyun #define WM8995_HPOUT2L_DLY_MASK 0x0020 /* HPOUT2L_DLY */ 1399*4882a593Smuzhiyun #define WM8995_HPOUT2L_DLY_SHIFT 5 /* HPOUT2L_DLY */ 1400*4882a593Smuzhiyun #define WM8995_HPOUT2L_DLY_WIDTH 1 /* HPOUT2L_DLY */ 1401*4882a593Smuzhiyun #define WM8995_HPOUT2R_RMV_SHORT 0x0008 /* HPOUT2R_RMV_SHORT */ 1402*4882a593Smuzhiyun #define WM8995_HPOUT2R_RMV_SHORT_MASK 0x0008 /* HPOUT2R_RMV_SHORT */ 1403*4882a593Smuzhiyun #define WM8995_HPOUT2R_RMV_SHORT_SHIFT 3 /* HPOUT2R_RMV_SHORT */ 1404*4882a593Smuzhiyun #define WM8995_HPOUT2R_RMV_SHORT_WIDTH 1 /* HPOUT2R_RMV_SHORT */ 1405*4882a593Smuzhiyun #define WM8995_HPOUT2R_OUTP 0x0004 /* HPOUT2R_OUTP */ 1406*4882a593Smuzhiyun #define WM8995_HPOUT2R_OUTP_MASK 0x0004 /* HPOUT2R_OUTP */ 1407*4882a593Smuzhiyun #define WM8995_HPOUT2R_OUTP_SHIFT 2 /* HPOUT2R_OUTP */ 1408*4882a593Smuzhiyun #define WM8995_HPOUT2R_OUTP_WIDTH 1 /* HPOUT2R_OUTP */ 1409*4882a593Smuzhiyun #define WM8995_HPOUT2R_DLY 0x0002 /* HPOUT2R_DLY */ 1410*4882a593Smuzhiyun #define WM8995_HPOUT2R_DLY_MASK 0x0002 /* HPOUT2R_DLY */ 1411*4882a593Smuzhiyun #define WM8995_HPOUT2R_DLY_SHIFT 1 /* HPOUT2R_DLY */ 1412*4882a593Smuzhiyun #define WM8995_HPOUT2R_DLY_WIDTH 1 /* HPOUT2R_DLY */ 1413*4882a593Smuzhiyun 1414*4882a593Smuzhiyun /* 1415*4882a593Smuzhiyun * R256 (0x100) - Chip Revision 1416*4882a593Smuzhiyun */ 1417*4882a593Smuzhiyun #define WM8995_CHIP_REV_MASK 0x000F /* CHIP_REV - [3:0] */ 1418*4882a593Smuzhiyun #define WM8995_CHIP_REV_SHIFT 0 /* CHIP_REV - [3:0] */ 1419*4882a593Smuzhiyun #define WM8995_CHIP_REV_WIDTH 4 /* CHIP_REV - [3:0] */ 1420*4882a593Smuzhiyun 1421*4882a593Smuzhiyun /* 1422*4882a593Smuzhiyun * R257 (0x101) - Control Interface (1) 1423*4882a593Smuzhiyun */ 1424*4882a593Smuzhiyun #define WM8995_REG_SYNC 0x8000 /* REG_SYNC */ 1425*4882a593Smuzhiyun #define WM8995_REG_SYNC_MASK 0x8000 /* REG_SYNC */ 1426*4882a593Smuzhiyun #define WM8995_REG_SYNC_SHIFT 15 /* REG_SYNC */ 1427*4882a593Smuzhiyun #define WM8995_REG_SYNC_WIDTH 1 /* REG_SYNC */ 1428*4882a593Smuzhiyun #define WM8995_SPI_CONTRD 0x0040 /* SPI_CONTRD */ 1429*4882a593Smuzhiyun #define WM8995_SPI_CONTRD_MASK 0x0040 /* SPI_CONTRD */ 1430*4882a593Smuzhiyun #define WM8995_SPI_CONTRD_SHIFT 6 /* SPI_CONTRD */ 1431*4882a593Smuzhiyun #define WM8995_SPI_CONTRD_WIDTH 1 /* SPI_CONTRD */ 1432*4882a593Smuzhiyun #define WM8995_SPI_4WIRE 0x0020 /* SPI_4WIRE */ 1433*4882a593Smuzhiyun #define WM8995_SPI_4WIRE_MASK 0x0020 /* SPI_4WIRE */ 1434*4882a593Smuzhiyun #define WM8995_SPI_4WIRE_SHIFT 5 /* SPI_4WIRE */ 1435*4882a593Smuzhiyun #define WM8995_SPI_4WIRE_WIDTH 1 /* SPI_4WIRE */ 1436*4882a593Smuzhiyun #define WM8995_SPI_CFG 0x0010 /* SPI_CFG */ 1437*4882a593Smuzhiyun #define WM8995_SPI_CFG_MASK 0x0010 /* SPI_CFG */ 1438*4882a593Smuzhiyun #define WM8995_SPI_CFG_SHIFT 4 /* SPI_CFG */ 1439*4882a593Smuzhiyun #define WM8995_SPI_CFG_WIDTH 1 /* SPI_CFG */ 1440*4882a593Smuzhiyun #define WM8995_AUTO_INC 0x0004 /* AUTO_INC */ 1441*4882a593Smuzhiyun #define WM8995_AUTO_INC_MASK 0x0004 /* AUTO_INC */ 1442*4882a593Smuzhiyun #define WM8995_AUTO_INC_SHIFT 2 /* AUTO_INC */ 1443*4882a593Smuzhiyun #define WM8995_AUTO_INC_WIDTH 1 /* AUTO_INC */ 1444*4882a593Smuzhiyun 1445*4882a593Smuzhiyun /* 1446*4882a593Smuzhiyun * R258 (0x102) - Control Interface (2) 1447*4882a593Smuzhiyun */ 1448*4882a593Smuzhiyun #define WM8995_CTRL_IF_SRC 0x0001 /* CTRL_IF_SRC */ 1449*4882a593Smuzhiyun #define WM8995_CTRL_IF_SRC_MASK 0x0001 /* CTRL_IF_SRC */ 1450*4882a593Smuzhiyun #define WM8995_CTRL_IF_SRC_SHIFT 0 /* CTRL_IF_SRC */ 1451*4882a593Smuzhiyun #define WM8995_CTRL_IF_SRC_WIDTH 1 /* CTRL_IF_SRC */ 1452*4882a593Smuzhiyun 1453*4882a593Smuzhiyun /* 1454*4882a593Smuzhiyun * R272 (0x110) - Write Sequencer Ctrl (1) 1455*4882a593Smuzhiyun */ 1456*4882a593Smuzhiyun #define WM8995_WSEQ_ENA 0x8000 /* WSEQ_ENA */ 1457*4882a593Smuzhiyun #define WM8995_WSEQ_ENA_MASK 0x8000 /* WSEQ_ENA */ 1458*4882a593Smuzhiyun #define WM8995_WSEQ_ENA_SHIFT 15 /* WSEQ_ENA */ 1459*4882a593Smuzhiyun #define WM8995_WSEQ_ENA_WIDTH 1 /* WSEQ_ENA */ 1460*4882a593Smuzhiyun #define WM8995_WSEQ_ABORT 0x0200 /* WSEQ_ABORT */ 1461*4882a593Smuzhiyun #define WM8995_WSEQ_ABORT_MASK 0x0200 /* WSEQ_ABORT */ 1462*4882a593Smuzhiyun #define WM8995_WSEQ_ABORT_SHIFT 9 /* WSEQ_ABORT */ 1463*4882a593Smuzhiyun #define WM8995_WSEQ_ABORT_WIDTH 1 /* WSEQ_ABORT */ 1464*4882a593Smuzhiyun #define WM8995_WSEQ_START 0x0100 /* WSEQ_START */ 1465*4882a593Smuzhiyun #define WM8995_WSEQ_START_MASK 0x0100 /* WSEQ_START */ 1466*4882a593Smuzhiyun #define WM8995_WSEQ_START_SHIFT 8 /* WSEQ_START */ 1467*4882a593Smuzhiyun #define WM8995_WSEQ_START_WIDTH 1 /* WSEQ_START */ 1468*4882a593Smuzhiyun #define WM8995_WSEQ_START_INDEX_MASK 0x007F /* WSEQ_START_INDEX - [6:0] */ 1469*4882a593Smuzhiyun #define WM8995_WSEQ_START_INDEX_SHIFT 0 /* WSEQ_START_INDEX - [6:0] */ 1470*4882a593Smuzhiyun #define WM8995_WSEQ_START_INDEX_WIDTH 7 /* WSEQ_START_INDEX - [6:0] */ 1471*4882a593Smuzhiyun 1472*4882a593Smuzhiyun /* 1473*4882a593Smuzhiyun * R273 (0x111) - Write Sequencer Ctrl (2) 1474*4882a593Smuzhiyun */ 1475*4882a593Smuzhiyun #define WM8995_WSEQ_BUSY 0x0100 /* WSEQ_BUSY */ 1476*4882a593Smuzhiyun #define WM8995_WSEQ_BUSY_MASK 0x0100 /* WSEQ_BUSY */ 1477*4882a593Smuzhiyun #define WM8995_WSEQ_BUSY_SHIFT 8 /* WSEQ_BUSY */ 1478*4882a593Smuzhiyun #define WM8995_WSEQ_BUSY_WIDTH 1 /* WSEQ_BUSY */ 1479*4882a593Smuzhiyun #define WM8995_WSEQ_CURRENT_INDEX_MASK 0x007F /* WSEQ_CURRENT_INDEX - [6:0] */ 1480*4882a593Smuzhiyun #define WM8995_WSEQ_CURRENT_INDEX_SHIFT 0 /* WSEQ_CURRENT_INDEX - [6:0] */ 1481*4882a593Smuzhiyun #define WM8995_WSEQ_CURRENT_INDEX_WIDTH 7 /* WSEQ_CURRENT_INDEX - [6:0] */ 1482*4882a593Smuzhiyun 1483*4882a593Smuzhiyun /* 1484*4882a593Smuzhiyun * R512 (0x200) - AIF1 Clocking (1) 1485*4882a593Smuzhiyun */ 1486*4882a593Smuzhiyun #define WM8995_AIF1CLK_SRC_MASK 0x0018 /* AIF1CLK_SRC - [4:3] */ 1487*4882a593Smuzhiyun #define WM8995_AIF1CLK_SRC_SHIFT 3 /* AIF1CLK_SRC - [4:3] */ 1488*4882a593Smuzhiyun #define WM8995_AIF1CLK_SRC_WIDTH 2 /* AIF1CLK_SRC - [4:3] */ 1489*4882a593Smuzhiyun #define WM8995_AIF1CLK_INV 0x0004 /* AIF1CLK_INV */ 1490*4882a593Smuzhiyun #define WM8995_AIF1CLK_INV_MASK 0x0004 /* AIF1CLK_INV */ 1491*4882a593Smuzhiyun #define WM8995_AIF1CLK_INV_SHIFT 2 /* AIF1CLK_INV */ 1492*4882a593Smuzhiyun #define WM8995_AIF1CLK_INV_WIDTH 1 /* AIF1CLK_INV */ 1493*4882a593Smuzhiyun #define WM8995_AIF1CLK_DIV 0x0002 /* AIF1CLK_DIV */ 1494*4882a593Smuzhiyun #define WM8995_AIF1CLK_DIV_MASK 0x0002 /* AIF1CLK_DIV */ 1495*4882a593Smuzhiyun #define WM8995_AIF1CLK_DIV_SHIFT 1 /* AIF1CLK_DIV */ 1496*4882a593Smuzhiyun #define WM8995_AIF1CLK_DIV_WIDTH 1 /* AIF1CLK_DIV */ 1497*4882a593Smuzhiyun #define WM8995_AIF1CLK_ENA 0x0001 /* AIF1CLK_ENA */ 1498*4882a593Smuzhiyun #define WM8995_AIF1CLK_ENA_MASK 0x0001 /* AIF1CLK_ENA */ 1499*4882a593Smuzhiyun #define WM8995_AIF1CLK_ENA_SHIFT 0 /* AIF1CLK_ENA */ 1500*4882a593Smuzhiyun #define WM8995_AIF1CLK_ENA_WIDTH 1 /* AIF1CLK_ENA */ 1501*4882a593Smuzhiyun 1502*4882a593Smuzhiyun /* 1503*4882a593Smuzhiyun * R513 (0x201) - AIF1 Clocking (2) 1504*4882a593Smuzhiyun */ 1505*4882a593Smuzhiyun #define WM8995_AIF1DAC_DIV_MASK 0x0038 /* AIF1DAC_DIV - [5:3] */ 1506*4882a593Smuzhiyun #define WM8995_AIF1DAC_DIV_SHIFT 3 /* AIF1DAC_DIV - [5:3] */ 1507*4882a593Smuzhiyun #define WM8995_AIF1DAC_DIV_WIDTH 3 /* AIF1DAC_DIV - [5:3] */ 1508*4882a593Smuzhiyun #define WM8995_AIF1ADC_DIV_MASK 0x0007 /* AIF1ADC_DIV - [2:0] */ 1509*4882a593Smuzhiyun #define WM8995_AIF1ADC_DIV_SHIFT 0 /* AIF1ADC_DIV - [2:0] */ 1510*4882a593Smuzhiyun #define WM8995_AIF1ADC_DIV_WIDTH 3 /* AIF1ADC_DIV - [2:0] */ 1511*4882a593Smuzhiyun 1512*4882a593Smuzhiyun /* 1513*4882a593Smuzhiyun * R516 (0x204) - AIF2 Clocking (1) 1514*4882a593Smuzhiyun */ 1515*4882a593Smuzhiyun #define WM8995_AIF2CLK_SRC_MASK 0x0018 /* AIF2CLK_SRC - [4:3] */ 1516*4882a593Smuzhiyun #define WM8995_AIF2CLK_SRC_SHIFT 3 /* AIF2CLK_SRC - [4:3] */ 1517*4882a593Smuzhiyun #define WM8995_AIF2CLK_SRC_WIDTH 2 /* AIF2CLK_SRC - [4:3] */ 1518*4882a593Smuzhiyun #define WM8995_AIF2CLK_INV 0x0004 /* AIF2CLK_INV */ 1519*4882a593Smuzhiyun #define WM8995_AIF2CLK_INV_MASK 0x0004 /* AIF2CLK_INV */ 1520*4882a593Smuzhiyun #define WM8995_AIF2CLK_INV_SHIFT 2 /* AIF2CLK_INV */ 1521*4882a593Smuzhiyun #define WM8995_AIF2CLK_INV_WIDTH 1 /* AIF2CLK_INV */ 1522*4882a593Smuzhiyun #define WM8995_AIF2CLK_DIV 0x0002 /* AIF2CLK_DIV */ 1523*4882a593Smuzhiyun #define WM8995_AIF2CLK_DIV_MASK 0x0002 /* AIF2CLK_DIV */ 1524*4882a593Smuzhiyun #define WM8995_AIF2CLK_DIV_SHIFT 1 /* AIF2CLK_DIV */ 1525*4882a593Smuzhiyun #define WM8995_AIF2CLK_DIV_WIDTH 1 /* AIF2CLK_DIV */ 1526*4882a593Smuzhiyun #define WM8995_AIF2CLK_ENA 0x0001 /* AIF2CLK_ENA */ 1527*4882a593Smuzhiyun #define WM8995_AIF2CLK_ENA_MASK 0x0001 /* AIF2CLK_ENA */ 1528*4882a593Smuzhiyun #define WM8995_AIF2CLK_ENA_SHIFT 0 /* AIF2CLK_ENA */ 1529*4882a593Smuzhiyun #define WM8995_AIF2CLK_ENA_WIDTH 1 /* AIF2CLK_ENA */ 1530*4882a593Smuzhiyun 1531*4882a593Smuzhiyun /* 1532*4882a593Smuzhiyun * R517 (0x205) - AIF2 Clocking (2) 1533*4882a593Smuzhiyun */ 1534*4882a593Smuzhiyun #define WM8995_AIF2DAC_DIV_MASK 0x0038 /* AIF2DAC_DIV - [5:3] */ 1535*4882a593Smuzhiyun #define WM8995_AIF2DAC_DIV_SHIFT 3 /* AIF2DAC_DIV - [5:3] */ 1536*4882a593Smuzhiyun #define WM8995_AIF2DAC_DIV_WIDTH 3 /* AIF2DAC_DIV - [5:3] */ 1537*4882a593Smuzhiyun #define WM8995_AIF2ADC_DIV_MASK 0x0007 /* AIF2ADC_DIV - [2:0] */ 1538*4882a593Smuzhiyun #define WM8995_AIF2ADC_DIV_SHIFT 0 /* AIF2ADC_DIV - [2:0] */ 1539*4882a593Smuzhiyun #define WM8995_AIF2ADC_DIV_WIDTH 3 /* AIF2ADC_DIV - [2:0] */ 1540*4882a593Smuzhiyun 1541*4882a593Smuzhiyun /* 1542*4882a593Smuzhiyun * R520 (0x208) - Clocking (1) 1543*4882a593Smuzhiyun */ 1544*4882a593Smuzhiyun #define WM8995_LFCLK_ENA 0x0020 /* LFCLK_ENA */ 1545*4882a593Smuzhiyun #define WM8995_LFCLK_ENA_MASK 0x0020 /* LFCLK_ENA */ 1546*4882a593Smuzhiyun #define WM8995_LFCLK_ENA_SHIFT 5 /* LFCLK_ENA */ 1547*4882a593Smuzhiyun #define WM8995_LFCLK_ENA_WIDTH 1 /* LFCLK_ENA */ 1548*4882a593Smuzhiyun #define WM8995_TOCLK_ENA 0x0010 /* TOCLK_ENA */ 1549*4882a593Smuzhiyun #define WM8995_TOCLK_ENA_MASK 0x0010 /* TOCLK_ENA */ 1550*4882a593Smuzhiyun #define WM8995_TOCLK_ENA_SHIFT 4 /* TOCLK_ENA */ 1551*4882a593Smuzhiyun #define WM8995_TOCLK_ENA_WIDTH 1 /* TOCLK_ENA */ 1552*4882a593Smuzhiyun #define WM8995_AIF1DSPCLK_ENA 0x0008 /* AIF1DSPCLK_ENA */ 1553*4882a593Smuzhiyun #define WM8995_AIF1DSPCLK_ENA_MASK 0x0008 /* AIF1DSPCLK_ENA */ 1554*4882a593Smuzhiyun #define WM8995_AIF1DSPCLK_ENA_SHIFT 3 /* AIF1DSPCLK_ENA */ 1555*4882a593Smuzhiyun #define WM8995_AIF1DSPCLK_ENA_WIDTH 1 /* AIF1DSPCLK_ENA */ 1556*4882a593Smuzhiyun #define WM8995_AIF2DSPCLK_ENA 0x0004 /* AIF2DSPCLK_ENA */ 1557*4882a593Smuzhiyun #define WM8995_AIF2DSPCLK_ENA_MASK 0x0004 /* AIF2DSPCLK_ENA */ 1558*4882a593Smuzhiyun #define WM8995_AIF2DSPCLK_ENA_SHIFT 2 /* AIF2DSPCLK_ENA */ 1559*4882a593Smuzhiyun #define WM8995_AIF2DSPCLK_ENA_WIDTH 1 /* AIF2DSPCLK_ENA */ 1560*4882a593Smuzhiyun #define WM8995_SYSDSPCLK_ENA 0x0002 /* SYSDSPCLK_ENA */ 1561*4882a593Smuzhiyun #define WM8995_SYSDSPCLK_ENA_MASK 0x0002 /* SYSDSPCLK_ENA */ 1562*4882a593Smuzhiyun #define WM8995_SYSDSPCLK_ENA_SHIFT 1 /* SYSDSPCLK_ENA */ 1563*4882a593Smuzhiyun #define WM8995_SYSDSPCLK_ENA_WIDTH 1 /* SYSDSPCLK_ENA */ 1564*4882a593Smuzhiyun #define WM8995_SYSCLK_SRC 0x0001 /* SYSCLK_SRC */ 1565*4882a593Smuzhiyun #define WM8995_SYSCLK_SRC_MASK 0x0001 /* SYSCLK_SRC */ 1566*4882a593Smuzhiyun #define WM8995_SYSCLK_SRC_SHIFT 0 /* SYSCLK_SRC */ 1567*4882a593Smuzhiyun #define WM8995_SYSCLK_SRC_WIDTH 1 /* SYSCLK_SRC */ 1568*4882a593Smuzhiyun 1569*4882a593Smuzhiyun /* 1570*4882a593Smuzhiyun * R521 (0x209) - Clocking (2) 1571*4882a593Smuzhiyun */ 1572*4882a593Smuzhiyun #define WM8995_TOCLK_DIV_MASK 0x0700 /* TOCLK_DIV - [10:8] */ 1573*4882a593Smuzhiyun #define WM8995_TOCLK_DIV_SHIFT 8 /* TOCLK_DIV - [10:8] */ 1574*4882a593Smuzhiyun #define WM8995_TOCLK_DIV_WIDTH 3 /* TOCLK_DIV - [10:8] */ 1575*4882a593Smuzhiyun #define WM8995_DBCLK_DIV_MASK 0x00F0 /* DBCLK_DIV - [7:4] */ 1576*4882a593Smuzhiyun #define WM8995_DBCLK_DIV_SHIFT 4 /* DBCLK_DIV - [7:4] */ 1577*4882a593Smuzhiyun #define WM8995_DBCLK_DIV_WIDTH 4 /* DBCLK_DIV - [7:4] */ 1578*4882a593Smuzhiyun #define WM8995_OPCLK_DIV_MASK 0x0007 /* OPCLK_DIV - [2:0] */ 1579*4882a593Smuzhiyun #define WM8995_OPCLK_DIV_SHIFT 0 /* OPCLK_DIV - [2:0] */ 1580*4882a593Smuzhiyun #define WM8995_OPCLK_DIV_WIDTH 3 /* OPCLK_DIV - [2:0] */ 1581*4882a593Smuzhiyun 1582*4882a593Smuzhiyun /* 1583*4882a593Smuzhiyun * R528 (0x210) - AIF1 Rate 1584*4882a593Smuzhiyun */ 1585*4882a593Smuzhiyun #define WM8995_AIF1_SR_MASK 0x00F0 /* AIF1_SR - [7:4] */ 1586*4882a593Smuzhiyun #define WM8995_AIF1_SR_SHIFT 4 /* AIF1_SR - [7:4] */ 1587*4882a593Smuzhiyun #define WM8995_AIF1_SR_WIDTH 4 /* AIF1_SR - [7:4] */ 1588*4882a593Smuzhiyun #define WM8995_AIF1CLK_RATE_MASK 0x000F /* AIF1CLK_RATE - [3:0] */ 1589*4882a593Smuzhiyun #define WM8995_AIF1CLK_RATE_SHIFT 0 /* AIF1CLK_RATE - [3:0] */ 1590*4882a593Smuzhiyun #define WM8995_AIF1CLK_RATE_WIDTH 4 /* AIF1CLK_RATE - [3:0] */ 1591*4882a593Smuzhiyun 1592*4882a593Smuzhiyun /* 1593*4882a593Smuzhiyun * R529 (0x211) - AIF2 Rate 1594*4882a593Smuzhiyun */ 1595*4882a593Smuzhiyun #define WM8995_AIF2_SR_MASK 0x00F0 /* AIF2_SR - [7:4] */ 1596*4882a593Smuzhiyun #define WM8995_AIF2_SR_SHIFT 4 /* AIF2_SR - [7:4] */ 1597*4882a593Smuzhiyun #define WM8995_AIF2_SR_WIDTH 4 /* AIF2_SR - [7:4] */ 1598*4882a593Smuzhiyun #define WM8995_AIF2CLK_RATE_MASK 0x000F /* AIF2CLK_RATE - [3:0] */ 1599*4882a593Smuzhiyun #define WM8995_AIF2CLK_RATE_SHIFT 0 /* AIF2CLK_RATE - [3:0] */ 1600*4882a593Smuzhiyun #define WM8995_AIF2CLK_RATE_WIDTH 4 /* AIF2CLK_RATE - [3:0] */ 1601*4882a593Smuzhiyun 1602*4882a593Smuzhiyun /* 1603*4882a593Smuzhiyun * R530 (0x212) - Rate Status 1604*4882a593Smuzhiyun */ 1605*4882a593Smuzhiyun #define WM8995_SR_ERROR_MASK 0x000F /* SR_ERROR - [3:0] */ 1606*4882a593Smuzhiyun #define WM8995_SR_ERROR_SHIFT 0 /* SR_ERROR - [3:0] */ 1607*4882a593Smuzhiyun #define WM8995_SR_ERROR_WIDTH 4 /* SR_ERROR - [3:0] */ 1608*4882a593Smuzhiyun 1609*4882a593Smuzhiyun /* 1610*4882a593Smuzhiyun * R544 (0x220) - FLL1 Control (1) 1611*4882a593Smuzhiyun */ 1612*4882a593Smuzhiyun #define WM8995_FLL1_OSC_ENA 0x0002 /* FLL1_OSC_ENA */ 1613*4882a593Smuzhiyun #define WM8995_FLL1_OSC_ENA_MASK 0x0002 /* FLL1_OSC_ENA */ 1614*4882a593Smuzhiyun #define WM8995_FLL1_OSC_ENA_SHIFT 1 /* FLL1_OSC_ENA */ 1615*4882a593Smuzhiyun #define WM8995_FLL1_OSC_ENA_WIDTH 1 /* FLL1_OSC_ENA */ 1616*4882a593Smuzhiyun #define WM8995_FLL1_ENA 0x0001 /* FLL1_ENA */ 1617*4882a593Smuzhiyun #define WM8995_FLL1_ENA_MASK 0x0001 /* FLL1_ENA */ 1618*4882a593Smuzhiyun #define WM8995_FLL1_ENA_SHIFT 0 /* FLL1_ENA */ 1619*4882a593Smuzhiyun #define WM8995_FLL1_ENA_WIDTH 1 /* FLL1_ENA */ 1620*4882a593Smuzhiyun 1621*4882a593Smuzhiyun /* 1622*4882a593Smuzhiyun * R545 (0x221) - FLL1 Control (2) 1623*4882a593Smuzhiyun */ 1624*4882a593Smuzhiyun #define WM8995_FLL1_OUTDIV_MASK 0x3F00 /* FLL1_OUTDIV - [13:8] */ 1625*4882a593Smuzhiyun #define WM8995_FLL1_OUTDIV_SHIFT 8 /* FLL1_OUTDIV - [13:8] */ 1626*4882a593Smuzhiyun #define WM8995_FLL1_OUTDIV_WIDTH 6 /* FLL1_OUTDIV - [13:8] */ 1627*4882a593Smuzhiyun #define WM8995_FLL1_CTRL_RATE_MASK 0x0070 /* FLL1_CTRL_RATE - [6:4] */ 1628*4882a593Smuzhiyun #define WM8995_FLL1_CTRL_RATE_SHIFT 4 /* FLL1_CTRL_RATE - [6:4] */ 1629*4882a593Smuzhiyun #define WM8995_FLL1_CTRL_RATE_WIDTH 3 /* FLL1_CTRL_RATE - [6:4] */ 1630*4882a593Smuzhiyun #define WM8995_FLL1_FRATIO_MASK 0x0007 /* FLL1_FRATIO - [2:0] */ 1631*4882a593Smuzhiyun #define WM8995_FLL1_FRATIO_SHIFT 0 /* FLL1_FRATIO - [2:0] */ 1632*4882a593Smuzhiyun #define WM8995_FLL1_FRATIO_WIDTH 3 /* FLL1_FRATIO - [2:0] */ 1633*4882a593Smuzhiyun 1634*4882a593Smuzhiyun /* 1635*4882a593Smuzhiyun * R546 (0x222) - FLL1 Control (3) 1636*4882a593Smuzhiyun */ 1637*4882a593Smuzhiyun #define WM8995_FLL1_K_MASK 0xFFFF /* FLL1_K - [15:0] */ 1638*4882a593Smuzhiyun #define WM8995_FLL1_K_SHIFT 0 /* FLL1_K - [15:0] */ 1639*4882a593Smuzhiyun #define WM8995_FLL1_K_WIDTH 16 /* FLL1_K - [15:0] */ 1640*4882a593Smuzhiyun 1641*4882a593Smuzhiyun /* 1642*4882a593Smuzhiyun * R547 (0x223) - FLL1 Control (4) 1643*4882a593Smuzhiyun */ 1644*4882a593Smuzhiyun #define WM8995_FLL1_N_MASK 0x7FE0 /* FLL1_N - [14:5] */ 1645*4882a593Smuzhiyun #define WM8995_FLL1_N_SHIFT 5 /* FLL1_N - [14:5] */ 1646*4882a593Smuzhiyun #define WM8995_FLL1_N_WIDTH 10 /* FLL1_N - [14:5] */ 1647*4882a593Smuzhiyun #define WM8995_FLL1_LOOP_GAIN_MASK 0x000F /* FLL1_LOOP_GAIN - [3:0] */ 1648*4882a593Smuzhiyun #define WM8995_FLL1_LOOP_GAIN_SHIFT 0 /* FLL1_LOOP_GAIN - [3:0] */ 1649*4882a593Smuzhiyun #define WM8995_FLL1_LOOP_GAIN_WIDTH 4 /* FLL1_LOOP_GAIN - [3:0] */ 1650*4882a593Smuzhiyun 1651*4882a593Smuzhiyun /* 1652*4882a593Smuzhiyun * R548 (0x224) - FLL1 Control (5) 1653*4882a593Smuzhiyun */ 1654*4882a593Smuzhiyun #define WM8995_FLL1_FRC_NCO_VAL_MASK 0x1F80 /* FLL1_FRC_NCO_VAL - [12:7] */ 1655*4882a593Smuzhiyun #define WM8995_FLL1_FRC_NCO_VAL_SHIFT 7 /* FLL1_FRC_NCO_VAL - [12:7] */ 1656*4882a593Smuzhiyun #define WM8995_FLL1_FRC_NCO_VAL_WIDTH 6 /* FLL1_FRC_NCO_VAL - [12:7] */ 1657*4882a593Smuzhiyun #define WM8995_FLL1_FRC_NCO 0x0040 /* FLL1_FRC_NCO */ 1658*4882a593Smuzhiyun #define WM8995_FLL1_FRC_NCO_MASK 0x0040 /* FLL1_FRC_NCO */ 1659*4882a593Smuzhiyun #define WM8995_FLL1_FRC_NCO_SHIFT 6 /* FLL1_FRC_NCO */ 1660*4882a593Smuzhiyun #define WM8995_FLL1_FRC_NCO_WIDTH 1 /* FLL1_FRC_NCO */ 1661*4882a593Smuzhiyun #define WM8995_FLL1_REFCLK_DIV_MASK 0x0018 /* FLL1_REFCLK_DIV - [4:3] */ 1662*4882a593Smuzhiyun #define WM8995_FLL1_REFCLK_DIV_SHIFT 3 /* FLL1_REFCLK_DIV - [4:3] */ 1663*4882a593Smuzhiyun #define WM8995_FLL1_REFCLK_DIV_WIDTH 2 /* FLL1_REFCLK_DIV - [4:3] */ 1664*4882a593Smuzhiyun #define WM8995_FLL1_REFCLK_SRC_MASK 0x0003 /* FLL1_REFCLK_SRC - [1:0] */ 1665*4882a593Smuzhiyun #define WM8995_FLL1_REFCLK_SRC_SHIFT 0 /* FLL1_REFCLK_SRC - [1:0] */ 1666*4882a593Smuzhiyun #define WM8995_FLL1_REFCLK_SRC_WIDTH 2 /* FLL1_REFCLK_SRC - [1:0] */ 1667*4882a593Smuzhiyun 1668*4882a593Smuzhiyun /* 1669*4882a593Smuzhiyun * R576 (0x240) - FLL2 Control (1) 1670*4882a593Smuzhiyun */ 1671*4882a593Smuzhiyun #define WM8995_FLL2_OSC_ENA 0x0002 /* FLL2_OSC_ENA */ 1672*4882a593Smuzhiyun #define WM8995_FLL2_OSC_ENA_MASK 0x0002 /* FLL2_OSC_ENA */ 1673*4882a593Smuzhiyun #define WM8995_FLL2_OSC_ENA_SHIFT 1 /* FLL2_OSC_ENA */ 1674*4882a593Smuzhiyun #define WM8995_FLL2_OSC_ENA_WIDTH 1 /* FLL2_OSC_ENA */ 1675*4882a593Smuzhiyun #define WM8995_FLL2_ENA 0x0001 /* FLL2_ENA */ 1676*4882a593Smuzhiyun #define WM8995_FLL2_ENA_MASK 0x0001 /* FLL2_ENA */ 1677*4882a593Smuzhiyun #define WM8995_FLL2_ENA_SHIFT 0 /* FLL2_ENA */ 1678*4882a593Smuzhiyun #define WM8995_FLL2_ENA_WIDTH 1 /* FLL2_ENA */ 1679*4882a593Smuzhiyun 1680*4882a593Smuzhiyun /* 1681*4882a593Smuzhiyun * R577 (0x241) - FLL2 Control (2) 1682*4882a593Smuzhiyun */ 1683*4882a593Smuzhiyun #define WM8995_FLL2_OUTDIV_MASK 0x3F00 /* FLL2_OUTDIV - [13:8] */ 1684*4882a593Smuzhiyun #define WM8995_FLL2_OUTDIV_SHIFT 8 /* FLL2_OUTDIV - [13:8] */ 1685*4882a593Smuzhiyun #define WM8995_FLL2_OUTDIV_WIDTH 6 /* FLL2_OUTDIV - [13:8] */ 1686*4882a593Smuzhiyun #define WM8995_FLL2_CTRL_RATE_MASK 0x0070 /* FLL2_CTRL_RATE - [6:4] */ 1687*4882a593Smuzhiyun #define WM8995_FLL2_CTRL_RATE_SHIFT 4 /* FLL2_CTRL_RATE - [6:4] */ 1688*4882a593Smuzhiyun #define WM8995_FLL2_CTRL_RATE_WIDTH 3 /* FLL2_CTRL_RATE - [6:4] */ 1689*4882a593Smuzhiyun #define WM8995_FLL2_FRATIO_MASK 0x0007 /* FLL2_FRATIO - [2:0] */ 1690*4882a593Smuzhiyun #define WM8995_FLL2_FRATIO_SHIFT 0 /* FLL2_FRATIO - [2:0] */ 1691*4882a593Smuzhiyun #define WM8995_FLL2_FRATIO_WIDTH 3 /* FLL2_FRATIO - [2:0] */ 1692*4882a593Smuzhiyun 1693*4882a593Smuzhiyun /* 1694*4882a593Smuzhiyun * R578 (0x242) - FLL2 Control (3) 1695*4882a593Smuzhiyun */ 1696*4882a593Smuzhiyun #define WM8995_FLL2_K_MASK 0xFFFF /* FLL2_K - [15:0] */ 1697*4882a593Smuzhiyun #define WM8995_FLL2_K_SHIFT 0 /* FLL2_K - [15:0] */ 1698*4882a593Smuzhiyun #define WM8995_FLL2_K_WIDTH 16 /* FLL2_K - [15:0] */ 1699*4882a593Smuzhiyun 1700*4882a593Smuzhiyun /* 1701*4882a593Smuzhiyun * R579 (0x243) - FLL2 Control (4) 1702*4882a593Smuzhiyun */ 1703*4882a593Smuzhiyun #define WM8995_FLL2_N_MASK 0x7FE0 /* FLL2_N - [14:5] */ 1704*4882a593Smuzhiyun #define WM8995_FLL2_N_SHIFT 5 /* FLL2_N - [14:5] */ 1705*4882a593Smuzhiyun #define WM8995_FLL2_N_WIDTH 10 /* FLL2_N - [14:5] */ 1706*4882a593Smuzhiyun #define WM8995_FLL2_LOOP_GAIN_MASK 0x000F /* FLL2_LOOP_GAIN - [3:0] */ 1707*4882a593Smuzhiyun #define WM8995_FLL2_LOOP_GAIN_SHIFT 0 /* FLL2_LOOP_GAIN - [3:0] */ 1708*4882a593Smuzhiyun #define WM8995_FLL2_LOOP_GAIN_WIDTH 4 /* FLL2_LOOP_GAIN - [3:0] */ 1709*4882a593Smuzhiyun 1710*4882a593Smuzhiyun /* 1711*4882a593Smuzhiyun * R580 (0x244) - FLL2 Control (5) 1712*4882a593Smuzhiyun */ 1713*4882a593Smuzhiyun #define WM8995_FLL2_FRC_NCO_VAL_MASK 0x1F80 /* FLL2_FRC_NCO_VAL - [12:7] */ 1714*4882a593Smuzhiyun #define WM8995_FLL2_FRC_NCO_VAL_SHIFT 7 /* FLL2_FRC_NCO_VAL - [12:7] */ 1715*4882a593Smuzhiyun #define WM8995_FLL2_FRC_NCO_VAL_WIDTH 6 /* FLL2_FRC_NCO_VAL - [12:7] */ 1716*4882a593Smuzhiyun #define WM8995_FLL2_FRC_NCO 0x0040 /* FLL2_FRC_NCO */ 1717*4882a593Smuzhiyun #define WM8995_FLL2_FRC_NCO_MASK 0x0040 /* FLL2_FRC_NCO */ 1718*4882a593Smuzhiyun #define WM8995_FLL2_FRC_NCO_SHIFT 6 /* FLL2_FRC_NCO */ 1719*4882a593Smuzhiyun #define WM8995_FLL2_FRC_NCO_WIDTH 1 /* FLL2_FRC_NCO */ 1720*4882a593Smuzhiyun #define WM8995_FLL2_REFCLK_DIV_MASK 0x0018 /* FLL2_REFCLK_DIV - [4:3] */ 1721*4882a593Smuzhiyun #define WM8995_FLL2_REFCLK_DIV_SHIFT 3 /* FLL2_REFCLK_DIV - [4:3] */ 1722*4882a593Smuzhiyun #define WM8995_FLL2_REFCLK_DIV_WIDTH 2 /* FLL2_REFCLK_DIV - [4:3] */ 1723*4882a593Smuzhiyun #define WM8995_FLL2_REFCLK_SRC_MASK 0x0003 /* FLL2_REFCLK_SRC - [1:0] */ 1724*4882a593Smuzhiyun #define WM8995_FLL2_REFCLK_SRC_SHIFT 0 /* FLL2_REFCLK_SRC - [1:0] */ 1725*4882a593Smuzhiyun #define WM8995_FLL2_REFCLK_SRC_WIDTH 2 /* FLL2_REFCLK_SRC - [1:0] */ 1726*4882a593Smuzhiyun 1727*4882a593Smuzhiyun /* 1728*4882a593Smuzhiyun * R768 (0x300) - AIF1 Control (1) 1729*4882a593Smuzhiyun */ 1730*4882a593Smuzhiyun #define WM8995_AIF1ADCL_SRC 0x8000 /* AIF1ADCL_SRC */ 1731*4882a593Smuzhiyun #define WM8995_AIF1ADCL_SRC_MASK 0x8000 /* AIF1ADCL_SRC */ 1732*4882a593Smuzhiyun #define WM8995_AIF1ADCL_SRC_SHIFT 15 /* AIF1ADCL_SRC */ 1733*4882a593Smuzhiyun #define WM8995_AIF1ADCL_SRC_WIDTH 1 /* AIF1ADCL_SRC */ 1734*4882a593Smuzhiyun #define WM8995_AIF1ADCR_SRC 0x4000 /* AIF1ADCR_SRC */ 1735*4882a593Smuzhiyun #define WM8995_AIF1ADCR_SRC_MASK 0x4000 /* AIF1ADCR_SRC */ 1736*4882a593Smuzhiyun #define WM8995_AIF1ADCR_SRC_SHIFT 14 /* AIF1ADCR_SRC */ 1737*4882a593Smuzhiyun #define WM8995_AIF1ADCR_SRC_WIDTH 1 /* AIF1ADCR_SRC */ 1738*4882a593Smuzhiyun #define WM8995_AIF1ADC_TDM 0x2000 /* AIF1ADC_TDM */ 1739*4882a593Smuzhiyun #define WM8995_AIF1ADC_TDM_MASK 0x2000 /* AIF1ADC_TDM */ 1740*4882a593Smuzhiyun #define WM8995_AIF1ADC_TDM_SHIFT 13 /* AIF1ADC_TDM */ 1741*4882a593Smuzhiyun #define WM8995_AIF1ADC_TDM_WIDTH 1 /* AIF1ADC_TDM */ 1742*4882a593Smuzhiyun #define WM8995_AIF1_BCLK_INV 0x0100 /* AIF1_BCLK_INV */ 1743*4882a593Smuzhiyun #define WM8995_AIF1_BCLK_INV_MASK 0x0100 /* AIF1_BCLK_INV */ 1744*4882a593Smuzhiyun #define WM8995_AIF1_BCLK_INV_SHIFT 8 /* AIF1_BCLK_INV */ 1745*4882a593Smuzhiyun #define WM8995_AIF1_BCLK_INV_WIDTH 1 /* AIF1_BCLK_INV */ 1746*4882a593Smuzhiyun #define WM8995_AIF1_LRCLK_INV 0x0080 /* AIF1_LRCLK_INV */ 1747*4882a593Smuzhiyun #define WM8995_AIF1_LRCLK_INV_MASK 0x0080 /* AIF1_LRCLK_INV */ 1748*4882a593Smuzhiyun #define WM8995_AIF1_LRCLK_INV_SHIFT 7 /* AIF1_LRCLK_INV */ 1749*4882a593Smuzhiyun #define WM8995_AIF1_LRCLK_INV_WIDTH 1 /* AIF1_LRCLK_INV */ 1750*4882a593Smuzhiyun #define WM8995_AIF1_WL_MASK 0x0060 /* AIF1_WL - [6:5] */ 1751*4882a593Smuzhiyun #define WM8995_AIF1_WL_SHIFT 5 /* AIF1_WL - [6:5] */ 1752*4882a593Smuzhiyun #define WM8995_AIF1_WL_WIDTH 2 /* AIF1_WL - [6:5] */ 1753*4882a593Smuzhiyun #define WM8995_AIF1_FMT_MASK 0x0018 /* AIF1_FMT - [4:3] */ 1754*4882a593Smuzhiyun #define WM8995_AIF1_FMT_SHIFT 3 /* AIF1_FMT - [4:3] */ 1755*4882a593Smuzhiyun #define WM8995_AIF1_FMT_WIDTH 2 /* AIF1_FMT - [4:3] */ 1756*4882a593Smuzhiyun 1757*4882a593Smuzhiyun /* 1758*4882a593Smuzhiyun * R769 (0x301) - AIF1 Control (2) 1759*4882a593Smuzhiyun */ 1760*4882a593Smuzhiyun #define WM8995_AIF1DACL_SRC 0x8000 /* AIF1DACL_SRC */ 1761*4882a593Smuzhiyun #define WM8995_AIF1DACL_SRC_MASK 0x8000 /* AIF1DACL_SRC */ 1762*4882a593Smuzhiyun #define WM8995_AIF1DACL_SRC_SHIFT 15 /* AIF1DACL_SRC */ 1763*4882a593Smuzhiyun #define WM8995_AIF1DACL_SRC_WIDTH 1 /* AIF1DACL_SRC */ 1764*4882a593Smuzhiyun #define WM8995_AIF1DACR_SRC 0x4000 /* AIF1DACR_SRC */ 1765*4882a593Smuzhiyun #define WM8995_AIF1DACR_SRC_MASK 0x4000 /* AIF1DACR_SRC */ 1766*4882a593Smuzhiyun #define WM8995_AIF1DACR_SRC_SHIFT 14 /* AIF1DACR_SRC */ 1767*4882a593Smuzhiyun #define WM8995_AIF1DACR_SRC_WIDTH 1 /* AIF1DACR_SRC */ 1768*4882a593Smuzhiyun #define WM8995_AIF1DAC_BOOST_MASK 0x0C00 /* AIF1DAC_BOOST - [11:10] */ 1769*4882a593Smuzhiyun #define WM8995_AIF1DAC_BOOST_SHIFT 10 /* AIF1DAC_BOOST - [11:10] */ 1770*4882a593Smuzhiyun #define WM8995_AIF1DAC_BOOST_WIDTH 2 /* AIF1DAC_BOOST - [11:10] */ 1771*4882a593Smuzhiyun #define WM8995_AIF1DAC_COMP 0x0010 /* AIF1DAC_COMP */ 1772*4882a593Smuzhiyun #define WM8995_AIF1DAC_COMP_MASK 0x0010 /* AIF1DAC_COMP */ 1773*4882a593Smuzhiyun #define WM8995_AIF1DAC_COMP_SHIFT 4 /* AIF1DAC_COMP */ 1774*4882a593Smuzhiyun #define WM8995_AIF1DAC_COMP_WIDTH 1 /* AIF1DAC_COMP */ 1775*4882a593Smuzhiyun #define WM8995_AIF1DAC_COMPMODE 0x0008 /* AIF1DAC_COMPMODE */ 1776*4882a593Smuzhiyun #define WM8995_AIF1DAC_COMPMODE_MASK 0x0008 /* AIF1DAC_COMPMODE */ 1777*4882a593Smuzhiyun #define WM8995_AIF1DAC_COMPMODE_SHIFT 3 /* AIF1DAC_COMPMODE */ 1778*4882a593Smuzhiyun #define WM8995_AIF1DAC_COMPMODE_WIDTH 1 /* AIF1DAC_COMPMODE */ 1779*4882a593Smuzhiyun #define WM8995_AIF1ADC_COMP 0x0004 /* AIF1ADC_COMP */ 1780*4882a593Smuzhiyun #define WM8995_AIF1ADC_COMP_MASK 0x0004 /* AIF1ADC_COMP */ 1781*4882a593Smuzhiyun #define WM8995_AIF1ADC_COMP_SHIFT 2 /* AIF1ADC_COMP */ 1782*4882a593Smuzhiyun #define WM8995_AIF1ADC_COMP_WIDTH 1 /* AIF1ADC_COMP */ 1783*4882a593Smuzhiyun #define WM8995_AIF1ADC_COMPMODE 0x0002 /* AIF1ADC_COMPMODE */ 1784*4882a593Smuzhiyun #define WM8995_AIF1ADC_COMPMODE_MASK 0x0002 /* AIF1ADC_COMPMODE */ 1785*4882a593Smuzhiyun #define WM8995_AIF1ADC_COMPMODE_SHIFT 1 /* AIF1ADC_COMPMODE */ 1786*4882a593Smuzhiyun #define WM8995_AIF1ADC_COMPMODE_WIDTH 1 /* AIF1ADC_COMPMODE */ 1787*4882a593Smuzhiyun #define WM8995_AIF1_LOOPBACK 0x0001 /* AIF1_LOOPBACK */ 1788*4882a593Smuzhiyun #define WM8995_AIF1_LOOPBACK_MASK 0x0001 /* AIF1_LOOPBACK */ 1789*4882a593Smuzhiyun #define WM8995_AIF1_LOOPBACK_SHIFT 0 /* AIF1_LOOPBACK */ 1790*4882a593Smuzhiyun #define WM8995_AIF1_LOOPBACK_WIDTH 1 /* AIF1_LOOPBACK */ 1791*4882a593Smuzhiyun 1792*4882a593Smuzhiyun /* 1793*4882a593Smuzhiyun * R770 (0x302) - AIF1 Master/Slave 1794*4882a593Smuzhiyun */ 1795*4882a593Smuzhiyun #define WM8995_AIF1_TRI 0x8000 /* AIF1_TRI */ 1796*4882a593Smuzhiyun #define WM8995_AIF1_TRI_MASK 0x8000 /* AIF1_TRI */ 1797*4882a593Smuzhiyun #define WM8995_AIF1_TRI_SHIFT 15 /* AIF1_TRI */ 1798*4882a593Smuzhiyun #define WM8995_AIF1_TRI_WIDTH 1 /* AIF1_TRI */ 1799*4882a593Smuzhiyun #define WM8995_AIF1_MSTR 0x4000 /* AIF1_MSTR */ 1800*4882a593Smuzhiyun #define WM8995_AIF1_MSTR_MASK 0x4000 /* AIF1_MSTR */ 1801*4882a593Smuzhiyun #define WM8995_AIF1_MSTR_SHIFT 14 /* AIF1_MSTR */ 1802*4882a593Smuzhiyun #define WM8995_AIF1_MSTR_WIDTH 1 /* AIF1_MSTR */ 1803*4882a593Smuzhiyun #define WM8995_AIF1_CLK_FRC 0x2000 /* AIF1_CLK_FRC */ 1804*4882a593Smuzhiyun #define WM8995_AIF1_CLK_FRC_MASK 0x2000 /* AIF1_CLK_FRC */ 1805*4882a593Smuzhiyun #define WM8995_AIF1_CLK_FRC_SHIFT 13 /* AIF1_CLK_FRC */ 1806*4882a593Smuzhiyun #define WM8995_AIF1_CLK_FRC_WIDTH 1 /* AIF1_CLK_FRC */ 1807*4882a593Smuzhiyun #define WM8995_AIF1_LRCLK_FRC 0x1000 /* AIF1_LRCLK_FRC */ 1808*4882a593Smuzhiyun #define WM8995_AIF1_LRCLK_FRC_MASK 0x1000 /* AIF1_LRCLK_FRC */ 1809*4882a593Smuzhiyun #define WM8995_AIF1_LRCLK_FRC_SHIFT 12 /* AIF1_LRCLK_FRC */ 1810*4882a593Smuzhiyun #define WM8995_AIF1_LRCLK_FRC_WIDTH 1 /* AIF1_LRCLK_FRC */ 1811*4882a593Smuzhiyun 1812*4882a593Smuzhiyun /* 1813*4882a593Smuzhiyun * R771 (0x303) - AIF1 BCLK 1814*4882a593Smuzhiyun */ 1815*4882a593Smuzhiyun #define WM8995_AIF1_BCLK_DIV_MASK 0x00F0 /* AIF1_BCLK_DIV - [7:4] */ 1816*4882a593Smuzhiyun #define WM8995_AIF1_BCLK_DIV_SHIFT 4 /* AIF1_BCLK_DIV - [7:4] */ 1817*4882a593Smuzhiyun #define WM8995_AIF1_BCLK_DIV_WIDTH 4 /* AIF1_BCLK_DIV - [7:4] */ 1818*4882a593Smuzhiyun 1819*4882a593Smuzhiyun /* 1820*4882a593Smuzhiyun * R772 (0x304) - AIF1ADC LRCLK 1821*4882a593Smuzhiyun */ 1822*4882a593Smuzhiyun #define WM8995_AIF1ADC_LRCLK_DIR 0x0800 /* AIF1ADC_LRCLK_DIR */ 1823*4882a593Smuzhiyun #define WM8995_AIF1ADC_LRCLK_DIR_MASK 0x0800 /* AIF1ADC_LRCLK_DIR */ 1824*4882a593Smuzhiyun #define WM8995_AIF1ADC_LRCLK_DIR_SHIFT 11 /* AIF1ADC_LRCLK_DIR */ 1825*4882a593Smuzhiyun #define WM8995_AIF1ADC_LRCLK_DIR_WIDTH 1 /* AIF1ADC_LRCLK_DIR */ 1826*4882a593Smuzhiyun #define WM8995_AIF1ADC_RATE_MASK 0x07FF /* AIF1ADC_RATE - [10:0] */ 1827*4882a593Smuzhiyun #define WM8995_AIF1ADC_RATE_SHIFT 0 /* AIF1ADC_RATE - [10:0] */ 1828*4882a593Smuzhiyun #define WM8995_AIF1ADC_RATE_WIDTH 11 /* AIF1ADC_RATE - [10:0] */ 1829*4882a593Smuzhiyun 1830*4882a593Smuzhiyun /* 1831*4882a593Smuzhiyun * R773 (0x305) - AIF1DAC LRCLK 1832*4882a593Smuzhiyun */ 1833*4882a593Smuzhiyun #define WM8995_AIF1DAC_LRCLK_DIR 0x0800 /* AIF1DAC_LRCLK_DIR */ 1834*4882a593Smuzhiyun #define WM8995_AIF1DAC_LRCLK_DIR_MASK 0x0800 /* AIF1DAC_LRCLK_DIR */ 1835*4882a593Smuzhiyun #define WM8995_AIF1DAC_LRCLK_DIR_SHIFT 11 /* AIF1DAC_LRCLK_DIR */ 1836*4882a593Smuzhiyun #define WM8995_AIF1DAC_LRCLK_DIR_WIDTH 1 /* AIF1DAC_LRCLK_DIR */ 1837*4882a593Smuzhiyun #define WM8995_AIF1DAC_RATE_MASK 0x07FF /* AIF1DAC_RATE - [10:0] */ 1838*4882a593Smuzhiyun #define WM8995_AIF1DAC_RATE_SHIFT 0 /* AIF1DAC_RATE - [10:0] */ 1839*4882a593Smuzhiyun #define WM8995_AIF1DAC_RATE_WIDTH 11 /* AIF1DAC_RATE - [10:0] */ 1840*4882a593Smuzhiyun 1841*4882a593Smuzhiyun /* 1842*4882a593Smuzhiyun * R774 (0x306) - AIF1DAC Data 1843*4882a593Smuzhiyun */ 1844*4882a593Smuzhiyun #define WM8995_AIF1DACL_DAT_INV 0x0002 /* AIF1DACL_DAT_INV */ 1845*4882a593Smuzhiyun #define WM8995_AIF1DACL_DAT_INV_MASK 0x0002 /* AIF1DACL_DAT_INV */ 1846*4882a593Smuzhiyun #define WM8995_AIF1DACL_DAT_INV_SHIFT 1 /* AIF1DACL_DAT_INV */ 1847*4882a593Smuzhiyun #define WM8995_AIF1DACL_DAT_INV_WIDTH 1 /* AIF1DACL_DAT_INV */ 1848*4882a593Smuzhiyun #define WM8995_AIF1DACR_DAT_INV 0x0001 /* AIF1DACR_DAT_INV */ 1849*4882a593Smuzhiyun #define WM8995_AIF1DACR_DAT_INV_MASK 0x0001 /* AIF1DACR_DAT_INV */ 1850*4882a593Smuzhiyun #define WM8995_AIF1DACR_DAT_INV_SHIFT 0 /* AIF1DACR_DAT_INV */ 1851*4882a593Smuzhiyun #define WM8995_AIF1DACR_DAT_INV_WIDTH 1 /* AIF1DACR_DAT_INV */ 1852*4882a593Smuzhiyun 1853*4882a593Smuzhiyun /* 1854*4882a593Smuzhiyun * R775 (0x307) - AIF1ADC Data 1855*4882a593Smuzhiyun */ 1856*4882a593Smuzhiyun #define WM8995_AIF1ADCL_DAT_INV 0x0002 /* AIF1ADCL_DAT_INV */ 1857*4882a593Smuzhiyun #define WM8995_AIF1ADCL_DAT_INV_MASK 0x0002 /* AIF1ADCL_DAT_INV */ 1858*4882a593Smuzhiyun #define WM8995_AIF1ADCL_DAT_INV_SHIFT 1 /* AIF1ADCL_DAT_INV */ 1859*4882a593Smuzhiyun #define WM8995_AIF1ADCL_DAT_INV_WIDTH 1 /* AIF1ADCL_DAT_INV */ 1860*4882a593Smuzhiyun #define WM8995_AIF1ADCR_DAT_INV 0x0001 /* AIF1ADCR_DAT_INV */ 1861*4882a593Smuzhiyun #define WM8995_AIF1ADCR_DAT_INV_MASK 0x0001 /* AIF1ADCR_DAT_INV */ 1862*4882a593Smuzhiyun #define WM8995_AIF1ADCR_DAT_INV_SHIFT 0 /* AIF1ADCR_DAT_INV */ 1863*4882a593Smuzhiyun #define WM8995_AIF1ADCR_DAT_INV_WIDTH 1 /* AIF1ADCR_DAT_INV */ 1864*4882a593Smuzhiyun 1865*4882a593Smuzhiyun /* 1866*4882a593Smuzhiyun * R784 (0x310) - AIF2 Control (1) 1867*4882a593Smuzhiyun */ 1868*4882a593Smuzhiyun #define WM8995_AIF2ADCL_SRC 0x8000 /* AIF2ADCL_SRC */ 1869*4882a593Smuzhiyun #define WM8995_AIF2ADCL_SRC_MASK 0x8000 /* AIF2ADCL_SRC */ 1870*4882a593Smuzhiyun #define WM8995_AIF2ADCL_SRC_SHIFT 15 /* AIF2ADCL_SRC */ 1871*4882a593Smuzhiyun #define WM8995_AIF2ADCL_SRC_WIDTH 1 /* AIF2ADCL_SRC */ 1872*4882a593Smuzhiyun #define WM8995_AIF2ADCR_SRC 0x4000 /* AIF2ADCR_SRC */ 1873*4882a593Smuzhiyun #define WM8995_AIF2ADCR_SRC_MASK 0x4000 /* AIF2ADCR_SRC */ 1874*4882a593Smuzhiyun #define WM8995_AIF2ADCR_SRC_SHIFT 14 /* AIF2ADCR_SRC */ 1875*4882a593Smuzhiyun #define WM8995_AIF2ADCR_SRC_WIDTH 1 /* AIF2ADCR_SRC */ 1876*4882a593Smuzhiyun #define WM8995_AIF2ADC_TDM 0x2000 /* AIF2ADC_TDM */ 1877*4882a593Smuzhiyun #define WM8995_AIF2ADC_TDM_MASK 0x2000 /* AIF2ADC_TDM */ 1878*4882a593Smuzhiyun #define WM8995_AIF2ADC_TDM_SHIFT 13 /* AIF2ADC_TDM */ 1879*4882a593Smuzhiyun #define WM8995_AIF2ADC_TDM_WIDTH 1 /* AIF2ADC_TDM */ 1880*4882a593Smuzhiyun #define WM8995_AIF2ADC_TDM_CHAN 0x1000 /* AIF2ADC_TDM_CHAN */ 1881*4882a593Smuzhiyun #define WM8995_AIF2ADC_TDM_CHAN_MASK 0x1000 /* AIF2ADC_TDM_CHAN */ 1882*4882a593Smuzhiyun #define WM8995_AIF2ADC_TDM_CHAN_SHIFT 12 /* AIF2ADC_TDM_CHAN */ 1883*4882a593Smuzhiyun #define WM8995_AIF2ADC_TDM_CHAN_WIDTH 1 /* AIF2ADC_TDM_CHAN */ 1884*4882a593Smuzhiyun #define WM8995_AIF2_BCLK_INV 0x0100 /* AIF2_BCLK_INV */ 1885*4882a593Smuzhiyun #define WM8995_AIF2_BCLK_INV_MASK 0x0100 /* AIF2_BCLK_INV */ 1886*4882a593Smuzhiyun #define WM8995_AIF2_BCLK_INV_SHIFT 8 /* AIF2_BCLK_INV */ 1887*4882a593Smuzhiyun #define WM8995_AIF2_BCLK_INV_WIDTH 1 /* AIF2_BCLK_INV */ 1888*4882a593Smuzhiyun #define WM8995_AIF2_LRCLK_INV 0x0080 /* AIF2_LRCLK_INV */ 1889*4882a593Smuzhiyun #define WM8995_AIF2_LRCLK_INV_MASK 0x0080 /* AIF2_LRCLK_INV */ 1890*4882a593Smuzhiyun #define WM8995_AIF2_LRCLK_INV_SHIFT 7 /* AIF2_LRCLK_INV */ 1891*4882a593Smuzhiyun #define WM8995_AIF2_LRCLK_INV_WIDTH 1 /* AIF2_LRCLK_INV */ 1892*4882a593Smuzhiyun #define WM8995_AIF2_WL_MASK 0x0060 /* AIF2_WL - [6:5] */ 1893*4882a593Smuzhiyun #define WM8995_AIF2_WL_SHIFT 5 /* AIF2_WL - [6:5] */ 1894*4882a593Smuzhiyun #define WM8995_AIF2_WL_WIDTH 2 /* AIF2_WL - [6:5] */ 1895*4882a593Smuzhiyun #define WM8995_AIF2_FMT_MASK 0x0018 /* AIF2_FMT - [4:3] */ 1896*4882a593Smuzhiyun #define WM8995_AIF2_FMT_SHIFT 3 /* AIF2_FMT - [4:3] */ 1897*4882a593Smuzhiyun #define WM8995_AIF2_FMT_WIDTH 2 /* AIF2_FMT - [4:3] */ 1898*4882a593Smuzhiyun 1899*4882a593Smuzhiyun /* 1900*4882a593Smuzhiyun * R785 (0x311) - AIF2 Control (2) 1901*4882a593Smuzhiyun */ 1902*4882a593Smuzhiyun #define WM8995_AIF2DACL_SRC 0x8000 /* AIF2DACL_SRC */ 1903*4882a593Smuzhiyun #define WM8995_AIF2DACL_SRC_MASK 0x8000 /* AIF2DACL_SRC */ 1904*4882a593Smuzhiyun #define WM8995_AIF2DACL_SRC_SHIFT 15 /* AIF2DACL_SRC */ 1905*4882a593Smuzhiyun #define WM8995_AIF2DACL_SRC_WIDTH 1 /* AIF2DACL_SRC */ 1906*4882a593Smuzhiyun #define WM8995_AIF2DACR_SRC 0x4000 /* AIF2DACR_SRC */ 1907*4882a593Smuzhiyun #define WM8995_AIF2DACR_SRC_MASK 0x4000 /* AIF2DACR_SRC */ 1908*4882a593Smuzhiyun #define WM8995_AIF2DACR_SRC_SHIFT 14 /* AIF2DACR_SRC */ 1909*4882a593Smuzhiyun #define WM8995_AIF2DACR_SRC_WIDTH 1 /* AIF2DACR_SRC */ 1910*4882a593Smuzhiyun #define WM8995_AIF2DAC_TDM 0x2000 /* AIF2DAC_TDM */ 1911*4882a593Smuzhiyun #define WM8995_AIF2DAC_TDM_MASK 0x2000 /* AIF2DAC_TDM */ 1912*4882a593Smuzhiyun #define WM8995_AIF2DAC_TDM_SHIFT 13 /* AIF2DAC_TDM */ 1913*4882a593Smuzhiyun #define WM8995_AIF2DAC_TDM_WIDTH 1 /* AIF2DAC_TDM */ 1914*4882a593Smuzhiyun #define WM8995_AIF2DAC_TDM_CHAN 0x1000 /* AIF2DAC_TDM_CHAN */ 1915*4882a593Smuzhiyun #define WM8995_AIF2DAC_TDM_CHAN_MASK 0x1000 /* AIF2DAC_TDM_CHAN */ 1916*4882a593Smuzhiyun #define WM8995_AIF2DAC_TDM_CHAN_SHIFT 12 /* AIF2DAC_TDM_CHAN */ 1917*4882a593Smuzhiyun #define WM8995_AIF2DAC_TDM_CHAN_WIDTH 1 /* AIF2DAC_TDM_CHAN */ 1918*4882a593Smuzhiyun #define WM8995_AIF2DAC_BOOST_MASK 0x0C00 /* AIF2DAC_BOOST - [11:10] */ 1919*4882a593Smuzhiyun #define WM8995_AIF2DAC_BOOST_SHIFT 10 /* AIF2DAC_BOOST - [11:10] */ 1920*4882a593Smuzhiyun #define WM8995_AIF2DAC_BOOST_WIDTH 2 /* AIF2DAC_BOOST - [11:10] */ 1921*4882a593Smuzhiyun #define WM8995_AIF2DAC_COMP 0x0010 /* AIF2DAC_COMP */ 1922*4882a593Smuzhiyun #define WM8995_AIF2DAC_COMP_MASK 0x0010 /* AIF2DAC_COMP */ 1923*4882a593Smuzhiyun #define WM8995_AIF2DAC_COMP_SHIFT 4 /* AIF2DAC_COMP */ 1924*4882a593Smuzhiyun #define WM8995_AIF2DAC_COMP_WIDTH 1 /* AIF2DAC_COMP */ 1925*4882a593Smuzhiyun #define WM8995_AIF2DAC_COMPMODE 0x0008 /* AIF2DAC_COMPMODE */ 1926*4882a593Smuzhiyun #define WM8995_AIF2DAC_COMPMODE_MASK 0x0008 /* AIF2DAC_COMPMODE */ 1927*4882a593Smuzhiyun #define WM8995_AIF2DAC_COMPMODE_SHIFT 3 /* AIF2DAC_COMPMODE */ 1928*4882a593Smuzhiyun #define WM8995_AIF2DAC_COMPMODE_WIDTH 1 /* AIF2DAC_COMPMODE */ 1929*4882a593Smuzhiyun #define WM8995_AIF2ADC_COMP 0x0004 /* AIF2ADC_COMP */ 1930*4882a593Smuzhiyun #define WM8995_AIF2ADC_COMP_MASK 0x0004 /* AIF2ADC_COMP */ 1931*4882a593Smuzhiyun #define WM8995_AIF2ADC_COMP_SHIFT 2 /* AIF2ADC_COMP */ 1932*4882a593Smuzhiyun #define WM8995_AIF2ADC_COMP_WIDTH 1 /* AIF2ADC_COMP */ 1933*4882a593Smuzhiyun #define WM8995_AIF2ADC_COMPMODE 0x0002 /* AIF2ADC_COMPMODE */ 1934*4882a593Smuzhiyun #define WM8995_AIF2ADC_COMPMODE_MASK 0x0002 /* AIF2ADC_COMPMODE */ 1935*4882a593Smuzhiyun #define WM8995_AIF2ADC_COMPMODE_SHIFT 1 /* AIF2ADC_COMPMODE */ 1936*4882a593Smuzhiyun #define WM8995_AIF2ADC_COMPMODE_WIDTH 1 /* AIF2ADC_COMPMODE */ 1937*4882a593Smuzhiyun #define WM8995_AIF2_LOOPBACK 0x0001 /* AIF2_LOOPBACK */ 1938*4882a593Smuzhiyun #define WM8995_AIF2_LOOPBACK_MASK 0x0001 /* AIF2_LOOPBACK */ 1939*4882a593Smuzhiyun #define WM8995_AIF2_LOOPBACK_SHIFT 0 /* AIF2_LOOPBACK */ 1940*4882a593Smuzhiyun #define WM8995_AIF2_LOOPBACK_WIDTH 1 /* AIF2_LOOPBACK */ 1941*4882a593Smuzhiyun 1942*4882a593Smuzhiyun /* 1943*4882a593Smuzhiyun * R786 (0x312) - AIF2 Master/Slave 1944*4882a593Smuzhiyun */ 1945*4882a593Smuzhiyun #define WM8995_AIF2_TRI 0x8000 /* AIF2_TRI */ 1946*4882a593Smuzhiyun #define WM8995_AIF2_TRI_MASK 0x8000 /* AIF2_TRI */ 1947*4882a593Smuzhiyun #define WM8995_AIF2_TRI_SHIFT 15 /* AIF2_TRI */ 1948*4882a593Smuzhiyun #define WM8995_AIF2_TRI_WIDTH 1 /* AIF2_TRI */ 1949*4882a593Smuzhiyun #define WM8995_AIF2_MSTR 0x4000 /* AIF2_MSTR */ 1950*4882a593Smuzhiyun #define WM8995_AIF2_MSTR_MASK 0x4000 /* AIF2_MSTR */ 1951*4882a593Smuzhiyun #define WM8995_AIF2_MSTR_SHIFT 14 /* AIF2_MSTR */ 1952*4882a593Smuzhiyun #define WM8995_AIF2_MSTR_WIDTH 1 /* AIF2_MSTR */ 1953*4882a593Smuzhiyun #define WM8995_AIF2_CLK_FRC 0x2000 /* AIF2_CLK_FRC */ 1954*4882a593Smuzhiyun #define WM8995_AIF2_CLK_FRC_MASK 0x2000 /* AIF2_CLK_FRC */ 1955*4882a593Smuzhiyun #define WM8995_AIF2_CLK_FRC_SHIFT 13 /* AIF2_CLK_FRC */ 1956*4882a593Smuzhiyun #define WM8995_AIF2_CLK_FRC_WIDTH 1 /* AIF2_CLK_FRC */ 1957*4882a593Smuzhiyun #define WM8995_AIF2_LRCLK_FRC 0x1000 /* AIF2_LRCLK_FRC */ 1958*4882a593Smuzhiyun #define WM8995_AIF2_LRCLK_FRC_MASK 0x1000 /* AIF2_LRCLK_FRC */ 1959*4882a593Smuzhiyun #define WM8995_AIF2_LRCLK_FRC_SHIFT 12 /* AIF2_LRCLK_FRC */ 1960*4882a593Smuzhiyun #define WM8995_AIF2_LRCLK_FRC_WIDTH 1 /* AIF2_LRCLK_FRC */ 1961*4882a593Smuzhiyun 1962*4882a593Smuzhiyun /* 1963*4882a593Smuzhiyun * R787 (0x313) - AIF2 BCLK 1964*4882a593Smuzhiyun */ 1965*4882a593Smuzhiyun #define WM8995_AIF2_BCLK_DIV_MASK 0x00F0 /* AIF2_BCLK_DIV - [7:4] */ 1966*4882a593Smuzhiyun #define WM8995_AIF2_BCLK_DIV_SHIFT 4 /* AIF2_BCLK_DIV - [7:4] */ 1967*4882a593Smuzhiyun #define WM8995_AIF2_BCLK_DIV_WIDTH 4 /* AIF2_BCLK_DIV - [7:4] */ 1968*4882a593Smuzhiyun 1969*4882a593Smuzhiyun /* 1970*4882a593Smuzhiyun * R788 (0x314) - AIF2ADC LRCLK 1971*4882a593Smuzhiyun */ 1972*4882a593Smuzhiyun #define WM8995_AIF2ADC_LRCLK_DIR 0x0800 /* AIF2ADC_LRCLK_DIR */ 1973*4882a593Smuzhiyun #define WM8995_AIF2ADC_LRCLK_DIR_MASK 0x0800 /* AIF2ADC_LRCLK_DIR */ 1974*4882a593Smuzhiyun #define WM8995_AIF2ADC_LRCLK_DIR_SHIFT 11 /* AIF2ADC_LRCLK_DIR */ 1975*4882a593Smuzhiyun #define WM8995_AIF2ADC_LRCLK_DIR_WIDTH 1 /* AIF2ADC_LRCLK_DIR */ 1976*4882a593Smuzhiyun #define WM8995_AIF2ADC_RATE_MASK 0x07FF /* AIF2ADC_RATE - [10:0] */ 1977*4882a593Smuzhiyun #define WM8995_AIF2ADC_RATE_SHIFT 0 /* AIF2ADC_RATE - [10:0] */ 1978*4882a593Smuzhiyun #define WM8995_AIF2ADC_RATE_WIDTH 11 /* AIF2ADC_RATE - [10:0] */ 1979*4882a593Smuzhiyun 1980*4882a593Smuzhiyun /* 1981*4882a593Smuzhiyun * R789 (0x315) - AIF2DAC LRCLK 1982*4882a593Smuzhiyun */ 1983*4882a593Smuzhiyun #define WM8995_AIF2DAC_LRCLK_DIR 0x0800 /* AIF2DAC_LRCLK_DIR */ 1984*4882a593Smuzhiyun #define WM8995_AIF2DAC_LRCLK_DIR_MASK 0x0800 /* AIF2DAC_LRCLK_DIR */ 1985*4882a593Smuzhiyun #define WM8995_AIF2DAC_LRCLK_DIR_SHIFT 11 /* AIF2DAC_LRCLK_DIR */ 1986*4882a593Smuzhiyun #define WM8995_AIF2DAC_LRCLK_DIR_WIDTH 1 /* AIF2DAC_LRCLK_DIR */ 1987*4882a593Smuzhiyun #define WM8995_AIF2DAC_RATE_MASK 0x07FF /* AIF2DAC_RATE - [10:0] */ 1988*4882a593Smuzhiyun #define WM8995_AIF2DAC_RATE_SHIFT 0 /* AIF2DAC_RATE - [10:0] */ 1989*4882a593Smuzhiyun #define WM8995_AIF2DAC_RATE_WIDTH 11 /* AIF2DAC_RATE - [10:0] */ 1990*4882a593Smuzhiyun 1991*4882a593Smuzhiyun /* 1992*4882a593Smuzhiyun * R790 (0x316) - AIF2DAC Data 1993*4882a593Smuzhiyun */ 1994*4882a593Smuzhiyun #define WM8995_AIF2DACL_DAT_INV 0x0002 /* AIF2DACL_DAT_INV */ 1995*4882a593Smuzhiyun #define WM8995_AIF2DACL_DAT_INV_MASK 0x0002 /* AIF2DACL_DAT_INV */ 1996*4882a593Smuzhiyun #define WM8995_AIF2DACL_DAT_INV_SHIFT 1 /* AIF2DACL_DAT_INV */ 1997*4882a593Smuzhiyun #define WM8995_AIF2DACL_DAT_INV_WIDTH 1 /* AIF2DACL_DAT_INV */ 1998*4882a593Smuzhiyun #define WM8995_AIF2DACR_DAT_INV 0x0001 /* AIF2DACR_DAT_INV */ 1999*4882a593Smuzhiyun #define WM8995_AIF2DACR_DAT_INV_MASK 0x0001 /* AIF2DACR_DAT_INV */ 2000*4882a593Smuzhiyun #define WM8995_AIF2DACR_DAT_INV_SHIFT 0 /* AIF2DACR_DAT_INV */ 2001*4882a593Smuzhiyun #define WM8995_AIF2DACR_DAT_INV_WIDTH 1 /* AIF2DACR_DAT_INV */ 2002*4882a593Smuzhiyun 2003*4882a593Smuzhiyun /* 2004*4882a593Smuzhiyun * R791 (0x317) - AIF2ADC Data 2005*4882a593Smuzhiyun */ 2006*4882a593Smuzhiyun #define WM8995_AIF2ADCL_DAT_INV 0x0002 /* AIF2ADCL_DAT_INV */ 2007*4882a593Smuzhiyun #define WM8995_AIF2ADCL_DAT_INV_MASK 0x0002 /* AIF2ADCL_DAT_INV */ 2008*4882a593Smuzhiyun #define WM8995_AIF2ADCL_DAT_INV_SHIFT 1 /* AIF2ADCL_DAT_INV */ 2009*4882a593Smuzhiyun #define WM8995_AIF2ADCL_DAT_INV_WIDTH 1 /* AIF2ADCL_DAT_INV */ 2010*4882a593Smuzhiyun #define WM8995_AIF2ADCR_DAT_INV 0x0001 /* AIF2ADCR_DAT_INV */ 2011*4882a593Smuzhiyun #define WM8995_AIF2ADCR_DAT_INV_MASK 0x0001 /* AIF2ADCR_DAT_INV */ 2012*4882a593Smuzhiyun #define WM8995_AIF2ADCR_DAT_INV_SHIFT 0 /* AIF2ADCR_DAT_INV */ 2013*4882a593Smuzhiyun #define WM8995_AIF2ADCR_DAT_INV_WIDTH 1 /* AIF2ADCR_DAT_INV */ 2014*4882a593Smuzhiyun 2015*4882a593Smuzhiyun /* 2016*4882a593Smuzhiyun * R1024 (0x400) - AIF1 ADC1 Left Volume 2017*4882a593Smuzhiyun */ 2018*4882a593Smuzhiyun #define WM8995_AIF1ADC1_VU 0x0100 /* AIF1ADC1_VU */ 2019*4882a593Smuzhiyun #define WM8995_AIF1ADC1_VU_MASK 0x0100 /* AIF1ADC1_VU */ 2020*4882a593Smuzhiyun #define WM8995_AIF1ADC1_VU_SHIFT 8 /* AIF1ADC1_VU */ 2021*4882a593Smuzhiyun #define WM8995_AIF1ADC1_VU_WIDTH 1 /* AIF1ADC1_VU */ 2022*4882a593Smuzhiyun #define WM8995_AIF1ADC1L_VOL_MASK 0x00FF /* AIF1ADC1L_VOL - [7:0] */ 2023*4882a593Smuzhiyun #define WM8995_AIF1ADC1L_VOL_SHIFT 0 /* AIF1ADC1L_VOL - [7:0] */ 2024*4882a593Smuzhiyun #define WM8995_AIF1ADC1L_VOL_WIDTH 8 /* AIF1ADC1L_VOL - [7:0] */ 2025*4882a593Smuzhiyun 2026*4882a593Smuzhiyun /* 2027*4882a593Smuzhiyun * R1025 (0x401) - AIF1 ADC1 Right Volume 2028*4882a593Smuzhiyun */ 2029*4882a593Smuzhiyun #define WM8995_AIF1ADC1_VU 0x0100 /* AIF1ADC1_VU */ 2030*4882a593Smuzhiyun #define WM8995_AIF1ADC1_VU_MASK 0x0100 /* AIF1ADC1_VU */ 2031*4882a593Smuzhiyun #define WM8995_AIF1ADC1_VU_SHIFT 8 /* AIF1ADC1_VU */ 2032*4882a593Smuzhiyun #define WM8995_AIF1ADC1_VU_WIDTH 1 /* AIF1ADC1_VU */ 2033*4882a593Smuzhiyun #define WM8995_AIF1ADC1R_VOL_MASK 0x00FF /* AIF1ADC1R_VOL - [7:0] */ 2034*4882a593Smuzhiyun #define WM8995_AIF1ADC1R_VOL_SHIFT 0 /* AIF1ADC1R_VOL - [7:0] */ 2035*4882a593Smuzhiyun #define WM8995_AIF1ADC1R_VOL_WIDTH 8 /* AIF1ADC1R_VOL - [7:0] */ 2036*4882a593Smuzhiyun 2037*4882a593Smuzhiyun /* 2038*4882a593Smuzhiyun * R1026 (0x402) - AIF1 DAC1 Left Volume 2039*4882a593Smuzhiyun */ 2040*4882a593Smuzhiyun #define WM8995_AIF1DAC1_VU 0x0100 /* AIF1DAC1_VU */ 2041*4882a593Smuzhiyun #define WM8995_AIF1DAC1_VU_MASK 0x0100 /* AIF1DAC1_VU */ 2042*4882a593Smuzhiyun #define WM8995_AIF1DAC1_VU_SHIFT 8 /* AIF1DAC1_VU */ 2043*4882a593Smuzhiyun #define WM8995_AIF1DAC1_VU_WIDTH 1 /* AIF1DAC1_VU */ 2044*4882a593Smuzhiyun #define WM8995_AIF1DAC1L_VOL_MASK 0x00FF /* AIF1DAC1L_VOL - [7:0] */ 2045*4882a593Smuzhiyun #define WM8995_AIF1DAC1L_VOL_SHIFT 0 /* AIF1DAC1L_VOL - [7:0] */ 2046*4882a593Smuzhiyun #define WM8995_AIF1DAC1L_VOL_WIDTH 8 /* AIF1DAC1L_VOL - [7:0] */ 2047*4882a593Smuzhiyun 2048*4882a593Smuzhiyun /* 2049*4882a593Smuzhiyun * R1027 (0x403) - AIF1 DAC1 Right Volume 2050*4882a593Smuzhiyun */ 2051*4882a593Smuzhiyun #define WM8995_AIF1DAC1_VU 0x0100 /* AIF1DAC1_VU */ 2052*4882a593Smuzhiyun #define WM8995_AIF1DAC1_VU_MASK 0x0100 /* AIF1DAC1_VU */ 2053*4882a593Smuzhiyun #define WM8995_AIF1DAC1_VU_SHIFT 8 /* AIF1DAC1_VU */ 2054*4882a593Smuzhiyun #define WM8995_AIF1DAC1_VU_WIDTH 1 /* AIF1DAC1_VU */ 2055*4882a593Smuzhiyun #define WM8995_AIF1DAC1R_VOL_MASK 0x00FF /* AIF1DAC1R_VOL - [7:0] */ 2056*4882a593Smuzhiyun #define WM8995_AIF1DAC1R_VOL_SHIFT 0 /* AIF1DAC1R_VOL - [7:0] */ 2057*4882a593Smuzhiyun #define WM8995_AIF1DAC1R_VOL_WIDTH 8 /* AIF1DAC1R_VOL - [7:0] */ 2058*4882a593Smuzhiyun 2059*4882a593Smuzhiyun /* 2060*4882a593Smuzhiyun * R1028 (0x404) - AIF1 ADC2 Left Volume 2061*4882a593Smuzhiyun */ 2062*4882a593Smuzhiyun #define WM8995_AIF1ADC2_VU 0x0100 /* AIF1ADC2_VU */ 2063*4882a593Smuzhiyun #define WM8995_AIF1ADC2_VU_MASK 0x0100 /* AIF1ADC2_VU */ 2064*4882a593Smuzhiyun #define WM8995_AIF1ADC2_VU_SHIFT 8 /* AIF1ADC2_VU */ 2065*4882a593Smuzhiyun #define WM8995_AIF1ADC2_VU_WIDTH 1 /* AIF1ADC2_VU */ 2066*4882a593Smuzhiyun #define WM8995_AIF1ADC2L_VOL_MASK 0x00FF /* AIF1ADC2L_VOL - [7:0] */ 2067*4882a593Smuzhiyun #define WM8995_AIF1ADC2L_VOL_SHIFT 0 /* AIF1ADC2L_VOL - [7:0] */ 2068*4882a593Smuzhiyun #define WM8995_AIF1ADC2L_VOL_WIDTH 8 /* AIF1ADC2L_VOL - [7:0] */ 2069*4882a593Smuzhiyun 2070*4882a593Smuzhiyun /* 2071*4882a593Smuzhiyun * R1029 (0x405) - AIF1 ADC2 Right Volume 2072*4882a593Smuzhiyun */ 2073*4882a593Smuzhiyun #define WM8995_AIF1ADC2_VU 0x0100 /* AIF1ADC2_VU */ 2074*4882a593Smuzhiyun #define WM8995_AIF1ADC2_VU_MASK 0x0100 /* AIF1ADC2_VU */ 2075*4882a593Smuzhiyun #define WM8995_AIF1ADC2_VU_SHIFT 8 /* AIF1ADC2_VU */ 2076*4882a593Smuzhiyun #define WM8995_AIF1ADC2_VU_WIDTH 1 /* AIF1ADC2_VU */ 2077*4882a593Smuzhiyun #define WM8995_AIF1ADC2R_VOL_MASK 0x00FF /* AIF1ADC2R_VOL - [7:0] */ 2078*4882a593Smuzhiyun #define WM8995_AIF1ADC2R_VOL_SHIFT 0 /* AIF1ADC2R_VOL - [7:0] */ 2079*4882a593Smuzhiyun #define WM8995_AIF1ADC2R_VOL_WIDTH 8 /* AIF1ADC2R_VOL - [7:0] */ 2080*4882a593Smuzhiyun 2081*4882a593Smuzhiyun /* 2082*4882a593Smuzhiyun * R1030 (0x406) - AIF1 DAC2 Left Volume 2083*4882a593Smuzhiyun */ 2084*4882a593Smuzhiyun #define WM8995_AIF1DAC2_VU 0x0100 /* AIF1DAC2_VU */ 2085*4882a593Smuzhiyun #define WM8995_AIF1DAC2_VU_MASK 0x0100 /* AIF1DAC2_VU */ 2086*4882a593Smuzhiyun #define WM8995_AIF1DAC2_VU_SHIFT 8 /* AIF1DAC2_VU */ 2087*4882a593Smuzhiyun #define WM8995_AIF1DAC2_VU_WIDTH 1 /* AIF1DAC2_VU */ 2088*4882a593Smuzhiyun #define WM8995_AIF1DAC2L_VOL_MASK 0x00FF /* AIF1DAC2L_VOL - [7:0] */ 2089*4882a593Smuzhiyun #define WM8995_AIF1DAC2L_VOL_SHIFT 0 /* AIF1DAC2L_VOL - [7:0] */ 2090*4882a593Smuzhiyun #define WM8995_AIF1DAC2L_VOL_WIDTH 8 /* AIF1DAC2L_VOL - [7:0] */ 2091*4882a593Smuzhiyun 2092*4882a593Smuzhiyun /* 2093*4882a593Smuzhiyun * R1031 (0x407) - AIF1 DAC2 Right Volume 2094*4882a593Smuzhiyun */ 2095*4882a593Smuzhiyun #define WM8995_AIF1DAC2_VU 0x0100 /* AIF1DAC2_VU */ 2096*4882a593Smuzhiyun #define WM8995_AIF1DAC2_VU_MASK 0x0100 /* AIF1DAC2_VU */ 2097*4882a593Smuzhiyun #define WM8995_AIF1DAC2_VU_SHIFT 8 /* AIF1DAC2_VU */ 2098*4882a593Smuzhiyun #define WM8995_AIF1DAC2_VU_WIDTH 1 /* AIF1DAC2_VU */ 2099*4882a593Smuzhiyun #define WM8995_AIF1DAC2R_VOL_MASK 0x00FF /* AIF1DAC2R_VOL - [7:0] */ 2100*4882a593Smuzhiyun #define WM8995_AIF1DAC2R_VOL_SHIFT 0 /* AIF1DAC2R_VOL - [7:0] */ 2101*4882a593Smuzhiyun #define WM8995_AIF1DAC2R_VOL_WIDTH 8 /* AIF1DAC2R_VOL - [7:0] */ 2102*4882a593Smuzhiyun 2103*4882a593Smuzhiyun /* 2104*4882a593Smuzhiyun * R1040 (0x410) - AIF1 ADC1 Filters 2105*4882a593Smuzhiyun */ 2106*4882a593Smuzhiyun #define WM8995_AIF1ADC_4FS 0x8000 /* AIF1ADC_4FS */ 2107*4882a593Smuzhiyun #define WM8995_AIF1ADC_4FS_MASK 0x8000 /* AIF1ADC_4FS */ 2108*4882a593Smuzhiyun #define WM8995_AIF1ADC_4FS_SHIFT 15 /* AIF1ADC_4FS */ 2109*4882a593Smuzhiyun #define WM8995_AIF1ADC_4FS_WIDTH 1 /* AIF1ADC_4FS */ 2110*4882a593Smuzhiyun #define WM8995_AIF1ADC1L_HPF 0x1000 /* AIF1ADC1L_HPF */ 2111*4882a593Smuzhiyun #define WM8995_AIF1ADC1L_HPF_MASK 0x1000 /* AIF1ADC1L_HPF */ 2112*4882a593Smuzhiyun #define WM8995_AIF1ADC1L_HPF_SHIFT 12 /* AIF1ADC1L_HPF */ 2113*4882a593Smuzhiyun #define WM8995_AIF1ADC1L_HPF_WIDTH 1 /* AIF1ADC1L_HPF */ 2114*4882a593Smuzhiyun #define WM8995_AIF1ADC1R_HPF 0x0800 /* AIF1ADC1R_HPF */ 2115*4882a593Smuzhiyun #define WM8995_AIF1ADC1R_HPF_MASK 0x0800 /* AIF1ADC1R_HPF */ 2116*4882a593Smuzhiyun #define WM8995_AIF1ADC1R_HPF_SHIFT 11 /* AIF1ADC1R_HPF */ 2117*4882a593Smuzhiyun #define WM8995_AIF1ADC1R_HPF_WIDTH 1 /* AIF1ADC1R_HPF */ 2118*4882a593Smuzhiyun #define WM8995_AIF1ADC1_HPF_MODE 0x0008 /* AIF1ADC1_HPF_MODE */ 2119*4882a593Smuzhiyun #define WM8995_AIF1ADC1_HPF_MODE_MASK 0x0008 /* AIF1ADC1_HPF_MODE */ 2120*4882a593Smuzhiyun #define WM8995_AIF1ADC1_HPF_MODE_SHIFT 3 /* AIF1ADC1_HPF_MODE */ 2121*4882a593Smuzhiyun #define WM8995_AIF1ADC1_HPF_MODE_WIDTH 1 /* AIF1ADC1_HPF_MODE */ 2122*4882a593Smuzhiyun #define WM8995_AIF1ADC1_HPF_CUT_MASK 0x0007 /* AIF1ADC1_HPF_CUT - [2:0] */ 2123*4882a593Smuzhiyun #define WM8995_AIF1ADC1_HPF_CUT_SHIFT 0 /* AIF1ADC1_HPF_CUT - [2:0] */ 2124*4882a593Smuzhiyun #define WM8995_AIF1ADC1_HPF_CUT_WIDTH 3 /* AIF1ADC1_HPF_CUT - [2:0] */ 2125*4882a593Smuzhiyun 2126*4882a593Smuzhiyun /* 2127*4882a593Smuzhiyun * R1041 (0x411) - AIF1 ADC2 Filters 2128*4882a593Smuzhiyun */ 2129*4882a593Smuzhiyun #define WM8995_AIF1ADC2L_HPF 0x1000 /* AIF1ADC2L_HPF */ 2130*4882a593Smuzhiyun #define WM8995_AIF1ADC2L_HPF_MASK 0x1000 /* AIF1ADC2L_HPF */ 2131*4882a593Smuzhiyun #define WM8995_AIF1ADC2L_HPF_SHIFT 12 /* AIF1ADC2L_HPF */ 2132*4882a593Smuzhiyun #define WM8995_AIF1ADC2L_HPF_WIDTH 1 /* AIF1ADC2L_HPF */ 2133*4882a593Smuzhiyun #define WM8995_AIF1ADC2R_HPF 0x0800 /* AIF1ADC2R_HPF */ 2134*4882a593Smuzhiyun #define WM8995_AIF1ADC2R_HPF_MASK 0x0800 /* AIF1ADC2R_HPF */ 2135*4882a593Smuzhiyun #define WM8995_AIF1ADC2R_HPF_SHIFT 11 /* AIF1ADC2R_HPF */ 2136*4882a593Smuzhiyun #define WM8995_AIF1ADC2R_HPF_WIDTH 1 /* AIF1ADC2R_HPF */ 2137*4882a593Smuzhiyun #define WM8995_AIF1ADC2_HPF_MODE 0x0008 /* AIF1ADC2_HPF_MODE */ 2138*4882a593Smuzhiyun #define WM8995_AIF1ADC2_HPF_MODE_MASK 0x0008 /* AIF1ADC2_HPF_MODE */ 2139*4882a593Smuzhiyun #define WM8995_AIF1ADC2_HPF_MODE_SHIFT 3 /* AIF1ADC2_HPF_MODE */ 2140*4882a593Smuzhiyun #define WM8995_AIF1ADC2_HPF_MODE_WIDTH 1 /* AIF1ADC2_HPF_MODE */ 2141*4882a593Smuzhiyun #define WM8995_AIF1ADC2_HPF_CUT_MASK 0x0007 /* AIF1ADC2_HPF_CUT - [2:0] */ 2142*4882a593Smuzhiyun #define WM8995_AIF1ADC2_HPF_CUT_SHIFT 0 /* AIF1ADC2_HPF_CUT - [2:0] */ 2143*4882a593Smuzhiyun #define WM8995_AIF1ADC2_HPF_CUT_WIDTH 3 /* AIF1ADC2_HPF_CUT - [2:0] */ 2144*4882a593Smuzhiyun 2145*4882a593Smuzhiyun /* 2146*4882a593Smuzhiyun * R1056 (0x420) - AIF1 DAC1 Filters (1) 2147*4882a593Smuzhiyun */ 2148*4882a593Smuzhiyun #define WM8995_AIF1DAC1_MUTE 0x0200 /* AIF1DAC1_MUTE */ 2149*4882a593Smuzhiyun #define WM8995_AIF1DAC1_MUTE_MASK 0x0200 /* AIF1DAC1_MUTE */ 2150*4882a593Smuzhiyun #define WM8995_AIF1DAC1_MUTE_SHIFT 9 /* AIF1DAC1_MUTE */ 2151*4882a593Smuzhiyun #define WM8995_AIF1DAC1_MUTE_WIDTH 1 /* AIF1DAC1_MUTE */ 2152*4882a593Smuzhiyun #define WM8995_AIF1DAC1_MONO 0x0080 /* AIF1DAC1_MONO */ 2153*4882a593Smuzhiyun #define WM8995_AIF1DAC1_MONO_MASK 0x0080 /* AIF1DAC1_MONO */ 2154*4882a593Smuzhiyun #define WM8995_AIF1DAC1_MONO_SHIFT 7 /* AIF1DAC1_MONO */ 2155*4882a593Smuzhiyun #define WM8995_AIF1DAC1_MONO_WIDTH 1 /* AIF1DAC1_MONO */ 2156*4882a593Smuzhiyun #define WM8995_AIF1DAC1_MUTERATE 0x0020 /* AIF1DAC1_MUTERATE */ 2157*4882a593Smuzhiyun #define WM8995_AIF1DAC1_MUTERATE_MASK 0x0020 /* AIF1DAC1_MUTERATE */ 2158*4882a593Smuzhiyun #define WM8995_AIF1DAC1_MUTERATE_SHIFT 5 /* AIF1DAC1_MUTERATE */ 2159*4882a593Smuzhiyun #define WM8995_AIF1DAC1_MUTERATE_WIDTH 1 /* AIF1DAC1_MUTERATE */ 2160*4882a593Smuzhiyun #define WM8995_AIF1DAC1_UNMUTE_RAMP 0x0010 /* AIF1DAC1_UNMUTE_RAMP */ 2161*4882a593Smuzhiyun #define WM8995_AIF1DAC1_UNMUTE_RAMP_MASK 0x0010 /* AIF1DAC1_UNMUTE_RAMP */ 2162*4882a593Smuzhiyun #define WM8995_AIF1DAC1_UNMUTE_RAMP_SHIFT 4 /* AIF1DAC1_UNMUTE_RAMP */ 2163*4882a593Smuzhiyun #define WM8995_AIF1DAC1_UNMUTE_RAMP_WIDTH 1 /* AIF1DAC1_UNMUTE_RAMP */ 2164*4882a593Smuzhiyun #define WM8995_AIF1DAC1_DEEMP_MASK 0x0006 /* AIF1DAC1_DEEMP - [2:1] */ 2165*4882a593Smuzhiyun #define WM8995_AIF1DAC1_DEEMP_SHIFT 1 /* AIF1DAC1_DEEMP - [2:1] */ 2166*4882a593Smuzhiyun #define WM8995_AIF1DAC1_DEEMP_WIDTH 2 /* AIF1DAC1_DEEMP - [2:1] */ 2167*4882a593Smuzhiyun 2168*4882a593Smuzhiyun /* 2169*4882a593Smuzhiyun * R1057 (0x421) - AIF1 DAC1 Filters (2) 2170*4882a593Smuzhiyun */ 2171*4882a593Smuzhiyun #define WM8995_AIF1DAC1_3D_GAIN_MASK 0x3E00 /* AIF1DAC1_3D_GAIN - [13:9] */ 2172*4882a593Smuzhiyun #define WM8995_AIF1DAC1_3D_GAIN_SHIFT 9 /* AIF1DAC1_3D_GAIN - [13:9] */ 2173*4882a593Smuzhiyun #define WM8995_AIF1DAC1_3D_GAIN_WIDTH 5 /* AIF1DAC1_3D_GAIN - [13:9] */ 2174*4882a593Smuzhiyun #define WM8995_AIF1DAC1_3D_ENA 0x0100 /* AIF1DAC1_3D_ENA */ 2175*4882a593Smuzhiyun #define WM8995_AIF1DAC1_3D_ENA_MASK 0x0100 /* AIF1DAC1_3D_ENA */ 2176*4882a593Smuzhiyun #define WM8995_AIF1DAC1_3D_ENA_SHIFT 8 /* AIF1DAC1_3D_ENA */ 2177*4882a593Smuzhiyun #define WM8995_AIF1DAC1_3D_ENA_WIDTH 1 /* AIF1DAC1_3D_ENA */ 2178*4882a593Smuzhiyun 2179*4882a593Smuzhiyun /* 2180*4882a593Smuzhiyun * R1058 (0x422) - AIF1 DAC2 Filters (1) 2181*4882a593Smuzhiyun */ 2182*4882a593Smuzhiyun #define WM8995_AIF1DAC2_MUTE 0x0200 /* AIF1DAC2_MUTE */ 2183*4882a593Smuzhiyun #define WM8995_AIF1DAC2_MUTE_MASK 0x0200 /* AIF1DAC2_MUTE */ 2184*4882a593Smuzhiyun #define WM8995_AIF1DAC2_MUTE_SHIFT 9 /* AIF1DAC2_MUTE */ 2185*4882a593Smuzhiyun #define WM8995_AIF1DAC2_MUTE_WIDTH 1 /* AIF1DAC2_MUTE */ 2186*4882a593Smuzhiyun #define WM8995_AIF1DAC2_MONO 0x0080 /* AIF1DAC2_MONO */ 2187*4882a593Smuzhiyun #define WM8995_AIF1DAC2_MONO_MASK 0x0080 /* AIF1DAC2_MONO */ 2188*4882a593Smuzhiyun #define WM8995_AIF1DAC2_MONO_SHIFT 7 /* AIF1DAC2_MONO */ 2189*4882a593Smuzhiyun #define WM8995_AIF1DAC2_MONO_WIDTH 1 /* AIF1DAC2_MONO */ 2190*4882a593Smuzhiyun #define WM8995_AIF1DAC2_MUTERATE 0x0020 /* AIF1DAC2_MUTERATE */ 2191*4882a593Smuzhiyun #define WM8995_AIF1DAC2_MUTERATE_MASK 0x0020 /* AIF1DAC2_MUTERATE */ 2192*4882a593Smuzhiyun #define WM8995_AIF1DAC2_MUTERATE_SHIFT 5 /* AIF1DAC2_MUTERATE */ 2193*4882a593Smuzhiyun #define WM8995_AIF1DAC2_MUTERATE_WIDTH 1 /* AIF1DAC2_MUTERATE */ 2194*4882a593Smuzhiyun #define WM8995_AIF1DAC2_UNMUTE_RAMP 0x0010 /* AIF1DAC2_UNMUTE_RAMP */ 2195*4882a593Smuzhiyun #define WM8995_AIF1DAC2_UNMUTE_RAMP_MASK 0x0010 /* AIF1DAC2_UNMUTE_RAMP */ 2196*4882a593Smuzhiyun #define WM8995_AIF1DAC2_UNMUTE_RAMP_SHIFT 4 /* AIF1DAC2_UNMUTE_RAMP */ 2197*4882a593Smuzhiyun #define WM8995_AIF1DAC2_UNMUTE_RAMP_WIDTH 1 /* AIF1DAC2_UNMUTE_RAMP */ 2198*4882a593Smuzhiyun #define WM8995_AIF1DAC2_DEEMP_MASK 0x0006 /* AIF1DAC2_DEEMP - [2:1] */ 2199*4882a593Smuzhiyun #define WM8995_AIF1DAC2_DEEMP_SHIFT 1 /* AIF1DAC2_DEEMP - [2:1] */ 2200*4882a593Smuzhiyun #define WM8995_AIF1DAC2_DEEMP_WIDTH 2 /* AIF1DAC2_DEEMP - [2:1] */ 2201*4882a593Smuzhiyun 2202*4882a593Smuzhiyun /* 2203*4882a593Smuzhiyun * R1059 (0x423) - AIF1 DAC2 Filters (2) 2204*4882a593Smuzhiyun */ 2205*4882a593Smuzhiyun #define WM8995_AIF1DAC2_3D_GAIN_MASK 0x3E00 /* AIF1DAC2_3D_GAIN - [13:9] */ 2206*4882a593Smuzhiyun #define WM8995_AIF1DAC2_3D_GAIN_SHIFT 9 /* AIF1DAC2_3D_GAIN - [13:9] */ 2207*4882a593Smuzhiyun #define WM8995_AIF1DAC2_3D_GAIN_WIDTH 5 /* AIF1DAC2_3D_GAIN - [13:9] */ 2208*4882a593Smuzhiyun #define WM8995_AIF1DAC2_3D_ENA 0x0100 /* AIF1DAC2_3D_ENA */ 2209*4882a593Smuzhiyun #define WM8995_AIF1DAC2_3D_ENA_MASK 0x0100 /* AIF1DAC2_3D_ENA */ 2210*4882a593Smuzhiyun #define WM8995_AIF1DAC2_3D_ENA_SHIFT 8 /* AIF1DAC2_3D_ENA */ 2211*4882a593Smuzhiyun #define WM8995_AIF1DAC2_3D_ENA_WIDTH 1 /* AIF1DAC2_3D_ENA */ 2212*4882a593Smuzhiyun 2213*4882a593Smuzhiyun /* 2214*4882a593Smuzhiyun * R1088 (0x440) - AIF1 DRC1 (1) 2215*4882a593Smuzhiyun */ 2216*4882a593Smuzhiyun #define WM8995_AIF1DRC1_SIG_DET_RMS_MASK 0xF800 /* AIF1DRC1_SIG_DET_RMS - [15:11] */ 2217*4882a593Smuzhiyun #define WM8995_AIF1DRC1_SIG_DET_RMS_SHIFT 11 /* AIF1DRC1_SIG_DET_RMS - [15:11] */ 2218*4882a593Smuzhiyun #define WM8995_AIF1DRC1_SIG_DET_RMS_WIDTH 5 /* AIF1DRC1_SIG_DET_RMS - [15:11] */ 2219*4882a593Smuzhiyun #define WM8995_AIF1DRC1_SIG_DET_PK_MASK 0x0600 /* AIF1DRC1_SIG_DET_PK - [10:9] */ 2220*4882a593Smuzhiyun #define WM8995_AIF1DRC1_SIG_DET_PK_SHIFT 9 /* AIF1DRC1_SIG_DET_PK - [10:9] */ 2221*4882a593Smuzhiyun #define WM8995_AIF1DRC1_SIG_DET_PK_WIDTH 2 /* AIF1DRC1_SIG_DET_PK - [10:9] */ 2222*4882a593Smuzhiyun #define WM8995_AIF1DRC1_NG_ENA 0x0100 /* AIF1DRC1_NG_ENA */ 2223*4882a593Smuzhiyun #define WM8995_AIF1DRC1_NG_ENA_MASK 0x0100 /* AIF1DRC1_NG_ENA */ 2224*4882a593Smuzhiyun #define WM8995_AIF1DRC1_NG_ENA_SHIFT 8 /* AIF1DRC1_NG_ENA */ 2225*4882a593Smuzhiyun #define WM8995_AIF1DRC1_NG_ENA_WIDTH 1 /* AIF1DRC1_NG_ENA */ 2226*4882a593Smuzhiyun #define WM8995_AIF1DRC1_SIG_DET_MODE 0x0080 /* AIF1DRC1_SIG_DET_MODE */ 2227*4882a593Smuzhiyun #define WM8995_AIF1DRC1_SIG_DET_MODE_MASK 0x0080 /* AIF1DRC1_SIG_DET_MODE */ 2228*4882a593Smuzhiyun #define WM8995_AIF1DRC1_SIG_DET_MODE_SHIFT 7 /* AIF1DRC1_SIG_DET_MODE */ 2229*4882a593Smuzhiyun #define WM8995_AIF1DRC1_SIG_DET_MODE_WIDTH 1 /* AIF1DRC1_SIG_DET_MODE */ 2230*4882a593Smuzhiyun #define WM8995_AIF1DRC1_SIG_DET 0x0040 /* AIF1DRC1_SIG_DET */ 2231*4882a593Smuzhiyun #define WM8995_AIF1DRC1_SIG_DET_MASK 0x0040 /* AIF1DRC1_SIG_DET */ 2232*4882a593Smuzhiyun #define WM8995_AIF1DRC1_SIG_DET_SHIFT 6 /* AIF1DRC1_SIG_DET */ 2233*4882a593Smuzhiyun #define WM8995_AIF1DRC1_SIG_DET_WIDTH 1 /* AIF1DRC1_SIG_DET */ 2234*4882a593Smuzhiyun #define WM8995_AIF1DRC1_KNEE2_OP_ENA 0x0020 /* AIF1DRC1_KNEE2_OP_ENA */ 2235*4882a593Smuzhiyun #define WM8995_AIF1DRC1_KNEE2_OP_ENA_MASK 0x0020 /* AIF1DRC1_KNEE2_OP_ENA */ 2236*4882a593Smuzhiyun #define WM8995_AIF1DRC1_KNEE2_OP_ENA_SHIFT 5 /* AIF1DRC1_KNEE2_OP_ENA */ 2237*4882a593Smuzhiyun #define WM8995_AIF1DRC1_KNEE2_OP_ENA_WIDTH 1 /* AIF1DRC1_KNEE2_OP_ENA */ 2238*4882a593Smuzhiyun #define WM8995_AIF1DRC1_QR 0x0010 /* AIF1DRC1_QR */ 2239*4882a593Smuzhiyun #define WM8995_AIF1DRC1_QR_MASK 0x0010 /* AIF1DRC1_QR */ 2240*4882a593Smuzhiyun #define WM8995_AIF1DRC1_QR_SHIFT 4 /* AIF1DRC1_QR */ 2241*4882a593Smuzhiyun #define WM8995_AIF1DRC1_QR_WIDTH 1 /* AIF1DRC1_QR */ 2242*4882a593Smuzhiyun #define WM8995_AIF1DRC1_ANTICLIP 0x0008 /* AIF1DRC1_ANTICLIP */ 2243*4882a593Smuzhiyun #define WM8995_AIF1DRC1_ANTICLIP_MASK 0x0008 /* AIF1DRC1_ANTICLIP */ 2244*4882a593Smuzhiyun #define WM8995_AIF1DRC1_ANTICLIP_SHIFT 3 /* AIF1DRC1_ANTICLIP */ 2245*4882a593Smuzhiyun #define WM8995_AIF1DRC1_ANTICLIP_WIDTH 1 /* AIF1DRC1_ANTICLIP */ 2246*4882a593Smuzhiyun #define WM8995_AIF1DAC1_DRC_ENA 0x0004 /* AIF1DAC1_DRC_ENA */ 2247*4882a593Smuzhiyun #define WM8995_AIF1DAC1_DRC_ENA_MASK 0x0004 /* AIF1DAC1_DRC_ENA */ 2248*4882a593Smuzhiyun #define WM8995_AIF1DAC1_DRC_ENA_SHIFT 2 /* AIF1DAC1_DRC_ENA */ 2249*4882a593Smuzhiyun #define WM8995_AIF1DAC1_DRC_ENA_WIDTH 1 /* AIF1DAC1_DRC_ENA */ 2250*4882a593Smuzhiyun #define WM8995_AIF1ADC1L_DRC_ENA 0x0002 /* AIF1ADC1L_DRC_ENA */ 2251*4882a593Smuzhiyun #define WM8995_AIF1ADC1L_DRC_ENA_MASK 0x0002 /* AIF1ADC1L_DRC_ENA */ 2252*4882a593Smuzhiyun #define WM8995_AIF1ADC1L_DRC_ENA_SHIFT 1 /* AIF1ADC1L_DRC_ENA */ 2253*4882a593Smuzhiyun #define WM8995_AIF1ADC1L_DRC_ENA_WIDTH 1 /* AIF1ADC1L_DRC_ENA */ 2254*4882a593Smuzhiyun #define WM8995_AIF1ADC1R_DRC_ENA 0x0001 /* AIF1ADC1R_DRC_ENA */ 2255*4882a593Smuzhiyun #define WM8995_AIF1ADC1R_DRC_ENA_MASK 0x0001 /* AIF1ADC1R_DRC_ENA */ 2256*4882a593Smuzhiyun #define WM8995_AIF1ADC1R_DRC_ENA_SHIFT 0 /* AIF1ADC1R_DRC_ENA */ 2257*4882a593Smuzhiyun #define WM8995_AIF1ADC1R_DRC_ENA_WIDTH 1 /* AIF1ADC1R_DRC_ENA */ 2258*4882a593Smuzhiyun 2259*4882a593Smuzhiyun /* 2260*4882a593Smuzhiyun * R1089 (0x441) - AIF1 DRC1 (2) 2261*4882a593Smuzhiyun */ 2262*4882a593Smuzhiyun #define WM8995_AIF1DRC1_ATK_MASK 0x1E00 /* AIF1DRC1_ATK - [12:9] */ 2263*4882a593Smuzhiyun #define WM8995_AIF1DRC1_ATK_SHIFT 9 /* AIF1DRC1_ATK - [12:9] */ 2264*4882a593Smuzhiyun #define WM8995_AIF1DRC1_ATK_WIDTH 4 /* AIF1DRC1_ATK - [12:9] */ 2265*4882a593Smuzhiyun #define WM8995_AIF1DRC1_DCY_MASK 0x01E0 /* AIF1DRC1_DCY - [8:5] */ 2266*4882a593Smuzhiyun #define WM8995_AIF1DRC1_DCY_SHIFT 5 /* AIF1DRC1_DCY - [8:5] */ 2267*4882a593Smuzhiyun #define WM8995_AIF1DRC1_DCY_WIDTH 4 /* AIF1DRC1_DCY - [8:5] */ 2268*4882a593Smuzhiyun #define WM8995_AIF1DRC1_MINGAIN_MASK 0x001C /* AIF1DRC1_MINGAIN - [4:2] */ 2269*4882a593Smuzhiyun #define WM8995_AIF1DRC1_MINGAIN_SHIFT 2 /* AIF1DRC1_MINGAIN - [4:2] */ 2270*4882a593Smuzhiyun #define WM8995_AIF1DRC1_MINGAIN_WIDTH 3 /* AIF1DRC1_MINGAIN - [4:2] */ 2271*4882a593Smuzhiyun #define WM8995_AIF1DRC1_MAXGAIN_MASK 0x0003 /* AIF1DRC1_MAXGAIN - [1:0] */ 2272*4882a593Smuzhiyun #define WM8995_AIF1DRC1_MAXGAIN_SHIFT 0 /* AIF1DRC1_MAXGAIN - [1:0] */ 2273*4882a593Smuzhiyun #define WM8995_AIF1DRC1_MAXGAIN_WIDTH 2 /* AIF1DRC1_MAXGAIN - [1:0] */ 2274*4882a593Smuzhiyun 2275*4882a593Smuzhiyun /* 2276*4882a593Smuzhiyun * R1090 (0x442) - AIF1 DRC1 (3) 2277*4882a593Smuzhiyun */ 2278*4882a593Smuzhiyun #define WM8995_AIF1DRC1_NG_MINGAIN_MASK 0xF000 /* AIF1DRC1_NG_MINGAIN - [15:12] */ 2279*4882a593Smuzhiyun #define WM8995_AIF1DRC1_NG_MINGAIN_SHIFT 12 /* AIF1DRC1_NG_MINGAIN - [15:12] */ 2280*4882a593Smuzhiyun #define WM8995_AIF1DRC1_NG_MINGAIN_WIDTH 4 /* AIF1DRC1_NG_MINGAIN - [15:12] */ 2281*4882a593Smuzhiyun #define WM8995_AIF1DRC1_NG_EXP_MASK 0x0C00 /* AIF1DRC1_NG_EXP - [11:10] */ 2282*4882a593Smuzhiyun #define WM8995_AIF1DRC1_NG_EXP_SHIFT 10 /* AIF1DRC1_NG_EXP - [11:10] */ 2283*4882a593Smuzhiyun #define WM8995_AIF1DRC1_NG_EXP_WIDTH 2 /* AIF1DRC1_NG_EXP - [11:10] */ 2284*4882a593Smuzhiyun #define WM8995_AIF1DRC1_QR_THR_MASK 0x0300 /* AIF1DRC1_QR_THR - [9:8] */ 2285*4882a593Smuzhiyun #define WM8995_AIF1DRC1_QR_THR_SHIFT 8 /* AIF1DRC1_QR_THR - [9:8] */ 2286*4882a593Smuzhiyun #define WM8995_AIF1DRC1_QR_THR_WIDTH 2 /* AIF1DRC1_QR_THR - [9:8] */ 2287*4882a593Smuzhiyun #define WM8995_AIF1DRC1_QR_DCY_MASK 0x00C0 /* AIF1DRC1_QR_DCY - [7:6] */ 2288*4882a593Smuzhiyun #define WM8995_AIF1DRC1_QR_DCY_SHIFT 6 /* AIF1DRC1_QR_DCY - [7:6] */ 2289*4882a593Smuzhiyun #define WM8995_AIF1DRC1_QR_DCY_WIDTH 2 /* AIF1DRC1_QR_DCY - [7:6] */ 2290*4882a593Smuzhiyun #define WM8995_AIF1DRC1_HI_COMP_MASK 0x0038 /* AIF1DRC1_HI_COMP - [5:3] */ 2291*4882a593Smuzhiyun #define WM8995_AIF1DRC1_HI_COMP_SHIFT 3 /* AIF1DRC1_HI_COMP - [5:3] */ 2292*4882a593Smuzhiyun #define WM8995_AIF1DRC1_HI_COMP_WIDTH 3 /* AIF1DRC1_HI_COMP - [5:3] */ 2293*4882a593Smuzhiyun #define WM8995_AIF1DRC1_LO_COMP_MASK 0x0007 /* AIF1DRC1_LO_COMP - [2:0] */ 2294*4882a593Smuzhiyun #define WM8995_AIF1DRC1_LO_COMP_SHIFT 0 /* AIF1DRC1_LO_COMP - [2:0] */ 2295*4882a593Smuzhiyun #define WM8995_AIF1DRC1_LO_COMP_WIDTH 3 /* AIF1DRC1_LO_COMP - [2:0] */ 2296*4882a593Smuzhiyun 2297*4882a593Smuzhiyun /* 2298*4882a593Smuzhiyun * R1091 (0x443) - AIF1 DRC1 (4) 2299*4882a593Smuzhiyun */ 2300*4882a593Smuzhiyun #define WM8995_AIF1DRC1_KNEE_IP_MASK 0x07E0 /* AIF1DRC1_KNEE_IP - [10:5] */ 2301*4882a593Smuzhiyun #define WM8995_AIF1DRC1_KNEE_IP_SHIFT 5 /* AIF1DRC1_KNEE_IP - [10:5] */ 2302*4882a593Smuzhiyun #define WM8995_AIF1DRC1_KNEE_IP_WIDTH 6 /* AIF1DRC1_KNEE_IP - [10:5] */ 2303*4882a593Smuzhiyun #define WM8995_AIF1DRC1_KNEE_OP_MASK 0x001F /* AIF1DRC1_KNEE_OP - [4:0] */ 2304*4882a593Smuzhiyun #define WM8995_AIF1DRC1_KNEE_OP_SHIFT 0 /* AIF1DRC1_KNEE_OP - [4:0] */ 2305*4882a593Smuzhiyun #define WM8995_AIF1DRC1_KNEE_OP_WIDTH 5 /* AIF1DRC1_KNEE_OP - [4:0] */ 2306*4882a593Smuzhiyun 2307*4882a593Smuzhiyun /* 2308*4882a593Smuzhiyun * R1092 (0x444) - AIF1 DRC1 (5) 2309*4882a593Smuzhiyun */ 2310*4882a593Smuzhiyun #define WM8995_AIF1DRC1_KNEE2_IP_MASK 0x03E0 /* AIF1DRC1_KNEE2_IP - [9:5] */ 2311*4882a593Smuzhiyun #define WM8995_AIF1DRC1_KNEE2_IP_SHIFT 5 /* AIF1DRC1_KNEE2_IP - [9:5] */ 2312*4882a593Smuzhiyun #define WM8995_AIF1DRC1_KNEE2_IP_WIDTH 5 /* AIF1DRC1_KNEE2_IP - [9:5] */ 2313*4882a593Smuzhiyun #define WM8995_AIF1DRC1_KNEE2_OP_MASK 0x001F /* AIF1DRC1_KNEE2_OP - [4:0] */ 2314*4882a593Smuzhiyun #define WM8995_AIF1DRC1_KNEE2_OP_SHIFT 0 /* AIF1DRC1_KNEE2_OP - [4:0] */ 2315*4882a593Smuzhiyun #define WM8995_AIF1DRC1_KNEE2_OP_WIDTH 5 /* AIF1DRC1_KNEE2_OP - [4:0] */ 2316*4882a593Smuzhiyun 2317*4882a593Smuzhiyun /* 2318*4882a593Smuzhiyun * R1104 (0x450) - AIF1 DRC2 (1) 2319*4882a593Smuzhiyun */ 2320*4882a593Smuzhiyun #define WM8995_AIF1DRC2_SIG_DET_RMS_MASK 0xF800 /* AIF1DRC2_SIG_DET_RMS - [15:11] */ 2321*4882a593Smuzhiyun #define WM8995_AIF1DRC2_SIG_DET_RMS_SHIFT 11 /* AIF1DRC2_SIG_DET_RMS - [15:11] */ 2322*4882a593Smuzhiyun #define WM8995_AIF1DRC2_SIG_DET_RMS_WIDTH 5 /* AIF1DRC2_SIG_DET_RMS - [15:11] */ 2323*4882a593Smuzhiyun #define WM8995_AIF1DRC2_SIG_DET_PK_MASK 0x0600 /* AIF1DRC2_SIG_DET_PK - [10:9] */ 2324*4882a593Smuzhiyun #define WM8995_AIF1DRC2_SIG_DET_PK_SHIFT 9 /* AIF1DRC2_SIG_DET_PK - [10:9] */ 2325*4882a593Smuzhiyun #define WM8995_AIF1DRC2_SIG_DET_PK_WIDTH 2 /* AIF1DRC2_SIG_DET_PK - [10:9] */ 2326*4882a593Smuzhiyun #define WM8995_AIF1DRC2_NG_ENA 0x0100 /* AIF1DRC2_NG_ENA */ 2327*4882a593Smuzhiyun #define WM8995_AIF1DRC2_NG_ENA_MASK 0x0100 /* AIF1DRC2_NG_ENA */ 2328*4882a593Smuzhiyun #define WM8995_AIF1DRC2_NG_ENA_SHIFT 8 /* AIF1DRC2_NG_ENA */ 2329*4882a593Smuzhiyun #define WM8995_AIF1DRC2_NG_ENA_WIDTH 1 /* AIF1DRC2_NG_ENA */ 2330*4882a593Smuzhiyun #define WM8995_AIF1DRC2_SIG_DET_MODE 0x0080 /* AIF1DRC2_SIG_DET_MODE */ 2331*4882a593Smuzhiyun #define WM8995_AIF1DRC2_SIG_DET_MODE_MASK 0x0080 /* AIF1DRC2_SIG_DET_MODE */ 2332*4882a593Smuzhiyun #define WM8995_AIF1DRC2_SIG_DET_MODE_SHIFT 7 /* AIF1DRC2_SIG_DET_MODE */ 2333*4882a593Smuzhiyun #define WM8995_AIF1DRC2_SIG_DET_MODE_WIDTH 1 /* AIF1DRC2_SIG_DET_MODE */ 2334*4882a593Smuzhiyun #define WM8995_AIF1DRC2_SIG_DET 0x0040 /* AIF1DRC2_SIG_DET */ 2335*4882a593Smuzhiyun #define WM8995_AIF1DRC2_SIG_DET_MASK 0x0040 /* AIF1DRC2_SIG_DET */ 2336*4882a593Smuzhiyun #define WM8995_AIF1DRC2_SIG_DET_SHIFT 6 /* AIF1DRC2_SIG_DET */ 2337*4882a593Smuzhiyun #define WM8995_AIF1DRC2_SIG_DET_WIDTH 1 /* AIF1DRC2_SIG_DET */ 2338*4882a593Smuzhiyun #define WM8995_AIF1DRC2_KNEE2_OP_ENA 0x0020 /* AIF1DRC2_KNEE2_OP_ENA */ 2339*4882a593Smuzhiyun #define WM8995_AIF1DRC2_KNEE2_OP_ENA_MASK 0x0020 /* AIF1DRC2_KNEE2_OP_ENA */ 2340*4882a593Smuzhiyun #define WM8995_AIF1DRC2_KNEE2_OP_ENA_SHIFT 5 /* AIF1DRC2_KNEE2_OP_ENA */ 2341*4882a593Smuzhiyun #define WM8995_AIF1DRC2_KNEE2_OP_ENA_WIDTH 1 /* AIF1DRC2_KNEE2_OP_ENA */ 2342*4882a593Smuzhiyun #define WM8995_AIF1DRC2_QR 0x0010 /* AIF1DRC2_QR */ 2343*4882a593Smuzhiyun #define WM8995_AIF1DRC2_QR_MASK 0x0010 /* AIF1DRC2_QR */ 2344*4882a593Smuzhiyun #define WM8995_AIF1DRC2_QR_SHIFT 4 /* AIF1DRC2_QR */ 2345*4882a593Smuzhiyun #define WM8995_AIF1DRC2_QR_WIDTH 1 /* AIF1DRC2_QR */ 2346*4882a593Smuzhiyun #define WM8995_AIF1DRC2_ANTICLIP 0x0008 /* AIF1DRC2_ANTICLIP */ 2347*4882a593Smuzhiyun #define WM8995_AIF1DRC2_ANTICLIP_MASK 0x0008 /* AIF1DRC2_ANTICLIP */ 2348*4882a593Smuzhiyun #define WM8995_AIF1DRC2_ANTICLIP_SHIFT 3 /* AIF1DRC2_ANTICLIP */ 2349*4882a593Smuzhiyun #define WM8995_AIF1DRC2_ANTICLIP_WIDTH 1 /* AIF1DRC2_ANTICLIP */ 2350*4882a593Smuzhiyun #define WM8995_AIF1DAC2_DRC_ENA 0x0004 /* AIF1DAC2_DRC_ENA */ 2351*4882a593Smuzhiyun #define WM8995_AIF1DAC2_DRC_ENA_MASK 0x0004 /* AIF1DAC2_DRC_ENA */ 2352*4882a593Smuzhiyun #define WM8995_AIF1DAC2_DRC_ENA_SHIFT 2 /* AIF1DAC2_DRC_ENA */ 2353*4882a593Smuzhiyun #define WM8995_AIF1DAC2_DRC_ENA_WIDTH 1 /* AIF1DAC2_DRC_ENA */ 2354*4882a593Smuzhiyun #define WM8995_AIF1ADC2L_DRC_ENA 0x0002 /* AIF1ADC2L_DRC_ENA */ 2355*4882a593Smuzhiyun #define WM8995_AIF1ADC2L_DRC_ENA_MASK 0x0002 /* AIF1ADC2L_DRC_ENA */ 2356*4882a593Smuzhiyun #define WM8995_AIF1ADC2L_DRC_ENA_SHIFT 1 /* AIF1ADC2L_DRC_ENA */ 2357*4882a593Smuzhiyun #define WM8995_AIF1ADC2L_DRC_ENA_WIDTH 1 /* AIF1ADC2L_DRC_ENA */ 2358*4882a593Smuzhiyun #define WM8995_AIF1ADC2R_DRC_ENA 0x0001 /* AIF1ADC2R_DRC_ENA */ 2359*4882a593Smuzhiyun #define WM8995_AIF1ADC2R_DRC_ENA_MASK 0x0001 /* AIF1ADC2R_DRC_ENA */ 2360*4882a593Smuzhiyun #define WM8995_AIF1ADC2R_DRC_ENA_SHIFT 0 /* AIF1ADC2R_DRC_ENA */ 2361*4882a593Smuzhiyun #define WM8995_AIF1ADC2R_DRC_ENA_WIDTH 1 /* AIF1ADC2R_DRC_ENA */ 2362*4882a593Smuzhiyun 2363*4882a593Smuzhiyun /* 2364*4882a593Smuzhiyun * R1105 (0x451) - AIF1 DRC2 (2) 2365*4882a593Smuzhiyun */ 2366*4882a593Smuzhiyun #define WM8995_AIF1DRC2_ATK_MASK 0x1E00 /* AIF1DRC2_ATK - [12:9] */ 2367*4882a593Smuzhiyun #define WM8995_AIF1DRC2_ATK_SHIFT 9 /* AIF1DRC2_ATK - [12:9] */ 2368*4882a593Smuzhiyun #define WM8995_AIF1DRC2_ATK_WIDTH 4 /* AIF1DRC2_ATK - [12:9] */ 2369*4882a593Smuzhiyun #define WM8995_AIF1DRC2_DCY_MASK 0x01E0 /* AIF1DRC2_DCY - [8:5] */ 2370*4882a593Smuzhiyun #define WM8995_AIF1DRC2_DCY_SHIFT 5 /* AIF1DRC2_DCY - [8:5] */ 2371*4882a593Smuzhiyun #define WM8995_AIF1DRC2_DCY_WIDTH 4 /* AIF1DRC2_DCY - [8:5] */ 2372*4882a593Smuzhiyun #define WM8995_AIF1DRC2_MINGAIN_MASK 0x001C /* AIF1DRC2_MINGAIN - [4:2] */ 2373*4882a593Smuzhiyun #define WM8995_AIF1DRC2_MINGAIN_SHIFT 2 /* AIF1DRC2_MINGAIN - [4:2] */ 2374*4882a593Smuzhiyun #define WM8995_AIF1DRC2_MINGAIN_WIDTH 3 /* AIF1DRC2_MINGAIN - [4:2] */ 2375*4882a593Smuzhiyun #define WM8995_AIF1DRC2_MAXGAIN_MASK 0x0003 /* AIF1DRC2_MAXGAIN - [1:0] */ 2376*4882a593Smuzhiyun #define WM8995_AIF1DRC2_MAXGAIN_SHIFT 0 /* AIF1DRC2_MAXGAIN - [1:0] */ 2377*4882a593Smuzhiyun #define WM8995_AIF1DRC2_MAXGAIN_WIDTH 2 /* AIF1DRC2_MAXGAIN - [1:0] */ 2378*4882a593Smuzhiyun 2379*4882a593Smuzhiyun /* 2380*4882a593Smuzhiyun * R1106 (0x452) - AIF1 DRC2 (3) 2381*4882a593Smuzhiyun */ 2382*4882a593Smuzhiyun #define WM8995_AIF1DRC2_NG_MINGAIN_MASK 0xF000 /* AIF1DRC2_NG_MINGAIN - [15:12] */ 2383*4882a593Smuzhiyun #define WM8995_AIF1DRC2_NG_MINGAIN_SHIFT 12 /* AIF1DRC2_NG_MINGAIN - [15:12] */ 2384*4882a593Smuzhiyun #define WM8995_AIF1DRC2_NG_MINGAIN_WIDTH 4 /* AIF1DRC2_NG_MINGAIN - [15:12] */ 2385*4882a593Smuzhiyun #define WM8995_AIF1DRC2_NG_EXP_MASK 0x0C00 /* AIF1DRC2_NG_EXP - [11:10] */ 2386*4882a593Smuzhiyun #define WM8995_AIF1DRC2_NG_EXP_SHIFT 10 /* AIF1DRC2_NG_EXP - [11:10] */ 2387*4882a593Smuzhiyun #define WM8995_AIF1DRC2_NG_EXP_WIDTH 2 /* AIF1DRC2_NG_EXP - [11:10] */ 2388*4882a593Smuzhiyun #define WM8995_AIF1DRC2_QR_THR_MASK 0x0300 /* AIF1DRC2_QR_THR - [9:8] */ 2389*4882a593Smuzhiyun #define WM8995_AIF1DRC2_QR_THR_SHIFT 8 /* AIF1DRC2_QR_THR - [9:8] */ 2390*4882a593Smuzhiyun #define WM8995_AIF1DRC2_QR_THR_WIDTH 2 /* AIF1DRC2_QR_THR - [9:8] */ 2391*4882a593Smuzhiyun #define WM8995_AIF1DRC2_QR_DCY_MASK 0x00C0 /* AIF1DRC2_QR_DCY - [7:6] */ 2392*4882a593Smuzhiyun #define WM8995_AIF1DRC2_QR_DCY_SHIFT 6 /* AIF1DRC2_QR_DCY - [7:6] */ 2393*4882a593Smuzhiyun #define WM8995_AIF1DRC2_QR_DCY_WIDTH 2 /* AIF1DRC2_QR_DCY - [7:6] */ 2394*4882a593Smuzhiyun #define WM8995_AIF1DRC2_HI_COMP_MASK 0x0038 /* AIF1DRC2_HI_COMP - [5:3] */ 2395*4882a593Smuzhiyun #define WM8995_AIF1DRC2_HI_COMP_SHIFT 3 /* AIF1DRC2_HI_COMP - [5:3] */ 2396*4882a593Smuzhiyun #define WM8995_AIF1DRC2_HI_COMP_WIDTH 3 /* AIF1DRC2_HI_COMP - [5:3] */ 2397*4882a593Smuzhiyun #define WM8995_AIF1DRC2_LO_COMP_MASK 0x0007 /* AIF1DRC2_LO_COMP - [2:0] */ 2398*4882a593Smuzhiyun #define WM8995_AIF1DRC2_LO_COMP_SHIFT 0 /* AIF1DRC2_LO_COMP - [2:0] */ 2399*4882a593Smuzhiyun #define WM8995_AIF1DRC2_LO_COMP_WIDTH 3 /* AIF1DRC2_LO_COMP - [2:0] */ 2400*4882a593Smuzhiyun 2401*4882a593Smuzhiyun /* 2402*4882a593Smuzhiyun * R1107 (0x453) - AIF1 DRC2 (4) 2403*4882a593Smuzhiyun */ 2404*4882a593Smuzhiyun #define WM8995_AIF1DRC2_KNEE_IP_MASK 0x07E0 /* AIF1DRC2_KNEE_IP - [10:5] */ 2405*4882a593Smuzhiyun #define WM8995_AIF1DRC2_KNEE_IP_SHIFT 5 /* AIF1DRC2_KNEE_IP - [10:5] */ 2406*4882a593Smuzhiyun #define WM8995_AIF1DRC2_KNEE_IP_WIDTH 6 /* AIF1DRC2_KNEE_IP - [10:5] */ 2407*4882a593Smuzhiyun #define WM8995_AIF1DRC2_KNEE_OP_MASK 0x001F /* AIF1DRC2_KNEE_OP - [4:0] */ 2408*4882a593Smuzhiyun #define WM8995_AIF1DRC2_KNEE_OP_SHIFT 0 /* AIF1DRC2_KNEE_OP - [4:0] */ 2409*4882a593Smuzhiyun #define WM8995_AIF1DRC2_KNEE_OP_WIDTH 5 /* AIF1DRC2_KNEE_OP - [4:0] */ 2410*4882a593Smuzhiyun 2411*4882a593Smuzhiyun /* 2412*4882a593Smuzhiyun * R1108 (0x454) - AIF1 DRC2 (5) 2413*4882a593Smuzhiyun */ 2414*4882a593Smuzhiyun #define WM8995_AIF1DRC2_KNEE2_IP_MASK 0x03E0 /* AIF1DRC2_KNEE2_IP - [9:5] */ 2415*4882a593Smuzhiyun #define WM8995_AIF1DRC2_KNEE2_IP_SHIFT 5 /* AIF1DRC2_KNEE2_IP - [9:5] */ 2416*4882a593Smuzhiyun #define WM8995_AIF1DRC2_KNEE2_IP_WIDTH 5 /* AIF1DRC2_KNEE2_IP - [9:5] */ 2417*4882a593Smuzhiyun #define WM8995_AIF1DRC2_KNEE2_OP_MASK 0x001F /* AIF1DRC2_KNEE2_OP - [4:0] */ 2418*4882a593Smuzhiyun #define WM8995_AIF1DRC2_KNEE2_OP_SHIFT 0 /* AIF1DRC2_KNEE2_OP - [4:0] */ 2419*4882a593Smuzhiyun #define WM8995_AIF1DRC2_KNEE2_OP_WIDTH 5 /* AIF1DRC2_KNEE2_OP - [4:0] */ 2420*4882a593Smuzhiyun 2421*4882a593Smuzhiyun /* 2422*4882a593Smuzhiyun * R1152 (0x480) - AIF1 DAC1 EQ Gains (1) 2423*4882a593Smuzhiyun */ 2424*4882a593Smuzhiyun #define WM8995_AIF1DAC1_EQ_B1_GAIN_MASK 0xF800 /* AIF1DAC1_EQ_B1_GAIN - [15:11] */ 2425*4882a593Smuzhiyun #define WM8995_AIF1DAC1_EQ_B1_GAIN_SHIFT 11 /* AIF1DAC1_EQ_B1_GAIN - [15:11] */ 2426*4882a593Smuzhiyun #define WM8995_AIF1DAC1_EQ_B1_GAIN_WIDTH 5 /* AIF1DAC1_EQ_B1_GAIN - [15:11] */ 2427*4882a593Smuzhiyun #define WM8995_AIF1DAC1_EQ_B2_GAIN_MASK 0x07C0 /* AIF1DAC1_EQ_B2_GAIN - [10:6] */ 2428*4882a593Smuzhiyun #define WM8995_AIF1DAC1_EQ_B2_GAIN_SHIFT 6 /* AIF1DAC1_EQ_B2_GAIN - [10:6] */ 2429*4882a593Smuzhiyun #define WM8995_AIF1DAC1_EQ_B2_GAIN_WIDTH 5 /* AIF1DAC1_EQ_B2_GAIN - [10:6] */ 2430*4882a593Smuzhiyun #define WM8995_AIF1DAC1_EQ_B3_GAIN_MASK 0x003E /* AIF1DAC1_EQ_B3_GAIN - [5:1] */ 2431*4882a593Smuzhiyun #define WM8995_AIF1DAC1_EQ_B3_GAIN_SHIFT 1 /* AIF1DAC1_EQ_B3_GAIN - [5:1] */ 2432*4882a593Smuzhiyun #define WM8995_AIF1DAC1_EQ_B3_GAIN_WIDTH 5 /* AIF1DAC1_EQ_B3_GAIN - [5:1] */ 2433*4882a593Smuzhiyun #define WM8995_AIF1DAC1_EQ_ENA 0x0001 /* AIF1DAC1_EQ_ENA */ 2434*4882a593Smuzhiyun #define WM8995_AIF1DAC1_EQ_ENA_MASK 0x0001 /* AIF1DAC1_EQ_ENA */ 2435*4882a593Smuzhiyun #define WM8995_AIF1DAC1_EQ_ENA_SHIFT 0 /* AIF1DAC1_EQ_ENA */ 2436*4882a593Smuzhiyun #define WM8995_AIF1DAC1_EQ_ENA_WIDTH 1 /* AIF1DAC1_EQ_ENA */ 2437*4882a593Smuzhiyun 2438*4882a593Smuzhiyun /* 2439*4882a593Smuzhiyun * R1153 (0x481) - AIF1 DAC1 EQ Gains (2) 2440*4882a593Smuzhiyun */ 2441*4882a593Smuzhiyun #define WM8995_AIF1DAC1_EQ_B4_GAIN_MASK 0xF800 /* AIF1DAC1_EQ_B4_GAIN - [15:11] */ 2442*4882a593Smuzhiyun #define WM8995_AIF1DAC1_EQ_B4_GAIN_SHIFT 11 /* AIF1DAC1_EQ_B4_GAIN - [15:11] */ 2443*4882a593Smuzhiyun #define WM8995_AIF1DAC1_EQ_B4_GAIN_WIDTH 5 /* AIF1DAC1_EQ_B4_GAIN - [15:11] */ 2444*4882a593Smuzhiyun #define WM8995_AIF1DAC1_EQ_B5_GAIN_MASK 0x07C0 /* AIF1DAC1_EQ_B5_GAIN - [10:6] */ 2445*4882a593Smuzhiyun #define WM8995_AIF1DAC1_EQ_B5_GAIN_SHIFT 6 /* AIF1DAC1_EQ_B5_GAIN - [10:6] */ 2446*4882a593Smuzhiyun #define WM8995_AIF1DAC1_EQ_B5_GAIN_WIDTH 5 /* AIF1DAC1_EQ_B5_GAIN - [10:6] */ 2447*4882a593Smuzhiyun 2448*4882a593Smuzhiyun /* 2449*4882a593Smuzhiyun * R1154 (0x482) - AIF1 DAC1 EQ Band 1 A 2450*4882a593Smuzhiyun */ 2451*4882a593Smuzhiyun #define WM8995_AIF1DAC1_EQ_B1_A_MASK 0xFFFF /* AIF1DAC1_EQ_B1_A - [15:0] */ 2452*4882a593Smuzhiyun #define WM8995_AIF1DAC1_EQ_B1_A_SHIFT 0 /* AIF1DAC1_EQ_B1_A - [15:0] */ 2453*4882a593Smuzhiyun #define WM8995_AIF1DAC1_EQ_B1_A_WIDTH 16 /* AIF1DAC1_EQ_B1_A - [15:0] */ 2454*4882a593Smuzhiyun 2455*4882a593Smuzhiyun /* 2456*4882a593Smuzhiyun * R1155 (0x483) - AIF1 DAC1 EQ Band 1 B 2457*4882a593Smuzhiyun */ 2458*4882a593Smuzhiyun #define WM8995_AIF1DAC1_EQ_B1_B_MASK 0xFFFF /* AIF1DAC1_EQ_B1_B - [15:0] */ 2459*4882a593Smuzhiyun #define WM8995_AIF1DAC1_EQ_B1_B_SHIFT 0 /* AIF1DAC1_EQ_B1_B - [15:0] */ 2460*4882a593Smuzhiyun #define WM8995_AIF1DAC1_EQ_B1_B_WIDTH 16 /* AIF1DAC1_EQ_B1_B - [15:0] */ 2461*4882a593Smuzhiyun 2462*4882a593Smuzhiyun /* 2463*4882a593Smuzhiyun * R1156 (0x484) - AIF1 DAC1 EQ Band 1 PG 2464*4882a593Smuzhiyun */ 2465*4882a593Smuzhiyun #define WM8995_AIF1DAC1_EQ_B1_PG_MASK 0xFFFF /* AIF1DAC1_EQ_B1_PG - [15:0] */ 2466*4882a593Smuzhiyun #define WM8995_AIF1DAC1_EQ_B1_PG_SHIFT 0 /* AIF1DAC1_EQ_B1_PG - [15:0] */ 2467*4882a593Smuzhiyun #define WM8995_AIF1DAC1_EQ_B1_PG_WIDTH 16 /* AIF1DAC1_EQ_B1_PG - [15:0] */ 2468*4882a593Smuzhiyun 2469*4882a593Smuzhiyun /* 2470*4882a593Smuzhiyun * R1157 (0x485) - AIF1 DAC1 EQ Band 2 A 2471*4882a593Smuzhiyun */ 2472*4882a593Smuzhiyun #define WM8995_AIF1DAC1_EQ_B2_A_MASK 0xFFFF /* AIF1DAC1_EQ_B2_A - [15:0] */ 2473*4882a593Smuzhiyun #define WM8995_AIF1DAC1_EQ_B2_A_SHIFT 0 /* AIF1DAC1_EQ_B2_A - [15:0] */ 2474*4882a593Smuzhiyun #define WM8995_AIF1DAC1_EQ_B2_A_WIDTH 16 /* AIF1DAC1_EQ_B2_A - [15:0] */ 2475*4882a593Smuzhiyun 2476*4882a593Smuzhiyun /* 2477*4882a593Smuzhiyun * R1158 (0x486) - AIF1 DAC1 EQ Band 2 B 2478*4882a593Smuzhiyun */ 2479*4882a593Smuzhiyun #define WM8995_AIF1DAC1_EQ_B2_B_MASK 0xFFFF /* AIF1DAC1_EQ_B2_B - [15:0] */ 2480*4882a593Smuzhiyun #define WM8995_AIF1DAC1_EQ_B2_B_SHIFT 0 /* AIF1DAC1_EQ_B2_B - [15:0] */ 2481*4882a593Smuzhiyun #define WM8995_AIF1DAC1_EQ_B2_B_WIDTH 16 /* AIF1DAC1_EQ_B2_B - [15:0] */ 2482*4882a593Smuzhiyun 2483*4882a593Smuzhiyun /* 2484*4882a593Smuzhiyun * R1159 (0x487) - AIF1 DAC1 EQ Band 2 C 2485*4882a593Smuzhiyun */ 2486*4882a593Smuzhiyun #define WM8995_AIF1DAC1_EQ_B2_C_MASK 0xFFFF /* AIF1DAC1_EQ_B2_C - [15:0] */ 2487*4882a593Smuzhiyun #define WM8995_AIF1DAC1_EQ_B2_C_SHIFT 0 /* AIF1DAC1_EQ_B2_C - [15:0] */ 2488*4882a593Smuzhiyun #define WM8995_AIF1DAC1_EQ_B2_C_WIDTH 16 /* AIF1DAC1_EQ_B2_C - [15:0] */ 2489*4882a593Smuzhiyun 2490*4882a593Smuzhiyun /* 2491*4882a593Smuzhiyun * R1160 (0x488) - AIF1 DAC1 EQ Band 2 PG 2492*4882a593Smuzhiyun */ 2493*4882a593Smuzhiyun #define WM8995_AIF1DAC1_EQ_B2_PG_MASK 0xFFFF /* AIF1DAC1_EQ_B2_PG - [15:0] */ 2494*4882a593Smuzhiyun #define WM8995_AIF1DAC1_EQ_B2_PG_SHIFT 0 /* AIF1DAC1_EQ_B2_PG - [15:0] */ 2495*4882a593Smuzhiyun #define WM8995_AIF1DAC1_EQ_B2_PG_WIDTH 16 /* AIF1DAC1_EQ_B2_PG - [15:0] */ 2496*4882a593Smuzhiyun 2497*4882a593Smuzhiyun /* 2498*4882a593Smuzhiyun * R1161 (0x489) - AIF1 DAC1 EQ Band 3 A 2499*4882a593Smuzhiyun */ 2500*4882a593Smuzhiyun #define WM8995_AIF1DAC1_EQ_B3_A_MASK 0xFFFF /* AIF1DAC1_EQ_B3_A - [15:0] */ 2501*4882a593Smuzhiyun #define WM8995_AIF1DAC1_EQ_B3_A_SHIFT 0 /* AIF1DAC1_EQ_B3_A - [15:0] */ 2502*4882a593Smuzhiyun #define WM8995_AIF1DAC1_EQ_B3_A_WIDTH 16 /* AIF1DAC1_EQ_B3_A - [15:0] */ 2503*4882a593Smuzhiyun 2504*4882a593Smuzhiyun /* 2505*4882a593Smuzhiyun * R1162 (0x48A) - AIF1 DAC1 EQ Band 3 B 2506*4882a593Smuzhiyun */ 2507*4882a593Smuzhiyun #define WM8995_AIF1DAC1_EQ_B3_B_MASK 0xFFFF /* AIF1DAC1_EQ_B3_B - [15:0] */ 2508*4882a593Smuzhiyun #define WM8995_AIF1DAC1_EQ_B3_B_SHIFT 0 /* AIF1DAC1_EQ_B3_B - [15:0] */ 2509*4882a593Smuzhiyun #define WM8995_AIF1DAC1_EQ_B3_B_WIDTH 16 /* AIF1DAC1_EQ_B3_B - [15:0] */ 2510*4882a593Smuzhiyun 2511*4882a593Smuzhiyun /* 2512*4882a593Smuzhiyun * R1163 (0x48B) - AIF1 DAC1 EQ Band 3 C 2513*4882a593Smuzhiyun */ 2514*4882a593Smuzhiyun #define WM8995_AIF1DAC1_EQ_B3_C_MASK 0xFFFF /* AIF1DAC1_EQ_B3_C - [15:0] */ 2515*4882a593Smuzhiyun #define WM8995_AIF1DAC1_EQ_B3_C_SHIFT 0 /* AIF1DAC1_EQ_B3_C - [15:0] */ 2516*4882a593Smuzhiyun #define WM8995_AIF1DAC1_EQ_B3_C_WIDTH 16 /* AIF1DAC1_EQ_B3_C - [15:0] */ 2517*4882a593Smuzhiyun 2518*4882a593Smuzhiyun /* 2519*4882a593Smuzhiyun * R1164 (0x48C) - AIF1 DAC1 EQ Band 3 PG 2520*4882a593Smuzhiyun */ 2521*4882a593Smuzhiyun #define WM8995_AIF1DAC1_EQ_B3_PG_MASK 0xFFFF /* AIF1DAC1_EQ_B3_PG - [15:0] */ 2522*4882a593Smuzhiyun #define WM8995_AIF1DAC1_EQ_B3_PG_SHIFT 0 /* AIF1DAC1_EQ_B3_PG - [15:0] */ 2523*4882a593Smuzhiyun #define WM8995_AIF1DAC1_EQ_B3_PG_WIDTH 16 /* AIF1DAC1_EQ_B3_PG - [15:0] */ 2524*4882a593Smuzhiyun 2525*4882a593Smuzhiyun /* 2526*4882a593Smuzhiyun * R1165 (0x48D) - AIF1 DAC1 EQ Band 4 A 2527*4882a593Smuzhiyun */ 2528*4882a593Smuzhiyun #define WM8995_AIF1DAC1_EQ_B4_A_MASK 0xFFFF /* AIF1DAC1_EQ_B4_A - [15:0] */ 2529*4882a593Smuzhiyun #define WM8995_AIF1DAC1_EQ_B4_A_SHIFT 0 /* AIF1DAC1_EQ_B4_A - [15:0] */ 2530*4882a593Smuzhiyun #define WM8995_AIF1DAC1_EQ_B4_A_WIDTH 16 /* AIF1DAC1_EQ_B4_A - [15:0] */ 2531*4882a593Smuzhiyun 2532*4882a593Smuzhiyun /* 2533*4882a593Smuzhiyun * R1166 (0x48E) - AIF1 DAC1 EQ Band 4 B 2534*4882a593Smuzhiyun */ 2535*4882a593Smuzhiyun #define WM8995_AIF1DAC1_EQ_B4_B_MASK 0xFFFF /* AIF1DAC1_EQ_B4_B - [15:0] */ 2536*4882a593Smuzhiyun #define WM8995_AIF1DAC1_EQ_B4_B_SHIFT 0 /* AIF1DAC1_EQ_B4_B - [15:0] */ 2537*4882a593Smuzhiyun #define WM8995_AIF1DAC1_EQ_B4_B_WIDTH 16 /* AIF1DAC1_EQ_B4_B - [15:0] */ 2538*4882a593Smuzhiyun 2539*4882a593Smuzhiyun /* 2540*4882a593Smuzhiyun * R1167 (0x48F) - AIF1 DAC1 EQ Band 4 C 2541*4882a593Smuzhiyun */ 2542*4882a593Smuzhiyun #define WM8995_AIF1DAC1_EQ_B4_C_MASK 0xFFFF /* AIF1DAC1_EQ_B4_C - [15:0] */ 2543*4882a593Smuzhiyun #define WM8995_AIF1DAC1_EQ_B4_C_SHIFT 0 /* AIF1DAC1_EQ_B4_C - [15:0] */ 2544*4882a593Smuzhiyun #define WM8995_AIF1DAC1_EQ_B4_C_WIDTH 16 /* AIF1DAC1_EQ_B4_C - [15:0] */ 2545*4882a593Smuzhiyun 2546*4882a593Smuzhiyun /* 2547*4882a593Smuzhiyun * R1168 (0x490) - AIF1 DAC1 EQ Band 4 PG 2548*4882a593Smuzhiyun */ 2549*4882a593Smuzhiyun #define WM8995_AIF1DAC1_EQ_B4_PG_MASK 0xFFFF /* AIF1DAC1_EQ_B4_PG - [15:0] */ 2550*4882a593Smuzhiyun #define WM8995_AIF1DAC1_EQ_B4_PG_SHIFT 0 /* AIF1DAC1_EQ_B4_PG - [15:0] */ 2551*4882a593Smuzhiyun #define WM8995_AIF1DAC1_EQ_B4_PG_WIDTH 16 /* AIF1DAC1_EQ_B4_PG - [15:0] */ 2552*4882a593Smuzhiyun 2553*4882a593Smuzhiyun /* 2554*4882a593Smuzhiyun * R1169 (0x491) - AIF1 DAC1 EQ Band 5 A 2555*4882a593Smuzhiyun */ 2556*4882a593Smuzhiyun #define WM8995_AIF1DAC1_EQ_B5_A_MASK 0xFFFF /* AIF1DAC1_EQ_B5_A - [15:0] */ 2557*4882a593Smuzhiyun #define WM8995_AIF1DAC1_EQ_B5_A_SHIFT 0 /* AIF1DAC1_EQ_B5_A - [15:0] */ 2558*4882a593Smuzhiyun #define WM8995_AIF1DAC1_EQ_B5_A_WIDTH 16 /* AIF1DAC1_EQ_B5_A - [15:0] */ 2559*4882a593Smuzhiyun 2560*4882a593Smuzhiyun /* 2561*4882a593Smuzhiyun * R1170 (0x492) - AIF1 DAC1 EQ Band 5 B 2562*4882a593Smuzhiyun */ 2563*4882a593Smuzhiyun #define WM8995_AIF1DAC1_EQ_B5_B_MASK 0xFFFF /* AIF1DAC1_EQ_B5_B - [15:0] */ 2564*4882a593Smuzhiyun #define WM8995_AIF1DAC1_EQ_B5_B_SHIFT 0 /* AIF1DAC1_EQ_B5_B - [15:0] */ 2565*4882a593Smuzhiyun #define WM8995_AIF1DAC1_EQ_B5_B_WIDTH 16 /* AIF1DAC1_EQ_B5_B - [15:0] */ 2566*4882a593Smuzhiyun 2567*4882a593Smuzhiyun /* 2568*4882a593Smuzhiyun * R1171 (0x493) - AIF1 DAC1 EQ Band 5 PG 2569*4882a593Smuzhiyun */ 2570*4882a593Smuzhiyun #define WM8995_AIF1DAC1_EQ_B5_PG_MASK 0xFFFF /* AIF1DAC1_EQ_B5_PG - [15:0] */ 2571*4882a593Smuzhiyun #define WM8995_AIF1DAC1_EQ_B5_PG_SHIFT 0 /* AIF1DAC1_EQ_B5_PG - [15:0] */ 2572*4882a593Smuzhiyun #define WM8995_AIF1DAC1_EQ_B5_PG_WIDTH 16 /* AIF1DAC1_EQ_B5_PG - [15:0] */ 2573*4882a593Smuzhiyun 2574*4882a593Smuzhiyun /* 2575*4882a593Smuzhiyun * R1184 (0x4A0) - AIF1 DAC2 EQ Gains (1) 2576*4882a593Smuzhiyun */ 2577*4882a593Smuzhiyun #define WM8995_AIF1DAC2_EQ_B1_GAIN_MASK 0xF800 /* AIF1DAC2_EQ_B1_GAIN - [15:11] */ 2578*4882a593Smuzhiyun #define WM8995_AIF1DAC2_EQ_B1_GAIN_SHIFT 11 /* AIF1DAC2_EQ_B1_GAIN - [15:11] */ 2579*4882a593Smuzhiyun #define WM8995_AIF1DAC2_EQ_B1_GAIN_WIDTH 5 /* AIF1DAC2_EQ_B1_GAIN - [15:11] */ 2580*4882a593Smuzhiyun #define WM8995_AIF1DAC2_EQ_B2_GAIN_MASK 0x07C0 /* AIF1DAC2_EQ_B2_GAIN - [10:6] */ 2581*4882a593Smuzhiyun #define WM8995_AIF1DAC2_EQ_B2_GAIN_SHIFT 6 /* AIF1DAC2_EQ_B2_GAIN - [10:6] */ 2582*4882a593Smuzhiyun #define WM8995_AIF1DAC2_EQ_B2_GAIN_WIDTH 5 /* AIF1DAC2_EQ_B2_GAIN - [10:6] */ 2583*4882a593Smuzhiyun #define WM8995_AIF1DAC2_EQ_B3_GAIN_MASK 0x003E /* AIF1DAC2_EQ_B3_GAIN - [5:1] */ 2584*4882a593Smuzhiyun #define WM8995_AIF1DAC2_EQ_B3_GAIN_SHIFT 1 /* AIF1DAC2_EQ_B3_GAIN - [5:1] */ 2585*4882a593Smuzhiyun #define WM8995_AIF1DAC2_EQ_B3_GAIN_WIDTH 5 /* AIF1DAC2_EQ_B3_GAIN - [5:1] */ 2586*4882a593Smuzhiyun #define WM8995_AIF1DAC2_EQ_ENA 0x0001 /* AIF1DAC2_EQ_ENA */ 2587*4882a593Smuzhiyun #define WM8995_AIF1DAC2_EQ_ENA_MASK 0x0001 /* AIF1DAC2_EQ_ENA */ 2588*4882a593Smuzhiyun #define WM8995_AIF1DAC2_EQ_ENA_SHIFT 0 /* AIF1DAC2_EQ_ENA */ 2589*4882a593Smuzhiyun #define WM8995_AIF1DAC2_EQ_ENA_WIDTH 1 /* AIF1DAC2_EQ_ENA */ 2590*4882a593Smuzhiyun 2591*4882a593Smuzhiyun /* 2592*4882a593Smuzhiyun * R1185 (0x4A1) - AIF1 DAC2 EQ Gains (2) 2593*4882a593Smuzhiyun */ 2594*4882a593Smuzhiyun #define WM8995_AIF1DAC2_EQ_B4_GAIN_MASK 0xF800 /* AIF1DAC2_EQ_B4_GAIN - [15:11] */ 2595*4882a593Smuzhiyun #define WM8995_AIF1DAC2_EQ_B4_GAIN_SHIFT 11 /* AIF1DAC2_EQ_B4_GAIN - [15:11] */ 2596*4882a593Smuzhiyun #define WM8995_AIF1DAC2_EQ_B4_GAIN_WIDTH 5 /* AIF1DAC2_EQ_B4_GAIN - [15:11] */ 2597*4882a593Smuzhiyun #define WM8995_AIF1DAC2_EQ_B5_GAIN_MASK 0x07C0 /* AIF1DAC2_EQ_B5_GAIN - [10:6] */ 2598*4882a593Smuzhiyun #define WM8995_AIF1DAC2_EQ_B5_GAIN_SHIFT 6 /* AIF1DAC2_EQ_B5_GAIN - [10:6] */ 2599*4882a593Smuzhiyun #define WM8995_AIF1DAC2_EQ_B5_GAIN_WIDTH 5 /* AIF1DAC2_EQ_B5_GAIN - [10:6] */ 2600*4882a593Smuzhiyun 2601*4882a593Smuzhiyun /* 2602*4882a593Smuzhiyun * R1186 (0x4A2) - AIF1 DAC2 EQ Band 1 A 2603*4882a593Smuzhiyun */ 2604*4882a593Smuzhiyun #define WM8995_AIF1DAC2_EQ_B1_A_MASK 0xFFFF /* AIF1DAC2_EQ_B1_A - [15:0] */ 2605*4882a593Smuzhiyun #define WM8995_AIF1DAC2_EQ_B1_A_SHIFT 0 /* AIF1DAC2_EQ_B1_A - [15:0] */ 2606*4882a593Smuzhiyun #define WM8995_AIF1DAC2_EQ_B1_A_WIDTH 16 /* AIF1DAC2_EQ_B1_A - [15:0] */ 2607*4882a593Smuzhiyun 2608*4882a593Smuzhiyun /* 2609*4882a593Smuzhiyun * R1187 (0x4A3) - AIF1 DAC2 EQ Band 1 B 2610*4882a593Smuzhiyun */ 2611*4882a593Smuzhiyun #define WM8995_AIF1DAC2_EQ_B1_B_MASK 0xFFFF /* AIF1DAC2_EQ_B1_B - [15:0] */ 2612*4882a593Smuzhiyun #define WM8995_AIF1DAC2_EQ_B1_B_SHIFT 0 /* AIF1DAC2_EQ_B1_B - [15:0] */ 2613*4882a593Smuzhiyun #define WM8995_AIF1DAC2_EQ_B1_B_WIDTH 16 /* AIF1DAC2_EQ_B1_B - [15:0] */ 2614*4882a593Smuzhiyun 2615*4882a593Smuzhiyun /* 2616*4882a593Smuzhiyun * R1188 (0x4A4) - AIF1 DAC2 EQ Band 1 PG 2617*4882a593Smuzhiyun */ 2618*4882a593Smuzhiyun #define WM8995_AIF1DAC2_EQ_B1_PG_MASK 0xFFFF /* AIF1DAC2_EQ_B1_PG - [15:0] */ 2619*4882a593Smuzhiyun #define WM8995_AIF1DAC2_EQ_B1_PG_SHIFT 0 /* AIF1DAC2_EQ_B1_PG - [15:0] */ 2620*4882a593Smuzhiyun #define WM8995_AIF1DAC2_EQ_B1_PG_WIDTH 16 /* AIF1DAC2_EQ_B1_PG - [15:0] */ 2621*4882a593Smuzhiyun 2622*4882a593Smuzhiyun /* 2623*4882a593Smuzhiyun * R1189 (0x4A5) - AIF1 DAC2 EQ Band 2 A 2624*4882a593Smuzhiyun */ 2625*4882a593Smuzhiyun #define WM8995_AIF1DAC2_EQ_B2_A_MASK 0xFFFF /* AIF1DAC2_EQ_B2_A - [15:0] */ 2626*4882a593Smuzhiyun #define WM8995_AIF1DAC2_EQ_B2_A_SHIFT 0 /* AIF1DAC2_EQ_B2_A - [15:0] */ 2627*4882a593Smuzhiyun #define WM8995_AIF1DAC2_EQ_B2_A_WIDTH 16 /* AIF1DAC2_EQ_B2_A - [15:0] */ 2628*4882a593Smuzhiyun 2629*4882a593Smuzhiyun /* 2630*4882a593Smuzhiyun * R1190 (0x4A6) - AIF1 DAC2 EQ Band 2 B 2631*4882a593Smuzhiyun */ 2632*4882a593Smuzhiyun #define WM8995_AIF1DAC2_EQ_B2_B_MASK 0xFFFF /* AIF1DAC2_EQ_B2_B - [15:0] */ 2633*4882a593Smuzhiyun #define WM8995_AIF1DAC2_EQ_B2_B_SHIFT 0 /* AIF1DAC2_EQ_B2_B - [15:0] */ 2634*4882a593Smuzhiyun #define WM8995_AIF1DAC2_EQ_B2_B_WIDTH 16 /* AIF1DAC2_EQ_B2_B - [15:0] */ 2635*4882a593Smuzhiyun 2636*4882a593Smuzhiyun /* 2637*4882a593Smuzhiyun * R1191 (0x4A7) - AIF1 DAC2 EQ Band 2 C 2638*4882a593Smuzhiyun */ 2639*4882a593Smuzhiyun #define WM8995_AIF1DAC2_EQ_B2_C_MASK 0xFFFF /* AIF1DAC2_EQ_B2_C - [15:0] */ 2640*4882a593Smuzhiyun #define WM8995_AIF1DAC2_EQ_B2_C_SHIFT 0 /* AIF1DAC2_EQ_B2_C - [15:0] */ 2641*4882a593Smuzhiyun #define WM8995_AIF1DAC2_EQ_B2_C_WIDTH 16 /* AIF1DAC2_EQ_B2_C - [15:0] */ 2642*4882a593Smuzhiyun 2643*4882a593Smuzhiyun /* 2644*4882a593Smuzhiyun * R1192 (0x4A8) - AIF1 DAC2 EQ Band 2 PG 2645*4882a593Smuzhiyun */ 2646*4882a593Smuzhiyun #define WM8995_AIF1DAC2_EQ_B2_PG_MASK 0xFFFF /* AIF1DAC2_EQ_B2_PG - [15:0] */ 2647*4882a593Smuzhiyun #define WM8995_AIF1DAC2_EQ_B2_PG_SHIFT 0 /* AIF1DAC2_EQ_B2_PG - [15:0] */ 2648*4882a593Smuzhiyun #define WM8995_AIF1DAC2_EQ_B2_PG_WIDTH 16 /* AIF1DAC2_EQ_B2_PG - [15:0] */ 2649*4882a593Smuzhiyun 2650*4882a593Smuzhiyun /* 2651*4882a593Smuzhiyun * R1193 (0x4A9) - AIF1 DAC2 EQ Band 3 A 2652*4882a593Smuzhiyun */ 2653*4882a593Smuzhiyun #define WM8995_AIF1DAC2_EQ_B3_A_MASK 0xFFFF /* AIF1DAC2_EQ_B3_A - [15:0] */ 2654*4882a593Smuzhiyun #define WM8995_AIF1DAC2_EQ_B3_A_SHIFT 0 /* AIF1DAC2_EQ_B3_A - [15:0] */ 2655*4882a593Smuzhiyun #define WM8995_AIF1DAC2_EQ_B3_A_WIDTH 16 /* AIF1DAC2_EQ_B3_A - [15:0] */ 2656*4882a593Smuzhiyun 2657*4882a593Smuzhiyun /* 2658*4882a593Smuzhiyun * R1194 (0x4AA) - AIF1 DAC2 EQ Band 3 B 2659*4882a593Smuzhiyun */ 2660*4882a593Smuzhiyun #define WM8995_AIF1DAC2_EQ_B3_B_MASK 0xFFFF /* AIF1DAC2_EQ_B3_B - [15:0] */ 2661*4882a593Smuzhiyun #define WM8995_AIF1DAC2_EQ_B3_B_SHIFT 0 /* AIF1DAC2_EQ_B3_B - [15:0] */ 2662*4882a593Smuzhiyun #define WM8995_AIF1DAC2_EQ_B3_B_WIDTH 16 /* AIF1DAC2_EQ_B3_B - [15:0] */ 2663*4882a593Smuzhiyun 2664*4882a593Smuzhiyun /* 2665*4882a593Smuzhiyun * R1195 (0x4AB) - AIF1 DAC2 EQ Band 3 C 2666*4882a593Smuzhiyun */ 2667*4882a593Smuzhiyun #define WM8995_AIF1DAC2_EQ_B3_C_MASK 0xFFFF /* AIF1DAC2_EQ_B3_C - [15:0] */ 2668*4882a593Smuzhiyun #define WM8995_AIF1DAC2_EQ_B3_C_SHIFT 0 /* AIF1DAC2_EQ_B3_C - [15:0] */ 2669*4882a593Smuzhiyun #define WM8995_AIF1DAC2_EQ_B3_C_WIDTH 16 /* AIF1DAC2_EQ_B3_C - [15:0] */ 2670*4882a593Smuzhiyun 2671*4882a593Smuzhiyun /* 2672*4882a593Smuzhiyun * R1196 (0x4AC) - AIF1 DAC2 EQ Band 3 PG 2673*4882a593Smuzhiyun */ 2674*4882a593Smuzhiyun #define WM8995_AIF1DAC2_EQ_B3_PG_MASK 0xFFFF /* AIF1DAC2_EQ_B3_PG - [15:0] */ 2675*4882a593Smuzhiyun #define WM8995_AIF1DAC2_EQ_B3_PG_SHIFT 0 /* AIF1DAC2_EQ_B3_PG - [15:0] */ 2676*4882a593Smuzhiyun #define WM8995_AIF1DAC2_EQ_B3_PG_WIDTH 16 /* AIF1DAC2_EQ_B3_PG - [15:0] */ 2677*4882a593Smuzhiyun 2678*4882a593Smuzhiyun /* 2679*4882a593Smuzhiyun * R1197 (0x4AD) - AIF1 DAC2 EQ Band 4 A 2680*4882a593Smuzhiyun */ 2681*4882a593Smuzhiyun #define WM8995_AIF1DAC2_EQ_B4_A_MASK 0xFFFF /* AIF1DAC2_EQ_B4_A - [15:0] */ 2682*4882a593Smuzhiyun #define WM8995_AIF1DAC2_EQ_B4_A_SHIFT 0 /* AIF1DAC2_EQ_B4_A - [15:0] */ 2683*4882a593Smuzhiyun #define WM8995_AIF1DAC2_EQ_B4_A_WIDTH 16 /* AIF1DAC2_EQ_B4_A - [15:0] */ 2684*4882a593Smuzhiyun 2685*4882a593Smuzhiyun /* 2686*4882a593Smuzhiyun * R1198 (0x4AE) - AIF1 DAC2 EQ Band 4 B 2687*4882a593Smuzhiyun */ 2688*4882a593Smuzhiyun #define WM8995_AIF1DAC2_EQ_B4_B_MASK 0xFFFF /* AIF1DAC2_EQ_B4_B - [15:0] */ 2689*4882a593Smuzhiyun #define WM8995_AIF1DAC2_EQ_B4_B_SHIFT 0 /* AIF1DAC2_EQ_B4_B - [15:0] */ 2690*4882a593Smuzhiyun #define WM8995_AIF1DAC2_EQ_B4_B_WIDTH 16 /* AIF1DAC2_EQ_B4_B - [15:0] */ 2691*4882a593Smuzhiyun 2692*4882a593Smuzhiyun /* 2693*4882a593Smuzhiyun * R1199 (0x4AF) - AIF1 DAC2 EQ Band 4 C 2694*4882a593Smuzhiyun */ 2695*4882a593Smuzhiyun #define WM8995_AIF1DAC2_EQ_B4_C_MASK 0xFFFF /* AIF1DAC2_EQ_B4_C - [15:0] */ 2696*4882a593Smuzhiyun #define WM8995_AIF1DAC2_EQ_B4_C_SHIFT 0 /* AIF1DAC2_EQ_B4_C - [15:0] */ 2697*4882a593Smuzhiyun #define WM8995_AIF1DAC2_EQ_B4_C_WIDTH 16 /* AIF1DAC2_EQ_B4_C - [15:0] */ 2698*4882a593Smuzhiyun 2699*4882a593Smuzhiyun /* 2700*4882a593Smuzhiyun * R1200 (0x4B0) - AIF1 DAC2 EQ Band 4 PG 2701*4882a593Smuzhiyun */ 2702*4882a593Smuzhiyun #define WM8995_AIF1DAC2_EQ_B4_PG_MASK 0xFFFF /* AIF1DAC2_EQ_B4_PG - [15:0] */ 2703*4882a593Smuzhiyun #define WM8995_AIF1DAC2_EQ_B4_PG_SHIFT 0 /* AIF1DAC2_EQ_B4_PG - [15:0] */ 2704*4882a593Smuzhiyun #define WM8995_AIF1DAC2_EQ_B4_PG_WIDTH 16 /* AIF1DAC2_EQ_B4_PG - [15:0] */ 2705*4882a593Smuzhiyun 2706*4882a593Smuzhiyun /* 2707*4882a593Smuzhiyun * R1201 (0x4B1) - AIF1 DAC2 EQ Band 5 A 2708*4882a593Smuzhiyun */ 2709*4882a593Smuzhiyun #define WM8995_AIF1DAC2_EQ_B5_A_MASK 0xFFFF /* AIF1DAC2_EQ_B5_A - [15:0] */ 2710*4882a593Smuzhiyun #define WM8995_AIF1DAC2_EQ_B5_A_SHIFT 0 /* AIF1DAC2_EQ_B5_A - [15:0] */ 2711*4882a593Smuzhiyun #define WM8995_AIF1DAC2_EQ_B5_A_WIDTH 16 /* AIF1DAC2_EQ_B5_A - [15:0] */ 2712*4882a593Smuzhiyun 2713*4882a593Smuzhiyun /* 2714*4882a593Smuzhiyun * R1202 (0x4B2) - AIF1 DAC2 EQ Band 5 B 2715*4882a593Smuzhiyun */ 2716*4882a593Smuzhiyun #define WM8995_AIF1DAC2_EQ_B5_B_MASK 0xFFFF /* AIF1DAC2_EQ_B5_B - [15:0] */ 2717*4882a593Smuzhiyun #define WM8995_AIF1DAC2_EQ_B5_B_SHIFT 0 /* AIF1DAC2_EQ_B5_B - [15:0] */ 2718*4882a593Smuzhiyun #define WM8995_AIF1DAC2_EQ_B5_B_WIDTH 16 /* AIF1DAC2_EQ_B5_B - [15:0] */ 2719*4882a593Smuzhiyun 2720*4882a593Smuzhiyun /* 2721*4882a593Smuzhiyun * R1203 (0x4B3) - AIF1 DAC2 EQ Band 5 PG 2722*4882a593Smuzhiyun */ 2723*4882a593Smuzhiyun #define WM8995_AIF1DAC2_EQ_B5_PG_MASK 0xFFFF /* AIF1DAC2_EQ_B5_PG - [15:0] */ 2724*4882a593Smuzhiyun #define WM8995_AIF1DAC2_EQ_B5_PG_SHIFT 0 /* AIF1DAC2_EQ_B5_PG - [15:0] */ 2725*4882a593Smuzhiyun #define WM8995_AIF1DAC2_EQ_B5_PG_WIDTH 16 /* AIF1DAC2_EQ_B5_PG - [15:0] */ 2726*4882a593Smuzhiyun 2727*4882a593Smuzhiyun /* 2728*4882a593Smuzhiyun * R1280 (0x500) - AIF2 ADC Left Volume 2729*4882a593Smuzhiyun */ 2730*4882a593Smuzhiyun #define WM8995_AIF2ADC_VU 0x0100 /* AIF2ADC_VU */ 2731*4882a593Smuzhiyun #define WM8995_AIF2ADC_VU_MASK 0x0100 /* AIF2ADC_VU */ 2732*4882a593Smuzhiyun #define WM8995_AIF2ADC_VU_SHIFT 8 /* AIF2ADC_VU */ 2733*4882a593Smuzhiyun #define WM8995_AIF2ADC_VU_WIDTH 1 /* AIF2ADC_VU */ 2734*4882a593Smuzhiyun #define WM8995_AIF2ADCL_VOL_MASK 0x00FF /* AIF2ADCL_VOL - [7:0] */ 2735*4882a593Smuzhiyun #define WM8995_AIF2ADCL_VOL_SHIFT 0 /* AIF2ADCL_VOL - [7:0] */ 2736*4882a593Smuzhiyun #define WM8995_AIF2ADCL_VOL_WIDTH 8 /* AIF2ADCL_VOL - [7:0] */ 2737*4882a593Smuzhiyun 2738*4882a593Smuzhiyun /* 2739*4882a593Smuzhiyun * R1281 (0x501) - AIF2 ADC Right Volume 2740*4882a593Smuzhiyun */ 2741*4882a593Smuzhiyun #define WM8995_AIF2ADC_VU 0x0100 /* AIF2ADC_VU */ 2742*4882a593Smuzhiyun #define WM8995_AIF2ADC_VU_MASK 0x0100 /* AIF2ADC_VU */ 2743*4882a593Smuzhiyun #define WM8995_AIF2ADC_VU_SHIFT 8 /* AIF2ADC_VU */ 2744*4882a593Smuzhiyun #define WM8995_AIF2ADC_VU_WIDTH 1 /* AIF2ADC_VU */ 2745*4882a593Smuzhiyun #define WM8995_AIF2ADCR_VOL_MASK 0x00FF /* AIF2ADCR_VOL - [7:0] */ 2746*4882a593Smuzhiyun #define WM8995_AIF2ADCR_VOL_SHIFT 0 /* AIF2ADCR_VOL - [7:0] */ 2747*4882a593Smuzhiyun #define WM8995_AIF2ADCR_VOL_WIDTH 8 /* AIF2ADCR_VOL - [7:0] */ 2748*4882a593Smuzhiyun 2749*4882a593Smuzhiyun /* 2750*4882a593Smuzhiyun * R1282 (0x502) - AIF2 DAC Left Volume 2751*4882a593Smuzhiyun */ 2752*4882a593Smuzhiyun #define WM8995_AIF2DAC_VU 0x0100 /* AIF2DAC_VU */ 2753*4882a593Smuzhiyun #define WM8995_AIF2DAC_VU_MASK 0x0100 /* AIF2DAC_VU */ 2754*4882a593Smuzhiyun #define WM8995_AIF2DAC_VU_SHIFT 8 /* AIF2DAC_VU */ 2755*4882a593Smuzhiyun #define WM8995_AIF2DAC_VU_WIDTH 1 /* AIF2DAC_VU */ 2756*4882a593Smuzhiyun #define WM8995_AIF2DACL_VOL_MASK 0x00FF /* AIF2DACL_VOL - [7:0] */ 2757*4882a593Smuzhiyun #define WM8995_AIF2DACL_VOL_SHIFT 0 /* AIF2DACL_VOL - [7:0] */ 2758*4882a593Smuzhiyun #define WM8995_AIF2DACL_VOL_WIDTH 8 /* AIF2DACL_VOL - [7:0] */ 2759*4882a593Smuzhiyun 2760*4882a593Smuzhiyun /* 2761*4882a593Smuzhiyun * R1283 (0x503) - AIF2 DAC Right Volume 2762*4882a593Smuzhiyun */ 2763*4882a593Smuzhiyun #define WM8995_AIF2DAC_VU 0x0100 /* AIF2DAC_VU */ 2764*4882a593Smuzhiyun #define WM8995_AIF2DAC_VU_MASK 0x0100 /* AIF2DAC_VU */ 2765*4882a593Smuzhiyun #define WM8995_AIF2DAC_VU_SHIFT 8 /* AIF2DAC_VU */ 2766*4882a593Smuzhiyun #define WM8995_AIF2DAC_VU_WIDTH 1 /* AIF2DAC_VU */ 2767*4882a593Smuzhiyun #define WM8995_AIF2DACR_VOL_MASK 0x00FF /* AIF2DACR_VOL - [7:0] */ 2768*4882a593Smuzhiyun #define WM8995_AIF2DACR_VOL_SHIFT 0 /* AIF2DACR_VOL - [7:0] */ 2769*4882a593Smuzhiyun #define WM8995_AIF2DACR_VOL_WIDTH 8 /* AIF2DACR_VOL - [7:0] */ 2770*4882a593Smuzhiyun 2771*4882a593Smuzhiyun /* 2772*4882a593Smuzhiyun * R1296 (0x510) - AIF2 ADC Filters 2773*4882a593Smuzhiyun */ 2774*4882a593Smuzhiyun #define WM8995_AIF2ADC_4FS 0x8000 /* AIF2ADC_4FS */ 2775*4882a593Smuzhiyun #define WM8995_AIF2ADC_4FS_MASK 0x8000 /* AIF2ADC_4FS */ 2776*4882a593Smuzhiyun #define WM8995_AIF2ADC_4FS_SHIFT 15 /* AIF2ADC_4FS */ 2777*4882a593Smuzhiyun #define WM8995_AIF2ADC_4FS_WIDTH 1 /* AIF2ADC_4FS */ 2778*4882a593Smuzhiyun #define WM8995_AIF2ADCL_HPF 0x1000 /* AIF2ADCL_HPF */ 2779*4882a593Smuzhiyun #define WM8995_AIF2ADCL_HPF_MASK 0x1000 /* AIF2ADCL_HPF */ 2780*4882a593Smuzhiyun #define WM8995_AIF2ADCL_HPF_SHIFT 12 /* AIF2ADCL_HPF */ 2781*4882a593Smuzhiyun #define WM8995_AIF2ADCL_HPF_WIDTH 1 /* AIF2ADCL_HPF */ 2782*4882a593Smuzhiyun #define WM8995_AIF2ADCR_HPF 0x0800 /* AIF2ADCR_HPF */ 2783*4882a593Smuzhiyun #define WM8995_AIF2ADCR_HPF_MASK 0x0800 /* AIF2ADCR_HPF */ 2784*4882a593Smuzhiyun #define WM8995_AIF2ADCR_HPF_SHIFT 11 /* AIF2ADCR_HPF */ 2785*4882a593Smuzhiyun #define WM8995_AIF2ADCR_HPF_WIDTH 1 /* AIF2ADCR_HPF */ 2786*4882a593Smuzhiyun #define WM8995_AIF2ADC_HPF_MODE 0x0008 /* AIF2ADC_HPF_MODE */ 2787*4882a593Smuzhiyun #define WM8995_AIF2ADC_HPF_MODE_MASK 0x0008 /* AIF2ADC_HPF_MODE */ 2788*4882a593Smuzhiyun #define WM8995_AIF2ADC_HPF_MODE_SHIFT 3 /* AIF2ADC_HPF_MODE */ 2789*4882a593Smuzhiyun #define WM8995_AIF2ADC_HPF_MODE_WIDTH 1 /* AIF2ADC_HPF_MODE */ 2790*4882a593Smuzhiyun #define WM8995_AIF2ADC_HPF_CUT_MASK 0x0007 /* AIF2ADC_HPF_CUT - [2:0] */ 2791*4882a593Smuzhiyun #define WM8995_AIF2ADC_HPF_CUT_SHIFT 0 /* AIF2ADC_HPF_CUT - [2:0] */ 2792*4882a593Smuzhiyun #define WM8995_AIF2ADC_HPF_CUT_WIDTH 3 /* AIF2ADC_HPF_CUT - [2:0] */ 2793*4882a593Smuzhiyun 2794*4882a593Smuzhiyun /* 2795*4882a593Smuzhiyun * R1312 (0x520) - AIF2 DAC Filters (1) 2796*4882a593Smuzhiyun */ 2797*4882a593Smuzhiyun #define WM8995_AIF2DAC_MUTE 0x0200 /* AIF2DAC_MUTE */ 2798*4882a593Smuzhiyun #define WM8995_AIF2DAC_MUTE_MASK 0x0200 /* AIF2DAC_MUTE */ 2799*4882a593Smuzhiyun #define WM8995_AIF2DAC_MUTE_SHIFT 9 /* AIF2DAC_MUTE */ 2800*4882a593Smuzhiyun #define WM8995_AIF2DAC_MUTE_WIDTH 1 /* AIF2DAC_MUTE */ 2801*4882a593Smuzhiyun #define WM8995_AIF2DAC_MONO 0x0080 /* AIF2DAC_MONO */ 2802*4882a593Smuzhiyun #define WM8995_AIF2DAC_MONO_MASK 0x0080 /* AIF2DAC_MONO */ 2803*4882a593Smuzhiyun #define WM8995_AIF2DAC_MONO_SHIFT 7 /* AIF2DAC_MONO */ 2804*4882a593Smuzhiyun #define WM8995_AIF2DAC_MONO_WIDTH 1 /* AIF2DAC_MONO */ 2805*4882a593Smuzhiyun #define WM8995_AIF2DAC_MUTERATE 0x0020 /* AIF2DAC_MUTERATE */ 2806*4882a593Smuzhiyun #define WM8995_AIF2DAC_MUTERATE_MASK 0x0020 /* AIF2DAC_MUTERATE */ 2807*4882a593Smuzhiyun #define WM8995_AIF2DAC_MUTERATE_SHIFT 5 /* AIF2DAC_MUTERATE */ 2808*4882a593Smuzhiyun #define WM8995_AIF2DAC_MUTERATE_WIDTH 1 /* AIF2DAC_MUTERATE */ 2809*4882a593Smuzhiyun #define WM8995_AIF2DAC_UNMUTE_RAMP 0x0010 /* AIF2DAC_UNMUTE_RAMP */ 2810*4882a593Smuzhiyun #define WM8995_AIF2DAC_UNMUTE_RAMP_MASK 0x0010 /* AIF2DAC_UNMUTE_RAMP */ 2811*4882a593Smuzhiyun #define WM8995_AIF2DAC_UNMUTE_RAMP_SHIFT 4 /* AIF2DAC_UNMUTE_RAMP */ 2812*4882a593Smuzhiyun #define WM8995_AIF2DAC_UNMUTE_RAMP_WIDTH 1 /* AIF2DAC_UNMUTE_RAMP */ 2813*4882a593Smuzhiyun #define WM8995_AIF2DAC_DEEMP_MASK 0x0006 /* AIF2DAC_DEEMP - [2:1] */ 2814*4882a593Smuzhiyun #define WM8995_AIF2DAC_DEEMP_SHIFT 1 /* AIF2DAC_DEEMP - [2:1] */ 2815*4882a593Smuzhiyun #define WM8995_AIF2DAC_DEEMP_WIDTH 2 /* AIF2DAC_DEEMP - [2:1] */ 2816*4882a593Smuzhiyun 2817*4882a593Smuzhiyun /* 2818*4882a593Smuzhiyun * R1313 (0x521) - AIF2 DAC Filters (2) 2819*4882a593Smuzhiyun */ 2820*4882a593Smuzhiyun #define WM8995_AIF2DAC_3D_GAIN_MASK 0x3E00 /* AIF2DAC_3D_GAIN - [13:9] */ 2821*4882a593Smuzhiyun #define WM8995_AIF2DAC_3D_GAIN_SHIFT 9 /* AIF2DAC_3D_GAIN - [13:9] */ 2822*4882a593Smuzhiyun #define WM8995_AIF2DAC_3D_GAIN_WIDTH 5 /* AIF2DAC_3D_GAIN - [13:9] */ 2823*4882a593Smuzhiyun #define WM8995_AIF2DAC_3D_ENA 0x0100 /* AIF2DAC_3D_ENA */ 2824*4882a593Smuzhiyun #define WM8995_AIF2DAC_3D_ENA_MASK 0x0100 /* AIF2DAC_3D_ENA */ 2825*4882a593Smuzhiyun #define WM8995_AIF2DAC_3D_ENA_SHIFT 8 /* AIF2DAC_3D_ENA */ 2826*4882a593Smuzhiyun #define WM8995_AIF2DAC_3D_ENA_WIDTH 1 /* AIF2DAC_3D_ENA */ 2827*4882a593Smuzhiyun 2828*4882a593Smuzhiyun /* 2829*4882a593Smuzhiyun * R1344 (0x540) - AIF2 DRC (1) 2830*4882a593Smuzhiyun */ 2831*4882a593Smuzhiyun #define WM8995_AIF2DRC_SIG_DET_RMS_MASK 0xF800 /* AIF2DRC_SIG_DET_RMS - [15:11] */ 2832*4882a593Smuzhiyun #define WM8995_AIF2DRC_SIG_DET_RMS_SHIFT 11 /* AIF2DRC_SIG_DET_RMS - [15:11] */ 2833*4882a593Smuzhiyun #define WM8995_AIF2DRC_SIG_DET_RMS_WIDTH 5 /* AIF2DRC_SIG_DET_RMS - [15:11] */ 2834*4882a593Smuzhiyun #define WM8995_AIF2DRC_SIG_DET_PK_MASK 0x0600 /* AIF2DRC_SIG_DET_PK - [10:9] */ 2835*4882a593Smuzhiyun #define WM8995_AIF2DRC_SIG_DET_PK_SHIFT 9 /* AIF2DRC_SIG_DET_PK - [10:9] */ 2836*4882a593Smuzhiyun #define WM8995_AIF2DRC_SIG_DET_PK_WIDTH 2 /* AIF2DRC_SIG_DET_PK - [10:9] */ 2837*4882a593Smuzhiyun #define WM8995_AIF2DRC_NG_ENA 0x0100 /* AIF2DRC_NG_ENA */ 2838*4882a593Smuzhiyun #define WM8995_AIF2DRC_NG_ENA_MASK 0x0100 /* AIF2DRC_NG_ENA */ 2839*4882a593Smuzhiyun #define WM8995_AIF2DRC_NG_ENA_SHIFT 8 /* AIF2DRC_NG_ENA */ 2840*4882a593Smuzhiyun #define WM8995_AIF2DRC_NG_ENA_WIDTH 1 /* AIF2DRC_NG_ENA */ 2841*4882a593Smuzhiyun #define WM8995_AIF2DRC_SIG_DET_MODE 0x0080 /* AIF2DRC_SIG_DET_MODE */ 2842*4882a593Smuzhiyun #define WM8995_AIF2DRC_SIG_DET_MODE_MASK 0x0080 /* AIF2DRC_SIG_DET_MODE */ 2843*4882a593Smuzhiyun #define WM8995_AIF2DRC_SIG_DET_MODE_SHIFT 7 /* AIF2DRC_SIG_DET_MODE */ 2844*4882a593Smuzhiyun #define WM8995_AIF2DRC_SIG_DET_MODE_WIDTH 1 /* AIF2DRC_SIG_DET_MODE */ 2845*4882a593Smuzhiyun #define WM8995_AIF2DRC_SIG_DET 0x0040 /* AIF2DRC_SIG_DET */ 2846*4882a593Smuzhiyun #define WM8995_AIF2DRC_SIG_DET_MASK 0x0040 /* AIF2DRC_SIG_DET */ 2847*4882a593Smuzhiyun #define WM8995_AIF2DRC_SIG_DET_SHIFT 6 /* AIF2DRC_SIG_DET */ 2848*4882a593Smuzhiyun #define WM8995_AIF2DRC_SIG_DET_WIDTH 1 /* AIF2DRC_SIG_DET */ 2849*4882a593Smuzhiyun #define WM8995_AIF2DRC_KNEE2_OP_ENA 0x0020 /* AIF2DRC_KNEE2_OP_ENA */ 2850*4882a593Smuzhiyun #define WM8995_AIF2DRC_KNEE2_OP_ENA_MASK 0x0020 /* AIF2DRC_KNEE2_OP_ENA */ 2851*4882a593Smuzhiyun #define WM8995_AIF2DRC_KNEE2_OP_ENA_SHIFT 5 /* AIF2DRC_KNEE2_OP_ENA */ 2852*4882a593Smuzhiyun #define WM8995_AIF2DRC_KNEE2_OP_ENA_WIDTH 1 /* AIF2DRC_KNEE2_OP_ENA */ 2853*4882a593Smuzhiyun #define WM8995_AIF2DRC_QR 0x0010 /* AIF2DRC_QR */ 2854*4882a593Smuzhiyun #define WM8995_AIF2DRC_QR_MASK 0x0010 /* AIF2DRC_QR */ 2855*4882a593Smuzhiyun #define WM8995_AIF2DRC_QR_SHIFT 4 /* AIF2DRC_QR */ 2856*4882a593Smuzhiyun #define WM8995_AIF2DRC_QR_WIDTH 1 /* AIF2DRC_QR */ 2857*4882a593Smuzhiyun #define WM8995_AIF2DRC_ANTICLIP 0x0008 /* AIF2DRC_ANTICLIP */ 2858*4882a593Smuzhiyun #define WM8995_AIF2DRC_ANTICLIP_MASK 0x0008 /* AIF2DRC_ANTICLIP */ 2859*4882a593Smuzhiyun #define WM8995_AIF2DRC_ANTICLIP_SHIFT 3 /* AIF2DRC_ANTICLIP */ 2860*4882a593Smuzhiyun #define WM8995_AIF2DRC_ANTICLIP_WIDTH 1 /* AIF2DRC_ANTICLIP */ 2861*4882a593Smuzhiyun #define WM8995_AIF2DAC_DRC_ENA 0x0004 /* AIF2DAC_DRC_ENA */ 2862*4882a593Smuzhiyun #define WM8995_AIF2DAC_DRC_ENA_MASK 0x0004 /* AIF2DAC_DRC_ENA */ 2863*4882a593Smuzhiyun #define WM8995_AIF2DAC_DRC_ENA_SHIFT 2 /* AIF2DAC_DRC_ENA */ 2864*4882a593Smuzhiyun #define WM8995_AIF2DAC_DRC_ENA_WIDTH 1 /* AIF2DAC_DRC_ENA */ 2865*4882a593Smuzhiyun #define WM8995_AIF2ADCL_DRC_ENA 0x0002 /* AIF2ADCL_DRC_ENA */ 2866*4882a593Smuzhiyun #define WM8995_AIF2ADCL_DRC_ENA_MASK 0x0002 /* AIF2ADCL_DRC_ENA */ 2867*4882a593Smuzhiyun #define WM8995_AIF2ADCL_DRC_ENA_SHIFT 1 /* AIF2ADCL_DRC_ENA */ 2868*4882a593Smuzhiyun #define WM8995_AIF2ADCL_DRC_ENA_WIDTH 1 /* AIF2ADCL_DRC_ENA */ 2869*4882a593Smuzhiyun #define WM8995_AIF2ADCR_DRC_ENA 0x0001 /* AIF2ADCR_DRC_ENA */ 2870*4882a593Smuzhiyun #define WM8995_AIF2ADCR_DRC_ENA_MASK 0x0001 /* AIF2ADCR_DRC_ENA */ 2871*4882a593Smuzhiyun #define WM8995_AIF2ADCR_DRC_ENA_SHIFT 0 /* AIF2ADCR_DRC_ENA */ 2872*4882a593Smuzhiyun #define WM8995_AIF2ADCR_DRC_ENA_WIDTH 1 /* AIF2ADCR_DRC_ENA */ 2873*4882a593Smuzhiyun 2874*4882a593Smuzhiyun /* 2875*4882a593Smuzhiyun * R1345 (0x541) - AIF2 DRC (2) 2876*4882a593Smuzhiyun */ 2877*4882a593Smuzhiyun #define WM8995_AIF2DRC_ATK_MASK 0x1E00 /* AIF2DRC_ATK - [12:9] */ 2878*4882a593Smuzhiyun #define WM8995_AIF2DRC_ATK_SHIFT 9 /* AIF2DRC_ATK - [12:9] */ 2879*4882a593Smuzhiyun #define WM8995_AIF2DRC_ATK_WIDTH 4 /* AIF2DRC_ATK - [12:9] */ 2880*4882a593Smuzhiyun #define WM8995_AIF2DRC_DCY_MASK 0x01E0 /* AIF2DRC_DCY - [8:5] */ 2881*4882a593Smuzhiyun #define WM8995_AIF2DRC_DCY_SHIFT 5 /* AIF2DRC_DCY - [8:5] */ 2882*4882a593Smuzhiyun #define WM8995_AIF2DRC_DCY_WIDTH 4 /* AIF2DRC_DCY - [8:5] */ 2883*4882a593Smuzhiyun #define WM8995_AIF2DRC_MINGAIN_MASK 0x001C /* AIF2DRC_MINGAIN - [4:2] */ 2884*4882a593Smuzhiyun #define WM8995_AIF2DRC_MINGAIN_SHIFT 2 /* AIF2DRC_MINGAIN - [4:2] */ 2885*4882a593Smuzhiyun #define WM8995_AIF2DRC_MINGAIN_WIDTH 3 /* AIF2DRC_MINGAIN - [4:2] */ 2886*4882a593Smuzhiyun #define WM8995_AIF2DRC_MAXGAIN_MASK 0x0003 /* AIF2DRC_MAXGAIN - [1:0] */ 2887*4882a593Smuzhiyun #define WM8995_AIF2DRC_MAXGAIN_SHIFT 0 /* AIF2DRC_MAXGAIN - [1:0] */ 2888*4882a593Smuzhiyun #define WM8995_AIF2DRC_MAXGAIN_WIDTH 2 /* AIF2DRC_MAXGAIN - [1:0] */ 2889*4882a593Smuzhiyun 2890*4882a593Smuzhiyun /* 2891*4882a593Smuzhiyun * R1346 (0x542) - AIF2 DRC (3) 2892*4882a593Smuzhiyun */ 2893*4882a593Smuzhiyun #define WM8995_AIF2DRC_NG_MINGAIN_MASK 0xF000 /* AIF2DRC_NG_MINGAIN - [15:12] */ 2894*4882a593Smuzhiyun #define WM8995_AIF2DRC_NG_MINGAIN_SHIFT 12 /* AIF2DRC_NG_MINGAIN - [15:12] */ 2895*4882a593Smuzhiyun #define WM8995_AIF2DRC_NG_MINGAIN_WIDTH 4 /* AIF2DRC_NG_MINGAIN - [15:12] */ 2896*4882a593Smuzhiyun #define WM8995_AIF2DRC_NG_EXP_MASK 0x0C00 /* AIF2DRC_NG_EXP - [11:10] */ 2897*4882a593Smuzhiyun #define WM8995_AIF2DRC_NG_EXP_SHIFT 10 /* AIF2DRC_NG_EXP - [11:10] */ 2898*4882a593Smuzhiyun #define WM8995_AIF2DRC_NG_EXP_WIDTH 2 /* AIF2DRC_NG_EXP - [11:10] */ 2899*4882a593Smuzhiyun #define WM8995_AIF2DRC_QR_THR_MASK 0x0300 /* AIF2DRC_QR_THR - [9:8] */ 2900*4882a593Smuzhiyun #define WM8995_AIF2DRC_QR_THR_SHIFT 8 /* AIF2DRC_QR_THR - [9:8] */ 2901*4882a593Smuzhiyun #define WM8995_AIF2DRC_QR_THR_WIDTH 2 /* AIF2DRC_QR_THR - [9:8] */ 2902*4882a593Smuzhiyun #define WM8995_AIF2DRC_QR_DCY_MASK 0x00C0 /* AIF2DRC_QR_DCY - [7:6] */ 2903*4882a593Smuzhiyun #define WM8995_AIF2DRC_QR_DCY_SHIFT 6 /* AIF2DRC_QR_DCY - [7:6] */ 2904*4882a593Smuzhiyun #define WM8995_AIF2DRC_QR_DCY_WIDTH 2 /* AIF2DRC_QR_DCY - [7:6] */ 2905*4882a593Smuzhiyun #define WM8995_AIF2DRC_HI_COMP_MASK 0x0038 /* AIF2DRC_HI_COMP - [5:3] */ 2906*4882a593Smuzhiyun #define WM8995_AIF2DRC_HI_COMP_SHIFT 3 /* AIF2DRC_HI_COMP - [5:3] */ 2907*4882a593Smuzhiyun #define WM8995_AIF2DRC_HI_COMP_WIDTH 3 /* AIF2DRC_HI_COMP - [5:3] */ 2908*4882a593Smuzhiyun #define WM8995_AIF2DRC_LO_COMP_MASK 0x0007 /* AIF2DRC_LO_COMP - [2:0] */ 2909*4882a593Smuzhiyun #define WM8995_AIF2DRC_LO_COMP_SHIFT 0 /* AIF2DRC_LO_COMP - [2:0] */ 2910*4882a593Smuzhiyun #define WM8995_AIF2DRC_LO_COMP_WIDTH 3 /* AIF2DRC_LO_COMP - [2:0] */ 2911*4882a593Smuzhiyun 2912*4882a593Smuzhiyun /* 2913*4882a593Smuzhiyun * R1347 (0x543) - AIF2 DRC (4) 2914*4882a593Smuzhiyun */ 2915*4882a593Smuzhiyun #define WM8995_AIF2DRC_KNEE_IP_MASK 0x07E0 /* AIF2DRC_KNEE_IP - [10:5] */ 2916*4882a593Smuzhiyun #define WM8995_AIF2DRC_KNEE_IP_SHIFT 5 /* AIF2DRC_KNEE_IP - [10:5] */ 2917*4882a593Smuzhiyun #define WM8995_AIF2DRC_KNEE_IP_WIDTH 6 /* AIF2DRC_KNEE_IP - [10:5] */ 2918*4882a593Smuzhiyun #define WM8995_AIF2DRC_KNEE_OP_MASK 0x001F /* AIF2DRC_KNEE_OP - [4:0] */ 2919*4882a593Smuzhiyun #define WM8995_AIF2DRC_KNEE_OP_SHIFT 0 /* AIF2DRC_KNEE_OP - [4:0] */ 2920*4882a593Smuzhiyun #define WM8995_AIF2DRC_KNEE_OP_WIDTH 5 /* AIF2DRC_KNEE_OP - [4:0] */ 2921*4882a593Smuzhiyun 2922*4882a593Smuzhiyun /* 2923*4882a593Smuzhiyun * R1348 (0x544) - AIF2 DRC (5) 2924*4882a593Smuzhiyun */ 2925*4882a593Smuzhiyun #define WM8995_AIF2DRC_KNEE2_IP_MASK 0x03E0 /* AIF2DRC_KNEE2_IP - [9:5] */ 2926*4882a593Smuzhiyun #define WM8995_AIF2DRC_KNEE2_IP_SHIFT 5 /* AIF2DRC_KNEE2_IP - [9:5] */ 2927*4882a593Smuzhiyun #define WM8995_AIF2DRC_KNEE2_IP_WIDTH 5 /* AIF2DRC_KNEE2_IP - [9:5] */ 2928*4882a593Smuzhiyun #define WM8995_AIF2DRC_KNEE2_OP_MASK 0x001F /* AIF2DRC_KNEE2_OP - [4:0] */ 2929*4882a593Smuzhiyun #define WM8995_AIF2DRC_KNEE2_OP_SHIFT 0 /* AIF2DRC_KNEE2_OP - [4:0] */ 2930*4882a593Smuzhiyun #define WM8995_AIF2DRC_KNEE2_OP_WIDTH 5 /* AIF2DRC_KNEE2_OP - [4:0] */ 2931*4882a593Smuzhiyun 2932*4882a593Smuzhiyun /* 2933*4882a593Smuzhiyun * R1408 (0x580) - AIF2 EQ Gains (1) 2934*4882a593Smuzhiyun */ 2935*4882a593Smuzhiyun #define WM8995_AIF2DAC_EQ_B1_GAIN_MASK 0xF800 /* AIF2DAC_EQ_B1_GAIN - [15:11] */ 2936*4882a593Smuzhiyun #define WM8995_AIF2DAC_EQ_B1_GAIN_SHIFT 11 /* AIF2DAC_EQ_B1_GAIN - [15:11] */ 2937*4882a593Smuzhiyun #define WM8995_AIF2DAC_EQ_B1_GAIN_WIDTH 5 /* AIF2DAC_EQ_B1_GAIN - [15:11] */ 2938*4882a593Smuzhiyun #define WM8995_AIF2DAC_EQ_B2_GAIN_MASK 0x07C0 /* AIF2DAC_EQ_B2_GAIN - [10:6] */ 2939*4882a593Smuzhiyun #define WM8995_AIF2DAC_EQ_B2_GAIN_SHIFT 6 /* AIF2DAC_EQ_B2_GAIN - [10:6] */ 2940*4882a593Smuzhiyun #define WM8995_AIF2DAC_EQ_B2_GAIN_WIDTH 5 /* AIF2DAC_EQ_B2_GAIN - [10:6] */ 2941*4882a593Smuzhiyun #define WM8995_AIF2DAC_EQ_B3_GAIN_MASK 0x003E /* AIF2DAC_EQ_B3_GAIN - [5:1] */ 2942*4882a593Smuzhiyun #define WM8995_AIF2DAC_EQ_B3_GAIN_SHIFT 1 /* AIF2DAC_EQ_B3_GAIN - [5:1] */ 2943*4882a593Smuzhiyun #define WM8995_AIF2DAC_EQ_B3_GAIN_WIDTH 5 /* AIF2DAC_EQ_B3_GAIN - [5:1] */ 2944*4882a593Smuzhiyun #define WM8995_AIF2DAC_EQ_ENA 0x0001 /* AIF2DAC_EQ_ENA */ 2945*4882a593Smuzhiyun #define WM8995_AIF2DAC_EQ_ENA_MASK 0x0001 /* AIF2DAC_EQ_ENA */ 2946*4882a593Smuzhiyun #define WM8995_AIF2DAC_EQ_ENA_SHIFT 0 /* AIF2DAC_EQ_ENA */ 2947*4882a593Smuzhiyun #define WM8995_AIF2DAC_EQ_ENA_WIDTH 1 /* AIF2DAC_EQ_ENA */ 2948*4882a593Smuzhiyun 2949*4882a593Smuzhiyun /* 2950*4882a593Smuzhiyun * R1409 (0x581) - AIF2 EQ Gains (2) 2951*4882a593Smuzhiyun */ 2952*4882a593Smuzhiyun #define WM8995_AIF2DAC_EQ_B4_GAIN_MASK 0xF800 /* AIF2DAC_EQ_B4_GAIN - [15:11] */ 2953*4882a593Smuzhiyun #define WM8995_AIF2DAC_EQ_B4_GAIN_SHIFT 11 /* AIF2DAC_EQ_B4_GAIN - [15:11] */ 2954*4882a593Smuzhiyun #define WM8995_AIF2DAC_EQ_B4_GAIN_WIDTH 5 /* AIF2DAC_EQ_B4_GAIN - [15:11] */ 2955*4882a593Smuzhiyun #define WM8995_AIF2DAC_EQ_B5_GAIN_MASK 0x07C0 /* AIF2DAC_EQ_B5_GAIN - [10:6] */ 2956*4882a593Smuzhiyun #define WM8995_AIF2DAC_EQ_B5_GAIN_SHIFT 6 /* AIF2DAC_EQ_B5_GAIN - [10:6] */ 2957*4882a593Smuzhiyun #define WM8995_AIF2DAC_EQ_B5_GAIN_WIDTH 5 /* AIF2DAC_EQ_B5_GAIN - [10:6] */ 2958*4882a593Smuzhiyun 2959*4882a593Smuzhiyun /* 2960*4882a593Smuzhiyun * R1410 (0x582) - AIF2 EQ Band 1 A 2961*4882a593Smuzhiyun */ 2962*4882a593Smuzhiyun #define WM8995_AIF2DAC_EQ_B1_A_MASK 0xFFFF /* AIF2DAC_EQ_B1_A - [15:0] */ 2963*4882a593Smuzhiyun #define WM8995_AIF2DAC_EQ_B1_A_SHIFT 0 /* AIF2DAC_EQ_B1_A - [15:0] */ 2964*4882a593Smuzhiyun #define WM8995_AIF2DAC_EQ_B1_A_WIDTH 16 /* AIF2DAC_EQ_B1_A - [15:0] */ 2965*4882a593Smuzhiyun 2966*4882a593Smuzhiyun /* 2967*4882a593Smuzhiyun * R1411 (0x583) - AIF2 EQ Band 1 B 2968*4882a593Smuzhiyun */ 2969*4882a593Smuzhiyun #define WM8995_AIF2DAC_EQ_B1_B_MASK 0xFFFF /* AIF2DAC_EQ_B1_B - [15:0] */ 2970*4882a593Smuzhiyun #define WM8995_AIF2DAC_EQ_B1_B_SHIFT 0 /* AIF2DAC_EQ_B1_B - [15:0] */ 2971*4882a593Smuzhiyun #define WM8995_AIF2DAC_EQ_B1_B_WIDTH 16 /* AIF2DAC_EQ_B1_B - [15:0] */ 2972*4882a593Smuzhiyun 2973*4882a593Smuzhiyun /* 2974*4882a593Smuzhiyun * R1412 (0x584) - AIF2 EQ Band 1 PG 2975*4882a593Smuzhiyun */ 2976*4882a593Smuzhiyun #define WM8995_AIF2DAC_EQ_B1_PG_MASK 0xFFFF /* AIF2DAC_EQ_B1_PG - [15:0] */ 2977*4882a593Smuzhiyun #define WM8995_AIF2DAC_EQ_B1_PG_SHIFT 0 /* AIF2DAC_EQ_B1_PG - [15:0] */ 2978*4882a593Smuzhiyun #define WM8995_AIF2DAC_EQ_B1_PG_WIDTH 16 /* AIF2DAC_EQ_B1_PG - [15:0] */ 2979*4882a593Smuzhiyun 2980*4882a593Smuzhiyun /* 2981*4882a593Smuzhiyun * R1413 (0x585) - AIF2 EQ Band 2 A 2982*4882a593Smuzhiyun */ 2983*4882a593Smuzhiyun #define WM8995_AIF2DAC_EQ_B2_A_MASK 0xFFFF /* AIF2DAC_EQ_B2_A - [15:0] */ 2984*4882a593Smuzhiyun #define WM8995_AIF2DAC_EQ_B2_A_SHIFT 0 /* AIF2DAC_EQ_B2_A - [15:0] */ 2985*4882a593Smuzhiyun #define WM8995_AIF2DAC_EQ_B2_A_WIDTH 16 /* AIF2DAC_EQ_B2_A - [15:0] */ 2986*4882a593Smuzhiyun 2987*4882a593Smuzhiyun /* 2988*4882a593Smuzhiyun * R1414 (0x586) - AIF2 EQ Band 2 B 2989*4882a593Smuzhiyun */ 2990*4882a593Smuzhiyun #define WM8995_AIF2DAC_EQ_B2_B_MASK 0xFFFF /* AIF2DAC_EQ_B2_B - [15:0] */ 2991*4882a593Smuzhiyun #define WM8995_AIF2DAC_EQ_B2_B_SHIFT 0 /* AIF2DAC_EQ_B2_B - [15:0] */ 2992*4882a593Smuzhiyun #define WM8995_AIF2DAC_EQ_B2_B_WIDTH 16 /* AIF2DAC_EQ_B2_B - [15:0] */ 2993*4882a593Smuzhiyun 2994*4882a593Smuzhiyun /* 2995*4882a593Smuzhiyun * R1415 (0x587) - AIF2 EQ Band 2 C 2996*4882a593Smuzhiyun */ 2997*4882a593Smuzhiyun #define WM8995_AIF2DAC_EQ_B2_C_MASK 0xFFFF /* AIF2DAC_EQ_B2_C - [15:0] */ 2998*4882a593Smuzhiyun #define WM8995_AIF2DAC_EQ_B2_C_SHIFT 0 /* AIF2DAC_EQ_B2_C - [15:0] */ 2999*4882a593Smuzhiyun #define WM8995_AIF2DAC_EQ_B2_C_WIDTH 16 /* AIF2DAC_EQ_B2_C - [15:0] */ 3000*4882a593Smuzhiyun 3001*4882a593Smuzhiyun /* 3002*4882a593Smuzhiyun * R1416 (0x588) - AIF2 EQ Band 2 PG 3003*4882a593Smuzhiyun */ 3004*4882a593Smuzhiyun #define WM8995_AIF2DAC_EQ_B2_PG_MASK 0xFFFF /* AIF2DAC_EQ_B2_PG - [15:0] */ 3005*4882a593Smuzhiyun #define WM8995_AIF2DAC_EQ_B2_PG_SHIFT 0 /* AIF2DAC_EQ_B2_PG - [15:0] */ 3006*4882a593Smuzhiyun #define WM8995_AIF2DAC_EQ_B2_PG_WIDTH 16 /* AIF2DAC_EQ_B2_PG - [15:0] */ 3007*4882a593Smuzhiyun 3008*4882a593Smuzhiyun /* 3009*4882a593Smuzhiyun * R1417 (0x589) - AIF2 EQ Band 3 A 3010*4882a593Smuzhiyun */ 3011*4882a593Smuzhiyun #define WM8995_AIF2DAC_EQ_B3_A_MASK 0xFFFF /* AIF2DAC_EQ_B3_A - [15:0] */ 3012*4882a593Smuzhiyun #define WM8995_AIF2DAC_EQ_B3_A_SHIFT 0 /* AIF2DAC_EQ_B3_A - [15:0] */ 3013*4882a593Smuzhiyun #define WM8995_AIF2DAC_EQ_B3_A_WIDTH 16 /* AIF2DAC_EQ_B3_A - [15:0] */ 3014*4882a593Smuzhiyun 3015*4882a593Smuzhiyun /* 3016*4882a593Smuzhiyun * R1418 (0x58A) - AIF2 EQ Band 3 B 3017*4882a593Smuzhiyun */ 3018*4882a593Smuzhiyun #define WM8995_AIF2DAC_EQ_B3_B_MASK 0xFFFF /* AIF2DAC_EQ_B3_B - [15:0] */ 3019*4882a593Smuzhiyun #define WM8995_AIF2DAC_EQ_B3_B_SHIFT 0 /* AIF2DAC_EQ_B3_B - [15:0] */ 3020*4882a593Smuzhiyun #define WM8995_AIF2DAC_EQ_B3_B_WIDTH 16 /* AIF2DAC_EQ_B3_B - [15:0] */ 3021*4882a593Smuzhiyun 3022*4882a593Smuzhiyun /* 3023*4882a593Smuzhiyun * R1419 (0x58B) - AIF2 EQ Band 3 C 3024*4882a593Smuzhiyun */ 3025*4882a593Smuzhiyun #define WM8995_AIF2DAC_EQ_B3_C_MASK 0xFFFF /* AIF2DAC_EQ_B3_C - [15:0] */ 3026*4882a593Smuzhiyun #define WM8995_AIF2DAC_EQ_B3_C_SHIFT 0 /* AIF2DAC_EQ_B3_C - [15:0] */ 3027*4882a593Smuzhiyun #define WM8995_AIF2DAC_EQ_B3_C_WIDTH 16 /* AIF2DAC_EQ_B3_C - [15:0] */ 3028*4882a593Smuzhiyun 3029*4882a593Smuzhiyun /* 3030*4882a593Smuzhiyun * R1420 (0x58C) - AIF2 EQ Band 3 PG 3031*4882a593Smuzhiyun */ 3032*4882a593Smuzhiyun #define WM8995_AIF2DAC_EQ_B3_PG_MASK 0xFFFF /* AIF2DAC_EQ_B3_PG - [15:0] */ 3033*4882a593Smuzhiyun #define WM8995_AIF2DAC_EQ_B3_PG_SHIFT 0 /* AIF2DAC_EQ_B3_PG - [15:0] */ 3034*4882a593Smuzhiyun #define WM8995_AIF2DAC_EQ_B3_PG_WIDTH 16 /* AIF2DAC_EQ_B3_PG - [15:0] */ 3035*4882a593Smuzhiyun 3036*4882a593Smuzhiyun /* 3037*4882a593Smuzhiyun * R1421 (0x58D) - AIF2 EQ Band 4 A 3038*4882a593Smuzhiyun */ 3039*4882a593Smuzhiyun #define WM8995_AIF2DAC_EQ_B4_A_MASK 0xFFFF /* AIF2DAC_EQ_B4_A - [15:0] */ 3040*4882a593Smuzhiyun #define WM8995_AIF2DAC_EQ_B4_A_SHIFT 0 /* AIF2DAC_EQ_B4_A - [15:0] */ 3041*4882a593Smuzhiyun #define WM8995_AIF2DAC_EQ_B4_A_WIDTH 16 /* AIF2DAC_EQ_B4_A - [15:0] */ 3042*4882a593Smuzhiyun 3043*4882a593Smuzhiyun /* 3044*4882a593Smuzhiyun * R1422 (0x58E) - AIF2 EQ Band 4 B 3045*4882a593Smuzhiyun */ 3046*4882a593Smuzhiyun #define WM8995_AIF2DAC_EQ_B4_B_MASK 0xFFFF /* AIF2DAC_EQ_B4_B - [15:0] */ 3047*4882a593Smuzhiyun #define WM8995_AIF2DAC_EQ_B4_B_SHIFT 0 /* AIF2DAC_EQ_B4_B - [15:0] */ 3048*4882a593Smuzhiyun #define WM8995_AIF2DAC_EQ_B4_B_WIDTH 16 /* AIF2DAC_EQ_B4_B - [15:0] */ 3049*4882a593Smuzhiyun 3050*4882a593Smuzhiyun /* 3051*4882a593Smuzhiyun * R1423 (0x58F) - AIF2 EQ Band 4 C 3052*4882a593Smuzhiyun */ 3053*4882a593Smuzhiyun #define WM8995_AIF2DAC_EQ_B4_C_MASK 0xFFFF /* AIF2DAC_EQ_B4_C - [15:0] */ 3054*4882a593Smuzhiyun #define WM8995_AIF2DAC_EQ_B4_C_SHIFT 0 /* AIF2DAC_EQ_B4_C - [15:0] */ 3055*4882a593Smuzhiyun #define WM8995_AIF2DAC_EQ_B4_C_WIDTH 16 /* AIF2DAC_EQ_B4_C - [15:0] */ 3056*4882a593Smuzhiyun 3057*4882a593Smuzhiyun /* 3058*4882a593Smuzhiyun * R1424 (0x590) - AIF2 EQ Band 4 PG 3059*4882a593Smuzhiyun */ 3060*4882a593Smuzhiyun #define WM8995_AIF2DAC_EQ_B4_PG_MASK 0xFFFF /* AIF2DAC_EQ_B4_PG - [15:0] */ 3061*4882a593Smuzhiyun #define WM8995_AIF2DAC_EQ_B4_PG_SHIFT 0 /* AIF2DAC_EQ_B4_PG - [15:0] */ 3062*4882a593Smuzhiyun #define WM8995_AIF2DAC_EQ_B4_PG_WIDTH 16 /* AIF2DAC_EQ_B4_PG - [15:0] */ 3063*4882a593Smuzhiyun 3064*4882a593Smuzhiyun /* 3065*4882a593Smuzhiyun * R1425 (0x591) - AIF2 EQ Band 5 A 3066*4882a593Smuzhiyun */ 3067*4882a593Smuzhiyun #define WM8995_AIF2DAC_EQ_B5_A_MASK 0xFFFF /* AIF2DAC_EQ_B5_A - [15:0] */ 3068*4882a593Smuzhiyun #define WM8995_AIF2DAC_EQ_B5_A_SHIFT 0 /* AIF2DAC_EQ_B5_A - [15:0] */ 3069*4882a593Smuzhiyun #define WM8995_AIF2DAC_EQ_B5_A_WIDTH 16 /* AIF2DAC_EQ_B5_A - [15:0] */ 3070*4882a593Smuzhiyun 3071*4882a593Smuzhiyun /* 3072*4882a593Smuzhiyun * R1426 (0x592) - AIF2 EQ Band 5 B 3073*4882a593Smuzhiyun */ 3074*4882a593Smuzhiyun #define WM8995_AIF2DAC_EQ_B5_B_MASK 0xFFFF /* AIF2DAC_EQ_B5_B - [15:0] */ 3075*4882a593Smuzhiyun #define WM8995_AIF2DAC_EQ_B5_B_SHIFT 0 /* AIF2DAC_EQ_B5_B - [15:0] */ 3076*4882a593Smuzhiyun #define WM8995_AIF2DAC_EQ_B5_B_WIDTH 16 /* AIF2DAC_EQ_B5_B - [15:0] */ 3077*4882a593Smuzhiyun 3078*4882a593Smuzhiyun /* 3079*4882a593Smuzhiyun * R1427 (0x593) - AIF2 EQ Band 5 PG 3080*4882a593Smuzhiyun */ 3081*4882a593Smuzhiyun #define WM8995_AIF2DAC_EQ_B5_PG_MASK 0xFFFF /* AIF2DAC_EQ_B5_PG - [15:0] */ 3082*4882a593Smuzhiyun #define WM8995_AIF2DAC_EQ_B5_PG_SHIFT 0 /* AIF2DAC_EQ_B5_PG - [15:0] */ 3083*4882a593Smuzhiyun #define WM8995_AIF2DAC_EQ_B5_PG_WIDTH 16 /* AIF2DAC_EQ_B5_PG - [15:0] */ 3084*4882a593Smuzhiyun 3085*4882a593Smuzhiyun /* 3086*4882a593Smuzhiyun * R1536 (0x600) - DAC1 Mixer Volumes 3087*4882a593Smuzhiyun */ 3088*4882a593Smuzhiyun #define WM8995_ADCR_DAC1_VOL_MASK 0x03E0 /* ADCR_DAC1_VOL - [9:5] */ 3089*4882a593Smuzhiyun #define WM8995_ADCR_DAC1_VOL_SHIFT 5 /* ADCR_DAC1_VOL - [9:5] */ 3090*4882a593Smuzhiyun #define WM8995_ADCR_DAC1_VOL_WIDTH 5 /* ADCR_DAC1_VOL - [9:5] */ 3091*4882a593Smuzhiyun #define WM8995_ADCL_DAC1_VOL_MASK 0x001F /* ADCL_DAC1_VOL - [4:0] */ 3092*4882a593Smuzhiyun #define WM8995_ADCL_DAC1_VOL_SHIFT 0 /* ADCL_DAC1_VOL - [4:0] */ 3093*4882a593Smuzhiyun #define WM8995_ADCL_DAC1_VOL_WIDTH 5 /* ADCL_DAC1_VOL - [4:0] */ 3094*4882a593Smuzhiyun 3095*4882a593Smuzhiyun /* 3096*4882a593Smuzhiyun * R1537 (0x601) - DAC1 Left Mixer Routing 3097*4882a593Smuzhiyun */ 3098*4882a593Smuzhiyun #define WM8995_ADCR_TO_DAC1L 0x0020 /* ADCR_TO_DAC1L */ 3099*4882a593Smuzhiyun #define WM8995_ADCR_TO_DAC1L_MASK 0x0020 /* ADCR_TO_DAC1L */ 3100*4882a593Smuzhiyun #define WM8995_ADCR_TO_DAC1L_SHIFT 5 /* ADCR_TO_DAC1L */ 3101*4882a593Smuzhiyun #define WM8995_ADCR_TO_DAC1L_WIDTH 1 /* ADCR_TO_DAC1L */ 3102*4882a593Smuzhiyun #define WM8995_ADCL_TO_DAC1L 0x0010 /* ADCL_TO_DAC1L */ 3103*4882a593Smuzhiyun #define WM8995_ADCL_TO_DAC1L_MASK 0x0010 /* ADCL_TO_DAC1L */ 3104*4882a593Smuzhiyun #define WM8995_ADCL_TO_DAC1L_SHIFT 4 /* ADCL_TO_DAC1L */ 3105*4882a593Smuzhiyun #define WM8995_ADCL_TO_DAC1L_WIDTH 1 /* ADCL_TO_DAC1L */ 3106*4882a593Smuzhiyun #define WM8995_AIF2DACL_TO_DAC1L 0x0004 /* AIF2DACL_TO_DAC1L */ 3107*4882a593Smuzhiyun #define WM8995_AIF2DACL_TO_DAC1L_MASK 0x0004 /* AIF2DACL_TO_DAC1L */ 3108*4882a593Smuzhiyun #define WM8995_AIF2DACL_TO_DAC1L_SHIFT 2 /* AIF2DACL_TO_DAC1L */ 3109*4882a593Smuzhiyun #define WM8995_AIF2DACL_TO_DAC1L_WIDTH 1 /* AIF2DACL_TO_DAC1L */ 3110*4882a593Smuzhiyun #define WM8995_AIF1DAC2L_TO_DAC1L 0x0002 /* AIF1DAC2L_TO_DAC1L */ 3111*4882a593Smuzhiyun #define WM8995_AIF1DAC2L_TO_DAC1L_MASK 0x0002 /* AIF1DAC2L_TO_DAC1L */ 3112*4882a593Smuzhiyun #define WM8995_AIF1DAC2L_TO_DAC1L_SHIFT 1 /* AIF1DAC2L_TO_DAC1L */ 3113*4882a593Smuzhiyun #define WM8995_AIF1DAC2L_TO_DAC1L_WIDTH 1 /* AIF1DAC2L_TO_DAC1L */ 3114*4882a593Smuzhiyun #define WM8995_AIF1DAC1L_TO_DAC1L 0x0001 /* AIF1DAC1L_TO_DAC1L */ 3115*4882a593Smuzhiyun #define WM8995_AIF1DAC1L_TO_DAC1L_MASK 0x0001 /* AIF1DAC1L_TO_DAC1L */ 3116*4882a593Smuzhiyun #define WM8995_AIF1DAC1L_TO_DAC1L_SHIFT 0 /* AIF1DAC1L_TO_DAC1L */ 3117*4882a593Smuzhiyun #define WM8995_AIF1DAC1L_TO_DAC1L_WIDTH 1 /* AIF1DAC1L_TO_DAC1L */ 3118*4882a593Smuzhiyun 3119*4882a593Smuzhiyun /* 3120*4882a593Smuzhiyun * R1538 (0x602) - DAC1 Right Mixer Routing 3121*4882a593Smuzhiyun */ 3122*4882a593Smuzhiyun #define WM8995_ADCR_TO_DAC1R 0x0020 /* ADCR_TO_DAC1R */ 3123*4882a593Smuzhiyun #define WM8995_ADCR_TO_DAC1R_MASK 0x0020 /* ADCR_TO_DAC1R */ 3124*4882a593Smuzhiyun #define WM8995_ADCR_TO_DAC1R_SHIFT 5 /* ADCR_TO_DAC1R */ 3125*4882a593Smuzhiyun #define WM8995_ADCR_TO_DAC1R_WIDTH 1 /* ADCR_TO_DAC1R */ 3126*4882a593Smuzhiyun #define WM8995_ADCL_TO_DAC1R 0x0010 /* ADCL_TO_DAC1R */ 3127*4882a593Smuzhiyun #define WM8995_ADCL_TO_DAC1R_MASK 0x0010 /* ADCL_TO_DAC1R */ 3128*4882a593Smuzhiyun #define WM8995_ADCL_TO_DAC1R_SHIFT 4 /* ADCL_TO_DAC1R */ 3129*4882a593Smuzhiyun #define WM8995_ADCL_TO_DAC1R_WIDTH 1 /* ADCL_TO_DAC1R */ 3130*4882a593Smuzhiyun #define WM8995_AIF2DACR_TO_DAC1R 0x0004 /* AIF2DACR_TO_DAC1R */ 3131*4882a593Smuzhiyun #define WM8995_AIF2DACR_TO_DAC1R_MASK 0x0004 /* AIF2DACR_TO_DAC1R */ 3132*4882a593Smuzhiyun #define WM8995_AIF2DACR_TO_DAC1R_SHIFT 2 /* AIF2DACR_TO_DAC1R */ 3133*4882a593Smuzhiyun #define WM8995_AIF2DACR_TO_DAC1R_WIDTH 1 /* AIF2DACR_TO_DAC1R */ 3134*4882a593Smuzhiyun #define WM8995_AIF1DAC2R_TO_DAC1R 0x0002 /* AIF1DAC2R_TO_DAC1R */ 3135*4882a593Smuzhiyun #define WM8995_AIF1DAC2R_TO_DAC1R_MASK 0x0002 /* AIF1DAC2R_TO_DAC1R */ 3136*4882a593Smuzhiyun #define WM8995_AIF1DAC2R_TO_DAC1R_SHIFT 1 /* AIF1DAC2R_TO_DAC1R */ 3137*4882a593Smuzhiyun #define WM8995_AIF1DAC2R_TO_DAC1R_WIDTH 1 /* AIF1DAC2R_TO_DAC1R */ 3138*4882a593Smuzhiyun #define WM8995_AIF1DAC1R_TO_DAC1R 0x0001 /* AIF1DAC1R_TO_DAC1R */ 3139*4882a593Smuzhiyun #define WM8995_AIF1DAC1R_TO_DAC1R_MASK 0x0001 /* AIF1DAC1R_TO_DAC1R */ 3140*4882a593Smuzhiyun #define WM8995_AIF1DAC1R_TO_DAC1R_SHIFT 0 /* AIF1DAC1R_TO_DAC1R */ 3141*4882a593Smuzhiyun #define WM8995_AIF1DAC1R_TO_DAC1R_WIDTH 1 /* AIF1DAC1R_TO_DAC1R */ 3142*4882a593Smuzhiyun 3143*4882a593Smuzhiyun /* 3144*4882a593Smuzhiyun * R1539 (0x603) - DAC2 Mixer Volumes 3145*4882a593Smuzhiyun */ 3146*4882a593Smuzhiyun #define WM8995_ADCR_DAC2_VOL_MASK 0x03E0 /* ADCR_DAC2_VOL - [9:5] */ 3147*4882a593Smuzhiyun #define WM8995_ADCR_DAC2_VOL_SHIFT 5 /* ADCR_DAC2_VOL - [9:5] */ 3148*4882a593Smuzhiyun #define WM8995_ADCR_DAC2_VOL_WIDTH 5 /* ADCR_DAC2_VOL - [9:5] */ 3149*4882a593Smuzhiyun #define WM8995_ADCL_DAC2_VOL_MASK 0x001F /* ADCL_DAC2_VOL - [4:0] */ 3150*4882a593Smuzhiyun #define WM8995_ADCL_DAC2_VOL_SHIFT 0 /* ADCL_DAC2_VOL - [4:0] */ 3151*4882a593Smuzhiyun #define WM8995_ADCL_DAC2_VOL_WIDTH 5 /* ADCL_DAC2_VOL - [4:0] */ 3152*4882a593Smuzhiyun 3153*4882a593Smuzhiyun /* 3154*4882a593Smuzhiyun * R1540 (0x604) - DAC2 Left Mixer Routing 3155*4882a593Smuzhiyun */ 3156*4882a593Smuzhiyun #define WM8995_ADCR_TO_DAC2L 0x0020 /* ADCR_TO_DAC2L */ 3157*4882a593Smuzhiyun #define WM8995_ADCR_TO_DAC2L_MASK 0x0020 /* ADCR_TO_DAC2L */ 3158*4882a593Smuzhiyun #define WM8995_ADCR_TO_DAC2L_SHIFT 5 /* ADCR_TO_DAC2L */ 3159*4882a593Smuzhiyun #define WM8995_ADCR_TO_DAC2L_WIDTH 1 /* ADCR_TO_DAC2L */ 3160*4882a593Smuzhiyun #define WM8995_ADCL_TO_DAC2L 0x0010 /* ADCL_TO_DAC2L */ 3161*4882a593Smuzhiyun #define WM8995_ADCL_TO_DAC2L_MASK 0x0010 /* ADCL_TO_DAC2L */ 3162*4882a593Smuzhiyun #define WM8995_ADCL_TO_DAC2L_SHIFT 4 /* ADCL_TO_DAC2L */ 3163*4882a593Smuzhiyun #define WM8995_ADCL_TO_DAC2L_WIDTH 1 /* ADCL_TO_DAC2L */ 3164*4882a593Smuzhiyun #define WM8995_AIF2DACL_TO_DAC2L 0x0004 /* AIF2DACL_TO_DAC2L */ 3165*4882a593Smuzhiyun #define WM8995_AIF2DACL_TO_DAC2L_MASK 0x0004 /* AIF2DACL_TO_DAC2L */ 3166*4882a593Smuzhiyun #define WM8995_AIF2DACL_TO_DAC2L_SHIFT 2 /* AIF2DACL_TO_DAC2L */ 3167*4882a593Smuzhiyun #define WM8995_AIF2DACL_TO_DAC2L_WIDTH 1 /* AIF2DACL_TO_DAC2L */ 3168*4882a593Smuzhiyun #define WM8995_AIF1DAC2L_TO_DAC2L 0x0002 /* AIF1DAC2L_TO_DAC2L */ 3169*4882a593Smuzhiyun #define WM8995_AIF1DAC2L_TO_DAC2L_MASK 0x0002 /* AIF1DAC2L_TO_DAC2L */ 3170*4882a593Smuzhiyun #define WM8995_AIF1DAC2L_TO_DAC2L_SHIFT 1 /* AIF1DAC2L_TO_DAC2L */ 3171*4882a593Smuzhiyun #define WM8995_AIF1DAC2L_TO_DAC2L_WIDTH 1 /* AIF1DAC2L_TO_DAC2L */ 3172*4882a593Smuzhiyun #define WM8995_AIF1DAC1L_TO_DAC2L 0x0001 /* AIF1DAC1L_TO_DAC2L */ 3173*4882a593Smuzhiyun #define WM8995_AIF1DAC1L_TO_DAC2L_MASK 0x0001 /* AIF1DAC1L_TO_DAC2L */ 3174*4882a593Smuzhiyun #define WM8995_AIF1DAC1L_TO_DAC2L_SHIFT 0 /* AIF1DAC1L_TO_DAC2L */ 3175*4882a593Smuzhiyun #define WM8995_AIF1DAC1L_TO_DAC2L_WIDTH 1 /* AIF1DAC1L_TO_DAC2L */ 3176*4882a593Smuzhiyun 3177*4882a593Smuzhiyun /* 3178*4882a593Smuzhiyun * R1541 (0x605) - DAC2 Right Mixer Routing 3179*4882a593Smuzhiyun */ 3180*4882a593Smuzhiyun #define WM8995_ADCR_TO_DAC2R 0x0020 /* ADCR_TO_DAC2R */ 3181*4882a593Smuzhiyun #define WM8995_ADCR_TO_DAC2R_MASK 0x0020 /* ADCR_TO_DAC2R */ 3182*4882a593Smuzhiyun #define WM8995_ADCR_TO_DAC2R_SHIFT 5 /* ADCR_TO_DAC2R */ 3183*4882a593Smuzhiyun #define WM8995_ADCR_TO_DAC2R_WIDTH 1 /* ADCR_TO_DAC2R */ 3184*4882a593Smuzhiyun #define WM8995_ADCL_TO_DAC2R 0x0010 /* ADCL_TO_DAC2R */ 3185*4882a593Smuzhiyun #define WM8995_ADCL_TO_DAC2R_MASK 0x0010 /* ADCL_TO_DAC2R */ 3186*4882a593Smuzhiyun #define WM8995_ADCL_TO_DAC2R_SHIFT 4 /* ADCL_TO_DAC2R */ 3187*4882a593Smuzhiyun #define WM8995_ADCL_TO_DAC2R_WIDTH 1 /* ADCL_TO_DAC2R */ 3188*4882a593Smuzhiyun #define WM8995_AIF2DACR_TO_DAC2R 0x0004 /* AIF2DACR_TO_DAC2R */ 3189*4882a593Smuzhiyun #define WM8995_AIF2DACR_TO_DAC2R_MASK 0x0004 /* AIF2DACR_TO_DAC2R */ 3190*4882a593Smuzhiyun #define WM8995_AIF2DACR_TO_DAC2R_SHIFT 2 /* AIF2DACR_TO_DAC2R */ 3191*4882a593Smuzhiyun #define WM8995_AIF2DACR_TO_DAC2R_WIDTH 1 /* AIF2DACR_TO_DAC2R */ 3192*4882a593Smuzhiyun #define WM8995_AIF1DAC2R_TO_DAC2R 0x0002 /* AIF1DAC2R_TO_DAC2R */ 3193*4882a593Smuzhiyun #define WM8995_AIF1DAC2R_TO_DAC2R_MASK 0x0002 /* AIF1DAC2R_TO_DAC2R */ 3194*4882a593Smuzhiyun #define WM8995_AIF1DAC2R_TO_DAC2R_SHIFT 1 /* AIF1DAC2R_TO_DAC2R */ 3195*4882a593Smuzhiyun #define WM8995_AIF1DAC2R_TO_DAC2R_WIDTH 1 /* AIF1DAC2R_TO_DAC2R */ 3196*4882a593Smuzhiyun #define WM8995_AIF1DAC1R_TO_DAC2R 0x0001 /* AIF1DAC1R_TO_DAC2R */ 3197*4882a593Smuzhiyun #define WM8995_AIF1DAC1R_TO_DAC2R_MASK 0x0001 /* AIF1DAC1R_TO_DAC2R */ 3198*4882a593Smuzhiyun #define WM8995_AIF1DAC1R_TO_DAC2R_SHIFT 0 /* AIF1DAC1R_TO_DAC2R */ 3199*4882a593Smuzhiyun #define WM8995_AIF1DAC1R_TO_DAC2R_WIDTH 1 /* AIF1DAC1R_TO_DAC2R */ 3200*4882a593Smuzhiyun 3201*4882a593Smuzhiyun /* 3202*4882a593Smuzhiyun * R1542 (0x606) - AIF1 ADC1 Left Mixer Routing 3203*4882a593Smuzhiyun */ 3204*4882a593Smuzhiyun #define WM8995_ADC1L_TO_AIF1ADC1L 0x0002 /* ADC1L_TO_AIF1ADC1L */ 3205*4882a593Smuzhiyun #define WM8995_ADC1L_TO_AIF1ADC1L_MASK 0x0002 /* ADC1L_TO_AIF1ADC1L */ 3206*4882a593Smuzhiyun #define WM8995_ADC1L_TO_AIF1ADC1L_SHIFT 1 /* ADC1L_TO_AIF1ADC1L */ 3207*4882a593Smuzhiyun #define WM8995_ADC1L_TO_AIF1ADC1L_WIDTH 1 /* ADC1L_TO_AIF1ADC1L */ 3208*4882a593Smuzhiyun #define WM8995_AIF2DACL_TO_AIF1ADC1L 0x0001 /* AIF2DACL_TO_AIF1ADC1L */ 3209*4882a593Smuzhiyun #define WM8995_AIF2DACL_TO_AIF1ADC1L_MASK 0x0001 /* AIF2DACL_TO_AIF1ADC1L */ 3210*4882a593Smuzhiyun #define WM8995_AIF2DACL_TO_AIF1ADC1L_SHIFT 0 /* AIF2DACL_TO_AIF1ADC1L */ 3211*4882a593Smuzhiyun #define WM8995_AIF2DACL_TO_AIF1ADC1L_WIDTH 1 /* AIF2DACL_TO_AIF1ADC1L */ 3212*4882a593Smuzhiyun 3213*4882a593Smuzhiyun /* 3214*4882a593Smuzhiyun * R1543 (0x607) - AIF1 ADC1 Right Mixer Routing 3215*4882a593Smuzhiyun */ 3216*4882a593Smuzhiyun #define WM8995_ADC1R_TO_AIF1ADC1R 0x0002 /* ADC1R_TO_AIF1ADC1R */ 3217*4882a593Smuzhiyun #define WM8995_ADC1R_TO_AIF1ADC1R_MASK 0x0002 /* ADC1R_TO_AIF1ADC1R */ 3218*4882a593Smuzhiyun #define WM8995_ADC1R_TO_AIF1ADC1R_SHIFT 1 /* ADC1R_TO_AIF1ADC1R */ 3219*4882a593Smuzhiyun #define WM8995_ADC1R_TO_AIF1ADC1R_WIDTH 1 /* ADC1R_TO_AIF1ADC1R */ 3220*4882a593Smuzhiyun #define WM8995_AIF2DACR_TO_AIF1ADC1R 0x0001 /* AIF2DACR_TO_AIF1ADC1R */ 3221*4882a593Smuzhiyun #define WM8995_AIF2DACR_TO_AIF1ADC1R_MASK 0x0001 /* AIF2DACR_TO_AIF1ADC1R */ 3222*4882a593Smuzhiyun #define WM8995_AIF2DACR_TO_AIF1ADC1R_SHIFT 0 /* AIF2DACR_TO_AIF1ADC1R */ 3223*4882a593Smuzhiyun #define WM8995_AIF2DACR_TO_AIF1ADC1R_WIDTH 1 /* AIF2DACR_TO_AIF1ADC1R */ 3224*4882a593Smuzhiyun 3225*4882a593Smuzhiyun /* 3226*4882a593Smuzhiyun * R1544 (0x608) - AIF1 ADC2 Left Mixer Routing 3227*4882a593Smuzhiyun */ 3228*4882a593Smuzhiyun #define WM8995_ADC2L_TO_AIF1ADC2L 0x0002 /* ADC2L_TO_AIF1ADC2L */ 3229*4882a593Smuzhiyun #define WM8995_ADC2L_TO_AIF1ADC2L_MASK 0x0002 /* ADC2L_TO_AIF1ADC2L */ 3230*4882a593Smuzhiyun #define WM8995_ADC2L_TO_AIF1ADC2L_SHIFT 1 /* ADC2L_TO_AIF1ADC2L */ 3231*4882a593Smuzhiyun #define WM8995_ADC2L_TO_AIF1ADC2L_WIDTH 1 /* ADC2L_TO_AIF1ADC2L */ 3232*4882a593Smuzhiyun #define WM8995_AIF2DACL_TO_AIF1ADC2L 0x0001 /* AIF2DACL_TO_AIF1ADC2L */ 3233*4882a593Smuzhiyun #define WM8995_AIF2DACL_TO_AIF1ADC2L_MASK 0x0001 /* AIF2DACL_TO_AIF1ADC2L */ 3234*4882a593Smuzhiyun #define WM8995_AIF2DACL_TO_AIF1ADC2L_SHIFT 0 /* AIF2DACL_TO_AIF1ADC2L */ 3235*4882a593Smuzhiyun #define WM8995_AIF2DACL_TO_AIF1ADC2L_WIDTH 1 /* AIF2DACL_TO_AIF1ADC2L */ 3236*4882a593Smuzhiyun 3237*4882a593Smuzhiyun /* 3238*4882a593Smuzhiyun * R1545 (0x609) - AIF1 ADC2 Right mixer Routing 3239*4882a593Smuzhiyun */ 3240*4882a593Smuzhiyun #define WM8995_ADC2R_TO_AIF1ADC2R 0x0002 /* ADC2R_TO_AIF1ADC2R */ 3241*4882a593Smuzhiyun #define WM8995_ADC2R_TO_AIF1ADC2R_MASK 0x0002 /* ADC2R_TO_AIF1ADC2R */ 3242*4882a593Smuzhiyun #define WM8995_ADC2R_TO_AIF1ADC2R_SHIFT 1 /* ADC2R_TO_AIF1ADC2R */ 3243*4882a593Smuzhiyun #define WM8995_ADC2R_TO_AIF1ADC2R_WIDTH 1 /* ADC2R_TO_AIF1ADC2R */ 3244*4882a593Smuzhiyun #define WM8995_AIF2DACR_TO_AIF1ADC2R 0x0001 /* AIF2DACR_TO_AIF1ADC2R */ 3245*4882a593Smuzhiyun #define WM8995_AIF2DACR_TO_AIF1ADC2R_MASK 0x0001 /* AIF2DACR_TO_AIF1ADC2R */ 3246*4882a593Smuzhiyun #define WM8995_AIF2DACR_TO_AIF1ADC2R_SHIFT 0 /* AIF2DACR_TO_AIF1ADC2R */ 3247*4882a593Smuzhiyun #define WM8995_AIF2DACR_TO_AIF1ADC2R_WIDTH 1 /* AIF2DACR_TO_AIF1ADC2R */ 3248*4882a593Smuzhiyun 3249*4882a593Smuzhiyun /* 3250*4882a593Smuzhiyun * R1552 (0x610) - DAC Softmute 3251*4882a593Smuzhiyun */ 3252*4882a593Smuzhiyun #define WM8995_DAC_SOFTMUTEMODE 0x0002 /* DAC_SOFTMUTEMODE */ 3253*4882a593Smuzhiyun #define WM8995_DAC_SOFTMUTEMODE_MASK 0x0002 /* DAC_SOFTMUTEMODE */ 3254*4882a593Smuzhiyun #define WM8995_DAC_SOFTMUTEMODE_SHIFT 1 /* DAC_SOFTMUTEMODE */ 3255*4882a593Smuzhiyun #define WM8995_DAC_SOFTMUTEMODE_WIDTH 1 /* DAC_SOFTMUTEMODE */ 3256*4882a593Smuzhiyun #define WM8995_DAC_MUTERATE 0x0001 /* DAC_MUTERATE */ 3257*4882a593Smuzhiyun #define WM8995_DAC_MUTERATE_MASK 0x0001 /* DAC_MUTERATE */ 3258*4882a593Smuzhiyun #define WM8995_DAC_MUTERATE_SHIFT 0 /* DAC_MUTERATE */ 3259*4882a593Smuzhiyun #define WM8995_DAC_MUTERATE_WIDTH 1 /* DAC_MUTERATE */ 3260*4882a593Smuzhiyun 3261*4882a593Smuzhiyun /* 3262*4882a593Smuzhiyun * R1568 (0x620) - Oversampling 3263*4882a593Smuzhiyun */ 3264*4882a593Smuzhiyun #define WM8995_ADC_OSR128 0x0002 /* ADC_OSR128 */ 3265*4882a593Smuzhiyun #define WM8995_ADC_OSR128_MASK 0x0002 /* ADC_OSR128 */ 3266*4882a593Smuzhiyun #define WM8995_ADC_OSR128_SHIFT 1 /* ADC_OSR128 */ 3267*4882a593Smuzhiyun #define WM8995_ADC_OSR128_WIDTH 1 /* ADC_OSR128 */ 3268*4882a593Smuzhiyun #define WM8995_DAC_OSR128 0x0001 /* DAC_OSR128 */ 3269*4882a593Smuzhiyun #define WM8995_DAC_OSR128_MASK 0x0001 /* DAC_OSR128 */ 3270*4882a593Smuzhiyun #define WM8995_DAC_OSR128_SHIFT 0 /* DAC_OSR128 */ 3271*4882a593Smuzhiyun #define WM8995_DAC_OSR128_WIDTH 1 /* DAC_OSR128 */ 3272*4882a593Smuzhiyun 3273*4882a593Smuzhiyun /* 3274*4882a593Smuzhiyun * R1569 (0x621) - Sidetone 3275*4882a593Smuzhiyun */ 3276*4882a593Smuzhiyun #define WM8995_ST_LPF 0x1000 /* ST_LPF */ 3277*4882a593Smuzhiyun #define WM8995_ST_LPF_MASK 0x1000 /* ST_LPF */ 3278*4882a593Smuzhiyun #define WM8995_ST_LPF_SHIFT 12 /* ST_LPF */ 3279*4882a593Smuzhiyun #define WM8995_ST_LPF_WIDTH 1 /* ST_LPF */ 3280*4882a593Smuzhiyun #define WM8995_ST_HPF_CUT_MASK 0x0380 /* ST_HPF_CUT - [9:7] */ 3281*4882a593Smuzhiyun #define WM8995_ST_HPF_CUT_SHIFT 7 /* ST_HPF_CUT - [9:7] */ 3282*4882a593Smuzhiyun #define WM8995_ST_HPF_CUT_WIDTH 3 /* ST_HPF_CUT - [9:7] */ 3283*4882a593Smuzhiyun #define WM8995_ST_HPF 0x0040 /* ST_HPF */ 3284*4882a593Smuzhiyun #define WM8995_ST_HPF_MASK 0x0040 /* ST_HPF */ 3285*4882a593Smuzhiyun #define WM8995_ST_HPF_SHIFT 6 /* ST_HPF */ 3286*4882a593Smuzhiyun #define WM8995_ST_HPF_WIDTH 1 /* ST_HPF */ 3287*4882a593Smuzhiyun #define WM8995_STR_SEL 0x0002 /* STR_SEL */ 3288*4882a593Smuzhiyun #define WM8995_STR_SEL_MASK 0x0002 /* STR_SEL */ 3289*4882a593Smuzhiyun #define WM8995_STR_SEL_SHIFT 1 /* STR_SEL */ 3290*4882a593Smuzhiyun #define WM8995_STR_SEL_WIDTH 1 /* STR_SEL */ 3291*4882a593Smuzhiyun #define WM8995_STL_SEL 0x0001 /* STL_SEL */ 3292*4882a593Smuzhiyun #define WM8995_STL_SEL_MASK 0x0001 /* STL_SEL */ 3293*4882a593Smuzhiyun #define WM8995_STL_SEL_SHIFT 0 /* STL_SEL */ 3294*4882a593Smuzhiyun #define WM8995_STL_SEL_WIDTH 1 /* STL_SEL */ 3295*4882a593Smuzhiyun 3296*4882a593Smuzhiyun /* 3297*4882a593Smuzhiyun * R1792 (0x700) - GPIO 1 3298*4882a593Smuzhiyun */ 3299*4882a593Smuzhiyun #define WM8995_GP1_DIR 0x8000 /* GP1_DIR */ 3300*4882a593Smuzhiyun #define WM8995_GP1_DIR_MASK 0x8000 /* GP1_DIR */ 3301*4882a593Smuzhiyun #define WM8995_GP1_DIR_SHIFT 15 /* GP1_DIR */ 3302*4882a593Smuzhiyun #define WM8995_GP1_DIR_WIDTH 1 /* GP1_DIR */ 3303*4882a593Smuzhiyun #define WM8995_GP1_PU 0x4000 /* GP1_PU */ 3304*4882a593Smuzhiyun #define WM8995_GP1_PU_MASK 0x4000 /* GP1_PU */ 3305*4882a593Smuzhiyun #define WM8995_GP1_PU_SHIFT 14 /* GP1_PU */ 3306*4882a593Smuzhiyun #define WM8995_GP1_PU_WIDTH 1 /* GP1_PU */ 3307*4882a593Smuzhiyun #define WM8995_GP1_PD 0x2000 /* GP1_PD */ 3308*4882a593Smuzhiyun #define WM8995_GP1_PD_MASK 0x2000 /* GP1_PD */ 3309*4882a593Smuzhiyun #define WM8995_GP1_PD_SHIFT 13 /* GP1_PD */ 3310*4882a593Smuzhiyun #define WM8995_GP1_PD_WIDTH 1 /* GP1_PD */ 3311*4882a593Smuzhiyun #define WM8995_GP1_POL 0x0400 /* GP1_POL */ 3312*4882a593Smuzhiyun #define WM8995_GP1_POL_MASK 0x0400 /* GP1_POL */ 3313*4882a593Smuzhiyun #define WM8995_GP1_POL_SHIFT 10 /* GP1_POL */ 3314*4882a593Smuzhiyun #define WM8995_GP1_POL_WIDTH 1 /* GP1_POL */ 3315*4882a593Smuzhiyun #define WM8995_GP1_OP_CFG 0x0200 /* GP1_OP_CFG */ 3316*4882a593Smuzhiyun #define WM8995_GP1_OP_CFG_MASK 0x0200 /* GP1_OP_CFG */ 3317*4882a593Smuzhiyun #define WM8995_GP1_OP_CFG_SHIFT 9 /* GP1_OP_CFG */ 3318*4882a593Smuzhiyun #define WM8995_GP1_OP_CFG_WIDTH 1 /* GP1_OP_CFG */ 3319*4882a593Smuzhiyun #define WM8995_GP1_DB 0x0100 /* GP1_DB */ 3320*4882a593Smuzhiyun #define WM8995_GP1_DB_MASK 0x0100 /* GP1_DB */ 3321*4882a593Smuzhiyun #define WM8995_GP1_DB_SHIFT 8 /* GP1_DB */ 3322*4882a593Smuzhiyun #define WM8995_GP1_DB_WIDTH 1 /* GP1_DB */ 3323*4882a593Smuzhiyun #define WM8995_GP1_LVL 0x0040 /* GP1_LVL */ 3324*4882a593Smuzhiyun #define WM8995_GP1_LVL_MASK 0x0040 /* GP1_LVL */ 3325*4882a593Smuzhiyun #define WM8995_GP1_LVL_SHIFT 6 /* GP1_LVL */ 3326*4882a593Smuzhiyun #define WM8995_GP1_LVL_WIDTH 1 /* GP1_LVL */ 3327*4882a593Smuzhiyun #define WM8995_GP1_FN_MASK 0x001F /* GP1_FN - [4:0] */ 3328*4882a593Smuzhiyun #define WM8995_GP1_FN_SHIFT 0 /* GP1_FN - [4:0] */ 3329*4882a593Smuzhiyun #define WM8995_GP1_FN_WIDTH 5 /* GP1_FN - [4:0] */ 3330*4882a593Smuzhiyun 3331*4882a593Smuzhiyun /* 3332*4882a593Smuzhiyun * R1793 (0x701) - GPIO 2 3333*4882a593Smuzhiyun */ 3334*4882a593Smuzhiyun #define WM8995_GP2_DIR 0x8000 /* GP2_DIR */ 3335*4882a593Smuzhiyun #define WM8995_GP2_DIR_MASK 0x8000 /* GP2_DIR */ 3336*4882a593Smuzhiyun #define WM8995_GP2_DIR_SHIFT 15 /* GP2_DIR */ 3337*4882a593Smuzhiyun #define WM8995_GP2_DIR_WIDTH 1 /* GP2_DIR */ 3338*4882a593Smuzhiyun #define WM8995_GP2_PU 0x4000 /* GP2_PU */ 3339*4882a593Smuzhiyun #define WM8995_GP2_PU_MASK 0x4000 /* GP2_PU */ 3340*4882a593Smuzhiyun #define WM8995_GP2_PU_SHIFT 14 /* GP2_PU */ 3341*4882a593Smuzhiyun #define WM8995_GP2_PU_WIDTH 1 /* GP2_PU */ 3342*4882a593Smuzhiyun #define WM8995_GP2_PD 0x2000 /* GP2_PD */ 3343*4882a593Smuzhiyun #define WM8995_GP2_PD_MASK 0x2000 /* GP2_PD */ 3344*4882a593Smuzhiyun #define WM8995_GP2_PD_SHIFT 13 /* GP2_PD */ 3345*4882a593Smuzhiyun #define WM8995_GP2_PD_WIDTH 1 /* GP2_PD */ 3346*4882a593Smuzhiyun #define WM8995_GP2_POL 0x0400 /* GP2_POL */ 3347*4882a593Smuzhiyun #define WM8995_GP2_POL_MASK 0x0400 /* GP2_POL */ 3348*4882a593Smuzhiyun #define WM8995_GP2_POL_SHIFT 10 /* GP2_POL */ 3349*4882a593Smuzhiyun #define WM8995_GP2_POL_WIDTH 1 /* GP2_POL */ 3350*4882a593Smuzhiyun #define WM8995_GP2_OP_CFG 0x0200 /* GP2_OP_CFG */ 3351*4882a593Smuzhiyun #define WM8995_GP2_OP_CFG_MASK 0x0200 /* GP2_OP_CFG */ 3352*4882a593Smuzhiyun #define WM8995_GP2_OP_CFG_SHIFT 9 /* GP2_OP_CFG */ 3353*4882a593Smuzhiyun #define WM8995_GP2_OP_CFG_WIDTH 1 /* GP2_OP_CFG */ 3354*4882a593Smuzhiyun #define WM8995_GP2_DB 0x0100 /* GP2_DB */ 3355*4882a593Smuzhiyun #define WM8995_GP2_DB_MASK 0x0100 /* GP2_DB */ 3356*4882a593Smuzhiyun #define WM8995_GP2_DB_SHIFT 8 /* GP2_DB */ 3357*4882a593Smuzhiyun #define WM8995_GP2_DB_WIDTH 1 /* GP2_DB */ 3358*4882a593Smuzhiyun #define WM8995_GP2_LVL 0x0040 /* GP2_LVL */ 3359*4882a593Smuzhiyun #define WM8995_GP2_LVL_MASK 0x0040 /* GP2_LVL */ 3360*4882a593Smuzhiyun #define WM8995_GP2_LVL_SHIFT 6 /* GP2_LVL */ 3361*4882a593Smuzhiyun #define WM8995_GP2_LVL_WIDTH 1 /* GP2_LVL */ 3362*4882a593Smuzhiyun #define WM8995_GP2_FN_MASK 0x001F /* GP2_FN - [4:0] */ 3363*4882a593Smuzhiyun #define WM8995_GP2_FN_SHIFT 0 /* GP2_FN - [4:0] */ 3364*4882a593Smuzhiyun #define WM8995_GP2_FN_WIDTH 5 /* GP2_FN - [4:0] */ 3365*4882a593Smuzhiyun 3366*4882a593Smuzhiyun /* 3367*4882a593Smuzhiyun * R1794 (0x702) - GPIO 3 3368*4882a593Smuzhiyun */ 3369*4882a593Smuzhiyun #define WM8995_GP3_DIR 0x8000 /* GP3_DIR */ 3370*4882a593Smuzhiyun #define WM8995_GP3_DIR_MASK 0x8000 /* GP3_DIR */ 3371*4882a593Smuzhiyun #define WM8995_GP3_DIR_SHIFT 15 /* GP3_DIR */ 3372*4882a593Smuzhiyun #define WM8995_GP3_DIR_WIDTH 1 /* GP3_DIR */ 3373*4882a593Smuzhiyun #define WM8995_GP3_PU 0x4000 /* GP3_PU */ 3374*4882a593Smuzhiyun #define WM8995_GP3_PU_MASK 0x4000 /* GP3_PU */ 3375*4882a593Smuzhiyun #define WM8995_GP3_PU_SHIFT 14 /* GP3_PU */ 3376*4882a593Smuzhiyun #define WM8995_GP3_PU_WIDTH 1 /* GP3_PU */ 3377*4882a593Smuzhiyun #define WM8995_GP3_PD 0x2000 /* GP3_PD */ 3378*4882a593Smuzhiyun #define WM8995_GP3_PD_MASK 0x2000 /* GP3_PD */ 3379*4882a593Smuzhiyun #define WM8995_GP3_PD_SHIFT 13 /* GP3_PD */ 3380*4882a593Smuzhiyun #define WM8995_GP3_PD_WIDTH 1 /* GP3_PD */ 3381*4882a593Smuzhiyun #define WM8995_GP3_POL 0x0400 /* GP3_POL */ 3382*4882a593Smuzhiyun #define WM8995_GP3_POL_MASK 0x0400 /* GP3_POL */ 3383*4882a593Smuzhiyun #define WM8995_GP3_POL_SHIFT 10 /* GP3_POL */ 3384*4882a593Smuzhiyun #define WM8995_GP3_POL_WIDTH 1 /* GP3_POL */ 3385*4882a593Smuzhiyun #define WM8995_GP3_OP_CFG 0x0200 /* GP3_OP_CFG */ 3386*4882a593Smuzhiyun #define WM8995_GP3_OP_CFG_MASK 0x0200 /* GP3_OP_CFG */ 3387*4882a593Smuzhiyun #define WM8995_GP3_OP_CFG_SHIFT 9 /* GP3_OP_CFG */ 3388*4882a593Smuzhiyun #define WM8995_GP3_OP_CFG_WIDTH 1 /* GP3_OP_CFG */ 3389*4882a593Smuzhiyun #define WM8995_GP3_DB 0x0100 /* GP3_DB */ 3390*4882a593Smuzhiyun #define WM8995_GP3_DB_MASK 0x0100 /* GP3_DB */ 3391*4882a593Smuzhiyun #define WM8995_GP3_DB_SHIFT 8 /* GP3_DB */ 3392*4882a593Smuzhiyun #define WM8995_GP3_DB_WIDTH 1 /* GP3_DB */ 3393*4882a593Smuzhiyun #define WM8995_GP3_LVL 0x0040 /* GP3_LVL */ 3394*4882a593Smuzhiyun #define WM8995_GP3_LVL_MASK 0x0040 /* GP3_LVL */ 3395*4882a593Smuzhiyun #define WM8995_GP3_LVL_SHIFT 6 /* GP3_LVL */ 3396*4882a593Smuzhiyun #define WM8995_GP3_LVL_WIDTH 1 /* GP3_LVL */ 3397*4882a593Smuzhiyun #define WM8995_GP3_FN_MASK 0x001F /* GP3_FN - [4:0] */ 3398*4882a593Smuzhiyun #define WM8995_GP3_FN_SHIFT 0 /* GP3_FN - [4:0] */ 3399*4882a593Smuzhiyun #define WM8995_GP3_FN_WIDTH 5 /* GP3_FN - [4:0] */ 3400*4882a593Smuzhiyun 3401*4882a593Smuzhiyun /* 3402*4882a593Smuzhiyun * R1795 (0x703) - GPIO 4 3403*4882a593Smuzhiyun */ 3404*4882a593Smuzhiyun #define WM8995_GP4_DIR 0x8000 /* GP4_DIR */ 3405*4882a593Smuzhiyun #define WM8995_GP4_DIR_MASK 0x8000 /* GP4_DIR */ 3406*4882a593Smuzhiyun #define WM8995_GP4_DIR_SHIFT 15 /* GP4_DIR */ 3407*4882a593Smuzhiyun #define WM8995_GP4_DIR_WIDTH 1 /* GP4_DIR */ 3408*4882a593Smuzhiyun #define WM8995_GP4_PU 0x4000 /* GP4_PU */ 3409*4882a593Smuzhiyun #define WM8995_GP4_PU_MASK 0x4000 /* GP4_PU */ 3410*4882a593Smuzhiyun #define WM8995_GP4_PU_SHIFT 14 /* GP4_PU */ 3411*4882a593Smuzhiyun #define WM8995_GP4_PU_WIDTH 1 /* GP4_PU */ 3412*4882a593Smuzhiyun #define WM8995_GP4_PD 0x2000 /* GP4_PD */ 3413*4882a593Smuzhiyun #define WM8995_GP4_PD_MASK 0x2000 /* GP4_PD */ 3414*4882a593Smuzhiyun #define WM8995_GP4_PD_SHIFT 13 /* GP4_PD */ 3415*4882a593Smuzhiyun #define WM8995_GP4_PD_WIDTH 1 /* GP4_PD */ 3416*4882a593Smuzhiyun #define WM8995_GP4_POL 0x0400 /* GP4_POL */ 3417*4882a593Smuzhiyun #define WM8995_GP4_POL_MASK 0x0400 /* GP4_POL */ 3418*4882a593Smuzhiyun #define WM8995_GP4_POL_SHIFT 10 /* GP4_POL */ 3419*4882a593Smuzhiyun #define WM8995_GP4_POL_WIDTH 1 /* GP4_POL */ 3420*4882a593Smuzhiyun #define WM8995_GP4_OP_CFG 0x0200 /* GP4_OP_CFG */ 3421*4882a593Smuzhiyun #define WM8995_GP4_OP_CFG_MASK 0x0200 /* GP4_OP_CFG */ 3422*4882a593Smuzhiyun #define WM8995_GP4_OP_CFG_SHIFT 9 /* GP4_OP_CFG */ 3423*4882a593Smuzhiyun #define WM8995_GP4_OP_CFG_WIDTH 1 /* GP4_OP_CFG */ 3424*4882a593Smuzhiyun #define WM8995_GP4_DB 0x0100 /* GP4_DB */ 3425*4882a593Smuzhiyun #define WM8995_GP4_DB_MASK 0x0100 /* GP4_DB */ 3426*4882a593Smuzhiyun #define WM8995_GP4_DB_SHIFT 8 /* GP4_DB */ 3427*4882a593Smuzhiyun #define WM8995_GP4_DB_WIDTH 1 /* GP4_DB */ 3428*4882a593Smuzhiyun #define WM8995_GP4_LVL 0x0040 /* GP4_LVL */ 3429*4882a593Smuzhiyun #define WM8995_GP4_LVL_MASK 0x0040 /* GP4_LVL */ 3430*4882a593Smuzhiyun #define WM8995_GP4_LVL_SHIFT 6 /* GP4_LVL */ 3431*4882a593Smuzhiyun #define WM8995_GP4_LVL_WIDTH 1 /* GP4_LVL */ 3432*4882a593Smuzhiyun #define WM8995_GP4_FN_MASK 0x001F /* GP4_FN - [4:0] */ 3433*4882a593Smuzhiyun #define WM8995_GP4_FN_SHIFT 0 /* GP4_FN - [4:0] */ 3434*4882a593Smuzhiyun #define WM8995_GP4_FN_WIDTH 5 /* GP4_FN - [4:0] */ 3435*4882a593Smuzhiyun 3436*4882a593Smuzhiyun /* 3437*4882a593Smuzhiyun * R1796 (0x704) - GPIO 5 3438*4882a593Smuzhiyun */ 3439*4882a593Smuzhiyun #define WM8995_GP5_DIR 0x8000 /* GP5_DIR */ 3440*4882a593Smuzhiyun #define WM8995_GP5_DIR_MASK 0x8000 /* GP5_DIR */ 3441*4882a593Smuzhiyun #define WM8995_GP5_DIR_SHIFT 15 /* GP5_DIR */ 3442*4882a593Smuzhiyun #define WM8995_GP5_DIR_WIDTH 1 /* GP5_DIR */ 3443*4882a593Smuzhiyun #define WM8995_GP5_PU 0x4000 /* GP5_PU */ 3444*4882a593Smuzhiyun #define WM8995_GP5_PU_MASK 0x4000 /* GP5_PU */ 3445*4882a593Smuzhiyun #define WM8995_GP5_PU_SHIFT 14 /* GP5_PU */ 3446*4882a593Smuzhiyun #define WM8995_GP5_PU_WIDTH 1 /* GP5_PU */ 3447*4882a593Smuzhiyun #define WM8995_GP5_PD 0x2000 /* GP5_PD */ 3448*4882a593Smuzhiyun #define WM8995_GP5_PD_MASK 0x2000 /* GP5_PD */ 3449*4882a593Smuzhiyun #define WM8995_GP5_PD_SHIFT 13 /* GP5_PD */ 3450*4882a593Smuzhiyun #define WM8995_GP5_PD_WIDTH 1 /* GP5_PD */ 3451*4882a593Smuzhiyun #define WM8995_GP5_POL 0x0400 /* GP5_POL */ 3452*4882a593Smuzhiyun #define WM8995_GP5_POL_MASK 0x0400 /* GP5_POL */ 3453*4882a593Smuzhiyun #define WM8995_GP5_POL_SHIFT 10 /* GP5_POL */ 3454*4882a593Smuzhiyun #define WM8995_GP5_POL_WIDTH 1 /* GP5_POL */ 3455*4882a593Smuzhiyun #define WM8995_GP5_OP_CFG 0x0200 /* GP5_OP_CFG */ 3456*4882a593Smuzhiyun #define WM8995_GP5_OP_CFG_MASK 0x0200 /* GP5_OP_CFG */ 3457*4882a593Smuzhiyun #define WM8995_GP5_OP_CFG_SHIFT 9 /* GP5_OP_CFG */ 3458*4882a593Smuzhiyun #define WM8995_GP5_OP_CFG_WIDTH 1 /* GP5_OP_CFG */ 3459*4882a593Smuzhiyun #define WM8995_GP5_DB 0x0100 /* GP5_DB */ 3460*4882a593Smuzhiyun #define WM8995_GP5_DB_MASK 0x0100 /* GP5_DB */ 3461*4882a593Smuzhiyun #define WM8995_GP5_DB_SHIFT 8 /* GP5_DB */ 3462*4882a593Smuzhiyun #define WM8995_GP5_DB_WIDTH 1 /* GP5_DB */ 3463*4882a593Smuzhiyun #define WM8995_GP5_LVL 0x0040 /* GP5_LVL */ 3464*4882a593Smuzhiyun #define WM8995_GP5_LVL_MASK 0x0040 /* GP5_LVL */ 3465*4882a593Smuzhiyun #define WM8995_GP5_LVL_SHIFT 6 /* GP5_LVL */ 3466*4882a593Smuzhiyun #define WM8995_GP5_LVL_WIDTH 1 /* GP5_LVL */ 3467*4882a593Smuzhiyun #define WM8995_GP5_FN_MASK 0x001F /* GP5_FN - [4:0] */ 3468*4882a593Smuzhiyun #define WM8995_GP5_FN_SHIFT 0 /* GP5_FN - [4:0] */ 3469*4882a593Smuzhiyun #define WM8995_GP5_FN_WIDTH 5 /* GP5_FN - [4:0] */ 3470*4882a593Smuzhiyun 3471*4882a593Smuzhiyun /* 3472*4882a593Smuzhiyun * R1797 (0x705) - GPIO 6 3473*4882a593Smuzhiyun */ 3474*4882a593Smuzhiyun #define WM8995_GP6_DIR 0x8000 /* GP6_DIR */ 3475*4882a593Smuzhiyun #define WM8995_GP6_DIR_MASK 0x8000 /* GP6_DIR */ 3476*4882a593Smuzhiyun #define WM8995_GP6_DIR_SHIFT 15 /* GP6_DIR */ 3477*4882a593Smuzhiyun #define WM8995_GP6_DIR_WIDTH 1 /* GP6_DIR */ 3478*4882a593Smuzhiyun #define WM8995_GP6_PU 0x4000 /* GP6_PU */ 3479*4882a593Smuzhiyun #define WM8995_GP6_PU_MASK 0x4000 /* GP6_PU */ 3480*4882a593Smuzhiyun #define WM8995_GP6_PU_SHIFT 14 /* GP6_PU */ 3481*4882a593Smuzhiyun #define WM8995_GP6_PU_WIDTH 1 /* GP6_PU */ 3482*4882a593Smuzhiyun #define WM8995_GP6_PD 0x2000 /* GP6_PD */ 3483*4882a593Smuzhiyun #define WM8995_GP6_PD_MASK 0x2000 /* GP6_PD */ 3484*4882a593Smuzhiyun #define WM8995_GP6_PD_SHIFT 13 /* GP6_PD */ 3485*4882a593Smuzhiyun #define WM8995_GP6_PD_WIDTH 1 /* GP6_PD */ 3486*4882a593Smuzhiyun #define WM8995_GP6_POL 0x0400 /* GP6_POL */ 3487*4882a593Smuzhiyun #define WM8995_GP6_POL_MASK 0x0400 /* GP6_POL */ 3488*4882a593Smuzhiyun #define WM8995_GP6_POL_SHIFT 10 /* GP6_POL */ 3489*4882a593Smuzhiyun #define WM8995_GP6_POL_WIDTH 1 /* GP6_POL */ 3490*4882a593Smuzhiyun #define WM8995_GP6_OP_CFG 0x0200 /* GP6_OP_CFG */ 3491*4882a593Smuzhiyun #define WM8995_GP6_OP_CFG_MASK 0x0200 /* GP6_OP_CFG */ 3492*4882a593Smuzhiyun #define WM8995_GP6_OP_CFG_SHIFT 9 /* GP6_OP_CFG */ 3493*4882a593Smuzhiyun #define WM8995_GP6_OP_CFG_WIDTH 1 /* GP6_OP_CFG */ 3494*4882a593Smuzhiyun #define WM8995_GP6_DB 0x0100 /* GP6_DB */ 3495*4882a593Smuzhiyun #define WM8995_GP6_DB_MASK 0x0100 /* GP6_DB */ 3496*4882a593Smuzhiyun #define WM8995_GP6_DB_SHIFT 8 /* GP6_DB */ 3497*4882a593Smuzhiyun #define WM8995_GP6_DB_WIDTH 1 /* GP6_DB */ 3498*4882a593Smuzhiyun #define WM8995_GP6_LVL 0x0040 /* GP6_LVL */ 3499*4882a593Smuzhiyun #define WM8995_GP6_LVL_MASK 0x0040 /* GP6_LVL */ 3500*4882a593Smuzhiyun #define WM8995_GP6_LVL_SHIFT 6 /* GP6_LVL */ 3501*4882a593Smuzhiyun #define WM8995_GP6_LVL_WIDTH 1 /* GP6_LVL */ 3502*4882a593Smuzhiyun #define WM8995_GP6_FN_MASK 0x001F /* GP6_FN - [4:0] */ 3503*4882a593Smuzhiyun #define WM8995_GP6_FN_SHIFT 0 /* GP6_FN - [4:0] */ 3504*4882a593Smuzhiyun #define WM8995_GP6_FN_WIDTH 5 /* GP6_FN - [4:0] */ 3505*4882a593Smuzhiyun 3506*4882a593Smuzhiyun /* 3507*4882a593Smuzhiyun * R1798 (0x706) - GPIO 7 3508*4882a593Smuzhiyun */ 3509*4882a593Smuzhiyun #define WM8995_GP7_DIR 0x8000 /* GP7_DIR */ 3510*4882a593Smuzhiyun #define WM8995_GP7_DIR_MASK 0x8000 /* GP7_DIR */ 3511*4882a593Smuzhiyun #define WM8995_GP7_DIR_SHIFT 15 /* GP7_DIR */ 3512*4882a593Smuzhiyun #define WM8995_GP7_DIR_WIDTH 1 /* GP7_DIR */ 3513*4882a593Smuzhiyun #define WM8995_GP7_PU 0x4000 /* GP7_PU */ 3514*4882a593Smuzhiyun #define WM8995_GP7_PU_MASK 0x4000 /* GP7_PU */ 3515*4882a593Smuzhiyun #define WM8995_GP7_PU_SHIFT 14 /* GP7_PU */ 3516*4882a593Smuzhiyun #define WM8995_GP7_PU_WIDTH 1 /* GP7_PU */ 3517*4882a593Smuzhiyun #define WM8995_GP7_PD 0x2000 /* GP7_PD */ 3518*4882a593Smuzhiyun #define WM8995_GP7_PD_MASK 0x2000 /* GP7_PD */ 3519*4882a593Smuzhiyun #define WM8995_GP7_PD_SHIFT 13 /* GP7_PD */ 3520*4882a593Smuzhiyun #define WM8995_GP7_PD_WIDTH 1 /* GP7_PD */ 3521*4882a593Smuzhiyun #define WM8995_GP7_POL 0x0400 /* GP7_POL */ 3522*4882a593Smuzhiyun #define WM8995_GP7_POL_MASK 0x0400 /* GP7_POL */ 3523*4882a593Smuzhiyun #define WM8995_GP7_POL_SHIFT 10 /* GP7_POL */ 3524*4882a593Smuzhiyun #define WM8995_GP7_POL_WIDTH 1 /* GP7_POL */ 3525*4882a593Smuzhiyun #define WM8995_GP7_OP_CFG 0x0200 /* GP7_OP_CFG */ 3526*4882a593Smuzhiyun #define WM8995_GP7_OP_CFG_MASK 0x0200 /* GP7_OP_CFG */ 3527*4882a593Smuzhiyun #define WM8995_GP7_OP_CFG_SHIFT 9 /* GP7_OP_CFG */ 3528*4882a593Smuzhiyun #define WM8995_GP7_OP_CFG_WIDTH 1 /* GP7_OP_CFG */ 3529*4882a593Smuzhiyun #define WM8995_GP7_DB 0x0100 /* GP7_DB */ 3530*4882a593Smuzhiyun #define WM8995_GP7_DB_MASK 0x0100 /* GP7_DB */ 3531*4882a593Smuzhiyun #define WM8995_GP7_DB_SHIFT 8 /* GP7_DB */ 3532*4882a593Smuzhiyun #define WM8995_GP7_DB_WIDTH 1 /* GP7_DB */ 3533*4882a593Smuzhiyun #define WM8995_GP7_LVL 0x0040 /* GP7_LVL */ 3534*4882a593Smuzhiyun #define WM8995_GP7_LVL_MASK 0x0040 /* GP7_LVL */ 3535*4882a593Smuzhiyun #define WM8995_GP7_LVL_SHIFT 6 /* GP7_LVL */ 3536*4882a593Smuzhiyun #define WM8995_GP7_LVL_WIDTH 1 /* GP7_LVL */ 3537*4882a593Smuzhiyun #define WM8995_GP7_FN_MASK 0x001F /* GP7_FN - [4:0] */ 3538*4882a593Smuzhiyun #define WM8995_GP7_FN_SHIFT 0 /* GP7_FN - [4:0] */ 3539*4882a593Smuzhiyun #define WM8995_GP7_FN_WIDTH 5 /* GP7_FN - [4:0] */ 3540*4882a593Smuzhiyun 3541*4882a593Smuzhiyun /* 3542*4882a593Smuzhiyun * R1799 (0x707) - GPIO 8 3543*4882a593Smuzhiyun */ 3544*4882a593Smuzhiyun #define WM8995_GP8_DIR 0x8000 /* GP8_DIR */ 3545*4882a593Smuzhiyun #define WM8995_GP8_DIR_MASK 0x8000 /* GP8_DIR */ 3546*4882a593Smuzhiyun #define WM8995_GP8_DIR_SHIFT 15 /* GP8_DIR */ 3547*4882a593Smuzhiyun #define WM8995_GP8_DIR_WIDTH 1 /* GP8_DIR */ 3548*4882a593Smuzhiyun #define WM8995_GP8_PU 0x4000 /* GP8_PU */ 3549*4882a593Smuzhiyun #define WM8995_GP8_PU_MASK 0x4000 /* GP8_PU */ 3550*4882a593Smuzhiyun #define WM8995_GP8_PU_SHIFT 14 /* GP8_PU */ 3551*4882a593Smuzhiyun #define WM8995_GP8_PU_WIDTH 1 /* GP8_PU */ 3552*4882a593Smuzhiyun #define WM8995_GP8_PD 0x2000 /* GP8_PD */ 3553*4882a593Smuzhiyun #define WM8995_GP8_PD_MASK 0x2000 /* GP8_PD */ 3554*4882a593Smuzhiyun #define WM8995_GP8_PD_SHIFT 13 /* GP8_PD */ 3555*4882a593Smuzhiyun #define WM8995_GP8_PD_WIDTH 1 /* GP8_PD */ 3556*4882a593Smuzhiyun #define WM8995_GP8_POL 0x0400 /* GP8_POL */ 3557*4882a593Smuzhiyun #define WM8995_GP8_POL_MASK 0x0400 /* GP8_POL */ 3558*4882a593Smuzhiyun #define WM8995_GP8_POL_SHIFT 10 /* GP8_POL */ 3559*4882a593Smuzhiyun #define WM8995_GP8_POL_WIDTH 1 /* GP8_POL */ 3560*4882a593Smuzhiyun #define WM8995_GP8_OP_CFG 0x0200 /* GP8_OP_CFG */ 3561*4882a593Smuzhiyun #define WM8995_GP8_OP_CFG_MASK 0x0200 /* GP8_OP_CFG */ 3562*4882a593Smuzhiyun #define WM8995_GP8_OP_CFG_SHIFT 9 /* GP8_OP_CFG */ 3563*4882a593Smuzhiyun #define WM8995_GP8_OP_CFG_WIDTH 1 /* GP8_OP_CFG */ 3564*4882a593Smuzhiyun #define WM8995_GP8_DB 0x0100 /* GP8_DB */ 3565*4882a593Smuzhiyun #define WM8995_GP8_DB_MASK 0x0100 /* GP8_DB */ 3566*4882a593Smuzhiyun #define WM8995_GP8_DB_SHIFT 8 /* GP8_DB */ 3567*4882a593Smuzhiyun #define WM8995_GP8_DB_WIDTH 1 /* GP8_DB */ 3568*4882a593Smuzhiyun #define WM8995_GP8_LVL 0x0040 /* GP8_LVL */ 3569*4882a593Smuzhiyun #define WM8995_GP8_LVL_MASK 0x0040 /* GP8_LVL */ 3570*4882a593Smuzhiyun #define WM8995_GP8_LVL_SHIFT 6 /* GP8_LVL */ 3571*4882a593Smuzhiyun #define WM8995_GP8_LVL_WIDTH 1 /* GP8_LVL */ 3572*4882a593Smuzhiyun #define WM8995_GP8_FN_MASK 0x001F /* GP8_FN - [4:0] */ 3573*4882a593Smuzhiyun #define WM8995_GP8_FN_SHIFT 0 /* GP8_FN - [4:0] */ 3574*4882a593Smuzhiyun #define WM8995_GP8_FN_WIDTH 5 /* GP8_FN - [4:0] */ 3575*4882a593Smuzhiyun 3576*4882a593Smuzhiyun /* 3577*4882a593Smuzhiyun * R1800 (0x708) - GPIO 9 3578*4882a593Smuzhiyun */ 3579*4882a593Smuzhiyun #define WM8995_GP9_DIR 0x8000 /* GP9_DIR */ 3580*4882a593Smuzhiyun #define WM8995_GP9_DIR_MASK 0x8000 /* GP9_DIR */ 3581*4882a593Smuzhiyun #define WM8995_GP9_DIR_SHIFT 15 /* GP9_DIR */ 3582*4882a593Smuzhiyun #define WM8995_GP9_DIR_WIDTH 1 /* GP9_DIR */ 3583*4882a593Smuzhiyun #define WM8995_GP9_PU 0x4000 /* GP9_PU */ 3584*4882a593Smuzhiyun #define WM8995_GP9_PU_MASK 0x4000 /* GP9_PU */ 3585*4882a593Smuzhiyun #define WM8995_GP9_PU_SHIFT 14 /* GP9_PU */ 3586*4882a593Smuzhiyun #define WM8995_GP9_PU_WIDTH 1 /* GP9_PU */ 3587*4882a593Smuzhiyun #define WM8995_GP9_PD 0x2000 /* GP9_PD */ 3588*4882a593Smuzhiyun #define WM8995_GP9_PD_MASK 0x2000 /* GP9_PD */ 3589*4882a593Smuzhiyun #define WM8995_GP9_PD_SHIFT 13 /* GP9_PD */ 3590*4882a593Smuzhiyun #define WM8995_GP9_PD_WIDTH 1 /* GP9_PD */ 3591*4882a593Smuzhiyun #define WM8995_GP9_POL 0x0400 /* GP9_POL */ 3592*4882a593Smuzhiyun #define WM8995_GP9_POL_MASK 0x0400 /* GP9_POL */ 3593*4882a593Smuzhiyun #define WM8995_GP9_POL_SHIFT 10 /* GP9_POL */ 3594*4882a593Smuzhiyun #define WM8995_GP9_POL_WIDTH 1 /* GP9_POL */ 3595*4882a593Smuzhiyun #define WM8995_GP9_OP_CFG 0x0200 /* GP9_OP_CFG */ 3596*4882a593Smuzhiyun #define WM8995_GP9_OP_CFG_MASK 0x0200 /* GP9_OP_CFG */ 3597*4882a593Smuzhiyun #define WM8995_GP9_OP_CFG_SHIFT 9 /* GP9_OP_CFG */ 3598*4882a593Smuzhiyun #define WM8995_GP9_OP_CFG_WIDTH 1 /* GP9_OP_CFG */ 3599*4882a593Smuzhiyun #define WM8995_GP9_DB 0x0100 /* GP9_DB */ 3600*4882a593Smuzhiyun #define WM8995_GP9_DB_MASK 0x0100 /* GP9_DB */ 3601*4882a593Smuzhiyun #define WM8995_GP9_DB_SHIFT 8 /* GP9_DB */ 3602*4882a593Smuzhiyun #define WM8995_GP9_DB_WIDTH 1 /* GP9_DB */ 3603*4882a593Smuzhiyun #define WM8995_GP9_LVL 0x0040 /* GP9_LVL */ 3604*4882a593Smuzhiyun #define WM8995_GP9_LVL_MASK 0x0040 /* GP9_LVL */ 3605*4882a593Smuzhiyun #define WM8995_GP9_LVL_SHIFT 6 /* GP9_LVL */ 3606*4882a593Smuzhiyun #define WM8995_GP9_LVL_WIDTH 1 /* GP9_LVL */ 3607*4882a593Smuzhiyun #define WM8995_GP9_FN_MASK 0x001F /* GP9_FN - [4:0] */ 3608*4882a593Smuzhiyun #define WM8995_GP9_FN_SHIFT 0 /* GP9_FN - [4:0] */ 3609*4882a593Smuzhiyun #define WM8995_GP9_FN_WIDTH 5 /* GP9_FN - [4:0] */ 3610*4882a593Smuzhiyun 3611*4882a593Smuzhiyun /* 3612*4882a593Smuzhiyun * R1801 (0x709) - GPIO 10 3613*4882a593Smuzhiyun */ 3614*4882a593Smuzhiyun #define WM8995_GP10_DIR 0x8000 /* GP10_DIR */ 3615*4882a593Smuzhiyun #define WM8995_GP10_DIR_MASK 0x8000 /* GP10_DIR */ 3616*4882a593Smuzhiyun #define WM8995_GP10_DIR_SHIFT 15 /* GP10_DIR */ 3617*4882a593Smuzhiyun #define WM8995_GP10_DIR_WIDTH 1 /* GP10_DIR */ 3618*4882a593Smuzhiyun #define WM8995_GP10_PU 0x4000 /* GP10_PU */ 3619*4882a593Smuzhiyun #define WM8995_GP10_PU_MASK 0x4000 /* GP10_PU */ 3620*4882a593Smuzhiyun #define WM8995_GP10_PU_SHIFT 14 /* GP10_PU */ 3621*4882a593Smuzhiyun #define WM8995_GP10_PU_WIDTH 1 /* GP10_PU */ 3622*4882a593Smuzhiyun #define WM8995_GP10_PD 0x2000 /* GP10_PD */ 3623*4882a593Smuzhiyun #define WM8995_GP10_PD_MASK 0x2000 /* GP10_PD */ 3624*4882a593Smuzhiyun #define WM8995_GP10_PD_SHIFT 13 /* GP10_PD */ 3625*4882a593Smuzhiyun #define WM8995_GP10_PD_WIDTH 1 /* GP10_PD */ 3626*4882a593Smuzhiyun #define WM8995_GP10_POL 0x0400 /* GP10_POL */ 3627*4882a593Smuzhiyun #define WM8995_GP10_POL_MASK 0x0400 /* GP10_POL */ 3628*4882a593Smuzhiyun #define WM8995_GP10_POL_SHIFT 10 /* GP10_POL */ 3629*4882a593Smuzhiyun #define WM8995_GP10_POL_WIDTH 1 /* GP10_POL */ 3630*4882a593Smuzhiyun #define WM8995_GP10_OP_CFG 0x0200 /* GP10_OP_CFG */ 3631*4882a593Smuzhiyun #define WM8995_GP10_OP_CFG_MASK 0x0200 /* GP10_OP_CFG */ 3632*4882a593Smuzhiyun #define WM8995_GP10_OP_CFG_SHIFT 9 /* GP10_OP_CFG */ 3633*4882a593Smuzhiyun #define WM8995_GP10_OP_CFG_WIDTH 1 /* GP10_OP_CFG */ 3634*4882a593Smuzhiyun #define WM8995_GP10_DB 0x0100 /* GP10_DB */ 3635*4882a593Smuzhiyun #define WM8995_GP10_DB_MASK 0x0100 /* GP10_DB */ 3636*4882a593Smuzhiyun #define WM8995_GP10_DB_SHIFT 8 /* GP10_DB */ 3637*4882a593Smuzhiyun #define WM8995_GP10_DB_WIDTH 1 /* GP10_DB */ 3638*4882a593Smuzhiyun #define WM8995_GP10_LVL 0x0040 /* GP10_LVL */ 3639*4882a593Smuzhiyun #define WM8995_GP10_LVL_MASK 0x0040 /* GP10_LVL */ 3640*4882a593Smuzhiyun #define WM8995_GP10_LVL_SHIFT 6 /* GP10_LVL */ 3641*4882a593Smuzhiyun #define WM8995_GP10_LVL_WIDTH 1 /* GP10_LVL */ 3642*4882a593Smuzhiyun #define WM8995_GP10_FN_MASK 0x001F /* GP10_FN - [4:0] */ 3643*4882a593Smuzhiyun #define WM8995_GP10_FN_SHIFT 0 /* GP10_FN - [4:0] */ 3644*4882a593Smuzhiyun #define WM8995_GP10_FN_WIDTH 5 /* GP10_FN - [4:0] */ 3645*4882a593Smuzhiyun 3646*4882a593Smuzhiyun /* 3647*4882a593Smuzhiyun * R1802 (0x70A) - GPIO 11 3648*4882a593Smuzhiyun */ 3649*4882a593Smuzhiyun #define WM8995_GP11_DIR 0x8000 /* GP11_DIR */ 3650*4882a593Smuzhiyun #define WM8995_GP11_DIR_MASK 0x8000 /* GP11_DIR */ 3651*4882a593Smuzhiyun #define WM8995_GP11_DIR_SHIFT 15 /* GP11_DIR */ 3652*4882a593Smuzhiyun #define WM8995_GP11_DIR_WIDTH 1 /* GP11_DIR */ 3653*4882a593Smuzhiyun #define WM8995_GP11_PU 0x4000 /* GP11_PU */ 3654*4882a593Smuzhiyun #define WM8995_GP11_PU_MASK 0x4000 /* GP11_PU */ 3655*4882a593Smuzhiyun #define WM8995_GP11_PU_SHIFT 14 /* GP11_PU */ 3656*4882a593Smuzhiyun #define WM8995_GP11_PU_WIDTH 1 /* GP11_PU */ 3657*4882a593Smuzhiyun #define WM8995_GP11_PD 0x2000 /* GP11_PD */ 3658*4882a593Smuzhiyun #define WM8995_GP11_PD_MASK 0x2000 /* GP11_PD */ 3659*4882a593Smuzhiyun #define WM8995_GP11_PD_SHIFT 13 /* GP11_PD */ 3660*4882a593Smuzhiyun #define WM8995_GP11_PD_WIDTH 1 /* GP11_PD */ 3661*4882a593Smuzhiyun #define WM8995_GP11_POL 0x0400 /* GP11_POL */ 3662*4882a593Smuzhiyun #define WM8995_GP11_POL_MASK 0x0400 /* GP11_POL */ 3663*4882a593Smuzhiyun #define WM8995_GP11_POL_SHIFT 10 /* GP11_POL */ 3664*4882a593Smuzhiyun #define WM8995_GP11_POL_WIDTH 1 /* GP11_POL */ 3665*4882a593Smuzhiyun #define WM8995_GP11_OP_CFG 0x0200 /* GP11_OP_CFG */ 3666*4882a593Smuzhiyun #define WM8995_GP11_OP_CFG_MASK 0x0200 /* GP11_OP_CFG */ 3667*4882a593Smuzhiyun #define WM8995_GP11_OP_CFG_SHIFT 9 /* GP11_OP_CFG */ 3668*4882a593Smuzhiyun #define WM8995_GP11_OP_CFG_WIDTH 1 /* GP11_OP_CFG */ 3669*4882a593Smuzhiyun #define WM8995_GP11_DB 0x0100 /* GP11_DB */ 3670*4882a593Smuzhiyun #define WM8995_GP11_DB_MASK 0x0100 /* GP11_DB */ 3671*4882a593Smuzhiyun #define WM8995_GP11_DB_SHIFT 8 /* GP11_DB */ 3672*4882a593Smuzhiyun #define WM8995_GP11_DB_WIDTH 1 /* GP11_DB */ 3673*4882a593Smuzhiyun #define WM8995_GP11_LVL 0x0040 /* GP11_LVL */ 3674*4882a593Smuzhiyun #define WM8995_GP11_LVL_MASK 0x0040 /* GP11_LVL */ 3675*4882a593Smuzhiyun #define WM8995_GP11_LVL_SHIFT 6 /* GP11_LVL */ 3676*4882a593Smuzhiyun #define WM8995_GP11_LVL_WIDTH 1 /* GP11_LVL */ 3677*4882a593Smuzhiyun #define WM8995_GP11_FN_MASK 0x001F /* GP11_FN - [4:0] */ 3678*4882a593Smuzhiyun #define WM8995_GP11_FN_SHIFT 0 /* GP11_FN - [4:0] */ 3679*4882a593Smuzhiyun #define WM8995_GP11_FN_WIDTH 5 /* GP11_FN - [4:0] */ 3680*4882a593Smuzhiyun 3681*4882a593Smuzhiyun /* 3682*4882a593Smuzhiyun * R1803 (0x70B) - GPIO 12 3683*4882a593Smuzhiyun */ 3684*4882a593Smuzhiyun #define WM8995_GP12_DIR 0x8000 /* GP12_DIR */ 3685*4882a593Smuzhiyun #define WM8995_GP12_DIR_MASK 0x8000 /* GP12_DIR */ 3686*4882a593Smuzhiyun #define WM8995_GP12_DIR_SHIFT 15 /* GP12_DIR */ 3687*4882a593Smuzhiyun #define WM8995_GP12_DIR_WIDTH 1 /* GP12_DIR */ 3688*4882a593Smuzhiyun #define WM8995_GP12_PU 0x4000 /* GP12_PU */ 3689*4882a593Smuzhiyun #define WM8995_GP12_PU_MASK 0x4000 /* GP12_PU */ 3690*4882a593Smuzhiyun #define WM8995_GP12_PU_SHIFT 14 /* GP12_PU */ 3691*4882a593Smuzhiyun #define WM8995_GP12_PU_WIDTH 1 /* GP12_PU */ 3692*4882a593Smuzhiyun #define WM8995_GP12_PD 0x2000 /* GP12_PD */ 3693*4882a593Smuzhiyun #define WM8995_GP12_PD_MASK 0x2000 /* GP12_PD */ 3694*4882a593Smuzhiyun #define WM8995_GP12_PD_SHIFT 13 /* GP12_PD */ 3695*4882a593Smuzhiyun #define WM8995_GP12_PD_WIDTH 1 /* GP12_PD */ 3696*4882a593Smuzhiyun #define WM8995_GP12_POL 0x0400 /* GP12_POL */ 3697*4882a593Smuzhiyun #define WM8995_GP12_POL_MASK 0x0400 /* GP12_POL */ 3698*4882a593Smuzhiyun #define WM8995_GP12_POL_SHIFT 10 /* GP12_POL */ 3699*4882a593Smuzhiyun #define WM8995_GP12_POL_WIDTH 1 /* GP12_POL */ 3700*4882a593Smuzhiyun #define WM8995_GP12_OP_CFG 0x0200 /* GP12_OP_CFG */ 3701*4882a593Smuzhiyun #define WM8995_GP12_OP_CFG_MASK 0x0200 /* GP12_OP_CFG */ 3702*4882a593Smuzhiyun #define WM8995_GP12_OP_CFG_SHIFT 9 /* GP12_OP_CFG */ 3703*4882a593Smuzhiyun #define WM8995_GP12_OP_CFG_WIDTH 1 /* GP12_OP_CFG */ 3704*4882a593Smuzhiyun #define WM8995_GP12_DB 0x0100 /* GP12_DB */ 3705*4882a593Smuzhiyun #define WM8995_GP12_DB_MASK 0x0100 /* GP12_DB */ 3706*4882a593Smuzhiyun #define WM8995_GP12_DB_SHIFT 8 /* GP12_DB */ 3707*4882a593Smuzhiyun #define WM8995_GP12_DB_WIDTH 1 /* GP12_DB */ 3708*4882a593Smuzhiyun #define WM8995_GP12_LVL 0x0040 /* GP12_LVL */ 3709*4882a593Smuzhiyun #define WM8995_GP12_LVL_MASK 0x0040 /* GP12_LVL */ 3710*4882a593Smuzhiyun #define WM8995_GP12_LVL_SHIFT 6 /* GP12_LVL */ 3711*4882a593Smuzhiyun #define WM8995_GP12_LVL_WIDTH 1 /* GP12_LVL */ 3712*4882a593Smuzhiyun #define WM8995_GP12_FN_MASK 0x001F /* GP12_FN - [4:0] */ 3713*4882a593Smuzhiyun #define WM8995_GP12_FN_SHIFT 0 /* GP12_FN - [4:0] */ 3714*4882a593Smuzhiyun #define WM8995_GP12_FN_WIDTH 5 /* GP12_FN - [4:0] */ 3715*4882a593Smuzhiyun 3716*4882a593Smuzhiyun /* 3717*4882a593Smuzhiyun * R1804 (0x70C) - GPIO 13 3718*4882a593Smuzhiyun */ 3719*4882a593Smuzhiyun #define WM8995_GP13_DIR 0x8000 /* GP13_DIR */ 3720*4882a593Smuzhiyun #define WM8995_GP13_DIR_MASK 0x8000 /* GP13_DIR */ 3721*4882a593Smuzhiyun #define WM8995_GP13_DIR_SHIFT 15 /* GP13_DIR */ 3722*4882a593Smuzhiyun #define WM8995_GP13_DIR_WIDTH 1 /* GP13_DIR */ 3723*4882a593Smuzhiyun #define WM8995_GP13_PU 0x4000 /* GP13_PU */ 3724*4882a593Smuzhiyun #define WM8995_GP13_PU_MASK 0x4000 /* GP13_PU */ 3725*4882a593Smuzhiyun #define WM8995_GP13_PU_SHIFT 14 /* GP13_PU */ 3726*4882a593Smuzhiyun #define WM8995_GP13_PU_WIDTH 1 /* GP13_PU */ 3727*4882a593Smuzhiyun #define WM8995_GP13_PD 0x2000 /* GP13_PD */ 3728*4882a593Smuzhiyun #define WM8995_GP13_PD_MASK 0x2000 /* GP13_PD */ 3729*4882a593Smuzhiyun #define WM8995_GP13_PD_SHIFT 13 /* GP13_PD */ 3730*4882a593Smuzhiyun #define WM8995_GP13_PD_WIDTH 1 /* GP13_PD */ 3731*4882a593Smuzhiyun #define WM8995_GP13_POL 0x0400 /* GP13_POL */ 3732*4882a593Smuzhiyun #define WM8995_GP13_POL_MASK 0x0400 /* GP13_POL */ 3733*4882a593Smuzhiyun #define WM8995_GP13_POL_SHIFT 10 /* GP13_POL */ 3734*4882a593Smuzhiyun #define WM8995_GP13_POL_WIDTH 1 /* GP13_POL */ 3735*4882a593Smuzhiyun #define WM8995_GP13_OP_CFG 0x0200 /* GP13_OP_CFG */ 3736*4882a593Smuzhiyun #define WM8995_GP13_OP_CFG_MASK 0x0200 /* GP13_OP_CFG */ 3737*4882a593Smuzhiyun #define WM8995_GP13_OP_CFG_SHIFT 9 /* GP13_OP_CFG */ 3738*4882a593Smuzhiyun #define WM8995_GP13_OP_CFG_WIDTH 1 /* GP13_OP_CFG */ 3739*4882a593Smuzhiyun #define WM8995_GP13_DB 0x0100 /* GP13_DB */ 3740*4882a593Smuzhiyun #define WM8995_GP13_DB_MASK 0x0100 /* GP13_DB */ 3741*4882a593Smuzhiyun #define WM8995_GP13_DB_SHIFT 8 /* GP13_DB */ 3742*4882a593Smuzhiyun #define WM8995_GP13_DB_WIDTH 1 /* GP13_DB */ 3743*4882a593Smuzhiyun #define WM8995_GP13_LVL 0x0040 /* GP13_LVL */ 3744*4882a593Smuzhiyun #define WM8995_GP13_LVL_MASK 0x0040 /* GP13_LVL */ 3745*4882a593Smuzhiyun #define WM8995_GP13_LVL_SHIFT 6 /* GP13_LVL */ 3746*4882a593Smuzhiyun #define WM8995_GP13_LVL_WIDTH 1 /* GP13_LVL */ 3747*4882a593Smuzhiyun #define WM8995_GP13_FN_MASK 0x001F /* GP13_FN - [4:0] */ 3748*4882a593Smuzhiyun #define WM8995_GP13_FN_SHIFT 0 /* GP13_FN - [4:0] */ 3749*4882a593Smuzhiyun #define WM8995_GP13_FN_WIDTH 5 /* GP13_FN - [4:0] */ 3750*4882a593Smuzhiyun 3751*4882a593Smuzhiyun /* 3752*4882a593Smuzhiyun * R1805 (0x70D) - GPIO 14 3753*4882a593Smuzhiyun */ 3754*4882a593Smuzhiyun #define WM8995_GP14_DIR 0x8000 /* GP14_DIR */ 3755*4882a593Smuzhiyun #define WM8995_GP14_DIR_MASK 0x8000 /* GP14_DIR */ 3756*4882a593Smuzhiyun #define WM8995_GP14_DIR_SHIFT 15 /* GP14_DIR */ 3757*4882a593Smuzhiyun #define WM8995_GP14_DIR_WIDTH 1 /* GP14_DIR */ 3758*4882a593Smuzhiyun #define WM8995_GP14_PU 0x4000 /* GP14_PU */ 3759*4882a593Smuzhiyun #define WM8995_GP14_PU_MASK 0x4000 /* GP14_PU */ 3760*4882a593Smuzhiyun #define WM8995_GP14_PU_SHIFT 14 /* GP14_PU */ 3761*4882a593Smuzhiyun #define WM8995_GP14_PU_WIDTH 1 /* GP14_PU */ 3762*4882a593Smuzhiyun #define WM8995_GP14_PD 0x2000 /* GP14_PD */ 3763*4882a593Smuzhiyun #define WM8995_GP14_PD_MASK 0x2000 /* GP14_PD */ 3764*4882a593Smuzhiyun #define WM8995_GP14_PD_SHIFT 13 /* GP14_PD */ 3765*4882a593Smuzhiyun #define WM8995_GP14_PD_WIDTH 1 /* GP14_PD */ 3766*4882a593Smuzhiyun #define WM8995_GP14_POL 0x0400 /* GP14_POL */ 3767*4882a593Smuzhiyun #define WM8995_GP14_POL_MASK 0x0400 /* GP14_POL */ 3768*4882a593Smuzhiyun #define WM8995_GP14_POL_SHIFT 10 /* GP14_POL */ 3769*4882a593Smuzhiyun #define WM8995_GP14_POL_WIDTH 1 /* GP14_POL */ 3770*4882a593Smuzhiyun #define WM8995_GP14_OP_CFG 0x0200 /* GP14_OP_CFG */ 3771*4882a593Smuzhiyun #define WM8995_GP14_OP_CFG_MASK 0x0200 /* GP14_OP_CFG */ 3772*4882a593Smuzhiyun #define WM8995_GP14_OP_CFG_SHIFT 9 /* GP14_OP_CFG */ 3773*4882a593Smuzhiyun #define WM8995_GP14_OP_CFG_WIDTH 1 /* GP14_OP_CFG */ 3774*4882a593Smuzhiyun #define WM8995_GP14_DB 0x0100 /* GP14_DB */ 3775*4882a593Smuzhiyun #define WM8995_GP14_DB_MASK 0x0100 /* GP14_DB */ 3776*4882a593Smuzhiyun #define WM8995_GP14_DB_SHIFT 8 /* GP14_DB */ 3777*4882a593Smuzhiyun #define WM8995_GP14_DB_WIDTH 1 /* GP14_DB */ 3778*4882a593Smuzhiyun #define WM8995_GP14_LVL 0x0040 /* GP14_LVL */ 3779*4882a593Smuzhiyun #define WM8995_GP14_LVL_MASK 0x0040 /* GP14_LVL */ 3780*4882a593Smuzhiyun #define WM8995_GP14_LVL_SHIFT 6 /* GP14_LVL */ 3781*4882a593Smuzhiyun #define WM8995_GP14_LVL_WIDTH 1 /* GP14_LVL */ 3782*4882a593Smuzhiyun #define WM8995_GP14_FN_MASK 0x001F /* GP14_FN - [4:0] */ 3783*4882a593Smuzhiyun #define WM8995_GP14_FN_SHIFT 0 /* GP14_FN - [4:0] */ 3784*4882a593Smuzhiyun #define WM8995_GP14_FN_WIDTH 5 /* GP14_FN - [4:0] */ 3785*4882a593Smuzhiyun 3786*4882a593Smuzhiyun /* 3787*4882a593Smuzhiyun * R1824 (0x720) - Pull Control (1) 3788*4882a593Smuzhiyun */ 3789*4882a593Smuzhiyun #define WM8995_DMICDAT3_PD 0x4000 /* DMICDAT3_PD */ 3790*4882a593Smuzhiyun #define WM8995_DMICDAT3_PD_MASK 0x4000 /* DMICDAT3_PD */ 3791*4882a593Smuzhiyun #define WM8995_DMICDAT3_PD_SHIFT 14 /* DMICDAT3_PD */ 3792*4882a593Smuzhiyun #define WM8995_DMICDAT3_PD_WIDTH 1 /* DMICDAT3_PD */ 3793*4882a593Smuzhiyun #define WM8995_DMICDAT2_PD 0x1000 /* DMICDAT2_PD */ 3794*4882a593Smuzhiyun #define WM8995_DMICDAT2_PD_MASK 0x1000 /* DMICDAT2_PD */ 3795*4882a593Smuzhiyun #define WM8995_DMICDAT2_PD_SHIFT 12 /* DMICDAT2_PD */ 3796*4882a593Smuzhiyun #define WM8995_DMICDAT2_PD_WIDTH 1 /* DMICDAT2_PD */ 3797*4882a593Smuzhiyun #define WM8995_DMICDAT1_PD 0x0400 /* DMICDAT1_PD */ 3798*4882a593Smuzhiyun #define WM8995_DMICDAT1_PD_MASK 0x0400 /* DMICDAT1_PD */ 3799*4882a593Smuzhiyun #define WM8995_DMICDAT1_PD_SHIFT 10 /* DMICDAT1_PD */ 3800*4882a593Smuzhiyun #define WM8995_DMICDAT1_PD_WIDTH 1 /* DMICDAT1_PD */ 3801*4882a593Smuzhiyun #define WM8995_MCLK2_PU 0x0200 /* MCLK2_PU */ 3802*4882a593Smuzhiyun #define WM8995_MCLK2_PU_MASK 0x0200 /* MCLK2_PU */ 3803*4882a593Smuzhiyun #define WM8995_MCLK2_PU_SHIFT 9 /* MCLK2_PU */ 3804*4882a593Smuzhiyun #define WM8995_MCLK2_PU_WIDTH 1 /* MCLK2_PU */ 3805*4882a593Smuzhiyun #define WM8995_MCLK2_PD 0x0100 /* MCLK2_PD */ 3806*4882a593Smuzhiyun #define WM8995_MCLK2_PD_MASK 0x0100 /* MCLK2_PD */ 3807*4882a593Smuzhiyun #define WM8995_MCLK2_PD_SHIFT 8 /* MCLK2_PD */ 3808*4882a593Smuzhiyun #define WM8995_MCLK2_PD_WIDTH 1 /* MCLK2_PD */ 3809*4882a593Smuzhiyun #define WM8995_MCLK1_PU 0x0080 /* MCLK1_PU */ 3810*4882a593Smuzhiyun #define WM8995_MCLK1_PU_MASK 0x0080 /* MCLK1_PU */ 3811*4882a593Smuzhiyun #define WM8995_MCLK1_PU_SHIFT 7 /* MCLK1_PU */ 3812*4882a593Smuzhiyun #define WM8995_MCLK1_PU_WIDTH 1 /* MCLK1_PU */ 3813*4882a593Smuzhiyun #define WM8995_MCLK1_PD 0x0040 /* MCLK1_PD */ 3814*4882a593Smuzhiyun #define WM8995_MCLK1_PD_MASK 0x0040 /* MCLK1_PD */ 3815*4882a593Smuzhiyun #define WM8995_MCLK1_PD_SHIFT 6 /* MCLK1_PD */ 3816*4882a593Smuzhiyun #define WM8995_MCLK1_PD_WIDTH 1 /* MCLK1_PD */ 3817*4882a593Smuzhiyun #define WM8995_DACDAT1_PU 0x0020 /* DACDAT1_PU */ 3818*4882a593Smuzhiyun #define WM8995_DACDAT1_PU_MASK 0x0020 /* DACDAT1_PU */ 3819*4882a593Smuzhiyun #define WM8995_DACDAT1_PU_SHIFT 5 /* DACDAT1_PU */ 3820*4882a593Smuzhiyun #define WM8995_DACDAT1_PU_WIDTH 1 /* DACDAT1_PU */ 3821*4882a593Smuzhiyun #define WM8995_DACDAT1_PD 0x0010 /* DACDAT1_PD */ 3822*4882a593Smuzhiyun #define WM8995_DACDAT1_PD_MASK 0x0010 /* DACDAT1_PD */ 3823*4882a593Smuzhiyun #define WM8995_DACDAT1_PD_SHIFT 4 /* DACDAT1_PD */ 3824*4882a593Smuzhiyun #define WM8995_DACDAT1_PD_WIDTH 1 /* DACDAT1_PD */ 3825*4882a593Smuzhiyun #define WM8995_DACLRCLK1_PU 0x0008 /* DACLRCLK1_PU */ 3826*4882a593Smuzhiyun #define WM8995_DACLRCLK1_PU_MASK 0x0008 /* DACLRCLK1_PU */ 3827*4882a593Smuzhiyun #define WM8995_DACLRCLK1_PU_SHIFT 3 /* DACLRCLK1_PU */ 3828*4882a593Smuzhiyun #define WM8995_DACLRCLK1_PU_WIDTH 1 /* DACLRCLK1_PU */ 3829*4882a593Smuzhiyun #define WM8995_DACLRCLK1_PD 0x0004 /* DACLRCLK1_PD */ 3830*4882a593Smuzhiyun #define WM8995_DACLRCLK1_PD_MASK 0x0004 /* DACLRCLK1_PD */ 3831*4882a593Smuzhiyun #define WM8995_DACLRCLK1_PD_SHIFT 2 /* DACLRCLK1_PD */ 3832*4882a593Smuzhiyun #define WM8995_DACLRCLK1_PD_WIDTH 1 /* DACLRCLK1_PD */ 3833*4882a593Smuzhiyun #define WM8995_BCLK1_PU 0x0002 /* BCLK1_PU */ 3834*4882a593Smuzhiyun #define WM8995_BCLK1_PU_MASK 0x0002 /* BCLK1_PU */ 3835*4882a593Smuzhiyun #define WM8995_BCLK1_PU_SHIFT 1 /* BCLK1_PU */ 3836*4882a593Smuzhiyun #define WM8995_BCLK1_PU_WIDTH 1 /* BCLK1_PU */ 3837*4882a593Smuzhiyun #define WM8995_BCLK1_PD 0x0001 /* BCLK1_PD */ 3838*4882a593Smuzhiyun #define WM8995_BCLK1_PD_MASK 0x0001 /* BCLK1_PD */ 3839*4882a593Smuzhiyun #define WM8995_BCLK1_PD_SHIFT 0 /* BCLK1_PD */ 3840*4882a593Smuzhiyun #define WM8995_BCLK1_PD_WIDTH 1 /* BCLK1_PD */ 3841*4882a593Smuzhiyun 3842*4882a593Smuzhiyun /* 3843*4882a593Smuzhiyun * R1825 (0x721) - Pull Control (2) 3844*4882a593Smuzhiyun */ 3845*4882a593Smuzhiyun #define WM8995_LDO1ENA_PD 0x0010 /* LDO1ENA_PD */ 3846*4882a593Smuzhiyun #define WM8995_LDO1ENA_PD_MASK 0x0010 /* LDO1ENA_PD */ 3847*4882a593Smuzhiyun #define WM8995_LDO1ENA_PD_SHIFT 4 /* LDO1ENA_PD */ 3848*4882a593Smuzhiyun #define WM8995_LDO1ENA_PD_WIDTH 1 /* LDO1ENA_PD */ 3849*4882a593Smuzhiyun #define WM8995_MODE_PD 0x0004 /* MODE_PD */ 3850*4882a593Smuzhiyun #define WM8995_MODE_PD_MASK 0x0004 /* MODE_PD */ 3851*4882a593Smuzhiyun #define WM8995_MODE_PD_SHIFT 2 /* MODE_PD */ 3852*4882a593Smuzhiyun #define WM8995_MODE_PD_WIDTH 1 /* MODE_PD */ 3853*4882a593Smuzhiyun #define WM8995_CSNADDR_PD 0x0001 /* CSNADDR_PD */ 3854*4882a593Smuzhiyun #define WM8995_CSNADDR_PD_MASK 0x0001 /* CSNADDR_PD */ 3855*4882a593Smuzhiyun #define WM8995_CSNADDR_PD_SHIFT 0 /* CSNADDR_PD */ 3856*4882a593Smuzhiyun #define WM8995_CSNADDR_PD_WIDTH 1 /* CSNADDR_PD */ 3857*4882a593Smuzhiyun 3858*4882a593Smuzhiyun /* 3859*4882a593Smuzhiyun * R1840 (0x730) - Interrupt Status 1 3860*4882a593Smuzhiyun */ 3861*4882a593Smuzhiyun #define WM8995_GP14_EINT 0x2000 /* GP14_EINT */ 3862*4882a593Smuzhiyun #define WM8995_GP14_EINT_MASK 0x2000 /* GP14_EINT */ 3863*4882a593Smuzhiyun #define WM8995_GP14_EINT_SHIFT 13 /* GP14_EINT */ 3864*4882a593Smuzhiyun #define WM8995_GP14_EINT_WIDTH 1 /* GP14_EINT */ 3865*4882a593Smuzhiyun #define WM8995_GP13_EINT 0x1000 /* GP13_EINT */ 3866*4882a593Smuzhiyun #define WM8995_GP13_EINT_MASK 0x1000 /* GP13_EINT */ 3867*4882a593Smuzhiyun #define WM8995_GP13_EINT_SHIFT 12 /* GP13_EINT */ 3868*4882a593Smuzhiyun #define WM8995_GP13_EINT_WIDTH 1 /* GP13_EINT */ 3869*4882a593Smuzhiyun #define WM8995_GP12_EINT 0x0800 /* GP12_EINT */ 3870*4882a593Smuzhiyun #define WM8995_GP12_EINT_MASK 0x0800 /* GP12_EINT */ 3871*4882a593Smuzhiyun #define WM8995_GP12_EINT_SHIFT 11 /* GP12_EINT */ 3872*4882a593Smuzhiyun #define WM8995_GP12_EINT_WIDTH 1 /* GP12_EINT */ 3873*4882a593Smuzhiyun #define WM8995_GP11_EINT 0x0400 /* GP11_EINT */ 3874*4882a593Smuzhiyun #define WM8995_GP11_EINT_MASK 0x0400 /* GP11_EINT */ 3875*4882a593Smuzhiyun #define WM8995_GP11_EINT_SHIFT 10 /* GP11_EINT */ 3876*4882a593Smuzhiyun #define WM8995_GP11_EINT_WIDTH 1 /* GP11_EINT */ 3877*4882a593Smuzhiyun #define WM8995_GP10_EINT 0x0200 /* GP10_EINT */ 3878*4882a593Smuzhiyun #define WM8995_GP10_EINT_MASK 0x0200 /* GP10_EINT */ 3879*4882a593Smuzhiyun #define WM8995_GP10_EINT_SHIFT 9 /* GP10_EINT */ 3880*4882a593Smuzhiyun #define WM8995_GP10_EINT_WIDTH 1 /* GP10_EINT */ 3881*4882a593Smuzhiyun #define WM8995_GP9_EINT 0x0100 /* GP9_EINT */ 3882*4882a593Smuzhiyun #define WM8995_GP9_EINT_MASK 0x0100 /* GP9_EINT */ 3883*4882a593Smuzhiyun #define WM8995_GP9_EINT_SHIFT 8 /* GP9_EINT */ 3884*4882a593Smuzhiyun #define WM8995_GP9_EINT_WIDTH 1 /* GP9_EINT */ 3885*4882a593Smuzhiyun #define WM8995_GP8_EINT 0x0080 /* GP8_EINT */ 3886*4882a593Smuzhiyun #define WM8995_GP8_EINT_MASK 0x0080 /* GP8_EINT */ 3887*4882a593Smuzhiyun #define WM8995_GP8_EINT_SHIFT 7 /* GP8_EINT */ 3888*4882a593Smuzhiyun #define WM8995_GP8_EINT_WIDTH 1 /* GP8_EINT */ 3889*4882a593Smuzhiyun #define WM8995_GP7_EINT 0x0040 /* GP7_EINT */ 3890*4882a593Smuzhiyun #define WM8995_GP7_EINT_MASK 0x0040 /* GP7_EINT */ 3891*4882a593Smuzhiyun #define WM8995_GP7_EINT_SHIFT 6 /* GP7_EINT */ 3892*4882a593Smuzhiyun #define WM8995_GP7_EINT_WIDTH 1 /* GP7_EINT */ 3893*4882a593Smuzhiyun #define WM8995_GP6_EINT 0x0020 /* GP6_EINT */ 3894*4882a593Smuzhiyun #define WM8995_GP6_EINT_MASK 0x0020 /* GP6_EINT */ 3895*4882a593Smuzhiyun #define WM8995_GP6_EINT_SHIFT 5 /* GP6_EINT */ 3896*4882a593Smuzhiyun #define WM8995_GP6_EINT_WIDTH 1 /* GP6_EINT */ 3897*4882a593Smuzhiyun #define WM8995_GP5_EINT 0x0010 /* GP5_EINT */ 3898*4882a593Smuzhiyun #define WM8995_GP5_EINT_MASK 0x0010 /* GP5_EINT */ 3899*4882a593Smuzhiyun #define WM8995_GP5_EINT_SHIFT 4 /* GP5_EINT */ 3900*4882a593Smuzhiyun #define WM8995_GP5_EINT_WIDTH 1 /* GP5_EINT */ 3901*4882a593Smuzhiyun #define WM8995_GP4_EINT 0x0008 /* GP4_EINT */ 3902*4882a593Smuzhiyun #define WM8995_GP4_EINT_MASK 0x0008 /* GP4_EINT */ 3903*4882a593Smuzhiyun #define WM8995_GP4_EINT_SHIFT 3 /* GP4_EINT */ 3904*4882a593Smuzhiyun #define WM8995_GP4_EINT_WIDTH 1 /* GP4_EINT */ 3905*4882a593Smuzhiyun #define WM8995_GP3_EINT 0x0004 /* GP3_EINT */ 3906*4882a593Smuzhiyun #define WM8995_GP3_EINT_MASK 0x0004 /* GP3_EINT */ 3907*4882a593Smuzhiyun #define WM8995_GP3_EINT_SHIFT 2 /* GP3_EINT */ 3908*4882a593Smuzhiyun #define WM8995_GP3_EINT_WIDTH 1 /* GP3_EINT */ 3909*4882a593Smuzhiyun #define WM8995_GP2_EINT 0x0002 /* GP2_EINT */ 3910*4882a593Smuzhiyun #define WM8995_GP2_EINT_MASK 0x0002 /* GP2_EINT */ 3911*4882a593Smuzhiyun #define WM8995_GP2_EINT_SHIFT 1 /* GP2_EINT */ 3912*4882a593Smuzhiyun #define WM8995_GP2_EINT_WIDTH 1 /* GP2_EINT */ 3913*4882a593Smuzhiyun #define WM8995_GP1_EINT 0x0001 /* GP1_EINT */ 3914*4882a593Smuzhiyun #define WM8995_GP1_EINT_MASK 0x0001 /* GP1_EINT */ 3915*4882a593Smuzhiyun #define WM8995_GP1_EINT_SHIFT 0 /* GP1_EINT */ 3916*4882a593Smuzhiyun #define WM8995_GP1_EINT_WIDTH 1 /* GP1_EINT */ 3917*4882a593Smuzhiyun 3918*4882a593Smuzhiyun /* 3919*4882a593Smuzhiyun * R1841 (0x731) - Interrupt Status 2 3920*4882a593Smuzhiyun */ 3921*4882a593Smuzhiyun #define WM8995_DCS_DONE_23_EINT 0x1000 /* DCS_DONE_23_EINT */ 3922*4882a593Smuzhiyun #define WM8995_DCS_DONE_23_EINT_MASK 0x1000 /* DCS_DONE_23_EINT */ 3923*4882a593Smuzhiyun #define WM8995_DCS_DONE_23_EINT_SHIFT 12 /* DCS_DONE_23_EINT */ 3924*4882a593Smuzhiyun #define WM8995_DCS_DONE_23_EINT_WIDTH 1 /* DCS_DONE_23_EINT */ 3925*4882a593Smuzhiyun #define WM8995_DCS_DONE_01_EINT 0x0800 /* DCS_DONE_01_EINT */ 3926*4882a593Smuzhiyun #define WM8995_DCS_DONE_01_EINT_MASK 0x0800 /* DCS_DONE_01_EINT */ 3927*4882a593Smuzhiyun #define WM8995_DCS_DONE_01_EINT_SHIFT 11 /* DCS_DONE_01_EINT */ 3928*4882a593Smuzhiyun #define WM8995_DCS_DONE_01_EINT_WIDTH 1 /* DCS_DONE_01_EINT */ 3929*4882a593Smuzhiyun #define WM8995_WSEQ_DONE_EINT 0x0400 /* WSEQ_DONE_EINT */ 3930*4882a593Smuzhiyun #define WM8995_WSEQ_DONE_EINT_MASK 0x0400 /* WSEQ_DONE_EINT */ 3931*4882a593Smuzhiyun #define WM8995_WSEQ_DONE_EINT_SHIFT 10 /* WSEQ_DONE_EINT */ 3932*4882a593Smuzhiyun #define WM8995_WSEQ_DONE_EINT_WIDTH 1 /* WSEQ_DONE_EINT */ 3933*4882a593Smuzhiyun #define WM8995_FIFOS_ERR_EINT 0x0200 /* FIFOS_ERR_EINT */ 3934*4882a593Smuzhiyun #define WM8995_FIFOS_ERR_EINT_MASK 0x0200 /* FIFOS_ERR_EINT */ 3935*4882a593Smuzhiyun #define WM8995_FIFOS_ERR_EINT_SHIFT 9 /* FIFOS_ERR_EINT */ 3936*4882a593Smuzhiyun #define WM8995_FIFOS_ERR_EINT_WIDTH 1 /* FIFOS_ERR_EINT */ 3937*4882a593Smuzhiyun #define WM8995_AIF2DRC_SIG_DET_EINT 0x0100 /* AIF2DRC_SIG_DET_EINT */ 3938*4882a593Smuzhiyun #define WM8995_AIF2DRC_SIG_DET_EINT_MASK 0x0100 /* AIF2DRC_SIG_DET_EINT */ 3939*4882a593Smuzhiyun #define WM8995_AIF2DRC_SIG_DET_EINT_SHIFT 8 /* AIF2DRC_SIG_DET_EINT */ 3940*4882a593Smuzhiyun #define WM8995_AIF2DRC_SIG_DET_EINT_WIDTH 1 /* AIF2DRC_SIG_DET_EINT */ 3941*4882a593Smuzhiyun #define WM8995_AIF1DRC2_SIG_DET_EINT 0x0080 /* AIF1DRC2_SIG_DET_EINT */ 3942*4882a593Smuzhiyun #define WM8995_AIF1DRC2_SIG_DET_EINT_MASK 0x0080 /* AIF1DRC2_SIG_DET_EINT */ 3943*4882a593Smuzhiyun #define WM8995_AIF1DRC2_SIG_DET_EINT_SHIFT 7 /* AIF1DRC2_SIG_DET_EINT */ 3944*4882a593Smuzhiyun #define WM8995_AIF1DRC2_SIG_DET_EINT_WIDTH 1 /* AIF1DRC2_SIG_DET_EINT */ 3945*4882a593Smuzhiyun #define WM8995_AIF1DRC1_SIG_DET_EINT 0x0040 /* AIF1DRC1_SIG_DET_EINT */ 3946*4882a593Smuzhiyun #define WM8995_AIF1DRC1_SIG_DET_EINT_MASK 0x0040 /* AIF1DRC1_SIG_DET_EINT */ 3947*4882a593Smuzhiyun #define WM8995_AIF1DRC1_SIG_DET_EINT_SHIFT 6 /* AIF1DRC1_SIG_DET_EINT */ 3948*4882a593Smuzhiyun #define WM8995_AIF1DRC1_SIG_DET_EINT_WIDTH 1 /* AIF1DRC1_SIG_DET_EINT */ 3949*4882a593Smuzhiyun #define WM8995_SRC2_LOCK_EINT 0x0020 /* SRC2_LOCK_EINT */ 3950*4882a593Smuzhiyun #define WM8995_SRC2_LOCK_EINT_MASK 0x0020 /* SRC2_LOCK_EINT */ 3951*4882a593Smuzhiyun #define WM8995_SRC2_LOCK_EINT_SHIFT 5 /* SRC2_LOCK_EINT */ 3952*4882a593Smuzhiyun #define WM8995_SRC2_LOCK_EINT_WIDTH 1 /* SRC2_LOCK_EINT */ 3953*4882a593Smuzhiyun #define WM8995_SRC1_LOCK_EINT 0x0010 /* SRC1_LOCK_EINT */ 3954*4882a593Smuzhiyun #define WM8995_SRC1_LOCK_EINT_MASK 0x0010 /* SRC1_LOCK_EINT */ 3955*4882a593Smuzhiyun #define WM8995_SRC1_LOCK_EINT_SHIFT 4 /* SRC1_LOCK_EINT */ 3956*4882a593Smuzhiyun #define WM8995_SRC1_LOCK_EINT_WIDTH 1 /* SRC1_LOCK_EINT */ 3957*4882a593Smuzhiyun #define WM8995_FLL2_LOCK_EINT 0x0008 /* FLL2_LOCK_EINT */ 3958*4882a593Smuzhiyun #define WM8995_FLL2_LOCK_EINT_MASK 0x0008 /* FLL2_LOCK_EINT */ 3959*4882a593Smuzhiyun #define WM8995_FLL2_LOCK_EINT_SHIFT 3 /* FLL2_LOCK_EINT */ 3960*4882a593Smuzhiyun #define WM8995_FLL2_LOCK_EINT_WIDTH 1 /* FLL2_LOCK_EINT */ 3961*4882a593Smuzhiyun #define WM8995_FLL1_LOCK_EINT 0x0004 /* FLL1_LOCK_EINT */ 3962*4882a593Smuzhiyun #define WM8995_FLL1_LOCK_EINT_MASK 0x0004 /* FLL1_LOCK_EINT */ 3963*4882a593Smuzhiyun #define WM8995_FLL1_LOCK_EINT_SHIFT 2 /* FLL1_LOCK_EINT */ 3964*4882a593Smuzhiyun #define WM8995_FLL1_LOCK_EINT_WIDTH 1 /* FLL1_LOCK_EINT */ 3965*4882a593Smuzhiyun #define WM8995_HP_DONE_EINT 0x0002 /* HP_DONE_EINT */ 3966*4882a593Smuzhiyun #define WM8995_HP_DONE_EINT_MASK 0x0002 /* HP_DONE_EINT */ 3967*4882a593Smuzhiyun #define WM8995_HP_DONE_EINT_SHIFT 1 /* HP_DONE_EINT */ 3968*4882a593Smuzhiyun #define WM8995_HP_DONE_EINT_WIDTH 1 /* HP_DONE_EINT */ 3969*4882a593Smuzhiyun #define WM8995_MICD_EINT 0x0001 /* MICD_EINT */ 3970*4882a593Smuzhiyun #define WM8995_MICD_EINT_MASK 0x0001 /* MICD_EINT */ 3971*4882a593Smuzhiyun #define WM8995_MICD_EINT_SHIFT 0 /* MICD_EINT */ 3972*4882a593Smuzhiyun #define WM8995_MICD_EINT_WIDTH 1 /* MICD_EINT */ 3973*4882a593Smuzhiyun 3974*4882a593Smuzhiyun /* 3975*4882a593Smuzhiyun * R1842 (0x732) - Interrupt Raw Status 2 3976*4882a593Smuzhiyun */ 3977*4882a593Smuzhiyun #define WM8995_DCS_DONE_23_STS 0x1000 /* DCS_DONE_23_STS */ 3978*4882a593Smuzhiyun #define WM8995_DCS_DONE_23_STS_MASK 0x1000 /* DCS_DONE_23_STS */ 3979*4882a593Smuzhiyun #define WM8995_DCS_DONE_23_STS_SHIFT 12 /* DCS_DONE_23_STS */ 3980*4882a593Smuzhiyun #define WM8995_DCS_DONE_23_STS_WIDTH 1 /* DCS_DONE_23_STS */ 3981*4882a593Smuzhiyun #define WM8995_DCS_DONE_01_STS 0x0800 /* DCS_DONE_01_STS */ 3982*4882a593Smuzhiyun #define WM8995_DCS_DONE_01_STS_MASK 0x0800 /* DCS_DONE_01_STS */ 3983*4882a593Smuzhiyun #define WM8995_DCS_DONE_01_STS_SHIFT 11 /* DCS_DONE_01_STS */ 3984*4882a593Smuzhiyun #define WM8995_DCS_DONE_01_STS_WIDTH 1 /* DCS_DONE_01_STS */ 3985*4882a593Smuzhiyun #define WM8995_WSEQ_DONE_STS 0x0400 /* WSEQ_DONE_STS */ 3986*4882a593Smuzhiyun #define WM8995_WSEQ_DONE_STS_MASK 0x0400 /* WSEQ_DONE_STS */ 3987*4882a593Smuzhiyun #define WM8995_WSEQ_DONE_STS_SHIFT 10 /* WSEQ_DONE_STS */ 3988*4882a593Smuzhiyun #define WM8995_WSEQ_DONE_STS_WIDTH 1 /* WSEQ_DONE_STS */ 3989*4882a593Smuzhiyun #define WM8995_FIFOS_ERR_STS 0x0200 /* FIFOS_ERR_STS */ 3990*4882a593Smuzhiyun #define WM8995_FIFOS_ERR_STS_MASK 0x0200 /* FIFOS_ERR_STS */ 3991*4882a593Smuzhiyun #define WM8995_FIFOS_ERR_STS_SHIFT 9 /* FIFOS_ERR_STS */ 3992*4882a593Smuzhiyun #define WM8995_FIFOS_ERR_STS_WIDTH 1 /* FIFOS_ERR_STS */ 3993*4882a593Smuzhiyun #define WM8995_AIF2DRC_SIG_DET_STS 0x0100 /* AIF2DRC_SIG_DET_STS */ 3994*4882a593Smuzhiyun #define WM8995_AIF2DRC_SIG_DET_STS_MASK 0x0100 /* AIF2DRC_SIG_DET_STS */ 3995*4882a593Smuzhiyun #define WM8995_AIF2DRC_SIG_DET_STS_SHIFT 8 /* AIF2DRC_SIG_DET_STS */ 3996*4882a593Smuzhiyun #define WM8995_AIF2DRC_SIG_DET_STS_WIDTH 1 /* AIF2DRC_SIG_DET_STS */ 3997*4882a593Smuzhiyun #define WM8995_AIF1DRC2_SIG_DET_STS 0x0080 /* AIF1DRC2_SIG_DET_STS */ 3998*4882a593Smuzhiyun #define WM8995_AIF1DRC2_SIG_DET_STS_MASK 0x0080 /* AIF1DRC2_SIG_DET_STS */ 3999*4882a593Smuzhiyun #define WM8995_AIF1DRC2_SIG_DET_STS_SHIFT 7 /* AIF1DRC2_SIG_DET_STS */ 4000*4882a593Smuzhiyun #define WM8995_AIF1DRC2_SIG_DET_STS_WIDTH 1 /* AIF1DRC2_SIG_DET_STS */ 4001*4882a593Smuzhiyun #define WM8995_AIF1DRC1_SIG_DET_STS 0x0040 /* AIF1DRC1_SIG_DET_STS */ 4002*4882a593Smuzhiyun #define WM8995_AIF1DRC1_SIG_DET_STS_MASK 0x0040 /* AIF1DRC1_SIG_DET_STS */ 4003*4882a593Smuzhiyun #define WM8995_AIF1DRC1_SIG_DET_STS_SHIFT 6 /* AIF1DRC1_SIG_DET_STS */ 4004*4882a593Smuzhiyun #define WM8995_AIF1DRC1_SIG_DET_STS_WIDTH 1 /* AIF1DRC1_SIG_DET_STS */ 4005*4882a593Smuzhiyun #define WM8995_SRC2_LOCK_STS 0x0020 /* SRC2_LOCK_STS */ 4006*4882a593Smuzhiyun #define WM8995_SRC2_LOCK_STS_MASK 0x0020 /* SRC2_LOCK_STS */ 4007*4882a593Smuzhiyun #define WM8995_SRC2_LOCK_STS_SHIFT 5 /* SRC2_LOCK_STS */ 4008*4882a593Smuzhiyun #define WM8995_SRC2_LOCK_STS_WIDTH 1 /* SRC2_LOCK_STS */ 4009*4882a593Smuzhiyun #define WM8995_SRC1_LOCK_STS 0x0010 /* SRC1_LOCK_STS */ 4010*4882a593Smuzhiyun #define WM8995_SRC1_LOCK_STS_MASK 0x0010 /* SRC1_LOCK_STS */ 4011*4882a593Smuzhiyun #define WM8995_SRC1_LOCK_STS_SHIFT 4 /* SRC1_LOCK_STS */ 4012*4882a593Smuzhiyun #define WM8995_SRC1_LOCK_STS_WIDTH 1 /* SRC1_LOCK_STS */ 4013*4882a593Smuzhiyun #define WM8995_FLL2_LOCK_STS 0x0008 /* FLL2_LOCK_STS */ 4014*4882a593Smuzhiyun #define WM8995_FLL2_LOCK_STS_MASK 0x0008 /* FLL2_LOCK_STS */ 4015*4882a593Smuzhiyun #define WM8995_FLL2_LOCK_STS_SHIFT 3 /* FLL2_LOCK_STS */ 4016*4882a593Smuzhiyun #define WM8995_FLL2_LOCK_STS_WIDTH 1 /* FLL2_LOCK_STS */ 4017*4882a593Smuzhiyun #define WM8995_FLL1_LOCK_STS 0x0004 /* FLL1_LOCK_STS */ 4018*4882a593Smuzhiyun #define WM8995_FLL1_LOCK_STS_MASK 0x0004 /* FLL1_LOCK_STS */ 4019*4882a593Smuzhiyun #define WM8995_FLL1_LOCK_STS_SHIFT 2 /* FLL1_LOCK_STS */ 4020*4882a593Smuzhiyun #define WM8995_FLL1_LOCK_STS_WIDTH 1 /* FLL1_LOCK_STS */ 4021*4882a593Smuzhiyun 4022*4882a593Smuzhiyun /* 4023*4882a593Smuzhiyun * R1848 (0x738) - Interrupt Status 1 Mask 4024*4882a593Smuzhiyun */ 4025*4882a593Smuzhiyun #define WM8995_IM_GP14_EINT 0x2000 /* IM_GP14_EINT */ 4026*4882a593Smuzhiyun #define WM8995_IM_GP14_EINT_MASK 0x2000 /* IM_GP14_EINT */ 4027*4882a593Smuzhiyun #define WM8995_IM_GP14_EINT_SHIFT 13 /* IM_GP14_EINT */ 4028*4882a593Smuzhiyun #define WM8995_IM_GP14_EINT_WIDTH 1 /* IM_GP14_EINT */ 4029*4882a593Smuzhiyun #define WM8995_IM_GP13_EINT 0x1000 /* IM_GP13_EINT */ 4030*4882a593Smuzhiyun #define WM8995_IM_GP13_EINT_MASK 0x1000 /* IM_GP13_EINT */ 4031*4882a593Smuzhiyun #define WM8995_IM_GP13_EINT_SHIFT 12 /* IM_GP13_EINT */ 4032*4882a593Smuzhiyun #define WM8995_IM_GP13_EINT_WIDTH 1 /* IM_GP13_EINT */ 4033*4882a593Smuzhiyun #define WM8995_IM_GP12_EINT 0x0800 /* IM_GP12_EINT */ 4034*4882a593Smuzhiyun #define WM8995_IM_GP12_EINT_MASK 0x0800 /* IM_GP12_EINT */ 4035*4882a593Smuzhiyun #define WM8995_IM_GP12_EINT_SHIFT 11 /* IM_GP12_EINT */ 4036*4882a593Smuzhiyun #define WM8995_IM_GP12_EINT_WIDTH 1 /* IM_GP12_EINT */ 4037*4882a593Smuzhiyun #define WM8995_IM_GP11_EINT 0x0400 /* IM_GP11_EINT */ 4038*4882a593Smuzhiyun #define WM8995_IM_GP11_EINT_MASK 0x0400 /* IM_GP11_EINT */ 4039*4882a593Smuzhiyun #define WM8995_IM_GP11_EINT_SHIFT 10 /* IM_GP11_EINT */ 4040*4882a593Smuzhiyun #define WM8995_IM_GP11_EINT_WIDTH 1 /* IM_GP11_EINT */ 4041*4882a593Smuzhiyun #define WM8995_IM_GP10_EINT 0x0200 /* IM_GP10_EINT */ 4042*4882a593Smuzhiyun #define WM8995_IM_GP10_EINT_MASK 0x0200 /* IM_GP10_EINT */ 4043*4882a593Smuzhiyun #define WM8995_IM_GP10_EINT_SHIFT 9 /* IM_GP10_EINT */ 4044*4882a593Smuzhiyun #define WM8995_IM_GP10_EINT_WIDTH 1 /* IM_GP10_EINT */ 4045*4882a593Smuzhiyun #define WM8995_IM_GP9_EINT 0x0100 /* IM_GP9_EINT */ 4046*4882a593Smuzhiyun #define WM8995_IM_GP9_EINT_MASK 0x0100 /* IM_GP9_EINT */ 4047*4882a593Smuzhiyun #define WM8995_IM_GP9_EINT_SHIFT 8 /* IM_GP9_EINT */ 4048*4882a593Smuzhiyun #define WM8995_IM_GP9_EINT_WIDTH 1 /* IM_GP9_EINT */ 4049*4882a593Smuzhiyun #define WM8995_IM_GP8_EINT 0x0080 /* IM_GP8_EINT */ 4050*4882a593Smuzhiyun #define WM8995_IM_GP8_EINT_MASK 0x0080 /* IM_GP8_EINT */ 4051*4882a593Smuzhiyun #define WM8995_IM_GP8_EINT_SHIFT 7 /* IM_GP8_EINT */ 4052*4882a593Smuzhiyun #define WM8995_IM_GP8_EINT_WIDTH 1 /* IM_GP8_EINT */ 4053*4882a593Smuzhiyun #define WM8995_IM_GP7_EINT 0x0040 /* IM_GP7_EINT */ 4054*4882a593Smuzhiyun #define WM8995_IM_GP7_EINT_MASK 0x0040 /* IM_GP7_EINT */ 4055*4882a593Smuzhiyun #define WM8995_IM_GP7_EINT_SHIFT 6 /* IM_GP7_EINT */ 4056*4882a593Smuzhiyun #define WM8995_IM_GP7_EINT_WIDTH 1 /* IM_GP7_EINT */ 4057*4882a593Smuzhiyun #define WM8995_IM_GP6_EINT 0x0020 /* IM_GP6_EINT */ 4058*4882a593Smuzhiyun #define WM8995_IM_GP6_EINT_MASK 0x0020 /* IM_GP6_EINT */ 4059*4882a593Smuzhiyun #define WM8995_IM_GP6_EINT_SHIFT 5 /* IM_GP6_EINT */ 4060*4882a593Smuzhiyun #define WM8995_IM_GP6_EINT_WIDTH 1 /* IM_GP6_EINT */ 4061*4882a593Smuzhiyun #define WM8995_IM_GP5_EINT 0x0010 /* IM_GP5_EINT */ 4062*4882a593Smuzhiyun #define WM8995_IM_GP5_EINT_MASK 0x0010 /* IM_GP5_EINT */ 4063*4882a593Smuzhiyun #define WM8995_IM_GP5_EINT_SHIFT 4 /* IM_GP5_EINT */ 4064*4882a593Smuzhiyun #define WM8995_IM_GP5_EINT_WIDTH 1 /* IM_GP5_EINT */ 4065*4882a593Smuzhiyun #define WM8995_IM_GP4_EINT 0x0008 /* IM_GP4_EINT */ 4066*4882a593Smuzhiyun #define WM8995_IM_GP4_EINT_MASK 0x0008 /* IM_GP4_EINT */ 4067*4882a593Smuzhiyun #define WM8995_IM_GP4_EINT_SHIFT 3 /* IM_GP4_EINT */ 4068*4882a593Smuzhiyun #define WM8995_IM_GP4_EINT_WIDTH 1 /* IM_GP4_EINT */ 4069*4882a593Smuzhiyun #define WM8995_IM_GP3_EINT 0x0004 /* IM_GP3_EINT */ 4070*4882a593Smuzhiyun #define WM8995_IM_GP3_EINT_MASK 0x0004 /* IM_GP3_EINT */ 4071*4882a593Smuzhiyun #define WM8995_IM_GP3_EINT_SHIFT 2 /* IM_GP3_EINT */ 4072*4882a593Smuzhiyun #define WM8995_IM_GP3_EINT_WIDTH 1 /* IM_GP3_EINT */ 4073*4882a593Smuzhiyun #define WM8995_IM_GP2_EINT 0x0002 /* IM_GP2_EINT */ 4074*4882a593Smuzhiyun #define WM8995_IM_GP2_EINT_MASK 0x0002 /* IM_GP2_EINT */ 4075*4882a593Smuzhiyun #define WM8995_IM_GP2_EINT_SHIFT 1 /* IM_GP2_EINT */ 4076*4882a593Smuzhiyun #define WM8995_IM_GP2_EINT_WIDTH 1 /* IM_GP2_EINT */ 4077*4882a593Smuzhiyun #define WM8995_IM_GP1_EINT 0x0001 /* IM_GP1_EINT */ 4078*4882a593Smuzhiyun #define WM8995_IM_GP1_EINT_MASK 0x0001 /* IM_GP1_EINT */ 4079*4882a593Smuzhiyun #define WM8995_IM_GP1_EINT_SHIFT 0 /* IM_GP1_EINT */ 4080*4882a593Smuzhiyun #define WM8995_IM_GP1_EINT_WIDTH 1 /* IM_GP1_EINT */ 4081*4882a593Smuzhiyun 4082*4882a593Smuzhiyun /* 4083*4882a593Smuzhiyun * R1849 (0x739) - Interrupt Status 2 Mask 4084*4882a593Smuzhiyun */ 4085*4882a593Smuzhiyun #define WM8995_IM_DCS_DONE_23_EINT 0x1000 /* IM_DCS_DONE_23_EINT */ 4086*4882a593Smuzhiyun #define WM8995_IM_DCS_DONE_23_EINT_MASK 0x1000 /* IM_DCS_DONE_23_EINT */ 4087*4882a593Smuzhiyun #define WM8995_IM_DCS_DONE_23_EINT_SHIFT 12 /* IM_DCS_DONE_23_EINT */ 4088*4882a593Smuzhiyun #define WM8995_IM_DCS_DONE_23_EINT_WIDTH 1 /* IM_DCS_DONE_23_EINT */ 4089*4882a593Smuzhiyun #define WM8995_IM_DCS_DONE_01_EINT 0x0800 /* IM_DCS_DONE_01_EINT */ 4090*4882a593Smuzhiyun #define WM8995_IM_DCS_DONE_01_EINT_MASK 0x0800 /* IM_DCS_DONE_01_EINT */ 4091*4882a593Smuzhiyun #define WM8995_IM_DCS_DONE_01_EINT_SHIFT 11 /* IM_DCS_DONE_01_EINT */ 4092*4882a593Smuzhiyun #define WM8995_IM_DCS_DONE_01_EINT_WIDTH 1 /* IM_DCS_DONE_01_EINT */ 4093*4882a593Smuzhiyun #define WM8995_IM_WSEQ_DONE_EINT 0x0400 /* IM_WSEQ_DONE_EINT */ 4094*4882a593Smuzhiyun #define WM8995_IM_WSEQ_DONE_EINT_MASK 0x0400 /* IM_WSEQ_DONE_EINT */ 4095*4882a593Smuzhiyun #define WM8995_IM_WSEQ_DONE_EINT_SHIFT 10 /* IM_WSEQ_DONE_EINT */ 4096*4882a593Smuzhiyun #define WM8995_IM_WSEQ_DONE_EINT_WIDTH 1 /* IM_WSEQ_DONE_EINT */ 4097*4882a593Smuzhiyun #define WM8995_IM_FIFOS_ERR_EINT 0x0200 /* IM_FIFOS_ERR_EINT */ 4098*4882a593Smuzhiyun #define WM8995_IM_FIFOS_ERR_EINT_MASK 0x0200 /* IM_FIFOS_ERR_EINT */ 4099*4882a593Smuzhiyun #define WM8995_IM_FIFOS_ERR_EINT_SHIFT 9 /* IM_FIFOS_ERR_EINT */ 4100*4882a593Smuzhiyun #define WM8995_IM_FIFOS_ERR_EINT_WIDTH 1 /* IM_FIFOS_ERR_EINT */ 4101*4882a593Smuzhiyun #define WM8995_IM_AIF2DRC_SIG_DET_EINT 0x0100 /* IM_AIF2DRC_SIG_DET_EINT */ 4102*4882a593Smuzhiyun #define WM8995_IM_AIF2DRC_SIG_DET_EINT_MASK 0x0100 /* IM_AIF2DRC_SIG_DET_EINT */ 4103*4882a593Smuzhiyun #define WM8995_IM_AIF2DRC_SIG_DET_EINT_SHIFT 8 /* IM_AIF2DRC_SIG_DET_EINT */ 4104*4882a593Smuzhiyun #define WM8995_IM_AIF2DRC_SIG_DET_EINT_WIDTH 1 /* IM_AIF2DRC_SIG_DET_EINT */ 4105*4882a593Smuzhiyun #define WM8995_IM_AIF1DRC2_SIG_DET_EINT 0x0080 /* IM_AIF1DRC2_SIG_DET_EINT */ 4106*4882a593Smuzhiyun #define WM8995_IM_AIF1DRC2_SIG_DET_EINT_MASK 0x0080 /* IM_AIF1DRC2_SIG_DET_EINT */ 4107*4882a593Smuzhiyun #define WM8995_IM_AIF1DRC2_SIG_DET_EINT_SHIFT 7 /* IM_AIF1DRC2_SIG_DET_EINT */ 4108*4882a593Smuzhiyun #define WM8995_IM_AIF1DRC2_SIG_DET_EINT_WIDTH 1 /* IM_AIF1DRC2_SIG_DET_EINT */ 4109*4882a593Smuzhiyun #define WM8995_IM_AIF1DRC1_SIG_DET_EINT 0x0040 /* IM_AIF1DRC1_SIG_DET_EINT */ 4110*4882a593Smuzhiyun #define WM8995_IM_AIF1DRC1_SIG_DET_EINT_MASK 0x0040 /* IM_AIF1DRC1_SIG_DET_EINT */ 4111*4882a593Smuzhiyun #define WM8995_IM_AIF1DRC1_SIG_DET_EINT_SHIFT 6 /* IM_AIF1DRC1_SIG_DET_EINT */ 4112*4882a593Smuzhiyun #define WM8995_IM_AIF1DRC1_SIG_DET_EINT_WIDTH 1 /* IM_AIF1DRC1_SIG_DET_EINT */ 4113*4882a593Smuzhiyun #define WM8995_IM_SRC2_LOCK_EINT 0x0020 /* IM_SRC2_LOCK_EINT */ 4114*4882a593Smuzhiyun #define WM8995_IM_SRC2_LOCK_EINT_MASK 0x0020 /* IM_SRC2_LOCK_EINT */ 4115*4882a593Smuzhiyun #define WM8995_IM_SRC2_LOCK_EINT_SHIFT 5 /* IM_SRC2_LOCK_EINT */ 4116*4882a593Smuzhiyun #define WM8995_IM_SRC2_LOCK_EINT_WIDTH 1 /* IM_SRC2_LOCK_EINT */ 4117*4882a593Smuzhiyun #define WM8995_IM_SRC1_LOCK_EINT 0x0010 /* IM_SRC1_LOCK_EINT */ 4118*4882a593Smuzhiyun #define WM8995_IM_SRC1_LOCK_EINT_MASK 0x0010 /* IM_SRC1_LOCK_EINT */ 4119*4882a593Smuzhiyun #define WM8995_IM_SRC1_LOCK_EINT_SHIFT 4 /* IM_SRC1_LOCK_EINT */ 4120*4882a593Smuzhiyun #define WM8995_IM_SRC1_LOCK_EINT_WIDTH 1 /* IM_SRC1_LOCK_EINT */ 4121*4882a593Smuzhiyun #define WM8995_IM_FLL2_LOCK_EINT 0x0008 /* IM_FLL2_LOCK_EINT */ 4122*4882a593Smuzhiyun #define WM8995_IM_FLL2_LOCK_EINT_MASK 0x0008 /* IM_FLL2_LOCK_EINT */ 4123*4882a593Smuzhiyun #define WM8995_IM_FLL2_LOCK_EINT_SHIFT 3 /* IM_FLL2_LOCK_EINT */ 4124*4882a593Smuzhiyun #define WM8995_IM_FLL2_LOCK_EINT_WIDTH 1 /* IM_FLL2_LOCK_EINT */ 4125*4882a593Smuzhiyun #define WM8995_IM_FLL1_LOCK_EINT 0x0004 /* IM_FLL1_LOCK_EINT */ 4126*4882a593Smuzhiyun #define WM8995_IM_FLL1_LOCK_EINT_MASK 0x0004 /* IM_FLL1_LOCK_EINT */ 4127*4882a593Smuzhiyun #define WM8995_IM_FLL1_LOCK_EINT_SHIFT 2 /* IM_FLL1_LOCK_EINT */ 4128*4882a593Smuzhiyun #define WM8995_IM_FLL1_LOCK_EINT_WIDTH 1 /* IM_FLL1_LOCK_EINT */ 4129*4882a593Smuzhiyun #define WM8995_IM_HP_DONE_EINT 0x0002 /* IM_HP_DONE_EINT */ 4130*4882a593Smuzhiyun #define WM8995_IM_HP_DONE_EINT_MASK 0x0002 /* IM_HP_DONE_EINT */ 4131*4882a593Smuzhiyun #define WM8995_IM_HP_DONE_EINT_SHIFT 1 /* IM_HP_DONE_EINT */ 4132*4882a593Smuzhiyun #define WM8995_IM_HP_DONE_EINT_WIDTH 1 /* IM_HP_DONE_EINT */ 4133*4882a593Smuzhiyun #define WM8995_IM_MICD_EINT 0x0001 /* IM_MICD_EINT */ 4134*4882a593Smuzhiyun #define WM8995_IM_MICD_EINT_MASK 0x0001 /* IM_MICD_EINT */ 4135*4882a593Smuzhiyun #define WM8995_IM_MICD_EINT_SHIFT 0 /* IM_MICD_EINT */ 4136*4882a593Smuzhiyun #define WM8995_IM_MICD_EINT_WIDTH 1 /* IM_MICD_EINT */ 4137*4882a593Smuzhiyun 4138*4882a593Smuzhiyun /* 4139*4882a593Smuzhiyun * R1856 (0x740) - Interrupt Control 4140*4882a593Smuzhiyun */ 4141*4882a593Smuzhiyun #define WM8995_IM_IRQ 0x0001 /* IM_IRQ */ 4142*4882a593Smuzhiyun #define WM8995_IM_IRQ_MASK 0x0001 /* IM_IRQ */ 4143*4882a593Smuzhiyun #define WM8995_IM_IRQ_SHIFT 0 /* IM_IRQ */ 4144*4882a593Smuzhiyun #define WM8995_IM_IRQ_WIDTH 1 /* IM_IRQ */ 4145*4882a593Smuzhiyun 4146*4882a593Smuzhiyun /* 4147*4882a593Smuzhiyun * R2048 (0x800) - Left PDM Speaker 1 4148*4882a593Smuzhiyun */ 4149*4882a593Smuzhiyun #define WM8995_SPK1L_ENA 0x0010 /* SPK1L_ENA */ 4150*4882a593Smuzhiyun #define WM8995_SPK1L_ENA_MASK 0x0010 /* SPK1L_ENA */ 4151*4882a593Smuzhiyun #define WM8995_SPK1L_ENA_SHIFT 4 /* SPK1L_ENA */ 4152*4882a593Smuzhiyun #define WM8995_SPK1L_ENA_WIDTH 1 /* SPK1L_ENA */ 4153*4882a593Smuzhiyun #define WM8995_SPK1L_MUTE 0x0008 /* SPK1L_MUTE */ 4154*4882a593Smuzhiyun #define WM8995_SPK1L_MUTE_MASK 0x0008 /* SPK1L_MUTE */ 4155*4882a593Smuzhiyun #define WM8995_SPK1L_MUTE_SHIFT 3 /* SPK1L_MUTE */ 4156*4882a593Smuzhiyun #define WM8995_SPK1L_MUTE_WIDTH 1 /* SPK1L_MUTE */ 4157*4882a593Smuzhiyun #define WM8995_SPK1L_MUTE_ZC 0x0004 /* SPK1L_MUTE_ZC */ 4158*4882a593Smuzhiyun #define WM8995_SPK1L_MUTE_ZC_MASK 0x0004 /* SPK1L_MUTE_ZC */ 4159*4882a593Smuzhiyun #define WM8995_SPK1L_MUTE_ZC_SHIFT 2 /* SPK1L_MUTE_ZC */ 4160*4882a593Smuzhiyun #define WM8995_SPK1L_MUTE_ZC_WIDTH 1 /* SPK1L_MUTE_ZC */ 4161*4882a593Smuzhiyun #define WM8995_SPK1L_SRC_MASK 0x0003 /* SPK1L_SRC - [1:0] */ 4162*4882a593Smuzhiyun #define WM8995_SPK1L_SRC_SHIFT 0 /* SPK1L_SRC - [1:0] */ 4163*4882a593Smuzhiyun #define WM8995_SPK1L_SRC_WIDTH 2 /* SPK1L_SRC - [1:0] */ 4164*4882a593Smuzhiyun 4165*4882a593Smuzhiyun /* 4166*4882a593Smuzhiyun * R2049 (0x801) - Right PDM Speaker 1 4167*4882a593Smuzhiyun */ 4168*4882a593Smuzhiyun #define WM8995_SPK1R_ENA 0x0010 /* SPK1R_ENA */ 4169*4882a593Smuzhiyun #define WM8995_SPK1R_ENA_MASK 0x0010 /* SPK1R_ENA */ 4170*4882a593Smuzhiyun #define WM8995_SPK1R_ENA_SHIFT 4 /* SPK1R_ENA */ 4171*4882a593Smuzhiyun #define WM8995_SPK1R_ENA_WIDTH 1 /* SPK1R_ENA */ 4172*4882a593Smuzhiyun #define WM8995_SPK1R_MUTE 0x0008 /* SPK1R_MUTE */ 4173*4882a593Smuzhiyun #define WM8995_SPK1R_MUTE_MASK 0x0008 /* SPK1R_MUTE */ 4174*4882a593Smuzhiyun #define WM8995_SPK1R_MUTE_SHIFT 3 /* SPK1R_MUTE */ 4175*4882a593Smuzhiyun #define WM8995_SPK1R_MUTE_WIDTH 1 /* SPK1R_MUTE */ 4176*4882a593Smuzhiyun #define WM8995_SPK1R_MUTE_ZC 0x0004 /* SPK1R_MUTE_ZC */ 4177*4882a593Smuzhiyun #define WM8995_SPK1R_MUTE_ZC_MASK 0x0004 /* SPK1R_MUTE_ZC */ 4178*4882a593Smuzhiyun #define WM8995_SPK1R_MUTE_ZC_SHIFT 2 /* SPK1R_MUTE_ZC */ 4179*4882a593Smuzhiyun #define WM8995_SPK1R_MUTE_ZC_WIDTH 1 /* SPK1R_MUTE_ZC */ 4180*4882a593Smuzhiyun #define WM8995_SPK1R_SRC_MASK 0x0003 /* SPK1R_SRC - [1:0] */ 4181*4882a593Smuzhiyun #define WM8995_SPK1R_SRC_SHIFT 0 /* SPK1R_SRC - [1:0] */ 4182*4882a593Smuzhiyun #define WM8995_SPK1R_SRC_WIDTH 2 /* SPK1R_SRC - [1:0] */ 4183*4882a593Smuzhiyun 4184*4882a593Smuzhiyun /* 4185*4882a593Smuzhiyun * R2050 (0x802) - PDM Speaker 1 Mute Sequence 4186*4882a593Smuzhiyun */ 4187*4882a593Smuzhiyun #define WM8995_SPK1_MUTE_SEQ1_MASK 0x00FF /* SPK1_MUTE_SEQ1 - [7:0] */ 4188*4882a593Smuzhiyun #define WM8995_SPK1_MUTE_SEQ1_SHIFT 0 /* SPK1_MUTE_SEQ1 - [7:0] */ 4189*4882a593Smuzhiyun #define WM8995_SPK1_MUTE_SEQ1_WIDTH 8 /* SPK1_MUTE_SEQ1 - [7:0] */ 4190*4882a593Smuzhiyun 4191*4882a593Smuzhiyun /* 4192*4882a593Smuzhiyun * R2056 (0x808) - Left PDM Speaker 2 4193*4882a593Smuzhiyun */ 4194*4882a593Smuzhiyun #define WM8995_SPK2L_ENA 0x0010 /* SPK2L_ENA */ 4195*4882a593Smuzhiyun #define WM8995_SPK2L_ENA_MASK 0x0010 /* SPK2L_ENA */ 4196*4882a593Smuzhiyun #define WM8995_SPK2L_ENA_SHIFT 4 /* SPK2L_ENA */ 4197*4882a593Smuzhiyun #define WM8995_SPK2L_ENA_WIDTH 1 /* SPK2L_ENA */ 4198*4882a593Smuzhiyun #define WM8995_SPK2L_MUTE 0x0008 /* SPK2L_MUTE */ 4199*4882a593Smuzhiyun #define WM8995_SPK2L_MUTE_MASK 0x0008 /* SPK2L_MUTE */ 4200*4882a593Smuzhiyun #define WM8995_SPK2L_MUTE_SHIFT 3 /* SPK2L_MUTE */ 4201*4882a593Smuzhiyun #define WM8995_SPK2L_MUTE_WIDTH 1 /* SPK2L_MUTE */ 4202*4882a593Smuzhiyun #define WM8995_SPK2L_MUTE_ZC 0x0004 /* SPK2L_MUTE_ZC */ 4203*4882a593Smuzhiyun #define WM8995_SPK2L_MUTE_ZC_MASK 0x0004 /* SPK2L_MUTE_ZC */ 4204*4882a593Smuzhiyun #define WM8995_SPK2L_MUTE_ZC_SHIFT 2 /* SPK2L_MUTE_ZC */ 4205*4882a593Smuzhiyun #define WM8995_SPK2L_MUTE_ZC_WIDTH 1 /* SPK2L_MUTE_ZC */ 4206*4882a593Smuzhiyun #define WM8995_SPK2L_SRC_MASK 0x0003 /* SPK2L_SRC - [1:0] */ 4207*4882a593Smuzhiyun #define WM8995_SPK2L_SRC_SHIFT 0 /* SPK2L_SRC - [1:0] */ 4208*4882a593Smuzhiyun #define WM8995_SPK2L_SRC_WIDTH 2 /* SPK2L_SRC - [1:0] */ 4209*4882a593Smuzhiyun 4210*4882a593Smuzhiyun /* 4211*4882a593Smuzhiyun * R2057 (0x809) - Right PDM Speaker 2 4212*4882a593Smuzhiyun */ 4213*4882a593Smuzhiyun #define WM8995_SPK2R_ENA 0x0010 /* SPK2R_ENA */ 4214*4882a593Smuzhiyun #define WM8995_SPK2R_ENA_MASK 0x0010 /* SPK2R_ENA */ 4215*4882a593Smuzhiyun #define WM8995_SPK2R_ENA_SHIFT 4 /* SPK2R_ENA */ 4216*4882a593Smuzhiyun #define WM8995_SPK2R_ENA_WIDTH 1 /* SPK2R_ENA */ 4217*4882a593Smuzhiyun #define WM8995_SPK2R_MUTE 0x0008 /* SPK2R_MUTE */ 4218*4882a593Smuzhiyun #define WM8995_SPK2R_MUTE_MASK 0x0008 /* SPK2R_MUTE */ 4219*4882a593Smuzhiyun #define WM8995_SPK2R_MUTE_SHIFT 3 /* SPK2R_MUTE */ 4220*4882a593Smuzhiyun #define WM8995_SPK2R_MUTE_WIDTH 1 /* SPK2R_MUTE */ 4221*4882a593Smuzhiyun #define WM8995_SPK2R_MUTE_ZC 0x0004 /* SPK2R_MUTE_ZC */ 4222*4882a593Smuzhiyun #define WM8995_SPK2R_MUTE_ZC_MASK 0x0004 /* SPK2R_MUTE_ZC */ 4223*4882a593Smuzhiyun #define WM8995_SPK2R_MUTE_ZC_SHIFT 2 /* SPK2R_MUTE_ZC */ 4224*4882a593Smuzhiyun #define WM8995_SPK2R_MUTE_ZC_WIDTH 1 /* SPK2R_MUTE_ZC */ 4225*4882a593Smuzhiyun #define WM8995_SPK2R_SRC_MASK 0x0003 /* SPK2R_SRC - [1:0] */ 4226*4882a593Smuzhiyun #define WM8995_SPK2R_SRC_SHIFT 0 /* SPK2R_SRC - [1:0] */ 4227*4882a593Smuzhiyun #define WM8995_SPK2R_SRC_WIDTH 2 /* SPK2R_SRC - [1:0] */ 4228*4882a593Smuzhiyun 4229*4882a593Smuzhiyun /* 4230*4882a593Smuzhiyun * R2058 (0x80A) - PDM Speaker 2 Mute Sequence 4231*4882a593Smuzhiyun */ 4232*4882a593Smuzhiyun #define WM8995_SPK2_MUTE_SEQ1_MASK 0x00FF /* SPK2_MUTE_SEQ1 - [7:0] */ 4233*4882a593Smuzhiyun #define WM8995_SPK2_MUTE_SEQ1_SHIFT 0 /* SPK2_MUTE_SEQ1 - [7:0] */ 4234*4882a593Smuzhiyun #define WM8995_SPK2_MUTE_SEQ1_WIDTH 8 /* SPK2_MUTE_SEQ1 - [7:0] */ 4235*4882a593Smuzhiyun 4236*4882a593Smuzhiyun #define WM8995_CLASS_W_SWITCH(xname, reg, shift, max, invert) \ 4237*4882a593Smuzhiyun SOC_SINGLE_EXT(xname, reg, shift, max, invert, \ 4238*4882a593Smuzhiyun snd_soc_dapm_get_volsw, wm8995_put_class_w) 4239*4882a593Smuzhiyun 4240*4882a593Smuzhiyun struct wm8995_reg_access { 4241*4882a593Smuzhiyun u16 read; 4242*4882a593Smuzhiyun u16 write; 4243*4882a593Smuzhiyun u16 vol; 4244*4882a593Smuzhiyun }; 4245*4882a593Smuzhiyun 4246*4882a593Smuzhiyun /* Sources for AIF1/2 SYSCLK - use with set_dai_sysclk() */ 4247*4882a593Smuzhiyun enum clk_src { 4248*4882a593Smuzhiyun WM8995_SYSCLK_MCLK1 = 1, 4249*4882a593Smuzhiyun WM8995_SYSCLK_MCLK2, 4250*4882a593Smuzhiyun WM8995_SYSCLK_FLL1, 4251*4882a593Smuzhiyun WM8995_SYSCLK_FLL2, 4252*4882a593Smuzhiyun WM8995_SYSCLK_OPCLK 4253*4882a593Smuzhiyun }; 4254*4882a593Smuzhiyun 4255*4882a593Smuzhiyun #define WM8995_FLL1 1 4256*4882a593Smuzhiyun #define WM8995_FLL2 2 4257*4882a593Smuzhiyun 4258*4882a593Smuzhiyun #define WM8995_FLL_SRC_MCLK1 1 4259*4882a593Smuzhiyun #define WM8995_FLL_SRC_MCLK2 2 4260*4882a593Smuzhiyun #define WM8995_FLL_SRC_LRCLK 3 4261*4882a593Smuzhiyun #define WM8995_FLL_SRC_BCLK 4 4262*4882a593Smuzhiyun 4263*4882a593Smuzhiyun #endif /* _WM8995_H */ 4264