1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * wm8990.h -- audio driver for WM8990 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright 2007 Wolfson Microelectronics PLC. 6*4882a593Smuzhiyun * Author: Graeme Gregory 7*4882a593Smuzhiyun * graeme.gregory@wolfsonmicro.com or linux@wolfsonmicro.com 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __WM8990REGISTERDEFS_H__ 11*4882a593Smuzhiyun #define __WM8990REGISTERDEFS_H__ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* 14*4882a593Smuzhiyun * Register values. 15*4882a593Smuzhiyun */ 16*4882a593Smuzhiyun #define WM8990_RESET 0x00 17*4882a593Smuzhiyun #define WM8990_POWER_MANAGEMENT_1 0x01 18*4882a593Smuzhiyun #define WM8990_POWER_MANAGEMENT_2 0x02 19*4882a593Smuzhiyun #define WM8990_POWER_MANAGEMENT_3 0x03 20*4882a593Smuzhiyun #define WM8990_AUDIO_INTERFACE_1 0x04 21*4882a593Smuzhiyun #define WM8990_AUDIO_INTERFACE_2 0x05 22*4882a593Smuzhiyun #define WM8990_CLOCKING_1 0x06 23*4882a593Smuzhiyun #define WM8990_CLOCKING_2 0x07 24*4882a593Smuzhiyun #define WM8990_AUDIO_INTERFACE_3 0x08 25*4882a593Smuzhiyun #define WM8990_AUDIO_INTERFACE_4 0x09 26*4882a593Smuzhiyun #define WM8990_DAC_CTRL 0x0A 27*4882a593Smuzhiyun #define WM8990_LEFT_DAC_DIGITAL_VOLUME 0x0B 28*4882a593Smuzhiyun #define WM8990_RIGHT_DAC_DIGITAL_VOLUME 0x0C 29*4882a593Smuzhiyun #define WM8990_DIGITAL_SIDE_TONE 0x0D 30*4882a593Smuzhiyun #define WM8990_ADC_CTRL 0x0E 31*4882a593Smuzhiyun #define WM8990_LEFT_ADC_DIGITAL_VOLUME 0x0F 32*4882a593Smuzhiyun #define WM8990_RIGHT_ADC_DIGITAL_VOLUME 0x10 33*4882a593Smuzhiyun #define WM8990_GPIO_CTRL_1 0x12 34*4882a593Smuzhiyun #define WM8990_GPIO1_GPIO2 0x13 35*4882a593Smuzhiyun #define WM8990_GPIO3_GPIO4 0x14 36*4882a593Smuzhiyun #define WM8990_GPIO5_GPIO6 0x15 37*4882a593Smuzhiyun #define WM8990_GPIOCTRL_2 0x16 38*4882a593Smuzhiyun #define WM8990_GPIO_POL 0x17 39*4882a593Smuzhiyun #define WM8990_LEFT_LINE_INPUT_1_2_VOLUME 0x18 40*4882a593Smuzhiyun #define WM8990_LEFT_LINE_INPUT_3_4_VOLUME 0x19 41*4882a593Smuzhiyun #define WM8990_RIGHT_LINE_INPUT_1_2_VOLUME 0x1A 42*4882a593Smuzhiyun #define WM8990_RIGHT_LINE_INPUT_3_4_VOLUME 0x1B 43*4882a593Smuzhiyun #define WM8990_LEFT_OUTPUT_VOLUME 0x1C 44*4882a593Smuzhiyun #define WM8990_RIGHT_OUTPUT_VOLUME 0x1D 45*4882a593Smuzhiyun #define WM8990_LINE_OUTPUTS_VOLUME 0x1E 46*4882a593Smuzhiyun #define WM8990_OUT3_4_VOLUME 0x1F 47*4882a593Smuzhiyun #define WM8990_LEFT_OPGA_VOLUME 0x20 48*4882a593Smuzhiyun #define WM8990_RIGHT_OPGA_VOLUME 0x21 49*4882a593Smuzhiyun #define WM8990_SPEAKER_VOLUME 0x22 50*4882a593Smuzhiyun #define WM8990_CLASSD1 0x23 51*4882a593Smuzhiyun #define WM8990_CLASSD3 0x25 52*4882a593Smuzhiyun #define WM8990_CLASSD4 0x26 53*4882a593Smuzhiyun #define WM8990_INPUT_MIXER1 0x27 54*4882a593Smuzhiyun #define WM8990_INPUT_MIXER2 0x28 55*4882a593Smuzhiyun #define WM8990_INPUT_MIXER3 0x29 56*4882a593Smuzhiyun #define WM8990_INPUT_MIXER4 0x2A 57*4882a593Smuzhiyun #define WM8990_INPUT_MIXER5 0x2B 58*4882a593Smuzhiyun #define WM8990_INPUT_MIXER6 0x2C 59*4882a593Smuzhiyun #define WM8990_OUTPUT_MIXER1 0x2D 60*4882a593Smuzhiyun #define WM8990_OUTPUT_MIXER2 0x2E 61*4882a593Smuzhiyun #define WM8990_OUTPUT_MIXER3 0x2F 62*4882a593Smuzhiyun #define WM8990_OUTPUT_MIXER4 0x30 63*4882a593Smuzhiyun #define WM8990_OUTPUT_MIXER5 0x31 64*4882a593Smuzhiyun #define WM8990_OUTPUT_MIXER6 0x32 65*4882a593Smuzhiyun #define WM8990_OUT3_4_MIXER 0x33 66*4882a593Smuzhiyun #define WM8990_LINE_MIXER1 0x34 67*4882a593Smuzhiyun #define WM8990_LINE_MIXER2 0x35 68*4882a593Smuzhiyun #define WM8990_SPEAKER_MIXER 0x36 69*4882a593Smuzhiyun #define WM8990_ADDITIONAL_CONTROL 0x37 70*4882a593Smuzhiyun #define WM8990_ANTIPOP1 0x38 71*4882a593Smuzhiyun #define WM8990_ANTIPOP2 0x39 72*4882a593Smuzhiyun #define WM8990_MICBIAS 0x3A 73*4882a593Smuzhiyun #define WM8990_PLL1 0x3C 74*4882a593Smuzhiyun #define WM8990_PLL2 0x3D 75*4882a593Smuzhiyun #define WM8990_PLL3 0x3E 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun #define WM8990_EXT_ACCESS_ENA 0x75 78*4882a593Smuzhiyun #define WM8990_EXT_CTL1 0x7a 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun /* 81*4882a593Smuzhiyun * Field Definitions. 82*4882a593Smuzhiyun */ 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun /* 85*4882a593Smuzhiyun * R0 (0x00) - Reset 86*4882a593Smuzhiyun */ 87*4882a593Smuzhiyun #define WM8990_SW_RESET_CHIP_ID_MASK 0xFFFF /* SW_RESET_CHIP_ID */ 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun /* 90*4882a593Smuzhiyun * R1 (0x01) - Power Management (1) 91*4882a593Smuzhiyun */ 92*4882a593Smuzhiyun #define WM8990_SPK_ENA 0x1000 /* SPK_ENA */ 93*4882a593Smuzhiyun #define WM8990_SPK_ENA_BIT 12 94*4882a593Smuzhiyun #define WM8990_OUT3_ENA 0x0800 /* OUT3_ENA */ 95*4882a593Smuzhiyun #define WM8990_OUT3_ENA_BIT 11 96*4882a593Smuzhiyun #define WM8990_OUT4_ENA 0x0400 /* OUT4_ENA */ 97*4882a593Smuzhiyun #define WM8990_OUT4_ENA_BIT 10 98*4882a593Smuzhiyun #define WM8990_LOUT_ENA 0x0200 /* LOUT_ENA */ 99*4882a593Smuzhiyun #define WM8990_LOUT_ENA_BIT 9 100*4882a593Smuzhiyun #define WM8990_ROUT_ENA 0x0100 /* ROUT_ENA */ 101*4882a593Smuzhiyun #define WM8990_ROUT_ENA_BIT 8 102*4882a593Smuzhiyun #define WM8990_MICBIAS_ENA 0x0010 /* MICBIAS_ENA */ 103*4882a593Smuzhiyun #define WM8990_MICBIAS_ENA_BIT 4 104*4882a593Smuzhiyun #define WM8990_VMID_MODE_MASK 0x0006 /* VMID_MODE - [2:1] */ 105*4882a593Smuzhiyun #define WM8990_VREF_ENA 0x0001 /* VREF_ENA */ 106*4882a593Smuzhiyun #define WM8990_VREF_ENA_BIT 0 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun /* 109*4882a593Smuzhiyun * R2 (0x02) - Power Management (2) 110*4882a593Smuzhiyun */ 111*4882a593Smuzhiyun #define WM8990_PLL_ENA 0x8000 /* PLL_ENA */ 112*4882a593Smuzhiyun #define WM8990_PLL_ENA_BIT 15 113*4882a593Smuzhiyun #define WM8990_TSHUT_ENA 0x4000 /* TSHUT_ENA */ 114*4882a593Smuzhiyun #define WM8990_TSHUT_ENA_BIT 14 115*4882a593Smuzhiyun #define WM8990_TSHUT_OPDIS 0x2000 /* TSHUT_OPDIS */ 116*4882a593Smuzhiyun #define WM8990_TSHUT_OPDIS_BIT 13 117*4882a593Smuzhiyun #define WM8990_OPCLK_ENA 0x0800 /* OPCLK_ENA */ 118*4882a593Smuzhiyun #define WM8990_OPCLK_ENA_BIT 11 119*4882a593Smuzhiyun #define WM8990_AINL_ENA 0x0200 /* AINL_ENA */ 120*4882a593Smuzhiyun #define WM8990_AINL_ENA_BIT 9 121*4882a593Smuzhiyun #define WM8990_AINR_ENA 0x0100 /* AINR_ENA */ 122*4882a593Smuzhiyun #define WM8990_AINR_ENA_BIT 8 123*4882a593Smuzhiyun #define WM8990_LIN34_ENA 0x0080 /* LIN34_ENA */ 124*4882a593Smuzhiyun #define WM8990_LIN34_ENA_BIT 7 125*4882a593Smuzhiyun #define WM8990_LIN12_ENA 0x0040 /* LIN12_ENA */ 126*4882a593Smuzhiyun #define WM8990_LIN12_ENA_BIT 6 127*4882a593Smuzhiyun #define WM8990_RIN34_ENA 0x0020 /* RIN34_ENA */ 128*4882a593Smuzhiyun #define WM8990_RIN34_ENA_BIT 5 129*4882a593Smuzhiyun #define WM8990_RIN12_ENA 0x0010 /* RIN12_ENA */ 130*4882a593Smuzhiyun #define WM8990_RIN12_ENA_BIT 4 131*4882a593Smuzhiyun #define WM8990_ADCL_ENA 0x0002 /* ADCL_ENA */ 132*4882a593Smuzhiyun #define WM8990_ADCL_ENA_BIT 1 133*4882a593Smuzhiyun #define WM8990_ADCR_ENA 0x0001 /* ADCR_ENA */ 134*4882a593Smuzhiyun #define WM8990_ADCR_ENA_BIT 0 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun /* 137*4882a593Smuzhiyun * R3 (0x03) - Power Management (3) 138*4882a593Smuzhiyun */ 139*4882a593Smuzhiyun #define WM8990_LON_ENA 0x2000 /* LON_ENA */ 140*4882a593Smuzhiyun #define WM8990_LON_ENA_BIT 13 141*4882a593Smuzhiyun #define WM8990_LOP_ENA 0x1000 /* LOP_ENA */ 142*4882a593Smuzhiyun #define WM8990_LOP_ENA_BIT 12 143*4882a593Smuzhiyun #define WM8990_RON_ENA 0x0800 /* RON_ENA */ 144*4882a593Smuzhiyun #define WM8990_RON_ENA_BIT 11 145*4882a593Smuzhiyun #define WM8990_ROP_ENA 0x0400 /* ROP_ENA */ 146*4882a593Smuzhiyun #define WM8990_ROP_ENA_BIT 10 147*4882a593Smuzhiyun #define WM8990_LOPGA_ENA 0x0080 /* LOPGA_ENA */ 148*4882a593Smuzhiyun #define WM8990_LOPGA_ENA_BIT 7 149*4882a593Smuzhiyun #define WM8990_ROPGA_ENA 0x0040 /* ROPGA_ENA */ 150*4882a593Smuzhiyun #define WM8990_ROPGA_ENA_BIT 6 151*4882a593Smuzhiyun #define WM8990_LOMIX_ENA 0x0020 /* LOMIX_ENA */ 152*4882a593Smuzhiyun #define WM8990_LOMIX_ENA_BIT 5 153*4882a593Smuzhiyun #define WM8990_ROMIX_ENA 0x0010 /* ROMIX_ENA */ 154*4882a593Smuzhiyun #define WM8990_ROMIX_ENA_BIT 4 155*4882a593Smuzhiyun #define WM8990_DACL_ENA 0x0002 /* DACL_ENA */ 156*4882a593Smuzhiyun #define WM8990_DACL_ENA_BIT 1 157*4882a593Smuzhiyun #define WM8990_DACR_ENA 0x0001 /* DACR_ENA */ 158*4882a593Smuzhiyun #define WM8990_DACR_ENA_BIT 0 159*4882a593Smuzhiyun 160*4882a593Smuzhiyun /* 161*4882a593Smuzhiyun * R4 (0x04) - Audio Interface (1) 162*4882a593Smuzhiyun */ 163*4882a593Smuzhiyun #define WM8990_AIFADCL_SRC 0x8000 /* AIFADCL_SRC */ 164*4882a593Smuzhiyun #define WM8990_AIFADCR_SRC 0x4000 /* AIFADCR_SRC */ 165*4882a593Smuzhiyun #define WM8990_AIFADC_TDM 0x2000 /* AIFADC_TDM */ 166*4882a593Smuzhiyun #define WM8990_AIFADC_TDM_CHAN 0x1000 /* AIFADC_TDM_CHAN */ 167*4882a593Smuzhiyun #define WM8990_AIF_BCLK_INV 0x0100 /* AIF_BCLK_INV */ 168*4882a593Smuzhiyun #define WM8990_AIF_LRCLK_INV 0x0080 /* AIF_LRCLK_INV */ 169*4882a593Smuzhiyun #define WM8990_AIF_WL_MASK 0x0060 /* AIF_WL - [6:5] */ 170*4882a593Smuzhiyun #define WM8990_AIF_WL_16BITS (0 << 5) 171*4882a593Smuzhiyun #define WM8990_AIF_WL_20BITS (1 << 5) 172*4882a593Smuzhiyun #define WM8990_AIF_WL_24BITS (2 << 5) 173*4882a593Smuzhiyun #define WM8990_AIF_WL_32BITS (3 << 5) 174*4882a593Smuzhiyun #define WM8990_AIF_FMT_MASK 0x0018 /* AIF_FMT - [4:3] */ 175*4882a593Smuzhiyun #define WM8990_AIF_TMF_RIGHTJ (0 << 3) 176*4882a593Smuzhiyun #define WM8990_AIF_TMF_LEFTJ (1 << 3) 177*4882a593Smuzhiyun #define WM8990_AIF_TMF_I2S (2 << 3) 178*4882a593Smuzhiyun #define WM8990_AIF_TMF_DSP (3 << 3) 179*4882a593Smuzhiyun 180*4882a593Smuzhiyun /* 181*4882a593Smuzhiyun * R5 (0x05) - Audio Interface (2) 182*4882a593Smuzhiyun */ 183*4882a593Smuzhiyun #define WM8990_DACL_SRC 0x8000 /* DACL_SRC */ 184*4882a593Smuzhiyun #define WM8990_DACR_SRC 0x4000 /* DACR_SRC */ 185*4882a593Smuzhiyun #define WM8990_AIFDAC_TDM 0x2000 /* AIFDAC_TDM */ 186*4882a593Smuzhiyun #define WM8990_AIFDAC_TDM_CHAN 0x1000 /* AIFDAC_TDM_CHAN */ 187*4882a593Smuzhiyun #define WM8990_DAC_BOOST_MASK 0x0C00 /* DAC_BOOST */ 188*4882a593Smuzhiyun #define WM8990_DAC_COMP 0x0010 /* DAC_COMP */ 189*4882a593Smuzhiyun #define WM8990_DAC_COMPMODE 0x0008 /* DAC_COMPMODE */ 190*4882a593Smuzhiyun #define WM8990_ADC_COMP 0x0004 /* ADC_COMP */ 191*4882a593Smuzhiyun #define WM8990_ADC_COMPMODE 0x0002 /* ADC_COMPMODE */ 192*4882a593Smuzhiyun #define WM8990_LOOPBACK 0x0001 /* LOOPBACK */ 193*4882a593Smuzhiyun 194*4882a593Smuzhiyun /* 195*4882a593Smuzhiyun * R6 (0x06) - Clocking (1) 196*4882a593Smuzhiyun */ 197*4882a593Smuzhiyun #define WM8990_TOCLK_RATE 0x8000 /* TOCLK_RATE */ 198*4882a593Smuzhiyun #define WM8990_TOCLK_ENA 0x4000 /* TOCLK_ENA */ 199*4882a593Smuzhiyun #define WM8990_OPCLKDIV_MASK 0x1E00 /* OPCLKDIV - [12:9] */ 200*4882a593Smuzhiyun #define WM8990_DCLKDIV_MASK 0x01C0 /* DCLKDIV - [8:6] */ 201*4882a593Smuzhiyun #define WM8990_BCLK_DIV_MASK 0x001E /* BCLK_DIV - [4:1] */ 202*4882a593Smuzhiyun #define WM8990_BCLK_DIV_1 (0x0 << 1) 203*4882a593Smuzhiyun #define WM8990_BCLK_DIV_1_5 (0x1 << 1) 204*4882a593Smuzhiyun #define WM8990_BCLK_DIV_2 (0x2 << 1) 205*4882a593Smuzhiyun #define WM8990_BCLK_DIV_3 (0x3 << 1) 206*4882a593Smuzhiyun #define WM8990_BCLK_DIV_4 (0x4 << 1) 207*4882a593Smuzhiyun #define WM8990_BCLK_DIV_5_5 (0x5 << 1) 208*4882a593Smuzhiyun #define WM8990_BCLK_DIV_6 (0x6 << 1) 209*4882a593Smuzhiyun #define WM8990_BCLK_DIV_8 (0x7 << 1) 210*4882a593Smuzhiyun #define WM8990_BCLK_DIV_11 (0x8 << 1) 211*4882a593Smuzhiyun #define WM8990_BCLK_DIV_12 (0x9 << 1) 212*4882a593Smuzhiyun #define WM8990_BCLK_DIV_16 (0xA << 1) 213*4882a593Smuzhiyun #define WM8990_BCLK_DIV_22 (0xB << 1) 214*4882a593Smuzhiyun #define WM8990_BCLK_DIV_24 (0xC << 1) 215*4882a593Smuzhiyun #define WM8990_BCLK_DIV_32 (0xD << 1) 216*4882a593Smuzhiyun #define WM8990_BCLK_DIV_44 (0xE << 1) 217*4882a593Smuzhiyun #define WM8990_BCLK_DIV_48 (0xF << 1) 218*4882a593Smuzhiyun 219*4882a593Smuzhiyun /* 220*4882a593Smuzhiyun * R7 (0x07) - Clocking (2) 221*4882a593Smuzhiyun */ 222*4882a593Smuzhiyun #define WM8990_MCLK_SRC 0x8000 /* MCLK_SRC */ 223*4882a593Smuzhiyun #define WM8990_SYSCLK_SRC 0x4000 /* SYSCLK_SRC */ 224*4882a593Smuzhiyun #define WM8990_CLK_FORCE 0x2000 /* CLK_FORCE */ 225*4882a593Smuzhiyun #define WM8990_MCLK_DIV_MASK 0x1800 /* MCLK_DIV - [12:11] */ 226*4882a593Smuzhiyun #define WM8990_MCLK_DIV_1 (0 << 11) 227*4882a593Smuzhiyun #define WM8990_MCLK_DIV_2 (2 << 11) 228*4882a593Smuzhiyun #define WM8990_MCLK_INV 0x0400 /* MCLK_INV */ 229*4882a593Smuzhiyun #define WM8990_ADC_CLKDIV_MASK 0x00E0 /* ADC_CLKDIV */ 230*4882a593Smuzhiyun #define WM8990_ADC_CLKDIV_1 (0 << 5) 231*4882a593Smuzhiyun #define WM8990_ADC_CLKDIV_1_5 (1 << 5) 232*4882a593Smuzhiyun #define WM8990_ADC_CLKDIV_2 (2 << 5) 233*4882a593Smuzhiyun #define WM8990_ADC_CLKDIV_3 (3 << 5) 234*4882a593Smuzhiyun #define WM8990_ADC_CLKDIV_4 (4 << 5) 235*4882a593Smuzhiyun #define WM8990_ADC_CLKDIV_5_5 (5 << 5) 236*4882a593Smuzhiyun #define WM8990_ADC_CLKDIV_6 (6 << 5) 237*4882a593Smuzhiyun #define WM8990_DAC_CLKDIV_MASK 0x001C /* DAC_CLKDIV - [4:2] */ 238*4882a593Smuzhiyun #define WM8990_DAC_CLKDIV_1 (0 << 2) 239*4882a593Smuzhiyun #define WM8990_DAC_CLKDIV_1_5 (1 << 2) 240*4882a593Smuzhiyun #define WM8990_DAC_CLKDIV_2 (2 << 2) 241*4882a593Smuzhiyun #define WM8990_DAC_CLKDIV_3 (3 << 2) 242*4882a593Smuzhiyun #define WM8990_DAC_CLKDIV_4 (4 << 2) 243*4882a593Smuzhiyun #define WM8990_DAC_CLKDIV_5_5 (5 << 2) 244*4882a593Smuzhiyun #define WM8990_DAC_CLKDIV_6 (6 << 2) 245*4882a593Smuzhiyun 246*4882a593Smuzhiyun /* 247*4882a593Smuzhiyun * R8 (0x08) - Audio Interface (3) 248*4882a593Smuzhiyun */ 249*4882a593Smuzhiyun #define WM8990_AIF_MSTR1 0x8000 /* AIF_MSTR1 */ 250*4882a593Smuzhiyun #define WM8990_AIF_MSTR2 0x4000 /* AIF_MSTR2 */ 251*4882a593Smuzhiyun #define WM8990_AIF_SEL 0x2000 /* AIF_SEL */ 252*4882a593Smuzhiyun #define WM8990_ADCLRC_DIR 0x0800 /* ADCLRC_DIR */ 253*4882a593Smuzhiyun #define WM8990_ADCLRC_RATE_MASK 0x07FF /* ADCLRC_RATE */ 254*4882a593Smuzhiyun 255*4882a593Smuzhiyun /* 256*4882a593Smuzhiyun * R9 (0x09) - Audio Interface (4) 257*4882a593Smuzhiyun */ 258*4882a593Smuzhiyun #define WM8990_ALRCGPIO1 0x8000 /* ALRCGPIO1 */ 259*4882a593Smuzhiyun #define WM8990_ALRCBGPIO6 0x4000 /* ALRCBGPIO6 */ 260*4882a593Smuzhiyun #define WM8990_AIF_TRIS 0x2000 /* AIF_TRIS */ 261*4882a593Smuzhiyun #define WM8990_DACLRC_DIR 0x0800 /* DACLRC_DIR */ 262*4882a593Smuzhiyun #define WM8990_DACLRC_RATE_MASK 0x07FF /* DACLRC_RATE */ 263*4882a593Smuzhiyun 264*4882a593Smuzhiyun /* 265*4882a593Smuzhiyun * R10 (0x0A) - DAC CTRL 266*4882a593Smuzhiyun */ 267*4882a593Smuzhiyun #define WM8990_AIF_LRCLKRATE 0x0400 /* AIF_LRCLKRATE */ 268*4882a593Smuzhiyun #define WM8990_DAC_MONO 0x0200 /* DAC_MONO */ 269*4882a593Smuzhiyun #define WM8990_DAC_SB_FILT 0x0100 /* DAC_SB_FILT */ 270*4882a593Smuzhiyun #define WM8990_DAC_MUTERATE 0x0080 /* DAC_MUTERATE */ 271*4882a593Smuzhiyun #define WM8990_DAC_MUTEMODE 0x0040 /* DAC_MUTEMODE */ 272*4882a593Smuzhiyun #define WM8990_DEEMP_MASK 0x0030 /* DEEMP - [5:4] */ 273*4882a593Smuzhiyun #define WM8990_DAC_MUTE 0x0004 /* DAC_MUTE */ 274*4882a593Smuzhiyun #define WM8990_DACL_DATINV 0x0002 /* DACL_DATINV */ 275*4882a593Smuzhiyun #define WM8990_DACR_DATINV 0x0001 /* DACR_DATINV */ 276*4882a593Smuzhiyun 277*4882a593Smuzhiyun /* 278*4882a593Smuzhiyun * R11 (0x0B) - Left DAC Digital Volume 279*4882a593Smuzhiyun */ 280*4882a593Smuzhiyun #define WM8990_DAC_VU 0x0100 /* DAC_VU */ 281*4882a593Smuzhiyun #define WM8990_DACL_VOL_MASK 0x00FF /* DACL_VOL - [7:0] */ 282*4882a593Smuzhiyun #define WM8990_DACL_VOL_SHIFT 0 283*4882a593Smuzhiyun /* 284*4882a593Smuzhiyun * R12 (0x0C) - Right DAC Digital Volume 285*4882a593Smuzhiyun */ 286*4882a593Smuzhiyun #define WM8990_DAC_VU 0x0100 /* DAC_VU */ 287*4882a593Smuzhiyun #define WM8990_DACR_VOL_MASK 0x00FF /* DACR_VOL - [7:0] */ 288*4882a593Smuzhiyun #define WM8990_DACR_VOL_SHIFT 0 289*4882a593Smuzhiyun /* 290*4882a593Smuzhiyun * R13 (0x0D) - Digital Side Tone 291*4882a593Smuzhiyun */ 292*4882a593Smuzhiyun #define WM8990_ADCL_DAC_SVOL_MASK 0x0F /* ADCL_DAC_SVOL */ 293*4882a593Smuzhiyun #define WM8990_ADCL_DAC_SVOL_SHIFT 9 294*4882a593Smuzhiyun #define WM8990_ADCR_DAC_SVOL_MASK 0x0F /* ADCR_DAC_SVOL */ 295*4882a593Smuzhiyun #define WM8990_ADCR_DAC_SVOL_SHIFT 5 296*4882a593Smuzhiyun #define WM8990_ADC_TO_DACL_MASK 0x03 /* ADC_TO_DACL - [3:2] */ 297*4882a593Smuzhiyun #define WM8990_ADC_TO_DACL_SHIFT 2 298*4882a593Smuzhiyun #define WM8990_ADC_TO_DACR_MASK 0x03 /* ADC_TO_DACR - [1:0] */ 299*4882a593Smuzhiyun #define WM8990_ADC_TO_DACR_SHIFT 0 300*4882a593Smuzhiyun 301*4882a593Smuzhiyun /* 302*4882a593Smuzhiyun * R14 (0x0E) - ADC CTRL 303*4882a593Smuzhiyun */ 304*4882a593Smuzhiyun #define WM8990_ADC_HPF_ENA 0x0100 /* ADC_HPF_ENA */ 305*4882a593Smuzhiyun #define WM8990_ADC_HPF_ENA_BIT 8 306*4882a593Smuzhiyun #define WM8990_ADC_HPF_CUT_MASK 0x03 /* ADC_HPF_CUT - [6:5] */ 307*4882a593Smuzhiyun #define WM8990_ADC_HPF_CUT_SHIFT 5 308*4882a593Smuzhiyun #define WM8990_ADCL_DATINV 0x0002 /* ADCL_DATINV */ 309*4882a593Smuzhiyun #define WM8990_ADCL_DATINV_BIT 1 310*4882a593Smuzhiyun #define WM8990_ADCR_DATINV 0x0001 /* ADCR_DATINV */ 311*4882a593Smuzhiyun #define WM8990_ADCR_DATINV_BIT 0 312*4882a593Smuzhiyun 313*4882a593Smuzhiyun /* 314*4882a593Smuzhiyun * R15 (0x0F) - Left ADC Digital Volume 315*4882a593Smuzhiyun */ 316*4882a593Smuzhiyun #define WM8990_ADC_VU 0x0100 /* ADC_VU */ 317*4882a593Smuzhiyun #define WM8990_ADCL_VOL_MASK 0x00FF /* ADCL_VOL - [7:0] */ 318*4882a593Smuzhiyun #define WM8990_ADCL_VOL_SHIFT 0 319*4882a593Smuzhiyun 320*4882a593Smuzhiyun /* 321*4882a593Smuzhiyun * R16 (0x10) - Right ADC Digital Volume 322*4882a593Smuzhiyun */ 323*4882a593Smuzhiyun #define WM8990_ADC_VU 0x0100 /* ADC_VU */ 324*4882a593Smuzhiyun #define WM8990_ADCR_VOL_MASK 0x00FF /* ADCR_VOL - [7:0] */ 325*4882a593Smuzhiyun #define WM8990_ADCR_VOL_SHIFT 0 326*4882a593Smuzhiyun 327*4882a593Smuzhiyun /* 328*4882a593Smuzhiyun * R18 (0x12) - GPIO CTRL 1 329*4882a593Smuzhiyun */ 330*4882a593Smuzhiyun #define WM8990_IRQ 0x1000 /* IRQ */ 331*4882a593Smuzhiyun #define WM8990_TEMPOK 0x0800 /* TEMPOK */ 332*4882a593Smuzhiyun #define WM8990_MICSHRT 0x0400 /* MICSHRT */ 333*4882a593Smuzhiyun #define WM8990_MICDET 0x0200 /* MICDET */ 334*4882a593Smuzhiyun #define WM8990_PLL_LCK 0x0100 /* PLL_LCK */ 335*4882a593Smuzhiyun #define WM8990_GPI8_STATUS 0x0080 /* GPI8_STATUS */ 336*4882a593Smuzhiyun #define WM8990_GPI7_STATUS 0x0040 /* GPI7_STATUS */ 337*4882a593Smuzhiyun #define WM8990_GPIO6_STATUS 0x0020 /* GPIO6_STATUS */ 338*4882a593Smuzhiyun #define WM8990_GPIO5_STATUS 0x0010 /* GPIO5_STATUS */ 339*4882a593Smuzhiyun #define WM8990_GPIO4_STATUS 0x0008 /* GPIO4_STATUS */ 340*4882a593Smuzhiyun #define WM8990_GPIO3_STATUS 0x0004 /* GPIO3_STATUS */ 341*4882a593Smuzhiyun #define WM8990_GPIO2_STATUS 0x0002 /* GPIO2_STATUS */ 342*4882a593Smuzhiyun #define WM8990_GPIO1_STATUS 0x0001 /* GPIO1_STATUS */ 343*4882a593Smuzhiyun 344*4882a593Smuzhiyun /* 345*4882a593Smuzhiyun * R19 (0x13) - GPIO1 & GPIO2 346*4882a593Smuzhiyun */ 347*4882a593Smuzhiyun #define WM8990_GPIO2_DEB_ENA 0x8000 /* GPIO2_DEB_ENA */ 348*4882a593Smuzhiyun #define WM8990_GPIO2_IRQ_ENA 0x4000 /* GPIO2_IRQ_ENA */ 349*4882a593Smuzhiyun #define WM8990_GPIO2_PU 0x2000 /* GPIO2_PU */ 350*4882a593Smuzhiyun #define WM8990_GPIO2_PD 0x1000 /* GPIO2_PD */ 351*4882a593Smuzhiyun #define WM8990_GPIO2_SEL_MASK 0x0F00 /* GPIO2_SEL - [11:8] */ 352*4882a593Smuzhiyun #define WM8990_GPIO1_DEB_ENA 0x0080 /* GPIO1_DEB_ENA */ 353*4882a593Smuzhiyun #define WM8990_GPIO1_IRQ_ENA 0x0040 /* GPIO1_IRQ_ENA */ 354*4882a593Smuzhiyun #define WM8990_GPIO1_PU 0x0020 /* GPIO1_PU */ 355*4882a593Smuzhiyun #define WM8990_GPIO1_PD 0x0010 /* GPIO1_PD */ 356*4882a593Smuzhiyun #define WM8990_GPIO1_SEL_MASK 0x000F /* GPIO1_SEL - [3:0] */ 357*4882a593Smuzhiyun 358*4882a593Smuzhiyun /* 359*4882a593Smuzhiyun * R20 (0x14) - GPIO3 & GPIO4 360*4882a593Smuzhiyun */ 361*4882a593Smuzhiyun #define WM8990_GPIO4_DEB_ENA 0x8000 /* GPIO4_DEB_ENA */ 362*4882a593Smuzhiyun #define WM8990_GPIO4_IRQ_ENA 0x4000 /* GPIO4_IRQ_ENA */ 363*4882a593Smuzhiyun #define WM8990_GPIO4_PU 0x2000 /* GPIO4_PU */ 364*4882a593Smuzhiyun #define WM8990_GPIO4_PD 0x1000 /* GPIO4_PD */ 365*4882a593Smuzhiyun #define WM8990_GPIO4_SEL_MASK 0x0F00 /* GPIO4_SEL - [11:8] */ 366*4882a593Smuzhiyun #define WM8990_GPIO3_DEB_ENA 0x0080 /* GPIO3_DEB_ENA */ 367*4882a593Smuzhiyun #define WM8990_GPIO3_IRQ_ENA 0x0040 /* GPIO3_IRQ_ENA */ 368*4882a593Smuzhiyun #define WM8990_GPIO3_PU 0x0020 /* GPIO3_PU */ 369*4882a593Smuzhiyun #define WM8990_GPIO3_PD 0x0010 /* GPIO3_PD */ 370*4882a593Smuzhiyun #define WM8990_GPIO3_SEL_MASK 0x000F /* GPIO3_SEL - [3:0] */ 371*4882a593Smuzhiyun 372*4882a593Smuzhiyun /* 373*4882a593Smuzhiyun * R21 (0x15) - GPIO5 & GPIO6 374*4882a593Smuzhiyun */ 375*4882a593Smuzhiyun #define WM8990_GPIO6_DEB_ENA 0x8000 /* GPIO6_DEB_ENA */ 376*4882a593Smuzhiyun #define WM8990_GPIO6_IRQ_ENA 0x4000 /* GPIO6_IRQ_ENA */ 377*4882a593Smuzhiyun #define WM8990_GPIO6_PU 0x2000 /* GPIO6_PU */ 378*4882a593Smuzhiyun #define WM8990_GPIO6_PD 0x1000 /* GPIO6_PD */ 379*4882a593Smuzhiyun #define WM8990_GPIO6_SEL_MASK 0x0F00 /* GPIO6_SEL - [11:8] */ 380*4882a593Smuzhiyun #define WM8990_GPIO5_DEB_ENA 0x0080 /* GPIO5_DEB_ENA */ 381*4882a593Smuzhiyun #define WM8990_GPIO5_IRQ_ENA 0x0040 /* GPIO5_IRQ_ENA */ 382*4882a593Smuzhiyun #define WM8990_GPIO5_PU 0x0020 /* GPIO5_PU */ 383*4882a593Smuzhiyun #define WM8990_GPIO5_PD 0x0010 /* GPIO5_PD */ 384*4882a593Smuzhiyun #define WM8990_GPIO5_SEL_MASK 0x000F /* GPIO5_SEL - [3:0] */ 385*4882a593Smuzhiyun 386*4882a593Smuzhiyun /* 387*4882a593Smuzhiyun * R22 (0x16) - GPIOCTRL 2 388*4882a593Smuzhiyun */ 389*4882a593Smuzhiyun #define WM8990_RD_3W_ENA 0x8000 /* RD_3W_ENA */ 390*4882a593Smuzhiyun #define WM8990_MODE_3W4W 0x4000 /* MODE_3W4W */ 391*4882a593Smuzhiyun #define WM8990_TEMPOK_IRQ_ENA 0x0800 /* TEMPOK_IRQ_ENA */ 392*4882a593Smuzhiyun #define WM8990_MICSHRT_IRQ_ENA 0x0400 /* MICSHRT_IRQ_ENA */ 393*4882a593Smuzhiyun #define WM8990_MICDET_IRQ_ENA 0x0200 /* MICDET_IRQ_ENA */ 394*4882a593Smuzhiyun #define WM8990_PLL_LCK_IRQ_ENA 0x0100 /* PLL_LCK_IRQ_ENA */ 395*4882a593Smuzhiyun #define WM8990_GPI8_DEB_ENA 0x0080 /* GPI8_DEB_ENA */ 396*4882a593Smuzhiyun #define WM8990_GPI8_IRQ_ENA 0x0040 /* GPI8_IRQ_ENA */ 397*4882a593Smuzhiyun #define WM8990_GPI8_ENA 0x0010 /* GPI8_ENA */ 398*4882a593Smuzhiyun #define WM8990_GPI7_DEB_ENA 0x0008 /* GPI7_DEB_ENA */ 399*4882a593Smuzhiyun #define WM8990_GPI7_IRQ_ENA 0x0004 /* GPI7_IRQ_ENA */ 400*4882a593Smuzhiyun #define WM8990_GPI7_ENA 0x0001 /* GPI7_ENA */ 401*4882a593Smuzhiyun 402*4882a593Smuzhiyun /* 403*4882a593Smuzhiyun * R23 (0x17) - GPIO_POL 404*4882a593Smuzhiyun */ 405*4882a593Smuzhiyun #define WM8990_IRQ_INV 0x1000 /* IRQ_INV */ 406*4882a593Smuzhiyun #define WM8990_TEMPOK_POL 0x0800 /* TEMPOK_POL */ 407*4882a593Smuzhiyun #define WM8990_MICSHRT_POL 0x0400 /* MICSHRT_POL */ 408*4882a593Smuzhiyun #define WM8990_MICDET_POL 0x0200 /* MICDET_POL */ 409*4882a593Smuzhiyun #define WM8990_PLL_LCK_POL 0x0100 /* PLL_LCK_POL */ 410*4882a593Smuzhiyun #define WM8990_GPI8_POL 0x0080 /* GPI8_POL */ 411*4882a593Smuzhiyun #define WM8990_GPI7_POL 0x0040 /* GPI7_POL */ 412*4882a593Smuzhiyun #define WM8990_GPIO6_POL 0x0020 /* GPIO6_POL */ 413*4882a593Smuzhiyun #define WM8990_GPIO5_POL 0x0010 /* GPIO5_POL */ 414*4882a593Smuzhiyun #define WM8990_GPIO4_POL 0x0008 /* GPIO4_POL */ 415*4882a593Smuzhiyun #define WM8990_GPIO3_POL 0x0004 /* GPIO3_POL */ 416*4882a593Smuzhiyun #define WM8990_GPIO2_POL 0x0002 /* GPIO2_POL */ 417*4882a593Smuzhiyun #define WM8990_GPIO1_POL 0x0001 /* GPIO1_POL */ 418*4882a593Smuzhiyun 419*4882a593Smuzhiyun /* 420*4882a593Smuzhiyun * R24 (0x18) - Left Line Input 1&2 Volume 421*4882a593Smuzhiyun */ 422*4882a593Smuzhiyun #define WM8990_IPVU 0x0100 /* IPVU */ 423*4882a593Smuzhiyun #define WM8990_LI12MUTE 0x0080 /* LI12MUTE */ 424*4882a593Smuzhiyun #define WM8990_LI12MUTE_BIT 7 425*4882a593Smuzhiyun #define WM8990_LI12ZC 0x0040 /* LI12ZC */ 426*4882a593Smuzhiyun #define WM8990_LI12ZC_BIT 6 427*4882a593Smuzhiyun #define WM8990_LIN12VOL_MASK 0x001F /* LIN12VOL - [4:0] */ 428*4882a593Smuzhiyun #define WM8990_LIN12VOL_SHIFT 0 429*4882a593Smuzhiyun /* 430*4882a593Smuzhiyun * R25 (0x19) - Left Line Input 3&4 Volume 431*4882a593Smuzhiyun */ 432*4882a593Smuzhiyun #define WM8990_IPVU 0x0100 /* IPVU */ 433*4882a593Smuzhiyun #define WM8990_LI34MUTE 0x0080 /* LI34MUTE */ 434*4882a593Smuzhiyun #define WM8990_LI34MUTE_BIT 7 435*4882a593Smuzhiyun #define WM8990_LI34ZC 0x0040 /* LI34ZC */ 436*4882a593Smuzhiyun #define WM8990_LI34ZC_BIT 6 437*4882a593Smuzhiyun #define WM8990_LIN34VOL_MASK 0x001F /* LIN34VOL - [4:0] */ 438*4882a593Smuzhiyun #define WM8990_LIN34VOL_SHIFT 0 439*4882a593Smuzhiyun 440*4882a593Smuzhiyun /* 441*4882a593Smuzhiyun * R26 (0x1A) - Right Line Input 1&2 Volume 442*4882a593Smuzhiyun */ 443*4882a593Smuzhiyun #define WM8990_IPVU 0x0100 /* IPVU */ 444*4882a593Smuzhiyun #define WM8990_RI12MUTE 0x0080 /* RI12MUTE */ 445*4882a593Smuzhiyun #define WM8990_RI12MUTE_BIT 7 446*4882a593Smuzhiyun #define WM8990_RI12ZC 0x0040 /* RI12ZC */ 447*4882a593Smuzhiyun #define WM8990_RI12ZC_BIT 6 448*4882a593Smuzhiyun #define WM8990_RIN12VOL_MASK 0x001F /* RIN12VOL - [4:0] */ 449*4882a593Smuzhiyun #define WM8990_RIN12VOL_SHIFT 0 450*4882a593Smuzhiyun 451*4882a593Smuzhiyun /* 452*4882a593Smuzhiyun * R27 (0x1B) - Right Line Input 3&4 Volume 453*4882a593Smuzhiyun */ 454*4882a593Smuzhiyun #define WM8990_IPVU 0x0100 /* IPVU */ 455*4882a593Smuzhiyun #define WM8990_RI34MUTE 0x0080 /* RI34MUTE */ 456*4882a593Smuzhiyun #define WM8990_RI34MUTE_BIT 7 457*4882a593Smuzhiyun #define WM8990_RI34ZC 0x0040 /* RI34ZC */ 458*4882a593Smuzhiyun #define WM8990_RI34ZC_BIT 6 459*4882a593Smuzhiyun #define WM8990_RIN34VOL_MASK 0x001F /* RIN34VOL - [4:0] */ 460*4882a593Smuzhiyun #define WM8990_RIN34VOL_SHIFT 0 461*4882a593Smuzhiyun 462*4882a593Smuzhiyun /* 463*4882a593Smuzhiyun * R28 (0x1C) - Left Output Volume 464*4882a593Smuzhiyun */ 465*4882a593Smuzhiyun #define WM8990_OPVU 0x0100 /* OPVU */ 466*4882a593Smuzhiyun #define WM8990_LOZC 0x0080 /* LOZC */ 467*4882a593Smuzhiyun #define WM8990_LOZC_BIT 7 468*4882a593Smuzhiyun #define WM8990_LOUTVOL_MASK 0x007F /* LOUTVOL - [6:0] */ 469*4882a593Smuzhiyun #define WM8990_LOUTVOL_SHIFT 0 470*4882a593Smuzhiyun /* 471*4882a593Smuzhiyun * R29 (0x1D) - Right Output Volume 472*4882a593Smuzhiyun */ 473*4882a593Smuzhiyun #define WM8990_OPVU 0x0100 /* OPVU */ 474*4882a593Smuzhiyun #define WM8990_ROZC 0x0080 /* ROZC */ 475*4882a593Smuzhiyun #define WM8990_ROZC_BIT 7 476*4882a593Smuzhiyun #define WM8990_ROUTVOL_MASK 0x007F /* ROUTVOL - [6:0] */ 477*4882a593Smuzhiyun #define WM8990_ROUTVOL_SHIFT 0 478*4882a593Smuzhiyun /* 479*4882a593Smuzhiyun * R30 (0x1E) - Line Outputs Volume 480*4882a593Smuzhiyun */ 481*4882a593Smuzhiyun #define WM8990_LONMUTE 0x0040 /* LONMUTE */ 482*4882a593Smuzhiyun #define WM8990_LONMUTE_BIT 6 483*4882a593Smuzhiyun #define WM8990_LOPMUTE 0x0020 /* LOPMUTE */ 484*4882a593Smuzhiyun #define WM8990_LOPMUTE_BIT 5 485*4882a593Smuzhiyun #define WM8990_LOATTN 0x0010 /* LOATTN */ 486*4882a593Smuzhiyun #define WM8990_LOATTN_BIT 4 487*4882a593Smuzhiyun #define WM8990_RONMUTE 0x0004 /* RONMUTE */ 488*4882a593Smuzhiyun #define WM8990_RONMUTE_BIT 2 489*4882a593Smuzhiyun #define WM8990_ROPMUTE 0x0002 /* ROPMUTE */ 490*4882a593Smuzhiyun #define WM8990_ROPMUTE_BIT 1 491*4882a593Smuzhiyun #define WM8990_ROATTN 0x0001 /* ROATTN */ 492*4882a593Smuzhiyun #define WM8990_ROATTN_BIT 0 493*4882a593Smuzhiyun 494*4882a593Smuzhiyun /* 495*4882a593Smuzhiyun * R31 (0x1F) - Out3/4 Volume 496*4882a593Smuzhiyun */ 497*4882a593Smuzhiyun #define WM8990_OUT3MUTE 0x0020 /* OUT3MUTE */ 498*4882a593Smuzhiyun #define WM8990_OUT3MUTE_BIT 5 499*4882a593Smuzhiyun #define WM8990_OUT3ATTN 0x0010 /* OUT3ATTN */ 500*4882a593Smuzhiyun #define WM8990_OUT3ATTN_BIT 4 501*4882a593Smuzhiyun #define WM8990_OUT4MUTE 0x0002 /* OUT4MUTE */ 502*4882a593Smuzhiyun #define WM8990_OUT4MUTE_BIT 1 503*4882a593Smuzhiyun #define WM8990_OUT4ATTN 0x0001 /* OUT4ATTN */ 504*4882a593Smuzhiyun #define WM8990_OUT4ATTN_BIT 0 505*4882a593Smuzhiyun 506*4882a593Smuzhiyun /* 507*4882a593Smuzhiyun * R32 (0x20) - Left OPGA Volume 508*4882a593Smuzhiyun */ 509*4882a593Smuzhiyun #define WM8990_OPVU 0x0100 /* OPVU */ 510*4882a593Smuzhiyun #define WM8990_LOPGAZC 0x0080 /* LOPGAZC */ 511*4882a593Smuzhiyun #define WM8990_LOPGAZC_BIT 7 512*4882a593Smuzhiyun #define WM8990_LOPGAVOL_MASK 0x007F /* LOPGAVOL - [6:0] */ 513*4882a593Smuzhiyun #define WM8990_LOPGAVOL_SHIFT 0 514*4882a593Smuzhiyun 515*4882a593Smuzhiyun /* 516*4882a593Smuzhiyun * R33 (0x21) - Right OPGA Volume 517*4882a593Smuzhiyun */ 518*4882a593Smuzhiyun #define WM8990_OPVU 0x0100 /* OPVU */ 519*4882a593Smuzhiyun #define WM8990_ROPGAZC 0x0080 /* ROPGAZC */ 520*4882a593Smuzhiyun #define WM8990_ROPGAZC_BIT 7 521*4882a593Smuzhiyun #define WM8990_ROPGAVOL_MASK 0x007F /* ROPGAVOL - [6:0] */ 522*4882a593Smuzhiyun #define WM8990_ROPGAVOL_SHIFT 0 523*4882a593Smuzhiyun /* 524*4882a593Smuzhiyun * R34 (0x22) - Speaker Volume 525*4882a593Smuzhiyun */ 526*4882a593Smuzhiyun #define WM8990_SPKATTN_MASK 0x0003 /* SPKATTN - [1:0] */ 527*4882a593Smuzhiyun #define WM8990_SPKATTN_SHIFT 0 528*4882a593Smuzhiyun 529*4882a593Smuzhiyun /* 530*4882a593Smuzhiyun * R35 (0x23) - ClassD1 531*4882a593Smuzhiyun */ 532*4882a593Smuzhiyun #define WM8990_CDMODE 0x0100 /* CDMODE */ 533*4882a593Smuzhiyun #define WM8990_CDMODE_BIT 8 534*4882a593Smuzhiyun 535*4882a593Smuzhiyun /* 536*4882a593Smuzhiyun * R37 (0x25) - ClassD3 537*4882a593Smuzhiyun */ 538*4882a593Smuzhiyun #define WM8990_DCGAIN_MASK 0x0007 /* DCGAIN - [5:3] */ 539*4882a593Smuzhiyun #define WM8990_DCGAIN_SHIFT 3 540*4882a593Smuzhiyun #define WM8990_ACGAIN_MASK 0x0007 /* ACGAIN - [2:0] */ 541*4882a593Smuzhiyun #define WM8990_ACGAIN_SHIFT 0 542*4882a593Smuzhiyun 543*4882a593Smuzhiyun /* 544*4882a593Smuzhiyun * R38 (0x26) - ClassD4 545*4882a593Smuzhiyun */ 546*4882a593Smuzhiyun #define WM8990_SPKZC_MASK 0x0001 /* SPKZC */ 547*4882a593Smuzhiyun #define WM8990_SPKZC_SHIFT 7 /* SPKZC */ 548*4882a593Smuzhiyun #define WM8990_SPKVOL_MASK 0x007F /* SPKVOL - [6:0] */ 549*4882a593Smuzhiyun #define WM8990_SPKVOL_SHIFT 0 /* SPKVOL - [6:0] */ 550*4882a593Smuzhiyun 551*4882a593Smuzhiyun /* 552*4882a593Smuzhiyun * R39 (0x27) - Input Mixer1 553*4882a593Smuzhiyun */ 554*4882a593Smuzhiyun #define WM8990_AINLMODE_MASK 0x000C /* AINLMODE - [3:2] */ 555*4882a593Smuzhiyun #define WM8990_AINLMODE_SHIFT 2 556*4882a593Smuzhiyun #define WM8990_AINRMODE_MASK 0x0003 /* AINRMODE - [1:0] */ 557*4882a593Smuzhiyun #define WM8990_AINRMODE_SHIFT 0 558*4882a593Smuzhiyun 559*4882a593Smuzhiyun /* 560*4882a593Smuzhiyun * R40 (0x28) - Input Mixer2 561*4882a593Smuzhiyun */ 562*4882a593Smuzhiyun #define WM8990_LMP4 0x0080 /* LMP4 */ 563*4882a593Smuzhiyun #define WM8990_LMP4_BIT 7 /* LMP4 */ 564*4882a593Smuzhiyun #define WM8990_LMN3 0x0040 /* LMN3 */ 565*4882a593Smuzhiyun #define WM8990_LMN3_BIT 6 /* LMN3 */ 566*4882a593Smuzhiyun #define WM8990_LMP2 0x0020 /* LMP2 */ 567*4882a593Smuzhiyun #define WM8990_LMP2_BIT 5 /* LMP2 */ 568*4882a593Smuzhiyun #define WM8990_LMN1 0x0010 /* LMN1 */ 569*4882a593Smuzhiyun #define WM8990_LMN1_BIT 4 /* LMN1 */ 570*4882a593Smuzhiyun #define WM8990_RMP4 0x0008 /* RMP4 */ 571*4882a593Smuzhiyun #define WM8990_RMP4_BIT 3 /* RMP4 */ 572*4882a593Smuzhiyun #define WM8990_RMN3 0x0004 /* RMN3 */ 573*4882a593Smuzhiyun #define WM8990_RMN3_BIT 2 /* RMN3 */ 574*4882a593Smuzhiyun #define WM8990_RMP2 0x0002 /* RMP2 */ 575*4882a593Smuzhiyun #define WM8990_RMP2_BIT 1 /* RMP2 */ 576*4882a593Smuzhiyun #define WM8990_RMN1 0x0001 /* RMN1 */ 577*4882a593Smuzhiyun #define WM8990_RMN1_BIT 0 /* RMN1 */ 578*4882a593Smuzhiyun 579*4882a593Smuzhiyun /* 580*4882a593Smuzhiyun * R41 (0x29) - Input Mixer3 581*4882a593Smuzhiyun */ 582*4882a593Smuzhiyun #define WM8990_L34MNB 0x0100 /* L34MNB */ 583*4882a593Smuzhiyun #define WM8990_L34MNB_BIT 8 584*4882a593Smuzhiyun #define WM8990_L34MNBST 0x0080 /* L34MNBST */ 585*4882a593Smuzhiyun #define WM8990_L34MNBST_BIT 7 586*4882a593Smuzhiyun #define WM8990_L12MNB 0x0020 /* L12MNB */ 587*4882a593Smuzhiyun #define WM8990_L12MNB_BIT 5 588*4882a593Smuzhiyun #define WM8990_L12MNBST 0x0010 /* L12MNBST */ 589*4882a593Smuzhiyun #define WM8990_L12MNBST_BIT 4 590*4882a593Smuzhiyun #define WM8990_LDBVOL_MASK 0x0007 /* LDBVOL - [2:0] */ 591*4882a593Smuzhiyun #define WM8990_LDBVOL_SHIFT 0 592*4882a593Smuzhiyun 593*4882a593Smuzhiyun /* 594*4882a593Smuzhiyun * R42 (0x2A) - Input Mixer4 595*4882a593Smuzhiyun */ 596*4882a593Smuzhiyun #define WM8990_R34MNB 0x0100 /* R34MNB */ 597*4882a593Smuzhiyun #define WM8990_R34MNB_BIT 8 598*4882a593Smuzhiyun #define WM8990_R34MNBST 0x0080 /* R34MNBST */ 599*4882a593Smuzhiyun #define WM8990_R34MNBST_BIT 7 600*4882a593Smuzhiyun #define WM8990_R12MNB 0x0020 /* R12MNB */ 601*4882a593Smuzhiyun #define WM8990_R12MNB_BIT 5 602*4882a593Smuzhiyun #define WM8990_R12MNBST 0x0010 /* R12MNBST */ 603*4882a593Smuzhiyun #define WM8990_R12MNBST_BIT 4 604*4882a593Smuzhiyun #define WM8990_RDBVOL_MASK 0x0007 /* RDBVOL - [2:0] */ 605*4882a593Smuzhiyun #define WM8990_RDBVOL_SHIFT 0 606*4882a593Smuzhiyun 607*4882a593Smuzhiyun /* 608*4882a593Smuzhiyun * R43 (0x2B) - Input Mixer5 609*4882a593Smuzhiyun */ 610*4882a593Smuzhiyun #define WM8990_LI2BVOL_MASK 0x07 /* LI2BVOL - [8:6] */ 611*4882a593Smuzhiyun #define WM8990_LI2BVOL_SHIFT 6 612*4882a593Smuzhiyun #define WM8990_LR4BVOL_MASK 0x07 /* LR4BVOL - [5:3] */ 613*4882a593Smuzhiyun #define WM8990_LR4BVOL_SHIFT 3 614*4882a593Smuzhiyun #define WM8990_LL4BVOL_MASK 0x07 /* LL4BVOL - [2:0] */ 615*4882a593Smuzhiyun #define WM8990_LL4BVOL_SHIFT 0 616*4882a593Smuzhiyun 617*4882a593Smuzhiyun /* 618*4882a593Smuzhiyun * R44 (0x2C) - Input Mixer6 619*4882a593Smuzhiyun */ 620*4882a593Smuzhiyun #define WM8990_RI2BVOL_MASK 0x07 /* RI2BVOL - [8:6] */ 621*4882a593Smuzhiyun #define WM8990_RI2BVOL_SHIFT 6 622*4882a593Smuzhiyun #define WM8990_RL4BVOL_MASK 0x07 /* RL4BVOL - [5:3] */ 623*4882a593Smuzhiyun #define WM8990_RL4BVOL_SHIFT 3 624*4882a593Smuzhiyun #define WM8990_RR4BVOL_MASK 0x07 /* RR4BVOL - [2:0] */ 625*4882a593Smuzhiyun #define WM8990_RR4BVOL_SHIFT 0 626*4882a593Smuzhiyun 627*4882a593Smuzhiyun /* 628*4882a593Smuzhiyun * R45 (0x2D) - Output Mixer1 629*4882a593Smuzhiyun */ 630*4882a593Smuzhiyun #define WM8990_LRBLO 0x0080 /* LRBLO */ 631*4882a593Smuzhiyun #define WM8990_LRBLO_BIT 7 632*4882a593Smuzhiyun #define WM8990_LLBLO 0x0040 /* LLBLO */ 633*4882a593Smuzhiyun #define WM8990_LLBLO_BIT 6 634*4882a593Smuzhiyun #define WM8990_LRI3LO 0x0020 /* LRI3LO */ 635*4882a593Smuzhiyun #define WM8990_LRI3LO_BIT 5 636*4882a593Smuzhiyun #define WM8990_LLI3LO 0x0010 /* LLI3LO */ 637*4882a593Smuzhiyun #define WM8990_LLI3LO_BIT 4 638*4882a593Smuzhiyun #define WM8990_LR12LO 0x0008 /* LR12LO */ 639*4882a593Smuzhiyun #define WM8990_LR12LO_BIT 3 640*4882a593Smuzhiyun #define WM8990_LL12LO 0x0004 /* LL12LO */ 641*4882a593Smuzhiyun #define WM8990_LL12LO_BIT 2 642*4882a593Smuzhiyun #define WM8990_LDLO 0x0001 /* LDLO */ 643*4882a593Smuzhiyun #define WM8990_LDLO_BIT 0 644*4882a593Smuzhiyun 645*4882a593Smuzhiyun /* 646*4882a593Smuzhiyun * R46 (0x2E) - Output Mixer2 647*4882a593Smuzhiyun */ 648*4882a593Smuzhiyun #define WM8990_RLBRO 0x0080 /* RLBRO */ 649*4882a593Smuzhiyun #define WM8990_RLBRO_BIT 7 650*4882a593Smuzhiyun #define WM8990_RRBRO 0x0040 /* RRBRO */ 651*4882a593Smuzhiyun #define WM8990_RRBRO_BIT 6 652*4882a593Smuzhiyun #define WM8990_RLI3RO 0x0020 /* RLI3RO */ 653*4882a593Smuzhiyun #define WM8990_RLI3RO_BIT 5 654*4882a593Smuzhiyun #define WM8990_RRI3RO 0x0010 /* RRI3RO */ 655*4882a593Smuzhiyun #define WM8990_RRI3RO_BIT 4 656*4882a593Smuzhiyun #define WM8990_RL12RO 0x0008 /* RL12RO */ 657*4882a593Smuzhiyun #define WM8990_RL12RO_BIT 3 658*4882a593Smuzhiyun #define WM8990_RR12RO 0x0004 /* RR12RO */ 659*4882a593Smuzhiyun #define WM8990_RR12RO_BIT 2 660*4882a593Smuzhiyun #define WM8990_RDRO 0x0001 /* RDRO */ 661*4882a593Smuzhiyun #define WM8990_RDRO_BIT 0 662*4882a593Smuzhiyun 663*4882a593Smuzhiyun /* 664*4882a593Smuzhiyun * R47 (0x2F) - Output Mixer3 665*4882a593Smuzhiyun */ 666*4882a593Smuzhiyun #define WM8990_LLI3LOVOL_MASK 0x07 /* LLI3LOVOL - [8:6] */ 667*4882a593Smuzhiyun #define WM8990_LLI3LOVOL_SHIFT 6 668*4882a593Smuzhiyun #define WM8990_LR12LOVOL_MASK 0x07 /* LR12LOVOL - [5:3] */ 669*4882a593Smuzhiyun #define WM8990_LR12LOVOL_SHIFT 3 670*4882a593Smuzhiyun #define WM8990_LL12LOVOL_MASK 0x07 /* LL12LOVOL - [2:0] */ 671*4882a593Smuzhiyun #define WM8990_LL12LOVOL_SHIFT 0 672*4882a593Smuzhiyun 673*4882a593Smuzhiyun /* 674*4882a593Smuzhiyun * R48 (0x30) - Output Mixer4 675*4882a593Smuzhiyun */ 676*4882a593Smuzhiyun #define WM8990_RRI3ROVOL_MASK 0x07 /* RRI3ROVOL - [8:6] */ 677*4882a593Smuzhiyun #define WM8990_RRI3ROVOL_SHIFT 6 678*4882a593Smuzhiyun #define WM8990_RL12ROVOL_MASK 0x07 /* RL12ROVOL - [5:3] */ 679*4882a593Smuzhiyun #define WM8990_RL12ROVOL_SHIFT 3 680*4882a593Smuzhiyun #define WM8990_RR12ROVOL_MASK 0x07 /* RR12ROVOL - [2:0] */ 681*4882a593Smuzhiyun #define WM8990_RR12ROVOL_SHIFT 0 682*4882a593Smuzhiyun 683*4882a593Smuzhiyun /* 684*4882a593Smuzhiyun * R49 (0x31) - Output Mixer5 685*4882a593Smuzhiyun */ 686*4882a593Smuzhiyun #define WM8990_LRI3LOVOL_MASK 0x07 /* LRI3LOVOL - [8:6] */ 687*4882a593Smuzhiyun #define WM8990_LRI3LOVOL_SHIFT 6 688*4882a593Smuzhiyun #define WM8990_LRBLOVOL_MASK 0x07 /* LRBLOVOL - [5:3] */ 689*4882a593Smuzhiyun #define WM8990_LRBLOVOL_SHIFT 3 690*4882a593Smuzhiyun #define WM8990_LLBLOVOL_MASK 0x07 /* LLBLOVOL - [2:0] */ 691*4882a593Smuzhiyun #define WM8990_LLBLOVOL_SHIFT 0 692*4882a593Smuzhiyun 693*4882a593Smuzhiyun /* 694*4882a593Smuzhiyun * R50 (0x32) - Output Mixer6 695*4882a593Smuzhiyun */ 696*4882a593Smuzhiyun #define WM8990_RLI3ROVOL_MASK 0x07 /* RLI3ROVOL - [8:6] */ 697*4882a593Smuzhiyun #define WM8990_RLI3ROVOL_SHIFT 6 698*4882a593Smuzhiyun #define WM8990_RLBROVOL_MASK 0x07 /* RLBROVOL - [5:3] */ 699*4882a593Smuzhiyun #define WM8990_RLBROVOL_SHIFT 3 700*4882a593Smuzhiyun #define WM8990_RRBROVOL_MASK 0x07 /* RRBROVOL - [2:0] */ 701*4882a593Smuzhiyun #define WM8990_RRBROVOL_SHIFT 0 702*4882a593Smuzhiyun 703*4882a593Smuzhiyun /* 704*4882a593Smuzhiyun * R51 (0x33) - Out3/4 Mixer 705*4882a593Smuzhiyun */ 706*4882a593Smuzhiyun #define WM8990_VSEL_MASK 0x0180 /* VSEL - [8:7] */ 707*4882a593Smuzhiyun #define WM8990_LI4O3 0x0020 /* LI4O3 */ 708*4882a593Smuzhiyun #define WM8990_LI4O3_BIT 5 709*4882a593Smuzhiyun #define WM8990_LPGAO3 0x0010 /* LPGAO3 */ 710*4882a593Smuzhiyun #define WM8990_LPGAO3_BIT 4 711*4882a593Smuzhiyun #define WM8990_RI4O4 0x0002 /* RI4O4 */ 712*4882a593Smuzhiyun #define WM8990_RI4O4_BIT 1 713*4882a593Smuzhiyun #define WM8990_RPGAO4 0x0001 /* RPGAO4 */ 714*4882a593Smuzhiyun #define WM8990_RPGAO4_BIT 0 715*4882a593Smuzhiyun /* 716*4882a593Smuzhiyun * R52 (0x34) - Line Mixer1 717*4882a593Smuzhiyun */ 718*4882a593Smuzhiyun #define WM8990_LLOPGALON 0x0040 /* LLOPGALON */ 719*4882a593Smuzhiyun #define WM8990_LLOPGALON_BIT 6 720*4882a593Smuzhiyun #define WM8990_LROPGALON 0x0020 /* LROPGALON */ 721*4882a593Smuzhiyun #define WM8990_LROPGALON_BIT 5 722*4882a593Smuzhiyun #define WM8990_LOPLON 0x0010 /* LOPLON */ 723*4882a593Smuzhiyun #define WM8990_LOPLON_BIT 4 724*4882a593Smuzhiyun #define WM8990_LR12LOP 0x0004 /* LR12LOP */ 725*4882a593Smuzhiyun #define WM8990_LR12LOP_BIT 2 726*4882a593Smuzhiyun #define WM8990_LL12LOP 0x0002 /* LL12LOP */ 727*4882a593Smuzhiyun #define WM8990_LL12LOP_BIT 1 728*4882a593Smuzhiyun #define WM8990_LLOPGALOP 0x0001 /* LLOPGALOP */ 729*4882a593Smuzhiyun #define WM8990_LLOPGALOP_BIT 0 730*4882a593Smuzhiyun /* 731*4882a593Smuzhiyun * R53 (0x35) - Line Mixer2 732*4882a593Smuzhiyun */ 733*4882a593Smuzhiyun #define WM8990_RROPGARON 0x0040 /* RROPGARON */ 734*4882a593Smuzhiyun #define WM8990_RROPGARON_BIT 6 735*4882a593Smuzhiyun #define WM8990_RLOPGARON 0x0020 /* RLOPGARON */ 736*4882a593Smuzhiyun #define WM8990_RLOPGARON_BIT 5 737*4882a593Smuzhiyun #define WM8990_ROPRON 0x0010 /* ROPRON */ 738*4882a593Smuzhiyun #define WM8990_ROPRON_BIT 4 739*4882a593Smuzhiyun #define WM8990_RL12ROP 0x0004 /* RL12ROP */ 740*4882a593Smuzhiyun #define WM8990_RL12ROP_BIT 2 741*4882a593Smuzhiyun #define WM8990_RR12ROP 0x0002 /* RR12ROP */ 742*4882a593Smuzhiyun #define WM8990_RR12ROP_BIT 1 743*4882a593Smuzhiyun #define WM8990_RROPGAROP 0x0001 /* RROPGAROP */ 744*4882a593Smuzhiyun #define WM8990_RROPGAROP_BIT 0 745*4882a593Smuzhiyun 746*4882a593Smuzhiyun /* 747*4882a593Smuzhiyun * R54 (0x36) - Speaker Mixer 748*4882a593Smuzhiyun */ 749*4882a593Smuzhiyun #define WM8990_LB2SPK 0x0080 /* LB2SPK */ 750*4882a593Smuzhiyun #define WM8990_LB2SPK_BIT 7 751*4882a593Smuzhiyun #define WM8990_RB2SPK 0x0040 /* RB2SPK */ 752*4882a593Smuzhiyun #define WM8990_RB2SPK_BIT 6 753*4882a593Smuzhiyun #define WM8990_LI2SPK 0x0020 /* LI2SPK */ 754*4882a593Smuzhiyun #define WM8990_LI2SPK_BIT 5 755*4882a593Smuzhiyun #define WM8990_RI2SPK 0x0010 /* RI2SPK */ 756*4882a593Smuzhiyun #define WM8990_RI2SPK_BIT 4 757*4882a593Smuzhiyun #define WM8990_LOPGASPK 0x0008 /* LOPGASPK */ 758*4882a593Smuzhiyun #define WM8990_LOPGASPK_BIT 3 759*4882a593Smuzhiyun #define WM8990_ROPGASPK 0x0004 /* ROPGASPK */ 760*4882a593Smuzhiyun #define WM8990_ROPGASPK_BIT 2 761*4882a593Smuzhiyun #define WM8990_LDSPK 0x0002 /* LDSPK */ 762*4882a593Smuzhiyun #define WM8990_LDSPK_BIT 1 763*4882a593Smuzhiyun #define WM8990_RDSPK 0x0001 /* RDSPK */ 764*4882a593Smuzhiyun #define WM8990_RDSPK_BIT 0 765*4882a593Smuzhiyun 766*4882a593Smuzhiyun /* 767*4882a593Smuzhiyun * R55 (0x37) - Additional Control 768*4882a593Smuzhiyun */ 769*4882a593Smuzhiyun #define WM8990_VROI 0x0001 /* VROI */ 770*4882a593Smuzhiyun 771*4882a593Smuzhiyun /* 772*4882a593Smuzhiyun * R56 (0x38) - AntiPOP1 773*4882a593Smuzhiyun */ 774*4882a593Smuzhiyun #define WM8990_DIS_LLINE 0x0020 /* DIS_LLINE */ 775*4882a593Smuzhiyun #define WM8990_DIS_RLINE 0x0010 /* DIS_RLINE */ 776*4882a593Smuzhiyun #define WM8990_DIS_OUT3 0x0008 /* DIS_OUT3 */ 777*4882a593Smuzhiyun #define WM8990_DIS_OUT4 0x0004 /* DIS_OUT4 */ 778*4882a593Smuzhiyun #define WM8990_DIS_LOUT 0x0002 /* DIS_LOUT */ 779*4882a593Smuzhiyun #define WM8990_DIS_ROUT 0x0001 /* DIS_ROUT */ 780*4882a593Smuzhiyun 781*4882a593Smuzhiyun /* 782*4882a593Smuzhiyun * R57 (0x39) - AntiPOP2 783*4882a593Smuzhiyun */ 784*4882a593Smuzhiyun #define WM8990_SOFTST 0x0040 /* SOFTST */ 785*4882a593Smuzhiyun #define WM8990_BUFIOEN 0x0008 /* BUFIOEN */ 786*4882a593Smuzhiyun #define WM8990_BUFDCOPEN 0x0004 /* BUFDCOPEN */ 787*4882a593Smuzhiyun #define WM8990_POBCTRL 0x0002 /* POBCTRL */ 788*4882a593Smuzhiyun #define WM8990_VMIDTOG 0x0001 /* VMIDTOG */ 789*4882a593Smuzhiyun 790*4882a593Smuzhiyun /* 791*4882a593Smuzhiyun * R58 (0x3A) - MICBIAS 792*4882a593Smuzhiyun */ 793*4882a593Smuzhiyun #define WM8990_MCDSCTH_MASK 0x00C0 /* MCDSCTH - [7:6] */ 794*4882a593Smuzhiyun #define WM8990_MCDTHR_MASK 0x0038 /* MCDTHR - [5:3] */ 795*4882a593Smuzhiyun #define WM8990_MCD 0x0004 /* MCD */ 796*4882a593Smuzhiyun #define WM8990_MBSEL 0x0001 /* MBSEL */ 797*4882a593Smuzhiyun 798*4882a593Smuzhiyun /* 799*4882a593Smuzhiyun * R60 (0x3C) - PLL1 800*4882a593Smuzhiyun */ 801*4882a593Smuzhiyun #define WM8990_SDM 0x0080 /* SDM */ 802*4882a593Smuzhiyun #define WM8990_PRESCALE 0x0040 /* PRESCALE */ 803*4882a593Smuzhiyun #define WM8990_PLLN_MASK 0x000F /* PLLN - [3:0] */ 804*4882a593Smuzhiyun 805*4882a593Smuzhiyun /* 806*4882a593Smuzhiyun * R61 (0x3D) - PLL2 807*4882a593Smuzhiyun */ 808*4882a593Smuzhiyun #define WM8990_PLLK1_MASK 0x00FF /* PLLK1 - [7:0] */ 809*4882a593Smuzhiyun 810*4882a593Smuzhiyun /* 811*4882a593Smuzhiyun * R62 (0x3E) - PLL3 812*4882a593Smuzhiyun */ 813*4882a593Smuzhiyun #define WM8990_PLLK2_MASK 0x00FF /* PLLK2 - [7:0] */ 814*4882a593Smuzhiyun 815*4882a593Smuzhiyun #define WM8990_MCLK_DIV 0 816*4882a593Smuzhiyun #define WM8990_DACCLK_DIV 1 817*4882a593Smuzhiyun #define WM8990_ADCCLK_DIV 2 818*4882a593Smuzhiyun #define WM8990_BCLK_DIV 3 819*4882a593Smuzhiyun 820*4882a593Smuzhiyun #endif /* __WM8990REGISTERDEFS_H__ */ 821*4882a593Smuzhiyun /*------------------------------ END OF FILE ---------------------------------*/ 822