1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * wm8978.h -- codec driver for WM8978 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright 2009 Guennadi Liakhovetski <g.liakhovetski@gmx.de> 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __WM8978_H__ 9*4882a593Smuzhiyun #define __WM8978_H__ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* 12*4882a593Smuzhiyun * Register values. 13*4882a593Smuzhiyun */ 14*4882a593Smuzhiyun #define WM8978_RESET 0x00 15*4882a593Smuzhiyun #define WM8978_POWER_MANAGEMENT_1 0x01 16*4882a593Smuzhiyun #define WM8978_POWER_MANAGEMENT_2 0x02 17*4882a593Smuzhiyun #define WM8978_POWER_MANAGEMENT_3 0x03 18*4882a593Smuzhiyun #define WM8978_AUDIO_INTERFACE 0x04 19*4882a593Smuzhiyun #define WM8978_COMPANDING_CONTROL 0x05 20*4882a593Smuzhiyun #define WM8978_CLOCKING 0x06 21*4882a593Smuzhiyun #define WM8978_ADDITIONAL_CONTROL 0x07 22*4882a593Smuzhiyun #define WM8978_GPIO_CONTROL 0x08 23*4882a593Smuzhiyun #define WM8978_JACK_DETECT_CONTROL_1 0x09 24*4882a593Smuzhiyun #define WM8978_DAC_CONTROL 0x0A 25*4882a593Smuzhiyun #define WM8978_LEFT_DAC_DIGITAL_VOLUME 0x0B 26*4882a593Smuzhiyun #define WM8978_RIGHT_DAC_DIGITAL_VOLUME 0x0C 27*4882a593Smuzhiyun #define WM8978_JACK_DETECT_CONTROL_2 0x0D 28*4882a593Smuzhiyun #define WM8978_ADC_CONTROL 0x0E 29*4882a593Smuzhiyun #define WM8978_LEFT_ADC_DIGITAL_VOLUME 0x0F 30*4882a593Smuzhiyun #define WM8978_RIGHT_ADC_DIGITAL_VOLUME 0x10 31*4882a593Smuzhiyun #define WM8978_EQ1 0x12 32*4882a593Smuzhiyun #define WM8978_EQ2 0x13 33*4882a593Smuzhiyun #define WM8978_EQ3 0x14 34*4882a593Smuzhiyun #define WM8978_EQ4 0x15 35*4882a593Smuzhiyun #define WM8978_EQ5 0x16 36*4882a593Smuzhiyun #define WM8978_DAC_LIMITER_1 0x18 37*4882a593Smuzhiyun #define WM8978_DAC_LIMITER_2 0x19 38*4882a593Smuzhiyun #define WM8978_NOTCH_FILTER_1 0x1b 39*4882a593Smuzhiyun #define WM8978_NOTCH_FILTER_2 0x1c 40*4882a593Smuzhiyun #define WM8978_NOTCH_FILTER_3 0x1d 41*4882a593Smuzhiyun #define WM8978_NOTCH_FILTER_4 0x1e 42*4882a593Smuzhiyun #define WM8978_ALC_CONTROL_1 0x20 43*4882a593Smuzhiyun #define WM8978_ALC_CONTROL_2 0x21 44*4882a593Smuzhiyun #define WM8978_ALC_CONTROL_3 0x22 45*4882a593Smuzhiyun #define WM8978_NOISE_GATE 0x23 46*4882a593Smuzhiyun #define WM8978_PLL_N 0x24 47*4882a593Smuzhiyun #define WM8978_PLL_K1 0x25 48*4882a593Smuzhiyun #define WM8978_PLL_K2 0x26 49*4882a593Smuzhiyun #define WM8978_PLL_K3 0x27 50*4882a593Smuzhiyun #define WM8978_3D_CONTROL 0x29 51*4882a593Smuzhiyun #define WM8978_BEEP_CONTROL 0x2b 52*4882a593Smuzhiyun #define WM8978_INPUT_CONTROL 0x2c 53*4882a593Smuzhiyun #define WM8978_LEFT_INP_PGA_CONTROL 0x2d 54*4882a593Smuzhiyun #define WM8978_RIGHT_INP_PGA_CONTROL 0x2e 55*4882a593Smuzhiyun #define WM8978_LEFT_ADC_BOOST_CONTROL 0x2f 56*4882a593Smuzhiyun #define WM8978_RIGHT_ADC_BOOST_CONTROL 0x30 57*4882a593Smuzhiyun #define WM8978_OUTPUT_CONTROL 0x31 58*4882a593Smuzhiyun #define WM8978_LEFT_MIXER_CONTROL 0x32 59*4882a593Smuzhiyun #define WM8978_RIGHT_MIXER_CONTROL 0x33 60*4882a593Smuzhiyun #define WM8978_LOUT1_HP_CONTROL 0x34 61*4882a593Smuzhiyun #define WM8978_ROUT1_HP_CONTROL 0x35 62*4882a593Smuzhiyun #define WM8978_LOUT2_SPK_CONTROL 0x36 63*4882a593Smuzhiyun #define WM8978_ROUT2_SPK_CONTROL 0x37 64*4882a593Smuzhiyun #define WM8978_OUT3_MIXER_CONTROL 0x38 65*4882a593Smuzhiyun #define WM8978_OUT4_MIXER_CONTROL 0x39 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun #define WM8978_MAX_REGISTER 0x39 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun #define WM8978_CACHEREGNUM 58 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun /* Clock divider Id's */ 72*4882a593Smuzhiyun enum wm8978_clk_id { 73*4882a593Smuzhiyun WM8978_OPCLKRATE, 74*4882a593Smuzhiyun WM8978_BCLKDIV, 75*4882a593Smuzhiyun }; 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun enum wm8978_sysclk_src { 78*4882a593Smuzhiyun WM8978_MCLK = 0, 79*4882a593Smuzhiyun WM8978_PLL, 80*4882a593Smuzhiyun }; 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun #endif /* __WM8978_H__ */ 83