1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * wm8974.h -- WM8974 Soc Audio driver 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef _WM8974_H 7*4882a593Smuzhiyun #define _WM8974_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun /* WM8974 register space */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define WM8974_RESET 0x0 12*4882a593Smuzhiyun #define WM8974_POWER1 0x1 13*4882a593Smuzhiyun #define WM8974_POWER2 0x2 14*4882a593Smuzhiyun #define WM8974_POWER3 0x3 15*4882a593Smuzhiyun #define WM8974_IFACE 0x4 16*4882a593Smuzhiyun #define WM8974_COMP 0x5 17*4882a593Smuzhiyun #define WM8974_CLOCK 0x6 18*4882a593Smuzhiyun #define WM8974_ADD 0x7 19*4882a593Smuzhiyun #define WM8974_GPIO 0x8 20*4882a593Smuzhiyun #define WM8974_DAC 0xa 21*4882a593Smuzhiyun #define WM8974_DACVOL 0xb 22*4882a593Smuzhiyun #define WM8974_ADC 0xe 23*4882a593Smuzhiyun #define WM8974_ADCVOL 0xf 24*4882a593Smuzhiyun #define WM8974_EQ1 0x12 25*4882a593Smuzhiyun #define WM8974_EQ2 0x13 26*4882a593Smuzhiyun #define WM8974_EQ3 0x14 27*4882a593Smuzhiyun #define WM8974_EQ4 0x15 28*4882a593Smuzhiyun #define WM8974_EQ5 0x16 29*4882a593Smuzhiyun #define WM8974_DACLIM1 0x18 30*4882a593Smuzhiyun #define WM8974_DACLIM2 0x19 31*4882a593Smuzhiyun #define WM8974_NOTCH1 0x1b 32*4882a593Smuzhiyun #define WM8974_NOTCH2 0x1c 33*4882a593Smuzhiyun #define WM8974_NOTCH3 0x1d 34*4882a593Smuzhiyun #define WM8974_NOTCH4 0x1e 35*4882a593Smuzhiyun #define WM8974_ALC1 0x20 36*4882a593Smuzhiyun #define WM8974_ALC2 0x21 37*4882a593Smuzhiyun #define WM8974_ALC3 0x22 38*4882a593Smuzhiyun #define WM8974_NGATE 0x23 39*4882a593Smuzhiyun #define WM8974_PLLN 0x24 40*4882a593Smuzhiyun #define WM8974_PLLK1 0x25 41*4882a593Smuzhiyun #define WM8974_PLLK2 0x26 42*4882a593Smuzhiyun #define WM8974_PLLK3 0x27 43*4882a593Smuzhiyun #define WM8974_ATTEN 0x28 44*4882a593Smuzhiyun #define WM8974_INPUT 0x2c 45*4882a593Smuzhiyun #define WM8974_INPPGA 0x2d 46*4882a593Smuzhiyun #define WM8974_ADCBOOST 0x2f 47*4882a593Smuzhiyun #define WM8974_OUTPUT 0x31 48*4882a593Smuzhiyun #define WM8974_SPKMIX 0x32 49*4882a593Smuzhiyun #define WM8974_SPKVOL 0x36 50*4882a593Smuzhiyun #define WM8974_MONOMIX 0x38 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun #define WM8974_CACHEREGNUM 57 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun /* Clock divider Id's */ 55*4882a593Smuzhiyun #define WM8974_OPCLKDIV 0 56*4882a593Smuzhiyun #define WM8974_MCLKDIV 1 57*4882a593Smuzhiyun #define WM8974_BCLKDIV 2 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun /* PLL Out dividers */ 60*4882a593Smuzhiyun #define WM8974_OPCLKDIV_1 (0 << 4) 61*4882a593Smuzhiyun #define WM8974_OPCLKDIV_2 (1 << 4) 62*4882a593Smuzhiyun #define WM8974_OPCLKDIV_3 (2 << 4) 63*4882a593Smuzhiyun #define WM8974_OPCLKDIV_4 (3 << 4) 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun /* BCLK clock dividers */ 66*4882a593Smuzhiyun #define WM8974_BCLKDIV_1 (0 << 2) 67*4882a593Smuzhiyun #define WM8974_BCLKDIV_2 (1 << 2) 68*4882a593Smuzhiyun #define WM8974_BCLKDIV_4 (2 << 2) 69*4882a593Smuzhiyun #define WM8974_BCLKDIV_8 (3 << 2) 70*4882a593Smuzhiyun #define WM8974_BCLKDIV_16 (4 << 2) 71*4882a593Smuzhiyun #define WM8974_BCLKDIV_32 (5 << 2) 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun /* MCLK clock dividers */ 74*4882a593Smuzhiyun #define WM8974_MCLKDIV_1 (0 << 5) 75*4882a593Smuzhiyun #define WM8974_MCLKDIV_1_5 (1 << 5) 76*4882a593Smuzhiyun #define WM8974_MCLKDIV_2 (2 << 5) 77*4882a593Smuzhiyun #define WM8974_MCLKDIV_3 (3 << 5) 78*4882a593Smuzhiyun #define WM8974_MCLKDIV_4 (4 << 5) 79*4882a593Smuzhiyun #define WM8974_MCLKDIV_6 (5 << 5) 80*4882a593Smuzhiyun #define WM8974_MCLKDIV_8 (6 << 5) 81*4882a593Smuzhiyun #define WM8974_MCLKDIV_12 (7 << 5) 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun #endif 84