1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * wm8962.h -- WM8962 ASoC driver 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright 2010 Wolfson Microelectronics, plc 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef _WM8962_H 11*4882a593Smuzhiyun #define _WM8962_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #include <asm/types.h> 14*4882a593Smuzhiyun #include <sound/soc.h> 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #define WM8962_SYSCLK_MCLK 0 17*4882a593Smuzhiyun #define WM8962_SYSCLK_FLL 1 18*4882a593Smuzhiyun #define WM8962_SYSCLK_PLL3 2 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define WM8962_FLL 1 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define WM8962_FLL_MCLK 1 23*4882a593Smuzhiyun #define WM8962_FLL_BCLK 2 24*4882a593Smuzhiyun #define WM8962_FLL_OSC 3 25*4882a593Smuzhiyun #define WM8962_FLL_INT 4 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /* 28*4882a593Smuzhiyun * Register values. 29*4882a593Smuzhiyun */ 30*4882a593Smuzhiyun #define WM8962_LEFT_INPUT_VOLUME 0x00 31*4882a593Smuzhiyun #define WM8962_RIGHT_INPUT_VOLUME 0x01 32*4882a593Smuzhiyun #define WM8962_HPOUTL_VOLUME 0x02 33*4882a593Smuzhiyun #define WM8962_HPOUTR_VOLUME 0x03 34*4882a593Smuzhiyun #define WM8962_CLOCKING1 0x04 35*4882a593Smuzhiyun #define WM8962_ADC_DAC_CONTROL_1 0x05 36*4882a593Smuzhiyun #define WM8962_ADC_DAC_CONTROL_2 0x06 37*4882a593Smuzhiyun #define WM8962_AUDIO_INTERFACE_0 0x07 38*4882a593Smuzhiyun #define WM8962_CLOCKING2 0x08 39*4882a593Smuzhiyun #define WM8962_AUDIO_INTERFACE_1 0x09 40*4882a593Smuzhiyun #define WM8962_LEFT_DAC_VOLUME 0x0A 41*4882a593Smuzhiyun #define WM8962_RIGHT_DAC_VOLUME 0x0B 42*4882a593Smuzhiyun #define WM8962_AUDIO_INTERFACE_2 0x0E 43*4882a593Smuzhiyun #define WM8962_SOFTWARE_RESET 0x0F 44*4882a593Smuzhiyun #define WM8962_ALC1 0x11 45*4882a593Smuzhiyun #define WM8962_ALC2 0x12 46*4882a593Smuzhiyun #define WM8962_ALC3 0x13 47*4882a593Smuzhiyun #define WM8962_NOISE_GATE 0x14 48*4882a593Smuzhiyun #define WM8962_LEFT_ADC_VOLUME 0x15 49*4882a593Smuzhiyun #define WM8962_RIGHT_ADC_VOLUME 0x16 50*4882a593Smuzhiyun #define WM8962_ADDITIONAL_CONTROL_1 0x17 51*4882a593Smuzhiyun #define WM8962_ADDITIONAL_CONTROL_2 0x18 52*4882a593Smuzhiyun #define WM8962_PWR_MGMT_1 0x19 53*4882a593Smuzhiyun #define WM8962_PWR_MGMT_2 0x1A 54*4882a593Smuzhiyun #define WM8962_ADDITIONAL_CONTROL_3 0x1B 55*4882a593Smuzhiyun #define WM8962_ANTI_POP 0x1C 56*4882a593Smuzhiyun #define WM8962_CLOCKING_3 0x1E 57*4882a593Smuzhiyun #define WM8962_INPUT_MIXER_CONTROL_1 0x1F 58*4882a593Smuzhiyun #define WM8962_LEFT_INPUT_MIXER_VOLUME 0x20 59*4882a593Smuzhiyun #define WM8962_RIGHT_INPUT_MIXER_VOLUME 0x21 60*4882a593Smuzhiyun #define WM8962_INPUT_MIXER_CONTROL_2 0x22 61*4882a593Smuzhiyun #define WM8962_INPUT_BIAS_CONTROL 0x23 62*4882a593Smuzhiyun #define WM8962_LEFT_INPUT_PGA_CONTROL 0x25 63*4882a593Smuzhiyun #define WM8962_RIGHT_INPUT_PGA_CONTROL 0x26 64*4882a593Smuzhiyun #define WM8962_SPKOUTL_VOLUME 0x28 65*4882a593Smuzhiyun #define WM8962_SPKOUTR_VOLUME 0x29 66*4882a593Smuzhiyun #define WM8962_THERMAL_SHUTDOWN_STATUS 0x2F 67*4882a593Smuzhiyun #define WM8962_ADDITIONAL_CONTROL_4 0x30 68*4882a593Smuzhiyun #define WM8962_CLASS_D_CONTROL_1 0x31 69*4882a593Smuzhiyun #define WM8962_CLASS_D_CONTROL_2 0x33 70*4882a593Smuzhiyun #define WM8962_CLOCKING_4 0x38 71*4882a593Smuzhiyun #define WM8962_DAC_DSP_MIXING_1 0x39 72*4882a593Smuzhiyun #define WM8962_DAC_DSP_MIXING_2 0x3A 73*4882a593Smuzhiyun #define WM8962_DC_SERVO_0 0x3C 74*4882a593Smuzhiyun #define WM8962_DC_SERVO_1 0x3D 75*4882a593Smuzhiyun #define WM8962_DC_SERVO_4 0x40 76*4882a593Smuzhiyun #define WM8962_DC_SERVO_6 0x42 77*4882a593Smuzhiyun #define WM8962_ANALOGUE_PGA_BIAS 0x44 78*4882a593Smuzhiyun #define WM8962_ANALOGUE_HP_0 0x45 79*4882a593Smuzhiyun #define WM8962_ANALOGUE_HP_2 0x47 80*4882a593Smuzhiyun #define WM8962_CHARGE_PUMP_1 0x48 81*4882a593Smuzhiyun #define WM8962_CHARGE_PUMP_B 0x52 82*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_CONTROL_1 0x57 83*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_CONTROL_2 0x5A 84*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_CONTROL_3 0x5D 85*4882a593Smuzhiyun #define WM8962_CONTROL_INTERFACE 0x5E 86*4882a593Smuzhiyun #define WM8962_MIXER_ENABLES 0x63 87*4882a593Smuzhiyun #define WM8962_HEADPHONE_MIXER_1 0x64 88*4882a593Smuzhiyun #define WM8962_HEADPHONE_MIXER_2 0x65 89*4882a593Smuzhiyun #define WM8962_HEADPHONE_MIXER_3 0x66 90*4882a593Smuzhiyun #define WM8962_HEADPHONE_MIXER_4 0x67 91*4882a593Smuzhiyun #define WM8962_SPEAKER_MIXER_1 0x69 92*4882a593Smuzhiyun #define WM8962_SPEAKER_MIXER_2 0x6A 93*4882a593Smuzhiyun #define WM8962_SPEAKER_MIXER_3 0x6B 94*4882a593Smuzhiyun #define WM8962_SPEAKER_MIXER_4 0x6C 95*4882a593Smuzhiyun #define WM8962_SPEAKER_MIXER_5 0x6D 96*4882a593Smuzhiyun #define WM8962_BEEP_GENERATOR_1 0x6E 97*4882a593Smuzhiyun #define WM8962_OSCILLATOR_TRIM_3 0x73 98*4882a593Smuzhiyun #define WM8962_OSCILLATOR_TRIM_4 0x74 99*4882a593Smuzhiyun #define WM8962_OSCILLATOR_TRIM_7 0x77 100*4882a593Smuzhiyun #define WM8962_ANALOGUE_CLOCKING1 0x7C 101*4882a593Smuzhiyun #define WM8962_ANALOGUE_CLOCKING2 0x7D 102*4882a593Smuzhiyun #define WM8962_ANALOGUE_CLOCKING3 0x7E 103*4882a593Smuzhiyun #define WM8962_PLL_SOFTWARE_RESET 0x7F 104*4882a593Smuzhiyun #define WM8962_PLL2 0x81 105*4882a593Smuzhiyun #define WM8962_PLL_4 0x83 106*4882a593Smuzhiyun #define WM8962_PLL_9 0x88 107*4882a593Smuzhiyun #define WM8962_PLL_10 0x89 108*4882a593Smuzhiyun #define WM8962_PLL_11 0x8A 109*4882a593Smuzhiyun #define WM8962_PLL_12 0x8B 110*4882a593Smuzhiyun #define WM8962_PLL_13 0x8C 111*4882a593Smuzhiyun #define WM8962_PLL_14 0x8D 112*4882a593Smuzhiyun #define WM8962_PLL_15 0x8E 113*4882a593Smuzhiyun #define WM8962_PLL_16 0x8F 114*4882a593Smuzhiyun #define WM8962_FLL_CONTROL_1 0x9B 115*4882a593Smuzhiyun #define WM8962_FLL_CONTROL_2 0x9C 116*4882a593Smuzhiyun #define WM8962_FLL_CONTROL_3 0x9D 117*4882a593Smuzhiyun #define WM8962_FLL_CONTROL_5 0x9F 118*4882a593Smuzhiyun #define WM8962_FLL_CONTROL_6 0xA0 119*4882a593Smuzhiyun #define WM8962_FLL_CONTROL_7 0xA1 120*4882a593Smuzhiyun #define WM8962_FLL_CONTROL_8 0xA2 121*4882a593Smuzhiyun #define WM8962_GENERAL_TEST_1 0xFC 122*4882a593Smuzhiyun #define WM8962_DF1 0x100 123*4882a593Smuzhiyun #define WM8962_DF2 0x101 124*4882a593Smuzhiyun #define WM8962_DF3 0x102 125*4882a593Smuzhiyun #define WM8962_DF4 0x103 126*4882a593Smuzhiyun #define WM8962_DF5 0x104 127*4882a593Smuzhiyun #define WM8962_DF6 0x105 128*4882a593Smuzhiyun #define WM8962_DF7 0x106 129*4882a593Smuzhiyun #define WM8962_LHPF1 0x108 130*4882a593Smuzhiyun #define WM8962_LHPF2 0x109 131*4882a593Smuzhiyun #define WM8962_THREED1 0x10C 132*4882a593Smuzhiyun #define WM8962_THREED2 0x10D 133*4882a593Smuzhiyun #define WM8962_THREED3 0x10E 134*4882a593Smuzhiyun #define WM8962_THREED4 0x10F 135*4882a593Smuzhiyun #define WM8962_DRC_1 0x114 136*4882a593Smuzhiyun #define WM8962_DRC_2 0x115 137*4882a593Smuzhiyun #define WM8962_DRC_3 0x116 138*4882a593Smuzhiyun #define WM8962_DRC_4 0x117 139*4882a593Smuzhiyun #define WM8962_DRC_5 0x118 140*4882a593Smuzhiyun #define WM8962_TLOOPBACK 0x11D 141*4882a593Smuzhiyun #define WM8962_EQ1 0x14F 142*4882a593Smuzhiyun #define WM8962_EQ2 0x150 143*4882a593Smuzhiyun #define WM8962_EQ3 0x151 144*4882a593Smuzhiyun #define WM8962_EQ4 0x152 145*4882a593Smuzhiyun #define WM8962_EQ5 0x153 146*4882a593Smuzhiyun #define WM8962_EQ6 0x154 147*4882a593Smuzhiyun #define WM8962_EQ7 0x155 148*4882a593Smuzhiyun #define WM8962_EQ8 0x156 149*4882a593Smuzhiyun #define WM8962_EQ9 0x157 150*4882a593Smuzhiyun #define WM8962_EQ10 0x158 151*4882a593Smuzhiyun #define WM8962_EQ11 0x159 152*4882a593Smuzhiyun #define WM8962_EQ12 0x15A 153*4882a593Smuzhiyun #define WM8962_EQ13 0x15B 154*4882a593Smuzhiyun #define WM8962_EQ14 0x15C 155*4882a593Smuzhiyun #define WM8962_EQ15 0x15D 156*4882a593Smuzhiyun #define WM8962_EQ16 0x15E 157*4882a593Smuzhiyun #define WM8962_EQ17 0x15F 158*4882a593Smuzhiyun #define WM8962_EQ18 0x160 159*4882a593Smuzhiyun #define WM8962_EQ19 0x161 160*4882a593Smuzhiyun #define WM8962_EQ20 0x162 161*4882a593Smuzhiyun #define WM8962_EQ21 0x163 162*4882a593Smuzhiyun #define WM8962_EQ22 0x164 163*4882a593Smuzhiyun #define WM8962_EQ23 0x165 164*4882a593Smuzhiyun #define WM8962_EQ24 0x166 165*4882a593Smuzhiyun #define WM8962_EQ25 0x167 166*4882a593Smuzhiyun #define WM8962_EQ26 0x168 167*4882a593Smuzhiyun #define WM8962_EQ27 0x169 168*4882a593Smuzhiyun #define WM8962_EQ28 0x16A 169*4882a593Smuzhiyun #define WM8962_EQ29 0x16B 170*4882a593Smuzhiyun #define WM8962_EQ30 0x16C 171*4882a593Smuzhiyun #define WM8962_EQ31 0x16D 172*4882a593Smuzhiyun #define WM8962_EQ32 0x16E 173*4882a593Smuzhiyun #define WM8962_EQ33 0x16F 174*4882a593Smuzhiyun #define WM8962_EQ34 0x170 175*4882a593Smuzhiyun #define WM8962_EQ35 0x171 176*4882a593Smuzhiyun #define WM8962_EQ36 0x172 177*4882a593Smuzhiyun #define WM8962_EQ37 0x173 178*4882a593Smuzhiyun #define WM8962_EQ38 0x174 179*4882a593Smuzhiyun #define WM8962_EQ39 0x175 180*4882a593Smuzhiyun #define WM8962_EQ40 0x176 181*4882a593Smuzhiyun #define WM8962_EQ41 0x177 182*4882a593Smuzhiyun #define WM8962_GPIO_BASE 0x200 183*4882a593Smuzhiyun #define WM8962_GPIO_2 0x201 184*4882a593Smuzhiyun #define WM8962_GPIO_3 0x202 185*4882a593Smuzhiyun #define WM8962_GPIO_5 0x204 186*4882a593Smuzhiyun #define WM8962_GPIO_6 0x205 187*4882a593Smuzhiyun #define WM8962_INTERRUPT_STATUS_1 0x230 188*4882a593Smuzhiyun #define WM8962_INTERRUPT_STATUS_2 0x231 189*4882a593Smuzhiyun #define WM8962_INTERRUPT_STATUS_1_MASK 0x238 190*4882a593Smuzhiyun #define WM8962_INTERRUPT_STATUS_2_MASK 0x239 191*4882a593Smuzhiyun #define WM8962_INTERRUPT_CONTROL 0x240 192*4882a593Smuzhiyun #define WM8962_IRQ_DEBOUNCE 0x248 193*4882a593Smuzhiyun #define WM8962_MICINT_SOURCE_POL 0x24A 194*4882a593Smuzhiyun #define WM8962_DSP2_POWER_MANAGEMENT 0x300 195*4882a593Smuzhiyun #define WM8962_DSP2_EXECCONTROL 0x40D 196*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_0 0x1000 197*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_1 0x1001 198*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_2 0x1002 199*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_3 0x1003 200*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_4 0x1004 201*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_5 0x1005 202*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_6 0x1006 203*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_7 0x1007 204*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_8 0x1008 205*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_9 0x1009 206*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_10 0x100A 207*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_11 0x100B 208*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_12 0x100C 209*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_13 0x100D 210*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_14 0x100E 211*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_15 0x100F 212*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_16 0x1010 213*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_17 0x1011 214*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_18 0x1012 215*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_19 0x1013 216*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_20 0x1014 217*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_21 0x1015 218*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_22 0x1016 219*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_23 0x1017 220*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_24 0x1018 221*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_25 0x1019 222*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_26 0x101A 223*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_27 0x101B 224*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_28 0x101C 225*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_29 0x101D 226*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_30 0x101E 227*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_31 0x101F 228*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_32 0x1020 229*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_33 0x1021 230*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_34 0x1022 231*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_35 0x1023 232*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_36 0x1024 233*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_37 0x1025 234*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_38 0x1026 235*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_39 0x1027 236*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_40 0x1028 237*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_41 0x1029 238*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_42 0x102A 239*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_43 0x102B 240*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_44 0x102C 241*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_45 0x102D 242*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_46 0x102E 243*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_47 0x102F 244*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_48 0x1030 245*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_49 0x1031 246*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_50 0x1032 247*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_51 0x1033 248*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_52 0x1034 249*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_53 0x1035 250*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_54 0x1036 251*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_55 0x1037 252*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_56 0x1038 253*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_57 0x1039 254*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_58 0x103A 255*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_59 0x103B 256*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_60 0x103C 257*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_61 0x103D 258*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_62 0x103E 259*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_63 0x103F 260*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_64 0x1040 261*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_65 0x1041 262*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_66 0x1042 263*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_67 0x1043 264*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_68 0x1044 265*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_69 0x1045 266*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_70 0x1046 267*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_71 0x1047 268*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_72 0x1048 269*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_73 0x1049 270*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_74 0x104A 271*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_75 0x104B 272*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_76 0x104C 273*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_77 0x104D 274*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_78 0x104E 275*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_79 0x104F 276*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_80 0x1050 277*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_81 0x1051 278*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_82 0x1052 279*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_83 0x1053 280*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_84 0x1054 281*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_85 0x1055 282*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_86 0x1056 283*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_87 0x1057 284*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_88 0x1058 285*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_89 0x1059 286*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_90 0x105A 287*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_91 0x105B 288*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_92 0x105C 289*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_93 0x105D 290*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_94 0x105E 291*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_95 0x105F 292*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_96 0x1060 293*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_97 0x1061 294*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_98 0x1062 295*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_99 0x1063 296*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_100 0x1064 297*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_101 0x1065 298*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_102 0x1066 299*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_103 0x1067 300*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_104 0x1068 301*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_105 0x1069 302*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_106 0x106A 303*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_107 0x106B 304*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_108 0x106C 305*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_109 0x106D 306*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_110 0x106E 307*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_111 0x106F 308*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_112 0x1070 309*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_113 0x1071 310*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_114 0x1072 311*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_115 0x1073 312*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_116 0x1074 313*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_117 0x1075 314*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_118 0x1076 315*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_119 0x1077 316*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_120 0x1078 317*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_121 0x1079 318*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_122 0x107A 319*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_123 0x107B 320*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_124 0x107C 321*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_125 0x107D 322*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_126 0x107E 323*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_127 0x107F 324*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_128 0x1080 325*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_129 0x1081 326*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_130 0x1082 327*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_131 0x1083 328*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_132 0x1084 329*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_133 0x1085 330*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_134 0x1086 331*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_135 0x1087 332*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_136 0x1088 333*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_137 0x1089 334*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_138 0x108A 335*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_139 0x108B 336*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_140 0x108C 337*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_141 0x108D 338*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_142 0x108E 339*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_143 0x108F 340*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_144 0x1090 341*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_145 0x1091 342*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_146 0x1092 343*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_147 0x1093 344*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_148 0x1094 345*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_149 0x1095 346*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_150 0x1096 347*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_151 0x1097 348*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_152 0x1098 349*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_153 0x1099 350*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_154 0x109A 351*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_155 0x109B 352*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_156 0x109C 353*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_157 0x109D 354*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_158 0x109E 355*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_159 0x109F 356*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_160 0x10A0 357*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_161 0x10A1 358*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_162 0x10A2 359*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_163 0x10A3 360*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_164 0x10A4 361*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_165 0x10A5 362*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_166 0x10A6 363*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_167 0x10A7 364*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_168 0x10A8 365*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_169 0x10A9 366*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_170 0x10AA 367*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_171 0x10AB 368*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_172 0x10AC 369*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_173 0x10AD 370*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_174 0x10AE 371*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_175 0x10AF 372*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_176 0x10B0 373*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_177 0x10B1 374*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_178 0x10B2 375*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_179 0x10B3 376*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_180 0x10B4 377*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_181 0x10B5 378*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_182 0x10B6 379*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_183 0x10B7 380*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_184 0x10B8 381*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_185 0x10B9 382*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_186 0x10BA 383*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_187 0x10BB 384*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_188 0x10BC 385*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_189 0x10BD 386*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_190 0x10BE 387*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_191 0x10BF 388*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_192 0x10C0 389*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_193 0x10C1 390*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_194 0x10C2 391*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_195 0x10C3 392*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_196 0x10C4 393*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_197 0x10C5 394*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_198 0x10C6 395*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_199 0x10C7 396*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_200 0x10C8 397*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_201 0x10C9 398*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_202 0x10CA 399*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_203 0x10CB 400*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_204 0x10CC 401*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_205 0x10CD 402*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_206 0x10CE 403*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_207 0x10CF 404*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_208 0x10D0 405*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_209 0x10D1 406*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_210 0x10D2 407*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_211 0x10D3 408*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_212 0x10D4 409*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_213 0x10D5 410*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_214 0x10D6 411*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_215 0x10D7 412*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_216 0x10D8 413*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_217 0x10D9 414*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_218 0x10DA 415*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_219 0x10DB 416*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_220 0x10DC 417*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_221 0x10DD 418*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_222 0x10DE 419*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_223 0x10DF 420*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_224 0x10E0 421*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_225 0x10E1 422*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_226 0x10E2 423*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_227 0x10E3 424*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_228 0x10E4 425*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_229 0x10E5 426*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_230 0x10E6 427*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_231 0x10E7 428*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_232 0x10E8 429*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_233 0x10E9 430*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_234 0x10EA 431*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_235 0x10EB 432*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_236 0x10EC 433*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_237 0x10ED 434*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_238 0x10EE 435*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_239 0x10EF 436*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_240 0x10F0 437*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_241 0x10F1 438*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_242 0x10F2 439*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_243 0x10F3 440*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_244 0x10F4 441*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_245 0x10F5 442*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_246 0x10F6 443*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_247 0x10F7 444*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_248 0x10F8 445*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_249 0x10F9 446*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_250 0x10FA 447*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_251 0x10FB 448*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_252 0x10FC 449*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_253 0x10FD 450*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_254 0x10FE 451*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_255 0x10FF 452*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_256 0x1100 453*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_257 0x1101 454*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_258 0x1102 455*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_259 0x1103 456*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_260 0x1104 457*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_261 0x1105 458*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_262 0x1106 459*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_263 0x1107 460*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_264 0x1108 461*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_265 0x1109 462*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_266 0x110A 463*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_267 0x110B 464*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_268 0x110C 465*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_269 0x110D 466*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_270 0x110E 467*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_271 0x110F 468*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_272 0x1110 469*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_273 0x1111 470*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_274 0x1112 471*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_275 0x1113 472*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_276 0x1114 473*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_277 0x1115 474*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_278 0x1116 475*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_279 0x1117 476*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_280 0x1118 477*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_281 0x1119 478*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_282 0x111A 479*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_283 0x111B 480*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_284 0x111C 481*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_285 0x111D 482*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_286 0x111E 483*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_287 0x111F 484*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_288 0x1120 485*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_289 0x1121 486*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_290 0x1122 487*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_291 0x1123 488*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_292 0x1124 489*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_293 0x1125 490*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_294 0x1126 491*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_295 0x1127 492*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_296 0x1128 493*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_297 0x1129 494*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_298 0x112A 495*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_299 0x112B 496*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_300 0x112C 497*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_301 0x112D 498*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_302 0x112E 499*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_303 0x112F 500*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_304 0x1130 501*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_305 0x1131 502*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_306 0x1132 503*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_307 0x1133 504*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_308 0x1134 505*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_309 0x1135 506*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_310 0x1136 507*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_311 0x1137 508*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_312 0x1138 509*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_313 0x1139 510*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_314 0x113A 511*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_315 0x113B 512*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_316 0x113C 513*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_317 0x113D 514*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_318 0x113E 515*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_319 0x113F 516*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_320 0x1140 517*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_321 0x1141 518*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_322 0x1142 519*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_323 0x1143 520*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_324 0x1144 521*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_325 0x1145 522*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_326 0x1146 523*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_327 0x1147 524*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_328 0x1148 525*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_329 0x1149 526*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_330 0x114A 527*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_331 0x114B 528*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_332 0x114C 529*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_333 0x114D 530*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_334 0x114E 531*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_335 0x114F 532*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_336 0x1150 533*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_337 0x1151 534*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_338 0x1152 535*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_339 0x1153 536*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_340 0x1154 537*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_341 0x1155 538*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_342 0x1156 539*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_343 0x1157 540*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_344 0x1158 541*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_345 0x1159 542*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_346 0x115A 543*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_347 0x115B 544*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_348 0x115C 545*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_349 0x115D 546*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_350 0x115E 547*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_351 0x115F 548*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_352 0x1160 549*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_353 0x1161 550*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_354 0x1162 551*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_355 0x1163 552*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_356 0x1164 553*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_357 0x1165 554*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_358 0x1166 555*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_359 0x1167 556*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_360 0x1168 557*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_361 0x1169 558*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_362 0x116A 559*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_363 0x116B 560*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_364 0x116C 561*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_365 0x116D 562*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_366 0x116E 563*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_367 0x116F 564*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_368 0x1170 565*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_369 0x1171 566*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_370 0x1172 567*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_371 0x1173 568*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_372 0x1174 569*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_373 0x1175 570*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_374 0x1176 571*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_375 0x1177 572*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_376 0x1178 573*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_377 0x1179 574*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_378 0x117A 575*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_379 0x117B 576*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_380 0x117C 577*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_381 0x117D 578*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_382 0x117E 579*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_383 0x117F 580*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_384 0x1180 581*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_385 0x1181 582*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_386 0x1182 583*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_387 0x1183 584*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_388 0x1184 585*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_389 0x1185 586*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_390 0x1186 587*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_391 0x1187 588*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_392 0x1188 589*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_393 0x1189 590*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_394 0x118A 591*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_395 0x118B 592*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_396 0x118C 593*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_397 0x118D 594*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_398 0x118E 595*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_399 0x118F 596*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_400 0x1190 597*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_401 0x1191 598*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_402 0x1192 599*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_403 0x1193 600*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_404 0x1194 601*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_405 0x1195 602*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_406 0x1196 603*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_407 0x1197 604*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_408 0x1198 605*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_409 0x1199 606*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_410 0x119A 607*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_411 0x119B 608*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_412 0x119C 609*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_413 0x119D 610*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_414 0x119E 611*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_415 0x119F 612*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_416 0x11A0 613*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_417 0x11A1 614*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_418 0x11A2 615*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_419 0x11A3 616*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_420 0x11A4 617*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_421 0x11A5 618*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_422 0x11A6 619*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_423 0x11A7 620*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_424 0x11A8 621*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_425 0x11A9 622*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_426 0x11AA 623*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_427 0x11AB 624*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_428 0x11AC 625*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_429 0x11AD 626*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_430 0x11AE 627*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_431 0x11AF 628*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_432 0x11B0 629*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_433 0x11B1 630*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_434 0x11B2 631*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_435 0x11B3 632*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_436 0x11B4 633*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_437 0x11B5 634*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_438 0x11B6 635*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_439 0x11B7 636*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_440 0x11B8 637*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_441 0x11B9 638*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_442 0x11BA 639*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_443 0x11BB 640*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_444 0x11BC 641*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_445 0x11BD 642*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_446 0x11BE 643*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_447 0x11BF 644*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_448 0x11C0 645*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_449 0x11C1 646*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_450 0x11C2 647*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_451 0x11C3 648*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_452 0x11C4 649*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_453 0x11C5 650*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_454 0x11C6 651*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_455 0x11C7 652*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_456 0x11C8 653*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_457 0x11C9 654*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_458 0x11CA 655*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_459 0x11CB 656*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_460 0x11CC 657*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_461 0x11CD 658*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_462 0x11CE 659*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_463 0x11CF 660*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_464 0x11D0 661*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_465 0x11D1 662*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_466 0x11D2 663*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_467 0x11D3 664*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_468 0x11D4 665*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_469 0x11D5 666*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_470 0x11D6 667*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_471 0x11D7 668*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_472 0x11D8 669*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_473 0x11D9 670*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_474 0x11DA 671*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_475 0x11DB 672*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_476 0x11DC 673*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_477 0x11DD 674*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_478 0x11DE 675*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_479 0x11DF 676*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_480 0x11E0 677*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_481 0x11E1 678*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_482 0x11E2 679*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_483 0x11E3 680*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_484 0x11E4 681*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_485 0x11E5 682*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_486 0x11E6 683*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_487 0x11E7 684*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_488 0x11E8 685*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_489 0x11E9 686*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_490 0x11EA 687*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_491 0x11EB 688*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_492 0x11EC 689*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_493 0x11ED 690*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_494 0x11EE 691*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_495 0x11EF 692*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_496 0x11F0 693*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_497 0x11F1 694*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_498 0x11F2 695*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_499 0x11F3 696*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_500 0x11F4 697*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_501 0x11F5 698*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_502 0x11F6 699*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_503 0x11F7 700*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_504 0x11F8 701*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_505 0x11F9 702*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_506 0x11FA 703*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_507 0x11FB 704*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_508 0x11FC 705*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_509 0x11FD 706*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_510 0x11FE 707*4882a593Smuzhiyun #define WM8962_WRITE_SEQUENCER_511 0x11FF 708*4882a593Smuzhiyun #define WM8962_DSP2_INSTRUCTION_RAM_0 0x2000 709*4882a593Smuzhiyun #define WM8962_DSP2_ADDRESS_RAM_2 0x2400 710*4882a593Smuzhiyun #define WM8962_DSP2_ADDRESS_RAM_1 0x2401 711*4882a593Smuzhiyun #define WM8962_DSP2_ADDRESS_RAM_0 0x2402 712*4882a593Smuzhiyun #define WM8962_DSP2_DATA1_RAM_1 0x3000 713*4882a593Smuzhiyun #define WM8962_DSP2_DATA1_RAM_0 0x3001 714*4882a593Smuzhiyun #define WM8962_DSP2_DATA2_RAM_1 0x3400 715*4882a593Smuzhiyun #define WM8962_DSP2_DATA2_RAM_0 0x3401 716*4882a593Smuzhiyun #define WM8962_DSP2_DATA3_RAM_1 0x3800 717*4882a593Smuzhiyun #define WM8962_DSP2_DATA3_RAM_0 0x3801 718*4882a593Smuzhiyun #define WM8962_DSP2_COEFF_RAM_0 0x3C00 719*4882a593Smuzhiyun #define WM8962_RETUNEADC_SHARED_COEFF_1 0x4000 720*4882a593Smuzhiyun #define WM8962_RETUNEADC_SHARED_COEFF_0 0x4001 721*4882a593Smuzhiyun #define WM8962_RETUNEDAC_SHARED_COEFF_1 0x4002 722*4882a593Smuzhiyun #define WM8962_RETUNEDAC_SHARED_COEFF_0 0x4003 723*4882a593Smuzhiyun #define WM8962_SOUNDSTAGE_ENABLES_1 0x4004 724*4882a593Smuzhiyun #define WM8962_SOUNDSTAGE_ENABLES_0 0x4005 725*4882a593Smuzhiyun #define WM8962_HDBASS_AI_1 0x4200 726*4882a593Smuzhiyun #define WM8962_HDBASS_AI_0 0x4201 727*4882a593Smuzhiyun #define WM8962_HDBASS_AR_1 0x4202 728*4882a593Smuzhiyun #define WM8962_HDBASS_AR_0 0x4203 729*4882a593Smuzhiyun #define WM8962_HDBASS_B_1 0x4204 730*4882a593Smuzhiyun #define WM8962_HDBASS_B_0 0x4205 731*4882a593Smuzhiyun #define WM8962_HDBASS_K_1 0x4206 732*4882a593Smuzhiyun #define WM8962_HDBASS_K_0 0x4207 733*4882a593Smuzhiyun #define WM8962_HDBASS_N1_1 0x4208 734*4882a593Smuzhiyun #define WM8962_HDBASS_N1_0 0x4209 735*4882a593Smuzhiyun #define WM8962_HDBASS_N2_1 0x420A 736*4882a593Smuzhiyun #define WM8962_HDBASS_N2_0 0x420B 737*4882a593Smuzhiyun #define WM8962_HDBASS_N3_1 0x420C 738*4882a593Smuzhiyun #define WM8962_HDBASS_N3_0 0x420D 739*4882a593Smuzhiyun #define WM8962_HDBASS_N4_1 0x420E 740*4882a593Smuzhiyun #define WM8962_HDBASS_N4_0 0x420F 741*4882a593Smuzhiyun #define WM8962_HDBASS_N5_1 0x4210 742*4882a593Smuzhiyun #define WM8962_HDBASS_N5_0 0x4211 743*4882a593Smuzhiyun #define WM8962_HDBASS_X1_1 0x4212 744*4882a593Smuzhiyun #define WM8962_HDBASS_X1_0 0x4213 745*4882a593Smuzhiyun #define WM8962_HDBASS_X2_1 0x4214 746*4882a593Smuzhiyun #define WM8962_HDBASS_X2_0 0x4215 747*4882a593Smuzhiyun #define WM8962_HDBASS_X3_1 0x4216 748*4882a593Smuzhiyun #define WM8962_HDBASS_X3_0 0x4217 749*4882a593Smuzhiyun #define WM8962_HDBASS_ATK_1 0x4218 750*4882a593Smuzhiyun #define WM8962_HDBASS_ATK_0 0x4219 751*4882a593Smuzhiyun #define WM8962_HDBASS_DCY_1 0x421A 752*4882a593Smuzhiyun #define WM8962_HDBASS_DCY_0 0x421B 753*4882a593Smuzhiyun #define WM8962_HDBASS_PG_1 0x421C 754*4882a593Smuzhiyun #define WM8962_HDBASS_PG_0 0x421D 755*4882a593Smuzhiyun #define WM8962_HPF_C_1 0x4400 756*4882a593Smuzhiyun #define WM8962_HPF_C_0 0x4401 757*4882a593Smuzhiyun #define WM8962_ADCL_RETUNE_C1_1 0x4600 758*4882a593Smuzhiyun #define WM8962_ADCL_RETUNE_C1_0 0x4601 759*4882a593Smuzhiyun #define WM8962_ADCL_RETUNE_C2_1 0x4602 760*4882a593Smuzhiyun #define WM8962_ADCL_RETUNE_C2_0 0x4603 761*4882a593Smuzhiyun #define WM8962_ADCL_RETUNE_C3_1 0x4604 762*4882a593Smuzhiyun #define WM8962_ADCL_RETUNE_C3_0 0x4605 763*4882a593Smuzhiyun #define WM8962_ADCL_RETUNE_C4_1 0x4606 764*4882a593Smuzhiyun #define WM8962_ADCL_RETUNE_C4_0 0x4607 765*4882a593Smuzhiyun #define WM8962_ADCL_RETUNE_C5_1 0x4608 766*4882a593Smuzhiyun #define WM8962_ADCL_RETUNE_C5_0 0x4609 767*4882a593Smuzhiyun #define WM8962_ADCL_RETUNE_C6_1 0x460A 768*4882a593Smuzhiyun #define WM8962_ADCL_RETUNE_C6_0 0x460B 769*4882a593Smuzhiyun #define WM8962_ADCL_RETUNE_C7_1 0x460C 770*4882a593Smuzhiyun #define WM8962_ADCL_RETUNE_C7_0 0x460D 771*4882a593Smuzhiyun #define WM8962_ADCL_RETUNE_C8_1 0x460E 772*4882a593Smuzhiyun #define WM8962_ADCL_RETUNE_C8_0 0x460F 773*4882a593Smuzhiyun #define WM8962_ADCL_RETUNE_C9_1 0x4610 774*4882a593Smuzhiyun #define WM8962_ADCL_RETUNE_C9_0 0x4611 775*4882a593Smuzhiyun #define WM8962_ADCL_RETUNE_C10_1 0x4612 776*4882a593Smuzhiyun #define WM8962_ADCL_RETUNE_C10_0 0x4613 777*4882a593Smuzhiyun #define WM8962_ADCL_RETUNE_C11_1 0x4614 778*4882a593Smuzhiyun #define WM8962_ADCL_RETUNE_C11_0 0x4615 779*4882a593Smuzhiyun #define WM8962_ADCL_RETUNE_C12_1 0x4616 780*4882a593Smuzhiyun #define WM8962_ADCL_RETUNE_C12_0 0x4617 781*4882a593Smuzhiyun #define WM8962_ADCL_RETUNE_C13_1 0x4618 782*4882a593Smuzhiyun #define WM8962_ADCL_RETUNE_C13_0 0x4619 783*4882a593Smuzhiyun #define WM8962_ADCL_RETUNE_C14_1 0x461A 784*4882a593Smuzhiyun #define WM8962_ADCL_RETUNE_C14_0 0x461B 785*4882a593Smuzhiyun #define WM8962_ADCL_RETUNE_C15_1 0x461C 786*4882a593Smuzhiyun #define WM8962_ADCL_RETUNE_C15_0 0x461D 787*4882a593Smuzhiyun #define WM8962_ADCL_RETUNE_C16_1 0x461E 788*4882a593Smuzhiyun #define WM8962_ADCL_RETUNE_C16_0 0x461F 789*4882a593Smuzhiyun #define WM8962_ADCL_RETUNE_C17_1 0x4620 790*4882a593Smuzhiyun #define WM8962_ADCL_RETUNE_C17_0 0x4621 791*4882a593Smuzhiyun #define WM8962_ADCL_RETUNE_C18_1 0x4622 792*4882a593Smuzhiyun #define WM8962_ADCL_RETUNE_C18_0 0x4623 793*4882a593Smuzhiyun #define WM8962_ADCL_RETUNE_C19_1 0x4624 794*4882a593Smuzhiyun #define WM8962_ADCL_RETUNE_C19_0 0x4625 795*4882a593Smuzhiyun #define WM8962_ADCL_RETUNE_C20_1 0x4626 796*4882a593Smuzhiyun #define WM8962_ADCL_RETUNE_C20_0 0x4627 797*4882a593Smuzhiyun #define WM8962_ADCL_RETUNE_C21_1 0x4628 798*4882a593Smuzhiyun #define WM8962_ADCL_RETUNE_C21_0 0x4629 799*4882a593Smuzhiyun #define WM8962_ADCL_RETUNE_C22_1 0x462A 800*4882a593Smuzhiyun #define WM8962_ADCL_RETUNE_C22_0 0x462B 801*4882a593Smuzhiyun #define WM8962_ADCL_RETUNE_C23_1 0x462C 802*4882a593Smuzhiyun #define WM8962_ADCL_RETUNE_C23_0 0x462D 803*4882a593Smuzhiyun #define WM8962_ADCL_RETUNE_C24_1 0x462E 804*4882a593Smuzhiyun #define WM8962_ADCL_RETUNE_C24_0 0x462F 805*4882a593Smuzhiyun #define WM8962_ADCL_RETUNE_C25_1 0x4630 806*4882a593Smuzhiyun #define WM8962_ADCL_RETUNE_C25_0 0x4631 807*4882a593Smuzhiyun #define WM8962_ADCL_RETUNE_C26_1 0x4632 808*4882a593Smuzhiyun #define WM8962_ADCL_RETUNE_C26_0 0x4633 809*4882a593Smuzhiyun #define WM8962_ADCL_RETUNE_C27_1 0x4634 810*4882a593Smuzhiyun #define WM8962_ADCL_RETUNE_C27_0 0x4635 811*4882a593Smuzhiyun #define WM8962_ADCL_RETUNE_C28_1 0x4636 812*4882a593Smuzhiyun #define WM8962_ADCL_RETUNE_C28_0 0x4637 813*4882a593Smuzhiyun #define WM8962_ADCL_RETUNE_C29_1 0x4638 814*4882a593Smuzhiyun #define WM8962_ADCL_RETUNE_C29_0 0x4639 815*4882a593Smuzhiyun #define WM8962_ADCL_RETUNE_C30_1 0x463A 816*4882a593Smuzhiyun #define WM8962_ADCL_RETUNE_C30_0 0x463B 817*4882a593Smuzhiyun #define WM8962_ADCL_RETUNE_C31_1 0x463C 818*4882a593Smuzhiyun #define WM8962_ADCL_RETUNE_C31_0 0x463D 819*4882a593Smuzhiyun #define WM8962_ADCL_RETUNE_C32_1 0x463E 820*4882a593Smuzhiyun #define WM8962_ADCL_RETUNE_C32_0 0x463F 821*4882a593Smuzhiyun #define WM8962_RETUNEADC_PG2_1 0x4800 822*4882a593Smuzhiyun #define WM8962_RETUNEADC_PG2_0 0x4801 823*4882a593Smuzhiyun #define WM8962_RETUNEADC_PG_1 0x4802 824*4882a593Smuzhiyun #define WM8962_RETUNEADC_PG_0 0x4803 825*4882a593Smuzhiyun #define WM8962_ADCR_RETUNE_C1_1 0x4A00 826*4882a593Smuzhiyun #define WM8962_ADCR_RETUNE_C1_0 0x4A01 827*4882a593Smuzhiyun #define WM8962_ADCR_RETUNE_C2_1 0x4A02 828*4882a593Smuzhiyun #define WM8962_ADCR_RETUNE_C2_0 0x4A03 829*4882a593Smuzhiyun #define WM8962_ADCR_RETUNE_C3_1 0x4A04 830*4882a593Smuzhiyun #define WM8962_ADCR_RETUNE_C3_0 0x4A05 831*4882a593Smuzhiyun #define WM8962_ADCR_RETUNE_C4_1 0x4A06 832*4882a593Smuzhiyun #define WM8962_ADCR_RETUNE_C4_0 0x4A07 833*4882a593Smuzhiyun #define WM8962_ADCR_RETUNE_C5_1 0x4A08 834*4882a593Smuzhiyun #define WM8962_ADCR_RETUNE_C5_0 0x4A09 835*4882a593Smuzhiyun #define WM8962_ADCR_RETUNE_C6_1 0x4A0A 836*4882a593Smuzhiyun #define WM8962_ADCR_RETUNE_C6_0 0x4A0B 837*4882a593Smuzhiyun #define WM8962_ADCR_RETUNE_C7_1 0x4A0C 838*4882a593Smuzhiyun #define WM8962_ADCR_RETUNE_C7_0 0x4A0D 839*4882a593Smuzhiyun #define WM8962_ADCR_RETUNE_C8_1 0x4A0E 840*4882a593Smuzhiyun #define WM8962_ADCR_RETUNE_C8_0 0x4A0F 841*4882a593Smuzhiyun #define WM8962_ADCR_RETUNE_C9_1 0x4A10 842*4882a593Smuzhiyun #define WM8962_ADCR_RETUNE_C9_0 0x4A11 843*4882a593Smuzhiyun #define WM8962_ADCR_RETUNE_C10_1 0x4A12 844*4882a593Smuzhiyun #define WM8962_ADCR_RETUNE_C10_0 0x4A13 845*4882a593Smuzhiyun #define WM8962_ADCR_RETUNE_C11_1 0x4A14 846*4882a593Smuzhiyun #define WM8962_ADCR_RETUNE_C11_0 0x4A15 847*4882a593Smuzhiyun #define WM8962_ADCR_RETUNE_C12_1 0x4A16 848*4882a593Smuzhiyun #define WM8962_ADCR_RETUNE_C12_0 0x4A17 849*4882a593Smuzhiyun #define WM8962_ADCR_RETUNE_C13_1 0x4A18 850*4882a593Smuzhiyun #define WM8962_ADCR_RETUNE_C13_0 0x4A19 851*4882a593Smuzhiyun #define WM8962_ADCR_RETUNE_C14_1 0x4A1A 852*4882a593Smuzhiyun #define WM8962_ADCR_RETUNE_C14_0 0x4A1B 853*4882a593Smuzhiyun #define WM8962_ADCR_RETUNE_C15_1 0x4A1C 854*4882a593Smuzhiyun #define WM8962_ADCR_RETUNE_C15_0 0x4A1D 855*4882a593Smuzhiyun #define WM8962_ADCR_RETUNE_C16_1 0x4A1E 856*4882a593Smuzhiyun #define WM8962_ADCR_RETUNE_C16_0 0x4A1F 857*4882a593Smuzhiyun #define WM8962_ADCR_RETUNE_C17_1 0x4A20 858*4882a593Smuzhiyun #define WM8962_ADCR_RETUNE_C17_0 0x4A21 859*4882a593Smuzhiyun #define WM8962_ADCR_RETUNE_C18_1 0x4A22 860*4882a593Smuzhiyun #define WM8962_ADCR_RETUNE_C18_0 0x4A23 861*4882a593Smuzhiyun #define WM8962_ADCR_RETUNE_C19_1 0x4A24 862*4882a593Smuzhiyun #define WM8962_ADCR_RETUNE_C19_0 0x4A25 863*4882a593Smuzhiyun #define WM8962_ADCR_RETUNE_C20_1 0x4A26 864*4882a593Smuzhiyun #define WM8962_ADCR_RETUNE_C20_0 0x4A27 865*4882a593Smuzhiyun #define WM8962_ADCR_RETUNE_C21_1 0x4A28 866*4882a593Smuzhiyun #define WM8962_ADCR_RETUNE_C21_0 0x4A29 867*4882a593Smuzhiyun #define WM8962_ADCR_RETUNE_C22_1 0x4A2A 868*4882a593Smuzhiyun #define WM8962_ADCR_RETUNE_C22_0 0x4A2B 869*4882a593Smuzhiyun #define WM8962_ADCR_RETUNE_C23_1 0x4A2C 870*4882a593Smuzhiyun #define WM8962_ADCR_RETUNE_C23_0 0x4A2D 871*4882a593Smuzhiyun #define WM8962_ADCR_RETUNE_C24_1 0x4A2E 872*4882a593Smuzhiyun #define WM8962_ADCR_RETUNE_C24_0 0x4A2F 873*4882a593Smuzhiyun #define WM8962_ADCR_RETUNE_C25_1 0x4A30 874*4882a593Smuzhiyun #define WM8962_ADCR_RETUNE_C25_0 0x4A31 875*4882a593Smuzhiyun #define WM8962_ADCR_RETUNE_C26_1 0x4A32 876*4882a593Smuzhiyun #define WM8962_ADCR_RETUNE_C26_0 0x4A33 877*4882a593Smuzhiyun #define WM8962_ADCR_RETUNE_C27_1 0x4A34 878*4882a593Smuzhiyun #define WM8962_ADCR_RETUNE_C27_0 0x4A35 879*4882a593Smuzhiyun #define WM8962_ADCR_RETUNE_C28_1 0x4A36 880*4882a593Smuzhiyun #define WM8962_ADCR_RETUNE_C28_0 0x4A37 881*4882a593Smuzhiyun #define WM8962_ADCR_RETUNE_C29_1 0x4A38 882*4882a593Smuzhiyun #define WM8962_ADCR_RETUNE_C29_0 0x4A39 883*4882a593Smuzhiyun #define WM8962_ADCR_RETUNE_C30_1 0x4A3A 884*4882a593Smuzhiyun #define WM8962_ADCR_RETUNE_C30_0 0x4A3B 885*4882a593Smuzhiyun #define WM8962_ADCR_RETUNE_C31_1 0x4A3C 886*4882a593Smuzhiyun #define WM8962_ADCR_RETUNE_C31_0 0x4A3D 887*4882a593Smuzhiyun #define WM8962_ADCR_RETUNE_C32_1 0x4A3E 888*4882a593Smuzhiyun #define WM8962_ADCR_RETUNE_C32_0 0x4A3F 889*4882a593Smuzhiyun #define WM8962_DACL_RETUNE_C1_1 0x4C00 890*4882a593Smuzhiyun #define WM8962_DACL_RETUNE_C1_0 0x4C01 891*4882a593Smuzhiyun #define WM8962_DACL_RETUNE_C2_1 0x4C02 892*4882a593Smuzhiyun #define WM8962_DACL_RETUNE_C2_0 0x4C03 893*4882a593Smuzhiyun #define WM8962_DACL_RETUNE_C3_1 0x4C04 894*4882a593Smuzhiyun #define WM8962_DACL_RETUNE_C3_0 0x4C05 895*4882a593Smuzhiyun #define WM8962_DACL_RETUNE_C4_1 0x4C06 896*4882a593Smuzhiyun #define WM8962_DACL_RETUNE_C4_0 0x4C07 897*4882a593Smuzhiyun #define WM8962_DACL_RETUNE_C5_1 0x4C08 898*4882a593Smuzhiyun #define WM8962_DACL_RETUNE_C5_0 0x4C09 899*4882a593Smuzhiyun #define WM8962_DACL_RETUNE_C6_1 0x4C0A 900*4882a593Smuzhiyun #define WM8962_DACL_RETUNE_C6_0 0x4C0B 901*4882a593Smuzhiyun #define WM8962_DACL_RETUNE_C7_1 0x4C0C 902*4882a593Smuzhiyun #define WM8962_DACL_RETUNE_C7_0 0x4C0D 903*4882a593Smuzhiyun #define WM8962_DACL_RETUNE_C8_1 0x4C0E 904*4882a593Smuzhiyun #define WM8962_DACL_RETUNE_C8_0 0x4C0F 905*4882a593Smuzhiyun #define WM8962_DACL_RETUNE_C9_1 0x4C10 906*4882a593Smuzhiyun #define WM8962_DACL_RETUNE_C9_0 0x4C11 907*4882a593Smuzhiyun #define WM8962_DACL_RETUNE_C10_1 0x4C12 908*4882a593Smuzhiyun #define WM8962_DACL_RETUNE_C10_0 0x4C13 909*4882a593Smuzhiyun #define WM8962_DACL_RETUNE_C11_1 0x4C14 910*4882a593Smuzhiyun #define WM8962_DACL_RETUNE_C11_0 0x4C15 911*4882a593Smuzhiyun #define WM8962_DACL_RETUNE_C12_1 0x4C16 912*4882a593Smuzhiyun #define WM8962_DACL_RETUNE_C12_0 0x4C17 913*4882a593Smuzhiyun #define WM8962_DACL_RETUNE_C13_1 0x4C18 914*4882a593Smuzhiyun #define WM8962_DACL_RETUNE_C13_0 0x4C19 915*4882a593Smuzhiyun #define WM8962_DACL_RETUNE_C14_1 0x4C1A 916*4882a593Smuzhiyun #define WM8962_DACL_RETUNE_C14_0 0x4C1B 917*4882a593Smuzhiyun #define WM8962_DACL_RETUNE_C15_1 0x4C1C 918*4882a593Smuzhiyun #define WM8962_DACL_RETUNE_C15_0 0x4C1D 919*4882a593Smuzhiyun #define WM8962_DACL_RETUNE_C16_1 0x4C1E 920*4882a593Smuzhiyun #define WM8962_DACL_RETUNE_C16_0 0x4C1F 921*4882a593Smuzhiyun #define WM8962_DACL_RETUNE_C17_1 0x4C20 922*4882a593Smuzhiyun #define WM8962_DACL_RETUNE_C17_0 0x4C21 923*4882a593Smuzhiyun #define WM8962_DACL_RETUNE_C18_1 0x4C22 924*4882a593Smuzhiyun #define WM8962_DACL_RETUNE_C18_0 0x4C23 925*4882a593Smuzhiyun #define WM8962_DACL_RETUNE_C19_1 0x4C24 926*4882a593Smuzhiyun #define WM8962_DACL_RETUNE_C19_0 0x4C25 927*4882a593Smuzhiyun #define WM8962_DACL_RETUNE_C20_1 0x4C26 928*4882a593Smuzhiyun #define WM8962_DACL_RETUNE_C20_0 0x4C27 929*4882a593Smuzhiyun #define WM8962_DACL_RETUNE_C21_1 0x4C28 930*4882a593Smuzhiyun #define WM8962_DACL_RETUNE_C21_0 0x4C29 931*4882a593Smuzhiyun #define WM8962_DACL_RETUNE_C22_1 0x4C2A 932*4882a593Smuzhiyun #define WM8962_DACL_RETUNE_C22_0 0x4C2B 933*4882a593Smuzhiyun #define WM8962_DACL_RETUNE_C23_1 0x4C2C 934*4882a593Smuzhiyun #define WM8962_DACL_RETUNE_C23_0 0x4C2D 935*4882a593Smuzhiyun #define WM8962_DACL_RETUNE_C24_1 0x4C2E 936*4882a593Smuzhiyun #define WM8962_DACL_RETUNE_C24_0 0x4C2F 937*4882a593Smuzhiyun #define WM8962_DACL_RETUNE_C25_1 0x4C30 938*4882a593Smuzhiyun #define WM8962_DACL_RETUNE_C25_0 0x4C31 939*4882a593Smuzhiyun #define WM8962_DACL_RETUNE_C26_1 0x4C32 940*4882a593Smuzhiyun #define WM8962_DACL_RETUNE_C26_0 0x4C33 941*4882a593Smuzhiyun #define WM8962_DACL_RETUNE_C27_1 0x4C34 942*4882a593Smuzhiyun #define WM8962_DACL_RETUNE_C27_0 0x4C35 943*4882a593Smuzhiyun #define WM8962_DACL_RETUNE_C28_1 0x4C36 944*4882a593Smuzhiyun #define WM8962_DACL_RETUNE_C28_0 0x4C37 945*4882a593Smuzhiyun #define WM8962_DACL_RETUNE_C29_1 0x4C38 946*4882a593Smuzhiyun #define WM8962_DACL_RETUNE_C29_0 0x4C39 947*4882a593Smuzhiyun #define WM8962_DACL_RETUNE_C30_1 0x4C3A 948*4882a593Smuzhiyun #define WM8962_DACL_RETUNE_C30_0 0x4C3B 949*4882a593Smuzhiyun #define WM8962_DACL_RETUNE_C31_1 0x4C3C 950*4882a593Smuzhiyun #define WM8962_DACL_RETUNE_C31_0 0x4C3D 951*4882a593Smuzhiyun #define WM8962_DACL_RETUNE_C32_1 0x4C3E 952*4882a593Smuzhiyun #define WM8962_DACL_RETUNE_C32_0 0x4C3F 953*4882a593Smuzhiyun #define WM8962_RETUNEDAC_PG2_1 0x4E00 954*4882a593Smuzhiyun #define WM8962_RETUNEDAC_PG2_0 0x4E01 955*4882a593Smuzhiyun #define WM8962_RETUNEDAC_PG_1 0x4E02 956*4882a593Smuzhiyun #define WM8962_RETUNEDAC_PG_0 0x4E03 957*4882a593Smuzhiyun #define WM8962_DACR_RETUNE_C1_1 0x5000 958*4882a593Smuzhiyun #define WM8962_DACR_RETUNE_C1_0 0x5001 959*4882a593Smuzhiyun #define WM8962_DACR_RETUNE_C2_1 0x5002 960*4882a593Smuzhiyun #define WM8962_DACR_RETUNE_C2_0 0x5003 961*4882a593Smuzhiyun #define WM8962_DACR_RETUNE_C3_1 0x5004 962*4882a593Smuzhiyun #define WM8962_DACR_RETUNE_C3_0 0x5005 963*4882a593Smuzhiyun #define WM8962_DACR_RETUNE_C4_1 0x5006 964*4882a593Smuzhiyun #define WM8962_DACR_RETUNE_C4_0 0x5007 965*4882a593Smuzhiyun #define WM8962_DACR_RETUNE_C5_1 0x5008 966*4882a593Smuzhiyun #define WM8962_DACR_RETUNE_C5_0 0x5009 967*4882a593Smuzhiyun #define WM8962_DACR_RETUNE_C6_1 0x500A 968*4882a593Smuzhiyun #define WM8962_DACR_RETUNE_C6_0 0x500B 969*4882a593Smuzhiyun #define WM8962_DACR_RETUNE_C7_1 0x500C 970*4882a593Smuzhiyun #define WM8962_DACR_RETUNE_C7_0 0x500D 971*4882a593Smuzhiyun #define WM8962_DACR_RETUNE_C8_1 0x500E 972*4882a593Smuzhiyun #define WM8962_DACR_RETUNE_C8_0 0x500F 973*4882a593Smuzhiyun #define WM8962_DACR_RETUNE_C9_1 0x5010 974*4882a593Smuzhiyun #define WM8962_DACR_RETUNE_C9_0 0x5011 975*4882a593Smuzhiyun #define WM8962_DACR_RETUNE_C10_1 0x5012 976*4882a593Smuzhiyun #define WM8962_DACR_RETUNE_C10_0 0x5013 977*4882a593Smuzhiyun #define WM8962_DACR_RETUNE_C11_1 0x5014 978*4882a593Smuzhiyun #define WM8962_DACR_RETUNE_C11_0 0x5015 979*4882a593Smuzhiyun #define WM8962_DACR_RETUNE_C12_1 0x5016 980*4882a593Smuzhiyun #define WM8962_DACR_RETUNE_C12_0 0x5017 981*4882a593Smuzhiyun #define WM8962_DACR_RETUNE_C13_1 0x5018 982*4882a593Smuzhiyun #define WM8962_DACR_RETUNE_C13_0 0x5019 983*4882a593Smuzhiyun #define WM8962_DACR_RETUNE_C14_1 0x501A 984*4882a593Smuzhiyun #define WM8962_DACR_RETUNE_C14_0 0x501B 985*4882a593Smuzhiyun #define WM8962_DACR_RETUNE_C15_1 0x501C 986*4882a593Smuzhiyun #define WM8962_DACR_RETUNE_C15_0 0x501D 987*4882a593Smuzhiyun #define WM8962_DACR_RETUNE_C16_1 0x501E 988*4882a593Smuzhiyun #define WM8962_DACR_RETUNE_C16_0 0x501F 989*4882a593Smuzhiyun #define WM8962_DACR_RETUNE_C17_1 0x5020 990*4882a593Smuzhiyun #define WM8962_DACR_RETUNE_C17_0 0x5021 991*4882a593Smuzhiyun #define WM8962_DACR_RETUNE_C18_1 0x5022 992*4882a593Smuzhiyun #define WM8962_DACR_RETUNE_C18_0 0x5023 993*4882a593Smuzhiyun #define WM8962_DACR_RETUNE_C19_1 0x5024 994*4882a593Smuzhiyun #define WM8962_DACR_RETUNE_C19_0 0x5025 995*4882a593Smuzhiyun #define WM8962_DACR_RETUNE_C20_1 0x5026 996*4882a593Smuzhiyun #define WM8962_DACR_RETUNE_C20_0 0x5027 997*4882a593Smuzhiyun #define WM8962_DACR_RETUNE_C21_1 0x5028 998*4882a593Smuzhiyun #define WM8962_DACR_RETUNE_C21_0 0x5029 999*4882a593Smuzhiyun #define WM8962_DACR_RETUNE_C22_1 0x502A 1000*4882a593Smuzhiyun #define WM8962_DACR_RETUNE_C22_0 0x502B 1001*4882a593Smuzhiyun #define WM8962_DACR_RETUNE_C23_1 0x502C 1002*4882a593Smuzhiyun #define WM8962_DACR_RETUNE_C23_0 0x502D 1003*4882a593Smuzhiyun #define WM8962_DACR_RETUNE_C24_1 0x502E 1004*4882a593Smuzhiyun #define WM8962_DACR_RETUNE_C24_0 0x502F 1005*4882a593Smuzhiyun #define WM8962_DACR_RETUNE_C25_1 0x5030 1006*4882a593Smuzhiyun #define WM8962_DACR_RETUNE_C25_0 0x5031 1007*4882a593Smuzhiyun #define WM8962_DACR_RETUNE_C26_1 0x5032 1008*4882a593Smuzhiyun #define WM8962_DACR_RETUNE_C26_0 0x5033 1009*4882a593Smuzhiyun #define WM8962_DACR_RETUNE_C27_1 0x5034 1010*4882a593Smuzhiyun #define WM8962_DACR_RETUNE_C27_0 0x5035 1011*4882a593Smuzhiyun #define WM8962_DACR_RETUNE_C28_1 0x5036 1012*4882a593Smuzhiyun #define WM8962_DACR_RETUNE_C28_0 0x5037 1013*4882a593Smuzhiyun #define WM8962_DACR_RETUNE_C29_1 0x5038 1014*4882a593Smuzhiyun #define WM8962_DACR_RETUNE_C29_0 0x5039 1015*4882a593Smuzhiyun #define WM8962_DACR_RETUNE_C30_1 0x503A 1016*4882a593Smuzhiyun #define WM8962_DACR_RETUNE_C30_0 0x503B 1017*4882a593Smuzhiyun #define WM8962_DACR_RETUNE_C31_1 0x503C 1018*4882a593Smuzhiyun #define WM8962_DACR_RETUNE_C31_0 0x503D 1019*4882a593Smuzhiyun #define WM8962_DACR_RETUNE_C32_1 0x503E 1020*4882a593Smuzhiyun #define WM8962_DACR_RETUNE_C32_0 0x503F 1021*4882a593Smuzhiyun #define WM8962_VSS_XHD2_1 0x5200 1022*4882a593Smuzhiyun #define WM8962_VSS_XHD2_0 0x5201 1023*4882a593Smuzhiyun #define WM8962_VSS_XHD3_1 0x5202 1024*4882a593Smuzhiyun #define WM8962_VSS_XHD3_0 0x5203 1025*4882a593Smuzhiyun #define WM8962_VSS_XHN1_1 0x5204 1026*4882a593Smuzhiyun #define WM8962_VSS_XHN1_0 0x5205 1027*4882a593Smuzhiyun #define WM8962_VSS_XHN2_1 0x5206 1028*4882a593Smuzhiyun #define WM8962_VSS_XHN2_0 0x5207 1029*4882a593Smuzhiyun #define WM8962_VSS_XHN3_1 0x5208 1030*4882a593Smuzhiyun #define WM8962_VSS_XHN3_0 0x5209 1031*4882a593Smuzhiyun #define WM8962_VSS_XLA_1 0x520A 1032*4882a593Smuzhiyun #define WM8962_VSS_XLA_0 0x520B 1033*4882a593Smuzhiyun #define WM8962_VSS_XLB_1 0x520C 1034*4882a593Smuzhiyun #define WM8962_VSS_XLB_0 0x520D 1035*4882a593Smuzhiyun #define WM8962_VSS_XLG_1 0x520E 1036*4882a593Smuzhiyun #define WM8962_VSS_XLG_0 0x520F 1037*4882a593Smuzhiyun #define WM8962_VSS_PG2_1 0x5210 1038*4882a593Smuzhiyun #define WM8962_VSS_PG2_0 0x5211 1039*4882a593Smuzhiyun #define WM8962_VSS_PG_1 0x5212 1040*4882a593Smuzhiyun #define WM8962_VSS_PG_0 0x5213 1041*4882a593Smuzhiyun #define WM8962_VSS_XTD1_1 0x5214 1042*4882a593Smuzhiyun #define WM8962_VSS_XTD1_0 0x5215 1043*4882a593Smuzhiyun #define WM8962_VSS_XTD2_1 0x5216 1044*4882a593Smuzhiyun #define WM8962_VSS_XTD2_0 0x5217 1045*4882a593Smuzhiyun #define WM8962_VSS_XTD3_1 0x5218 1046*4882a593Smuzhiyun #define WM8962_VSS_XTD3_0 0x5219 1047*4882a593Smuzhiyun #define WM8962_VSS_XTD4_1 0x521A 1048*4882a593Smuzhiyun #define WM8962_VSS_XTD4_0 0x521B 1049*4882a593Smuzhiyun #define WM8962_VSS_XTD5_1 0x521C 1050*4882a593Smuzhiyun #define WM8962_VSS_XTD5_0 0x521D 1051*4882a593Smuzhiyun #define WM8962_VSS_XTD6_1 0x521E 1052*4882a593Smuzhiyun #define WM8962_VSS_XTD6_0 0x521F 1053*4882a593Smuzhiyun #define WM8962_VSS_XTD7_1 0x5220 1054*4882a593Smuzhiyun #define WM8962_VSS_XTD7_0 0x5221 1055*4882a593Smuzhiyun #define WM8962_VSS_XTD8_1 0x5222 1056*4882a593Smuzhiyun #define WM8962_VSS_XTD8_0 0x5223 1057*4882a593Smuzhiyun #define WM8962_VSS_XTD9_1 0x5224 1058*4882a593Smuzhiyun #define WM8962_VSS_XTD9_0 0x5225 1059*4882a593Smuzhiyun #define WM8962_VSS_XTD10_1 0x5226 1060*4882a593Smuzhiyun #define WM8962_VSS_XTD10_0 0x5227 1061*4882a593Smuzhiyun #define WM8962_VSS_XTD11_1 0x5228 1062*4882a593Smuzhiyun #define WM8962_VSS_XTD11_0 0x5229 1063*4882a593Smuzhiyun #define WM8962_VSS_XTD12_1 0x522A 1064*4882a593Smuzhiyun #define WM8962_VSS_XTD12_0 0x522B 1065*4882a593Smuzhiyun #define WM8962_VSS_XTD13_1 0x522C 1066*4882a593Smuzhiyun #define WM8962_VSS_XTD13_0 0x522D 1067*4882a593Smuzhiyun #define WM8962_VSS_XTD14_1 0x522E 1068*4882a593Smuzhiyun #define WM8962_VSS_XTD14_0 0x522F 1069*4882a593Smuzhiyun #define WM8962_VSS_XTD15_1 0x5230 1070*4882a593Smuzhiyun #define WM8962_VSS_XTD15_0 0x5231 1071*4882a593Smuzhiyun #define WM8962_VSS_XTD16_1 0x5232 1072*4882a593Smuzhiyun #define WM8962_VSS_XTD16_0 0x5233 1073*4882a593Smuzhiyun #define WM8962_VSS_XTD17_1 0x5234 1074*4882a593Smuzhiyun #define WM8962_VSS_XTD17_0 0x5235 1075*4882a593Smuzhiyun #define WM8962_VSS_XTD18_1 0x5236 1076*4882a593Smuzhiyun #define WM8962_VSS_XTD18_0 0x5237 1077*4882a593Smuzhiyun #define WM8962_VSS_XTD19_1 0x5238 1078*4882a593Smuzhiyun #define WM8962_VSS_XTD19_0 0x5239 1079*4882a593Smuzhiyun #define WM8962_VSS_XTD20_1 0x523A 1080*4882a593Smuzhiyun #define WM8962_VSS_XTD20_0 0x523B 1081*4882a593Smuzhiyun #define WM8962_VSS_XTD21_1 0x523C 1082*4882a593Smuzhiyun #define WM8962_VSS_XTD21_0 0x523D 1083*4882a593Smuzhiyun #define WM8962_VSS_XTD22_1 0x523E 1084*4882a593Smuzhiyun #define WM8962_VSS_XTD22_0 0x523F 1085*4882a593Smuzhiyun #define WM8962_VSS_XTD23_1 0x5240 1086*4882a593Smuzhiyun #define WM8962_VSS_XTD23_0 0x5241 1087*4882a593Smuzhiyun #define WM8962_VSS_XTD24_1 0x5242 1088*4882a593Smuzhiyun #define WM8962_VSS_XTD24_0 0x5243 1089*4882a593Smuzhiyun #define WM8962_VSS_XTD25_1 0x5244 1090*4882a593Smuzhiyun #define WM8962_VSS_XTD25_0 0x5245 1091*4882a593Smuzhiyun #define WM8962_VSS_XTD26_1 0x5246 1092*4882a593Smuzhiyun #define WM8962_VSS_XTD26_0 0x5247 1093*4882a593Smuzhiyun #define WM8962_VSS_XTD27_1 0x5248 1094*4882a593Smuzhiyun #define WM8962_VSS_XTD27_0 0x5249 1095*4882a593Smuzhiyun #define WM8962_VSS_XTD28_1 0x524A 1096*4882a593Smuzhiyun #define WM8962_VSS_XTD28_0 0x524B 1097*4882a593Smuzhiyun #define WM8962_VSS_XTD29_1 0x524C 1098*4882a593Smuzhiyun #define WM8962_VSS_XTD29_0 0x524D 1099*4882a593Smuzhiyun #define WM8962_VSS_XTD30_1 0x524E 1100*4882a593Smuzhiyun #define WM8962_VSS_XTD30_0 0x524F 1101*4882a593Smuzhiyun #define WM8962_VSS_XTD31_1 0x5250 1102*4882a593Smuzhiyun #define WM8962_VSS_XTD31_0 0x5251 1103*4882a593Smuzhiyun #define WM8962_VSS_XTD32_1 0x5252 1104*4882a593Smuzhiyun #define WM8962_VSS_XTD32_0 0x5253 1105*4882a593Smuzhiyun #define WM8962_VSS_XTS1_1 0x5254 1106*4882a593Smuzhiyun #define WM8962_VSS_XTS1_0 0x5255 1107*4882a593Smuzhiyun #define WM8962_VSS_XTS2_1 0x5256 1108*4882a593Smuzhiyun #define WM8962_VSS_XTS2_0 0x5257 1109*4882a593Smuzhiyun #define WM8962_VSS_XTS3_1 0x5258 1110*4882a593Smuzhiyun #define WM8962_VSS_XTS3_0 0x5259 1111*4882a593Smuzhiyun #define WM8962_VSS_XTS4_1 0x525A 1112*4882a593Smuzhiyun #define WM8962_VSS_XTS4_0 0x525B 1113*4882a593Smuzhiyun #define WM8962_VSS_XTS5_1 0x525C 1114*4882a593Smuzhiyun #define WM8962_VSS_XTS5_0 0x525D 1115*4882a593Smuzhiyun #define WM8962_VSS_XTS6_1 0x525E 1116*4882a593Smuzhiyun #define WM8962_VSS_XTS6_0 0x525F 1117*4882a593Smuzhiyun #define WM8962_VSS_XTS7_1 0x5260 1118*4882a593Smuzhiyun #define WM8962_VSS_XTS7_0 0x5261 1119*4882a593Smuzhiyun #define WM8962_VSS_XTS8_1 0x5262 1120*4882a593Smuzhiyun #define WM8962_VSS_XTS8_0 0x5263 1121*4882a593Smuzhiyun #define WM8962_VSS_XTS9_1 0x5264 1122*4882a593Smuzhiyun #define WM8962_VSS_XTS9_0 0x5265 1123*4882a593Smuzhiyun #define WM8962_VSS_XTS10_1 0x5266 1124*4882a593Smuzhiyun #define WM8962_VSS_XTS10_0 0x5267 1125*4882a593Smuzhiyun #define WM8962_VSS_XTS11_1 0x5268 1126*4882a593Smuzhiyun #define WM8962_VSS_XTS11_0 0x5269 1127*4882a593Smuzhiyun #define WM8962_VSS_XTS12_1 0x526A 1128*4882a593Smuzhiyun #define WM8962_VSS_XTS12_0 0x526B 1129*4882a593Smuzhiyun #define WM8962_VSS_XTS13_1 0x526C 1130*4882a593Smuzhiyun #define WM8962_VSS_XTS13_0 0x526D 1131*4882a593Smuzhiyun #define WM8962_VSS_XTS14_1 0x526E 1132*4882a593Smuzhiyun #define WM8962_VSS_XTS14_0 0x526F 1133*4882a593Smuzhiyun #define WM8962_VSS_XTS15_1 0x5270 1134*4882a593Smuzhiyun #define WM8962_VSS_XTS15_0 0x5271 1135*4882a593Smuzhiyun #define WM8962_VSS_XTS16_1 0x5272 1136*4882a593Smuzhiyun #define WM8962_VSS_XTS16_0 0x5273 1137*4882a593Smuzhiyun #define WM8962_VSS_XTS17_1 0x5274 1138*4882a593Smuzhiyun #define WM8962_VSS_XTS17_0 0x5275 1139*4882a593Smuzhiyun #define WM8962_VSS_XTS18_1 0x5276 1140*4882a593Smuzhiyun #define WM8962_VSS_XTS18_0 0x5277 1141*4882a593Smuzhiyun #define WM8962_VSS_XTS19_1 0x5278 1142*4882a593Smuzhiyun #define WM8962_VSS_XTS19_0 0x5279 1143*4882a593Smuzhiyun #define WM8962_VSS_XTS20_1 0x527A 1144*4882a593Smuzhiyun #define WM8962_VSS_XTS20_0 0x527B 1145*4882a593Smuzhiyun #define WM8962_VSS_XTS21_1 0x527C 1146*4882a593Smuzhiyun #define WM8962_VSS_XTS21_0 0x527D 1147*4882a593Smuzhiyun #define WM8962_VSS_XTS22_1 0x527E 1148*4882a593Smuzhiyun #define WM8962_VSS_XTS22_0 0x527F 1149*4882a593Smuzhiyun #define WM8962_VSS_XTS23_1 0x5280 1150*4882a593Smuzhiyun #define WM8962_VSS_XTS23_0 0x5281 1151*4882a593Smuzhiyun #define WM8962_VSS_XTS24_1 0x5282 1152*4882a593Smuzhiyun #define WM8962_VSS_XTS24_0 0x5283 1153*4882a593Smuzhiyun #define WM8962_VSS_XTS25_1 0x5284 1154*4882a593Smuzhiyun #define WM8962_VSS_XTS25_0 0x5285 1155*4882a593Smuzhiyun #define WM8962_VSS_XTS26_1 0x5286 1156*4882a593Smuzhiyun #define WM8962_VSS_XTS26_0 0x5287 1157*4882a593Smuzhiyun #define WM8962_VSS_XTS27_1 0x5288 1158*4882a593Smuzhiyun #define WM8962_VSS_XTS27_0 0x5289 1159*4882a593Smuzhiyun #define WM8962_VSS_XTS28_1 0x528A 1160*4882a593Smuzhiyun #define WM8962_VSS_XTS28_0 0x528B 1161*4882a593Smuzhiyun #define WM8962_VSS_XTS29_1 0x528C 1162*4882a593Smuzhiyun #define WM8962_VSS_XTS29_0 0x528D 1163*4882a593Smuzhiyun #define WM8962_VSS_XTS30_1 0x528E 1164*4882a593Smuzhiyun #define WM8962_VSS_XTS30_0 0x528F 1165*4882a593Smuzhiyun #define WM8962_VSS_XTS31_1 0x5290 1166*4882a593Smuzhiyun #define WM8962_VSS_XTS31_0 0x5291 1167*4882a593Smuzhiyun #define WM8962_VSS_XTS32_1 0x5292 1168*4882a593Smuzhiyun #define WM8962_VSS_XTS32_0 0x5293 1169*4882a593Smuzhiyun 1170*4882a593Smuzhiyun #define WM8962_REGISTER_COUNT 1138 1171*4882a593Smuzhiyun #define WM8962_MAX_REGISTER 0x5293 1172*4882a593Smuzhiyun 1173*4882a593Smuzhiyun /* 1174*4882a593Smuzhiyun * Field Definitions. 1175*4882a593Smuzhiyun */ 1176*4882a593Smuzhiyun 1177*4882a593Smuzhiyun /* 1178*4882a593Smuzhiyun * R0 (0x00) - Left Input volume 1179*4882a593Smuzhiyun */ 1180*4882a593Smuzhiyun #define WM8962_IN_VU 0x0100 /* IN_VU */ 1181*4882a593Smuzhiyun #define WM8962_IN_VU_MASK 0x0100 /* IN_VU */ 1182*4882a593Smuzhiyun #define WM8962_IN_VU_SHIFT 8 /* IN_VU */ 1183*4882a593Smuzhiyun #define WM8962_IN_VU_WIDTH 1 /* IN_VU */ 1184*4882a593Smuzhiyun #define WM8962_INPGAL_MUTE 0x0080 /* INPGAL_MUTE */ 1185*4882a593Smuzhiyun #define WM8962_INPGAL_MUTE_MASK 0x0080 /* INPGAL_MUTE */ 1186*4882a593Smuzhiyun #define WM8962_INPGAL_MUTE_SHIFT 7 /* INPGAL_MUTE */ 1187*4882a593Smuzhiyun #define WM8962_INPGAL_MUTE_WIDTH 1 /* INPGAL_MUTE */ 1188*4882a593Smuzhiyun #define WM8962_INL_ZC 0x0040 /* INL_ZC */ 1189*4882a593Smuzhiyun #define WM8962_INL_ZC_MASK 0x0040 /* INL_ZC */ 1190*4882a593Smuzhiyun #define WM8962_INL_ZC_SHIFT 6 /* INL_ZC */ 1191*4882a593Smuzhiyun #define WM8962_INL_ZC_WIDTH 1 /* INL_ZC */ 1192*4882a593Smuzhiyun #define WM8962_INL_VOL_MASK 0x003F /* INL_VOL - [5:0] */ 1193*4882a593Smuzhiyun #define WM8962_INL_VOL_SHIFT 0 /* INL_VOL - [5:0] */ 1194*4882a593Smuzhiyun #define WM8962_INL_VOL_WIDTH 6 /* INL_VOL - [5:0] */ 1195*4882a593Smuzhiyun 1196*4882a593Smuzhiyun /* 1197*4882a593Smuzhiyun * R1 (0x01) - Right Input volume 1198*4882a593Smuzhiyun */ 1199*4882a593Smuzhiyun #define WM8962_CUST_ID_MASK 0xF000 /* CUST_ID - [15:12] */ 1200*4882a593Smuzhiyun #define WM8962_CUST_ID_SHIFT 12 /* CUST_ID - [15:12] */ 1201*4882a593Smuzhiyun #define WM8962_CUST_ID_WIDTH 4 /* CUST_ID - [15:12] */ 1202*4882a593Smuzhiyun #define WM8962_CHIP_REV_MASK 0x0E00 /* CHIP_REV - [11:9] */ 1203*4882a593Smuzhiyun #define WM8962_CHIP_REV_SHIFT 9 /* CHIP_REV - [11:9] */ 1204*4882a593Smuzhiyun #define WM8962_CHIP_REV_WIDTH 3 /* CHIP_REV - [11:9] */ 1205*4882a593Smuzhiyun #define WM8962_IN_VU 0x0100 /* IN_VU */ 1206*4882a593Smuzhiyun #define WM8962_IN_VU_MASK 0x0100 /* IN_VU */ 1207*4882a593Smuzhiyun #define WM8962_IN_VU_SHIFT 8 /* IN_VU */ 1208*4882a593Smuzhiyun #define WM8962_IN_VU_WIDTH 1 /* IN_VU */ 1209*4882a593Smuzhiyun #define WM8962_INPGAR_MUTE 0x0080 /* INPGAR_MUTE */ 1210*4882a593Smuzhiyun #define WM8962_INPGAR_MUTE_MASK 0x0080 /* INPGAR_MUTE */ 1211*4882a593Smuzhiyun #define WM8962_INPGAR_MUTE_SHIFT 7 /* INPGAR_MUTE */ 1212*4882a593Smuzhiyun #define WM8962_INPGAR_MUTE_WIDTH 1 /* INPGAR_MUTE */ 1213*4882a593Smuzhiyun #define WM8962_INR_ZC 0x0040 /* INR_ZC */ 1214*4882a593Smuzhiyun #define WM8962_INR_ZC_MASK 0x0040 /* INR_ZC */ 1215*4882a593Smuzhiyun #define WM8962_INR_ZC_SHIFT 6 /* INR_ZC */ 1216*4882a593Smuzhiyun #define WM8962_INR_ZC_WIDTH 1 /* INR_ZC */ 1217*4882a593Smuzhiyun #define WM8962_INR_VOL_MASK 0x003F /* INR_VOL - [5:0] */ 1218*4882a593Smuzhiyun #define WM8962_INR_VOL_SHIFT 0 /* INR_VOL - [5:0] */ 1219*4882a593Smuzhiyun #define WM8962_INR_VOL_WIDTH 6 /* INR_VOL - [5:0] */ 1220*4882a593Smuzhiyun 1221*4882a593Smuzhiyun /* 1222*4882a593Smuzhiyun * R2 (0x02) - HPOUTL volume 1223*4882a593Smuzhiyun */ 1224*4882a593Smuzhiyun #define WM8962_HPOUT_VU 0x0100 /* HPOUT_VU */ 1225*4882a593Smuzhiyun #define WM8962_HPOUT_VU_MASK 0x0100 /* HPOUT_VU */ 1226*4882a593Smuzhiyun #define WM8962_HPOUT_VU_SHIFT 8 /* HPOUT_VU */ 1227*4882a593Smuzhiyun #define WM8962_HPOUT_VU_WIDTH 1 /* HPOUT_VU */ 1228*4882a593Smuzhiyun #define WM8962_HPOUTL_ZC 0x0080 /* HPOUTL_ZC */ 1229*4882a593Smuzhiyun #define WM8962_HPOUTL_ZC_MASK 0x0080 /* HPOUTL_ZC */ 1230*4882a593Smuzhiyun #define WM8962_HPOUTL_ZC_SHIFT 7 /* HPOUTL_ZC */ 1231*4882a593Smuzhiyun #define WM8962_HPOUTL_ZC_WIDTH 1 /* HPOUTL_ZC */ 1232*4882a593Smuzhiyun #define WM8962_HPOUTL_VOL_MASK 0x007F /* HPOUTL_VOL - [6:0] */ 1233*4882a593Smuzhiyun #define WM8962_HPOUTL_VOL_SHIFT 0 /* HPOUTL_VOL - [6:0] */ 1234*4882a593Smuzhiyun #define WM8962_HPOUTL_VOL_WIDTH 7 /* HPOUTL_VOL - [6:0] */ 1235*4882a593Smuzhiyun 1236*4882a593Smuzhiyun /* 1237*4882a593Smuzhiyun * R3 (0x03) - HPOUTR volume 1238*4882a593Smuzhiyun */ 1239*4882a593Smuzhiyun #define WM8962_HPOUT_VU 0x0100 /* HPOUT_VU */ 1240*4882a593Smuzhiyun #define WM8962_HPOUT_VU_MASK 0x0100 /* HPOUT_VU */ 1241*4882a593Smuzhiyun #define WM8962_HPOUT_VU_SHIFT 8 /* HPOUT_VU */ 1242*4882a593Smuzhiyun #define WM8962_HPOUT_VU_WIDTH 1 /* HPOUT_VU */ 1243*4882a593Smuzhiyun #define WM8962_HPOUTR_ZC 0x0080 /* HPOUTR_ZC */ 1244*4882a593Smuzhiyun #define WM8962_HPOUTR_ZC_MASK 0x0080 /* HPOUTR_ZC */ 1245*4882a593Smuzhiyun #define WM8962_HPOUTR_ZC_SHIFT 7 /* HPOUTR_ZC */ 1246*4882a593Smuzhiyun #define WM8962_HPOUTR_ZC_WIDTH 1 /* HPOUTR_ZC */ 1247*4882a593Smuzhiyun #define WM8962_HPOUTR_VOL_MASK 0x007F /* HPOUTR_VOL - [6:0] */ 1248*4882a593Smuzhiyun #define WM8962_HPOUTR_VOL_SHIFT 0 /* HPOUTR_VOL - [6:0] */ 1249*4882a593Smuzhiyun #define WM8962_HPOUTR_VOL_WIDTH 7 /* HPOUTR_VOL - [6:0] */ 1250*4882a593Smuzhiyun 1251*4882a593Smuzhiyun /* 1252*4882a593Smuzhiyun * R4 (0x04) - Clocking1 1253*4882a593Smuzhiyun */ 1254*4882a593Smuzhiyun #define WM8962_DSPCLK_DIV_MASK 0x0600 /* DSPCLK_DIV - [10:9] */ 1255*4882a593Smuzhiyun #define WM8962_DSPCLK_DIV_SHIFT 9 /* DSPCLK_DIV - [10:9] */ 1256*4882a593Smuzhiyun #define WM8962_DSPCLK_DIV_WIDTH 2 /* DSPCLK_DIV - [10:9] */ 1257*4882a593Smuzhiyun #define WM8962_ADCSYS_CLK_DIV_MASK 0x01C0 /* ADCSYS_CLK_DIV - [8:6] */ 1258*4882a593Smuzhiyun #define WM8962_ADCSYS_CLK_DIV_SHIFT 6 /* ADCSYS_CLK_DIV - [8:6] */ 1259*4882a593Smuzhiyun #define WM8962_ADCSYS_CLK_DIV_WIDTH 3 /* ADCSYS_CLK_DIV - [8:6] */ 1260*4882a593Smuzhiyun #define WM8962_DACSYS_CLK_DIV_MASK 0x0038 /* DACSYS_CLK_DIV - [5:3] */ 1261*4882a593Smuzhiyun #define WM8962_DACSYS_CLK_DIV_SHIFT 3 /* DACSYS_CLK_DIV - [5:3] */ 1262*4882a593Smuzhiyun #define WM8962_DACSYS_CLK_DIV_WIDTH 3 /* DACSYS_CLK_DIV - [5:3] */ 1263*4882a593Smuzhiyun #define WM8962_MCLKDIV_MASK 0x0006 /* MCLKDIV - [2:1] */ 1264*4882a593Smuzhiyun #define WM8962_MCLKDIV_SHIFT 1 /* MCLKDIV - [2:1] */ 1265*4882a593Smuzhiyun #define WM8962_MCLKDIV_WIDTH 2 /* MCLKDIV - [2:1] */ 1266*4882a593Smuzhiyun 1267*4882a593Smuzhiyun /* 1268*4882a593Smuzhiyun * R5 (0x05) - ADC & DAC Control 1 1269*4882a593Smuzhiyun */ 1270*4882a593Smuzhiyun #define WM8962_ADCR_DAT_INV 0x0040 /* ADCR_DAT_INV */ 1271*4882a593Smuzhiyun #define WM8962_ADCR_DAT_INV_MASK 0x0040 /* ADCR_DAT_INV */ 1272*4882a593Smuzhiyun #define WM8962_ADCR_DAT_INV_SHIFT 6 /* ADCR_DAT_INV */ 1273*4882a593Smuzhiyun #define WM8962_ADCR_DAT_INV_WIDTH 1 /* ADCR_DAT_INV */ 1274*4882a593Smuzhiyun #define WM8962_ADCL_DAT_INV 0x0020 /* ADCL_DAT_INV */ 1275*4882a593Smuzhiyun #define WM8962_ADCL_DAT_INV_MASK 0x0020 /* ADCL_DAT_INV */ 1276*4882a593Smuzhiyun #define WM8962_ADCL_DAT_INV_SHIFT 5 /* ADCL_DAT_INV */ 1277*4882a593Smuzhiyun #define WM8962_ADCL_DAT_INV_WIDTH 1 /* ADCL_DAT_INV */ 1278*4882a593Smuzhiyun #define WM8962_DAC_MUTE_RAMP 0x0010 /* DAC_MUTE_RAMP */ 1279*4882a593Smuzhiyun #define WM8962_DAC_MUTE_RAMP_MASK 0x0010 /* DAC_MUTE_RAMP */ 1280*4882a593Smuzhiyun #define WM8962_DAC_MUTE_RAMP_SHIFT 4 /* DAC_MUTE_RAMP */ 1281*4882a593Smuzhiyun #define WM8962_DAC_MUTE_RAMP_WIDTH 1 /* DAC_MUTE_RAMP */ 1282*4882a593Smuzhiyun #define WM8962_DAC_MUTE 0x0008 /* DAC_MUTE */ 1283*4882a593Smuzhiyun #define WM8962_DAC_MUTE_MASK 0x0008 /* DAC_MUTE */ 1284*4882a593Smuzhiyun #define WM8962_DAC_MUTE_SHIFT 3 /* DAC_MUTE */ 1285*4882a593Smuzhiyun #define WM8962_DAC_MUTE_WIDTH 1 /* DAC_MUTE */ 1286*4882a593Smuzhiyun #define WM8962_DAC_DEEMP_MASK 0x0006 /* DAC_DEEMP - [2:1] */ 1287*4882a593Smuzhiyun #define WM8962_DAC_DEEMP_SHIFT 1 /* DAC_DEEMP - [2:1] */ 1288*4882a593Smuzhiyun #define WM8962_DAC_DEEMP_WIDTH 2 /* DAC_DEEMP - [2:1] */ 1289*4882a593Smuzhiyun #define WM8962_ADC_HPF_DIS 0x0001 /* ADC_HPF_DIS */ 1290*4882a593Smuzhiyun #define WM8962_ADC_HPF_DIS_MASK 0x0001 /* ADC_HPF_DIS */ 1291*4882a593Smuzhiyun #define WM8962_ADC_HPF_DIS_SHIFT 0 /* ADC_HPF_DIS */ 1292*4882a593Smuzhiyun #define WM8962_ADC_HPF_DIS_WIDTH 1 /* ADC_HPF_DIS */ 1293*4882a593Smuzhiyun 1294*4882a593Smuzhiyun /* 1295*4882a593Smuzhiyun * R6 (0x06) - ADC & DAC Control 2 1296*4882a593Smuzhiyun */ 1297*4882a593Smuzhiyun #define WM8962_ADC_HPF_SR_MASK 0x3000 /* ADC_HPF_SR - [13:12] */ 1298*4882a593Smuzhiyun #define WM8962_ADC_HPF_SR_SHIFT 12 /* ADC_HPF_SR - [13:12] */ 1299*4882a593Smuzhiyun #define WM8962_ADC_HPF_SR_WIDTH 2 /* ADC_HPF_SR - [13:12] */ 1300*4882a593Smuzhiyun #define WM8962_ADC_HPF_MODE 0x0400 /* ADC_HPF_MODE */ 1301*4882a593Smuzhiyun #define WM8962_ADC_HPF_MODE_MASK 0x0400 /* ADC_HPF_MODE */ 1302*4882a593Smuzhiyun #define WM8962_ADC_HPF_MODE_SHIFT 10 /* ADC_HPF_MODE */ 1303*4882a593Smuzhiyun #define WM8962_ADC_HPF_MODE_WIDTH 1 /* ADC_HPF_MODE */ 1304*4882a593Smuzhiyun #define WM8962_ADC_HPF_CUT_MASK 0x0380 /* ADC_HPF_CUT - [9:7] */ 1305*4882a593Smuzhiyun #define WM8962_ADC_HPF_CUT_SHIFT 7 /* ADC_HPF_CUT - [9:7] */ 1306*4882a593Smuzhiyun #define WM8962_ADC_HPF_CUT_WIDTH 3 /* ADC_HPF_CUT - [9:7] */ 1307*4882a593Smuzhiyun #define WM8962_DACR_DAT_INV 0x0040 /* DACR_DAT_INV */ 1308*4882a593Smuzhiyun #define WM8962_DACR_DAT_INV_MASK 0x0040 /* DACR_DAT_INV */ 1309*4882a593Smuzhiyun #define WM8962_DACR_DAT_INV_SHIFT 6 /* DACR_DAT_INV */ 1310*4882a593Smuzhiyun #define WM8962_DACR_DAT_INV_WIDTH 1 /* DACR_DAT_INV */ 1311*4882a593Smuzhiyun #define WM8962_DACL_DAT_INV 0x0020 /* DACL_DAT_INV */ 1312*4882a593Smuzhiyun #define WM8962_DACL_DAT_INV_MASK 0x0020 /* DACL_DAT_INV */ 1313*4882a593Smuzhiyun #define WM8962_DACL_DAT_INV_SHIFT 5 /* DACL_DAT_INV */ 1314*4882a593Smuzhiyun #define WM8962_DACL_DAT_INV_WIDTH 1 /* DACL_DAT_INV */ 1315*4882a593Smuzhiyun #define WM8962_DAC_UNMUTE_RAMP 0x0008 /* DAC_UNMUTE_RAMP */ 1316*4882a593Smuzhiyun #define WM8962_DAC_UNMUTE_RAMP_MASK 0x0008 /* DAC_UNMUTE_RAMP */ 1317*4882a593Smuzhiyun #define WM8962_DAC_UNMUTE_RAMP_SHIFT 3 /* DAC_UNMUTE_RAMP */ 1318*4882a593Smuzhiyun #define WM8962_DAC_UNMUTE_RAMP_WIDTH 1 /* DAC_UNMUTE_RAMP */ 1319*4882a593Smuzhiyun #define WM8962_DAC_MUTERATE 0x0004 /* DAC_MUTERATE */ 1320*4882a593Smuzhiyun #define WM8962_DAC_MUTERATE_MASK 0x0004 /* DAC_MUTERATE */ 1321*4882a593Smuzhiyun #define WM8962_DAC_MUTERATE_SHIFT 2 /* DAC_MUTERATE */ 1322*4882a593Smuzhiyun #define WM8962_DAC_MUTERATE_WIDTH 1 /* DAC_MUTERATE */ 1323*4882a593Smuzhiyun #define WM8962_DAC_HP 0x0001 /* DAC_HP */ 1324*4882a593Smuzhiyun #define WM8962_DAC_HP_MASK 0x0001 /* DAC_HP */ 1325*4882a593Smuzhiyun #define WM8962_DAC_HP_SHIFT 0 /* DAC_HP */ 1326*4882a593Smuzhiyun #define WM8962_DAC_HP_WIDTH 1 /* DAC_HP */ 1327*4882a593Smuzhiyun 1328*4882a593Smuzhiyun /* 1329*4882a593Smuzhiyun * R7 (0x07) - Audio Interface 0 1330*4882a593Smuzhiyun */ 1331*4882a593Smuzhiyun #define WM8962_AIFDAC_TDM_MODE 0x1000 /* AIFDAC_TDM_MODE */ 1332*4882a593Smuzhiyun #define WM8962_AIFDAC_TDM_MODE_MASK 0x1000 /* AIFDAC_TDM_MODE */ 1333*4882a593Smuzhiyun #define WM8962_AIFDAC_TDM_MODE_SHIFT 12 /* AIFDAC_TDM_MODE */ 1334*4882a593Smuzhiyun #define WM8962_AIFDAC_TDM_MODE_WIDTH 1 /* AIFDAC_TDM_MODE */ 1335*4882a593Smuzhiyun #define WM8962_AIFDAC_TDM_SLOT 0x0800 /* AIFDAC_TDM_SLOT */ 1336*4882a593Smuzhiyun #define WM8962_AIFDAC_TDM_SLOT_MASK 0x0800 /* AIFDAC_TDM_SLOT */ 1337*4882a593Smuzhiyun #define WM8962_AIFDAC_TDM_SLOT_SHIFT 11 /* AIFDAC_TDM_SLOT */ 1338*4882a593Smuzhiyun #define WM8962_AIFDAC_TDM_SLOT_WIDTH 1 /* AIFDAC_TDM_SLOT */ 1339*4882a593Smuzhiyun #define WM8962_AIFADC_TDM_MODE 0x0400 /* AIFADC_TDM_MODE */ 1340*4882a593Smuzhiyun #define WM8962_AIFADC_TDM_MODE_MASK 0x0400 /* AIFADC_TDM_MODE */ 1341*4882a593Smuzhiyun #define WM8962_AIFADC_TDM_MODE_SHIFT 10 /* AIFADC_TDM_MODE */ 1342*4882a593Smuzhiyun #define WM8962_AIFADC_TDM_MODE_WIDTH 1 /* AIFADC_TDM_MODE */ 1343*4882a593Smuzhiyun #define WM8962_AIFADC_TDM_SLOT 0x0200 /* AIFADC_TDM_SLOT */ 1344*4882a593Smuzhiyun #define WM8962_AIFADC_TDM_SLOT_MASK 0x0200 /* AIFADC_TDM_SLOT */ 1345*4882a593Smuzhiyun #define WM8962_AIFADC_TDM_SLOT_SHIFT 9 /* AIFADC_TDM_SLOT */ 1346*4882a593Smuzhiyun #define WM8962_AIFADC_TDM_SLOT_WIDTH 1 /* AIFADC_TDM_SLOT */ 1347*4882a593Smuzhiyun #define WM8962_ADC_LRSWAP 0x0100 /* ADC_LRSWAP */ 1348*4882a593Smuzhiyun #define WM8962_ADC_LRSWAP_MASK 0x0100 /* ADC_LRSWAP */ 1349*4882a593Smuzhiyun #define WM8962_ADC_LRSWAP_SHIFT 8 /* ADC_LRSWAP */ 1350*4882a593Smuzhiyun #define WM8962_ADC_LRSWAP_WIDTH 1 /* ADC_LRSWAP */ 1351*4882a593Smuzhiyun #define WM8962_BCLK_INV 0x0080 /* BCLK_INV */ 1352*4882a593Smuzhiyun #define WM8962_BCLK_INV_MASK 0x0080 /* BCLK_INV */ 1353*4882a593Smuzhiyun #define WM8962_BCLK_INV_SHIFT 7 /* BCLK_INV */ 1354*4882a593Smuzhiyun #define WM8962_BCLK_INV_WIDTH 1 /* BCLK_INV */ 1355*4882a593Smuzhiyun #define WM8962_MSTR 0x0040 /* MSTR */ 1356*4882a593Smuzhiyun #define WM8962_MSTR_MASK 0x0040 /* MSTR */ 1357*4882a593Smuzhiyun #define WM8962_MSTR_SHIFT 6 /* MSTR */ 1358*4882a593Smuzhiyun #define WM8962_MSTR_WIDTH 1 /* MSTR */ 1359*4882a593Smuzhiyun #define WM8962_DAC_LRSWAP 0x0020 /* DAC_LRSWAP */ 1360*4882a593Smuzhiyun #define WM8962_DAC_LRSWAP_MASK 0x0020 /* DAC_LRSWAP */ 1361*4882a593Smuzhiyun #define WM8962_DAC_LRSWAP_SHIFT 5 /* DAC_LRSWAP */ 1362*4882a593Smuzhiyun #define WM8962_DAC_LRSWAP_WIDTH 1 /* DAC_LRSWAP */ 1363*4882a593Smuzhiyun #define WM8962_LRCLK_INV 0x0010 /* LRCLK_INV */ 1364*4882a593Smuzhiyun #define WM8962_LRCLK_INV_MASK 0x0010 /* LRCLK_INV */ 1365*4882a593Smuzhiyun #define WM8962_LRCLK_INV_SHIFT 4 /* LRCLK_INV */ 1366*4882a593Smuzhiyun #define WM8962_LRCLK_INV_WIDTH 1 /* LRCLK_INV */ 1367*4882a593Smuzhiyun #define WM8962_WL_MASK 0x000C /* WL - [3:2] */ 1368*4882a593Smuzhiyun #define WM8962_WL_SHIFT 2 /* WL - [3:2] */ 1369*4882a593Smuzhiyun #define WM8962_WL_WIDTH 2 /* WL - [3:2] */ 1370*4882a593Smuzhiyun #define WM8962_FMT_MASK 0x0003 /* FMT - [1:0] */ 1371*4882a593Smuzhiyun #define WM8962_FMT_SHIFT 0 /* FMT - [1:0] */ 1372*4882a593Smuzhiyun #define WM8962_FMT_WIDTH 2 /* FMT - [1:0] */ 1373*4882a593Smuzhiyun 1374*4882a593Smuzhiyun /* 1375*4882a593Smuzhiyun * R8 (0x08) - Clocking2 1376*4882a593Smuzhiyun */ 1377*4882a593Smuzhiyun #define WM8962_CLKREG_OVD 0x0800 /* CLKREG_OVD */ 1378*4882a593Smuzhiyun #define WM8962_CLKREG_OVD_MASK 0x0800 /* CLKREG_OVD */ 1379*4882a593Smuzhiyun #define WM8962_CLKREG_OVD_SHIFT 11 /* CLKREG_OVD */ 1380*4882a593Smuzhiyun #define WM8962_CLKREG_OVD_WIDTH 1 /* CLKREG_OVD */ 1381*4882a593Smuzhiyun #define WM8962_SYSCLK_SRC_MASK 0x0600 /* SYSCLK_SRC - [10:9] */ 1382*4882a593Smuzhiyun #define WM8962_SYSCLK_SRC_SHIFT 9 /* SYSCLK_SRC - [10:9] */ 1383*4882a593Smuzhiyun #define WM8962_SYSCLK_SRC_WIDTH 2 /* SYSCLK_SRC - [10:9] */ 1384*4882a593Smuzhiyun #define WM8962_CLASSD_CLK_DIV_MASK 0x01C0 /* CLASSD_CLK_DIV - [8:6] */ 1385*4882a593Smuzhiyun #define WM8962_CLASSD_CLK_DIV_SHIFT 6 /* CLASSD_CLK_DIV - [8:6] */ 1386*4882a593Smuzhiyun #define WM8962_CLASSD_CLK_DIV_WIDTH 3 /* CLASSD_CLK_DIV - [8:6] */ 1387*4882a593Smuzhiyun #define WM8962_SYSCLK_ENA 0x0020 /* SYSCLK_ENA */ 1388*4882a593Smuzhiyun #define WM8962_SYSCLK_ENA_MASK 0x0020 /* SYSCLK_ENA */ 1389*4882a593Smuzhiyun #define WM8962_SYSCLK_ENA_SHIFT 5 /* SYSCLK_ENA */ 1390*4882a593Smuzhiyun #define WM8962_SYSCLK_ENA_WIDTH 1 /* SYSCLK_ENA */ 1391*4882a593Smuzhiyun #define WM8962_BCLK_DIV_MASK 0x000F /* BCLK_DIV - [3:0] */ 1392*4882a593Smuzhiyun #define WM8962_BCLK_DIV_SHIFT 0 /* BCLK_DIV - [3:0] */ 1393*4882a593Smuzhiyun #define WM8962_BCLK_DIV_WIDTH 4 /* BCLK_DIV - [3:0] */ 1394*4882a593Smuzhiyun 1395*4882a593Smuzhiyun /* 1396*4882a593Smuzhiyun * R9 (0x09) - Audio Interface 1 1397*4882a593Smuzhiyun */ 1398*4882a593Smuzhiyun #define WM8962_AUTOMUTE_STS 0x0800 /* AUTOMUTE_STS */ 1399*4882a593Smuzhiyun #define WM8962_AUTOMUTE_STS_MASK 0x0800 /* AUTOMUTE_STS */ 1400*4882a593Smuzhiyun #define WM8962_AUTOMUTE_STS_SHIFT 11 /* AUTOMUTE_STS */ 1401*4882a593Smuzhiyun #define WM8962_AUTOMUTE_STS_WIDTH 1 /* AUTOMUTE_STS */ 1402*4882a593Smuzhiyun #define WM8962_DAC_AUTOMUTE_SAMPLES_MASK 0x0300 /* DAC_AUTOMUTE_SAMPLES - [9:8] */ 1403*4882a593Smuzhiyun #define WM8962_DAC_AUTOMUTE_SAMPLES_SHIFT 8 /* DAC_AUTOMUTE_SAMPLES - [9:8] */ 1404*4882a593Smuzhiyun #define WM8962_DAC_AUTOMUTE_SAMPLES_WIDTH 2 /* DAC_AUTOMUTE_SAMPLES - [9:8] */ 1405*4882a593Smuzhiyun #define WM8962_DAC_AUTOMUTE 0x0080 /* DAC_AUTOMUTE */ 1406*4882a593Smuzhiyun #define WM8962_DAC_AUTOMUTE_MASK 0x0080 /* DAC_AUTOMUTE */ 1407*4882a593Smuzhiyun #define WM8962_DAC_AUTOMUTE_SHIFT 7 /* DAC_AUTOMUTE */ 1408*4882a593Smuzhiyun #define WM8962_DAC_AUTOMUTE_WIDTH 1 /* DAC_AUTOMUTE */ 1409*4882a593Smuzhiyun #define WM8962_DAC_COMP 0x0010 /* DAC_COMP */ 1410*4882a593Smuzhiyun #define WM8962_DAC_COMP_MASK 0x0010 /* DAC_COMP */ 1411*4882a593Smuzhiyun #define WM8962_DAC_COMP_SHIFT 4 /* DAC_COMP */ 1412*4882a593Smuzhiyun #define WM8962_DAC_COMP_WIDTH 1 /* DAC_COMP */ 1413*4882a593Smuzhiyun #define WM8962_DAC_COMPMODE 0x0008 /* DAC_COMPMODE */ 1414*4882a593Smuzhiyun #define WM8962_DAC_COMPMODE_MASK 0x0008 /* DAC_COMPMODE */ 1415*4882a593Smuzhiyun #define WM8962_DAC_COMPMODE_SHIFT 3 /* DAC_COMPMODE */ 1416*4882a593Smuzhiyun #define WM8962_DAC_COMPMODE_WIDTH 1 /* DAC_COMPMODE */ 1417*4882a593Smuzhiyun #define WM8962_ADC_COMP 0x0004 /* ADC_COMP */ 1418*4882a593Smuzhiyun #define WM8962_ADC_COMP_MASK 0x0004 /* ADC_COMP */ 1419*4882a593Smuzhiyun #define WM8962_ADC_COMP_SHIFT 2 /* ADC_COMP */ 1420*4882a593Smuzhiyun #define WM8962_ADC_COMP_WIDTH 1 /* ADC_COMP */ 1421*4882a593Smuzhiyun #define WM8962_ADC_COMPMODE 0x0002 /* ADC_COMPMODE */ 1422*4882a593Smuzhiyun #define WM8962_ADC_COMPMODE_MASK 0x0002 /* ADC_COMPMODE */ 1423*4882a593Smuzhiyun #define WM8962_ADC_COMPMODE_SHIFT 1 /* ADC_COMPMODE */ 1424*4882a593Smuzhiyun #define WM8962_ADC_COMPMODE_WIDTH 1 /* ADC_COMPMODE */ 1425*4882a593Smuzhiyun #define WM8962_LOOPBACK 0x0001 /* LOOPBACK */ 1426*4882a593Smuzhiyun #define WM8962_LOOPBACK_MASK 0x0001 /* LOOPBACK */ 1427*4882a593Smuzhiyun #define WM8962_LOOPBACK_SHIFT 0 /* LOOPBACK */ 1428*4882a593Smuzhiyun #define WM8962_LOOPBACK_WIDTH 1 /* LOOPBACK */ 1429*4882a593Smuzhiyun 1430*4882a593Smuzhiyun /* 1431*4882a593Smuzhiyun * R10 (0x0A) - Left DAC volume 1432*4882a593Smuzhiyun */ 1433*4882a593Smuzhiyun #define WM8962_DAC_VU 0x0100 /* DAC_VU */ 1434*4882a593Smuzhiyun #define WM8962_DAC_VU_MASK 0x0100 /* DAC_VU */ 1435*4882a593Smuzhiyun #define WM8962_DAC_VU_SHIFT 8 /* DAC_VU */ 1436*4882a593Smuzhiyun #define WM8962_DAC_VU_WIDTH 1 /* DAC_VU */ 1437*4882a593Smuzhiyun #define WM8962_DACL_VOL_MASK 0x00FF /* DACL_VOL - [7:0] */ 1438*4882a593Smuzhiyun #define WM8962_DACL_VOL_SHIFT 0 /* DACL_VOL - [7:0] */ 1439*4882a593Smuzhiyun #define WM8962_DACL_VOL_WIDTH 8 /* DACL_VOL - [7:0] */ 1440*4882a593Smuzhiyun 1441*4882a593Smuzhiyun /* 1442*4882a593Smuzhiyun * R11 (0x0B) - Right DAC volume 1443*4882a593Smuzhiyun */ 1444*4882a593Smuzhiyun #define WM8962_DAC_VU 0x0100 /* DAC_VU */ 1445*4882a593Smuzhiyun #define WM8962_DAC_VU_MASK 0x0100 /* DAC_VU */ 1446*4882a593Smuzhiyun #define WM8962_DAC_VU_SHIFT 8 /* DAC_VU */ 1447*4882a593Smuzhiyun #define WM8962_DAC_VU_WIDTH 1 /* DAC_VU */ 1448*4882a593Smuzhiyun #define WM8962_DACR_VOL_MASK 0x00FF /* DACR_VOL - [7:0] */ 1449*4882a593Smuzhiyun #define WM8962_DACR_VOL_SHIFT 0 /* DACR_VOL - [7:0] */ 1450*4882a593Smuzhiyun #define WM8962_DACR_VOL_WIDTH 8 /* DACR_VOL - [7:0] */ 1451*4882a593Smuzhiyun 1452*4882a593Smuzhiyun /* 1453*4882a593Smuzhiyun * R14 (0x0E) - Audio Interface 2 1454*4882a593Smuzhiyun */ 1455*4882a593Smuzhiyun #define WM8962_AIF_RATE_MASK 0x07FF /* AIF_RATE - [10:0] */ 1456*4882a593Smuzhiyun #define WM8962_AIF_RATE_SHIFT 0 /* AIF_RATE - [10:0] */ 1457*4882a593Smuzhiyun #define WM8962_AIF_RATE_WIDTH 11 /* AIF_RATE - [10:0] */ 1458*4882a593Smuzhiyun 1459*4882a593Smuzhiyun /* 1460*4882a593Smuzhiyun * R15 (0x0F) - Software Reset 1461*4882a593Smuzhiyun */ 1462*4882a593Smuzhiyun #define WM8962_SW_RESET_MASK 0xFFFF /* SW_RESET - [15:0] */ 1463*4882a593Smuzhiyun #define WM8962_SW_RESET_SHIFT 0 /* SW_RESET - [15:0] */ 1464*4882a593Smuzhiyun #define WM8962_SW_RESET_WIDTH 16 /* SW_RESET - [15:0] */ 1465*4882a593Smuzhiyun 1466*4882a593Smuzhiyun /* 1467*4882a593Smuzhiyun * R17 (0x11) - ALC1 1468*4882a593Smuzhiyun */ 1469*4882a593Smuzhiyun #define WM8962_ALC_INACTIVE_ENA 0x0400 /* ALC_INACTIVE_ENA */ 1470*4882a593Smuzhiyun #define WM8962_ALC_INACTIVE_ENA_MASK 0x0400 /* ALC_INACTIVE_ENA */ 1471*4882a593Smuzhiyun #define WM8962_ALC_INACTIVE_ENA_SHIFT 10 /* ALC_INACTIVE_ENA */ 1472*4882a593Smuzhiyun #define WM8962_ALC_INACTIVE_ENA_WIDTH 1 /* ALC_INACTIVE_ENA */ 1473*4882a593Smuzhiyun #define WM8962_ALC_LVL_MODE 0x0200 /* ALC_LVL_MODE */ 1474*4882a593Smuzhiyun #define WM8962_ALC_LVL_MODE_MASK 0x0200 /* ALC_LVL_MODE */ 1475*4882a593Smuzhiyun #define WM8962_ALC_LVL_MODE_SHIFT 9 /* ALC_LVL_MODE */ 1476*4882a593Smuzhiyun #define WM8962_ALC_LVL_MODE_WIDTH 1 /* ALC_LVL_MODE */ 1477*4882a593Smuzhiyun #define WM8962_ALCL_ENA 0x0100 /* ALCL_ENA */ 1478*4882a593Smuzhiyun #define WM8962_ALCL_ENA_MASK 0x0100 /* ALCL_ENA */ 1479*4882a593Smuzhiyun #define WM8962_ALCL_ENA_SHIFT 8 /* ALCL_ENA */ 1480*4882a593Smuzhiyun #define WM8962_ALCL_ENA_WIDTH 1 /* ALCL_ENA */ 1481*4882a593Smuzhiyun #define WM8962_ALCR_ENA 0x0080 /* ALCR_ENA */ 1482*4882a593Smuzhiyun #define WM8962_ALCR_ENA_MASK 0x0080 /* ALCR_ENA */ 1483*4882a593Smuzhiyun #define WM8962_ALCR_ENA_SHIFT 7 /* ALCR_ENA */ 1484*4882a593Smuzhiyun #define WM8962_ALCR_ENA_WIDTH 1 /* ALCR_ENA */ 1485*4882a593Smuzhiyun #define WM8962_ALC_MAXGAIN_MASK 0x0070 /* ALC_MAXGAIN - [6:4] */ 1486*4882a593Smuzhiyun #define WM8962_ALC_MAXGAIN_SHIFT 4 /* ALC_MAXGAIN - [6:4] */ 1487*4882a593Smuzhiyun #define WM8962_ALC_MAXGAIN_WIDTH 3 /* ALC_MAXGAIN - [6:4] */ 1488*4882a593Smuzhiyun #define WM8962_ALC_LVL_MASK 0x000F /* ALC_LVL - [3:0] */ 1489*4882a593Smuzhiyun #define WM8962_ALC_LVL_SHIFT 0 /* ALC_LVL - [3:0] */ 1490*4882a593Smuzhiyun #define WM8962_ALC_LVL_WIDTH 4 /* ALC_LVL - [3:0] */ 1491*4882a593Smuzhiyun 1492*4882a593Smuzhiyun /* 1493*4882a593Smuzhiyun * R18 (0x12) - ALC2 1494*4882a593Smuzhiyun */ 1495*4882a593Smuzhiyun #define WM8962_ALC_LOCK_STS 0x8000 /* ALC_LOCK_STS */ 1496*4882a593Smuzhiyun #define WM8962_ALC_LOCK_STS_MASK 0x8000 /* ALC_LOCK_STS */ 1497*4882a593Smuzhiyun #define WM8962_ALC_LOCK_STS_SHIFT 15 /* ALC_LOCK_STS */ 1498*4882a593Smuzhiyun #define WM8962_ALC_LOCK_STS_WIDTH 1 /* ALC_LOCK_STS */ 1499*4882a593Smuzhiyun #define WM8962_ALC_THRESH_STS 0x4000 /* ALC_THRESH_STS */ 1500*4882a593Smuzhiyun #define WM8962_ALC_THRESH_STS_MASK 0x4000 /* ALC_THRESH_STS */ 1501*4882a593Smuzhiyun #define WM8962_ALC_THRESH_STS_SHIFT 14 /* ALC_THRESH_STS */ 1502*4882a593Smuzhiyun #define WM8962_ALC_THRESH_STS_WIDTH 1 /* ALC_THRESH_STS */ 1503*4882a593Smuzhiyun #define WM8962_ALC_SAT_STS 0x2000 /* ALC_SAT_STS */ 1504*4882a593Smuzhiyun #define WM8962_ALC_SAT_STS_MASK 0x2000 /* ALC_SAT_STS */ 1505*4882a593Smuzhiyun #define WM8962_ALC_SAT_STS_SHIFT 13 /* ALC_SAT_STS */ 1506*4882a593Smuzhiyun #define WM8962_ALC_SAT_STS_WIDTH 1 /* ALC_SAT_STS */ 1507*4882a593Smuzhiyun #define WM8962_ALC_PKOVR_STS 0x1000 /* ALC_PKOVR_STS */ 1508*4882a593Smuzhiyun #define WM8962_ALC_PKOVR_STS_MASK 0x1000 /* ALC_PKOVR_STS */ 1509*4882a593Smuzhiyun #define WM8962_ALC_PKOVR_STS_SHIFT 12 /* ALC_PKOVR_STS */ 1510*4882a593Smuzhiyun #define WM8962_ALC_PKOVR_STS_WIDTH 1 /* ALC_PKOVR_STS */ 1511*4882a593Smuzhiyun #define WM8962_ALC_NGATE_STS 0x0800 /* ALC_NGATE_STS */ 1512*4882a593Smuzhiyun #define WM8962_ALC_NGATE_STS_MASK 0x0800 /* ALC_NGATE_STS */ 1513*4882a593Smuzhiyun #define WM8962_ALC_NGATE_STS_SHIFT 11 /* ALC_NGATE_STS */ 1514*4882a593Smuzhiyun #define WM8962_ALC_NGATE_STS_WIDTH 1 /* ALC_NGATE_STS */ 1515*4882a593Smuzhiyun #define WM8962_ALC_ZC 0x0080 /* ALC_ZC */ 1516*4882a593Smuzhiyun #define WM8962_ALC_ZC_MASK 0x0080 /* ALC_ZC */ 1517*4882a593Smuzhiyun #define WM8962_ALC_ZC_SHIFT 7 /* ALC_ZC */ 1518*4882a593Smuzhiyun #define WM8962_ALC_ZC_WIDTH 1 /* ALC_ZC */ 1519*4882a593Smuzhiyun #define WM8962_ALC_MINGAIN_MASK 0x0070 /* ALC_MINGAIN - [6:4] */ 1520*4882a593Smuzhiyun #define WM8962_ALC_MINGAIN_SHIFT 4 /* ALC_MINGAIN - [6:4] */ 1521*4882a593Smuzhiyun #define WM8962_ALC_MINGAIN_WIDTH 3 /* ALC_MINGAIN - [6:4] */ 1522*4882a593Smuzhiyun #define WM8962_ALC_HLD_MASK 0x000F /* ALC_HLD - [3:0] */ 1523*4882a593Smuzhiyun #define WM8962_ALC_HLD_SHIFT 0 /* ALC_HLD - [3:0] */ 1524*4882a593Smuzhiyun #define WM8962_ALC_HLD_WIDTH 4 /* ALC_HLD - [3:0] */ 1525*4882a593Smuzhiyun 1526*4882a593Smuzhiyun /* 1527*4882a593Smuzhiyun * R19 (0x13) - ALC3 1528*4882a593Smuzhiyun */ 1529*4882a593Smuzhiyun #define WM8962_ALC_NGATE_GAIN_MASK 0x1C00 /* ALC_NGATE_GAIN - [12:10] */ 1530*4882a593Smuzhiyun #define WM8962_ALC_NGATE_GAIN_SHIFT 10 /* ALC_NGATE_GAIN - [12:10] */ 1531*4882a593Smuzhiyun #define WM8962_ALC_NGATE_GAIN_WIDTH 3 /* ALC_NGATE_GAIN - [12:10] */ 1532*4882a593Smuzhiyun #define WM8962_ALC_MODE 0x0100 /* ALC_MODE */ 1533*4882a593Smuzhiyun #define WM8962_ALC_MODE_MASK 0x0100 /* ALC_MODE */ 1534*4882a593Smuzhiyun #define WM8962_ALC_MODE_SHIFT 8 /* ALC_MODE */ 1535*4882a593Smuzhiyun #define WM8962_ALC_MODE_WIDTH 1 /* ALC_MODE */ 1536*4882a593Smuzhiyun #define WM8962_ALC_DCY_MASK 0x00F0 /* ALC_DCY - [7:4] */ 1537*4882a593Smuzhiyun #define WM8962_ALC_DCY_SHIFT 4 /* ALC_DCY - [7:4] */ 1538*4882a593Smuzhiyun #define WM8962_ALC_DCY_WIDTH 4 /* ALC_DCY - [7:4] */ 1539*4882a593Smuzhiyun #define WM8962_ALC_ATK_MASK 0x000F /* ALC_ATK - [3:0] */ 1540*4882a593Smuzhiyun #define WM8962_ALC_ATK_SHIFT 0 /* ALC_ATK - [3:0] */ 1541*4882a593Smuzhiyun #define WM8962_ALC_ATK_WIDTH 4 /* ALC_ATK - [3:0] */ 1542*4882a593Smuzhiyun 1543*4882a593Smuzhiyun /* 1544*4882a593Smuzhiyun * R20 (0x14) - Noise Gate 1545*4882a593Smuzhiyun */ 1546*4882a593Smuzhiyun #define WM8962_ALC_NGATE_DCY_MASK 0xF000 /* ALC_NGATE_DCY - [15:12] */ 1547*4882a593Smuzhiyun #define WM8962_ALC_NGATE_DCY_SHIFT 12 /* ALC_NGATE_DCY - [15:12] */ 1548*4882a593Smuzhiyun #define WM8962_ALC_NGATE_DCY_WIDTH 4 /* ALC_NGATE_DCY - [15:12] */ 1549*4882a593Smuzhiyun #define WM8962_ALC_NGATE_ATK_MASK 0x0F00 /* ALC_NGATE_ATK - [11:8] */ 1550*4882a593Smuzhiyun #define WM8962_ALC_NGATE_ATK_SHIFT 8 /* ALC_NGATE_ATK - [11:8] */ 1551*4882a593Smuzhiyun #define WM8962_ALC_NGATE_ATK_WIDTH 4 /* ALC_NGATE_ATK - [11:8] */ 1552*4882a593Smuzhiyun #define WM8962_ALC_NGATE_THR_MASK 0x00F8 /* ALC_NGATE_THR - [7:3] */ 1553*4882a593Smuzhiyun #define WM8962_ALC_NGATE_THR_SHIFT 3 /* ALC_NGATE_THR - [7:3] */ 1554*4882a593Smuzhiyun #define WM8962_ALC_NGATE_THR_WIDTH 5 /* ALC_NGATE_THR - [7:3] */ 1555*4882a593Smuzhiyun #define WM8962_ALC_NGATE_MODE_MASK 0x0006 /* ALC_NGATE_MODE - [2:1] */ 1556*4882a593Smuzhiyun #define WM8962_ALC_NGATE_MODE_SHIFT 1 /* ALC_NGATE_MODE - [2:1] */ 1557*4882a593Smuzhiyun #define WM8962_ALC_NGATE_MODE_WIDTH 2 /* ALC_NGATE_MODE - [2:1] */ 1558*4882a593Smuzhiyun #define WM8962_ALC_NGATE_ENA 0x0001 /* ALC_NGATE_ENA */ 1559*4882a593Smuzhiyun #define WM8962_ALC_NGATE_ENA_MASK 0x0001 /* ALC_NGATE_ENA */ 1560*4882a593Smuzhiyun #define WM8962_ALC_NGATE_ENA_SHIFT 0 /* ALC_NGATE_ENA */ 1561*4882a593Smuzhiyun #define WM8962_ALC_NGATE_ENA_WIDTH 1 /* ALC_NGATE_ENA */ 1562*4882a593Smuzhiyun 1563*4882a593Smuzhiyun /* 1564*4882a593Smuzhiyun * R21 (0x15) - Left ADC volume 1565*4882a593Smuzhiyun */ 1566*4882a593Smuzhiyun #define WM8962_ADC_VU 0x0100 /* ADC_VU */ 1567*4882a593Smuzhiyun #define WM8962_ADC_VU_MASK 0x0100 /* ADC_VU */ 1568*4882a593Smuzhiyun #define WM8962_ADC_VU_SHIFT 8 /* ADC_VU */ 1569*4882a593Smuzhiyun #define WM8962_ADC_VU_WIDTH 1 /* ADC_VU */ 1570*4882a593Smuzhiyun #define WM8962_ADCL_VOL_MASK 0x00FF /* ADCL_VOL - [7:0] */ 1571*4882a593Smuzhiyun #define WM8962_ADCL_VOL_SHIFT 0 /* ADCL_VOL - [7:0] */ 1572*4882a593Smuzhiyun #define WM8962_ADCL_VOL_WIDTH 8 /* ADCL_VOL - [7:0] */ 1573*4882a593Smuzhiyun 1574*4882a593Smuzhiyun /* 1575*4882a593Smuzhiyun * R22 (0x16) - Right ADC volume 1576*4882a593Smuzhiyun */ 1577*4882a593Smuzhiyun #define WM8962_ADC_VU 0x0100 /* ADC_VU */ 1578*4882a593Smuzhiyun #define WM8962_ADC_VU_MASK 0x0100 /* ADC_VU */ 1579*4882a593Smuzhiyun #define WM8962_ADC_VU_SHIFT 8 /* ADC_VU */ 1580*4882a593Smuzhiyun #define WM8962_ADC_VU_WIDTH 1 /* ADC_VU */ 1581*4882a593Smuzhiyun #define WM8962_ADCR_VOL_MASK 0x00FF /* ADCR_VOL - [7:0] */ 1582*4882a593Smuzhiyun #define WM8962_ADCR_VOL_SHIFT 0 /* ADCR_VOL - [7:0] */ 1583*4882a593Smuzhiyun #define WM8962_ADCR_VOL_WIDTH 8 /* ADCR_VOL - [7:0] */ 1584*4882a593Smuzhiyun 1585*4882a593Smuzhiyun /* 1586*4882a593Smuzhiyun * R23 (0x17) - Additional control(1) 1587*4882a593Smuzhiyun */ 1588*4882a593Smuzhiyun #define WM8962_THERR_ACT 0x0100 /* THERR_ACT */ 1589*4882a593Smuzhiyun #define WM8962_THERR_ACT_MASK 0x0100 /* THERR_ACT */ 1590*4882a593Smuzhiyun #define WM8962_THERR_ACT_SHIFT 8 /* THERR_ACT */ 1591*4882a593Smuzhiyun #define WM8962_THERR_ACT_WIDTH 1 /* THERR_ACT */ 1592*4882a593Smuzhiyun #define WM8962_ADC_BIAS 0x0040 /* ADC_BIAS */ 1593*4882a593Smuzhiyun #define WM8962_ADC_BIAS_MASK 0x0040 /* ADC_BIAS */ 1594*4882a593Smuzhiyun #define WM8962_ADC_BIAS_SHIFT 6 /* ADC_BIAS */ 1595*4882a593Smuzhiyun #define WM8962_ADC_BIAS_WIDTH 1 /* ADC_BIAS */ 1596*4882a593Smuzhiyun #define WM8962_ADC_HP 0x0020 /* ADC_HP */ 1597*4882a593Smuzhiyun #define WM8962_ADC_HP_MASK 0x0020 /* ADC_HP */ 1598*4882a593Smuzhiyun #define WM8962_ADC_HP_SHIFT 5 /* ADC_HP */ 1599*4882a593Smuzhiyun #define WM8962_ADC_HP_WIDTH 1 /* ADC_HP */ 1600*4882a593Smuzhiyun #define WM8962_TOCLK_ENA 0x0001 /* TOCLK_ENA */ 1601*4882a593Smuzhiyun #define WM8962_TOCLK_ENA_MASK 0x0001 /* TOCLK_ENA */ 1602*4882a593Smuzhiyun #define WM8962_TOCLK_ENA_SHIFT 0 /* TOCLK_ENA */ 1603*4882a593Smuzhiyun #define WM8962_TOCLK_ENA_WIDTH 1 /* TOCLK_ENA */ 1604*4882a593Smuzhiyun 1605*4882a593Smuzhiyun /* 1606*4882a593Smuzhiyun * R24 (0x18) - Additional control(2) 1607*4882a593Smuzhiyun */ 1608*4882a593Smuzhiyun #define WM8962_AIF_TRI 0x0008 /* AIF_TRI */ 1609*4882a593Smuzhiyun #define WM8962_AIF_TRI_MASK 0x0008 /* AIF_TRI */ 1610*4882a593Smuzhiyun #define WM8962_AIF_TRI_SHIFT 3 /* AIF_TRI */ 1611*4882a593Smuzhiyun #define WM8962_AIF_TRI_WIDTH 1 /* AIF_TRI */ 1612*4882a593Smuzhiyun 1613*4882a593Smuzhiyun /* 1614*4882a593Smuzhiyun * R25 (0x19) - Pwr Mgmt (1) 1615*4882a593Smuzhiyun */ 1616*4882a593Smuzhiyun #define WM8962_DMIC_ENA 0x0400 /* DMIC_ENA */ 1617*4882a593Smuzhiyun #define WM8962_DMIC_ENA_MASK 0x0400 /* DMIC_ENA */ 1618*4882a593Smuzhiyun #define WM8962_DMIC_ENA_SHIFT 10 /* DMIC_ENA */ 1619*4882a593Smuzhiyun #define WM8962_DMIC_ENA_WIDTH 1 /* DMIC_ENA */ 1620*4882a593Smuzhiyun #define WM8962_OPCLK_ENA 0x0200 /* OPCLK_ENA */ 1621*4882a593Smuzhiyun #define WM8962_OPCLK_ENA_MASK 0x0200 /* OPCLK_ENA */ 1622*4882a593Smuzhiyun #define WM8962_OPCLK_ENA_SHIFT 9 /* OPCLK_ENA */ 1623*4882a593Smuzhiyun #define WM8962_OPCLK_ENA_WIDTH 1 /* OPCLK_ENA */ 1624*4882a593Smuzhiyun #define WM8962_VMID_SEL_MASK 0x0180 /* VMID_SEL - [8:7] */ 1625*4882a593Smuzhiyun #define WM8962_VMID_SEL_SHIFT 7 /* VMID_SEL - [8:7] */ 1626*4882a593Smuzhiyun #define WM8962_VMID_SEL_WIDTH 2 /* VMID_SEL - [8:7] */ 1627*4882a593Smuzhiyun #define WM8962_BIAS_ENA 0x0040 /* BIAS_ENA */ 1628*4882a593Smuzhiyun #define WM8962_BIAS_ENA_MASK 0x0040 /* BIAS_ENA */ 1629*4882a593Smuzhiyun #define WM8962_BIAS_ENA_SHIFT 6 /* BIAS_ENA */ 1630*4882a593Smuzhiyun #define WM8962_BIAS_ENA_WIDTH 1 /* BIAS_ENA */ 1631*4882a593Smuzhiyun #define WM8962_INL_ENA 0x0020 /* INL_ENA */ 1632*4882a593Smuzhiyun #define WM8962_INL_ENA_MASK 0x0020 /* INL_ENA */ 1633*4882a593Smuzhiyun #define WM8962_INL_ENA_SHIFT 5 /* INL_ENA */ 1634*4882a593Smuzhiyun #define WM8962_INL_ENA_WIDTH 1 /* INL_ENA */ 1635*4882a593Smuzhiyun #define WM8962_INR_ENA 0x0010 /* INR_ENA */ 1636*4882a593Smuzhiyun #define WM8962_INR_ENA_MASK 0x0010 /* INR_ENA */ 1637*4882a593Smuzhiyun #define WM8962_INR_ENA_SHIFT 4 /* INR_ENA */ 1638*4882a593Smuzhiyun #define WM8962_INR_ENA_WIDTH 1 /* INR_ENA */ 1639*4882a593Smuzhiyun #define WM8962_ADCL_ENA 0x0008 /* ADCL_ENA */ 1640*4882a593Smuzhiyun #define WM8962_ADCL_ENA_MASK 0x0008 /* ADCL_ENA */ 1641*4882a593Smuzhiyun #define WM8962_ADCL_ENA_SHIFT 3 /* ADCL_ENA */ 1642*4882a593Smuzhiyun #define WM8962_ADCL_ENA_WIDTH 1 /* ADCL_ENA */ 1643*4882a593Smuzhiyun #define WM8962_ADCR_ENA 0x0004 /* ADCR_ENA */ 1644*4882a593Smuzhiyun #define WM8962_ADCR_ENA_MASK 0x0004 /* ADCR_ENA */ 1645*4882a593Smuzhiyun #define WM8962_ADCR_ENA_SHIFT 2 /* ADCR_ENA */ 1646*4882a593Smuzhiyun #define WM8962_ADCR_ENA_WIDTH 1 /* ADCR_ENA */ 1647*4882a593Smuzhiyun #define WM8962_MICBIAS_ENA 0x0002 /* MICBIAS_ENA */ 1648*4882a593Smuzhiyun #define WM8962_MICBIAS_ENA_MASK 0x0002 /* MICBIAS_ENA */ 1649*4882a593Smuzhiyun #define WM8962_MICBIAS_ENA_SHIFT 1 /* MICBIAS_ENA */ 1650*4882a593Smuzhiyun #define WM8962_MICBIAS_ENA_WIDTH 1 /* MICBIAS_ENA */ 1651*4882a593Smuzhiyun 1652*4882a593Smuzhiyun /* 1653*4882a593Smuzhiyun * R26 (0x1A) - Pwr Mgmt (2) 1654*4882a593Smuzhiyun */ 1655*4882a593Smuzhiyun #define WM8962_DACL_ENA 0x0100 /* DACL_ENA */ 1656*4882a593Smuzhiyun #define WM8962_DACL_ENA_MASK 0x0100 /* DACL_ENA */ 1657*4882a593Smuzhiyun #define WM8962_DACL_ENA_SHIFT 8 /* DACL_ENA */ 1658*4882a593Smuzhiyun #define WM8962_DACL_ENA_WIDTH 1 /* DACL_ENA */ 1659*4882a593Smuzhiyun #define WM8962_DACR_ENA 0x0080 /* DACR_ENA */ 1660*4882a593Smuzhiyun #define WM8962_DACR_ENA_MASK 0x0080 /* DACR_ENA */ 1661*4882a593Smuzhiyun #define WM8962_DACR_ENA_SHIFT 7 /* DACR_ENA */ 1662*4882a593Smuzhiyun #define WM8962_DACR_ENA_WIDTH 1 /* DACR_ENA */ 1663*4882a593Smuzhiyun #define WM8962_HPOUTL_PGA_ENA 0x0040 /* HPOUTL_PGA_ENA */ 1664*4882a593Smuzhiyun #define WM8962_HPOUTL_PGA_ENA_MASK 0x0040 /* HPOUTL_PGA_ENA */ 1665*4882a593Smuzhiyun #define WM8962_HPOUTL_PGA_ENA_SHIFT 6 /* HPOUTL_PGA_ENA */ 1666*4882a593Smuzhiyun #define WM8962_HPOUTL_PGA_ENA_WIDTH 1 /* HPOUTL_PGA_ENA */ 1667*4882a593Smuzhiyun #define WM8962_HPOUTR_PGA_ENA 0x0020 /* HPOUTR_PGA_ENA */ 1668*4882a593Smuzhiyun #define WM8962_HPOUTR_PGA_ENA_MASK 0x0020 /* HPOUTR_PGA_ENA */ 1669*4882a593Smuzhiyun #define WM8962_HPOUTR_PGA_ENA_SHIFT 5 /* HPOUTR_PGA_ENA */ 1670*4882a593Smuzhiyun #define WM8962_HPOUTR_PGA_ENA_WIDTH 1 /* HPOUTR_PGA_ENA */ 1671*4882a593Smuzhiyun #define WM8962_SPKOUTL_PGA_ENA 0x0010 /* SPKOUTL_PGA_ENA */ 1672*4882a593Smuzhiyun #define WM8962_SPKOUTL_PGA_ENA_MASK 0x0010 /* SPKOUTL_PGA_ENA */ 1673*4882a593Smuzhiyun #define WM8962_SPKOUTL_PGA_ENA_SHIFT 4 /* SPKOUTL_PGA_ENA */ 1674*4882a593Smuzhiyun #define WM8962_SPKOUTL_PGA_ENA_WIDTH 1 /* SPKOUTL_PGA_ENA */ 1675*4882a593Smuzhiyun #define WM8962_SPKOUTR_PGA_ENA 0x0008 /* SPKOUTR_PGA_ENA */ 1676*4882a593Smuzhiyun #define WM8962_SPKOUTR_PGA_ENA_MASK 0x0008 /* SPKOUTR_PGA_ENA */ 1677*4882a593Smuzhiyun #define WM8962_SPKOUTR_PGA_ENA_SHIFT 3 /* SPKOUTR_PGA_ENA */ 1678*4882a593Smuzhiyun #define WM8962_SPKOUTR_PGA_ENA_WIDTH 1 /* SPKOUTR_PGA_ENA */ 1679*4882a593Smuzhiyun #define WM8962_HPOUTL_PGA_MUTE 0x0002 /* HPOUTL_PGA_MUTE */ 1680*4882a593Smuzhiyun #define WM8962_HPOUTL_PGA_MUTE_MASK 0x0002 /* HPOUTL_PGA_MUTE */ 1681*4882a593Smuzhiyun #define WM8962_HPOUTL_PGA_MUTE_SHIFT 1 /* HPOUTL_PGA_MUTE */ 1682*4882a593Smuzhiyun #define WM8962_HPOUTL_PGA_MUTE_WIDTH 1 /* HPOUTL_PGA_MUTE */ 1683*4882a593Smuzhiyun #define WM8962_HPOUTR_PGA_MUTE 0x0001 /* HPOUTR_PGA_MUTE */ 1684*4882a593Smuzhiyun #define WM8962_HPOUTR_PGA_MUTE_MASK 0x0001 /* HPOUTR_PGA_MUTE */ 1685*4882a593Smuzhiyun #define WM8962_HPOUTR_PGA_MUTE_SHIFT 0 /* HPOUTR_PGA_MUTE */ 1686*4882a593Smuzhiyun #define WM8962_HPOUTR_PGA_MUTE_WIDTH 1 /* HPOUTR_PGA_MUTE */ 1687*4882a593Smuzhiyun 1688*4882a593Smuzhiyun /* 1689*4882a593Smuzhiyun * R27 (0x1B) - Additional Control (3) 1690*4882a593Smuzhiyun */ 1691*4882a593Smuzhiyun #define WM8962_SAMPLE_RATE_INT_MODE 0x0010 /* SAMPLE_RATE_INT_MODE */ 1692*4882a593Smuzhiyun #define WM8962_SAMPLE_RATE_INT_MODE_MASK 0x0010 /* SAMPLE_RATE_INT_MODE */ 1693*4882a593Smuzhiyun #define WM8962_SAMPLE_RATE_INT_MODE_SHIFT 4 /* SAMPLE_RATE_INT_MODE */ 1694*4882a593Smuzhiyun #define WM8962_SAMPLE_RATE_INT_MODE_WIDTH 1 /* SAMPLE_RATE_INT_MODE */ 1695*4882a593Smuzhiyun #define WM8962_SAMPLE_RATE_MASK 0x0007 /* SAMPLE_RATE - [2:0] */ 1696*4882a593Smuzhiyun #define WM8962_SAMPLE_RATE_SHIFT 0 /* SAMPLE_RATE - [2:0] */ 1697*4882a593Smuzhiyun #define WM8962_SAMPLE_RATE_WIDTH 3 /* SAMPLE_RATE - [2:0] */ 1698*4882a593Smuzhiyun 1699*4882a593Smuzhiyun /* 1700*4882a593Smuzhiyun * R28 (0x1C) - Anti-pop 1701*4882a593Smuzhiyun */ 1702*4882a593Smuzhiyun #define WM8962_STARTUP_BIAS_ENA 0x0010 /* STARTUP_BIAS_ENA */ 1703*4882a593Smuzhiyun #define WM8962_STARTUP_BIAS_ENA_MASK 0x0010 /* STARTUP_BIAS_ENA */ 1704*4882a593Smuzhiyun #define WM8962_STARTUP_BIAS_ENA_SHIFT 4 /* STARTUP_BIAS_ENA */ 1705*4882a593Smuzhiyun #define WM8962_STARTUP_BIAS_ENA_WIDTH 1 /* STARTUP_BIAS_ENA */ 1706*4882a593Smuzhiyun #define WM8962_VMID_BUF_ENA 0x0008 /* VMID_BUF_ENA */ 1707*4882a593Smuzhiyun #define WM8962_VMID_BUF_ENA_MASK 0x0008 /* VMID_BUF_ENA */ 1708*4882a593Smuzhiyun #define WM8962_VMID_BUF_ENA_SHIFT 3 /* VMID_BUF_ENA */ 1709*4882a593Smuzhiyun #define WM8962_VMID_BUF_ENA_WIDTH 1 /* VMID_BUF_ENA */ 1710*4882a593Smuzhiyun #define WM8962_VMID_RAMP 0x0004 /* VMID_RAMP */ 1711*4882a593Smuzhiyun #define WM8962_VMID_RAMP_MASK 0x0004 /* VMID_RAMP */ 1712*4882a593Smuzhiyun #define WM8962_VMID_RAMP_SHIFT 2 /* VMID_RAMP */ 1713*4882a593Smuzhiyun #define WM8962_VMID_RAMP_WIDTH 1 /* VMID_RAMP */ 1714*4882a593Smuzhiyun 1715*4882a593Smuzhiyun /* 1716*4882a593Smuzhiyun * R30 (0x1E) - Clocking 3 1717*4882a593Smuzhiyun */ 1718*4882a593Smuzhiyun #define WM8962_DBCLK_DIV_MASK 0xE000 /* DBCLK_DIV - [15:13] */ 1719*4882a593Smuzhiyun #define WM8962_DBCLK_DIV_SHIFT 13 /* DBCLK_DIV - [15:13] */ 1720*4882a593Smuzhiyun #define WM8962_DBCLK_DIV_WIDTH 3 /* DBCLK_DIV - [15:13] */ 1721*4882a593Smuzhiyun #define WM8962_OPCLK_DIV_MASK 0x1C00 /* OPCLK_DIV - [12:10] */ 1722*4882a593Smuzhiyun #define WM8962_OPCLK_DIV_SHIFT 10 /* OPCLK_DIV - [12:10] */ 1723*4882a593Smuzhiyun #define WM8962_OPCLK_DIV_WIDTH 3 /* OPCLK_DIV - [12:10] */ 1724*4882a593Smuzhiyun #define WM8962_TOCLK_DIV_MASK 0x0380 /* TOCLK_DIV - [9:7] */ 1725*4882a593Smuzhiyun #define WM8962_TOCLK_DIV_SHIFT 7 /* TOCLK_DIV - [9:7] */ 1726*4882a593Smuzhiyun #define WM8962_TOCLK_DIV_WIDTH 3 /* TOCLK_DIV - [9:7] */ 1727*4882a593Smuzhiyun #define WM8962_F256KCLK_DIV_MASK 0x007E /* F256KCLK_DIV - [6:1] */ 1728*4882a593Smuzhiyun #define WM8962_F256KCLK_DIV_SHIFT 1 /* F256KCLK_DIV - [6:1] */ 1729*4882a593Smuzhiyun #define WM8962_F256KCLK_DIV_WIDTH 6 /* F256KCLK_DIV - [6:1] */ 1730*4882a593Smuzhiyun 1731*4882a593Smuzhiyun /* 1732*4882a593Smuzhiyun * R31 (0x1F) - Input mixer control (1) 1733*4882a593Smuzhiyun */ 1734*4882a593Smuzhiyun #define WM8962_MIXINL_MUTE 0x0008 /* MIXINL_MUTE */ 1735*4882a593Smuzhiyun #define WM8962_MIXINL_MUTE_MASK 0x0008 /* MIXINL_MUTE */ 1736*4882a593Smuzhiyun #define WM8962_MIXINL_MUTE_SHIFT 3 /* MIXINL_MUTE */ 1737*4882a593Smuzhiyun #define WM8962_MIXINL_MUTE_WIDTH 1 /* MIXINL_MUTE */ 1738*4882a593Smuzhiyun #define WM8962_MIXINR_MUTE 0x0004 /* MIXINR_MUTE */ 1739*4882a593Smuzhiyun #define WM8962_MIXINR_MUTE_MASK 0x0004 /* MIXINR_MUTE */ 1740*4882a593Smuzhiyun #define WM8962_MIXINR_MUTE_SHIFT 2 /* MIXINR_MUTE */ 1741*4882a593Smuzhiyun #define WM8962_MIXINR_MUTE_WIDTH 1 /* MIXINR_MUTE */ 1742*4882a593Smuzhiyun #define WM8962_MIXINL_ENA 0x0002 /* MIXINL_ENA */ 1743*4882a593Smuzhiyun #define WM8962_MIXINL_ENA_MASK 0x0002 /* MIXINL_ENA */ 1744*4882a593Smuzhiyun #define WM8962_MIXINL_ENA_SHIFT 1 /* MIXINL_ENA */ 1745*4882a593Smuzhiyun #define WM8962_MIXINL_ENA_WIDTH 1 /* MIXINL_ENA */ 1746*4882a593Smuzhiyun #define WM8962_MIXINR_ENA 0x0001 /* MIXINR_ENA */ 1747*4882a593Smuzhiyun #define WM8962_MIXINR_ENA_MASK 0x0001 /* MIXINR_ENA */ 1748*4882a593Smuzhiyun #define WM8962_MIXINR_ENA_SHIFT 0 /* MIXINR_ENA */ 1749*4882a593Smuzhiyun #define WM8962_MIXINR_ENA_WIDTH 1 /* MIXINR_ENA */ 1750*4882a593Smuzhiyun 1751*4882a593Smuzhiyun /* 1752*4882a593Smuzhiyun * R32 (0x20) - Left input mixer volume 1753*4882a593Smuzhiyun */ 1754*4882a593Smuzhiyun #define WM8962_IN2L_MIXINL_VOL_MASK 0x01C0 /* IN2L_MIXINL_VOL - [8:6] */ 1755*4882a593Smuzhiyun #define WM8962_IN2L_MIXINL_VOL_SHIFT 6 /* IN2L_MIXINL_VOL - [8:6] */ 1756*4882a593Smuzhiyun #define WM8962_IN2L_MIXINL_VOL_WIDTH 3 /* IN2L_MIXINL_VOL - [8:6] */ 1757*4882a593Smuzhiyun #define WM8962_INPGAL_MIXINL_VOL_MASK 0x0038 /* INPGAL_MIXINL_VOL - [5:3] */ 1758*4882a593Smuzhiyun #define WM8962_INPGAL_MIXINL_VOL_SHIFT 3 /* INPGAL_MIXINL_VOL - [5:3] */ 1759*4882a593Smuzhiyun #define WM8962_INPGAL_MIXINL_VOL_WIDTH 3 /* INPGAL_MIXINL_VOL - [5:3] */ 1760*4882a593Smuzhiyun #define WM8962_IN3L_MIXINL_VOL_MASK 0x0007 /* IN3L_MIXINL_VOL - [2:0] */ 1761*4882a593Smuzhiyun #define WM8962_IN3L_MIXINL_VOL_SHIFT 0 /* IN3L_MIXINL_VOL - [2:0] */ 1762*4882a593Smuzhiyun #define WM8962_IN3L_MIXINL_VOL_WIDTH 3 /* IN3L_MIXINL_VOL - [2:0] */ 1763*4882a593Smuzhiyun 1764*4882a593Smuzhiyun /* 1765*4882a593Smuzhiyun * R33 (0x21) - Right input mixer volume 1766*4882a593Smuzhiyun */ 1767*4882a593Smuzhiyun #define WM8962_IN2R_MIXINR_VOL_MASK 0x01C0 /* IN2R_MIXINR_VOL - [8:6] */ 1768*4882a593Smuzhiyun #define WM8962_IN2R_MIXINR_VOL_SHIFT 6 /* IN2R_MIXINR_VOL - [8:6] */ 1769*4882a593Smuzhiyun #define WM8962_IN2R_MIXINR_VOL_WIDTH 3 /* IN2R_MIXINR_VOL - [8:6] */ 1770*4882a593Smuzhiyun #define WM8962_INPGAR_MIXINR_VOL_MASK 0x0038 /* INPGAR_MIXINR_VOL - [5:3] */ 1771*4882a593Smuzhiyun #define WM8962_INPGAR_MIXINR_VOL_SHIFT 3 /* INPGAR_MIXINR_VOL - [5:3] */ 1772*4882a593Smuzhiyun #define WM8962_INPGAR_MIXINR_VOL_WIDTH 3 /* INPGAR_MIXINR_VOL - [5:3] */ 1773*4882a593Smuzhiyun #define WM8962_IN3R_MIXINR_VOL_MASK 0x0007 /* IN3R_MIXINR_VOL - [2:0] */ 1774*4882a593Smuzhiyun #define WM8962_IN3R_MIXINR_VOL_SHIFT 0 /* IN3R_MIXINR_VOL - [2:0] */ 1775*4882a593Smuzhiyun #define WM8962_IN3R_MIXINR_VOL_WIDTH 3 /* IN3R_MIXINR_VOL - [2:0] */ 1776*4882a593Smuzhiyun 1777*4882a593Smuzhiyun /* 1778*4882a593Smuzhiyun * R34 (0x22) - Input mixer control (2) 1779*4882a593Smuzhiyun */ 1780*4882a593Smuzhiyun #define WM8962_IN2L_TO_MIXINL 0x0020 /* IN2L_TO_MIXINL */ 1781*4882a593Smuzhiyun #define WM8962_IN2L_TO_MIXINL_MASK 0x0020 /* IN2L_TO_MIXINL */ 1782*4882a593Smuzhiyun #define WM8962_IN2L_TO_MIXINL_SHIFT 5 /* IN2L_TO_MIXINL */ 1783*4882a593Smuzhiyun #define WM8962_IN2L_TO_MIXINL_WIDTH 1 /* IN2L_TO_MIXINL */ 1784*4882a593Smuzhiyun #define WM8962_IN3L_TO_MIXINL 0x0010 /* IN3L_TO_MIXINL */ 1785*4882a593Smuzhiyun #define WM8962_IN3L_TO_MIXINL_MASK 0x0010 /* IN3L_TO_MIXINL */ 1786*4882a593Smuzhiyun #define WM8962_IN3L_TO_MIXINL_SHIFT 4 /* IN3L_TO_MIXINL */ 1787*4882a593Smuzhiyun #define WM8962_IN3L_TO_MIXINL_WIDTH 1 /* IN3L_TO_MIXINL */ 1788*4882a593Smuzhiyun #define WM8962_INPGAL_TO_MIXINL 0x0008 /* INPGAL_TO_MIXINL */ 1789*4882a593Smuzhiyun #define WM8962_INPGAL_TO_MIXINL_MASK 0x0008 /* INPGAL_TO_MIXINL */ 1790*4882a593Smuzhiyun #define WM8962_INPGAL_TO_MIXINL_SHIFT 3 /* INPGAL_TO_MIXINL */ 1791*4882a593Smuzhiyun #define WM8962_INPGAL_TO_MIXINL_WIDTH 1 /* INPGAL_TO_MIXINL */ 1792*4882a593Smuzhiyun #define WM8962_IN2R_TO_MIXINR 0x0004 /* IN2R_TO_MIXINR */ 1793*4882a593Smuzhiyun #define WM8962_IN2R_TO_MIXINR_MASK 0x0004 /* IN2R_TO_MIXINR */ 1794*4882a593Smuzhiyun #define WM8962_IN2R_TO_MIXINR_SHIFT 2 /* IN2R_TO_MIXINR */ 1795*4882a593Smuzhiyun #define WM8962_IN2R_TO_MIXINR_WIDTH 1 /* IN2R_TO_MIXINR */ 1796*4882a593Smuzhiyun #define WM8962_IN3R_TO_MIXINR 0x0002 /* IN3R_TO_MIXINR */ 1797*4882a593Smuzhiyun #define WM8962_IN3R_TO_MIXINR_MASK 0x0002 /* IN3R_TO_MIXINR */ 1798*4882a593Smuzhiyun #define WM8962_IN3R_TO_MIXINR_SHIFT 1 /* IN3R_TO_MIXINR */ 1799*4882a593Smuzhiyun #define WM8962_IN3R_TO_MIXINR_WIDTH 1 /* IN3R_TO_MIXINR */ 1800*4882a593Smuzhiyun #define WM8962_INPGAR_TO_MIXINR 0x0001 /* INPGAR_TO_MIXINR */ 1801*4882a593Smuzhiyun #define WM8962_INPGAR_TO_MIXINR_MASK 0x0001 /* INPGAR_TO_MIXINR */ 1802*4882a593Smuzhiyun #define WM8962_INPGAR_TO_MIXINR_SHIFT 0 /* INPGAR_TO_MIXINR */ 1803*4882a593Smuzhiyun #define WM8962_INPGAR_TO_MIXINR_WIDTH 1 /* INPGAR_TO_MIXINR */ 1804*4882a593Smuzhiyun 1805*4882a593Smuzhiyun /* 1806*4882a593Smuzhiyun * R35 (0x23) - Input bias control 1807*4882a593Smuzhiyun */ 1808*4882a593Smuzhiyun #define WM8962_MIXIN_BIAS_MASK 0x0038 /* MIXIN_BIAS - [5:3] */ 1809*4882a593Smuzhiyun #define WM8962_MIXIN_BIAS_SHIFT 3 /* MIXIN_BIAS - [5:3] */ 1810*4882a593Smuzhiyun #define WM8962_MIXIN_BIAS_WIDTH 3 /* MIXIN_BIAS - [5:3] */ 1811*4882a593Smuzhiyun #define WM8962_INPGA_BIAS_MASK 0x0007 /* INPGA_BIAS - [2:0] */ 1812*4882a593Smuzhiyun #define WM8962_INPGA_BIAS_SHIFT 0 /* INPGA_BIAS - [2:0] */ 1813*4882a593Smuzhiyun #define WM8962_INPGA_BIAS_WIDTH 3 /* INPGA_BIAS - [2:0] */ 1814*4882a593Smuzhiyun 1815*4882a593Smuzhiyun /* 1816*4882a593Smuzhiyun * R37 (0x25) - Left input PGA control 1817*4882a593Smuzhiyun */ 1818*4882a593Smuzhiyun #define WM8962_INPGAL_ENA 0x0010 /* INPGAL_ENA */ 1819*4882a593Smuzhiyun #define WM8962_INPGAL_ENA_MASK 0x0010 /* INPGAL_ENA */ 1820*4882a593Smuzhiyun #define WM8962_INPGAL_ENA_SHIFT 4 /* INPGAL_ENA */ 1821*4882a593Smuzhiyun #define WM8962_INPGAL_ENA_WIDTH 1 /* INPGAL_ENA */ 1822*4882a593Smuzhiyun #define WM8962_IN1L_TO_INPGAL 0x0008 /* IN1L_TO_INPGAL */ 1823*4882a593Smuzhiyun #define WM8962_IN1L_TO_INPGAL_MASK 0x0008 /* IN1L_TO_INPGAL */ 1824*4882a593Smuzhiyun #define WM8962_IN1L_TO_INPGAL_SHIFT 3 /* IN1L_TO_INPGAL */ 1825*4882a593Smuzhiyun #define WM8962_IN1L_TO_INPGAL_WIDTH 1 /* IN1L_TO_INPGAL */ 1826*4882a593Smuzhiyun #define WM8962_IN2L_TO_INPGAL 0x0004 /* IN2L_TO_INPGAL */ 1827*4882a593Smuzhiyun #define WM8962_IN2L_TO_INPGAL_MASK 0x0004 /* IN2L_TO_INPGAL */ 1828*4882a593Smuzhiyun #define WM8962_IN2L_TO_INPGAL_SHIFT 2 /* IN2L_TO_INPGAL */ 1829*4882a593Smuzhiyun #define WM8962_IN2L_TO_INPGAL_WIDTH 1 /* IN2L_TO_INPGAL */ 1830*4882a593Smuzhiyun #define WM8962_IN3L_TO_INPGAL 0x0002 /* IN3L_TO_INPGAL */ 1831*4882a593Smuzhiyun #define WM8962_IN3L_TO_INPGAL_MASK 0x0002 /* IN3L_TO_INPGAL */ 1832*4882a593Smuzhiyun #define WM8962_IN3L_TO_INPGAL_SHIFT 1 /* IN3L_TO_INPGAL */ 1833*4882a593Smuzhiyun #define WM8962_IN3L_TO_INPGAL_WIDTH 1 /* IN3L_TO_INPGAL */ 1834*4882a593Smuzhiyun #define WM8962_IN4L_TO_INPGAL 0x0001 /* IN4L_TO_INPGAL */ 1835*4882a593Smuzhiyun #define WM8962_IN4L_TO_INPGAL_MASK 0x0001 /* IN4L_TO_INPGAL */ 1836*4882a593Smuzhiyun #define WM8962_IN4L_TO_INPGAL_SHIFT 0 /* IN4L_TO_INPGAL */ 1837*4882a593Smuzhiyun #define WM8962_IN4L_TO_INPGAL_WIDTH 1 /* IN4L_TO_INPGAL */ 1838*4882a593Smuzhiyun 1839*4882a593Smuzhiyun /* 1840*4882a593Smuzhiyun * R38 (0x26) - Right input PGA control 1841*4882a593Smuzhiyun */ 1842*4882a593Smuzhiyun #define WM8962_INPGAR_ENA 0x0010 /* INPGAR_ENA */ 1843*4882a593Smuzhiyun #define WM8962_INPGAR_ENA_MASK 0x0010 /* INPGAR_ENA */ 1844*4882a593Smuzhiyun #define WM8962_INPGAR_ENA_SHIFT 4 /* INPGAR_ENA */ 1845*4882a593Smuzhiyun #define WM8962_INPGAR_ENA_WIDTH 1 /* INPGAR_ENA */ 1846*4882a593Smuzhiyun #define WM8962_IN1R_TO_INPGAR 0x0008 /* IN1R_TO_INPGAR */ 1847*4882a593Smuzhiyun #define WM8962_IN1R_TO_INPGAR_MASK 0x0008 /* IN1R_TO_INPGAR */ 1848*4882a593Smuzhiyun #define WM8962_IN1R_TO_INPGAR_SHIFT 3 /* IN1R_TO_INPGAR */ 1849*4882a593Smuzhiyun #define WM8962_IN1R_TO_INPGAR_WIDTH 1 /* IN1R_TO_INPGAR */ 1850*4882a593Smuzhiyun #define WM8962_IN2R_TO_INPGAR 0x0004 /* IN2R_TO_INPGAR */ 1851*4882a593Smuzhiyun #define WM8962_IN2R_TO_INPGAR_MASK 0x0004 /* IN2R_TO_INPGAR */ 1852*4882a593Smuzhiyun #define WM8962_IN2R_TO_INPGAR_SHIFT 2 /* IN2R_TO_INPGAR */ 1853*4882a593Smuzhiyun #define WM8962_IN2R_TO_INPGAR_WIDTH 1 /* IN2R_TO_INPGAR */ 1854*4882a593Smuzhiyun #define WM8962_IN3R_TO_INPGAR 0x0002 /* IN3R_TO_INPGAR */ 1855*4882a593Smuzhiyun #define WM8962_IN3R_TO_INPGAR_MASK 0x0002 /* IN3R_TO_INPGAR */ 1856*4882a593Smuzhiyun #define WM8962_IN3R_TO_INPGAR_SHIFT 1 /* IN3R_TO_INPGAR */ 1857*4882a593Smuzhiyun #define WM8962_IN3R_TO_INPGAR_WIDTH 1 /* IN3R_TO_INPGAR */ 1858*4882a593Smuzhiyun #define WM8962_IN4R_TO_INPGAR 0x0001 /* IN4R_TO_INPGAR */ 1859*4882a593Smuzhiyun #define WM8962_IN4R_TO_INPGAR_MASK 0x0001 /* IN4R_TO_INPGAR */ 1860*4882a593Smuzhiyun #define WM8962_IN4R_TO_INPGAR_SHIFT 0 /* IN4R_TO_INPGAR */ 1861*4882a593Smuzhiyun #define WM8962_IN4R_TO_INPGAR_WIDTH 1 /* IN4R_TO_INPGAR */ 1862*4882a593Smuzhiyun 1863*4882a593Smuzhiyun /* 1864*4882a593Smuzhiyun * R40 (0x28) - SPKOUTL volume 1865*4882a593Smuzhiyun */ 1866*4882a593Smuzhiyun #define WM8962_SPKOUT_VU 0x0100 /* SPKOUT_VU */ 1867*4882a593Smuzhiyun #define WM8962_SPKOUT_VU_MASK 0x0100 /* SPKOUT_VU */ 1868*4882a593Smuzhiyun #define WM8962_SPKOUT_VU_SHIFT 8 /* SPKOUT_VU */ 1869*4882a593Smuzhiyun #define WM8962_SPKOUT_VU_WIDTH 1 /* SPKOUT_VU */ 1870*4882a593Smuzhiyun #define WM8962_SPKOUTL_ZC 0x0080 /* SPKOUTL_ZC */ 1871*4882a593Smuzhiyun #define WM8962_SPKOUTL_ZC_MASK 0x0080 /* SPKOUTL_ZC */ 1872*4882a593Smuzhiyun #define WM8962_SPKOUTL_ZC_SHIFT 7 /* SPKOUTL_ZC */ 1873*4882a593Smuzhiyun #define WM8962_SPKOUTL_ZC_WIDTH 1 /* SPKOUTL_ZC */ 1874*4882a593Smuzhiyun #define WM8962_SPKOUTL_VOL_MASK 0x007F /* SPKOUTL_VOL - [6:0] */ 1875*4882a593Smuzhiyun #define WM8962_SPKOUTL_VOL_SHIFT 0 /* SPKOUTL_VOL - [6:0] */ 1876*4882a593Smuzhiyun #define WM8962_SPKOUTL_VOL_WIDTH 7 /* SPKOUTL_VOL - [6:0] */ 1877*4882a593Smuzhiyun 1878*4882a593Smuzhiyun /* 1879*4882a593Smuzhiyun * R41 (0x29) - SPKOUTR volume 1880*4882a593Smuzhiyun */ 1881*4882a593Smuzhiyun #define WM8962_SPKOUTR_ZC 0x0080 /* SPKOUTR_ZC */ 1882*4882a593Smuzhiyun #define WM8962_SPKOUTR_ZC_MASK 0x0080 /* SPKOUTR_ZC */ 1883*4882a593Smuzhiyun #define WM8962_SPKOUTR_ZC_SHIFT 7 /* SPKOUTR_ZC */ 1884*4882a593Smuzhiyun #define WM8962_SPKOUTR_ZC_WIDTH 1 /* SPKOUTR_ZC */ 1885*4882a593Smuzhiyun #define WM8962_SPKOUTR_VOL_MASK 0x007F /* SPKOUTR_VOL - [6:0] */ 1886*4882a593Smuzhiyun #define WM8962_SPKOUTR_VOL_SHIFT 0 /* SPKOUTR_VOL - [6:0] */ 1887*4882a593Smuzhiyun #define WM8962_SPKOUTR_VOL_WIDTH 7 /* SPKOUTR_VOL - [6:0] */ 1888*4882a593Smuzhiyun 1889*4882a593Smuzhiyun /* 1890*4882a593Smuzhiyun * R47 (0x2F) - Thermal Shutdown Status 1891*4882a593Smuzhiyun */ 1892*4882a593Smuzhiyun #define WM8962_TEMP_ERR_HP 0x0008 /* TEMP_ERR_HP */ 1893*4882a593Smuzhiyun #define WM8962_TEMP_ERR_HP_MASK 0x0008 /* TEMP_ERR_HP */ 1894*4882a593Smuzhiyun #define WM8962_TEMP_ERR_HP_SHIFT 3 /* TEMP_ERR_HP */ 1895*4882a593Smuzhiyun #define WM8962_TEMP_ERR_HP_WIDTH 1 /* TEMP_ERR_HP */ 1896*4882a593Smuzhiyun #define WM8962_TEMP_WARN_HP 0x0004 /* TEMP_WARN_HP */ 1897*4882a593Smuzhiyun #define WM8962_TEMP_WARN_HP_MASK 0x0004 /* TEMP_WARN_HP */ 1898*4882a593Smuzhiyun #define WM8962_TEMP_WARN_HP_SHIFT 2 /* TEMP_WARN_HP */ 1899*4882a593Smuzhiyun #define WM8962_TEMP_WARN_HP_WIDTH 1 /* TEMP_WARN_HP */ 1900*4882a593Smuzhiyun #define WM8962_TEMP_ERR_SPK 0x0002 /* TEMP_ERR_SPK */ 1901*4882a593Smuzhiyun #define WM8962_TEMP_ERR_SPK_MASK 0x0002 /* TEMP_ERR_SPK */ 1902*4882a593Smuzhiyun #define WM8962_TEMP_ERR_SPK_SHIFT 1 /* TEMP_ERR_SPK */ 1903*4882a593Smuzhiyun #define WM8962_TEMP_ERR_SPK_WIDTH 1 /* TEMP_ERR_SPK */ 1904*4882a593Smuzhiyun #define WM8962_TEMP_WARN_SPK 0x0001 /* TEMP_WARN_SPK */ 1905*4882a593Smuzhiyun #define WM8962_TEMP_WARN_SPK_MASK 0x0001 /* TEMP_WARN_SPK */ 1906*4882a593Smuzhiyun #define WM8962_TEMP_WARN_SPK_SHIFT 0 /* TEMP_WARN_SPK */ 1907*4882a593Smuzhiyun #define WM8962_TEMP_WARN_SPK_WIDTH 1 /* TEMP_WARN_SPK */ 1908*4882a593Smuzhiyun 1909*4882a593Smuzhiyun /* 1910*4882a593Smuzhiyun * R48 (0x30) - Additional Control (4) 1911*4882a593Smuzhiyun */ 1912*4882a593Smuzhiyun #define WM8962_MICDET_THR_MASK 0x7000 /* MICDET_THR - [14:12] */ 1913*4882a593Smuzhiyun #define WM8962_MICDET_THR_SHIFT 12 /* MICDET_THR - [14:12] */ 1914*4882a593Smuzhiyun #define WM8962_MICDET_THR_WIDTH 3 /* MICDET_THR - [14:12] */ 1915*4882a593Smuzhiyun #define WM8962_MICSHORT_THR_MASK 0x0C00 /* MICSHORT_THR - [11:10] */ 1916*4882a593Smuzhiyun #define WM8962_MICSHORT_THR_SHIFT 10 /* MICSHORT_THR - [11:10] */ 1917*4882a593Smuzhiyun #define WM8962_MICSHORT_THR_WIDTH 2 /* MICSHORT_THR - [11:10] */ 1918*4882a593Smuzhiyun #define WM8962_MICDET_ENA 0x0200 /* MICDET_ENA */ 1919*4882a593Smuzhiyun #define WM8962_MICDET_ENA_MASK 0x0200 /* MICDET_ENA */ 1920*4882a593Smuzhiyun #define WM8962_MICDET_ENA_SHIFT 9 /* MICDET_ENA */ 1921*4882a593Smuzhiyun #define WM8962_MICDET_ENA_WIDTH 1 /* MICDET_ENA */ 1922*4882a593Smuzhiyun #define WM8962_MICDET_STS 0x0080 /* MICDET_STS */ 1923*4882a593Smuzhiyun #define WM8962_MICDET_STS_MASK 0x0080 /* MICDET_STS */ 1924*4882a593Smuzhiyun #define WM8962_MICDET_STS_SHIFT 7 /* MICDET_STS */ 1925*4882a593Smuzhiyun #define WM8962_MICDET_STS_WIDTH 1 /* MICDET_STS */ 1926*4882a593Smuzhiyun #define WM8962_MICSHORT_STS 0x0040 /* MICSHORT_STS */ 1927*4882a593Smuzhiyun #define WM8962_MICSHORT_STS_MASK 0x0040 /* MICSHORT_STS */ 1928*4882a593Smuzhiyun #define WM8962_MICSHORT_STS_SHIFT 6 /* MICSHORT_STS */ 1929*4882a593Smuzhiyun #define WM8962_MICSHORT_STS_WIDTH 1 /* MICSHORT_STS */ 1930*4882a593Smuzhiyun #define WM8962_TEMP_ENA_HP 0x0004 /* TEMP_ENA_HP */ 1931*4882a593Smuzhiyun #define WM8962_TEMP_ENA_HP_MASK 0x0004 /* TEMP_ENA_HP */ 1932*4882a593Smuzhiyun #define WM8962_TEMP_ENA_HP_SHIFT 2 /* TEMP_ENA_HP */ 1933*4882a593Smuzhiyun #define WM8962_TEMP_ENA_HP_WIDTH 1 /* TEMP_ENA_HP */ 1934*4882a593Smuzhiyun #define WM8962_TEMP_ENA_SPK 0x0002 /* TEMP_ENA_SPK */ 1935*4882a593Smuzhiyun #define WM8962_TEMP_ENA_SPK_MASK 0x0002 /* TEMP_ENA_SPK */ 1936*4882a593Smuzhiyun #define WM8962_TEMP_ENA_SPK_SHIFT 1 /* TEMP_ENA_SPK */ 1937*4882a593Smuzhiyun #define WM8962_TEMP_ENA_SPK_WIDTH 1 /* TEMP_ENA_SPK */ 1938*4882a593Smuzhiyun #define WM8962_MICBIAS_LVL 0x0001 /* MICBIAS_LVL */ 1939*4882a593Smuzhiyun #define WM8962_MICBIAS_LVL_MASK 0x0001 /* MICBIAS_LVL */ 1940*4882a593Smuzhiyun #define WM8962_MICBIAS_LVL_SHIFT 0 /* MICBIAS_LVL */ 1941*4882a593Smuzhiyun #define WM8962_MICBIAS_LVL_WIDTH 1 /* MICBIAS_LVL */ 1942*4882a593Smuzhiyun 1943*4882a593Smuzhiyun /* 1944*4882a593Smuzhiyun * R49 (0x31) - Class D Control 1 1945*4882a593Smuzhiyun */ 1946*4882a593Smuzhiyun #define WM8962_SPKOUTR_ENA 0x0080 /* SPKOUTR_ENA */ 1947*4882a593Smuzhiyun #define WM8962_SPKOUTR_ENA_MASK 0x0080 /* SPKOUTR_ENA */ 1948*4882a593Smuzhiyun #define WM8962_SPKOUTR_ENA_SHIFT 7 /* SPKOUTR_ENA */ 1949*4882a593Smuzhiyun #define WM8962_SPKOUTR_ENA_WIDTH 1 /* SPKOUTR_ENA */ 1950*4882a593Smuzhiyun #define WM8962_SPKOUTL_ENA 0x0040 /* SPKOUTL_ENA */ 1951*4882a593Smuzhiyun #define WM8962_SPKOUTL_ENA_MASK 0x0040 /* SPKOUTL_ENA */ 1952*4882a593Smuzhiyun #define WM8962_SPKOUTL_ENA_SHIFT 6 /* SPKOUTL_ENA */ 1953*4882a593Smuzhiyun #define WM8962_SPKOUTL_ENA_WIDTH 1 /* SPKOUTL_ENA */ 1954*4882a593Smuzhiyun #define WM8962_DAC_MUTE_ALT 0x0010 /* DAC_MUTE */ 1955*4882a593Smuzhiyun #define WM8962_DAC_MUTE_ALT_MASK 0x0010 /* DAC_MUTE */ 1956*4882a593Smuzhiyun #define WM8962_DAC_MUTE_ALT_SHIFT 4 /* DAC_MUTE */ 1957*4882a593Smuzhiyun #define WM8962_DAC_MUTE_ALT_WIDTH 1 /* DAC_MUTE */ 1958*4882a593Smuzhiyun #define WM8962_SPKOUTL_PGA_MUTE 0x0002 /* SPKOUTL_PGA_MUTE */ 1959*4882a593Smuzhiyun #define WM8962_SPKOUTL_PGA_MUTE_MASK 0x0002 /* SPKOUTL_PGA_MUTE */ 1960*4882a593Smuzhiyun #define WM8962_SPKOUTL_PGA_MUTE_SHIFT 1 /* SPKOUTL_PGA_MUTE */ 1961*4882a593Smuzhiyun #define WM8962_SPKOUTL_PGA_MUTE_WIDTH 1 /* SPKOUTL_PGA_MUTE */ 1962*4882a593Smuzhiyun #define WM8962_SPKOUTR_PGA_MUTE 0x0001 /* SPKOUTR_PGA_MUTE */ 1963*4882a593Smuzhiyun #define WM8962_SPKOUTR_PGA_MUTE_MASK 0x0001 /* SPKOUTR_PGA_MUTE */ 1964*4882a593Smuzhiyun #define WM8962_SPKOUTR_PGA_MUTE_SHIFT 0 /* SPKOUTR_PGA_MUTE */ 1965*4882a593Smuzhiyun #define WM8962_SPKOUTR_PGA_MUTE_WIDTH 1 /* SPKOUTR_PGA_MUTE */ 1966*4882a593Smuzhiyun 1967*4882a593Smuzhiyun /* 1968*4882a593Smuzhiyun * R51 (0x33) - Class D Control 2 1969*4882a593Smuzhiyun */ 1970*4882a593Smuzhiyun #define WM8962_SPK_MONO 0x0040 /* SPK_MONO */ 1971*4882a593Smuzhiyun #define WM8962_SPK_MONO_MASK 0x0040 /* SPK_MONO */ 1972*4882a593Smuzhiyun #define WM8962_SPK_MONO_SHIFT 6 /* SPK_MONO */ 1973*4882a593Smuzhiyun #define WM8962_SPK_MONO_WIDTH 1 /* SPK_MONO */ 1974*4882a593Smuzhiyun #define WM8962_CLASSD_VOL_MASK 0x0007 /* CLASSD_VOL - [2:0] */ 1975*4882a593Smuzhiyun #define WM8962_CLASSD_VOL_SHIFT 0 /* CLASSD_VOL - [2:0] */ 1976*4882a593Smuzhiyun #define WM8962_CLASSD_VOL_WIDTH 3 /* CLASSD_VOL - [2:0] */ 1977*4882a593Smuzhiyun 1978*4882a593Smuzhiyun /* 1979*4882a593Smuzhiyun * R56 (0x38) - Clocking 4 1980*4882a593Smuzhiyun */ 1981*4882a593Smuzhiyun #define WM8962_SYSCLK_RATE_MASK 0x001E /* SYSCLK_RATE - [4:1] */ 1982*4882a593Smuzhiyun #define WM8962_SYSCLK_RATE_SHIFT 1 /* SYSCLK_RATE - [4:1] */ 1983*4882a593Smuzhiyun #define WM8962_SYSCLK_RATE_WIDTH 4 /* SYSCLK_RATE - [4:1] */ 1984*4882a593Smuzhiyun 1985*4882a593Smuzhiyun /* 1986*4882a593Smuzhiyun * R57 (0x39) - DAC DSP Mixing (1) 1987*4882a593Smuzhiyun */ 1988*4882a593Smuzhiyun #define WM8962_DAC_MONOMIX 0x0200 /* DAC_MONOMIX */ 1989*4882a593Smuzhiyun #define WM8962_DAC_MONOMIX_MASK 0x0200 /* DAC_MONOMIX */ 1990*4882a593Smuzhiyun #define WM8962_DAC_MONOMIX_SHIFT 9 /* DAC_MONOMIX */ 1991*4882a593Smuzhiyun #define WM8962_DAC_MONOMIX_WIDTH 1 /* DAC_MONOMIX */ 1992*4882a593Smuzhiyun #define WM8962_ADCR_DAC_SVOL_MASK 0x00F0 /* ADCR_DAC_SVOL - [7:4] */ 1993*4882a593Smuzhiyun #define WM8962_ADCR_DAC_SVOL_SHIFT 4 /* ADCR_DAC_SVOL - [7:4] */ 1994*4882a593Smuzhiyun #define WM8962_ADCR_DAC_SVOL_WIDTH 4 /* ADCR_DAC_SVOL - [7:4] */ 1995*4882a593Smuzhiyun #define WM8962_ADC_TO_DACR_MASK 0x000C /* ADC_TO_DACR - [3:2] */ 1996*4882a593Smuzhiyun #define WM8962_ADC_TO_DACR_SHIFT 2 /* ADC_TO_DACR - [3:2] */ 1997*4882a593Smuzhiyun #define WM8962_ADC_TO_DACR_WIDTH 2 /* ADC_TO_DACR - [3:2] */ 1998*4882a593Smuzhiyun 1999*4882a593Smuzhiyun /* 2000*4882a593Smuzhiyun * R58 (0x3A) - DAC DSP Mixing (2) 2001*4882a593Smuzhiyun */ 2002*4882a593Smuzhiyun #define WM8962_ADCL_DAC_SVOL_MASK 0x00F0 /* ADCL_DAC_SVOL - [7:4] */ 2003*4882a593Smuzhiyun #define WM8962_ADCL_DAC_SVOL_SHIFT 4 /* ADCL_DAC_SVOL - [7:4] */ 2004*4882a593Smuzhiyun #define WM8962_ADCL_DAC_SVOL_WIDTH 4 /* ADCL_DAC_SVOL - [7:4] */ 2005*4882a593Smuzhiyun #define WM8962_ADC_TO_DACL_MASK 0x000C /* ADC_TO_DACL - [3:2] */ 2006*4882a593Smuzhiyun #define WM8962_ADC_TO_DACL_SHIFT 2 /* ADC_TO_DACL - [3:2] */ 2007*4882a593Smuzhiyun #define WM8962_ADC_TO_DACL_WIDTH 2 /* ADC_TO_DACL - [3:2] */ 2008*4882a593Smuzhiyun 2009*4882a593Smuzhiyun /* 2010*4882a593Smuzhiyun * R60 (0x3C) - DC Servo 0 2011*4882a593Smuzhiyun */ 2012*4882a593Smuzhiyun #define WM8962_INL_DCS_ENA 0x0080 /* INL_DCS_ENA */ 2013*4882a593Smuzhiyun #define WM8962_INL_DCS_ENA_MASK 0x0080 /* INL_DCS_ENA */ 2014*4882a593Smuzhiyun #define WM8962_INL_DCS_ENA_SHIFT 7 /* INL_DCS_ENA */ 2015*4882a593Smuzhiyun #define WM8962_INL_DCS_ENA_WIDTH 1 /* INL_DCS_ENA */ 2016*4882a593Smuzhiyun #define WM8962_INL_DCS_STARTUP 0x0040 /* INL_DCS_STARTUP */ 2017*4882a593Smuzhiyun #define WM8962_INL_DCS_STARTUP_MASK 0x0040 /* INL_DCS_STARTUP */ 2018*4882a593Smuzhiyun #define WM8962_INL_DCS_STARTUP_SHIFT 6 /* INL_DCS_STARTUP */ 2019*4882a593Smuzhiyun #define WM8962_INL_DCS_STARTUP_WIDTH 1 /* INL_DCS_STARTUP */ 2020*4882a593Smuzhiyun #define WM8962_INR_DCS_ENA 0x0008 /* INR_DCS_ENA */ 2021*4882a593Smuzhiyun #define WM8962_INR_DCS_ENA_MASK 0x0008 /* INR_DCS_ENA */ 2022*4882a593Smuzhiyun #define WM8962_INR_DCS_ENA_SHIFT 3 /* INR_DCS_ENA */ 2023*4882a593Smuzhiyun #define WM8962_INR_DCS_ENA_WIDTH 1 /* INR_DCS_ENA */ 2024*4882a593Smuzhiyun #define WM8962_INR_DCS_STARTUP 0x0004 /* INR_DCS_STARTUP */ 2025*4882a593Smuzhiyun #define WM8962_INR_DCS_STARTUP_MASK 0x0004 /* INR_DCS_STARTUP */ 2026*4882a593Smuzhiyun #define WM8962_INR_DCS_STARTUP_SHIFT 2 /* INR_DCS_STARTUP */ 2027*4882a593Smuzhiyun #define WM8962_INR_DCS_STARTUP_WIDTH 1 /* INR_DCS_STARTUP */ 2028*4882a593Smuzhiyun 2029*4882a593Smuzhiyun /* 2030*4882a593Smuzhiyun * R61 (0x3D) - DC Servo 1 2031*4882a593Smuzhiyun */ 2032*4882a593Smuzhiyun #define WM8962_HP1L_DCS_ENA 0x0080 /* HP1L_DCS_ENA */ 2033*4882a593Smuzhiyun #define WM8962_HP1L_DCS_ENA_MASK 0x0080 /* HP1L_DCS_ENA */ 2034*4882a593Smuzhiyun #define WM8962_HP1L_DCS_ENA_SHIFT 7 /* HP1L_DCS_ENA */ 2035*4882a593Smuzhiyun #define WM8962_HP1L_DCS_ENA_WIDTH 1 /* HP1L_DCS_ENA */ 2036*4882a593Smuzhiyun #define WM8962_HP1L_DCS_STARTUP 0x0040 /* HP1L_DCS_STARTUP */ 2037*4882a593Smuzhiyun #define WM8962_HP1L_DCS_STARTUP_MASK 0x0040 /* HP1L_DCS_STARTUP */ 2038*4882a593Smuzhiyun #define WM8962_HP1L_DCS_STARTUP_SHIFT 6 /* HP1L_DCS_STARTUP */ 2039*4882a593Smuzhiyun #define WM8962_HP1L_DCS_STARTUP_WIDTH 1 /* HP1L_DCS_STARTUP */ 2040*4882a593Smuzhiyun #define WM8962_HP1L_DCS_SYNC 0x0010 /* HP1L_DCS_SYNC */ 2041*4882a593Smuzhiyun #define WM8962_HP1L_DCS_SYNC_MASK 0x0010 /* HP1L_DCS_SYNC */ 2042*4882a593Smuzhiyun #define WM8962_HP1L_DCS_SYNC_SHIFT 4 /* HP1L_DCS_SYNC */ 2043*4882a593Smuzhiyun #define WM8962_HP1L_DCS_SYNC_WIDTH 1 /* HP1L_DCS_SYNC */ 2044*4882a593Smuzhiyun #define WM8962_HP1R_DCS_ENA 0x0008 /* HP1R_DCS_ENA */ 2045*4882a593Smuzhiyun #define WM8962_HP1R_DCS_ENA_MASK 0x0008 /* HP1R_DCS_ENA */ 2046*4882a593Smuzhiyun #define WM8962_HP1R_DCS_ENA_SHIFT 3 /* HP1R_DCS_ENA */ 2047*4882a593Smuzhiyun #define WM8962_HP1R_DCS_ENA_WIDTH 1 /* HP1R_DCS_ENA */ 2048*4882a593Smuzhiyun #define WM8962_HP1R_DCS_STARTUP 0x0004 /* HP1R_DCS_STARTUP */ 2049*4882a593Smuzhiyun #define WM8962_HP1R_DCS_STARTUP_MASK 0x0004 /* HP1R_DCS_STARTUP */ 2050*4882a593Smuzhiyun #define WM8962_HP1R_DCS_STARTUP_SHIFT 2 /* HP1R_DCS_STARTUP */ 2051*4882a593Smuzhiyun #define WM8962_HP1R_DCS_STARTUP_WIDTH 1 /* HP1R_DCS_STARTUP */ 2052*4882a593Smuzhiyun #define WM8962_HP1R_DCS_SYNC 0x0001 /* HP1R_DCS_SYNC */ 2053*4882a593Smuzhiyun #define WM8962_HP1R_DCS_SYNC_MASK 0x0001 /* HP1R_DCS_SYNC */ 2054*4882a593Smuzhiyun #define WM8962_HP1R_DCS_SYNC_SHIFT 0 /* HP1R_DCS_SYNC */ 2055*4882a593Smuzhiyun #define WM8962_HP1R_DCS_SYNC_WIDTH 1 /* HP1R_DCS_SYNC */ 2056*4882a593Smuzhiyun 2057*4882a593Smuzhiyun /* 2058*4882a593Smuzhiyun * R64 (0x40) - DC Servo 4 2059*4882a593Smuzhiyun */ 2060*4882a593Smuzhiyun #define WM8962_HP1_DCS_SYNC_STEPS_MASK 0x3F80 /* HP1_DCS_SYNC_STEPS - [13:7] */ 2061*4882a593Smuzhiyun #define WM8962_HP1_DCS_SYNC_STEPS_SHIFT 7 /* HP1_DCS_SYNC_STEPS - [13:7] */ 2062*4882a593Smuzhiyun #define WM8962_HP1_DCS_SYNC_STEPS_WIDTH 7 /* HP1_DCS_SYNC_STEPS - [13:7] */ 2063*4882a593Smuzhiyun 2064*4882a593Smuzhiyun /* 2065*4882a593Smuzhiyun * R66 (0x42) - DC Servo 6 2066*4882a593Smuzhiyun */ 2067*4882a593Smuzhiyun #define WM8962_DCS_STARTUP_DONE_INL 0x0400 /* DCS_STARTUP_DONE_INL */ 2068*4882a593Smuzhiyun #define WM8962_DCS_STARTUP_DONE_INL_MASK 0x0400 /* DCS_STARTUP_DONE_INL */ 2069*4882a593Smuzhiyun #define WM8962_DCS_STARTUP_DONE_INL_SHIFT 10 /* DCS_STARTUP_DONE_INL */ 2070*4882a593Smuzhiyun #define WM8962_DCS_STARTUP_DONE_INL_WIDTH 1 /* DCS_STARTUP_DONE_INL */ 2071*4882a593Smuzhiyun #define WM8962_DCS_STARTUP_DONE_INR 0x0200 /* DCS_STARTUP_DONE_INR */ 2072*4882a593Smuzhiyun #define WM8962_DCS_STARTUP_DONE_INR_MASK 0x0200 /* DCS_STARTUP_DONE_INR */ 2073*4882a593Smuzhiyun #define WM8962_DCS_STARTUP_DONE_INR_SHIFT 9 /* DCS_STARTUP_DONE_INR */ 2074*4882a593Smuzhiyun #define WM8962_DCS_STARTUP_DONE_INR_WIDTH 1 /* DCS_STARTUP_DONE_INR */ 2075*4882a593Smuzhiyun #define WM8962_DCS_STARTUP_DONE_HP1L 0x0100 /* DCS_STARTUP_DONE_HP1L */ 2076*4882a593Smuzhiyun #define WM8962_DCS_STARTUP_DONE_HP1L_MASK 0x0100 /* DCS_STARTUP_DONE_HP1L */ 2077*4882a593Smuzhiyun #define WM8962_DCS_STARTUP_DONE_HP1L_SHIFT 8 /* DCS_STARTUP_DONE_HP1L */ 2078*4882a593Smuzhiyun #define WM8962_DCS_STARTUP_DONE_HP1L_WIDTH 1 /* DCS_STARTUP_DONE_HP1L */ 2079*4882a593Smuzhiyun #define WM8962_DCS_STARTUP_DONE_HP1R 0x0080 /* DCS_STARTUP_DONE_HP1R */ 2080*4882a593Smuzhiyun #define WM8962_DCS_STARTUP_DONE_HP1R_MASK 0x0080 /* DCS_STARTUP_DONE_HP1R */ 2081*4882a593Smuzhiyun #define WM8962_DCS_STARTUP_DONE_HP1R_SHIFT 7 /* DCS_STARTUP_DONE_HP1R */ 2082*4882a593Smuzhiyun #define WM8962_DCS_STARTUP_DONE_HP1R_WIDTH 1 /* DCS_STARTUP_DONE_HP1R */ 2083*4882a593Smuzhiyun 2084*4882a593Smuzhiyun /* 2085*4882a593Smuzhiyun * R68 (0x44) - Analogue PGA Bias 2086*4882a593Smuzhiyun */ 2087*4882a593Smuzhiyun #define WM8962_HP_PGAS_BIAS_MASK 0x0007 /* HP_PGAS_BIAS - [2:0] */ 2088*4882a593Smuzhiyun #define WM8962_HP_PGAS_BIAS_SHIFT 0 /* HP_PGAS_BIAS - [2:0] */ 2089*4882a593Smuzhiyun #define WM8962_HP_PGAS_BIAS_WIDTH 3 /* HP_PGAS_BIAS - [2:0] */ 2090*4882a593Smuzhiyun 2091*4882a593Smuzhiyun /* 2092*4882a593Smuzhiyun * R69 (0x45) - Analogue HP 0 2093*4882a593Smuzhiyun */ 2094*4882a593Smuzhiyun #define WM8962_HP1L_RMV_SHORT 0x0080 /* HP1L_RMV_SHORT */ 2095*4882a593Smuzhiyun #define WM8962_HP1L_RMV_SHORT_MASK 0x0080 /* HP1L_RMV_SHORT */ 2096*4882a593Smuzhiyun #define WM8962_HP1L_RMV_SHORT_SHIFT 7 /* HP1L_RMV_SHORT */ 2097*4882a593Smuzhiyun #define WM8962_HP1L_RMV_SHORT_WIDTH 1 /* HP1L_RMV_SHORT */ 2098*4882a593Smuzhiyun #define WM8962_HP1L_ENA_OUTP 0x0040 /* HP1L_ENA_OUTP */ 2099*4882a593Smuzhiyun #define WM8962_HP1L_ENA_OUTP_MASK 0x0040 /* HP1L_ENA_OUTP */ 2100*4882a593Smuzhiyun #define WM8962_HP1L_ENA_OUTP_SHIFT 6 /* HP1L_ENA_OUTP */ 2101*4882a593Smuzhiyun #define WM8962_HP1L_ENA_OUTP_WIDTH 1 /* HP1L_ENA_OUTP */ 2102*4882a593Smuzhiyun #define WM8962_HP1L_ENA_DLY 0x0020 /* HP1L_ENA_DLY */ 2103*4882a593Smuzhiyun #define WM8962_HP1L_ENA_DLY_MASK 0x0020 /* HP1L_ENA_DLY */ 2104*4882a593Smuzhiyun #define WM8962_HP1L_ENA_DLY_SHIFT 5 /* HP1L_ENA_DLY */ 2105*4882a593Smuzhiyun #define WM8962_HP1L_ENA_DLY_WIDTH 1 /* HP1L_ENA_DLY */ 2106*4882a593Smuzhiyun #define WM8962_HP1L_ENA 0x0010 /* HP1L_ENA */ 2107*4882a593Smuzhiyun #define WM8962_HP1L_ENA_MASK 0x0010 /* HP1L_ENA */ 2108*4882a593Smuzhiyun #define WM8962_HP1L_ENA_SHIFT 4 /* HP1L_ENA */ 2109*4882a593Smuzhiyun #define WM8962_HP1L_ENA_WIDTH 1 /* HP1L_ENA */ 2110*4882a593Smuzhiyun #define WM8962_HP1R_RMV_SHORT 0x0008 /* HP1R_RMV_SHORT */ 2111*4882a593Smuzhiyun #define WM8962_HP1R_RMV_SHORT_MASK 0x0008 /* HP1R_RMV_SHORT */ 2112*4882a593Smuzhiyun #define WM8962_HP1R_RMV_SHORT_SHIFT 3 /* HP1R_RMV_SHORT */ 2113*4882a593Smuzhiyun #define WM8962_HP1R_RMV_SHORT_WIDTH 1 /* HP1R_RMV_SHORT */ 2114*4882a593Smuzhiyun #define WM8962_HP1R_ENA_OUTP 0x0004 /* HP1R_ENA_OUTP */ 2115*4882a593Smuzhiyun #define WM8962_HP1R_ENA_OUTP_MASK 0x0004 /* HP1R_ENA_OUTP */ 2116*4882a593Smuzhiyun #define WM8962_HP1R_ENA_OUTP_SHIFT 2 /* HP1R_ENA_OUTP */ 2117*4882a593Smuzhiyun #define WM8962_HP1R_ENA_OUTP_WIDTH 1 /* HP1R_ENA_OUTP */ 2118*4882a593Smuzhiyun #define WM8962_HP1R_ENA_DLY 0x0002 /* HP1R_ENA_DLY */ 2119*4882a593Smuzhiyun #define WM8962_HP1R_ENA_DLY_MASK 0x0002 /* HP1R_ENA_DLY */ 2120*4882a593Smuzhiyun #define WM8962_HP1R_ENA_DLY_SHIFT 1 /* HP1R_ENA_DLY */ 2121*4882a593Smuzhiyun #define WM8962_HP1R_ENA_DLY_WIDTH 1 /* HP1R_ENA_DLY */ 2122*4882a593Smuzhiyun #define WM8962_HP1R_ENA 0x0001 /* HP1R_ENA */ 2123*4882a593Smuzhiyun #define WM8962_HP1R_ENA_MASK 0x0001 /* HP1R_ENA */ 2124*4882a593Smuzhiyun #define WM8962_HP1R_ENA_SHIFT 0 /* HP1R_ENA */ 2125*4882a593Smuzhiyun #define WM8962_HP1R_ENA_WIDTH 1 /* HP1R_ENA */ 2126*4882a593Smuzhiyun 2127*4882a593Smuzhiyun /* 2128*4882a593Smuzhiyun * R71 (0x47) - Analogue HP 2 2129*4882a593Smuzhiyun */ 2130*4882a593Smuzhiyun #define WM8962_HP1L_VOL_MASK 0x01C0 /* HP1L_VOL - [8:6] */ 2131*4882a593Smuzhiyun #define WM8962_HP1L_VOL_SHIFT 6 /* HP1L_VOL - [8:6] */ 2132*4882a593Smuzhiyun #define WM8962_HP1L_VOL_WIDTH 3 /* HP1L_VOL - [8:6] */ 2133*4882a593Smuzhiyun #define WM8962_HP1R_VOL_MASK 0x0038 /* HP1R_VOL - [5:3] */ 2134*4882a593Smuzhiyun #define WM8962_HP1R_VOL_SHIFT 3 /* HP1R_VOL - [5:3] */ 2135*4882a593Smuzhiyun #define WM8962_HP1R_VOL_WIDTH 3 /* HP1R_VOL - [5:3] */ 2136*4882a593Smuzhiyun #define WM8962_HP_BIAS_BOOST_MASK 0x0007 /* HP_BIAS_BOOST - [2:0] */ 2137*4882a593Smuzhiyun #define WM8962_HP_BIAS_BOOST_SHIFT 0 /* HP_BIAS_BOOST - [2:0] */ 2138*4882a593Smuzhiyun #define WM8962_HP_BIAS_BOOST_WIDTH 3 /* HP_BIAS_BOOST - [2:0] */ 2139*4882a593Smuzhiyun 2140*4882a593Smuzhiyun /* 2141*4882a593Smuzhiyun * R72 (0x48) - Charge Pump 1 2142*4882a593Smuzhiyun */ 2143*4882a593Smuzhiyun #define WM8962_CP_ENA 0x0001 /* CP_ENA */ 2144*4882a593Smuzhiyun #define WM8962_CP_ENA_MASK 0x0001 /* CP_ENA */ 2145*4882a593Smuzhiyun #define WM8962_CP_ENA_SHIFT 0 /* CP_ENA */ 2146*4882a593Smuzhiyun #define WM8962_CP_ENA_WIDTH 1 /* CP_ENA */ 2147*4882a593Smuzhiyun 2148*4882a593Smuzhiyun /* 2149*4882a593Smuzhiyun * R82 (0x52) - Charge Pump B 2150*4882a593Smuzhiyun */ 2151*4882a593Smuzhiyun #define WM8962_CP_DYN_PWR 0x0001 /* CP_DYN_PWR */ 2152*4882a593Smuzhiyun #define WM8962_CP_DYN_PWR_MASK 0x0001 /* CP_DYN_PWR */ 2153*4882a593Smuzhiyun #define WM8962_CP_DYN_PWR_SHIFT 0 /* CP_DYN_PWR */ 2154*4882a593Smuzhiyun #define WM8962_CP_DYN_PWR_WIDTH 1 /* CP_DYN_PWR */ 2155*4882a593Smuzhiyun 2156*4882a593Smuzhiyun /* 2157*4882a593Smuzhiyun * R87 (0x57) - Write Sequencer Control 1 2158*4882a593Smuzhiyun */ 2159*4882a593Smuzhiyun #define WM8962_WSEQ_AUTOSEQ_ENA 0x0080 /* WSEQ_AUTOSEQ_ENA */ 2160*4882a593Smuzhiyun #define WM8962_WSEQ_AUTOSEQ_ENA_MASK 0x0080 /* WSEQ_AUTOSEQ_ENA */ 2161*4882a593Smuzhiyun #define WM8962_WSEQ_AUTOSEQ_ENA_SHIFT 7 /* WSEQ_AUTOSEQ_ENA */ 2162*4882a593Smuzhiyun #define WM8962_WSEQ_AUTOSEQ_ENA_WIDTH 1 /* WSEQ_AUTOSEQ_ENA */ 2163*4882a593Smuzhiyun #define WM8962_WSEQ_ENA 0x0020 /* WSEQ_ENA */ 2164*4882a593Smuzhiyun #define WM8962_WSEQ_ENA_MASK 0x0020 /* WSEQ_ENA */ 2165*4882a593Smuzhiyun #define WM8962_WSEQ_ENA_SHIFT 5 /* WSEQ_ENA */ 2166*4882a593Smuzhiyun #define WM8962_WSEQ_ENA_WIDTH 1 /* WSEQ_ENA */ 2167*4882a593Smuzhiyun 2168*4882a593Smuzhiyun /* 2169*4882a593Smuzhiyun * R90 (0x5A) - Write Sequencer Control 2 2170*4882a593Smuzhiyun */ 2171*4882a593Smuzhiyun #define WM8962_WSEQ_ABORT 0x0100 /* WSEQ_ABORT */ 2172*4882a593Smuzhiyun #define WM8962_WSEQ_ABORT_MASK 0x0100 /* WSEQ_ABORT */ 2173*4882a593Smuzhiyun #define WM8962_WSEQ_ABORT_SHIFT 8 /* WSEQ_ABORT */ 2174*4882a593Smuzhiyun #define WM8962_WSEQ_ABORT_WIDTH 1 /* WSEQ_ABORT */ 2175*4882a593Smuzhiyun #define WM8962_WSEQ_START 0x0080 /* WSEQ_START */ 2176*4882a593Smuzhiyun #define WM8962_WSEQ_START_MASK 0x0080 /* WSEQ_START */ 2177*4882a593Smuzhiyun #define WM8962_WSEQ_START_SHIFT 7 /* WSEQ_START */ 2178*4882a593Smuzhiyun #define WM8962_WSEQ_START_WIDTH 1 /* WSEQ_START */ 2179*4882a593Smuzhiyun #define WM8962_WSEQ_START_INDEX_MASK 0x007F /* WSEQ_START_INDEX - [6:0] */ 2180*4882a593Smuzhiyun #define WM8962_WSEQ_START_INDEX_SHIFT 0 /* WSEQ_START_INDEX - [6:0] */ 2181*4882a593Smuzhiyun #define WM8962_WSEQ_START_INDEX_WIDTH 7 /* WSEQ_START_INDEX - [6:0] */ 2182*4882a593Smuzhiyun 2183*4882a593Smuzhiyun /* 2184*4882a593Smuzhiyun * R93 (0x5D) - Write Sequencer Control 3 2185*4882a593Smuzhiyun */ 2186*4882a593Smuzhiyun #define WM8962_WSEQ_CURRENT_INDEX_MASK 0x03F8 /* WSEQ_CURRENT_INDEX - [9:3] */ 2187*4882a593Smuzhiyun #define WM8962_WSEQ_CURRENT_INDEX_SHIFT 3 /* WSEQ_CURRENT_INDEX - [9:3] */ 2188*4882a593Smuzhiyun #define WM8962_WSEQ_CURRENT_INDEX_WIDTH 7 /* WSEQ_CURRENT_INDEX - [9:3] */ 2189*4882a593Smuzhiyun #define WM8962_WSEQ_BUSY 0x0001 /* WSEQ_BUSY */ 2190*4882a593Smuzhiyun #define WM8962_WSEQ_BUSY_MASK 0x0001 /* WSEQ_BUSY */ 2191*4882a593Smuzhiyun #define WM8962_WSEQ_BUSY_SHIFT 0 /* WSEQ_BUSY */ 2192*4882a593Smuzhiyun #define WM8962_WSEQ_BUSY_WIDTH 1 /* WSEQ_BUSY */ 2193*4882a593Smuzhiyun 2194*4882a593Smuzhiyun /* 2195*4882a593Smuzhiyun * R94 (0x5E) - Control Interface 2196*4882a593Smuzhiyun */ 2197*4882a593Smuzhiyun #define WM8962_SPI_CONTRD 0x0040 /* SPI_CONTRD */ 2198*4882a593Smuzhiyun #define WM8962_SPI_CONTRD_MASK 0x0040 /* SPI_CONTRD */ 2199*4882a593Smuzhiyun #define WM8962_SPI_CONTRD_SHIFT 6 /* SPI_CONTRD */ 2200*4882a593Smuzhiyun #define WM8962_SPI_CONTRD_WIDTH 1 /* SPI_CONTRD */ 2201*4882a593Smuzhiyun #define WM8962_SPI_4WIRE 0x0020 /* SPI_4WIRE */ 2202*4882a593Smuzhiyun #define WM8962_SPI_4WIRE_MASK 0x0020 /* SPI_4WIRE */ 2203*4882a593Smuzhiyun #define WM8962_SPI_4WIRE_SHIFT 5 /* SPI_4WIRE */ 2204*4882a593Smuzhiyun #define WM8962_SPI_4WIRE_WIDTH 1 /* SPI_4WIRE */ 2205*4882a593Smuzhiyun #define WM8962_SPI_CFG 0x0010 /* SPI_CFG */ 2206*4882a593Smuzhiyun #define WM8962_SPI_CFG_MASK 0x0010 /* SPI_CFG */ 2207*4882a593Smuzhiyun #define WM8962_SPI_CFG_SHIFT 4 /* SPI_CFG */ 2208*4882a593Smuzhiyun #define WM8962_SPI_CFG_WIDTH 1 /* SPI_CFG */ 2209*4882a593Smuzhiyun 2210*4882a593Smuzhiyun /* 2211*4882a593Smuzhiyun * R99 (0x63) - Mixer Enables 2212*4882a593Smuzhiyun */ 2213*4882a593Smuzhiyun #define WM8962_HPMIXL_ENA 0x0008 /* HPMIXL_ENA */ 2214*4882a593Smuzhiyun #define WM8962_HPMIXL_ENA_MASK 0x0008 /* HPMIXL_ENA */ 2215*4882a593Smuzhiyun #define WM8962_HPMIXL_ENA_SHIFT 3 /* HPMIXL_ENA */ 2216*4882a593Smuzhiyun #define WM8962_HPMIXL_ENA_WIDTH 1 /* HPMIXL_ENA */ 2217*4882a593Smuzhiyun #define WM8962_HPMIXR_ENA 0x0004 /* HPMIXR_ENA */ 2218*4882a593Smuzhiyun #define WM8962_HPMIXR_ENA_MASK 0x0004 /* HPMIXR_ENA */ 2219*4882a593Smuzhiyun #define WM8962_HPMIXR_ENA_SHIFT 2 /* HPMIXR_ENA */ 2220*4882a593Smuzhiyun #define WM8962_HPMIXR_ENA_WIDTH 1 /* HPMIXR_ENA */ 2221*4882a593Smuzhiyun #define WM8962_SPKMIXL_ENA 0x0002 /* SPKMIXL_ENA */ 2222*4882a593Smuzhiyun #define WM8962_SPKMIXL_ENA_MASK 0x0002 /* SPKMIXL_ENA */ 2223*4882a593Smuzhiyun #define WM8962_SPKMIXL_ENA_SHIFT 1 /* SPKMIXL_ENA */ 2224*4882a593Smuzhiyun #define WM8962_SPKMIXL_ENA_WIDTH 1 /* SPKMIXL_ENA */ 2225*4882a593Smuzhiyun #define WM8962_SPKMIXR_ENA 0x0001 /* SPKMIXR_ENA */ 2226*4882a593Smuzhiyun #define WM8962_SPKMIXR_ENA_MASK 0x0001 /* SPKMIXR_ENA */ 2227*4882a593Smuzhiyun #define WM8962_SPKMIXR_ENA_SHIFT 0 /* SPKMIXR_ENA */ 2228*4882a593Smuzhiyun #define WM8962_SPKMIXR_ENA_WIDTH 1 /* SPKMIXR_ENA */ 2229*4882a593Smuzhiyun 2230*4882a593Smuzhiyun /* 2231*4882a593Smuzhiyun * R100 (0x64) - Headphone Mixer (1) 2232*4882a593Smuzhiyun */ 2233*4882a593Smuzhiyun #define WM8962_HPMIXL_TO_HPOUTL_PGA 0x0080 /* HPMIXL_TO_HPOUTL_PGA */ 2234*4882a593Smuzhiyun #define WM8962_HPMIXL_TO_HPOUTL_PGA_MASK 0x0080 /* HPMIXL_TO_HPOUTL_PGA */ 2235*4882a593Smuzhiyun #define WM8962_HPMIXL_TO_HPOUTL_PGA_SHIFT 7 /* HPMIXL_TO_HPOUTL_PGA */ 2236*4882a593Smuzhiyun #define WM8962_HPMIXL_TO_HPOUTL_PGA_WIDTH 1 /* HPMIXL_TO_HPOUTL_PGA */ 2237*4882a593Smuzhiyun #define WM8962_DACL_TO_HPMIXL 0x0020 /* DACL_TO_HPMIXL */ 2238*4882a593Smuzhiyun #define WM8962_DACL_TO_HPMIXL_MASK 0x0020 /* DACL_TO_HPMIXL */ 2239*4882a593Smuzhiyun #define WM8962_DACL_TO_HPMIXL_SHIFT 5 /* DACL_TO_HPMIXL */ 2240*4882a593Smuzhiyun #define WM8962_DACL_TO_HPMIXL_WIDTH 1 /* DACL_TO_HPMIXL */ 2241*4882a593Smuzhiyun #define WM8962_DACR_TO_HPMIXL 0x0010 /* DACR_TO_HPMIXL */ 2242*4882a593Smuzhiyun #define WM8962_DACR_TO_HPMIXL_MASK 0x0010 /* DACR_TO_HPMIXL */ 2243*4882a593Smuzhiyun #define WM8962_DACR_TO_HPMIXL_SHIFT 4 /* DACR_TO_HPMIXL */ 2244*4882a593Smuzhiyun #define WM8962_DACR_TO_HPMIXL_WIDTH 1 /* DACR_TO_HPMIXL */ 2245*4882a593Smuzhiyun #define WM8962_MIXINL_TO_HPMIXL 0x0008 /* MIXINL_TO_HPMIXL */ 2246*4882a593Smuzhiyun #define WM8962_MIXINL_TO_HPMIXL_MASK 0x0008 /* MIXINL_TO_HPMIXL */ 2247*4882a593Smuzhiyun #define WM8962_MIXINL_TO_HPMIXL_SHIFT 3 /* MIXINL_TO_HPMIXL */ 2248*4882a593Smuzhiyun #define WM8962_MIXINL_TO_HPMIXL_WIDTH 1 /* MIXINL_TO_HPMIXL */ 2249*4882a593Smuzhiyun #define WM8962_MIXINR_TO_HPMIXL 0x0004 /* MIXINR_TO_HPMIXL */ 2250*4882a593Smuzhiyun #define WM8962_MIXINR_TO_HPMIXL_MASK 0x0004 /* MIXINR_TO_HPMIXL */ 2251*4882a593Smuzhiyun #define WM8962_MIXINR_TO_HPMIXL_SHIFT 2 /* MIXINR_TO_HPMIXL */ 2252*4882a593Smuzhiyun #define WM8962_MIXINR_TO_HPMIXL_WIDTH 1 /* MIXINR_TO_HPMIXL */ 2253*4882a593Smuzhiyun #define WM8962_IN4L_TO_HPMIXL 0x0002 /* IN4L_TO_HPMIXL */ 2254*4882a593Smuzhiyun #define WM8962_IN4L_TO_HPMIXL_MASK 0x0002 /* IN4L_TO_HPMIXL */ 2255*4882a593Smuzhiyun #define WM8962_IN4L_TO_HPMIXL_SHIFT 1 /* IN4L_TO_HPMIXL */ 2256*4882a593Smuzhiyun #define WM8962_IN4L_TO_HPMIXL_WIDTH 1 /* IN4L_TO_HPMIXL */ 2257*4882a593Smuzhiyun #define WM8962_IN4R_TO_HPMIXL 0x0001 /* IN4R_TO_HPMIXL */ 2258*4882a593Smuzhiyun #define WM8962_IN4R_TO_HPMIXL_MASK 0x0001 /* IN4R_TO_HPMIXL */ 2259*4882a593Smuzhiyun #define WM8962_IN4R_TO_HPMIXL_SHIFT 0 /* IN4R_TO_HPMIXL */ 2260*4882a593Smuzhiyun #define WM8962_IN4R_TO_HPMIXL_WIDTH 1 /* IN4R_TO_HPMIXL */ 2261*4882a593Smuzhiyun 2262*4882a593Smuzhiyun /* 2263*4882a593Smuzhiyun * R101 (0x65) - Headphone Mixer (2) 2264*4882a593Smuzhiyun */ 2265*4882a593Smuzhiyun #define WM8962_HPMIXR_TO_HPOUTR_PGA 0x0080 /* HPMIXR_TO_HPOUTR_PGA */ 2266*4882a593Smuzhiyun #define WM8962_HPMIXR_TO_HPOUTR_PGA_MASK 0x0080 /* HPMIXR_TO_HPOUTR_PGA */ 2267*4882a593Smuzhiyun #define WM8962_HPMIXR_TO_HPOUTR_PGA_SHIFT 7 /* HPMIXR_TO_HPOUTR_PGA */ 2268*4882a593Smuzhiyun #define WM8962_HPMIXR_TO_HPOUTR_PGA_WIDTH 1 /* HPMIXR_TO_HPOUTR_PGA */ 2269*4882a593Smuzhiyun #define WM8962_DACL_TO_HPMIXR 0x0020 /* DACL_TO_HPMIXR */ 2270*4882a593Smuzhiyun #define WM8962_DACL_TO_HPMIXR_MASK 0x0020 /* DACL_TO_HPMIXR */ 2271*4882a593Smuzhiyun #define WM8962_DACL_TO_HPMIXR_SHIFT 5 /* DACL_TO_HPMIXR */ 2272*4882a593Smuzhiyun #define WM8962_DACL_TO_HPMIXR_WIDTH 1 /* DACL_TO_HPMIXR */ 2273*4882a593Smuzhiyun #define WM8962_DACR_TO_HPMIXR 0x0010 /* DACR_TO_HPMIXR */ 2274*4882a593Smuzhiyun #define WM8962_DACR_TO_HPMIXR_MASK 0x0010 /* DACR_TO_HPMIXR */ 2275*4882a593Smuzhiyun #define WM8962_DACR_TO_HPMIXR_SHIFT 4 /* DACR_TO_HPMIXR */ 2276*4882a593Smuzhiyun #define WM8962_DACR_TO_HPMIXR_WIDTH 1 /* DACR_TO_HPMIXR */ 2277*4882a593Smuzhiyun #define WM8962_MIXINL_TO_HPMIXR 0x0008 /* MIXINL_TO_HPMIXR */ 2278*4882a593Smuzhiyun #define WM8962_MIXINL_TO_HPMIXR_MASK 0x0008 /* MIXINL_TO_HPMIXR */ 2279*4882a593Smuzhiyun #define WM8962_MIXINL_TO_HPMIXR_SHIFT 3 /* MIXINL_TO_HPMIXR */ 2280*4882a593Smuzhiyun #define WM8962_MIXINL_TO_HPMIXR_WIDTH 1 /* MIXINL_TO_HPMIXR */ 2281*4882a593Smuzhiyun #define WM8962_MIXINR_TO_HPMIXR 0x0004 /* MIXINR_TO_HPMIXR */ 2282*4882a593Smuzhiyun #define WM8962_MIXINR_TO_HPMIXR_MASK 0x0004 /* MIXINR_TO_HPMIXR */ 2283*4882a593Smuzhiyun #define WM8962_MIXINR_TO_HPMIXR_SHIFT 2 /* MIXINR_TO_HPMIXR */ 2284*4882a593Smuzhiyun #define WM8962_MIXINR_TO_HPMIXR_WIDTH 1 /* MIXINR_TO_HPMIXR */ 2285*4882a593Smuzhiyun #define WM8962_IN4L_TO_HPMIXR 0x0002 /* IN4L_TO_HPMIXR */ 2286*4882a593Smuzhiyun #define WM8962_IN4L_TO_HPMIXR_MASK 0x0002 /* IN4L_TO_HPMIXR */ 2287*4882a593Smuzhiyun #define WM8962_IN4L_TO_HPMIXR_SHIFT 1 /* IN4L_TO_HPMIXR */ 2288*4882a593Smuzhiyun #define WM8962_IN4L_TO_HPMIXR_WIDTH 1 /* IN4L_TO_HPMIXR */ 2289*4882a593Smuzhiyun #define WM8962_IN4R_TO_HPMIXR 0x0001 /* IN4R_TO_HPMIXR */ 2290*4882a593Smuzhiyun #define WM8962_IN4R_TO_HPMIXR_MASK 0x0001 /* IN4R_TO_HPMIXR */ 2291*4882a593Smuzhiyun #define WM8962_IN4R_TO_HPMIXR_SHIFT 0 /* IN4R_TO_HPMIXR */ 2292*4882a593Smuzhiyun #define WM8962_IN4R_TO_HPMIXR_WIDTH 1 /* IN4R_TO_HPMIXR */ 2293*4882a593Smuzhiyun 2294*4882a593Smuzhiyun /* 2295*4882a593Smuzhiyun * R102 (0x66) - Headphone Mixer (3) 2296*4882a593Smuzhiyun */ 2297*4882a593Smuzhiyun #define WM8962_HPMIXL_MUTE 0x0100 /* HPMIXL_MUTE */ 2298*4882a593Smuzhiyun #define WM8962_HPMIXL_MUTE_MASK 0x0100 /* HPMIXL_MUTE */ 2299*4882a593Smuzhiyun #define WM8962_HPMIXL_MUTE_SHIFT 8 /* HPMIXL_MUTE */ 2300*4882a593Smuzhiyun #define WM8962_HPMIXL_MUTE_WIDTH 1 /* HPMIXL_MUTE */ 2301*4882a593Smuzhiyun #define WM8962_MIXINL_HPMIXL_VOL 0x0080 /* MIXINL_HPMIXL_VOL */ 2302*4882a593Smuzhiyun #define WM8962_MIXINL_HPMIXL_VOL_MASK 0x0080 /* MIXINL_HPMIXL_VOL */ 2303*4882a593Smuzhiyun #define WM8962_MIXINL_HPMIXL_VOL_SHIFT 7 /* MIXINL_HPMIXL_VOL */ 2304*4882a593Smuzhiyun #define WM8962_MIXINL_HPMIXL_VOL_WIDTH 1 /* MIXINL_HPMIXL_VOL */ 2305*4882a593Smuzhiyun #define WM8962_MIXINR_HPMIXL_VOL 0x0040 /* MIXINR_HPMIXL_VOL */ 2306*4882a593Smuzhiyun #define WM8962_MIXINR_HPMIXL_VOL_MASK 0x0040 /* MIXINR_HPMIXL_VOL */ 2307*4882a593Smuzhiyun #define WM8962_MIXINR_HPMIXL_VOL_SHIFT 6 /* MIXINR_HPMIXL_VOL */ 2308*4882a593Smuzhiyun #define WM8962_MIXINR_HPMIXL_VOL_WIDTH 1 /* MIXINR_HPMIXL_VOL */ 2309*4882a593Smuzhiyun #define WM8962_IN4L_HPMIXL_VOL_MASK 0x0038 /* IN4L_HPMIXL_VOL - [5:3] */ 2310*4882a593Smuzhiyun #define WM8962_IN4L_HPMIXL_VOL_SHIFT 3 /* IN4L_HPMIXL_VOL - [5:3] */ 2311*4882a593Smuzhiyun #define WM8962_IN4L_HPMIXL_VOL_WIDTH 3 /* IN4L_HPMIXL_VOL - [5:3] */ 2312*4882a593Smuzhiyun #define WM8962_IN4R_HPMIXL_VOL_MASK 0x0007 /* IN4R_HPMIXL_VOL - [2:0] */ 2313*4882a593Smuzhiyun #define WM8962_IN4R_HPMIXL_VOL_SHIFT 0 /* IN4R_HPMIXL_VOL - [2:0] */ 2314*4882a593Smuzhiyun #define WM8962_IN4R_HPMIXL_VOL_WIDTH 3 /* IN4R_HPMIXL_VOL - [2:0] */ 2315*4882a593Smuzhiyun 2316*4882a593Smuzhiyun /* 2317*4882a593Smuzhiyun * R103 (0x67) - Headphone Mixer (4) 2318*4882a593Smuzhiyun */ 2319*4882a593Smuzhiyun #define WM8962_HPMIXR_MUTE 0x0100 /* HPMIXR_MUTE */ 2320*4882a593Smuzhiyun #define WM8962_HPMIXR_MUTE_MASK 0x0100 /* HPMIXR_MUTE */ 2321*4882a593Smuzhiyun #define WM8962_HPMIXR_MUTE_SHIFT 8 /* HPMIXR_MUTE */ 2322*4882a593Smuzhiyun #define WM8962_HPMIXR_MUTE_WIDTH 1 /* HPMIXR_MUTE */ 2323*4882a593Smuzhiyun #define WM8962_MIXINL_HPMIXR_VOL 0x0080 /* MIXINL_HPMIXR_VOL */ 2324*4882a593Smuzhiyun #define WM8962_MIXINL_HPMIXR_VOL_MASK 0x0080 /* MIXINL_HPMIXR_VOL */ 2325*4882a593Smuzhiyun #define WM8962_MIXINL_HPMIXR_VOL_SHIFT 7 /* MIXINL_HPMIXR_VOL */ 2326*4882a593Smuzhiyun #define WM8962_MIXINL_HPMIXR_VOL_WIDTH 1 /* MIXINL_HPMIXR_VOL */ 2327*4882a593Smuzhiyun #define WM8962_MIXINR_HPMIXR_VOL 0x0040 /* MIXINR_HPMIXR_VOL */ 2328*4882a593Smuzhiyun #define WM8962_MIXINR_HPMIXR_VOL_MASK 0x0040 /* MIXINR_HPMIXR_VOL */ 2329*4882a593Smuzhiyun #define WM8962_MIXINR_HPMIXR_VOL_SHIFT 6 /* MIXINR_HPMIXR_VOL */ 2330*4882a593Smuzhiyun #define WM8962_MIXINR_HPMIXR_VOL_WIDTH 1 /* MIXINR_HPMIXR_VOL */ 2331*4882a593Smuzhiyun #define WM8962_IN4L_HPMIXR_VOL_MASK 0x0038 /* IN4L_HPMIXR_VOL - [5:3] */ 2332*4882a593Smuzhiyun #define WM8962_IN4L_HPMIXR_VOL_SHIFT 3 /* IN4L_HPMIXR_VOL - [5:3] */ 2333*4882a593Smuzhiyun #define WM8962_IN4L_HPMIXR_VOL_WIDTH 3 /* IN4L_HPMIXR_VOL - [5:3] */ 2334*4882a593Smuzhiyun #define WM8962_IN4R_HPMIXR_VOL_MASK 0x0007 /* IN4R_HPMIXR_VOL - [2:0] */ 2335*4882a593Smuzhiyun #define WM8962_IN4R_HPMIXR_VOL_SHIFT 0 /* IN4R_HPMIXR_VOL - [2:0] */ 2336*4882a593Smuzhiyun #define WM8962_IN4R_HPMIXR_VOL_WIDTH 3 /* IN4R_HPMIXR_VOL - [2:0] */ 2337*4882a593Smuzhiyun 2338*4882a593Smuzhiyun /* 2339*4882a593Smuzhiyun * R105 (0x69) - Speaker Mixer (1) 2340*4882a593Smuzhiyun */ 2341*4882a593Smuzhiyun #define WM8962_SPKMIXL_TO_SPKOUTL_PGA 0x0080 /* SPKMIXL_TO_SPKOUTL_PGA */ 2342*4882a593Smuzhiyun #define WM8962_SPKMIXL_TO_SPKOUTL_PGA_MASK 0x0080 /* SPKMIXL_TO_SPKOUTL_PGA */ 2343*4882a593Smuzhiyun #define WM8962_SPKMIXL_TO_SPKOUTL_PGA_SHIFT 7 /* SPKMIXL_TO_SPKOUTL_PGA */ 2344*4882a593Smuzhiyun #define WM8962_SPKMIXL_TO_SPKOUTL_PGA_WIDTH 1 /* SPKMIXL_TO_SPKOUTL_PGA */ 2345*4882a593Smuzhiyun #define WM8962_DACL_TO_SPKMIXL 0x0020 /* DACL_TO_SPKMIXL */ 2346*4882a593Smuzhiyun #define WM8962_DACL_TO_SPKMIXL_MASK 0x0020 /* DACL_TO_SPKMIXL */ 2347*4882a593Smuzhiyun #define WM8962_DACL_TO_SPKMIXL_SHIFT 5 /* DACL_TO_SPKMIXL */ 2348*4882a593Smuzhiyun #define WM8962_DACL_TO_SPKMIXL_WIDTH 1 /* DACL_TO_SPKMIXL */ 2349*4882a593Smuzhiyun #define WM8962_DACR_TO_SPKMIXL 0x0010 /* DACR_TO_SPKMIXL */ 2350*4882a593Smuzhiyun #define WM8962_DACR_TO_SPKMIXL_MASK 0x0010 /* DACR_TO_SPKMIXL */ 2351*4882a593Smuzhiyun #define WM8962_DACR_TO_SPKMIXL_SHIFT 4 /* DACR_TO_SPKMIXL */ 2352*4882a593Smuzhiyun #define WM8962_DACR_TO_SPKMIXL_WIDTH 1 /* DACR_TO_SPKMIXL */ 2353*4882a593Smuzhiyun #define WM8962_MIXINL_TO_SPKMIXL 0x0008 /* MIXINL_TO_SPKMIXL */ 2354*4882a593Smuzhiyun #define WM8962_MIXINL_TO_SPKMIXL_MASK 0x0008 /* MIXINL_TO_SPKMIXL */ 2355*4882a593Smuzhiyun #define WM8962_MIXINL_TO_SPKMIXL_SHIFT 3 /* MIXINL_TO_SPKMIXL */ 2356*4882a593Smuzhiyun #define WM8962_MIXINL_TO_SPKMIXL_WIDTH 1 /* MIXINL_TO_SPKMIXL */ 2357*4882a593Smuzhiyun #define WM8962_MIXINR_TO_SPKMIXL 0x0004 /* MIXINR_TO_SPKMIXL */ 2358*4882a593Smuzhiyun #define WM8962_MIXINR_TO_SPKMIXL_MASK 0x0004 /* MIXINR_TO_SPKMIXL */ 2359*4882a593Smuzhiyun #define WM8962_MIXINR_TO_SPKMIXL_SHIFT 2 /* MIXINR_TO_SPKMIXL */ 2360*4882a593Smuzhiyun #define WM8962_MIXINR_TO_SPKMIXL_WIDTH 1 /* MIXINR_TO_SPKMIXL */ 2361*4882a593Smuzhiyun #define WM8962_IN4L_TO_SPKMIXL 0x0002 /* IN4L_TO_SPKMIXL */ 2362*4882a593Smuzhiyun #define WM8962_IN4L_TO_SPKMIXL_MASK 0x0002 /* IN4L_TO_SPKMIXL */ 2363*4882a593Smuzhiyun #define WM8962_IN4L_TO_SPKMIXL_SHIFT 1 /* IN4L_TO_SPKMIXL */ 2364*4882a593Smuzhiyun #define WM8962_IN4L_TO_SPKMIXL_WIDTH 1 /* IN4L_TO_SPKMIXL */ 2365*4882a593Smuzhiyun #define WM8962_IN4R_TO_SPKMIXL 0x0001 /* IN4R_TO_SPKMIXL */ 2366*4882a593Smuzhiyun #define WM8962_IN4R_TO_SPKMIXL_MASK 0x0001 /* IN4R_TO_SPKMIXL */ 2367*4882a593Smuzhiyun #define WM8962_IN4R_TO_SPKMIXL_SHIFT 0 /* IN4R_TO_SPKMIXL */ 2368*4882a593Smuzhiyun #define WM8962_IN4R_TO_SPKMIXL_WIDTH 1 /* IN4R_TO_SPKMIXL */ 2369*4882a593Smuzhiyun 2370*4882a593Smuzhiyun /* 2371*4882a593Smuzhiyun * R106 (0x6A) - Speaker Mixer (2) 2372*4882a593Smuzhiyun */ 2373*4882a593Smuzhiyun #define WM8962_SPKMIXR_TO_SPKOUTR_PGA 0x0080 /* SPKMIXR_TO_SPKOUTR_PGA */ 2374*4882a593Smuzhiyun #define WM8962_SPKMIXR_TO_SPKOUTR_PGA_MASK 0x0080 /* SPKMIXR_TO_SPKOUTR_PGA */ 2375*4882a593Smuzhiyun #define WM8962_SPKMIXR_TO_SPKOUTR_PGA_SHIFT 7 /* SPKMIXR_TO_SPKOUTR_PGA */ 2376*4882a593Smuzhiyun #define WM8962_SPKMIXR_TO_SPKOUTR_PGA_WIDTH 1 /* SPKMIXR_TO_SPKOUTR_PGA */ 2377*4882a593Smuzhiyun #define WM8962_DACL_TO_SPKMIXR 0x0020 /* DACL_TO_SPKMIXR */ 2378*4882a593Smuzhiyun #define WM8962_DACL_TO_SPKMIXR_MASK 0x0020 /* DACL_TO_SPKMIXR */ 2379*4882a593Smuzhiyun #define WM8962_DACL_TO_SPKMIXR_SHIFT 5 /* DACL_TO_SPKMIXR */ 2380*4882a593Smuzhiyun #define WM8962_DACL_TO_SPKMIXR_WIDTH 1 /* DACL_TO_SPKMIXR */ 2381*4882a593Smuzhiyun #define WM8962_DACR_TO_SPKMIXR 0x0010 /* DACR_TO_SPKMIXR */ 2382*4882a593Smuzhiyun #define WM8962_DACR_TO_SPKMIXR_MASK 0x0010 /* DACR_TO_SPKMIXR */ 2383*4882a593Smuzhiyun #define WM8962_DACR_TO_SPKMIXR_SHIFT 4 /* DACR_TO_SPKMIXR */ 2384*4882a593Smuzhiyun #define WM8962_DACR_TO_SPKMIXR_WIDTH 1 /* DACR_TO_SPKMIXR */ 2385*4882a593Smuzhiyun #define WM8962_MIXINL_TO_SPKMIXR 0x0008 /* MIXINL_TO_SPKMIXR */ 2386*4882a593Smuzhiyun #define WM8962_MIXINL_TO_SPKMIXR_MASK 0x0008 /* MIXINL_TO_SPKMIXR */ 2387*4882a593Smuzhiyun #define WM8962_MIXINL_TO_SPKMIXR_SHIFT 3 /* MIXINL_TO_SPKMIXR */ 2388*4882a593Smuzhiyun #define WM8962_MIXINL_TO_SPKMIXR_WIDTH 1 /* MIXINL_TO_SPKMIXR */ 2389*4882a593Smuzhiyun #define WM8962_MIXINR_TO_SPKMIXR 0x0004 /* MIXINR_TO_SPKMIXR */ 2390*4882a593Smuzhiyun #define WM8962_MIXINR_TO_SPKMIXR_MASK 0x0004 /* MIXINR_TO_SPKMIXR */ 2391*4882a593Smuzhiyun #define WM8962_MIXINR_TO_SPKMIXR_SHIFT 2 /* MIXINR_TO_SPKMIXR */ 2392*4882a593Smuzhiyun #define WM8962_MIXINR_TO_SPKMIXR_WIDTH 1 /* MIXINR_TO_SPKMIXR */ 2393*4882a593Smuzhiyun #define WM8962_IN4L_TO_SPKMIXR 0x0002 /* IN4L_TO_SPKMIXR */ 2394*4882a593Smuzhiyun #define WM8962_IN4L_TO_SPKMIXR_MASK 0x0002 /* IN4L_TO_SPKMIXR */ 2395*4882a593Smuzhiyun #define WM8962_IN4L_TO_SPKMIXR_SHIFT 1 /* IN4L_TO_SPKMIXR */ 2396*4882a593Smuzhiyun #define WM8962_IN4L_TO_SPKMIXR_WIDTH 1 /* IN4L_TO_SPKMIXR */ 2397*4882a593Smuzhiyun #define WM8962_IN4R_TO_SPKMIXR 0x0001 /* IN4R_TO_SPKMIXR */ 2398*4882a593Smuzhiyun #define WM8962_IN4R_TO_SPKMIXR_MASK 0x0001 /* IN4R_TO_SPKMIXR */ 2399*4882a593Smuzhiyun #define WM8962_IN4R_TO_SPKMIXR_SHIFT 0 /* IN4R_TO_SPKMIXR */ 2400*4882a593Smuzhiyun #define WM8962_IN4R_TO_SPKMIXR_WIDTH 1 /* IN4R_TO_SPKMIXR */ 2401*4882a593Smuzhiyun 2402*4882a593Smuzhiyun /* 2403*4882a593Smuzhiyun * R107 (0x6B) - Speaker Mixer (3) 2404*4882a593Smuzhiyun */ 2405*4882a593Smuzhiyun #define WM8962_SPKMIXL_MUTE 0x0100 /* SPKMIXL_MUTE */ 2406*4882a593Smuzhiyun #define WM8962_SPKMIXL_MUTE_MASK 0x0100 /* SPKMIXL_MUTE */ 2407*4882a593Smuzhiyun #define WM8962_SPKMIXL_MUTE_SHIFT 8 /* SPKMIXL_MUTE */ 2408*4882a593Smuzhiyun #define WM8962_SPKMIXL_MUTE_WIDTH 1 /* SPKMIXL_MUTE */ 2409*4882a593Smuzhiyun #define WM8962_MIXINL_SPKMIXL_VOL 0x0080 /* MIXINL_SPKMIXL_VOL */ 2410*4882a593Smuzhiyun #define WM8962_MIXINL_SPKMIXL_VOL_MASK 0x0080 /* MIXINL_SPKMIXL_VOL */ 2411*4882a593Smuzhiyun #define WM8962_MIXINL_SPKMIXL_VOL_SHIFT 7 /* MIXINL_SPKMIXL_VOL */ 2412*4882a593Smuzhiyun #define WM8962_MIXINL_SPKMIXL_VOL_WIDTH 1 /* MIXINL_SPKMIXL_VOL */ 2413*4882a593Smuzhiyun #define WM8962_MIXINR_SPKMIXL_VOL 0x0040 /* MIXINR_SPKMIXL_VOL */ 2414*4882a593Smuzhiyun #define WM8962_MIXINR_SPKMIXL_VOL_MASK 0x0040 /* MIXINR_SPKMIXL_VOL */ 2415*4882a593Smuzhiyun #define WM8962_MIXINR_SPKMIXL_VOL_SHIFT 6 /* MIXINR_SPKMIXL_VOL */ 2416*4882a593Smuzhiyun #define WM8962_MIXINR_SPKMIXL_VOL_WIDTH 1 /* MIXINR_SPKMIXL_VOL */ 2417*4882a593Smuzhiyun #define WM8962_IN4L_SPKMIXL_VOL_MASK 0x0038 /* IN4L_SPKMIXL_VOL - [5:3] */ 2418*4882a593Smuzhiyun #define WM8962_IN4L_SPKMIXL_VOL_SHIFT 3 /* IN4L_SPKMIXL_VOL - [5:3] */ 2419*4882a593Smuzhiyun #define WM8962_IN4L_SPKMIXL_VOL_WIDTH 3 /* IN4L_SPKMIXL_VOL - [5:3] */ 2420*4882a593Smuzhiyun #define WM8962_IN4R_SPKMIXL_VOL_MASK 0x0007 /* IN4R_SPKMIXL_VOL - [2:0] */ 2421*4882a593Smuzhiyun #define WM8962_IN4R_SPKMIXL_VOL_SHIFT 0 /* IN4R_SPKMIXL_VOL - [2:0] */ 2422*4882a593Smuzhiyun #define WM8962_IN4R_SPKMIXL_VOL_WIDTH 3 /* IN4R_SPKMIXL_VOL - [2:0] */ 2423*4882a593Smuzhiyun 2424*4882a593Smuzhiyun /* 2425*4882a593Smuzhiyun * R108 (0x6C) - Speaker Mixer (4) 2426*4882a593Smuzhiyun */ 2427*4882a593Smuzhiyun #define WM8962_SPKMIXR_MUTE 0x0100 /* SPKMIXR_MUTE */ 2428*4882a593Smuzhiyun #define WM8962_SPKMIXR_MUTE_MASK 0x0100 /* SPKMIXR_MUTE */ 2429*4882a593Smuzhiyun #define WM8962_SPKMIXR_MUTE_SHIFT 8 /* SPKMIXR_MUTE */ 2430*4882a593Smuzhiyun #define WM8962_SPKMIXR_MUTE_WIDTH 1 /* SPKMIXR_MUTE */ 2431*4882a593Smuzhiyun #define WM8962_MIXINL_SPKMIXR_VOL 0x0080 /* MIXINL_SPKMIXR_VOL */ 2432*4882a593Smuzhiyun #define WM8962_MIXINL_SPKMIXR_VOL_MASK 0x0080 /* MIXINL_SPKMIXR_VOL */ 2433*4882a593Smuzhiyun #define WM8962_MIXINL_SPKMIXR_VOL_SHIFT 7 /* MIXINL_SPKMIXR_VOL */ 2434*4882a593Smuzhiyun #define WM8962_MIXINL_SPKMIXR_VOL_WIDTH 1 /* MIXINL_SPKMIXR_VOL */ 2435*4882a593Smuzhiyun #define WM8962_MIXINR_SPKMIXR_VOL 0x0040 /* MIXINR_SPKMIXR_VOL */ 2436*4882a593Smuzhiyun #define WM8962_MIXINR_SPKMIXR_VOL_MASK 0x0040 /* MIXINR_SPKMIXR_VOL */ 2437*4882a593Smuzhiyun #define WM8962_MIXINR_SPKMIXR_VOL_SHIFT 6 /* MIXINR_SPKMIXR_VOL */ 2438*4882a593Smuzhiyun #define WM8962_MIXINR_SPKMIXR_VOL_WIDTH 1 /* MIXINR_SPKMIXR_VOL */ 2439*4882a593Smuzhiyun #define WM8962_IN4L_SPKMIXR_VOL_MASK 0x0038 /* IN4L_SPKMIXR_VOL - [5:3] */ 2440*4882a593Smuzhiyun #define WM8962_IN4L_SPKMIXR_VOL_SHIFT 3 /* IN4L_SPKMIXR_VOL - [5:3] */ 2441*4882a593Smuzhiyun #define WM8962_IN4L_SPKMIXR_VOL_WIDTH 3 /* IN4L_SPKMIXR_VOL - [5:3] */ 2442*4882a593Smuzhiyun #define WM8962_IN4R_SPKMIXR_VOL_MASK 0x0007 /* IN4R_SPKMIXR_VOL - [2:0] */ 2443*4882a593Smuzhiyun #define WM8962_IN4R_SPKMIXR_VOL_SHIFT 0 /* IN4R_SPKMIXR_VOL - [2:0] */ 2444*4882a593Smuzhiyun #define WM8962_IN4R_SPKMIXR_VOL_WIDTH 3 /* IN4R_SPKMIXR_VOL - [2:0] */ 2445*4882a593Smuzhiyun 2446*4882a593Smuzhiyun /* 2447*4882a593Smuzhiyun * R109 (0x6D) - Speaker Mixer (5) 2448*4882a593Smuzhiyun */ 2449*4882a593Smuzhiyun #define WM8962_DACL_SPKMIXL_VOL 0x0080 /* DACL_SPKMIXL_VOL */ 2450*4882a593Smuzhiyun #define WM8962_DACL_SPKMIXL_VOL_MASK 0x0080 /* DACL_SPKMIXL_VOL */ 2451*4882a593Smuzhiyun #define WM8962_DACL_SPKMIXL_VOL_SHIFT 7 /* DACL_SPKMIXL_VOL */ 2452*4882a593Smuzhiyun #define WM8962_DACL_SPKMIXL_VOL_WIDTH 1 /* DACL_SPKMIXL_VOL */ 2453*4882a593Smuzhiyun #define WM8962_DACR_SPKMIXL_VOL 0x0040 /* DACR_SPKMIXL_VOL */ 2454*4882a593Smuzhiyun #define WM8962_DACR_SPKMIXL_VOL_MASK 0x0040 /* DACR_SPKMIXL_VOL */ 2455*4882a593Smuzhiyun #define WM8962_DACR_SPKMIXL_VOL_SHIFT 6 /* DACR_SPKMIXL_VOL */ 2456*4882a593Smuzhiyun #define WM8962_DACR_SPKMIXL_VOL_WIDTH 1 /* DACR_SPKMIXL_VOL */ 2457*4882a593Smuzhiyun #define WM8962_DACL_SPKMIXR_VOL 0x0020 /* DACL_SPKMIXR_VOL */ 2458*4882a593Smuzhiyun #define WM8962_DACL_SPKMIXR_VOL_MASK 0x0020 /* DACL_SPKMIXR_VOL */ 2459*4882a593Smuzhiyun #define WM8962_DACL_SPKMIXR_VOL_SHIFT 5 /* DACL_SPKMIXR_VOL */ 2460*4882a593Smuzhiyun #define WM8962_DACL_SPKMIXR_VOL_WIDTH 1 /* DACL_SPKMIXR_VOL */ 2461*4882a593Smuzhiyun #define WM8962_DACR_SPKMIXR_VOL 0x0010 /* DACR_SPKMIXR_VOL */ 2462*4882a593Smuzhiyun #define WM8962_DACR_SPKMIXR_VOL_MASK 0x0010 /* DACR_SPKMIXR_VOL */ 2463*4882a593Smuzhiyun #define WM8962_DACR_SPKMIXR_VOL_SHIFT 4 /* DACR_SPKMIXR_VOL */ 2464*4882a593Smuzhiyun #define WM8962_DACR_SPKMIXR_VOL_WIDTH 1 /* DACR_SPKMIXR_VOL */ 2465*4882a593Smuzhiyun 2466*4882a593Smuzhiyun /* 2467*4882a593Smuzhiyun * R110 (0x6E) - Beep Generator (1) 2468*4882a593Smuzhiyun */ 2469*4882a593Smuzhiyun #define WM8962_BEEP_GAIN_MASK 0x00F0 /* BEEP_GAIN - [7:4] */ 2470*4882a593Smuzhiyun #define WM8962_BEEP_GAIN_SHIFT 4 /* BEEP_GAIN - [7:4] */ 2471*4882a593Smuzhiyun #define WM8962_BEEP_GAIN_WIDTH 4 /* BEEP_GAIN - [7:4] */ 2472*4882a593Smuzhiyun #define WM8962_BEEP_RATE_MASK 0x0006 /* BEEP_RATE - [2:1] */ 2473*4882a593Smuzhiyun #define WM8962_BEEP_RATE_SHIFT 1 /* BEEP_RATE - [2:1] */ 2474*4882a593Smuzhiyun #define WM8962_BEEP_RATE_WIDTH 2 /* BEEP_RATE - [2:1] */ 2475*4882a593Smuzhiyun #define WM8962_BEEP_ENA 0x0001 /* BEEP_ENA */ 2476*4882a593Smuzhiyun #define WM8962_BEEP_ENA_MASK 0x0001 /* BEEP_ENA */ 2477*4882a593Smuzhiyun #define WM8962_BEEP_ENA_SHIFT 0 /* BEEP_ENA */ 2478*4882a593Smuzhiyun #define WM8962_BEEP_ENA_WIDTH 1 /* BEEP_ENA */ 2479*4882a593Smuzhiyun 2480*4882a593Smuzhiyun /* 2481*4882a593Smuzhiyun * R115 (0x73) - Oscillator Trim (3) 2482*4882a593Smuzhiyun */ 2483*4882a593Smuzhiyun #define WM8962_OSC_TRIM_XTI_MASK 0x001F /* OSC_TRIM_XTI - [4:0] */ 2484*4882a593Smuzhiyun #define WM8962_OSC_TRIM_XTI_SHIFT 0 /* OSC_TRIM_XTI - [4:0] */ 2485*4882a593Smuzhiyun #define WM8962_OSC_TRIM_XTI_WIDTH 5 /* OSC_TRIM_XTI - [4:0] */ 2486*4882a593Smuzhiyun 2487*4882a593Smuzhiyun /* 2488*4882a593Smuzhiyun * R116 (0x74) - Oscillator Trim (4) 2489*4882a593Smuzhiyun */ 2490*4882a593Smuzhiyun #define WM8962_OSC_TRIM_XTO_MASK 0x001F /* OSC_TRIM_XTO - [4:0] */ 2491*4882a593Smuzhiyun #define WM8962_OSC_TRIM_XTO_SHIFT 0 /* OSC_TRIM_XTO - [4:0] */ 2492*4882a593Smuzhiyun #define WM8962_OSC_TRIM_XTO_WIDTH 5 /* OSC_TRIM_XTO - [4:0] */ 2493*4882a593Smuzhiyun 2494*4882a593Smuzhiyun /* 2495*4882a593Smuzhiyun * R119 (0x77) - Oscillator Trim (7) 2496*4882a593Smuzhiyun */ 2497*4882a593Smuzhiyun #define WM8962_XTO_CAP_SEL_MASK 0x00F0 /* XTO_CAP_SEL - [7:4] */ 2498*4882a593Smuzhiyun #define WM8962_XTO_CAP_SEL_SHIFT 4 /* XTO_CAP_SEL - [7:4] */ 2499*4882a593Smuzhiyun #define WM8962_XTO_CAP_SEL_WIDTH 4 /* XTO_CAP_SEL - [7:4] */ 2500*4882a593Smuzhiyun #define WM8962_XTI_CAP_SEL_MASK 0x000F /* XTI_CAP_SEL - [3:0] */ 2501*4882a593Smuzhiyun #define WM8962_XTI_CAP_SEL_SHIFT 0 /* XTI_CAP_SEL - [3:0] */ 2502*4882a593Smuzhiyun #define WM8962_XTI_CAP_SEL_WIDTH 4 /* XTI_CAP_SEL - [3:0] */ 2503*4882a593Smuzhiyun 2504*4882a593Smuzhiyun /* 2505*4882a593Smuzhiyun * R124 (0x7C) - Analogue Clocking1 2506*4882a593Smuzhiyun */ 2507*4882a593Smuzhiyun #define WM8962_CLKOUT2_SEL_MASK 0x0060 /* CLKOUT2_SEL - [6:5] */ 2508*4882a593Smuzhiyun #define WM8962_CLKOUT2_SEL_SHIFT 5 /* CLKOUT2_SEL - [6:5] */ 2509*4882a593Smuzhiyun #define WM8962_CLKOUT2_SEL_WIDTH 2 /* CLKOUT2_SEL - [6:5] */ 2510*4882a593Smuzhiyun #define WM8962_CLKOUT3_SEL_MASK 0x0018 /* CLKOUT3_SEL - [4:3] */ 2511*4882a593Smuzhiyun #define WM8962_CLKOUT3_SEL_SHIFT 3 /* CLKOUT3_SEL - [4:3] */ 2512*4882a593Smuzhiyun #define WM8962_CLKOUT3_SEL_WIDTH 2 /* CLKOUT3_SEL - [4:3] */ 2513*4882a593Smuzhiyun #define WM8962_CLKOUT5_SEL 0x0001 /* CLKOUT5_SEL */ 2514*4882a593Smuzhiyun #define WM8962_CLKOUT5_SEL_MASK 0x0001 /* CLKOUT5_SEL */ 2515*4882a593Smuzhiyun #define WM8962_CLKOUT5_SEL_SHIFT 0 /* CLKOUT5_SEL */ 2516*4882a593Smuzhiyun #define WM8962_CLKOUT5_SEL_WIDTH 1 /* CLKOUT5_SEL */ 2517*4882a593Smuzhiyun 2518*4882a593Smuzhiyun /* 2519*4882a593Smuzhiyun * R125 (0x7D) - Analogue Clocking2 2520*4882a593Smuzhiyun */ 2521*4882a593Smuzhiyun #define WM8962_PLL2_OUTDIV 0x0080 /* PLL2_OUTDIV */ 2522*4882a593Smuzhiyun #define WM8962_PLL2_OUTDIV_MASK 0x0080 /* PLL2_OUTDIV */ 2523*4882a593Smuzhiyun #define WM8962_PLL2_OUTDIV_SHIFT 7 /* PLL2_OUTDIV */ 2524*4882a593Smuzhiyun #define WM8962_PLL2_OUTDIV_WIDTH 1 /* PLL2_OUTDIV */ 2525*4882a593Smuzhiyun #define WM8962_PLL3_OUTDIV 0x0040 /* PLL3_OUTDIV */ 2526*4882a593Smuzhiyun #define WM8962_PLL3_OUTDIV_MASK 0x0040 /* PLL3_OUTDIV */ 2527*4882a593Smuzhiyun #define WM8962_PLL3_OUTDIV_SHIFT 6 /* PLL3_OUTDIV */ 2528*4882a593Smuzhiyun #define WM8962_PLL3_OUTDIV_WIDTH 1 /* PLL3_OUTDIV */ 2529*4882a593Smuzhiyun #define WM8962_PLL_SYSCLK_DIV_MASK 0x0018 /* PLL_SYSCLK_DIV - [4:3] */ 2530*4882a593Smuzhiyun #define WM8962_PLL_SYSCLK_DIV_SHIFT 3 /* PLL_SYSCLK_DIV - [4:3] */ 2531*4882a593Smuzhiyun #define WM8962_PLL_SYSCLK_DIV_WIDTH 2 /* PLL_SYSCLK_DIV - [4:3] */ 2532*4882a593Smuzhiyun #define WM8962_CLKOUT3_DIV 0x0004 /* CLKOUT3_DIV */ 2533*4882a593Smuzhiyun #define WM8962_CLKOUT3_DIV_MASK 0x0004 /* CLKOUT3_DIV */ 2534*4882a593Smuzhiyun #define WM8962_CLKOUT3_DIV_SHIFT 2 /* CLKOUT3_DIV */ 2535*4882a593Smuzhiyun #define WM8962_CLKOUT3_DIV_WIDTH 1 /* CLKOUT3_DIV */ 2536*4882a593Smuzhiyun #define WM8962_CLKOUT2_DIV 0x0002 /* CLKOUT2_DIV */ 2537*4882a593Smuzhiyun #define WM8962_CLKOUT2_DIV_MASK 0x0002 /* CLKOUT2_DIV */ 2538*4882a593Smuzhiyun #define WM8962_CLKOUT2_DIV_SHIFT 1 /* CLKOUT2_DIV */ 2539*4882a593Smuzhiyun #define WM8962_CLKOUT2_DIV_WIDTH 1 /* CLKOUT2_DIV */ 2540*4882a593Smuzhiyun #define WM8962_CLKOUT5_DIV 0x0001 /* CLKOUT5_DIV */ 2541*4882a593Smuzhiyun #define WM8962_CLKOUT5_DIV_MASK 0x0001 /* CLKOUT5_DIV */ 2542*4882a593Smuzhiyun #define WM8962_CLKOUT5_DIV_SHIFT 0 /* CLKOUT5_DIV */ 2543*4882a593Smuzhiyun #define WM8962_CLKOUT5_DIV_WIDTH 1 /* CLKOUT5_DIV */ 2544*4882a593Smuzhiyun 2545*4882a593Smuzhiyun /* 2546*4882a593Smuzhiyun * R126 (0x7E) - Analogue Clocking3 2547*4882a593Smuzhiyun */ 2548*4882a593Smuzhiyun #define WM8962_CLKOUT2_OE 0x0008 /* CLKOUT2_OE */ 2549*4882a593Smuzhiyun #define WM8962_CLKOUT2_OE_MASK 0x0008 /* CLKOUT2_OE */ 2550*4882a593Smuzhiyun #define WM8962_CLKOUT2_OE_SHIFT 3 /* CLKOUT2_OE */ 2551*4882a593Smuzhiyun #define WM8962_CLKOUT2_OE_WIDTH 1 /* CLKOUT2_OE */ 2552*4882a593Smuzhiyun #define WM8962_CLKOUT3_OE 0x0004 /* CLKOUT3_OE */ 2553*4882a593Smuzhiyun #define WM8962_CLKOUT3_OE_MASK 0x0004 /* CLKOUT3_OE */ 2554*4882a593Smuzhiyun #define WM8962_CLKOUT3_OE_SHIFT 2 /* CLKOUT3_OE */ 2555*4882a593Smuzhiyun #define WM8962_CLKOUT3_OE_WIDTH 1 /* CLKOUT3_OE */ 2556*4882a593Smuzhiyun #define WM8962_CLKOUT5_OE 0x0001 /* CLKOUT5_OE */ 2557*4882a593Smuzhiyun #define WM8962_CLKOUT5_OE_MASK 0x0001 /* CLKOUT5_OE */ 2558*4882a593Smuzhiyun #define WM8962_CLKOUT5_OE_SHIFT 0 /* CLKOUT5_OE */ 2559*4882a593Smuzhiyun #define WM8962_CLKOUT5_OE_WIDTH 1 /* CLKOUT5_OE */ 2560*4882a593Smuzhiyun 2561*4882a593Smuzhiyun /* 2562*4882a593Smuzhiyun * R127 (0x7F) - PLL Software Reset 2563*4882a593Smuzhiyun */ 2564*4882a593Smuzhiyun #define WM8962_SW_RESET_PLL_MASK 0xFFFF /* SW_RESET_PLL - [15:0] */ 2565*4882a593Smuzhiyun #define WM8962_SW_RESET_PLL_SHIFT 0 /* SW_RESET_PLL - [15:0] */ 2566*4882a593Smuzhiyun #define WM8962_SW_RESET_PLL_WIDTH 16 /* SW_RESET_PLL - [15:0] */ 2567*4882a593Smuzhiyun 2568*4882a593Smuzhiyun /* 2569*4882a593Smuzhiyun * R129 (0x81) - PLL2 2570*4882a593Smuzhiyun */ 2571*4882a593Smuzhiyun #define WM8962_OSC_ENA 0x0080 /* OSC_ENA */ 2572*4882a593Smuzhiyun #define WM8962_OSC_ENA_MASK 0x0080 /* OSC_ENA */ 2573*4882a593Smuzhiyun #define WM8962_OSC_ENA_SHIFT 7 /* OSC_ENA */ 2574*4882a593Smuzhiyun #define WM8962_OSC_ENA_WIDTH 1 /* OSC_ENA */ 2575*4882a593Smuzhiyun #define WM8962_PLL2_ENA 0x0020 /* PLL2_ENA */ 2576*4882a593Smuzhiyun #define WM8962_PLL2_ENA_MASK 0x0020 /* PLL2_ENA */ 2577*4882a593Smuzhiyun #define WM8962_PLL2_ENA_SHIFT 5 /* PLL2_ENA */ 2578*4882a593Smuzhiyun #define WM8962_PLL2_ENA_WIDTH 1 /* PLL2_ENA */ 2579*4882a593Smuzhiyun #define WM8962_PLL3_ENA 0x0010 /* PLL3_ENA */ 2580*4882a593Smuzhiyun #define WM8962_PLL3_ENA_MASK 0x0010 /* PLL3_ENA */ 2581*4882a593Smuzhiyun #define WM8962_PLL3_ENA_SHIFT 4 /* PLL3_ENA */ 2582*4882a593Smuzhiyun #define WM8962_PLL3_ENA_WIDTH 1 /* PLL3_ENA */ 2583*4882a593Smuzhiyun 2584*4882a593Smuzhiyun /* 2585*4882a593Smuzhiyun * R131 (0x83) - PLL 4 2586*4882a593Smuzhiyun */ 2587*4882a593Smuzhiyun #define WM8962_PLL_CLK_SRC 0x0002 /* PLL_CLK_SRC */ 2588*4882a593Smuzhiyun #define WM8962_PLL_CLK_SRC_MASK 0x0002 /* PLL_CLK_SRC */ 2589*4882a593Smuzhiyun #define WM8962_PLL_CLK_SRC_SHIFT 1 /* PLL_CLK_SRC */ 2590*4882a593Smuzhiyun #define WM8962_PLL_CLK_SRC_WIDTH 1 /* PLL_CLK_SRC */ 2591*4882a593Smuzhiyun #define WM8962_FLL_TO_PLL3 0x0001 /* FLL_TO_PLL3 */ 2592*4882a593Smuzhiyun #define WM8962_FLL_TO_PLL3_MASK 0x0001 /* FLL_TO_PLL3 */ 2593*4882a593Smuzhiyun #define WM8962_FLL_TO_PLL3_SHIFT 0 /* FLL_TO_PLL3 */ 2594*4882a593Smuzhiyun #define WM8962_FLL_TO_PLL3_WIDTH 1 /* FLL_TO_PLL3 */ 2595*4882a593Smuzhiyun 2596*4882a593Smuzhiyun /* 2597*4882a593Smuzhiyun * R136 (0x88) - PLL 9 2598*4882a593Smuzhiyun */ 2599*4882a593Smuzhiyun #define WM8962_PLL2_FRAC 0x0040 /* PLL2_FRAC */ 2600*4882a593Smuzhiyun #define WM8962_PLL2_FRAC_MASK 0x0040 /* PLL2_FRAC */ 2601*4882a593Smuzhiyun #define WM8962_PLL2_FRAC_SHIFT 6 /* PLL2_FRAC */ 2602*4882a593Smuzhiyun #define WM8962_PLL2_FRAC_WIDTH 1 /* PLL2_FRAC */ 2603*4882a593Smuzhiyun #define WM8962_PLL2_N_MASK 0x001F /* PLL2_N - [4:0] */ 2604*4882a593Smuzhiyun #define WM8962_PLL2_N_SHIFT 0 /* PLL2_N - [4:0] */ 2605*4882a593Smuzhiyun #define WM8962_PLL2_N_WIDTH 5 /* PLL2_N - [4:0] */ 2606*4882a593Smuzhiyun 2607*4882a593Smuzhiyun /* 2608*4882a593Smuzhiyun * R137 (0x89) - PLL 10 2609*4882a593Smuzhiyun */ 2610*4882a593Smuzhiyun #define WM8962_PLL2_K_MASK 0x00FF /* PLL2_K - [7:0] */ 2611*4882a593Smuzhiyun #define WM8962_PLL2_K_SHIFT 0 /* PLL2_K - [7:0] */ 2612*4882a593Smuzhiyun #define WM8962_PLL2_K_WIDTH 8 /* PLL2_K - [7:0] */ 2613*4882a593Smuzhiyun 2614*4882a593Smuzhiyun /* 2615*4882a593Smuzhiyun * R138 (0x8A) - PLL 11 2616*4882a593Smuzhiyun */ 2617*4882a593Smuzhiyun #define WM8962_PLL2_K_MASK 0x00FF /* PLL2_K - [7:0] */ 2618*4882a593Smuzhiyun #define WM8962_PLL2_K_SHIFT 0 /* PLL2_K - [7:0] */ 2619*4882a593Smuzhiyun #define WM8962_PLL2_K_WIDTH 8 /* PLL2_K - [7:0] */ 2620*4882a593Smuzhiyun 2621*4882a593Smuzhiyun /* 2622*4882a593Smuzhiyun * R139 (0x8B) - PLL 12 2623*4882a593Smuzhiyun */ 2624*4882a593Smuzhiyun #define WM8962_PLL2_K_MASK 0x00FF /* PLL2_K - [7:0] */ 2625*4882a593Smuzhiyun #define WM8962_PLL2_K_SHIFT 0 /* PLL2_K - [7:0] */ 2626*4882a593Smuzhiyun #define WM8962_PLL2_K_WIDTH 8 /* PLL2_K - [7:0] */ 2627*4882a593Smuzhiyun 2628*4882a593Smuzhiyun /* 2629*4882a593Smuzhiyun * R140 (0x8C) - PLL 13 2630*4882a593Smuzhiyun */ 2631*4882a593Smuzhiyun #define WM8962_PLL3_FRAC 0x0040 /* PLL3_FRAC */ 2632*4882a593Smuzhiyun #define WM8962_PLL3_FRAC_MASK 0x0040 /* PLL3_FRAC */ 2633*4882a593Smuzhiyun #define WM8962_PLL3_FRAC_SHIFT 6 /* PLL3_FRAC */ 2634*4882a593Smuzhiyun #define WM8962_PLL3_FRAC_WIDTH 1 /* PLL3_FRAC */ 2635*4882a593Smuzhiyun #define WM8962_PLL3_N_MASK 0x001F /* PLL3_N - [4:0] */ 2636*4882a593Smuzhiyun #define WM8962_PLL3_N_SHIFT 0 /* PLL3_N - [4:0] */ 2637*4882a593Smuzhiyun #define WM8962_PLL3_N_WIDTH 5 /* PLL3_N - [4:0] */ 2638*4882a593Smuzhiyun 2639*4882a593Smuzhiyun /* 2640*4882a593Smuzhiyun * R141 (0x8D) - PLL 14 2641*4882a593Smuzhiyun */ 2642*4882a593Smuzhiyun #define WM8962_PLL3_K_MASK 0x00FF /* PLL3_K - [7:0] */ 2643*4882a593Smuzhiyun #define WM8962_PLL3_K_SHIFT 0 /* PLL3_K - [7:0] */ 2644*4882a593Smuzhiyun #define WM8962_PLL3_K_WIDTH 8 /* PLL3_K - [7:0] */ 2645*4882a593Smuzhiyun 2646*4882a593Smuzhiyun /* 2647*4882a593Smuzhiyun * R142 (0x8E) - PLL 15 2648*4882a593Smuzhiyun */ 2649*4882a593Smuzhiyun #define WM8962_PLL3_K_MASK 0x00FF /* PLL3_K - [7:0] */ 2650*4882a593Smuzhiyun #define WM8962_PLL3_K_SHIFT 0 /* PLL3_K - [7:0] */ 2651*4882a593Smuzhiyun #define WM8962_PLL3_K_WIDTH 8 /* PLL3_K - [7:0] */ 2652*4882a593Smuzhiyun 2653*4882a593Smuzhiyun /* 2654*4882a593Smuzhiyun * R143 (0x8F) - PLL 16 2655*4882a593Smuzhiyun */ 2656*4882a593Smuzhiyun #define WM8962_PLL3_K_MASK 0x00FF /* PLL3_K - [7:0] */ 2657*4882a593Smuzhiyun #define WM8962_PLL3_K_SHIFT 0 /* PLL3_K - [7:0] */ 2658*4882a593Smuzhiyun #define WM8962_PLL3_K_WIDTH 8 /* PLL3_K - [7:0] */ 2659*4882a593Smuzhiyun 2660*4882a593Smuzhiyun /* 2661*4882a593Smuzhiyun * R155 (0x9B) - FLL Control (1) 2662*4882a593Smuzhiyun */ 2663*4882a593Smuzhiyun #define WM8962_FLL_REFCLK_SRC_MASK 0x0060 /* FLL_REFCLK_SRC - [6:5] */ 2664*4882a593Smuzhiyun #define WM8962_FLL_REFCLK_SRC_SHIFT 5 /* FLL_REFCLK_SRC - [6:5] */ 2665*4882a593Smuzhiyun #define WM8962_FLL_REFCLK_SRC_WIDTH 2 /* FLL_REFCLK_SRC - [6:5] */ 2666*4882a593Smuzhiyun #define WM8962_FLL_FRAC 0x0004 /* FLL_FRAC */ 2667*4882a593Smuzhiyun #define WM8962_FLL_FRAC_MASK 0x0004 /* FLL_FRAC */ 2668*4882a593Smuzhiyun #define WM8962_FLL_FRAC_SHIFT 2 /* FLL_FRAC */ 2669*4882a593Smuzhiyun #define WM8962_FLL_FRAC_WIDTH 1 /* FLL_FRAC */ 2670*4882a593Smuzhiyun #define WM8962_FLL_OSC_ENA 0x0002 /* FLL_OSC_ENA */ 2671*4882a593Smuzhiyun #define WM8962_FLL_OSC_ENA_MASK 0x0002 /* FLL_OSC_ENA */ 2672*4882a593Smuzhiyun #define WM8962_FLL_OSC_ENA_SHIFT 1 /* FLL_OSC_ENA */ 2673*4882a593Smuzhiyun #define WM8962_FLL_OSC_ENA_WIDTH 1 /* FLL_OSC_ENA */ 2674*4882a593Smuzhiyun #define WM8962_FLL_ENA 0x0001 /* FLL_ENA */ 2675*4882a593Smuzhiyun #define WM8962_FLL_ENA_MASK 0x0001 /* FLL_ENA */ 2676*4882a593Smuzhiyun #define WM8962_FLL_ENA_SHIFT 0 /* FLL_ENA */ 2677*4882a593Smuzhiyun #define WM8962_FLL_ENA_WIDTH 1 /* FLL_ENA */ 2678*4882a593Smuzhiyun 2679*4882a593Smuzhiyun /* 2680*4882a593Smuzhiyun * R156 (0x9C) - FLL Control (2) 2681*4882a593Smuzhiyun */ 2682*4882a593Smuzhiyun #define WM8962_FLL_OUTDIV_MASK 0x01F8 /* FLL_OUTDIV - [8:3] */ 2683*4882a593Smuzhiyun #define WM8962_FLL_OUTDIV_SHIFT 3 /* FLL_OUTDIV - [8:3] */ 2684*4882a593Smuzhiyun #define WM8962_FLL_OUTDIV_WIDTH 6 /* FLL_OUTDIV - [8:3] */ 2685*4882a593Smuzhiyun #define WM8962_FLL_REFCLK_DIV_MASK 0x0003 /* FLL_REFCLK_DIV - [1:0] */ 2686*4882a593Smuzhiyun #define WM8962_FLL_REFCLK_DIV_SHIFT 0 /* FLL_REFCLK_DIV - [1:0] */ 2687*4882a593Smuzhiyun #define WM8962_FLL_REFCLK_DIV_WIDTH 2 /* FLL_REFCLK_DIV - [1:0] */ 2688*4882a593Smuzhiyun 2689*4882a593Smuzhiyun /* 2690*4882a593Smuzhiyun * R157 (0x9D) - FLL Control (3) 2691*4882a593Smuzhiyun */ 2692*4882a593Smuzhiyun #define WM8962_FLL_FRATIO_MASK 0x0007 /* FLL_FRATIO - [2:0] */ 2693*4882a593Smuzhiyun #define WM8962_FLL_FRATIO_SHIFT 0 /* FLL_FRATIO - [2:0] */ 2694*4882a593Smuzhiyun #define WM8962_FLL_FRATIO_WIDTH 3 /* FLL_FRATIO - [2:0] */ 2695*4882a593Smuzhiyun 2696*4882a593Smuzhiyun /* 2697*4882a593Smuzhiyun * R159 (0x9F) - FLL Control (5) 2698*4882a593Smuzhiyun */ 2699*4882a593Smuzhiyun #define WM8962_FLL_FRC_NCO_VAL_MASK 0x007E /* FLL_FRC_NCO_VAL - [6:1] */ 2700*4882a593Smuzhiyun #define WM8962_FLL_FRC_NCO_VAL_SHIFT 1 /* FLL_FRC_NCO_VAL - [6:1] */ 2701*4882a593Smuzhiyun #define WM8962_FLL_FRC_NCO_VAL_WIDTH 6 /* FLL_FRC_NCO_VAL - [6:1] */ 2702*4882a593Smuzhiyun #define WM8962_FLL_FRC_NCO 0x0001 /* FLL_FRC_NCO */ 2703*4882a593Smuzhiyun #define WM8962_FLL_FRC_NCO_MASK 0x0001 /* FLL_FRC_NCO */ 2704*4882a593Smuzhiyun #define WM8962_FLL_FRC_NCO_SHIFT 0 /* FLL_FRC_NCO */ 2705*4882a593Smuzhiyun #define WM8962_FLL_FRC_NCO_WIDTH 1 /* FLL_FRC_NCO */ 2706*4882a593Smuzhiyun 2707*4882a593Smuzhiyun /* 2708*4882a593Smuzhiyun * R160 (0xA0) - FLL Control (6) 2709*4882a593Smuzhiyun */ 2710*4882a593Smuzhiyun #define WM8962_FLL_THETA_MASK 0xFFFF /* FLL_THETA - [15:0] */ 2711*4882a593Smuzhiyun #define WM8962_FLL_THETA_SHIFT 0 /* FLL_THETA - [15:0] */ 2712*4882a593Smuzhiyun #define WM8962_FLL_THETA_WIDTH 16 /* FLL_THETA - [15:0] */ 2713*4882a593Smuzhiyun 2714*4882a593Smuzhiyun /* 2715*4882a593Smuzhiyun * R161 (0xA1) - FLL Control (7) 2716*4882a593Smuzhiyun */ 2717*4882a593Smuzhiyun #define WM8962_FLL_LAMBDA_MASK 0xFFFF /* FLL_LAMBDA - [15:0] */ 2718*4882a593Smuzhiyun #define WM8962_FLL_LAMBDA_SHIFT 0 /* FLL_LAMBDA - [15:0] */ 2719*4882a593Smuzhiyun #define WM8962_FLL_LAMBDA_WIDTH 16 /* FLL_LAMBDA - [15:0] */ 2720*4882a593Smuzhiyun 2721*4882a593Smuzhiyun /* 2722*4882a593Smuzhiyun * R162 (0xA2) - FLL Control (8) 2723*4882a593Smuzhiyun */ 2724*4882a593Smuzhiyun #define WM8962_FLL_N_MASK 0x03FF /* FLL_N - [9:0] */ 2725*4882a593Smuzhiyun #define WM8962_FLL_N_SHIFT 0 /* FLL_N - [9:0] */ 2726*4882a593Smuzhiyun #define WM8962_FLL_N_WIDTH 10 /* FLL_N - [9:0] */ 2727*4882a593Smuzhiyun 2728*4882a593Smuzhiyun /* 2729*4882a593Smuzhiyun * R252 (0xFC) - General test 1 2730*4882a593Smuzhiyun */ 2731*4882a593Smuzhiyun #define WM8962_REG_SYNC 0x0004 /* REG_SYNC */ 2732*4882a593Smuzhiyun #define WM8962_REG_SYNC_MASK 0x0004 /* REG_SYNC */ 2733*4882a593Smuzhiyun #define WM8962_REG_SYNC_SHIFT 2 /* REG_SYNC */ 2734*4882a593Smuzhiyun #define WM8962_REG_SYNC_WIDTH 1 /* REG_SYNC */ 2735*4882a593Smuzhiyun #define WM8962_AUTO_INC 0x0001 /* AUTO_INC */ 2736*4882a593Smuzhiyun #define WM8962_AUTO_INC_MASK 0x0001 /* AUTO_INC */ 2737*4882a593Smuzhiyun #define WM8962_AUTO_INC_SHIFT 0 /* AUTO_INC */ 2738*4882a593Smuzhiyun #define WM8962_AUTO_INC_WIDTH 1 /* AUTO_INC */ 2739*4882a593Smuzhiyun 2740*4882a593Smuzhiyun /* 2741*4882a593Smuzhiyun * R256 (0x100) - DF1 2742*4882a593Smuzhiyun */ 2743*4882a593Smuzhiyun #define WM8962_DRC_DF1_ENA 0x0008 /* DRC_DF1_ENA */ 2744*4882a593Smuzhiyun #define WM8962_DRC_DF1_ENA_MASK 0x0008 /* DRC_DF1_ENA */ 2745*4882a593Smuzhiyun #define WM8962_DRC_DF1_ENA_SHIFT 3 /* DRC_DF1_ENA */ 2746*4882a593Smuzhiyun #define WM8962_DRC_DF1_ENA_WIDTH 1 /* DRC_DF1_ENA */ 2747*4882a593Smuzhiyun #define WM8962_DF1_SHARED_COEFF 0x0004 /* DF1_SHARED_COEFF */ 2748*4882a593Smuzhiyun #define WM8962_DF1_SHARED_COEFF_MASK 0x0004 /* DF1_SHARED_COEFF */ 2749*4882a593Smuzhiyun #define WM8962_DF1_SHARED_COEFF_SHIFT 2 /* DF1_SHARED_COEFF */ 2750*4882a593Smuzhiyun #define WM8962_DF1_SHARED_COEFF_WIDTH 1 /* DF1_SHARED_COEFF */ 2751*4882a593Smuzhiyun #define WM8962_DF1_SHARED_COEFF_SEL 0x0002 /* DF1_SHARED_COEFF_SEL */ 2752*4882a593Smuzhiyun #define WM8962_DF1_SHARED_COEFF_SEL_MASK 0x0002 /* DF1_SHARED_COEFF_SEL */ 2753*4882a593Smuzhiyun #define WM8962_DF1_SHARED_COEFF_SEL_SHIFT 1 /* DF1_SHARED_COEFF_SEL */ 2754*4882a593Smuzhiyun #define WM8962_DF1_SHARED_COEFF_SEL_WIDTH 1 /* DF1_SHARED_COEFF_SEL */ 2755*4882a593Smuzhiyun #define WM8962_DF1_ENA 0x0001 /* DF1_ENA */ 2756*4882a593Smuzhiyun #define WM8962_DF1_ENA_MASK 0x0001 /* DF1_ENA */ 2757*4882a593Smuzhiyun #define WM8962_DF1_ENA_SHIFT 0 /* DF1_ENA */ 2758*4882a593Smuzhiyun #define WM8962_DF1_ENA_WIDTH 1 /* DF1_ENA */ 2759*4882a593Smuzhiyun 2760*4882a593Smuzhiyun /* 2761*4882a593Smuzhiyun * R257 (0x101) - DF2 2762*4882a593Smuzhiyun */ 2763*4882a593Smuzhiyun #define WM8962_DF1_COEFF_L0_MASK 0xFFFF /* DF1_COEFF_L0 - [15:0] */ 2764*4882a593Smuzhiyun #define WM8962_DF1_COEFF_L0_SHIFT 0 /* DF1_COEFF_L0 - [15:0] */ 2765*4882a593Smuzhiyun #define WM8962_DF1_COEFF_L0_WIDTH 16 /* DF1_COEFF_L0 - [15:0] */ 2766*4882a593Smuzhiyun 2767*4882a593Smuzhiyun /* 2768*4882a593Smuzhiyun * R258 (0x102) - DF3 2769*4882a593Smuzhiyun */ 2770*4882a593Smuzhiyun #define WM8962_DF1_COEFF_L1_MASK 0xFFFF /* DF1_COEFF_L1 - [15:0] */ 2771*4882a593Smuzhiyun #define WM8962_DF1_COEFF_L1_SHIFT 0 /* DF1_COEFF_L1 - [15:0] */ 2772*4882a593Smuzhiyun #define WM8962_DF1_COEFF_L1_WIDTH 16 /* DF1_COEFF_L1 - [15:0] */ 2773*4882a593Smuzhiyun 2774*4882a593Smuzhiyun /* 2775*4882a593Smuzhiyun * R259 (0x103) - DF4 2776*4882a593Smuzhiyun */ 2777*4882a593Smuzhiyun #define WM8962_DF1_COEFF_L2_MASK 0xFFFF /* DF1_COEFF_L2 - [15:0] */ 2778*4882a593Smuzhiyun #define WM8962_DF1_COEFF_L2_SHIFT 0 /* DF1_COEFF_L2 - [15:0] */ 2779*4882a593Smuzhiyun #define WM8962_DF1_COEFF_L2_WIDTH 16 /* DF1_COEFF_L2 - [15:0] */ 2780*4882a593Smuzhiyun 2781*4882a593Smuzhiyun /* 2782*4882a593Smuzhiyun * R260 (0x104) - DF5 2783*4882a593Smuzhiyun */ 2784*4882a593Smuzhiyun #define WM8962_DF1_COEFF_R0_MASK 0xFFFF /* DF1_COEFF_R0 - [15:0] */ 2785*4882a593Smuzhiyun #define WM8962_DF1_COEFF_R0_SHIFT 0 /* DF1_COEFF_R0 - [15:0] */ 2786*4882a593Smuzhiyun #define WM8962_DF1_COEFF_R0_WIDTH 16 /* DF1_COEFF_R0 - [15:0] */ 2787*4882a593Smuzhiyun 2788*4882a593Smuzhiyun /* 2789*4882a593Smuzhiyun * R261 (0x105) - DF6 2790*4882a593Smuzhiyun */ 2791*4882a593Smuzhiyun #define WM8962_DF1_COEFF_R1_MASK 0xFFFF /* DF1_COEFF_R1 - [15:0] */ 2792*4882a593Smuzhiyun #define WM8962_DF1_COEFF_R1_SHIFT 0 /* DF1_COEFF_R1 - [15:0] */ 2793*4882a593Smuzhiyun #define WM8962_DF1_COEFF_R1_WIDTH 16 /* DF1_COEFF_R1 - [15:0] */ 2794*4882a593Smuzhiyun 2795*4882a593Smuzhiyun /* 2796*4882a593Smuzhiyun * R262 (0x106) - DF7 2797*4882a593Smuzhiyun */ 2798*4882a593Smuzhiyun #define WM8962_DF1_COEFF_R2_MASK 0xFFFF /* DF1_COEFF_R2 - [15:0] */ 2799*4882a593Smuzhiyun #define WM8962_DF1_COEFF_R2_SHIFT 0 /* DF1_COEFF_R2 - [15:0] */ 2800*4882a593Smuzhiyun #define WM8962_DF1_COEFF_R2_WIDTH 16 /* DF1_COEFF_R2 - [15:0] */ 2801*4882a593Smuzhiyun 2802*4882a593Smuzhiyun /* 2803*4882a593Smuzhiyun * R264 (0x108) - LHPF1 2804*4882a593Smuzhiyun */ 2805*4882a593Smuzhiyun #define WM8962_LHPF_MODE 0x0002 /* LHPF_MODE */ 2806*4882a593Smuzhiyun #define WM8962_LHPF_MODE_MASK 0x0002 /* LHPF_MODE */ 2807*4882a593Smuzhiyun #define WM8962_LHPF_MODE_SHIFT 1 /* LHPF_MODE */ 2808*4882a593Smuzhiyun #define WM8962_LHPF_MODE_WIDTH 1 /* LHPF_MODE */ 2809*4882a593Smuzhiyun #define WM8962_LHPF_ENA 0x0001 /* LHPF_ENA */ 2810*4882a593Smuzhiyun #define WM8962_LHPF_ENA_MASK 0x0001 /* LHPF_ENA */ 2811*4882a593Smuzhiyun #define WM8962_LHPF_ENA_SHIFT 0 /* LHPF_ENA */ 2812*4882a593Smuzhiyun #define WM8962_LHPF_ENA_WIDTH 1 /* LHPF_ENA */ 2813*4882a593Smuzhiyun 2814*4882a593Smuzhiyun /* 2815*4882a593Smuzhiyun * R265 (0x109) - LHPF2 2816*4882a593Smuzhiyun */ 2817*4882a593Smuzhiyun #define WM8962_LHPF_COEFF_MASK 0xFFFF /* LHPF_COEFF - [15:0] */ 2818*4882a593Smuzhiyun #define WM8962_LHPF_COEFF_SHIFT 0 /* LHPF_COEFF - [15:0] */ 2819*4882a593Smuzhiyun #define WM8962_LHPF_COEFF_WIDTH 16 /* LHPF_COEFF - [15:0] */ 2820*4882a593Smuzhiyun 2821*4882a593Smuzhiyun /* 2822*4882a593Smuzhiyun * R268 (0x10C) - THREED1 2823*4882a593Smuzhiyun */ 2824*4882a593Smuzhiyun #define WM8962_ADC_MONOMIX 0x0040 /* ADC_MONOMIX */ 2825*4882a593Smuzhiyun #define WM8962_ADC_MONOMIX_MASK 0x0040 /* ADC_MONOMIX */ 2826*4882a593Smuzhiyun #define WM8962_ADC_MONOMIX_SHIFT 6 /* ADC_MONOMIX */ 2827*4882a593Smuzhiyun #define WM8962_ADC_MONOMIX_WIDTH 1 /* ADC_MONOMIX */ 2828*4882a593Smuzhiyun #define WM8962_THREED_SIGN_L 0x0020 /* THREED_SIGN_L */ 2829*4882a593Smuzhiyun #define WM8962_THREED_SIGN_L_MASK 0x0020 /* THREED_SIGN_L */ 2830*4882a593Smuzhiyun #define WM8962_THREED_SIGN_L_SHIFT 5 /* THREED_SIGN_L */ 2831*4882a593Smuzhiyun #define WM8962_THREED_SIGN_L_WIDTH 1 /* THREED_SIGN_L */ 2832*4882a593Smuzhiyun #define WM8962_THREED_SIGN_R 0x0010 /* THREED_SIGN_R */ 2833*4882a593Smuzhiyun #define WM8962_THREED_SIGN_R_MASK 0x0010 /* THREED_SIGN_R */ 2834*4882a593Smuzhiyun #define WM8962_THREED_SIGN_R_SHIFT 4 /* THREED_SIGN_R */ 2835*4882a593Smuzhiyun #define WM8962_THREED_SIGN_R_WIDTH 1 /* THREED_SIGN_R */ 2836*4882a593Smuzhiyun #define WM8962_THREED_LHPF_MODE 0x0004 /* THREED_LHPF_MODE */ 2837*4882a593Smuzhiyun #define WM8962_THREED_LHPF_MODE_MASK 0x0004 /* THREED_LHPF_MODE */ 2838*4882a593Smuzhiyun #define WM8962_THREED_LHPF_MODE_SHIFT 2 /* THREED_LHPF_MODE */ 2839*4882a593Smuzhiyun #define WM8962_THREED_LHPF_MODE_WIDTH 1 /* THREED_LHPF_MODE */ 2840*4882a593Smuzhiyun #define WM8962_THREED_LHPF_ENA 0x0002 /* THREED_LHPF_ENA */ 2841*4882a593Smuzhiyun #define WM8962_THREED_LHPF_ENA_MASK 0x0002 /* THREED_LHPF_ENA */ 2842*4882a593Smuzhiyun #define WM8962_THREED_LHPF_ENA_SHIFT 1 /* THREED_LHPF_ENA */ 2843*4882a593Smuzhiyun #define WM8962_THREED_LHPF_ENA_WIDTH 1 /* THREED_LHPF_ENA */ 2844*4882a593Smuzhiyun #define WM8962_THREED_ENA 0x0001 /* THREED_ENA */ 2845*4882a593Smuzhiyun #define WM8962_THREED_ENA_MASK 0x0001 /* THREED_ENA */ 2846*4882a593Smuzhiyun #define WM8962_THREED_ENA_SHIFT 0 /* THREED_ENA */ 2847*4882a593Smuzhiyun #define WM8962_THREED_ENA_WIDTH 1 /* THREED_ENA */ 2848*4882a593Smuzhiyun 2849*4882a593Smuzhiyun /* 2850*4882a593Smuzhiyun * R269 (0x10D) - THREED2 2851*4882a593Smuzhiyun */ 2852*4882a593Smuzhiyun #define WM8962_THREED_FGAINL_MASK 0xF800 /* THREED_FGAINL - [15:11] */ 2853*4882a593Smuzhiyun #define WM8962_THREED_FGAINL_SHIFT 11 /* THREED_FGAINL - [15:11] */ 2854*4882a593Smuzhiyun #define WM8962_THREED_FGAINL_WIDTH 5 /* THREED_FGAINL - [15:11] */ 2855*4882a593Smuzhiyun #define WM8962_THREED_CGAINL_MASK 0x07C0 /* THREED_CGAINL - [10:6] */ 2856*4882a593Smuzhiyun #define WM8962_THREED_CGAINL_SHIFT 6 /* THREED_CGAINL - [10:6] */ 2857*4882a593Smuzhiyun #define WM8962_THREED_CGAINL_WIDTH 5 /* THREED_CGAINL - [10:6] */ 2858*4882a593Smuzhiyun #define WM8962_THREED_DELAYL_MASK 0x003C /* THREED_DELAYL - [5:2] */ 2859*4882a593Smuzhiyun #define WM8962_THREED_DELAYL_SHIFT 2 /* THREED_DELAYL - [5:2] */ 2860*4882a593Smuzhiyun #define WM8962_THREED_DELAYL_WIDTH 4 /* THREED_DELAYL - [5:2] */ 2861*4882a593Smuzhiyun 2862*4882a593Smuzhiyun /* 2863*4882a593Smuzhiyun * R270 (0x10E) - THREED3 2864*4882a593Smuzhiyun */ 2865*4882a593Smuzhiyun #define WM8962_THREED_LHPF_COEFF_MASK 0xFFFF /* THREED_LHPF_COEFF - [15:0] */ 2866*4882a593Smuzhiyun #define WM8962_THREED_LHPF_COEFF_SHIFT 0 /* THREED_LHPF_COEFF - [15:0] */ 2867*4882a593Smuzhiyun #define WM8962_THREED_LHPF_COEFF_WIDTH 16 /* THREED_LHPF_COEFF - [15:0] */ 2868*4882a593Smuzhiyun 2869*4882a593Smuzhiyun /* 2870*4882a593Smuzhiyun * R271 (0x10F) - THREED4 2871*4882a593Smuzhiyun */ 2872*4882a593Smuzhiyun #define WM8962_THREED_FGAINR_MASK 0xF800 /* THREED_FGAINR - [15:11] */ 2873*4882a593Smuzhiyun #define WM8962_THREED_FGAINR_SHIFT 11 /* THREED_FGAINR - [15:11] */ 2874*4882a593Smuzhiyun #define WM8962_THREED_FGAINR_WIDTH 5 /* THREED_FGAINR - [15:11] */ 2875*4882a593Smuzhiyun #define WM8962_THREED_CGAINR_MASK 0x07C0 /* THREED_CGAINR - [10:6] */ 2876*4882a593Smuzhiyun #define WM8962_THREED_CGAINR_SHIFT 6 /* THREED_CGAINR - [10:6] */ 2877*4882a593Smuzhiyun #define WM8962_THREED_CGAINR_WIDTH 5 /* THREED_CGAINR - [10:6] */ 2878*4882a593Smuzhiyun #define WM8962_THREED_DELAYR_MASK 0x003C /* THREED_DELAYR - [5:2] */ 2879*4882a593Smuzhiyun #define WM8962_THREED_DELAYR_SHIFT 2 /* THREED_DELAYR - [5:2] */ 2880*4882a593Smuzhiyun #define WM8962_THREED_DELAYR_WIDTH 4 /* THREED_DELAYR - [5:2] */ 2881*4882a593Smuzhiyun 2882*4882a593Smuzhiyun /* 2883*4882a593Smuzhiyun * R276 (0x114) - DRC 1 2884*4882a593Smuzhiyun */ 2885*4882a593Smuzhiyun #define WM8962_DRC_SIG_DET_RMS_MASK 0x7C00 /* DRC_SIG_DET_RMS - [14:10] */ 2886*4882a593Smuzhiyun #define WM8962_DRC_SIG_DET_RMS_SHIFT 10 /* DRC_SIG_DET_RMS - [14:10] */ 2887*4882a593Smuzhiyun #define WM8962_DRC_SIG_DET_RMS_WIDTH 5 /* DRC_SIG_DET_RMS - [14:10] */ 2888*4882a593Smuzhiyun #define WM8962_DRC_SIG_DET_PK_MASK 0x0300 /* DRC_SIG_DET_PK - [9:8] */ 2889*4882a593Smuzhiyun #define WM8962_DRC_SIG_DET_PK_SHIFT 8 /* DRC_SIG_DET_PK - [9:8] */ 2890*4882a593Smuzhiyun #define WM8962_DRC_SIG_DET_PK_WIDTH 2 /* DRC_SIG_DET_PK - [9:8] */ 2891*4882a593Smuzhiyun #define WM8962_DRC_NG_ENA 0x0080 /* DRC_NG_ENA */ 2892*4882a593Smuzhiyun #define WM8962_DRC_NG_ENA_MASK 0x0080 /* DRC_NG_ENA */ 2893*4882a593Smuzhiyun #define WM8962_DRC_NG_ENA_SHIFT 7 /* DRC_NG_ENA */ 2894*4882a593Smuzhiyun #define WM8962_DRC_NG_ENA_WIDTH 1 /* DRC_NG_ENA */ 2895*4882a593Smuzhiyun #define WM8962_DRC_SIG_DET_MODE 0x0040 /* DRC_SIG_DET_MODE */ 2896*4882a593Smuzhiyun #define WM8962_DRC_SIG_DET_MODE_MASK 0x0040 /* DRC_SIG_DET_MODE */ 2897*4882a593Smuzhiyun #define WM8962_DRC_SIG_DET_MODE_SHIFT 6 /* DRC_SIG_DET_MODE */ 2898*4882a593Smuzhiyun #define WM8962_DRC_SIG_DET_MODE_WIDTH 1 /* DRC_SIG_DET_MODE */ 2899*4882a593Smuzhiyun #define WM8962_DRC_SIG_DET 0x0020 /* DRC_SIG_DET */ 2900*4882a593Smuzhiyun #define WM8962_DRC_SIG_DET_MASK 0x0020 /* DRC_SIG_DET */ 2901*4882a593Smuzhiyun #define WM8962_DRC_SIG_DET_SHIFT 5 /* DRC_SIG_DET */ 2902*4882a593Smuzhiyun #define WM8962_DRC_SIG_DET_WIDTH 1 /* DRC_SIG_DET */ 2903*4882a593Smuzhiyun #define WM8962_DRC_KNEE2_OP_ENA 0x0010 /* DRC_KNEE2_OP_ENA */ 2904*4882a593Smuzhiyun #define WM8962_DRC_KNEE2_OP_ENA_MASK 0x0010 /* DRC_KNEE2_OP_ENA */ 2905*4882a593Smuzhiyun #define WM8962_DRC_KNEE2_OP_ENA_SHIFT 4 /* DRC_KNEE2_OP_ENA */ 2906*4882a593Smuzhiyun #define WM8962_DRC_KNEE2_OP_ENA_WIDTH 1 /* DRC_KNEE2_OP_ENA */ 2907*4882a593Smuzhiyun #define WM8962_DRC_QR 0x0008 /* DRC_QR */ 2908*4882a593Smuzhiyun #define WM8962_DRC_QR_MASK 0x0008 /* DRC_QR */ 2909*4882a593Smuzhiyun #define WM8962_DRC_QR_SHIFT 3 /* DRC_QR */ 2910*4882a593Smuzhiyun #define WM8962_DRC_QR_WIDTH 1 /* DRC_QR */ 2911*4882a593Smuzhiyun #define WM8962_DRC_ANTICLIP 0x0004 /* DRC_ANTICLIP */ 2912*4882a593Smuzhiyun #define WM8962_DRC_ANTICLIP_MASK 0x0004 /* DRC_ANTICLIP */ 2913*4882a593Smuzhiyun #define WM8962_DRC_ANTICLIP_SHIFT 2 /* DRC_ANTICLIP */ 2914*4882a593Smuzhiyun #define WM8962_DRC_ANTICLIP_WIDTH 1 /* DRC_ANTICLIP */ 2915*4882a593Smuzhiyun #define WM8962_DRC_MODE 0x0002 /* DRC_MODE */ 2916*4882a593Smuzhiyun #define WM8962_DRC_MODE_MASK 0x0002 /* DRC_MODE */ 2917*4882a593Smuzhiyun #define WM8962_DRC_MODE_SHIFT 1 /* DRC_MODE */ 2918*4882a593Smuzhiyun #define WM8962_DRC_MODE_WIDTH 1 /* DRC_MODE */ 2919*4882a593Smuzhiyun #define WM8962_DRC_ENA 0x0001 /* DRC_ENA */ 2920*4882a593Smuzhiyun #define WM8962_DRC_ENA_MASK 0x0001 /* DRC_ENA */ 2921*4882a593Smuzhiyun #define WM8962_DRC_ENA_SHIFT 0 /* DRC_ENA */ 2922*4882a593Smuzhiyun #define WM8962_DRC_ENA_WIDTH 1 /* DRC_ENA */ 2923*4882a593Smuzhiyun 2924*4882a593Smuzhiyun /* 2925*4882a593Smuzhiyun * R277 (0x115) - DRC 2 2926*4882a593Smuzhiyun */ 2927*4882a593Smuzhiyun #define WM8962_DRC_ATK_MASK 0x1E00 /* DRC_ATK - [12:9] */ 2928*4882a593Smuzhiyun #define WM8962_DRC_ATK_SHIFT 9 /* DRC_ATK - [12:9] */ 2929*4882a593Smuzhiyun #define WM8962_DRC_ATK_WIDTH 4 /* DRC_ATK - [12:9] */ 2930*4882a593Smuzhiyun #define WM8962_DRC_DCY_MASK 0x01E0 /* DRC_DCY - [8:5] */ 2931*4882a593Smuzhiyun #define WM8962_DRC_DCY_SHIFT 5 /* DRC_DCY - [8:5] */ 2932*4882a593Smuzhiyun #define WM8962_DRC_DCY_WIDTH 4 /* DRC_DCY - [8:5] */ 2933*4882a593Smuzhiyun #define WM8962_DRC_MINGAIN_MASK 0x001C /* DRC_MINGAIN - [4:2] */ 2934*4882a593Smuzhiyun #define WM8962_DRC_MINGAIN_SHIFT 2 /* DRC_MINGAIN - [4:2] */ 2935*4882a593Smuzhiyun #define WM8962_DRC_MINGAIN_WIDTH 3 /* DRC_MINGAIN - [4:2] */ 2936*4882a593Smuzhiyun #define WM8962_DRC_MAXGAIN_MASK 0x0003 /* DRC_MAXGAIN - [1:0] */ 2937*4882a593Smuzhiyun #define WM8962_DRC_MAXGAIN_SHIFT 0 /* DRC_MAXGAIN - [1:0] */ 2938*4882a593Smuzhiyun #define WM8962_DRC_MAXGAIN_WIDTH 2 /* DRC_MAXGAIN - [1:0] */ 2939*4882a593Smuzhiyun 2940*4882a593Smuzhiyun /* 2941*4882a593Smuzhiyun * R278 (0x116) - DRC 3 2942*4882a593Smuzhiyun */ 2943*4882a593Smuzhiyun #define WM8962_DRC_NG_MINGAIN_MASK 0xF000 /* DRC_NG_MINGAIN - [15:12] */ 2944*4882a593Smuzhiyun #define WM8962_DRC_NG_MINGAIN_SHIFT 12 /* DRC_NG_MINGAIN - [15:12] */ 2945*4882a593Smuzhiyun #define WM8962_DRC_NG_MINGAIN_WIDTH 4 /* DRC_NG_MINGAIN - [15:12] */ 2946*4882a593Smuzhiyun #define WM8962_DRC_QR_THR_MASK 0x0C00 /* DRC_QR_THR - [11:10] */ 2947*4882a593Smuzhiyun #define WM8962_DRC_QR_THR_SHIFT 10 /* DRC_QR_THR - [11:10] */ 2948*4882a593Smuzhiyun #define WM8962_DRC_QR_THR_WIDTH 2 /* DRC_QR_THR - [11:10] */ 2949*4882a593Smuzhiyun #define WM8962_DRC_QR_DCY_MASK 0x0300 /* DRC_QR_DCY - [9:8] */ 2950*4882a593Smuzhiyun #define WM8962_DRC_QR_DCY_SHIFT 8 /* DRC_QR_DCY - [9:8] */ 2951*4882a593Smuzhiyun #define WM8962_DRC_QR_DCY_WIDTH 2 /* DRC_QR_DCY - [9:8] */ 2952*4882a593Smuzhiyun #define WM8962_DRC_NG_EXP_MASK 0x00C0 /* DRC_NG_EXP - [7:6] */ 2953*4882a593Smuzhiyun #define WM8962_DRC_NG_EXP_SHIFT 6 /* DRC_NG_EXP - [7:6] */ 2954*4882a593Smuzhiyun #define WM8962_DRC_NG_EXP_WIDTH 2 /* DRC_NG_EXP - [7:6] */ 2955*4882a593Smuzhiyun #define WM8962_DRC_HI_COMP_MASK 0x0038 /* DRC_HI_COMP - [5:3] */ 2956*4882a593Smuzhiyun #define WM8962_DRC_HI_COMP_SHIFT 3 /* DRC_HI_COMP - [5:3] */ 2957*4882a593Smuzhiyun #define WM8962_DRC_HI_COMP_WIDTH 3 /* DRC_HI_COMP - [5:3] */ 2958*4882a593Smuzhiyun #define WM8962_DRC_LO_COMP_MASK 0x0007 /* DRC_LO_COMP - [2:0] */ 2959*4882a593Smuzhiyun #define WM8962_DRC_LO_COMP_SHIFT 0 /* DRC_LO_COMP - [2:0] */ 2960*4882a593Smuzhiyun #define WM8962_DRC_LO_COMP_WIDTH 3 /* DRC_LO_COMP - [2:0] */ 2961*4882a593Smuzhiyun 2962*4882a593Smuzhiyun /* 2963*4882a593Smuzhiyun * R279 (0x117) - DRC 4 2964*4882a593Smuzhiyun */ 2965*4882a593Smuzhiyun #define WM8962_DRC_KNEE_IP_MASK 0x07E0 /* DRC_KNEE_IP - [10:5] */ 2966*4882a593Smuzhiyun #define WM8962_DRC_KNEE_IP_SHIFT 5 /* DRC_KNEE_IP - [10:5] */ 2967*4882a593Smuzhiyun #define WM8962_DRC_KNEE_IP_WIDTH 6 /* DRC_KNEE_IP - [10:5] */ 2968*4882a593Smuzhiyun #define WM8962_DRC_KNEE_OP_MASK 0x001F /* DRC_KNEE_OP - [4:0] */ 2969*4882a593Smuzhiyun #define WM8962_DRC_KNEE_OP_SHIFT 0 /* DRC_KNEE_OP - [4:0] */ 2970*4882a593Smuzhiyun #define WM8962_DRC_KNEE_OP_WIDTH 5 /* DRC_KNEE_OP - [4:0] */ 2971*4882a593Smuzhiyun 2972*4882a593Smuzhiyun /* 2973*4882a593Smuzhiyun * R280 (0x118) - DRC 5 2974*4882a593Smuzhiyun */ 2975*4882a593Smuzhiyun #define WM8962_DRC_KNEE2_IP_MASK 0x03E0 /* DRC_KNEE2_IP - [9:5] */ 2976*4882a593Smuzhiyun #define WM8962_DRC_KNEE2_IP_SHIFT 5 /* DRC_KNEE2_IP - [9:5] */ 2977*4882a593Smuzhiyun #define WM8962_DRC_KNEE2_IP_WIDTH 5 /* DRC_KNEE2_IP - [9:5] */ 2978*4882a593Smuzhiyun #define WM8962_DRC_KNEE2_OP_MASK 0x001F /* DRC_KNEE2_OP - [4:0] */ 2979*4882a593Smuzhiyun #define WM8962_DRC_KNEE2_OP_SHIFT 0 /* DRC_KNEE2_OP - [4:0] */ 2980*4882a593Smuzhiyun #define WM8962_DRC_KNEE2_OP_WIDTH 5 /* DRC_KNEE2_OP - [4:0] */ 2981*4882a593Smuzhiyun 2982*4882a593Smuzhiyun /* 2983*4882a593Smuzhiyun * R285 (0x11D) - Tloopback 2984*4882a593Smuzhiyun */ 2985*4882a593Smuzhiyun #define WM8962_TLB_ENA 0x0002 /* TLB_ENA */ 2986*4882a593Smuzhiyun #define WM8962_TLB_ENA_MASK 0x0002 /* TLB_ENA */ 2987*4882a593Smuzhiyun #define WM8962_TLB_ENA_SHIFT 1 /* TLB_ENA */ 2988*4882a593Smuzhiyun #define WM8962_TLB_ENA_WIDTH 1 /* TLB_ENA */ 2989*4882a593Smuzhiyun #define WM8962_TLB_MODE 0x0001 /* TLB_MODE */ 2990*4882a593Smuzhiyun #define WM8962_TLB_MODE_MASK 0x0001 /* TLB_MODE */ 2991*4882a593Smuzhiyun #define WM8962_TLB_MODE_SHIFT 0 /* TLB_MODE */ 2992*4882a593Smuzhiyun #define WM8962_TLB_MODE_WIDTH 1 /* TLB_MODE */ 2993*4882a593Smuzhiyun 2994*4882a593Smuzhiyun /* 2995*4882a593Smuzhiyun * R335 (0x14F) - EQ1 2996*4882a593Smuzhiyun */ 2997*4882a593Smuzhiyun #define WM8962_EQ_SHARED_COEFF 0x0004 /* EQ_SHARED_COEFF */ 2998*4882a593Smuzhiyun #define WM8962_EQ_SHARED_COEFF_MASK 0x0004 /* EQ_SHARED_COEFF */ 2999*4882a593Smuzhiyun #define WM8962_EQ_SHARED_COEFF_SHIFT 2 /* EQ_SHARED_COEFF */ 3000*4882a593Smuzhiyun #define WM8962_EQ_SHARED_COEFF_WIDTH 1 /* EQ_SHARED_COEFF */ 3001*4882a593Smuzhiyun #define WM8962_EQ_SHARED_COEFF_SEL 0x0002 /* EQ_SHARED_COEFF_SEL */ 3002*4882a593Smuzhiyun #define WM8962_EQ_SHARED_COEFF_SEL_MASK 0x0002 /* EQ_SHARED_COEFF_SEL */ 3003*4882a593Smuzhiyun #define WM8962_EQ_SHARED_COEFF_SEL_SHIFT 1 /* EQ_SHARED_COEFF_SEL */ 3004*4882a593Smuzhiyun #define WM8962_EQ_SHARED_COEFF_SEL_WIDTH 1 /* EQ_SHARED_COEFF_SEL */ 3005*4882a593Smuzhiyun #define WM8962_EQ_ENA 0x0001 /* EQ_ENA */ 3006*4882a593Smuzhiyun #define WM8962_EQ_ENA_MASK 0x0001 /* EQ_ENA */ 3007*4882a593Smuzhiyun #define WM8962_EQ_ENA_SHIFT 0 /* EQ_ENA */ 3008*4882a593Smuzhiyun #define WM8962_EQ_ENA_WIDTH 1 /* EQ_ENA */ 3009*4882a593Smuzhiyun 3010*4882a593Smuzhiyun /* 3011*4882a593Smuzhiyun * R336 (0x150) - EQ2 3012*4882a593Smuzhiyun */ 3013*4882a593Smuzhiyun #define WM8962_EQL_B1_GAIN_MASK 0xF800 /* EQL_B1_GAIN - [15:11] */ 3014*4882a593Smuzhiyun #define WM8962_EQL_B1_GAIN_SHIFT 11 /* EQL_B1_GAIN - [15:11] */ 3015*4882a593Smuzhiyun #define WM8962_EQL_B1_GAIN_WIDTH 5 /* EQL_B1_GAIN - [15:11] */ 3016*4882a593Smuzhiyun #define WM8962_EQL_B2_GAIN_MASK 0x07C0 /* EQL_B2_GAIN - [10:6] */ 3017*4882a593Smuzhiyun #define WM8962_EQL_B2_GAIN_SHIFT 6 /* EQL_B2_GAIN - [10:6] */ 3018*4882a593Smuzhiyun #define WM8962_EQL_B2_GAIN_WIDTH 5 /* EQL_B2_GAIN - [10:6] */ 3019*4882a593Smuzhiyun #define WM8962_EQL_B3_GAIN_MASK 0x003E /* EQL_B3_GAIN - [5:1] */ 3020*4882a593Smuzhiyun #define WM8962_EQL_B3_GAIN_SHIFT 1 /* EQL_B3_GAIN - [5:1] */ 3021*4882a593Smuzhiyun #define WM8962_EQL_B3_GAIN_WIDTH 5 /* EQL_B3_GAIN - [5:1] */ 3022*4882a593Smuzhiyun 3023*4882a593Smuzhiyun /* 3024*4882a593Smuzhiyun * R337 (0x151) - EQ3 3025*4882a593Smuzhiyun */ 3026*4882a593Smuzhiyun #define WM8962_EQL_B4_GAIN_MASK 0xF800 /* EQL_B4_GAIN - [15:11] */ 3027*4882a593Smuzhiyun #define WM8962_EQL_B4_GAIN_SHIFT 11 /* EQL_B4_GAIN - [15:11] */ 3028*4882a593Smuzhiyun #define WM8962_EQL_B4_GAIN_WIDTH 5 /* EQL_B4_GAIN - [15:11] */ 3029*4882a593Smuzhiyun #define WM8962_EQL_B5_GAIN_MASK 0x07C0 /* EQL_B5_GAIN - [10:6] */ 3030*4882a593Smuzhiyun #define WM8962_EQL_B5_GAIN_SHIFT 6 /* EQL_B5_GAIN - [10:6] */ 3031*4882a593Smuzhiyun #define WM8962_EQL_B5_GAIN_WIDTH 5 /* EQL_B5_GAIN - [10:6] */ 3032*4882a593Smuzhiyun 3033*4882a593Smuzhiyun /* 3034*4882a593Smuzhiyun * R338 (0x152) - EQ4 3035*4882a593Smuzhiyun */ 3036*4882a593Smuzhiyun #define WM8962_EQL_B1_A_MASK 0xFFFF /* EQL_B1_A - [15:0] */ 3037*4882a593Smuzhiyun #define WM8962_EQL_B1_A_SHIFT 0 /* EQL_B1_A - [15:0] */ 3038*4882a593Smuzhiyun #define WM8962_EQL_B1_A_WIDTH 16 /* EQL_B1_A - [15:0] */ 3039*4882a593Smuzhiyun 3040*4882a593Smuzhiyun /* 3041*4882a593Smuzhiyun * R339 (0x153) - EQ5 3042*4882a593Smuzhiyun */ 3043*4882a593Smuzhiyun #define WM8962_EQL_B1_B_MASK 0xFFFF /* EQL_B1_B - [15:0] */ 3044*4882a593Smuzhiyun #define WM8962_EQL_B1_B_SHIFT 0 /* EQL_B1_B - [15:0] */ 3045*4882a593Smuzhiyun #define WM8962_EQL_B1_B_WIDTH 16 /* EQL_B1_B - [15:0] */ 3046*4882a593Smuzhiyun 3047*4882a593Smuzhiyun /* 3048*4882a593Smuzhiyun * R340 (0x154) - EQ6 3049*4882a593Smuzhiyun */ 3050*4882a593Smuzhiyun #define WM8962_EQL_B1_PG_MASK 0xFFFF /* EQL_B1_PG - [15:0] */ 3051*4882a593Smuzhiyun #define WM8962_EQL_B1_PG_SHIFT 0 /* EQL_B1_PG - [15:0] */ 3052*4882a593Smuzhiyun #define WM8962_EQL_B1_PG_WIDTH 16 /* EQL_B1_PG - [15:0] */ 3053*4882a593Smuzhiyun 3054*4882a593Smuzhiyun /* 3055*4882a593Smuzhiyun * R341 (0x155) - EQ7 3056*4882a593Smuzhiyun */ 3057*4882a593Smuzhiyun #define WM8962_EQL_B2_A_MASK 0xFFFF /* EQL_B2_A - [15:0] */ 3058*4882a593Smuzhiyun #define WM8962_EQL_B2_A_SHIFT 0 /* EQL_B2_A - [15:0] */ 3059*4882a593Smuzhiyun #define WM8962_EQL_B2_A_WIDTH 16 /* EQL_B2_A - [15:0] */ 3060*4882a593Smuzhiyun 3061*4882a593Smuzhiyun /* 3062*4882a593Smuzhiyun * R342 (0x156) - EQ8 3063*4882a593Smuzhiyun */ 3064*4882a593Smuzhiyun #define WM8962_EQL_B2_B_MASK 0xFFFF /* EQL_B2_B - [15:0] */ 3065*4882a593Smuzhiyun #define WM8962_EQL_B2_B_SHIFT 0 /* EQL_B2_B - [15:0] */ 3066*4882a593Smuzhiyun #define WM8962_EQL_B2_B_WIDTH 16 /* EQL_B2_B - [15:0] */ 3067*4882a593Smuzhiyun 3068*4882a593Smuzhiyun /* 3069*4882a593Smuzhiyun * R343 (0x157) - EQ9 3070*4882a593Smuzhiyun */ 3071*4882a593Smuzhiyun #define WM8962_EQL_B2_C_MASK 0xFFFF /* EQL_B2_C - [15:0] */ 3072*4882a593Smuzhiyun #define WM8962_EQL_B2_C_SHIFT 0 /* EQL_B2_C - [15:0] */ 3073*4882a593Smuzhiyun #define WM8962_EQL_B2_C_WIDTH 16 /* EQL_B2_C - [15:0] */ 3074*4882a593Smuzhiyun 3075*4882a593Smuzhiyun /* 3076*4882a593Smuzhiyun * R344 (0x158) - EQ10 3077*4882a593Smuzhiyun */ 3078*4882a593Smuzhiyun #define WM8962_EQL_B2_PG_MASK 0xFFFF /* EQL_B2_PG - [15:0] */ 3079*4882a593Smuzhiyun #define WM8962_EQL_B2_PG_SHIFT 0 /* EQL_B2_PG - [15:0] */ 3080*4882a593Smuzhiyun #define WM8962_EQL_B2_PG_WIDTH 16 /* EQL_B2_PG - [15:0] */ 3081*4882a593Smuzhiyun 3082*4882a593Smuzhiyun /* 3083*4882a593Smuzhiyun * R345 (0x159) - EQ11 3084*4882a593Smuzhiyun */ 3085*4882a593Smuzhiyun #define WM8962_EQL_B3_A_MASK 0xFFFF /* EQL_B3_A - [15:0] */ 3086*4882a593Smuzhiyun #define WM8962_EQL_B3_A_SHIFT 0 /* EQL_B3_A - [15:0] */ 3087*4882a593Smuzhiyun #define WM8962_EQL_B3_A_WIDTH 16 /* EQL_B3_A - [15:0] */ 3088*4882a593Smuzhiyun 3089*4882a593Smuzhiyun /* 3090*4882a593Smuzhiyun * R346 (0x15A) - EQ12 3091*4882a593Smuzhiyun */ 3092*4882a593Smuzhiyun #define WM8962_EQL_B3_B_MASK 0xFFFF /* EQL_B3_B - [15:0] */ 3093*4882a593Smuzhiyun #define WM8962_EQL_B3_B_SHIFT 0 /* EQL_B3_B - [15:0] */ 3094*4882a593Smuzhiyun #define WM8962_EQL_B3_B_WIDTH 16 /* EQL_B3_B - [15:0] */ 3095*4882a593Smuzhiyun 3096*4882a593Smuzhiyun /* 3097*4882a593Smuzhiyun * R347 (0x15B) - EQ13 3098*4882a593Smuzhiyun */ 3099*4882a593Smuzhiyun #define WM8962_EQL_B3_C_MASK 0xFFFF /* EQL_B3_C - [15:0] */ 3100*4882a593Smuzhiyun #define WM8962_EQL_B3_C_SHIFT 0 /* EQL_B3_C - [15:0] */ 3101*4882a593Smuzhiyun #define WM8962_EQL_B3_C_WIDTH 16 /* EQL_B3_C - [15:0] */ 3102*4882a593Smuzhiyun 3103*4882a593Smuzhiyun /* 3104*4882a593Smuzhiyun * R348 (0x15C) - EQ14 3105*4882a593Smuzhiyun */ 3106*4882a593Smuzhiyun #define WM8962_EQL_B3_PG_MASK 0xFFFF /* EQL_B3_PG - [15:0] */ 3107*4882a593Smuzhiyun #define WM8962_EQL_B3_PG_SHIFT 0 /* EQL_B3_PG - [15:0] */ 3108*4882a593Smuzhiyun #define WM8962_EQL_B3_PG_WIDTH 16 /* EQL_B3_PG - [15:0] */ 3109*4882a593Smuzhiyun 3110*4882a593Smuzhiyun /* 3111*4882a593Smuzhiyun * R349 (0x15D) - EQ15 3112*4882a593Smuzhiyun */ 3113*4882a593Smuzhiyun #define WM8962_EQL_B4_A_MASK 0xFFFF /* EQL_B4_A - [15:0] */ 3114*4882a593Smuzhiyun #define WM8962_EQL_B4_A_SHIFT 0 /* EQL_B4_A - [15:0] */ 3115*4882a593Smuzhiyun #define WM8962_EQL_B4_A_WIDTH 16 /* EQL_B4_A - [15:0] */ 3116*4882a593Smuzhiyun 3117*4882a593Smuzhiyun /* 3118*4882a593Smuzhiyun * R350 (0x15E) - EQ16 3119*4882a593Smuzhiyun */ 3120*4882a593Smuzhiyun #define WM8962_EQL_B4_B_MASK 0xFFFF /* EQL_B4_B - [15:0] */ 3121*4882a593Smuzhiyun #define WM8962_EQL_B4_B_SHIFT 0 /* EQL_B4_B - [15:0] */ 3122*4882a593Smuzhiyun #define WM8962_EQL_B4_B_WIDTH 16 /* EQL_B4_B - [15:0] */ 3123*4882a593Smuzhiyun 3124*4882a593Smuzhiyun /* 3125*4882a593Smuzhiyun * R351 (0x15F) - EQ17 3126*4882a593Smuzhiyun */ 3127*4882a593Smuzhiyun #define WM8962_EQL_B4_C_MASK 0xFFFF /* EQL_B4_C - [15:0] */ 3128*4882a593Smuzhiyun #define WM8962_EQL_B4_C_SHIFT 0 /* EQL_B4_C - [15:0] */ 3129*4882a593Smuzhiyun #define WM8962_EQL_B4_C_WIDTH 16 /* EQL_B4_C - [15:0] */ 3130*4882a593Smuzhiyun 3131*4882a593Smuzhiyun /* 3132*4882a593Smuzhiyun * R352 (0x160) - EQ18 3133*4882a593Smuzhiyun */ 3134*4882a593Smuzhiyun #define WM8962_EQL_B4_PG_MASK 0xFFFF /* EQL_B4_PG - [15:0] */ 3135*4882a593Smuzhiyun #define WM8962_EQL_B4_PG_SHIFT 0 /* EQL_B4_PG - [15:0] */ 3136*4882a593Smuzhiyun #define WM8962_EQL_B4_PG_WIDTH 16 /* EQL_B4_PG - [15:0] */ 3137*4882a593Smuzhiyun 3138*4882a593Smuzhiyun /* 3139*4882a593Smuzhiyun * R353 (0x161) - EQ19 3140*4882a593Smuzhiyun */ 3141*4882a593Smuzhiyun #define WM8962_EQL_B5_A_MASK 0xFFFF /* EQL_B5_A - [15:0] */ 3142*4882a593Smuzhiyun #define WM8962_EQL_B5_A_SHIFT 0 /* EQL_B5_A - [15:0] */ 3143*4882a593Smuzhiyun #define WM8962_EQL_B5_A_WIDTH 16 /* EQL_B5_A - [15:0] */ 3144*4882a593Smuzhiyun 3145*4882a593Smuzhiyun /* 3146*4882a593Smuzhiyun * R354 (0x162) - EQ20 3147*4882a593Smuzhiyun */ 3148*4882a593Smuzhiyun #define WM8962_EQL_B5_B_MASK 0xFFFF /* EQL_B5_B - [15:0] */ 3149*4882a593Smuzhiyun #define WM8962_EQL_B5_B_SHIFT 0 /* EQL_B5_B - [15:0] */ 3150*4882a593Smuzhiyun #define WM8962_EQL_B5_B_WIDTH 16 /* EQL_B5_B - [15:0] */ 3151*4882a593Smuzhiyun 3152*4882a593Smuzhiyun /* 3153*4882a593Smuzhiyun * R355 (0x163) - EQ21 3154*4882a593Smuzhiyun */ 3155*4882a593Smuzhiyun #define WM8962_EQL_B5_PG_MASK 0xFFFF /* EQL_B5_PG - [15:0] */ 3156*4882a593Smuzhiyun #define WM8962_EQL_B5_PG_SHIFT 0 /* EQL_B5_PG - [15:0] */ 3157*4882a593Smuzhiyun #define WM8962_EQL_B5_PG_WIDTH 16 /* EQL_B5_PG - [15:0] */ 3158*4882a593Smuzhiyun 3159*4882a593Smuzhiyun /* 3160*4882a593Smuzhiyun * R356 (0x164) - EQ22 3161*4882a593Smuzhiyun */ 3162*4882a593Smuzhiyun #define WM8962_EQR_B1_GAIN_MASK 0xF800 /* EQR_B1_GAIN - [15:11] */ 3163*4882a593Smuzhiyun #define WM8962_EQR_B1_GAIN_SHIFT 11 /* EQR_B1_GAIN - [15:11] */ 3164*4882a593Smuzhiyun #define WM8962_EQR_B1_GAIN_WIDTH 5 /* EQR_B1_GAIN - [15:11] */ 3165*4882a593Smuzhiyun #define WM8962_EQR_B2_GAIN_MASK 0x07C0 /* EQR_B2_GAIN - [10:6] */ 3166*4882a593Smuzhiyun #define WM8962_EQR_B2_GAIN_SHIFT 6 /* EQR_B2_GAIN - [10:6] */ 3167*4882a593Smuzhiyun #define WM8962_EQR_B2_GAIN_WIDTH 5 /* EQR_B2_GAIN - [10:6] */ 3168*4882a593Smuzhiyun #define WM8962_EQR_B3_GAIN_MASK 0x003E /* EQR_B3_GAIN - [5:1] */ 3169*4882a593Smuzhiyun #define WM8962_EQR_B3_GAIN_SHIFT 1 /* EQR_B3_GAIN - [5:1] */ 3170*4882a593Smuzhiyun #define WM8962_EQR_B3_GAIN_WIDTH 5 /* EQR_B3_GAIN - [5:1] */ 3171*4882a593Smuzhiyun 3172*4882a593Smuzhiyun /* 3173*4882a593Smuzhiyun * R357 (0x165) - EQ23 3174*4882a593Smuzhiyun */ 3175*4882a593Smuzhiyun #define WM8962_EQR_B4_GAIN_MASK 0xF800 /* EQR_B4_GAIN - [15:11] */ 3176*4882a593Smuzhiyun #define WM8962_EQR_B4_GAIN_SHIFT 11 /* EQR_B4_GAIN - [15:11] */ 3177*4882a593Smuzhiyun #define WM8962_EQR_B4_GAIN_WIDTH 5 /* EQR_B4_GAIN - [15:11] */ 3178*4882a593Smuzhiyun #define WM8962_EQR_B5_GAIN_MASK 0x07C0 /* EQR_B5_GAIN - [10:6] */ 3179*4882a593Smuzhiyun #define WM8962_EQR_B5_GAIN_SHIFT 6 /* EQR_B5_GAIN - [10:6] */ 3180*4882a593Smuzhiyun #define WM8962_EQR_B5_GAIN_WIDTH 5 /* EQR_B5_GAIN - [10:6] */ 3181*4882a593Smuzhiyun 3182*4882a593Smuzhiyun /* 3183*4882a593Smuzhiyun * R358 (0x166) - EQ24 3184*4882a593Smuzhiyun */ 3185*4882a593Smuzhiyun #define WM8962_EQR_B1_A_MASK 0xFFFF /* EQR_B1_A - [15:0] */ 3186*4882a593Smuzhiyun #define WM8962_EQR_B1_A_SHIFT 0 /* EQR_B1_A - [15:0] */ 3187*4882a593Smuzhiyun #define WM8962_EQR_B1_A_WIDTH 16 /* EQR_B1_A - [15:0] */ 3188*4882a593Smuzhiyun 3189*4882a593Smuzhiyun /* 3190*4882a593Smuzhiyun * R359 (0x167) - EQ25 3191*4882a593Smuzhiyun */ 3192*4882a593Smuzhiyun #define WM8962_EQR_B1_B_MASK 0xFFFF /* EQR_B1_B - [15:0] */ 3193*4882a593Smuzhiyun #define WM8962_EQR_B1_B_SHIFT 0 /* EQR_B1_B - [15:0] */ 3194*4882a593Smuzhiyun #define WM8962_EQR_B1_B_WIDTH 16 /* EQR_B1_B - [15:0] */ 3195*4882a593Smuzhiyun 3196*4882a593Smuzhiyun /* 3197*4882a593Smuzhiyun * R360 (0x168) - EQ26 3198*4882a593Smuzhiyun */ 3199*4882a593Smuzhiyun #define WM8962_EQR_B1_PG_MASK 0xFFFF /* EQR_B1_PG - [15:0] */ 3200*4882a593Smuzhiyun #define WM8962_EQR_B1_PG_SHIFT 0 /* EQR_B1_PG - [15:0] */ 3201*4882a593Smuzhiyun #define WM8962_EQR_B1_PG_WIDTH 16 /* EQR_B1_PG - [15:0] */ 3202*4882a593Smuzhiyun 3203*4882a593Smuzhiyun /* 3204*4882a593Smuzhiyun * R361 (0x169) - EQ27 3205*4882a593Smuzhiyun */ 3206*4882a593Smuzhiyun #define WM8962_EQR_B2_A_MASK 0xFFFF /* EQR_B2_A - [15:0] */ 3207*4882a593Smuzhiyun #define WM8962_EQR_B2_A_SHIFT 0 /* EQR_B2_A - [15:0] */ 3208*4882a593Smuzhiyun #define WM8962_EQR_B2_A_WIDTH 16 /* EQR_B2_A - [15:0] */ 3209*4882a593Smuzhiyun 3210*4882a593Smuzhiyun /* 3211*4882a593Smuzhiyun * R362 (0x16A) - EQ28 3212*4882a593Smuzhiyun */ 3213*4882a593Smuzhiyun #define WM8962_EQR_B2_B_MASK 0xFFFF /* EQR_B2_B - [15:0] */ 3214*4882a593Smuzhiyun #define WM8962_EQR_B2_B_SHIFT 0 /* EQR_B2_B - [15:0] */ 3215*4882a593Smuzhiyun #define WM8962_EQR_B2_B_WIDTH 16 /* EQR_B2_B - [15:0] */ 3216*4882a593Smuzhiyun 3217*4882a593Smuzhiyun /* 3218*4882a593Smuzhiyun * R363 (0x16B) - EQ29 3219*4882a593Smuzhiyun */ 3220*4882a593Smuzhiyun #define WM8962_EQR_B2_C_MASK 0xFFFF /* EQR_B2_C - [15:0] */ 3221*4882a593Smuzhiyun #define WM8962_EQR_B2_C_SHIFT 0 /* EQR_B2_C - [15:0] */ 3222*4882a593Smuzhiyun #define WM8962_EQR_B2_C_WIDTH 16 /* EQR_B2_C - [15:0] */ 3223*4882a593Smuzhiyun 3224*4882a593Smuzhiyun /* 3225*4882a593Smuzhiyun * R364 (0x16C) - EQ30 3226*4882a593Smuzhiyun */ 3227*4882a593Smuzhiyun #define WM8962_EQR_B2_PG_MASK 0xFFFF /* EQR_B2_PG - [15:0] */ 3228*4882a593Smuzhiyun #define WM8962_EQR_B2_PG_SHIFT 0 /* EQR_B2_PG - [15:0] */ 3229*4882a593Smuzhiyun #define WM8962_EQR_B2_PG_WIDTH 16 /* EQR_B2_PG - [15:0] */ 3230*4882a593Smuzhiyun 3231*4882a593Smuzhiyun /* 3232*4882a593Smuzhiyun * R365 (0x16D) - EQ31 3233*4882a593Smuzhiyun */ 3234*4882a593Smuzhiyun #define WM8962_EQR_B3_A_MASK 0xFFFF /* EQR_B3_A - [15:0] */ 3235*4882a593Smuzhiyun #define WM8962_EQR_B3_A_SHIFT 0 /* EQR_B3_A - [15:0] */ 3236*4882a593Smuzhiyun #define WM8962_EQR_B3_A_WIDTH 16 /* EQR_B3_A - [15:0] */ 3237*4882a593Smuzhiyun 3238*4882a593Smuzhiyun /* 3239*4882a593Smuzhiyun * R366 (0x16E) - EQ32 3240*4882a593Smuzhiyun */ 3241*4882a593Smuzhiyun #define WM8962_EQR_B3_B_MASK 0xFFFF /* EQR_B3_B - [15:0] */ 3242*4882a593Smuzhiyun #define WM8962_EQR_B3_B_SHIFT 0 /* EQR_B3_B - [15:0] */ 3243*4882a593Smuzhiyun #define WM8962_EQR_B3_B_WIDTH 16 /* EQR_B3_B - [15:0] */ 3244*4882a593Smuzhiyun 3245*4882a593Smuzhiyun /* 3246*4882a593Smuzhiyun * R367 (0x16F) - EQ33 3247*4882a593Smuzhiyun */ 3248*4882a593Smuzhiyun #define WM8962_EQR_B3_C_MASK 0xFFFF /* EQR_B3_C - [15:0] */ 3249*4882a593Smuzhiyun #define WM8962_EQR_B3_C_SHIFT 0 /* EQR_B3_C - [15:0] */ 3250*4882a593Smuzhiyun #define WM8962_EQR_B3_C_WIDTH 16 /* EQR_B3_C - [15:0] */ 3251*4882a593Smuzhiyun 3252*4882a593Smuzhiyun /* 3253*4882a593Smuzhiyun * R368 (0x170) - EQ34 3254*4882a593Smuzhiyun */ 3255*4882a593Smuzhiyun #define WM8962_EQR_B3_PG_MASK 0xFFFF /* EQR_B3_PG - [15:0] */ 3256*4882a593Smuzhiyun #define WM8962_EQR_B3_PG_SHIFT 0 /* EQR_B3_PG - [15:0] */ 3257*4882a593Smuzhiyun #define WM8962_EQR_B3_PG_WIDTH 16 /* EQR_B3_PG - [15:0] */ 3258*4882a593Smuzhiyun 3259*4882a593Smuzhiyun /* 3260*4882a593Smuzhiyun * R369 (0x171) - EQ35 3261*4882a593Smuzhiyun */ 3262*4882a593Smuzhiyun #define WM8962_EQR_B4_A_MASK 0xFFFF /* EQR_B4_A - [15:0] */ 3263*4882a593Smuzhiyun #define WM8962_EQR_B4_A_SHIFT 0 /* EQR_B4_A - [15:0] */ 3264*4882a593Smuzhiyun #define WM8962_EQR_B4_A_WIDTH 16 /* EQR_B4_A - [15:0] */ 3265*4882a593Smuzhiyun 3266*4882a593Smuzhiyun /* 3267*4882a593Smuzhiyun * R370 (0x172) - EQ36 3268*4882a593Smuzhiyun */ 3269*4882a593Smuzhiyun #define WM8962_EQR_B4_B_MASK 0xFFFF /* EQR_B4_B - [15:0] */ 3270*4882a593Smuzhiyun #define WM8962_EQR_B4_B_SHIFT 0 /* EQR_B4_B - [15:0] */ 3271*4882a593Smuzhiyun #define WM8962_EQR_B4_B_WIDTH 16 /* EQR_B4_B - [15:0] */ 3272*4882a593Smuzhiyun 3273*4882a593Smuzhiyun /* 3274*4882a593Smuzhiyun * R371 (0x173) - EQ37 3275*4882a593Smuzhiyun */ 3276*4882a593Smuzhiyun #define WM8962_EQR_B4_C_MASK 0xFFFF /* EQR_B4_C - [15:0] */ 3277*4882a593Smuzhiyun #define WM8962_EQR_B4_C_SHIFT 0 /* EQR_B4_C - [15:0] */ 3278*4882a593Smuzhiyun #define WM8962_EQR_B4_C_WIDTH 16 /* EQR_B4_C - [15:0] */ 3279*4882a593Smuzhiyun 3280*4882a593Smuzhiyun /* 3281*4882a593Smuzhiyun * R372 (0x174) - EQ38 3282*4882a593Smuzhiyun */ 3283*4882a593Smuzhiyun #define WM8962_EQR_B4_PG_MASK 0xFFFF /* EQR_B4_PG - [15:0] */ 3284*4882a593Smuzhiyun #define WM8962_EQR_B4_PG_SHIFT 0 /* EQR_B4_PG - [15:0] */ 3285*4882a593Smuzhiyun #define WM8962_EQR_B4_PG_WIDTH 16 /* EQR_B4_PG - [15:0] */ 3286*4882a593Smuzhiyun 3287*4882a593Smuzhiyun /* 3288*4882a593Smuzhiyun * R373 (0x175) - EQ39 3289*4882a593Smuzhiyun */ 3290*4882a593Smuzhiyun #define WM8962_EQR_B5_A_MASK 0xFFFF /* EQR_B5_A - [15:0] */ 3291*4882a593Smuzhiyun #define WM8962_EQR_B5_A_SHIFT 0 /* EQR_B5_A - [15:0] */ 3292*4882a593Smuzhiyun #define WM8962_EQR_B5_A_WIDTH 16 /* EQR_B5_A - [15:0] */ 3293*4882a593Smuzhiyun 3294*4882a593Smuzhiyun /* 3295*4882a593Smuzhiyun * R374 (0x176) - EQ40 3296*4882a593Smuzhiyun */ 3297*4882a593Smuzhiyun #define WM8962_EQR_B5_B_MASK 0xFFFF /* EQR_B5_B - [15:0] */ 3298*4882a593Smuzhiyun #define WM8962_EQR_B5_B_SHIFT 0 /* EQR_B5_B - [15:0] */ 3299*4882a593Smuzhiyun #define WM8962_EQR_B5_B_WIDTH 16 /* EQR_B5_B - [15:0] */ 3300*4882a593Smuzhiyun 3301*4882a593Smuzhiyun /* 3302*4882a593Smuzhiyun * R375 (0x177) - EQ41 3303*4882a593Smuzhiyun */ 3304*4882a593Smuzhiyun #define WM8962_EQR_B5_PG_MASK 0xFFFF /* EQR_B5_PG - [15:0] */ 3305*4882a593Smuzhiyun #define WM8962_EQR_B5_PG_SHIFT 0 /* EQR_B5_PG - [15:0] */ 3306*4882a593Smuzhiyun #define WM8962_EQR_B5_PG_WIDTH 16 /* EQR_B5_PG - [15:0] */ 3307*4882a593Smuzhiyun 3308*4882a593Smuzhiyun /* 3309*4882a593Smuzhiyun * R513 (0x201) - GPIO 2 3310*4882a593Smuzhiyun */ 3311*4882a593Smuzhiyun #define WM8962_GP2_POL 0x0400 /* GP2_POL */ 3312*4882a593Smuzhiyun #define WM8962_GP2_POL_MASK 0x0400 /* GP2_POL */ 3313*4882a593Smuzhiyun #define WM8962_GP2_POL_SHIFT 10 /* GP2_POL */ 3314*4882a593Smuzhiyun #define WM8962_GP2_POL_WIDTH 1 /* GP2_POL */ 3315*4882a593Smuzhiyun #define WM8962_GP2_LVL 0x0040 /* GP2_LVL */ 3316*4882a593Smuzhiyun #define WM8962_GP2_LVL_MASK 0x0040 /* GP2_LVL */ 3317*4882a593Smuzhiyun #define WM8962_GP2_LVL_SHIFT 6 /* GP2_LVL */ 3318*4882a593Smuzhiyun #define WM8962_GP2_LVL_WIDTH 1 /* GP2_LVL */ 3319*4882a593Smuzhiyun #define WM8962_GP2_FN_MASK 0x001F /* GP2_FN - [4:0] */ 3320*4882a593Smuzhiyun #define WM8962_GP2_FN_SHIFT 0 /* GP2_FN - [4:0] */ 3321*4882a593Smuzhiyun #define WM8962_GP2_FN_WIDTH 5 /* GP2_FN - [4:0] */ 3322*4882a593Smuzhiyun 3323*4882a593Smuzhiyun /* 3324*4882a593Smuzhiyun * R514 (0x202) - GPIO 3 3325*4882a593Smuzhiyun */ 3326*4882a593Smuzhiyun #define WM8962_GP3_POL 0x0400 /* GP3_POL */ 3327*4882a593Smuzhiyun #define WM8962_GP3_POL_MASK 0x0400 /* GP3_POL */ 3328*4882a593Smuzhiyun #define WM8962_GP3_POL_SHIFT 10 /* GP3_POL */ 3329*4882a593Smuzhiyun #define WM8962_GP3_POL_WIDTH 1 /* GP3_POL */ 3330*4882a593Smuzhiyun #define WM8962_GP3_LVL 0x0040 /* GP3_LVL */ 3331*4882a593Smuzhiyun #define WM8962_GP3_LVL_MASK 0x0040 /* GP3_LVL */ 3332*4882a593Smuzhiyun #define WM8962_GP3_LVL_SHIFT 6 /* GP3_LVL */ 3333*4882a593Smuzhiyun #define WM8962_GP3_LVL_WIDTH 1 /* GP3_LVL */ 3334*4882a593Smuzhiyun #define WM8962_GP3_FN_MASK 0x001F /* GP3_FN - [4:0] */ 3335*4882a593Smuzhiyun #define WM8962_GP3_FN_SHIFT 0 /* GP3_FN - [4:0] */ 3336*4882a593Smuzhiyun #define WM8962_GP3_FN_WIDTH 5 /* GP3_FN - [4:0] */ 3337*4882a593Smuzhiyun 3338*4882a593Smuzhiyun /* 3339*4882a593Smuzhiyun * R516 (0x204) - GPIO 5 3340*4882a593Smuzhiyun */ 3341*4882a593Smuzhiyun #define WM8962_GP5_DIR 0x8000 /* GP5_DIR */ 3342*4882a593Smuzhiyun #define WM8962_GP5_DIR_MASK 0x8000 /* GP5_DIR */ 3343*4882a593Smuzhiyun #define WM8962_GP5_DIR_SHIFT 15 /* GP5_DIR */ 3344*4882a593Smuzhiyun #define WM8962_GP5_DIR_WIDTH 1 /* GP5_DIR */ 3345*4882a593Smuzhiyun #define WM8962_GP5_PU 0x4000 /* GP5_PU */ 3346*4882a593Smuzhiyun #define WM8962_GP5_PU_MASK 0x4000 /* GP5_PU */ 3347*4882a593Smuzhiyun #define WM8962_GP5_PU_SHIFT 14 /* GP5_PU */ 3348*4882a593Smuzhiyun #define WM8962_GP5_PU_WIDTH 1 /* GP5_PU */ 3349*4882a593Smuzhiyun #define WM8962_GP5_PD 0x2000 /* GP5_PD */ 3350*4882a593Smuzhiyun #define WM8962_GP5_PD_MASK 0x2000 /* GP5_PD */ 3351*4882a593Smuzhiyun #define WM8962_GP5_PD_SHIFT 13 /* GP5_PD */ 3352*4882a593Smuzhiyun #define WM8962_GP5_PD_WIDTH 1 /* GP5_PD */ 3353*4882a593Smuzhiyun #define WM8962_GP5_POL 0x0400 /* GP5_POL */ 3354*4882a593Smuzhiyun #define WM8962_GP5_POL_MASK 0x0400 /* GP5_POL */ 3355*4882a593Smuzhiyun #define WM8962_GP5_POL_SHIFT 10 /* GP5_POL */ 3356*4882a593Smuzhiyun #define WM8962_GP5_POL_WIDTH 1 /* GP5_POL */ 3357*4882a593Smuzhiyun #define WM8962_GP5_OP_CFG 0x0200 /* GP5_OP_CFG */ 3358*4882a593Smuzhiyun #define WM8962_GP5_OP_CFG_MASK 0x0200 /* GP5_OP_CFG */ 3359*4882a593Smuzhiyun #define WM8962_GP5_OP_CFG_SHIFT 9 /* GP5_OP_CFG */ 3360*4882a593Smuzhiyun #define WM8962_GP5_OP_CFG_WIDTH 1 /* GP5_OP_CFG */ 3361*4882a593Smuzhiyun #define WM8962_GP5_DB 0x0100 /* GP5_DB */ 3362*4882a593Smuzhiyun #define WM8962_GP5_DB_MASK 0x0100 /* GP5_DB */ 3363*4882a593Smuzhiyun #define WM8962_GP5_DB_SHIFT 8 /* GP5_DB */ 3364*4882a593Smuzhiyun #define WM8962_GP5_DB_WIDTH 1 /* GP5_DB */ 3365*4882a593Smuzhiyun #define WM8962_GP5_LVL 0x0040 /* GP5_LVL */ 3366*4882a593Smuzhiyun #define WM8962_GP5_LVL_MASK 0x0040 /* GP5_LVL */ 3367*4882a593Smuzhiyun #define WM8962_GP5_LVL_SHIFT 6 /* GP5_LVL */ 3368*4882a593Smuzhiyun #define WM8962_GP5_LVL_WIDTH 1 /* GP5_LVL */ 3369*4882a593Smuzhiyun #define WM8962_GP5_FN_MASK 0x001F /* GP5_FN - [4:0] */ 3370*4882a593Smuzhiyun #define WM8962_GP5_FN_SHIFT 0 /* GP5_FN - [4:0] */ 3371*4882a593Smuzhiyun #define WM8962_GP5_FN_WIDTH 5 /* GP5_FN - [4:0] */ 3372*4882a593Smuzhiyun 3373*4882a593Smuzhiyun /* 3374*4882a593Smuzhiyun * R517 (0x205) - GPIO 6 3375*4882a593Smuzhiyun */ 3376*4882a593Smuzhiyun #define WM8962_GP6_DIR 0x8000 /* GP6_DIR */ 3377*4882a593Smuzhiyun #define WM8962_GP6_DIR_MASK 0x8000 /* GP6_DIR */ 3378*4882a593Smuzhiyun #define WM8962_GP6_DIR_SHIFT 15 /* GP6_DIR */ 3379*4882a593Smuzhiyun #define WM8962_GP6_DIR_WIDTH 1 /* GP6_DIR */ 3380*4882a593Smuzhiyun #define WM8962_GP6_PU 0x4000 /* GP6_PU */ 3381*4882a593Smuzhiyun #define WM8962_GP6_PU_MASK 0x4000 /* GP6_PU */ 3382*4882a593Smuzhiyun #define WM8962_GP6_PU_SHIFT 14 /* GP6_PU */ 3383*4882a593Smuzhiyun #define WM8962_GP6_PU_WIDTH 1 /* GP6_PU */ 3384*4882a593Smuzhiyun #define WM8962_GP6_PD 0x2000 /* GP6_PD */ 3385*4882a593Smuzhiyun #define WM8962_GP6_PD_MASK 0x2000 /* GP6_PD */ 3386*4882a593Smuzhiyun #define WM8962_GP6_PD_SHIFT 13 /* GP6_PD */ 3387*4882a593Smuzhiyun #define WM8962_GP6_PD_WIDTH 1 /* GP6_PD */ 3388*4882a593Smuzhiyun #define WM8962_GP6_POL 0x0400 /* GP6_POL */ 3389*4882a593Smuzhiyun #define WM8962_GP6_POL_MASK 0x0400 /* GP6_POL */ 3390*4882a593Smuzhiyun #define WM8962_GP6_POL_SHIFT 10 /* GP6_POL */ 3391*4882a593Smuzhiyun #define WM8962_GP6_POL_WIDTH 1 /* GP6_POL */ 3392*4882a593Smuzhiyun #define WM8962_GP6_OP_CFG 0x0200 /* GP6_OP_CFG */ 3393*4882a593Smuzhiyun #define WM8962_GP6_OP_CFG_MASK 0x0200 /* GP6_OP_CFG */ 3394*4882a593Smuzhiyun #define WM8962_GP6_OP_CFG_SHIFT 9 /* GP6_OP_CFG */ 3395*4882a593Smuzhiyun #define WM8962_GP6_OP_CFG_WIDTH 1 /* GP6_OP_CFG */ 3396*4882a593Smuzhiyun #define WM8962_GP6_DB 0x0100 /* GP6_DB */ 3397*4882a593Smuzhiyun #define WM8962_GP6_DB_MASK 0x0100 /* GP6_DB */ 3398*4882a593Smuzhiyun #define WM8962_GP6_DB_SHIFT 8 /* GP6_DB */ 3399*4882a593Smuzhiyun #define WM8962_GP6_DB_WIDTH 1 /* GP6_DB */ 3400*4882a593Smuzhiyun #define WM8962_GP6_LVL 0x0040 /* GP6_LVL */ 3401*4882a593Smuzhiyun #define WM8962_GP6_LVL_MASK 0x0040 /* GP6_LVL */ 3402*4882a593Smuzhiyun #define WM8962_GP6_LVL_SHIFT 6 /* GP6_LVL */ 3403*4882a593Smuzhiyun #define WM8962_GP6_LVL_WIDTH 1 /* GP6_LVL */ 3404*4882a593Smuzhiyun #define WM8962_GP6_FN_MASK 0x001F /* GP6_FN - [4:0] */ 3405*4882a593Smuzhiyun #define WM8962_GP6_FN_SHIFT 0 /* GP6_FN - [4:0] */ 3406*4882a593Smuzhiyun #define WM8962_GP6_FN_WIDTH 5 /* GP6_FN - [4:0] */ 3407*4882a593Smuzhiyun 3408*4882a593Smuzhiyun /* 3409*4882a593Smuzhiyun * R560 (0x230) - Interrupt Status 1 3410*4882a593Smuzhiyun */ 3411*4882a593Smuzhiyun #define WM8962_GP6_EINT 0x0020 /* GP6_EINT */ 3412*4882a593Smuzhiyun #define WM8962_GP6_EINT_MASK 0x0020 /* GP6_EINT */ 3413*4882a593Smuzhiyun #define WM8962_GP6_EINT_SHIFT 5 /* GP6_EINT */ 3414*4882a593Smuzhiyun #define WM8962_GP6_EINT_WIDTH 1 /* GP6_EINT */ 3415*4882a593Smuzhiyun #define WM8962_GP5_EINT 0x0010 /* GP5_EINT */ 3416*4882a593Smuzhiyun #define WM8962_GP5_EINT_MASK 0x0010 /* GP5_EINT */ 3417*4882a593Smuzhiyun #define WM8962_GP5_EINT_SHIFT 4 /* GP5_EINT */ 3418*4882a593Smuzhiyun #define WM8962_GP5_EINT_WIDTH 1 /* GP5_EINT */ 3419*4882a593Smuzhiyun 3420*4882a593Smuzhiyun /* 3421*4882a593Smuzhiyun * R561 (0x231) - Interrupt Status 2 3422*4882a593Smuzhiyun */ 3423*4882a593Smuzhiyun #define WM8962_MICSCD_EINT 0x8000 /* MICSCD_EINT */ 3424*4882a593Smuzhiyun #define WM8962_MICSCD_EINT_MASK 0x8000 /* MICSCD_EINT */ 3425*4882a593Smuzhiyun #define WM8962_MICSCD_EINT_SHIFT 15 /* MICSCD_EINT */ 3426*4882a593Smuzhiyun #define WM8962_MICSCD_EINT_WIDTH 1 /* MICSCD_EINT */ 3427*4882a593Smuzhiyun #define WM8962_MICD_EINT 0x4000 /* MICD_EINT */ 3428*4882a593Smuzhiyun #define WM8962_MICD_EINT_MASK 0x4000 /* MICD_EINT */ 3429*4882a593Smuzhiyun #define WM8962_MICD_EINT_SHIFT 14 /* MICD_EINT */ 3430*4882a593Smuzhiyun #define WM8962_MICD_EINT_WIDTH 1 /* MICD_EINT */ 3431*4882a593Smuzhiyun #define WM8962_FIFOS_ERR_EINT 0x2000 /* FIFOS_ERR_EINT */ 3432*4882a593Smuzhiyun #define WM8962_FIFOS_ERR_EINT_MASK 0x2000 /* FIFOS_ERR_EINT */ 3433*4882a593Smuzhiyun #define WM8962_FIFOS_ERR_EINT_SHIFT 13 /* FIFOS_ERR_EINT */ 3434*4882a593Smuzhiyun #define WM8962_FIFOS_ERR_EINT_WIDTH 1 /* FIFOS_ERR_EINT */ 3435*4882a593Smuzhiyun #define WM8962_ALC_LOCK_EINT 0x1000 /* ALC_LOCK_EINT */ 3436*4882a593Smuzhiyun #define WM8962_ALC_LOCK_EINT_MASK 0x1000 /* ALC_LOCK_EINT */ 3437*4882a593Smuzhiyun #define WM8962_ALC_LOCK_EINT_SHIFT 12 /* ALC_LOCK_EINT */ 3438*4882a593Smuzhiyun #define WM8962_ALC_LOCK_EINT_WIDTH 1 /* ALC_LOCK_EINT */ 3439*4882a593Smuzhiyun #define WM8962_ALC_THRESH_EINT 0x0800 /* ALC_THRESH_EINT */ 3440*4882a593Smuzhiyun #define WM8962_ALC_THRESH_EINT_MASK 0x0800 /* ALC_THRESH_EINT */ 3441*4882a593Smuzhiyun #define WM8962_ALC_THRESH_EINT_SHIFT 11 /* ALC_THRESH_EINT */ 3442*4882a593Smuzhiyun #define WM8962_ALC_THRESH_EINT_WIDTH 1 /* ALC_THRESH_EINT */ 3443*4882a593Smuzhiyun #define WM8962_ALC_SAT_EINT 0x0400 /* ALC_SAT_EINT */ 3444*4882a593Smuzhiyun #define WM8962_ALC_SAT_EINT_MASK 0x0400 /* ALC_SAT_EINT */ 3445*4882a593Smuzhiyun #define WM8962_ALC_SAT_EINT_SHIFT 10 /* ALC_SAT_EINT */ 3446*4882a593Smuzhiyun #define WM8962_ALC_SAT_EINT_WIDTH 1 /* ALC_SAT_EINT */ 3447*4882a593Smuzhiyun #define WM8962_ALC_PKOVR_EINT 0x0200 /* ALC_PKOVR_EINT */ 3448*4882a593Smuzhiyun #define WM8962_ALC_PKOVR_EINT_MASK 0x0200 /* ALC_PKOVR_EINT */ 3449*4882a593Smuzhiyun #define WM8962_ALC_PKOVR_EINT_SHIFT 9 /* ALC_PKOVR_EINT */ 3450*4882a593Smuzhiyun #define WM8962_ALC_PKOVR_EINT_WIDTH 1 /* ALC_PKOVR_EINT */ 3451*4882a593Smuzhiyun #define WM8962_ALC_NGATE_EINT 0x0100 /* ALC_NGATE_EINT */ 3452*4882a593Smuzhiyun #define WM8962_ALC_NGATE_EINT_MASK 0x0100 /* ALC_NGATE_EINT */ 3453*4882a593Smuzhiyun #define WM8962_ALC_NGATE_EINT_SHIFT 8 /* ALC_NGATE_EINT */ 3454*4882a593Smuzhiyun #define WM8962_ALC_NGATE_EINT_WIDTH 1 /* ALC_NGATE_EINT */ 3455*4882a593Smuzhiyun #define WM8962_WSEQ_DONE_EINT 0x0080 /* WSEQ_DONE_EINT */ 3456*4882a593Smuzhiyun #define WM8962_WSEQ_DONE_EINT_MASK 0x0080 /* WSEQ_DONE_EINT */ 3457*4882a593Smuzhiyun #define WM8962_WSEQ_DONE_EINT_SHIFT 7 /* WSEQ_DONE_EINT */ 3458*4882a593Smuzhiyun #define WM8962_WSEQ_DONE_EINT_WIDTH 1 /* WSEQ_DONE_EINT */ 3459*4882a593Smuzhiyun #define WM8962_DRC_ACTDET_EINT 0x0040 /* DRC_ACTDET_EINT */ 3460*4882a593Smuzhiyun #define WM8962_DRC_ACTDET_EINT_MASK 0x0040 /* DRC_ACTDET_EINT */ 3461*4882a593Smuzhiyun #define WM8962_DRC_ACTDET_EINT_SHIFT 6 /* DRC_ACTDET_EINT */ 3462*4882a593Smuzhiyun #define WM8962_DRC_ACTDET_EINT_WIDTH 1 /* DRC_ACTDET_EINT */ 3463*4882a593Smuzhiyun #define WM8962_FLL_LOCK_EINT 0x0020 /* FLL_LOCK_EINT */ 3464*4882a593Smuzhiyun #define WM8962_FLL_LOCK_EINT_MASK 0x0020 /* FLL_LOCK_EINT */ 3465*4882a593Smuzhiyun #define WM8962_FLL_LOCK_EINT_SHIFT 5 /* FLL_LOCK_EINT */ 3466*4882a593Smuzhiyun #define WM8962_FLL_LOCK_EINT_WIDTH 1 /* FLL_LOCK_EINT */ 3467*4882a593Smuzhiyun #define WM8962_PLL3_LOCK_EINT 0x0008 /* PLL3_LOCK_EINT */ 3468*4882a593Smuzhiyun #define WM8962_PLL3_LOCK_EINT_MASK 0x0008 /* PLL3_LOCK_EINT */ 3469*4882a593Smuzhiyun #define WM8962_PLL3_LOCK_EINT_SHIFT 3 /* PLL3_LOCK_EINT */ 3470*4882a593Smuzhiyun #define WM8962_PLL3_LOCK_EINT_WIDTH 1 /* PLL3_LOCK_EINT */ 3471*4882a593Smuzhiyun #define WM8962_PLL2_LOCK_EINT 0x0004 /* PLL2_LOCK_EINT */ 3472*4882a593Smuzhiyun #define WM8962_PLL2_LOCK_EINT_MASK 0x0004 /* PLL2_LOCK_EINT */ 3473*4882a593Smuzhiyun #define WM8962_PLL2_LOCK_EINT_SHIFT 2 /* PLL2_LOCK_EINT */ 3474*4882a593Smuzhiyun #define WM8962_PLL2_LOCK_EINT_WIDTH 1 /* PLL2_LOCK_EINT */ 3475*4882a593Smuzhiyun #define WM8962_TEMP_SHUT_EINT 0x0001 /* TEMP_SHUT_EINT */ 3476*4882a593Smuzhiyun #define WM8962_TEMP_SHUT_EINT_MASK 0x0001 /* TEMP_SHUT_EINT */ 3477*4882a593Smuzhiyun #define WM8962_TEMP_SHUT_EINT_SHIFT 0 /* TEMP_SHUT_EINT */ 3478*4882a593Smuzhiyun #define WM8962_TEMP_SHUT_EINT_WIDTH 1 /* TEMP_SHUT_EINT */ 3479*4882a593Smuzhiyun 3480*4882a593Smuzhiyun /* 3481*4882a593Smuzhiyun * R568 (0x238) - Interrupt Status 1 Mask 3482*4882a593Smuzhiyun */ 3483*4882a593Smuzhiyun #define WM8962_IM_GP6_EINT 0x0020 /* IM_GP6_EINT */ 3484*4882a593Smuzhiyun #define WM8962_IM_GP6_EINT_MASK 0x0020 /* IM_GP6_EINT */ 3485*4882a593Smuzhiyun #define WM8962_IM_GP6_EINT_SHIFT 5 /* IM_GP6_EINT */ 3486*4882a593Smuzhiyun #define WM8962_IM_GP6_EINT_WIDTH 1 /* IM_GP6_EINT */ 3487*4882a593Smuzhiyun #define WM8962_IM_GP5_EINT 0x0010 /* IM_GP5_EINT */ 3488*4882a593Smuzhiyun #define WM8962_IM_GP5_EINT_MASK 0x0010 /* IM_GP5_EINT */ 3489*4882a593Smuzhiyun #define WM8962_IM_GP5_EINT_SHIFT 4 /* IM_GP5_EINT */ 3490*4882a593Smuzhiyun #define WM8962_IM_GP5_EINT_WIDTH 1 /* IM_GP5_EINT */ 3491*4882a593Smuzhiyun 3492*4882a593Smuzhiyun /* 3493*4882a593Smuzhiyun * R569 (0x239) - Interrupt Status 2 Mask 3494*4882a593Smuzhiyun */ 3495*4882a593Smuzhiyun #define WM8962_IM_MICSCD_EINT 0x8000 /* IM_MICSCD_EINT */ 3496*4882a593Smuzhiyun #define WM8962_IM_MICSCD_EINT_MASK 0x8000 /* IM_MICSCD_EINT */ 3497*4882a593Smuzhiyun #define WM8962_IM_MICSCD_EINT_SHIFT 15 /* IM_MICSCD_EINT */ 3498*4882a593Smuzhiyun #define WM8962_IM_MICSCD_EINT_WIDTH 1 /* IM_MICSCD_EINT */ 3499*4882a593Smuzhiyun #define WM8962_IM_MICD_EINT 0x4000 /* IM_MICD_EINT */ 3500*4882a593Smuzhiyun #define WM8962_IM_MICD_EINT_MASK 0x4000 /* IM_MICD_EINT */ 3501*4882a593Smuzhiyun #define WM8962_IM_MICD_EINT_SHIFT 14 /* IM_MICD_EINT */ 3502*4882a593Smuzhiyun #define WM8962_IM_MICD_EINT_WIDTH 1 /* IM_MICD_EINT */ 3503*4882a593Smuzhiyun #define WM8962_IM_FIFOS_ERR_EINT 0x2000 /* IM_FIFOS_ERR_EINT */ 3504*4882a593Smuzhiyun #define WM8962_IM_FIFOS_ERR_EINT_MASK 0x2000 /* IM_FIFOS_ERR_EINT */ 3505*4882a593Smuzhiyun #define WM8962_IM_FIFOS_ERR_EINT_SHIFT 13 /* IM_FIFOS_ERR_EINT */ 3506*4882a593Smuzhiyun #define WM8962_IM_FIFOS_ERR_EINT_WIDTH 1 /* IM_FIFOS_ERR_EINT */ 3507*4882a593Smuzhiyun #define WM8962_IM_ALC_LOCK_EINT 0x1000 /* IM_ALC_LOCK_EINT */ 3508*4882a593Smuzhiyun #define WM8962_IM_ALC_LOCK_EINT_MASK 0x1000 /* IM_ALC_LOCK_EINT */ 3509*4882a593Smuzhiyun #define WM8962_IM_ALC_LOCK_EINT_SHIFT 12 /* IM_ALC_LOCK_EINT */ 3510*4882a593Smuzhiyun #define WM8962_IM_ALC_LOCK_EINT_WIDTH 1 /* IM_ALC_LOCK_EINT */ 3511*4882a593Smuzhiyun #define WM8962_IM_ALC_THRESH_EINT 0x0800 /* IM_ALC_THRESH_EINT */ 3512*4882a593Smuzhiyun #define WM8962_IM_ALC_THRESH_EINT_MASK 0x0800 /* IM_ALC_THRESH_EINT */ 3513*4882a593Smuzhiyun #define WM8962_IM_ALC_THRESH_EINT_SHIFT 11 /* IM_ALC_THRESH_EINT */ 3514*4882a593Smuzhiyun #define WM8962_IM_ALC_THRESH_EINT_WIDTH 1 /* IM_ALC_THRESH_EINT */ 3515*4882a593Smuzhiyun #define WM8962_IM_ALC_SAT_EINT 0x0400 /* IM_ALC_SAT_EINT */ 3516*4882a593Smuzhiyun #define WM8962_IM_ALC_SAT_EINT_MASK 0x0400 /* IM_ALC_SAT_EINT */ 3517*4882a593Smuzhiyun #define WM8962_IM_ALC_SAT_EINT_SHIFT 10 /* IM_ALC_SAT_EINT */ 3518*4882a593Smuzhiyun #define WM8962_IM_ALC_SAT_EINT_WIDTH 1 /* IM_ALC_SAT_EINT */ 3519*4882a593Smuzhiyun #define WM8962_IM_ALC_PKOVR_EINT 0x0200 /* IM_ALC_PKOVR_EINT */ 3520*4882a593Smuzhiyun #define WM8962_IM_ALC_PKOVR_EINT_MASK 0x0200 /* IM_ALC_PKOVR_EINT */ 3521*4882a593Smuzhiyun #define WM8962_IM_ALC_PKOVR_EINT_SHIFT 9 /* IM_ALC_PKOVR_EINT */ 3522*4882a593Smuzhiyun #define WM8962_IM_ALC_PKOVR_EINT_WIDTH 1 /* IM_ALC_PKOVR_EINT */ 3523*4882a593Smuzhiyun #define WM8962_IM_ALC_NGATE_EINT 0x0100 /* IM_ALC_NGATE_EINT */ 3524*4882a593Smuzhiyun #define WM8962_IM_ALC_NGATE_EINT_MASK 0x0100 /* IM_ALC_NGATE_EINT */ 3525*4882a593Smuzhiyun #define WM8962_IM_ALC_NGATE_EINT_SHIFT 8 /* IM_ALC_NGATE_EINT */ 3526*4882a593Smuzhiyun #define WM8962_IM_ALC_NGATE_EINT_WIDTH 1 /* IM_ALC_NGATE_EINT */ 3527*4882a593Smuzhiyun #define WM8962_IM_WSEQ_DONE_EINT 0x0080 /* IM_WSEQ_DONE_EINT */ 3528*4882a593Smuzhiyun #define WM8962_IM_WSEQ_DONE_EINT_MASK 0x0080 /* IM_WSEQ_DONE_EINT */ 3529*4882a593Smuzhiyun #define WM8962_IM_WSEQ_DONE_EINT_SHIFT 7 /* IM_WSEQ_DONE_EINT */ 3530*4882a593Smuzhiyun #define WM8962_IM_WSEQ_DONE_EINT_WIDTH 1 /* IM_WSEQ_DONE_EINT */ 3531*4882a593Smuzhiyun #define WM8962_IM_DRC_ACTDET_EINT 0x0040 /* IM_DRC_ACTDET_EINT */ 3532*4882a593Smuzhiyun #define WM8962_IM_DRC_ACTDET_EINT_MASK 0x0040 /* IM_DRC_ACTDET_EINT */ 3533*4882a593Smuzhiyun #define WM8962_IM_DRC_ACTDET_EINT_SHIFT 6 /* IM_DRC_ACTDET_EINT */ 3534*4882a593Smuzhiyun #define WM8962_IM_DRC_ACTDET_EINT_WIDTH 1 /* IM_DRC_ACTDET_EINT */ 3535*4882a593Smuzhiyun #define WM8962_IM_FLL_LOCK_EINT 0x0020 /* IM_FLL_LOCK_EINT */ 3536*4882a593Smuzhiyun #define WM8962_IM_FLL_LOCK_EINT_MASK 0x0020 /* IM_FLL_LOCK_EINT */ 3537*4882a593Smuzhiyun #define WM8962_IM_FLL_LOCK_EINT_SHIFT 5 /* IM_FLL_LOCK_EINT */ 3538*4882a593Smuzhiyun #define WM8962_IM_FLL_LOCK_EINT_WIDTH 1 /* IM_FLL_LOCK_EINT */ 3539*4882a593Smuzhiyun #define WM8962_IM_PLL3_LOCK_EINT 0x0008 /* IM_PLL3_LOCK_EINT */ 3540*4882a593Smuzhiyun #define WM8962_IM_PLL3_LOCK_EINT_MASK 0x0008 /* IM_PLL3_LOCK_EINT */ 3541*4882a593Smuzhiyun #define WM8962_IM_PLL3_LOCK_EINT_SHIFT 3 /* IM_PLL3_LOCK_EINT */ 3542*4882a593Smuzhiyun #define WM8962_IM_PLL3_LOCK_EINT_WIDTH 1 /* IM_PLL3_LOCK_EINT */ 3543*4882a593Smuzhiyun #define WM8962_IM_PLL2_LOCK_EINT 0x0004 /* IM_PLL2_LOCK_EINT */ 3544*4882a593Smuzhiyun #define WM8962_IM_PLL2_LOCK_EINT_MASK 0x0004 /* IM_PLL2_LOCK_EINT */ 3545*4882a593Smuzhiyun #define WM8962_IM_PLL2_LOCK_EINT_SHIFT 2 /* IM_PLL2_LOCK_EINT */ 3546*4882a593Smuzhiyun #define WM8962_IM_PLL2_LOCK_EINT_WIDTH 1 /* IM_PLL2_LOCK_EINT */ 3547*4882a593Smuzhiyun #define WM8962_IM_TEMP_SHUT_EINT 0x0001 /* IM_TEMP_SHUT_EINT */ 3548*4882a593Smuzhiyun #define WM8962_IM_TEMP_SHUT_EINT_MASK 0x0001 /* IM_TEMP_SHUT_EINT */ 3549*4882a593Smuzhiyun #define WM8962_IM_TEMP_SHUT_EINT_SHIFT 0 /* IM_TEMP_SHUT_EINT */ 3550*4882a593Smuzhiyun #define WM8962_IM_TEMP_SHUT_EINT_WIDTH 1 /* IM_TEMP_SHUT_EINT */ 3551*4882a593Smuzhiyun 3552*4882a593Smuzhiyun /* 3553*4882a593Smuzhiyun * R576 (0x240) - Interrupt Control 3554*4882a593Smuzhiyun */ 3555*4882a593Smuzhiyun #define WM8962_IRQ_POL 0x0001 /* IRQ_POL */ 3556*4882a593Smuzhiyun #define WM8962_IRQ_POL_MASK 0x0001 /* IRQ_POL */ 3557*4882a593Smuzhiyun #define WM8962_IRQ_POL_SHIFT 0 /* IRQ_POL */ 3558*4882a593Smuzhiyun #define WM8962_IRQ_POL_WIDTH 1 /* IRQ_POL */ 3559*4882a593Smuzhiyun 3560*4882a593Smuzhiyun /* 3561*4882a593Smuzhiyun * R584 (0x248) - IRQ Debounce 3562*4882a593Smuzhiyun */ 3563*4882a593Smuzhiyun #define WM8962_FLL_LOCK_DB 0x0020 /* FLL_LOCK_DB */ 3564*4882a593Smuzhiyun #define WM8962_FLL_LOCK_DB_MASK 0x0020 /* FLL_LOCK_DB */ 3565*4882a593Smuzhiyun #define WM8962_FLL_LOCK_DB_SHIFT 5 /* FLL_LOCK_DB */ 3566*4882a593Smuzhiyun #define WM8962_FLL_LOCK_DB_WIDTH 1 /* FLL_LOCK_DB */ 3567*4882a593Smuzhiyun #define WM8962_PLL3_LOCK_DB 0x0008 /* PLL3_LOCK_DB */ 3568*4882a593Smuzhiyun #define WM8962_PLL3_LOCK_DB_MASK 0x0008 /* PLL3_LOCK_DB */ 3569*4882a593Smuzhiyun #define WM8962_PLL3_LOCK_DB_SHIFT 3 /* PLL3_LOCK_DB */ 3570*4882a593Smuzhiyun #define WM8962_PLL3_LOCK_DB_WIDTH 1 /* PLL3_LOCK_DB */ 3571*4882a593Smuzhiyun #define WM8962_PLL2_LOCK_DB 0x0004 /* PLL2_LOCK_DB */ 3572*4882a593Smuzhiyun #define WM8962_PLL2_LOCK_DB_MASK 0x0004 /* PLL2_LOCK_DB */ 3573*4882a593Smuzhiyun #define WM8962_PLL2_LOCK_DB_SHIFT 2 /* PLL2_LOCK_DB */ 3574*4882a593Smuzhiyun #define WM8962_PLL2_LOCK_DB_WIDTH 1 /* PLL2_LOCK_DB */ 3575*4882a593Smuzhiyun #define WM8962_TEMP_SHUT_DB 0x0001 /* TEMP_SHUT_DB */ 3576*4882a593Smuzhiyun #define WM8962_TEMP_SHUT_DB_MASK 0x0001 /* TEMP_SHUT_DB */ 3577*4882a593Smuzhiyun #define WM8962_TEMP_SHUT_DB_SHIFT 0 /* TEMP_SHUT_DB */ 3578*4882a593Smuzhiyun #define WM8962_TEMP_SHUT_DB_WIDTH 1 /* TEMP_SHUT_DB */ 3579*4882a593Smuzhiyun 3580*4882a593Smuzhiyun /* 3581*4882a593Smuzhiyun * R586 (0x24A) - MICINT Source Pol 3582*4882a593Smuzhiyun */ 3583*4882a593Smuzhiyun #define WM8962_MICSCD_IRQ_POL 0x8000 /* MICSCD_IRQ_POL */ 3584*4882a593Smuzhiyun #define WM8962_MICSCD_IRQ_POL_MASK 0x8000 /* MICSCD_IRQ_POL */ 3585*4882a593Smuzhiyun #define WM8962_MICSCD_IRQ_POL_SHIFT 15 /* MICSCD_IRQ_POL */ 3586*4882a593Smuzhiyun #define WM8962_MICSCD_IRQ_POL_WIDTH 1 /* MICSCD_IRQ_POL */ 3587*4882a593Smuzhiyun #define WM8962_MICD_IRQ_POL 0x4000 /* MICD_IRQ_POL */ 3588*4882a593Smuzhiyun #define WM8962_MICD_IRQ_POL_MASK 0x4000 /* MICD_IRQ_POL */ 3589*4882a593Smuzhiyun #define WM8962_MICD_IRQ_POL_SHIFT 14 /* MICD_IRQ_POL */ 3590*4882a593Smuzhiyun #define WM8962_MICD_IRQ_POL_WIDTH 1 /* MICD_IRQ_POL */ 3591*4882a593Smuzhiyun 3592*4882a593Smuzhiyun /* 3593*4882a593Smuzhiyun * R768 (0x300) - DSP2 Power Management 3594*4882a593Smuzhiyun */ 3595*4882a593Smuzhiyun #define WM8962_DSP2_ENA 0x0001 /* DSP2_ENA */ 3596*4882a593Smuzhiyun #define WM8962_DSP2_ENA_MASK 0x0001 /* DSP2_ENA */ 3597*4882a593Smuzhiyun #define WM8962_DSP2_ENA_SHIFT 0 /* DSP2_ENA */ 3598*4882a593Smuzhiyun #define WM8962_DSP2_ENA_WIDTH 1 /* DSP2_ENA */ 3599*4882a593Smuzhiyun 3600*4882a593Smuzhiyun /* 3601*4882a593Smuzhiyun * R1037 (0x40D) - DSP2_ExecControl 3602*4882a593Smuzhiyun */ 3603*4882a593Smuzhiyun #define WM8962_DSP2_STOPC 0x0020 /* DSP2_STOPC */ 3604*4882a593Smuzhiyun #define WM8962_DSP2_STOPC_MASK 0x0020 /* DSP2_STOPC */ 3605*4882a593Smuzhiyun #define WM8962_DSP2_STOPC_SHIFT 5 /* DSP2_STOPC */ 3606*4882a593Smuzhiyun #define WM8962_DSP2_STOPC_WIDTH 1 /* DSP2_STOPC */ 3607*4882a593Smuzhiyun #define WM8962_DSP2_STOPS 0x0010 /* DSP2_STOPS */ 3608*4882a593Smuzhiyun #define WM8962_DSP2_STOPS_MASK 0x0010 /* DSP2_STOPS */ 3609*4882a593Smuzhiyun #define WM8962_DSP2_STOPS_SHIFT 4 /* DSP2_STOPS */ 3610*4882a593Smuzhiyun #define WM8962_DSP2_STOPS_WIDTH 1 /* DSP2_STOPS */ 3611*4882a593Smuzhiyun #define WM8962_DSP2_STOPI 0x0008 /* DSP2_STOPI */ 3612*4882a593Smuzhiyun #define WM8962_DSP2_STOPI_MASK 0x0008 /* DSP2_STOPI */ 3613*4882a593Smuzhiyun #define WM8962_DSP2_STOPI_SHIFT 3 /* DSP2_STOPI */ 3614*4882a593Smuzhiyun #define WM8962_DSP2_STOPI_WIDTH 1 /* DSP2_STOPI */ 3615*4882a593Smuzhiyun #define WM8962_DSP2_STOP 0x0004 /* DSP2_STOP */ 3616*4882a593Smuzhiyun #define WM8962_DSP2_STOP_MASK 0x0004 /* DSP2_STOP */ 3617*4882a593Smuzhiyun #define WM8962_DSP2_STOP_SHIFT 2 /* DSP2_STOP */ 3618*4882a593Smuzhiyun #define WM8962_DSP2_STOP_WIDTH 1 /* DSP2_STOP */ 3619*4882a593Smuzhiyun #define WM8962_DSP2_RUNR 0x0002 /* DSP2_RUNR */ 3620*4882a593Smuzhiyun #define WM8962_DSP2_RUNR_MASK 0x0002 /* DSP2_RUNR */ 3621*4882a593Smuzhiyun #define WM8962_DSP2_RUNR_SHIFT 1 /* DSP2_RUNR */ 3622*4882a593Smuzhiyun #define WM8962_DSP2_RUNR_WIDTH 1 /* DSP2_RUNR */ 3623*4882a593Smuzhiyun #define WM8962_DSP2_RUN 0x0001 /* DSP2_RUN */ 3624*4882a593Smuzhiyun #define WM8962_DSP2_RUN_MASK 0x0001 /* DSP2_RUN */ 3625*4882a593Smuzhiyun #define WM8962_DSP2_RUN_SHIFT 0 /* DSP2_RUN */ 3626*4882a593Smuzhiyun #define WM8962_DSP2_RUN_WIDTH 1 /* DSP2_RUN */ 3627*4882a593Smuzhiyun 3628*4882a593Smuzhiyun /* 3629*4882a593Smuzhiyun * R8192 (0x2000) - DSP2 Instruction RAM 0 3630*4882a593Smuzhiyun */ 3631*4882a593Smuzhiyun #define WM8962_DSP2_INSTR_RAM_1024_10_9_0_MASK 0x03FF /* DSP2_INSTR_RAM_1024_10_9_0 - [9:0] */ 3632*4882a593Smuzhiyun #define WM8962_DSP2_INSTR_RAM_1024_10_9_0_SHIFT 0 /* DSP2_INSTR_RAM_1024_10_9_0 - [9:0] */ 3633*4882a593Smuzhiyun #define WM8962_DSP2_INSTR_RAM_1024_10_9_0_WIDTH 10 /* DSP2_INSTR_RAM_1024_10_9_0 - [9:0] */ 3634*4882a593Smuzhiyun 3635*4882a593Smuzhiyun /* 3636*4882a593Smuzhiyun * R9216 (0x2400) - DSP2 Address RAM 2 3637*4882a593Smuzhiyun */ 3638*4882a593Smuzhiyun #define WM8962_DSP2_ADDR_RAM_1024_38_37_32_MASK 0x003F /* DSP2_ADDR_RAM_1024_38_37_32 - [5:0] */ 3639*4882a593Smuzhiyun #define WM8962_DSP2_ADDR_RAM_1024_38_37_32_SHIFT 0 /* DSP2_ADDR_RAM_1024_38_37_32 - [5:0] */ 3640*4882a593Smuzhiyun #define WM8962_DSP2_ADDR_RAM_1024_38_37_32_WIDTH 6 /* DSP2_ADDR_RAM_1024_38_37_32 - [5:0] */ 3641*4882a593Smuzhiyun 3642*4882a593Smuzhiyun /* 3643*4882a593Smuzhiyun * R9217 (0x2401) - DSP2 Address RAM 1 3644*4882a593Smuzhiyun */ 3645*4882a593Smuzhiyun #define WM8962_DSP2_ADDR_RAM_1024_38_31_16_MASK 0xFFFF /* DSP2_ADDR_RAM_1024_38_31_16 - [15:0] */ 3646*4882a593Smuzhiyun #define WM8962_DSP2_ADDR_RAM_1024_38_31_16_SHIFT 0 /* DSP2_ADDR_RAM_1024_38_31_16 - [15:0] */ 3647*4882a593Smuzhiyun #define WM8962_DSP2_ADDR_RAM_1024_38_31_16_WIDTH 16 /* DSP2_ADDR_RAM_1024_38_31_16 - [15:0] */ 3648*4882a593Smuzhiyun 3649*4882a593Smuzhiyun /* 3650*4882a593Smuzhiyun * R9218 (0x2402) - DSP2 Address RAM 0 3651*4882a593Smuzhiyun */ 3652*4882a593Smuzhiyun #define WM8962_DSP2_ADDR_RAM_1024_38_15_0_MASK 0xFFFF /* DSP2_ADDR_RAM_1024_38_15_0 - [15:0] */ 3653*4882a593Smuzhiyun #define WM8962_DSP2_ADDR_RAM_1024_38_15_0_SHIFT 0 /* DSP2_ADDR_RAM_1024_38_15_0 - [15:0] */ 3654*4882a593Smuzhiyun #define WM8962_DSP2_ADDR_RAM_1024_38_15_0_WIDTH 16 /* DSP2_ADDR_RAM_1024_38_15_0 - [15:0] */ 3655*4882a593Smuzhiyun 3656*4882a593Smuzhiyun /* 3657*4882a593Smuzhiyun * R12288 (0x3000) - DSP2 Data1 RAM 1 3658*4882a593Smuzhiyun */ 3659*4882a593Smuzhiyun #define WM8962_DSP2_DATA1_RAM_384_24_23_16_MASK 0x00FF /* DSP2_DATA1_RAM_384_24_23_16 - [7:0] */ 3660*4882a593Smuzhiyun #define WM8962_DSP2_DATA1_RAM_384_24_23_16_SHIFT 0 /* DSP2_DATA1_RAM_384_24_23_16 - [7:0] */ 3661*4882a593Smuzhiyun #define WM8962_DSP2_DATA1_RAM_384_24_23_16_WIDTH 8 /* DSP2_DATA1_RAM_384_24_23_16 - [7:0] */ 3662*4882a593Smuzhiyun 3663*4882a593Smuzhiyun /* 3664*4882a593Smuzhiyun * R12289 (0x3001) - DSP2 Data1 RAM 0 3665*4882a593Smuzhiyun */ 3666*4882a593Smuzhiyun #define WM8962_DSP2_DATA1_RAM_384_24_15_0_MASK 0xFFFF /* DSP2_DATA1_RAM_384_24_15_0 - [15:0] */ 3667*4882a593Smuzhiyun #define WM8962_DSP2_DATA1_RAM_384_24_15_0_SHIFT 0 /* DSP2_DATA1_RAM_384_24_15_0 - [15:0] */ 3668*4882a593Smuzhiyun #define WM8962_DSP2_DATA1_RAM_384_24_15_0_WIDTH 16 /* DSP2_DATA1_RAM_384_24_15_0 - [15:0] */ 3669*4882a593Smuzhiyun 3670*4882a593Smuzhiyun /* 3671*4882a593Smuzhiyun * R13312 (0x3400) - DSP2 Data2 RAM 1 3672*4882a593Smuzhiyun */ 3673*4882a593Smuzhiyun #define WM8962_DSP2_DATA2_RAM_384_24_23_16_MASK 0x00FF /* DSP2_DATA2_RAM_384_24_23_16 - [7:0] */ 3674*4882a593Smuzhiyun #define WM8962_DSP2_DATA2_RAM_384_24_23_16_SHIFT 0 /* DSP2_DATA2_RAM_384_24_23_16 - [7:0] */ 3675*4882a593Smuzhiyun #define WM8962_DSP2_DATA2_RAM_384_24_23_16_WIDTH 8 /* DSP2_DATA2_RAM_384_24_23_16 - [7:0] */ 3676*4882a593Smuzhiyun 3677*4882a593Smuzhiyun /* 3678*4882a593Smuzhiyun * R13313 (0x3401) - DSP2 Data2 RAM 0 3679*4882a593Smuzhiyun */ 3680*4882a593Smuzhiyun #define WM8962_DSP2_DATA2_RAM_384_24_15_0_MASK 0xFFFF /* DSP2_DATA2_RAM_384_24_15_0 - [15:0] */ 3681*4882a593Smuzhiyun #define WM8962_DSP2_DATA2_RAM_384_24_15_0_SHIFT 0 /* DSP2_DATA2_RAM_384_24_15_0 - [15:0] */ 3682*4882a593Smuzhiyun #define WM8962_DSP2_DATA2_RAM_384_24_15_0_WIDTH 16 /* DSP2_DATA2_RAM_384_24_15_0 - [15:0] */ 3683*4882a593Smuzhiyun 3684*4882a593Smuzhiyun /* 3685*4882a593Smuzhiyun * R14336 (0x3800) - DSP2 Data3 RAM 1 3686*4882a593Smuzhiyun */ 3687*4882a593Smuzhiyun #define WM8962_DSP2_DATA3_RAM_384_24_23_16_MASK 0x00FF /* DSP2_DATA3_RAM_384_24_23_16 - [7:0] */ 3688*4882a593Smuzhiyun #define WM8962_DSP2_DATA3_RAM_384_24_23_16_SHIFT 0 /* DSP2_DATA3_RAM_384_24_23_16 - [7:0] */ 3689*4882a593Smuzhiyun #define WM8962_DSP2_DATA3_RAM_384_24_23_16_WIDTH 8 /* DSP2_DATA3_RAM_384_24_23_16 - [7:0] */ 3690*4882a593Smuzhiyun 3691*4882a593Smuzhiyun /* 3692*4882a593Smuzhiyun * R14337 (0x3801) - DSP2 Data3 RAM 0 3693*4882a593Smuzhiyun */ 3694*4882a593Smuzhiyun #define WM8962_DSP2_DATA3_RAM_384_24_15_0_MASK 0xFFFF /* DSP2_DATA3_RAM_384_24_15_0 - [15:0] */ 3695*4882a593Smuzhiyun #define WM8962_DSP2_DATA3_RAM_384_24_15_0_SHIFT 0 /* DSP2_DATA3_RAM_384_24_15_0 - [15:0] */ 3696*4882a593Smuzhiyun #define WM8962_DSP2_DATA3_RAM_384_24_15_0_WIDTH 16 /* DSP2_DATA3_RAM_384_24_15_0 - [15:0] */ 3697*4882a593Smuzhiyun 3698*4882a593Smuzhiyun /* 3699*4882a593Smuzhiyun * R15360 (0x3C00) - DSP2 Coeff RAM 0 3700*4882a593Smuzhiyun */ 3701*4882a593Smuzhiyun #define WM8962_DSP2_CMAP_RAM_384_11_10_0_MASK 0x07FF /* DSP2_CMAP_RAM_384_11_10_0 - [10:0] */ 3702*4882a593Smuzhiyun #define WM8962_DSP2_CMAP_RAM_384_11_10_0_SHIFT 0 /* DSP2_CMAP_RAM_384_11_10_0 - [10:0] */ 3703*4882a593Smuzhiyun #define WM8962_DSP2_CMAP_RAM_384_11_10_0_WIDTH 11 /* DSP2_CMAP_RAM_384_11_10_0 - [10:0] */ 3704*4882a593Smuzhiyun 3705*4882a593Smuzhiyun /* 3706*4882a593Smuzhiyun * R16384 (0x4000) - RETUNEADC_SHARED_COEFF_1 3707*4882a593Smuzhiyun */ 3708*4882a593Smuzhiyun #define WM8962_ADC_RETUNE_SCV 0x0080 /* ADC_RETUNE_SCV */ 3709*4882a593Smuzhiyun #define WM8962_ADC_RETUNE_SCV_MASK 0x0080 /* ADC_RETUNE_SCV */ 3710*4882a593Smuzhiyun #define WM8962_ADC_RETUNE_SCV_SHIFT 7 /* ADC_RETUNE_SCV */ 3711*4882a593Smuzhiyun #define WM8962_ADC_RETUNE_SCV_WIDTH 1 /* ADC_RETUNE_SCV */ 3712*4882a593Smuzhiyun #define WM8962_RETUNEADC_SHARED_COEFF_22_16_MASK 0x007F /* RETUNEADC_SHARED_COEFF_22_16 - [6:0] */ 3713*4882a593Smuzhiyun #define WM8962_RETUNEADC_SHARED_COEFF_22_16_SHIFT 0 /* RETUNEADC_SHARED_COEFF_22_16 - [6:0] */ 3714*4882a593Smuzhiyun #define WM8962_RETUNEADC_SHARED_COEFF_22_16_WIDTH 7 /* RETUNEADC_SHARED_COEFF_22_16 - [6:0] */ 3715*4882a593Smuzhiyun 3716*4882a593Smuzhiyun /* 3717*4882a593Smuzhiyun * R16385 (0x4001) - RETUNEADC_SHARED_COEFF_0 3718*4882a593Smuzhiyun */ 3719*4882a593Smuzhiyun #define WM8962_RETUNEADC_SHARED_COEFF_15_00_MASK 0xFFFF /* RETUNEADC_SHARED_COEFF_15_00 - [15:0] */ 3720*4882a593Smuzhiyun #define WM8962_RETUNEADC_SHARED_COEFF_15_00_SHIFT 0 /* RETUNEADC_SHARED_COEFF_15_00 - [15:0] */ 3721*4882a593Smuzhiyun #define WM8962_RETUNEADC_SHARED_COEFF_15_00_WIDTH 16 /* RETUNEADC_SHARED_COEFF_15_00 - [15:0] */ 3722*4882a593Smuzhiyun 3723*4882a593Smuzhiyun /* 3724*4882a593Smuzhiyun * R16386 (0x4002) - RETUNEDAC_SHARED_COEFF_1 3725*4882a593Smuzhiyun */ 3726*4882a593Smuzhiyun #define WM8962_DAC_RETUNE_SCV 0x0080 /* DAC_RETUNE_SCV */ 3727*4882a593Smuzhiyun #define WM8962_DAC_RETUNE_SCV_MASK 0x0080 /* DAC_RETUNE_SCV */ 3728*4882a593Smuzhiyun #define WM8962_DAC_RETUNE_SCV_SHIFT 7 /* DAC_RETUNE_SCV */ 3729*4882a593Smuzhiyun #define WM8962_DAC_RETUNE_SCV_WIDTH 1 /* DAC_RETUNE_SCV */ 3730*4882a593Smuzhiyun #define WM8962_RETUNEDAC_SHARED_COEFF_23_16_MASK 0x007F /* RETUNEDAC_SHARED_COEFF_23_16 - [6:0] */ 3731*4882a593Smuzhiyun #define WM8962_RETUNEDAC_SHARED_COEFF_23_16_SHIFT 0 /* RETUNEDAC_SHARED_COEFF_23_16 - [6:0] */ 3732*4882a593Smuzhiyun #define WM8962_RETUNEDAC_SHARED_COEFF_23_16_WIDTH 7 /* RETUNEDAC_SHARED_COEFF_23_16 - [6:0] */ 3733*4882a593Smuzhiyun 3734*4882a593Smuzhiyun /* 3735*4882a593Smuzhiyun * R16387 (0x4003) - RETUNEDAC_SHARED_COEFF_0 3736*4882a593Smuzhiyun */ 3737*4882a593Smuzhiyun #define WM8962_RETUNEDAC_SHARED_COEFF_15_00_MASK 0xFFFF /* RETUNEDAC_SHARED_COEFF_15_00 - [15:0] */ 3738*4882a593Smuzhiyun #define WM8962_RETUNEDAC_SHARED_COEFF_15_00_SHIFT 0 /* RETUNEDAC_SHARED_COEFF_15_00 - [15:0] */ 3739*4882a593Smuzhiyun #define WM8962_RETUNEDAC_SHARED_COEFF_15_00_WIDTH 16 /* RETUNEDAC_SHARED_COEFF_15_00 - [15:0] */ 3740*4882a593Smuzhiyun 3741*4882a593Smuzhiyun /* 3742*4882a593Smuzhiyun * R16388 (0x4004) - SOUNDSTAGE_ENABLES_1 3743*4882a593Smuzhiyun */ 3744*4882a593Smuzhiyun #define WM8962_SOUNDSTAGE_ENABLES_23_16_MASK 0x00FF /* SOUNDSTAGE_ENABLES_23_16 - [7:0] */ 3745*4882a593Smuzhiyun #define WM8962_SOUNDSTAGE_ENABLES_23_16_SHIFT 0 /* SOUNDSTAGE_ENABLES_23_16 - [7:0] */ 3746*4882a593Smuzhiyun #define WM8962_SOUNDSTAGE_ENABLES_23_16_WIDTH 8 /* SOUNDSTAGE_ENABLES_23_16 - [7:0] */ 3747*4882a593Smuzhiyun 3748*4882a593Smuzhiyun /* 3749*4882a593Smuzhiyun * R16389 (0x4005) - SOUNDSTAGE_ENABLES_0 3750*4882a593Smuzhiyun */ 3751*4882a593Smuzhiyun #define WM8962_SOUNDSTAGE_ENABLES_15_06_MASK 0xFFC0 /* SOUNDSTAGE_ENABLES_15_06 - [15:6] */ 3752*4882a593Smuzhiyun #define WM8962_SOUNDSTAGE_ENABLES_15_06_SHIFT 6 /* SOUNDSTAGE_ENABLES_15_06 - [15:6] */ 3753*4882a593Smuzhiyun #define WM8962_SOUNDSTAGE_ENABLES_15_06_WIDTH 10 /* SOUNDSTAGE_ENABLES_15_06 - [15:6] */ 3754*4882a593Smuzhiyun #define WM8962_RTN_ADC_ENA 0x0020 /* RTN_ADC_ENA */ 3755*4882a593Smuzhiyun #define WM8962_RTN_ADC_ENA_MASK 0x0020 /* RTN_ADC_ENA */ 3756*4882a593Smuzhiyun #define WM8962_RTN_ADC_ENA_SHIFT 5 /* RTN_ADC_ENA */ 3757*4882a593Smuzhiyun #define WM8962_RTN_ADC_ENA_WIDTH 1 /* RTN_ADC_ENA */ 3758*4882a593Smuzhiyun #define WM8962_RTN_DAC_ENA 0x0010 /* RTN_DAC_ENA */ 3759*4882a593Smuzhiyun #define WM8962_RTN_DAC_ENA_MASK 0x0010 /* RTN_DAC_ENA */ 3760*4882a593Smuzhiyun #define WM8962_RTN_DAC_ENA_SHIFT 4 /* RTN_DAC_ENA */ 3761*4882a593Smuzhiyun #define WM8962_RTN_DAC_ENA_WIDTH 1 /* RTN_DAC_ENA */ 3762*4882a593Smuzhiyun #define WM8962_HDBASS_ENA 0x0008 /* HDBASS_ENA */ 3763*4882a593Smuzhiyun #define WM8962_HDBASS_ENA_MASK 0x0008 /* HDBASS_ENA */ 3764*4882a593Smuzhiyun #define WM8962_HDBASS_ENA_SHIFT 3 /* HDBASS_ENA */ 3765*4882a593Smuzhiyun #define WM8962_HDBASS_ENA_WIDTH 1 /* HDBASS_ENA */ 3766*4882a593Smuzhiyun #define WM8962_HPF2_ENA 0x0004 /* HPF2_ENA */ 3767*4882a593Smuzhiyun #define WM8962_HPF2_ENA_MASK 0x0004 /* HPF2_ENA */ 3768*4882a593Smuzhiyun #define WM8962_HPF2_ENA_SHIFT 2 /* HPF2_ENA */ 3769*4882a593Smuzhiyun #define WM8962_HPF2_ENA_WIDTH 1 /* HPF2_ENA */ 3770*4882a593Smuzhiyun #define WM8962_HPF1_ENA 0x0002 /* HPF1_ENA */ 3771*4882a593Smuzhiyun #define WM8962_HPF1_ENA_MASK 0x0002 /* HPF1_ENA */ 3772*4882a593Smuzhiyun #define WM8962_HPF1_ENA_SHIFT 1 /* HPF1_ENA */ 3773*4882a593Smuzhiyun #define WM8962_HPF1_ENA_WIDTH 1 /* HPF1_ENA */ 3774*4882a593Smuzhiyun #define WM8962_VSS_ENA 0x0001 /* VSS_ENA */ 3775*4882a593Smuzhiyun #define WM8962_VSS_ENA_MASK 0x0001 /* VSS_ENA */ 3776*4882a593Smuzhiyun #define WM8962_VSS_ENA_SHIFT 0 /* VSS_ENA */ 3777*4882a593Smuzhiyun #define WM8962_VSS_ENA_WIDTH 1 /* VSS_ENA */ 3778*4882a593Smuzhiyun 3779*4882a593Smuzhiyun int wm8962_mic_detect(struct snd_soc_component *component, struct snd_soc_jack *jack); 3780*4882a593Smuzhiyun 3781*4882a593Smuzhiyun #endif 3782