1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * wm8961.h -- WM8961 Soc Audio driver 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef _WM8961_H 7*4882a593Smuzhiyun #define _WM8961_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include <sound/soc.h> 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define WM8961_BCLK 1 12*4882a593Smuzhiyun #define WM8961_LRCLK 2 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define WM8961_BCLK_DIV_1 0 15*4882a593Smuzhiyun #define WM8961_BCLK_DIV_1_5 1 16*4882a593Smuzhiyun #define WM8961_BCLK_DIV_2 2 17*4882a593Smuzhiyun #define WM8961_BCLK_DIV_3 3 18*4882a593Smuzhiyun #define WM8961_BCLK_DIV_4 4 19*4882a593Smuzhiyun #define WM8961_BCLK_DIV_5_5 5 20*4882a593Smuzhiyun #define WM8961_BCLK_DIV_6 6 21*4882a593Smuzhiyun #define WM8961_BCLK_DIV_8 7 22*4882a593Smuzhiyun #define WM8961_BCLK_DIV_11 8 23*4882a593Smuzhiyun #define WM8961_BCLK_DIV_12 9 24*4882a593Smuzhiyun #define WM8961_BCLK_DIV_16 10 25*4882a593Smuzhiyun #define WM8961_BCLK_DIV_24 11 26*4882a593Smuzhiyun #define WM8961_BCLK_DIV_32 13 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* 30*4882a593Smuzhiyun * Register values. 31*4882a593Smuzhiyun */ 32*4882a593Smuzhiyun #define WM8961_LEFT_INPUT_VOLUME 0x00 33*4882a593Smuzhiyun #define WM8961_RIGHT_INPUT_VOLUME 0x01 34*4882a593Smuzhiyun #define WM8961_LOUT1_VOLUME 0x02 35*4882a593Smuzhiyun #define WM8961_ROUT1_VOLUME 0x03 36*4882a593Smuzhiyun #define WM8961_CLOCKING1 0x04 37*4882a593Smuzhiyun #define WM8961_ADC_DAC_CONTROL_1 0x05 38*4882a593Smuzhiyun #define WM8961_ADC_DAC_CONTROL_2 0x06 39*4882a593Smuzhiyun #define WM8961_AUDIO_INTERFACE_0 0x07 40*4882a593Smuzhiyun #define WM8961_CLOCKING2 0x08 41*4882a593Smuzhiyun #define WM8961_AUDIO_INTERFACE_1 0x09 42*4882a593Smuzhiyun #define WM8961_LEFT_DAC_VOLUME 0x0A 43*4882a593Smuzhiyun #define WM8961_RIGHT_DAC_VOLUME 0x0B 44*4882a593Smuzhiyun #define WM8961_AUDIO_INTERFACE_2 0x0E 45*4882a593Smuzhiyun #define WM8961_SOFTWARE_RESET 0x0F 46*4882a593Smuzhiyun #define WM8961_ALC1 0x11 47*4882a593Smuzhiyun #define WM8961_ALC2 0x12 48*4882a593Smuzhiyun #define WM8961_ALC3 0x13 49*4882a593Smuzhiyun #define WM8961_NOISE_GATE 0x14 50*4882a593Smuzhiyun #define WM8961_LEFT_ADC_VOLUME 0x15 51*4882a593Smuzhiyun #define WM8961_RIGHT_ADC_VOLUME 0x16 52*4882a593Smuzhiyun #define WM8961_ADDITIONAL_CONTROL_1 0x17 53*4882a593Smuzhiyun #define WM8961_ADDITIONAL_CONTROL_2 0x18 54*4882a593Smuzhiyun #define WM8961_PWR_MGMT_1 0x19 55*4882a593Smuzhiyun #define WM8961_PWR_MGMT_2 0x1A 56*4882a593Smuzhiyun #define WM8961_ADDITIONAL_CONTROL_3 0x1B 57*4882a593Smuzhiyun #define WM8961_ANTI_POP 0x1C 58*4882a593Smuzhiyun #define WM8961_CLOCKING_3 0x1E 59*4882a593Smuzhiyun #define WM8961_ADCL_SIGNAL_PATH 0x20 60*4882a593Smuzhiyun #define WM8961_ADCR_SIGNAL_PATH 0x21 61*4882a593Smuzhiyun #define WM8961_LOUT2_VOLUME 0x28 62*4882a593Smuzhiyun #define WM8961_ROUT2_VOLUME 0x29 63*4882a593Smuzhiyun #define WM8961_PWR_MGMT_3 0x2F 64*4882a593Smuzhiyun #define WM8961_ADDITIONAL_CONTROL_4 0x30 65*4882a593Smuzhiyun #define WM8961_CLASS_D_CONTROL_1 0x31 66*4882a593Smuzhiyun #define WM8961_CLASS_D_CONTROL_2 0x33 67*4882a593Smuzhiyun #define WM8961_CLOCKING_4 0x38 68*4882a593Smuzhiyun #define WM8961_DSP_SIDETONE_0 0x39 69*4882a593Smuzhiyun #define WM8961_DSP_SIDETONE_1 0x3A 70*4882a593Smuzhiyun #define WM8961_DC_SERVO_0 0x3C 71*4882a593Smuzhiyun #define WM8961_DC_SERVO_1 0x3D 72*4882a593Smuzhiyun #define WM8961_DC_SERVO_3 0x3F 73*4882a593Smuzhiyun #define WM8961_DC_SERVO_5 0x41 74*4882a593Smuzhiyun #define WM8961_ANALOGUE_PGA_BIAS 0x44 75*4882a593Smuzhiyun #define WM8961_ANALOGUE_HP_0 0x45 76*4882a593Smuzhiyun #define WM8961_ANALOGUE_HP_2 0x47 77*4882a593Smuzhiyun #define WM8961_CHARGE_PUMP_1 0x48 78*4882a593Smuzhiyun #define WM8961_CHARGE_PUMP_B 0x52 79*4882a593Smuzhiyun #define WM8961_WRITE_SEQUENCER_1 0x57 80*4882a593Smuzhiyun #define WM8961_WRITE_SEQUENCER_2 0x58 81*4882a593Smuzhiyun #define WM8961_WRITE_SEQUENCER_3 0x59 82*4882a593Smuzhiyun #define WM8961_WRITE_SEQUENCER_4 0x5A 83*4882a593Smuzhiyun #define WM8961_WRITE_SEQUENCER_5 0x5B 84*4882a593Smuzhiyun #define WM8961_WRITE_SEQUENCER_6 0x5C 85*4882a593Smuzhiyun #define WM8961_WRITE_SEQUENCER_7 0x5D 86*4882a593Smuzhiyun #define WM8961_GENERAL_TEST_1 0xFC 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun /* 90*4882a593Smuzhiyun * Field Definitions. 91*4882a593Smuzhiyun */ 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun /* 94*4882a593Smuzhiyun * R0 (0x00) - Left Input volume 95*4882a593Smuzhiyun */ 96*4882a593Smuzhiyun #define WM8961_IPVU 0x0100 /* IPVU */ 97*4882a593Smuzhiyun #define WM8961_IPVU_MASK 0x0100 /* IPVU */ 98*4882a593Smuzhiyun #define WM8961_IPVU_SHIFT 8 /* IPVU */ 99*4882a593Smuzhiyun #define WM8961_IPVU_WIDTH 1 /* IPVU */ 100*4882a593Smuzhiyun #define WM8961_LINMUTE 0x0080 /* LINMUTE */ 101*4882a593Smuzhiyun #define WM8961_LINMUTE_MASK 0x0080 /* LINMUTE */ 102*4882a593Smuzhiyun #define WM8961_LINMUTE_SHIFT 7 /* LINMUTE */ 103*4882a593Smuzhiyun #define WM8961_LINMUTE_WIDTH 1 /* LINMUTE */ 104*4882a593Smuzhiyun #define WM8961_LIZC 0x0040 /* LIZC */ 105*4882a593Smuzhiyun #define WM8961_LIZC_MASK 0x0040 /* LIZC */ 106*4882a593Smuzhiyun #define WM8961_LIZC_SHIFT 6 /* LIZC */ 107*4882a593Smuzhiyun #define WM8961_LIZC_WIDTH 1 /* LIZC */ 108*4882a593Smuzhiyun #define WM8961_LINVOL_MASK 0x003F /* LINVOL - [5:0] */ 109*4882a593Smuzhiyun #define WM8961_LINVOL_SHIFT 0 /* LINVOL - [5:0] */ 110*4882a593Smuzhiyun #define WM8961_LINVOL_WIDTH 6 /* LINVOL - [5:0] */ 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun /* 113*4882a593Smuzhiyun * R1 (0x01) - Right Input volume 114*4882a593Smuzhiyun */ 115*4882a593Smuzhiyun #define WM8961_DEVICE_ID_MASK 0xF000 /* DEVICE_ID - [15:12] */ 116*4882a593Smuzhiyun #define WM8961_DEVICE_ID_SHIFT 12 /* DEVICE_ID - [15:12] */ 117*4882a593Smuzhiyun #define WM8961_DEVICE_ID_WIDTH 4 /* DEVICE_ID - [15:12] */ 118*4882a593Smuzhiyun #define WM8961_CHIP_REV_MASK 0x0E00 /* CHIP_REV - [11:9] */ 119*4882a593Smuzhiyun #define WM8961_CHIP_REV_SHIFT 9 /* CHIP_REV - [11:9] */ 120*4882a593Smuzhiyun #define WM8961_CHIP_REV_WIDTH 3 /* CHIP_REV - [11:9] */ 121*4882a593Smuzhiyun #define WM8961_IPVU 0x0100 /* IPVU */ 122*4882a593Smuzhiyun #define WM8961_IPVU_MASK 0x0100 /* IPVU */ 123*4882a593Smuzhiyun #define WM8961_IPVU_SHIFT 8 /* IPVU */ 124*4882a593Smuzhiyun #define WM8961_IPVU_WIDTH 1 /* IPVU */ 125*4882a593Smuzhiyun #define WM8961_RINMUTE 0x0080 /* RINMUTE */ 126*4882a593Smuzhiyun #define WM8961_RINMUTE_MASK 0x0080 /* RINMUTE */ 127*4882a593Smuzhiyun #define WM8961_RINMUTE_SHIFT 7 /* RINMUTE */ 128*4882a593Smuzhiyun #define WM8961_RINMUTE_WIDTH 1 /* RINMUTE */ 129*4882a593Smuzhiyun #define WM8961_RIZC 0x0040 /* RIZC */ 130*4882a593Smuzhiyun #define WM8961_RIZC_MASK 0x0040 /* RIZC */ 131*4882a593Smuzhiyun #define WM8961_RIZC_SHIFT 6 /* RIZC */ 132*4882a593Smuzhiyun #define WM8961_RIZC_WIDTH 1 /* RIZC */ 133*4882a593Smuzhiyun #define WM8961_RINVOL_MASK 0x003F /* RINVOL - [5:0] */ 134*4882a593Smuzhiyun #define WM8961_RINVOL_SHIFT 0 /* RINVOL - [5:0] */ 135*4882a593Smuzhiyun #define WM8961_RINVOL_WIDTH 6 /* RINVOL - [5:0] */ 136*4882a593Smuzhiyun 137*4882a593Smuzhiyun /* 138*4882a593Smuzhiyun * R2 (0x02) - LOUT1 volume 139*4882a593Smuzhiyun */ 140*4882a593Smuzhiyun #define WM8961_OUT1VU 0x0100 /* OUT1VU */ 141*4882a593Smuzhiyun #define WM8961_OUT1VU_MASK 0x0100 /* OUT1VU */ 142*4882a593Smuzhiyun #define WM8961_OUT1VU_SHIFT 8 /* OUT1VU */ 143*4882a593Smuzhiyun #define WM8961_OUT1VU_WIDTH 1 /* OUT1VU */ 144*4882a593Smuzhiyun #define WM8961_LO1ZC 0x0080 /* LO1ZC */ 145*4882a593Smuzhiyun #define WM8961_LO1ZC_MASK 0x0080 /* LO1ZC */ 146*4882a593Smuzhiyun #define WM8961_LO1ZC_SHIFT 7 /* LO1ZC */ 147*4882a593Smuzhiyun #define WM8961_LO1ZC_WIDTH 1 /* LO1ZC */ 148*4882a593Smuzhiyun #define WM8961_LOUT1VOL_MASK 0x007F /* LOUT1VOL - [6:0] */ 149*4882a593Smuzhiyun #define WM8961_LOUT1VOL_SHIFT 0 /* LOUT1VOL - [6:0] */ 150*4882a593Smuzhiyun #define WM8961_LOUT1VOL_WIDTH 7 /* LOUT1VOL - [6:0] */ 151*4882a593Smuzhiyun 152*4882a593Smuzhiyun /* 153*4882a593Smuzhiyun * R3 (0x03) - ROUT1 volume 154*4882a593Smuzhiyun */ 155*4882a593Smuzhiyun #define WM8961_OUT1VU 0x0100 /* OUT1VU */ 156*4882a593Smuzhiyun #define WM8961_OUT1VU_MASK 0x0100 /* OUT1VU */ 157*4882a593Smuzhiyun #define WM8961_OUT1VU_SHIFT 8 /* OUT1VU */ 158*4882a593Smuzhiyun #define WM8961_OUT1VU_WIDTH 1 /* OUT1VU */ 159*4882a593Smuzhiyun #define WM8961_RO1ZC 0x0080 /* RO1ZC */ 160*4882a593Smuzhiyun #define WM8961_RO1ZC_MASK 0x0080 /* RO1ZC */ 161*4882a593Smuzhiyun #define WM8961_RO1ZC_SHIFT 7 /* RO1ZC */ 162*4882a593Smuzhiyun #define WM8961_RO1ZC_WIDTH 1 /* RO1ZC */ 163*4882a593Smuzhiyun #define WM8961_ROUT1VOL_MASK 0x007F /* ROUT1VOL - [6:0] */ 164*4882a593Smuzhiyun #define WM8961_ROUT1VOL_SHIFT 0 /* ROUT1VOL - [6:0] */ 165*4882a593Smuzhiyun #define WM8961_ROUT1VOL_WIDTH 7 /* ROUT1VOL - [6:0] */ 166*4882a593Smuzhiyun 167*4882a593Smuzhiyun /* 168*4882a593Smuzhiyun * R4 (0x04) - Clocking1 169*4882a593Smuzhiyun */ 170*4882a593Smuzhiyun #define WM8961_ADCDIV_MASK 0x01C0 /* ADCDIV - [8:6] */ 171*4882a593Smuzhiyun #define WM8961_ADCDIV_SHIFT 6 /* ADCDIV - [8:6] */ 172*4882a593Smuzhiyun #define WM8961_ADCDIV_WIDTH 3 /* ADCDIV - [8:6] */ 173*4882a593Smuzhiyun #define WM8961_DACDIV_MASK 0x0038 /* DACDIV - [5:3] */ 174*4882a593Smuzhiyun #define WM8961_DACDIV_SHIFT 3 /* DACDIV - [5:3] */ 175*4882a593Smuzhiyun #define WM8961_DACDIV_WIDTH 3 /* DACDIV - [5:3] */ 176*4882a593Smuzhiyun #define WM8961_MCLKDIV 0x0004 /* MCLKDIV */ 177*4882a593Smuzhiyun #define WM8961_MCLKDIV_MASK 0x0004 /* MCLKDIV */ 178*4882a593Smuzhiyun #define WM8961_MCLKDIV_SHIFT 2 /* MCLKDIV */ 179*4882a593Smuzhiyun #define WM8961_MCLKDIV_WIDTH 1 /* MCLKDIV */ 180*4882a593Smuzhiyun 181*4882a593Smuzhiyun /* 182*4882a593Smuzhiyun * R5 (0x05) - ADC & DAC Control 1 183*4882a593Smuzhiyun */ 184*4882a593Smuzhiyun #define WM8961_ADCPOL_MASK 0x0060 /* ADCPOL - [6:5] */ 185*4882a593Smuzhiyun #define WM8961_ADCPOL_SHIFT 5 /* ADCPOL - [6:5] */ 186*4882a593Smuzhiyun #define WM8961_ADCPOL_WIDTH 2 /* ADCPOL - [6:5] */ 187*4882a593Smuzhiyun #define WM8961_DACMU 0x0008 /* DACMU */ 188*4882a593Smuzhiyun #define WM8961_DACMU_MASK 0x0008 /* DACMU */ 189*4882a593Smuzhiyun #define WM8961_DACMU_SHIFT 3 /* DACMU */ 190*4882a593Smuzhiyun #define WM8961_DACMU_WIDTH 1 /* DACMU */ 191*4882a593Smuzhiyun #define WM8961_DEEMPH_MASK 0x0006 /* DEEMPH - [2:1] */ 192*4882a593Smuzhiyun #define WM8961_DEEMPH_SHIFT 1 /* DEEMPH - [2:1] */ 193*4882a593Smuzhiyun #define WM8961_DEEMPH_WIDTH 2 /* DEEMPH - [2:1] */ 194*4882a593Smuzhiyun #define WM8961_ADCHPD 0x0001 /* ADCHPD */ 195*4882a593Smuzhiyun #define WM8961_ADCHPD_MASK 0x0001 /* ADCHPD */ 196*4882a593Smuzhiyun #define WM8961_ADCHPD_SHIFT 0 /* ADCHPD */ 197*4882a593Smuzhiyun #define WM8961_ADCHPD_WIDTH 1 /* ADCHPD */ 198*4882a593Smuzhiyun 199*4882a593Smuzhiyun /* 200*4882a593Smuzhiyun * R6 (0x06) - ADC & DAC Control 2 201*4882a593Smuzhiyun */ 202*4882a593Smuzhiyun #define WM8961_ADC_HPF_CUT_MASK 0x0180 /* ADC_HPF_CUT - [8:7] */ 203*4882a593Smuzhiyun #define WM8961_ADC_HPF_CUT_SHIFT 7 /* ADC_HPF_CUT - [8:7] */ 204*4882a593Smuzhiyun #define WM8961_ADC_HPF_CUT_WIDTH 2 /* ADC_HPF_CUT - [8:7] */ 205*4882a593Smuzhiyun #define WM8961_DACPOL_MASK 0x0060 /* DACPOL - [6:5] */ 206*4882a593Smuzhiyun #define WM8961_DACPOL_SHIFT 5 /* DACPOL - [6:5] */ 207*4882a593Smuzhiyun #define WM8961_DACPOL_WIDTH 2 /* DACPOL - [6:5] */ 208*4882a593Smuzhiyun #define WM8961_DACSMM 0x0008 /* DACSMM */ 209*4882a593Smuzhiyun #define WM8961_DACSMM_MASK 0x0008 /* DACSMM */ 210*4882a593Smuzhiyun #define WM8961_DACSMM_SHIFT 3 /* DACSMM */ 211*4882a593Smuzhiyun #define WM8961_DACSMM_WIDTH 1 /* DACSMM */ 212*4882a593Smuzhiyun #define WM8961_DACMR 0x0004 /* DACMR */ 213*4882a593Smuzhiyun #define WM8961_DACMR_MASK 0x0004 /* DACMR */ 214*4882a593Smuzhiyun #define WM8961_DACMR_SHIFT 2 /* DACMR */ 215*4882a593Smuzhiyun #define WM8961_DACMR_WIDTH 1 /* DACMR */ 216*4882a593Smuzhiyun #define WM8961_DACSLOPE 0x0002 /* DACSLOPE */ 217*4882a593Smuzhiyun #define WM8961_DACSLOPE_MASK 0x0002 /* DACSLOPE */ 218*4882a593Smuzhiyun #define WM8961_DACSLOPE_SHIFT 1 /* DACSLOPE */ 219*4882a593Smuzhiyun #define WM8961_DACSLOPE_WIDTH 1 /* DACSLOPE */ 220*4882a593Smuzhiyun #define WM8961_DAC_OSR128 0x0001 /* DAC_OSR128 */ 221*4882a593Smuzhiyun #define WM8961_DAC_OSR128_MASK 0x0001 /* DAC_OSR128 */ 222*4882a593Smuzhiyun #define WM8961_DAC_OSR128_SHIFT 0 /* DAC_OSR128 */ 223*4882a593Smuzhiyun #define WM8961_DAC_OSR128_WIDTH 1 /* DAC_OSR128 */ 224*4882a593Smuzhiyun 225*4882a593Smuzhiyun /* 226*4882a593Smuzhiyun * R7 (0x07) - Audio Interface 0 227*4882a593Smuzhiyun */ 228*4882a593Smuzhiyun #define WM8961_ALRSWAP 0x0100 /* ALRSWAP */ 229*4882a593Smuzhiyun #define WM8961_ALRSWAP_MASK 0x0100 /* ALRSWAP */ 230*4882a593Smuzhiyun #define WM8961_ALRSWAP_SHIFT 8 /* ALRSWAP */ 231*4882a593Smuzhiyun #define WM8961_ALRSWAP_WIDTH 1 /* ALRSWAP */ 232*4882a593Smuzhiyun #define WM8961_BCLKINV 0x0080 /* BCLKINV */ 233*4882a593Smuzhiyun #define WM8961_BCLKINV_MASK 0x0080 /* BCLKINV */ 234*4882a593Smuzhiyun #define WM8961_BCLKINV_SHIFT 7 /* BCLKINV */ 235*4882a593Smuzhiyun #define WM8961_BCLKINV_WIDTH 1 /* BCLKINV */ 236*4882a593Smuzhiyun #define WM8961_MS 0x0040 /* MS */ 237*4882a593Smuzhiyun #define WM8961_MS_MASK 0x0040 /* MS */ 238*4882a593Smuzhiyun #define WM8961_MS_SHIFT 6 /* MS */ 239*4882a593Smuzhiyun #define WM8961_MS_WIDTH 1 /* MS */ 240*4882a593Smuzhiyun #define WM8961_DLRSWAP 0x0020 /* DLRSWAP */ 241*4882a593Smuzhiyun #define WM8961_DLRSWAP_MASK 0x0020 /* DLRSWAP */ 242*4882a593Smuzhiyun #define WM8961_DLRSWAP_SHIFT 5 /* DLRSWAP */ 243*4882a593Smuzhiyun #define WM8961_DLRSWAP_WIDTH 1 /* DLRSWAP */ 244*4882a593Smuzhiyun #define WM8961_LRP 0x0010 /* LRP */ 245*4882a593Smuzhiyun #define WM8961_LRP_MASK 0x0010 /* LRP */ 246*4882a593Smuzhiyun #define WM8961_LRP_SHIFT 4 /* LRP */ 247*4882a593Smuzhiyun #define WM8961_LRP_WIDTH 1 /* LRP */ 248*4882a593Smuzhiyun #define WM8961_WL_MASK 0x000C /* WL - [3:2] */ 249*4882a593Smuzhiyun #define WM8961_WL_SHIFT 2 /* WL - [3:2] */ 250*4882a593Smuzhiyun #define WM8961_WL_WIDTH 2 /* WL - [3:2] */ 251*4882a593Smuzhiyun #define WM8961_FORMAT_MASK 0x0003 /* FORMAT - [1:0] */ 252*4882a593Smuzhiyun #define WM8961_FORMAT_SHIFT 0 /* FORMAT - [1:0] */ 253*4882a593Smuzhiyun #define WM8961_FORMAT_WIDTH 2 /* FORMAT - [1:0] */ 254*4882a593Smuzhiyun 255*4882a593Smuzhiyun /* 256*4882a593Smuzhiyun * R8 (0x08) - Clocking2 257*4882a593Smuzhiyun */ 258*4882a593Smuzhiyun #define WM8961_DCLKDIV_MASK 0x01C0 /* DCLKDIV - [8:6] */ 259*4882a593Smuzhiyun #define WM8961_DCLKDIV_SHIFT 6 /* DCLKDIV - [8:6] */ 260*4882a593Smuzhiyun #define WM8961_DCLKDIV_WIDTH 3 /* DCLKDIV - [8:6] */ 261*4882a593Smuzhiyun #define WM8961_CLK_SYS_ENA 0x0020 /* CLK_SYS_ENA */ 262*4882a593Smuzhiyun #define WM8961_CLK_SYS_ENA_MASK 0x0020 /* CLK_SYS_ENA */ 263*4882a593Smuzhiyun #define WM8961_CLK_SYS_ENA_SHIFT 5 /* CLK_SYS_ENA */ 264*4882a593Smuzhiyun #define WM8961_CLK_SYS_ENA_WIDTH 1 /* CLK_SYS_ENA */ 265*4882a593Smuzhiyun #define WM8961_CLK_DSP_ENA 0x0010 /* CLK_DSP_ENA */ 266*4882a593Smuzhiyun #define WM8961_CLK_DSP_ENA_MASK 0x0010 /* CLK_DSP_ENA */ 267*4882a593Smuzhiyun #define WM8961_CLK_DSP_ENA_SHIFT 4 /* CLK_DSP_ENA */ 268*4882a593Smuzhiyun #define WM8961_CLK_DSP_ENA_WIDTH 1 /* CLK_DSP_ENA */ 269*4882a593Smuzhiyun #define WM8961_BCLKDIV_MASK 0x000F /* BCLKDIV - [3:0] */ 270*4882a593Smuzhiyun #define WM8961_BCLKDIV_SHIFT 0 /* BCLKDIV - [3:0] */ 271*4882a593Smuzhiyun #define WM8961_BCLKDIV_WIDTH 4 /* BCLKDIV - [3:0] */ 272*4882a593Smuzhiyun 273*4882a593Smuzhiyun /* 274*4882a593Smuzhiyun * R9 (0x09) - Audio Interface 1 275*4882a593Smuzhiyun */ 276*4882a593Smuzhiyun #define WM8961_DACCOMP_MASK 0x0018 /* DACCOMP - [4:3] */ 277*4882a593Smuzhiyun #define WM8961_DACCOMP_SHIFT 3 /* DACCOMP - [4:3] */ 278*4882a593Smuzhiyun #define WM8961_DACCOMP_WIDTH 2 /* DACCOMP - [4:3] */ 279*4882a593Smuzhiyun #define WM8961_ADCCOMP_MASK 0x0006 /* ADCCOMP - [2:1] */ 280*4882a593Smuzhiyun #define WM8961_ADCCOMP_SHIFT 1 /* ADCCOMP - [2:1] */ 281*4882a593Smuzhiyun #define WM8961_ADCCOMP_WIDTH 2 /* ADCCOMP - [2:1] */ 282*4882a593Smuzhiyun #define WM8961_LOOPBACK 0x0001 /* LOOPBACK */ 283*4882a593Smuzhiyun #define WM8961_LOOPBACK_MASK 0x0001 /* LOOPBACK */ 284*4882a593Smuzhiyun #define WM8961_LOOPBACK_SHIFT 0 /* LOOPBACK */ 285*4882a593Smuzhiyun #define WM8961_LOOPBACK_WIDTH 1 /* LOOPBACK */ 286*4882a593Smuzhiyun 287*4882a593Smuzhiyun /* 288*4882a593Smuzhiyun * R10 (0x0A) - Left DAC volume 289*4882a593Smuzhiyun */ 290*4882a593Smuzhiyun #define WM8961_DACVU 0x0100 /* DACVU */ 291*4882a593Smuzhiyun #define WM8961_DACVU_MASK 0x0100 /* DACVU */ 292*4882a593Smuzhiyun #define WM8961_DACVU_SHIFT 8 /* DACVU */ 293*4882a593Smuzhiyun #define WM8961_DACVU_WIDTH 1 /* DACVU */ 294*4882a593Smuzhiyun #define WM8961_LDACVOL_MASK 0x00FF /* LDACVOL - [7:0] */ 295*4882a593Smuzhiyun #define WM8961_LDACVOL_SHIFT 0 /* LDACVOL - [7:0] */ 296*4882a593Smuzhiyun #define WM8961_LDACVOL_WIDTH 8 /* LDACVOL - [7:0] */ 297*4882a593Smuzhiyun 298*4882a593Smuzhiyun /* 299*4882a593Smuzhiyun * R11 (0x0B) - Right DAC volume 300*4882a593Smuzhiyun */ 301*4882a593Smuzhiyun #define WM8961_DACVU 0x0100 /* DACVU */ 302*4882a593Smuzhiyun #define WM8961_DACVU_MASK 0x0100 /* DACVU */ 303*4882a593Smuzhiyun #define WM8961_DACVU_SHIFT 8 /* DACVU */ 304*4882a593Smuzhiyun #define WM8961_DACVU_WIDTH 1 /* DACVU */ 305*4882a593Smuzhiyun #define WM8961_RDACVOL_MASK 0x00FF /* RDACVOL - [7:0] */ 306*4882a593Smuzhiyun #define WM8961_RDACVOL_SHIFT 0 /* RDACVOL - [7:0] */ 307*4882a593Smuzhiyun #define WM8961_RDACVOL_WIDTH 8 /* RDACVOL - [7:0] */ 308*4882a593Smuzhiyun 309*4882a593Smuzhiyun /* 310*4882a593Smuzhiyun * R14 (0x0E) - Audio Interface 2 311*4882a593Smuzhiyun */ 312*4882a593Smuzhiyun #define WM8961_LRCLK_RATE_MASK 0x01FF /* LRCLK_RATE - [8:0] */ 313*4882a593Smuzhiyun #define WM8961_LRCLK_RATE_SHIFT 0 /* LRCLK_RATE - [8:0] */ 314*4882a593Smuzhiyun #define WM8961_LRCLK_RATE_WIDTH 9 /* LRCLK_RATE - [8:0] */ 315*4882a593Smuzhiyun 316*4882a593Smuzhiyun /* 317*4882a593Smuzhiyun * R15 (0x0F) - Software Reset 318*4882a593Smuzhiyun */ 319*4882a593Smuzhiyun #define WM8961_SW_RST_DEV_ID1_MASK 0xFFFF /* SW_RST_DEV_ID1 - [15:0] */ 320*4882a593Smuzhiyun #define WM8961_SW_RST_DEV_ID1_SHIFT 0 /* SW_RST_DEV_ID1 - [15:0] */ 321*4882a593Smuzhiyun #define WM8961_SW_RST_DEV_ID1_WIDTH 16 /* SW_RST_DEV_ID1 - [15:0] */ 322*4882a593Smuzhiyun 323*4882a593Smuzhiyun /* 324*4882a593Smuzhiyun * R17 (0x11) - ALC1 325*4882a593Smuzhiyun */ 326*4882a593Smuzhiyun #define WM8961_ALCSEL_MASK 0x0180 /* ALCSEL - [8:7] */ 327*4882a593Smuzhiyun #define WM8961_ALCSEL_SHIFT 7 /* ALCSEL - [8:7] */ 328*4882a593Smuzhiyun #define WM8961_ALCSEL_WIDTH 2 /* ALCSEL - [8:7] */ 329*4882a593Smuzhiyun #define WM8961_MAXGAIN_MASK 0x0070 /* MAXGAIN - [6:4] */ 330*4882a593Smuzhiyun #define WM8961_MAXGAIN_SHIFT 4 /* MAXGAIN - [6:4] */ 331*4882a593Smuzhiyun #define WM8961_MAXGAIN_WIDTH 3 /* MAXGAIN - [6:4] */ 332*4882a593Smuzhiyun #define WM8961_ALCL_MASK 0x000F /* ALCL - [3:0] */ 333*4882a593Smuzhiyun #define WM8961_ALCL_SHIFT 0 /* ALCL - [3:0] */ 334*4882a593Smuzhiyun #define WM8961_ALCL_WIDTH 4 /* ALCL - [3:0] */ 335*4882a593Smuzhiyun 336*4882a593Smuzhiyun /* 337*4882a593Smuzhiyun * R18 (0x12) - ALC2 338*4882a593Smuzhiyun */ 339*4882a593Smuzhiyun #define WM8961_ALCZC 0x0080 /* ALCZC */ 340*4882a593Smuzhiyun #define WM8961_ALCZC_MASK 0x0080 /* ALCZC */ 341*4882a593Smuzhiyun #define WM8961_ALCZC_SHIFT 7 /* ALCZC */ 342*4882a593Smuzhiyun #define WM8961_ALCZC_WIDTH 1 /* ALCZC */ 343*4882a593Smuzhiyun #define WM8961_MINGAIN_MASK 0x0070 /* MINGAIN - [6:4] */ 344*4882a593Smuzhiyun #define WM8961_MINGAIN_SHIFT 4 /* MINGAIN - [6:4] */ 345*4882a593Smuzhiyun #define WM8961_MINGAIN_WIDTH 3 /* MINGAIN - [6:4] */ 346*4882a593Smuzhiyun #define WM8961_HLD_MASK 0x000F /* HLD - [3:0] */ 347*4882a593Smuzhiyun #define WM8961_HLD_SHIFT 0 /* HLD - [3:0] */ 348*4882a593Smuzhiyun #define WM8961_HLD_WIDTH 4 /* HLD - [3:0] */ 349*4882a593Smuzhiyun 350*4882a593Smuzhiyun /* 351*4882a593Smuzhiyun * R19 (0x13) - ALC3 352*4882a593Smuzhiyun */ 353*4882a593Smuzhiyun #define WM8961_ALCMODE 0x0100 /* ALCMODE */ 354*4882a593Smuzhiyun #define WM8961_ALCMODE_MASK 0x0100 /* ALCMODE */ 355*4882a593Smuzhiyun #define WM8961_ALCMODE_SHIFT 8 /* ALCMODE */ 356*4882a593Smuzhiyun #define WM8961_ALCMODE_WIDTH 1 /* ALCMODE */ 357*4882a593Smuzhiyun #define WM8961_DCY_MASK 0x00F0 /* DCY - [7:4] */ 358*4882a593Smuzhiyun #define WM8961_DCY_SHIFT 4 /* DCY - [7:4] */ 359*4882a593Smuzhiyun #define WM8961_DCY_WIDTH 4 /* DCY - [7:4] */ 360*4882a593Smuzhiyun #define WM8961_ATK_MASK 0x000F /* ATK - [3:0] */ 361*4882a593Smuzhiyun #define WM8961_ATK_SHIFT 0 /* ATK - [3:0] */ 362*4882a593Smuzhiyun #define WM8961_ATK_WIDTH 4 /* ATK - [3:0] */ 363*4882a593Smuzhiyun 364*4882a593Smuzhiyun /* 365*4882a593Smuzhiyun * R20 (0x14) - Noise Gate 366*4882a593Smuzhiyun */ 367*4882a593Smuzhiyun #define WM8961_NGTH_MASK 0x00F8 /* NGTH - [7:3] */ 368*4882a593Smuzhiyun #define WM8961_NGTH_SHIFT 3 /* NGTH - [7:3] */ 369*4882a593Smuzhiyun #define WM8961_NGTH_WIDTH 5 /* NGTH - [7:3] */ 370*4882a593Smuzhiyun #define WM8961_NGG 0x0002 /* NGG */ 371*4882a593Smuzhiyun #define WM8961_NGG_MASK 0x0002 /* NGG */ 372*4882a593Smuzhiyun #define WM8961_NGG_SHIFT 1 /* NGG */ 373*4882a593Smuzhiyun #define WM8961_NGG_WIDTH 1 /* NGG */ 374*4882a593Smuzhiyun #define WM8961_NGAT 0x0001 /* NGAT */ 375*4882a593Smuzhiyun #define WM8961_NGAT_MASK 0x0001 /* NGAT */ 376*4882a593Smuzhiyun #define WM8961_NGAT_SHIFT 0 /* NGAT */ 377*4882a593Smuzhiyun #define WM8961_NGAT_WIDTH 1 /* NGAT */ 378*4882a593Smuzhiyun 379*4882a593Smuzhiyun /* 380*4882a593Smuzhiyun * R21 (0x15) - Left ADC volume 381*4882a593Smuzhiyun */ 382*4882a593Smuzhiyun #define WM8961_ADCVU 0x0100 /* ADCVU */ 383*4882a593Smuzhiyun #define WM8961_ADCVU_MASK 0x0100 /* ADCVU */ 384*4882a593Smuzhiyun #define WM8961_ADCVU_SHIFT 8 /* ADCVU */ 385*4882a593Smuzhiyun #define WM8961_ADCVU_WIDTH 1 /* ADCVU */ 386*4882a593Smuzhiyun #define WM8961_LADCVOL_MASK 0x00FF /* LADCVOL - [7:0] */ 387*4882a593Smuzhiyun #define WM8961_LADCVOL_SHIFT 0 /* LADCVOL - [7:0] */ 388*4882a593Smuzhiyun #define WM8961_LADCVOL_WIDTH 8 /* LADCVOL - [7:0] */ 389*4882a593Smuzhiyun 390*4882a593Smuzhiyun /* 391*4882a593Smuzhiyun * R22 (0x16) - Right ADC volume 392*4882a593Smuzhiyun */ 393*4882a593Smuzhiyun #define WM8961_ADCVU 0x0100 /* ADCVU */ 394*4882a593Smuzhiyun #define WM8961_ADCVU_MASK 0x0100 /* ADCVU */ 395*4882a593Smuzhiyun #define WM8961_ADCVU_SHIFT 8 /* ADCVU */ 396*4882a593Smuzhiyun #define WM8961_ADCVU_WIDTH 1 /* ADCVU */ 397*4882a593Smuzhiyun #define WM8961_RADCVOL_MASK 0x00FF /* RADCVOL - [7:0] */ 398*4882a593Smuzhiyun #define WM8961_RADCVOL_SHIFT 0 /* RADCVOL - [7:0] */ 399*4882a593Smuzhiyun #define WM8961_RADCVOL_WIDTH 8 /* RADCVOL - [7:0] */ 400*4882a593Smuzhiyun 401*4882a593Smuzhiyun /* 402*4882a593Smuzhiyun * R23 (0x17) - Additional control(1) 403*4882a593Smuzhiyun */ 404*4882a593Smuzhiyun #define WM8961_TSDEN 0x0100 /* TSDEN */ 405*4882a593Smuzhiyun #define WM8961_TSDEN_MASK 0x0100 /* TSDEN */ 406*4882a593Smuzhiyun #define WM8961_TSDEN_SHIFT 8 /* TSDEN */ 407*4882a593Smuzhiyun #define WM8961_TSDEN_WIDTH 1 /* TSDEN */ 408*4882a593Smuzhiyun #define WM8961_DMONOMIX 0x0010 /* DMONOMIX */ 409*4882a593Smuzhiyun #define WM8961_DMONOMIX_MASK 0x0010 /* DMONOMIX */ 410*4882a593Smuzhiyun #define WM8961_DMONOMIX_SHIFT 4 /* DMONOMIX */ 411*4882a593Smuzhiyun #define WM8961_DMONOMIX_WIDTH 1 /* DMONOMIX */ 412*4882a593Smuzhiyun #define WM8961_TOEN 0x0001 /* TOEN */ 413*4882a593Smuzhiyun #define WM8961_TOEN_MASK 0x0001 /* TOEN */ 414*4882a593Smuzhiyun #define WM8961_TOEN_SHIFT 0 /* TOEN */ 415*4882a593Smuzhiyun #define WM8961_TOEN_WIDTH 1 /* TOEN */ 416*4882a593Smuzhiyun 417*4882a593Smuzhiyun /* 418*4882a593Smuzhiyun * R24 (0x18) - Additional control(2) 419*4882a593Smuzhiyun */ 420*4882a593Smuzhiyun #define WM8961_TRIS 0x0008 /* TRIS */ 421*4882a593Smuzhiyun #define WM8961_TRIS_MASK 0x0008 /* TRIS */ 422*4882a593Smuzhiyun #define WM8961_TRIS_SHIFT 3 /* TRIS */ 423*4882a593Smuzhiyun #define WM8961_TRIS_WIDTH 1 /* TRIS */ 424*4882a593Smuzhiyun 425*4882a593Smuzhiyun /* 426*4882a593Smuzhiyun * R25 (0x19) - Pwr Mgmt (1) 427*4882a593Smuzhiyun */ 428*4882a593Smuzhiyun #define WM8961_VMIDSEL_MASK 0x0180 /* VMIDSEL - [8:7] */ 429*4882a593Smuzhiyun #define WM8961_VMIDSEL_SHIFT 7 /* VMIDSEL - [8:7] */ 430*4882a593Smuzhiyun #define WM8961_VMIDSEL_WIDTH 2 /* VMIDSEL - [8:7] */ 431*4882a593Smuzhiyun #define WM8961_VREF 0x0040 /* VREF */ 432*4882a593Smuzhiyun #define WM8961_VREF_MASK 0x0040 /* VREF */ 433*4882a593Smuzhiyun #define WM8961_VREF_SHIFT 6 /* VREF */ 434*4882a593Smuzhiyun #define WM8961_VREF_WIDTH 1 /* VREF */ 435*4882a593Smuzhiyun #define WM8961_AINL 0x0020 /* AINL */ 436*4882a593Smuzhiyun #define WM8961_AINL_MASK 0x0020 /* AINL */ 437*4882a593Smuzhiyun #define WM8961_AINL_SHIFT 5 /* AINL */ 438*4882a593Smuzhiyun #define WM8961_AINL_WIDTH 1 /* AINL */ 439*4882a593Smuzhiyun #define WM8961_AINR 0x0010 /* AINR */ 440*4882a593Smuzhiyun #define WM8961_AINR_MASK 0x0010 /* AINR */ 441*4882a593Smuzhiyun #define WM8961_AINR_SHIFT 4 /* AINR */ 442*4882a593Smuzhiyun #define WM8961_AINR_WIDTH 1 /* AINR */ 443*4882a593Smuzhiyun #define WM8961_ADCL 0x0008 /* ADCL */ 444*4882a593Smuzhiyun #define WM8961_ADCL_MASK 0x0008 /* ADCL */ 445*4882a593Smuzhiyun #define WM8961_ADCL_SHIFT 3 /* ADCL */ 446*4882a593Smuzhiyun #define WM8961_ADCL_WIDTH 1 /* ADCL */ 447*4882a593Smuzhiyun #define WM8961_ADCR 0x0004 /* ADCR */ 448*4882a593Smuzhiyun #define WM8961_ADCR_MASK 0x0004 /* ADCR */ 449*4882a593Smuzhiyun #define WM8961_ADCR_SHIFT 2 /* ADCR */ 450*4882a593Smuzhiyun #define WM8961_ADCR_WIDTH 1 /* ADCR */ 451*4882a593Smuzhiyun #define WM8961_MICB 0x0002 /* MICB */ 452*4882a593Smuzhiyun #define WM8961_MICB_MASK 0x0002 /* MICB */ 453*4882a593Smuzhiyun #define WM8961_MICB_SHIFT 1 /* MICB */ 454*4882a593Smuzhiyun #define WM8961_MICB_WIDTH 1 /* MICB */ 455*4882a593Smuzhiyun 456*4882a593Smuzhiyun /* 457*4882a593Smuzhiyun * R26 (0x1A) - Pwr Mgmt (2) 458*4882a593Smuzhiyun */ 459*4882a593Smuzhiyun #define WM8961_DACL 0x0100 /* DACL */ 460*4882a593Smuzhiyun #define WM8961_DACL_MASK 0x0100 /* DACL */ 461*4882a593Smuzhiyun #define WM8961_DACL_SHIFT 8 /* DACL */ 462*4882a593Smuzhiyun #define WM8961_DACL_WIDTH 1 /* DACL */ 463*4882a593Smuzhiyun #define WM8961_DACR 0x0080 /* DACR */ 464*4882a593Smuzhiyun #define WM8961_DACR_MASK 0x0080 /* DACR */ 465*4882a593Smuzhiyun #define WM8961_DACR_SHIFT 7 /* DACR */ 466*4882a593Smuzhiyun #define WM8961_DACR_WIDTH 1 /* DACR */ 467*4882a593Smuzhiyun #define WM8961_LOUT1_PGA 0x0040 /* LOUT1_PGA */ 468*4882a593Smuzhiyun #define WM8961_LOUT1_PGA_MASK 0x0040 /* LOUT1_PGA */ 469*4882a593Smuzhiyun #define WM8961_LOUT1_PGA_SHIFT 6 /* LOUT1_PGA */ 470*4882a593Smuzhiyun #define WM8961_LOUT1_PGA_WIDTH 1 /* LOUT1_PGA */ 471*4882a593Smuzhiyun #define WM8961_ROUT1_PGA 0x0020 /* ROUT1_PGA */ 472*4882a593Smuzhiyun #define WM8961_ROUT1_PGA_MASK 0x0020 /* ROUT1_PGA */ 473*4882a593Smuzhiyun #define WM8961_ROUT1_PGA_SHIFT 5 /* ROUT1_PGA */ 474*4882a593Smuzhiyun #define WM8961_ROUT1_PGA_WIDTH 1 /* ROUT1_PGA */ 475*4882a593Smuzhiyun #define WM8961_SPKL_PGA 0x0010 /* SPKL_PGA */ 476*4882a593Smuzhiyun #define WM8961_SPKL_PGA_MASK 0x0010 /* SPKL_PGA */ 477*4882a593Smuzhiyun #define WM8961_SPKL_PGA_SHIFT 4 /* SPKL_PGA */ 478*4882a593Smuzhiyun #define WM8961_SPKL_PGA_WIDTH 1 /* SPKL_PGA */ 479*4882a593Smuzhiyun #define WM8961_SPKR_PGA 0x0008 /* SPKR_PGA */ 480*4882a593Smuzhiyun #define WM8961_SPKR_PGA_MASK 0x0008 /* SPKR_PGA */ 481*4882a593Smuzhiyun #define WM8961_SPKR_PGA_SHIFT 3 /* SPKR_PGA */ 482*4882a593Smuzhiyun #define WM8961_SPKR_PGA_WIDTH 1 /* SPKR_PGA */ 483*4882a593Smuzhiyun 484*4882a593Smuzhiyun /* 485*4882a593Smuzhiyun * R27 (0x1B) - Additional Control (3) 486*4882a593Smuzhiyun */ 487*4882a593Smuzhiyun #define WM8961_SAMPLE_RATE_MASK 0x0007 /* SAMPLE_RATE - [2:0] */ 488*4882a593Smuzhiyun #define WM8961_SAMPLE_RATE_SHIFT 0 /* SAMPLE_RATE - [2:0] */ 489*4882a593Smuzhiyun #define WM8961_SAMPLE_RATE_WIDTH 3 /* SAMPLE_RATE - [2:0] */ 490*4882a593Smuzhiyun 491*4882a593Smuzhiyun /* 492*4882a593Smuzhiyun * R28 (0x1C) - Anti-pop 493*4882a593Smuzhiyun */ 494*4882a593Smuzhiyun #define WM8961_BUFDCOPEN 0x0010 /* BUFDCOPEN */ 495*4882a593Smuzhiyun #define WM8961_BUFDCOPEN_MASK 0x0010 /* BUFDCOPEN */ 496*4882a593Smuzhiyun #define WM8961_BUFDCOPEN_SHIFT 4 /* BUFDCOPEN */ 497*4882a593Smuzhiyun #define WM8961_BUFDCOPEN_WIDTH 1 /* BUFDCOPEN */ 498*4882a593Smuzhiyun #define WM8961_BUFIOEN 0x0008 /* BUFIOEN */ 499*4882a593Smuzhiyun #define WM8961_BUFIOEN_MASK 0x0008 /* BUFIOEN */ 500*4882a593Smuzhiyun #define WM8961_BUFIOEN_SHIFT 3 /* BUFIOEN */ 501*4882a593Smuzhiyun #define WM8961_BUFIOEN_WIDTH 1 /* BUFIOEN */ 502*4882a593Smuzhiyun #define WM8961_SOFT_ST 0x0004 /* SOFT_ST */ 503*4882a593Smuzhiyun #define WM8961_SOFT_ST_MASK 0x0004 /* SOFT_ST */ 504*4882a593Smuzhiyun #define WM8961_SOFT_ST_SHIFT 2 /* SOFT_ST */ 505*4882a593Smuzhiyun #define WM8961_SOFT_ST_WIDTH 1 /* SOFT_ST */ 506*4882a593Smuzhiyun 507*4882a593Smuzhiyun /* 508*4882a593Smuzhiyun * R30 (0x1E) - Clocking 3 509*4882a593Smuzhiyun */ 510*4882a593Smuzhiyun #define WM8961_CLK_TO_DIV_MASK 0x0180 /* CLK_TO_DIV - [8:7] */ 511*4882a593Smuzhiyun #define WM8961_CLK_TO_DIV_SHIFT 7 /* CLK_TO_DIV - [8:7] */ 512*4882a593Smuzhiyun #define WM8961_CLK_TO_DIV_WIDTH 2 /* CLK_TO_DIV - [8:7] */ 513*4882a593Smuzhiyun #define WM8961_CLK_256K_DIV_MASK 0x007E /* CLK_256K_DIV - [6:1] */ 514*4882a593Smuzhiyun #define WM8961_CLK_256K_DIV_SHIFT 1 /* CLK_256K_DIV - [6:1] */ 515*4882a593Smuzhiyun #define WM8961_CLK_256K_DIV_WIDTH 6 /* CLK_256K_DIV - [6:1] */ 516*4882a593Smuzhiyun #define WM8961_MANUAL_MODE 0x0001 /* MANUAL_MODE */ 517*4882a593Smuzhiyun #define WM8961_MANUAL_MODE_MASK 0x0001 /* MANUAL_MODE */ 518*4882a593Smuzhiyun #define WM8961_MANUAL_MODE_SHIFT 0 /* MANUAL_MODE */ 519*4882a593Smuzhiyun #define WM8961_MANUAL_MODE_WIDTH 1 /* MANUAL_MODE */ 520*4882a593Smuzhiyun 521*4882a593Smuzhiyun /* 522*4882a593Smuzhiyun * R32 (0x20) - ADCL signal path 523*4882a593Smuzhiyun */ 524*4882a593Smuzhiyun #define WM8961_LMICBOOST_MASK 0x0030 /* LMICBOOST - [5:4] */ 525*4882a593Smuzhiyun #define WM8961_LMICBOOST_SHIFT 4 /* LMICBOOST - [5:4] */ 526*4882a593Smuzhiyun #define WM8961_LMICBOOST_WIDTH 2 /* LMICBOOST - [5:4] */ 527*4882a593Smuzhiyun 528*4882a593Smuzhiyun /* 529*4882a593Smuzhiyun * R33 (0x21) - ADCR signal path 530*4882a593Smuzhiyun */ 531*4882a593Smuzhiyun #define WM8961_RMICBOOST_MASK 0x0030 /* RMICBOOST - [5:4] */ 532*4882a593Smuzhiyun #define WM8961_RMICBOOST_SHIFT 4 /* RMICBOOST - [5:4] */ 533*4882a593Smuzhiyun #define WM8961_RMICBOOST_WIDTH 2 /* RMICBOOST - [5:4] */ 534*4882a593Smuzhiyun 535*4882a593Smuzhiyun /* 536*4882a593Smuzhiyun * R40 (0x28) - LOUT2 volume 537*4882a593Smuzhiyun */ 538*4882a593Smuzhiyun #define WM8961_SPKVU 0x0100 /* SPKVU */ 539*4882a593Smuzhiyun #define WM8961_SPKVU_MASK 0x0100 /* SPKVU */ 540*4882a593Smuzhiyun #define WM8961_SPKVU_SHIFT 8 /* SPKVU */ 541*4882a593Smuzhiyun #define WM8961_SPKVU_WIDTH 1 /* SPKVU */ 542*4882a593Smuzhiyun #define WM8961_SPKLZC 0x0080 /* SPKLZC */ 543*4882a593Smuzhiyun #define WM8961_SPKLZC_MASK 0x0080 /* SPKLZC */ 544*4882a593Smuzhiyun #define WM8961_SPKLZC_SHIFT 7 /* SPKLZC */ 545*4882a593Smuzhiyun #define WM8961_SPKLZC_WIDTH 1 /* SPKLZC */ 546*4882a593Smuzhiyun #define WM8961_SPKLVOL_MASK 0x007F /* SPKLVOL - [6:0] */ 547*4882a593Smuzhiyun #define WM8961_SPKLVOL_SHIFT 0 /* SPKLVOL - [6:0] */ 548*4882a593Smuzhiyun #define WM8961_SPKLVOL_WIDTH 7 /* SPKLVOL - [6:0] */ 549*4882a593Smuzhiyun 550*4882a593Smuzhiyun /* 551*4882a593Smuzhiyun * R41 (0x29) - ROUT2 volume 552*4882a593Smuzhiyun */ 553*4882a593Smuzhiyun #define WM8961_SPKVU 0x0100 /* SPKVU */ 554*4882a593Smuzhiyun #define WM8961_SPKVU_MASK 0x0100 /* SPKVU */ 555*4882a593Smuzhiyun #define WM8961_SPKVU_SHIFT 8 /* SPKVU */ 556*4882a593Smuzhiyun #define WM8961_SPKVU_WIDTH 1 /* SPKVU */ 557*4882a593Smuzhiyun #define WM8961_SPKRZC 0x0080 /* SPKRZC */ 558*4882a593Smuzhiyun #define WM8961_SPKRZC_MASK 0x0080 /* SPKRZC */ 559*4882a593Smuzhiyun #define WM8961_SPKRZC_SHIFT 7 /* SPKRZC */ 560*4882a593Smuzhiyun #define WM8961_SPKRZC_WIDTH 1 /* SPKRZC */ 561*4882a593Smuzhiyun #define WM8961_SPKRVOL_MASK 0x007F /* SPKRVOL - [6:0] */ 562*4882a593Smuzhiyun #define WM8961_SPKRVOL_SHIFT 0 /* SPKRVOL - [6:0] */ 563*4882a593Smuzhiyun #define WM8961_SPKRVOL_WIDTH 7 /* SPKRVOL - [6:0] */ 564*4882a593Smuzhiyun 565*4882a593Smuzhiyun /* 566*4882a593Smuzhiyun * R47 (0x2F) - Pwr Mgmt (3) 567*4882a593Smuzhiyun */ 568*4882a593Smuzhiyun #define WM8961_TEMP_SHUT 0x0002 /* TEMP_SHUT */ 569*4882a593Smuzhiyun #define WM8961_TEMP_SHUT_MASK 0x0002 /* TEMP_SHUT */ 570*4882a593Smuzhiyun #define WM8961_TEMP_SHUT_SHIFT 1 /* TEMP_SHUT */ 571*4882a593Smuzhiyun #define WM8961_TEMP_SHUT_WIDTH 1 /* TEMP_SHUT */ 572*4882a593Smuzhiyun #define WM8961_TEMP_WARN 0x0001 /* TEMP_WARN */ 573*4882a593Smuzhiyun #define WM8961_TEMP_WARN_MASK 0x0001 /* TEMP_WARN */ 574*4882a593Smuzhiyun #define WM8961_TEMP_WARN_SHIFT 0 /* TEMP_WARN */ 575*4882a593Smuzhiyun #define WM8961_TEMP_WARN_WIDTH 1 /* TEMP_WARN */ 576*4882a593Smuzhiyun 577*4882a593Smuzhiyun /* 578*4882a593Smuzhiyun * R48 (0x30) - Additional Control (4) 579*4882a593Smuzhiyun */ 580*4882a593Smuzhiyun #define WM8961_TSENSEN 0x0002 /* TSENSEN */ 581*4882a593Smuzhiyun #define WM8961_TSENSEN_MASK 0x0002 /* TSENSEN */ 582*4882a593Smuzhiyun #define WM8961_TSENSEN_SHIFT 1 /* TSENSEN */ 583*4882a593Smuzhiyun #define WM8961_TSENSEN_WIDTH 1 /* TSENSEN */ 584*4882a593Smuzhiyun #define WM8961_MBSEL 0x0001 /* MBSEL */ 585*4882a593Smuzhiyun #define WM8961_MBSEL_MASK 0x0001 /* MBSEL */ 586*4882a593Smuzhiyun #define WM8961_MBSEL_SHIFT 0 /* MBSEL */ 587*4882a593Smuzhiyun #define WM8961_MBSEL_WIDTH 1 /* MBSEL */ 588*4882a593Smuzhiyun 589*4882a593Smuzhiyun /* 590*4882a593Smuzhiyun * R49 (0x31) - Class D Control 1 591*4882a593Smuzhiyun */ 592*4882a593Smuzhiyun #define WM8961_SPKR_ENA 0x0080 /* SPKR_ENA */ 593*4882a593Smuzhiyun #define WM8961_SPKR_ENA_MASK 0x0080 /* SPKR_ENA */ 594*4882a593Smuzhiyun #define WM8961_SPKR_ENA_SHIFT 7 /* SPKR_ENA */ 595*4882a593Smuzhiyun #define WM8961_SPKR_ENA_WIDTH 1 /* SPKR_ENA */ 596*4882a593Smuzhiyun #define WM8961_SPKL_ENA 0x0040 /* SPKL_ENA */ 597*4882a593Smuzhiyun #define WM8961_SPKL_ENA_MASK 0x0040 /* SPKL_ENA */ 598*4882a593Smuzhiyun #define WM8961_SPKL_ENA_SHIFT 6 /* SPKL_ENA */ 599*4882a593Smuzhiyun #define WM8961_SPKL_ENA_WIDTH 1 /* SPKL_ENA */ 600*4882a593Smuzhiyun 601*4882a593Smuzhiyun /* 602*4882a593Smuzhiyun * R51 (0x33) - Class D Control 2 603*4882a593Smuzhiyun */ 604*4882a593Smuzhiyun #define WM8961_CLASSD_ACGAIN_MASK 0x0007 /* CLASSD_ACGAIN - [2:0] */ 605*4882a593Smuzhiyun #define WM8961_CLASSD_ACGAIN_SHIFT 0 /* CLASSD_ACGAIN - [2:0] */ 606*4882a593Smuzhiyun #define WM8961_CLASSD_ACGAIN_WIDTH 3 /* CLASSD_ACGAIN - [2:0] */ 607*4882a593Smuzhiyun 608*4882a593Smuzhiyun /* 609*4882a593Smuzhiyun * R56 (0x38) - Clocking 4 610*4882a593Smuzhiyun */ 611*4882a593Smuzhiyun #define WM8961_CLK_DCS_DIV_MASK 0x01E0 /* CLK_DCS_DIV - [8:5] */ 612*4882a593Smuzhiyun #define WM8961_CLK_DCS_DIV_SHIFT 5 /* CLK_DCS_DIV - [8:5] */ 613*4882a593Smuzhiyun #define WM8961_CLK_DCS_DIV_WIDTH 4 /* CLK_DCS_DIV - [8:5] */ 614*4882a593Smuzhiyun #define WM8961_CLK_SYS_RATE_MASK 0x001E /* CLK_SYS_RATE - [4:1] */ 615*4882a593Smuzhiyun #define WM8961_CLK_SYS_RATE_SHIFT 1 /* CLK_SYS_RATE - [4:1] */ 616*4882a593Smuzhiyun #define WM8961_CLK_SYS_RATE_WIDTH 4 /* CLK_SYS_RATE - [4:1] */ 617*4882a593Smuzhiyun 618*4882a593Smuzhiyun /* 619*4882a593Smuzhiyun * R57 (0x39) - DSP Sidetone 0 620*4882a593Smuzhiyun */ 621*4882a593Smuzhiyun #define WM8961_ADCR_DAC_SVOL_MASK 0x00F0 /* ADCR_DAC_SVOL - [7:4] */ 622*4882a593Smuzhiyun #define WM8961_ADCR_DAC_SVOL_SHIFT 4 /* ADCR_DAC_SVOL - [7:4] */ 623*4882a593Smuzhiyun #define WM8961_ADCR_DAC_SVOL_WIDTH 4 /* ADCR_DAC_SVOL - [7:4] */ 624*4882a593Smuzhiyun #define WM8961_ADC_TO_DACR_MASK 0x000C /* ADC_TO_DACR - [3:2] */ 625*4882a593Smuzhiyun #define WM8961_ADC_TO_DACR_SHIFT 2 /* ADC_TO_DACR - [3:2] */ 626*4882a593Smuzhiyun #define WM8961_ADC_TO_DACR_WIDTH 2 /* ADC_TO_DACR - [3:2] */ 627*4882a593Smuzhiyun 628*4882a593Smuzhiyun /* 629*4882a593Smuzhiyun * R58 (0x3A) - DSP Sidetone 1 630*4882a593Smuzhiyun */ 631*4882a593Smuzhiyun #define WM8961_ADCL_DAC_SVOL_MASK 0x00F0 /* ADCL_DAC_SVOL - [7:4] */ 632*4882a593Smuzhiyun #define WM8961_ADCL_DAC_SVOL_SHIFT 4 /* ADCL_DAC_SVOL - [7:4] */ 633*4882a593Smuzhiyun #define WM8961_ADCL_DAC_SVOL_WIDTH 4 /* ADCL_DAC_SVOL - [7:4] */ 634*4882a593Smuzhiyun #define WM8961_ADC_TO_DACL_MASK 0x000C /* ADC_TO_DACL - [3:2] */ 635*4882a593Smuzhiyun #define WM8961_ADC_TO_DACL_SHIFT 2 /* ADC_TO_DACL - [3:2] */ 636*4882a593Smuzhiyun #define WM8961_ADC_TO_DACL_WIDTH 2 /* ADC_TO_DACL - [3:2] */ 637*4882a593Smuzhiyun 638*4882a593Smuzhiyun /* 639*4882a593Smuzhiyun * R60 (0x3C) - DC Servo 0 640*4882a593Smuzhiyun */ 641*4882a593Smuzhiyun #define WM8961_DCS_ENA_CHAN_INL 0x0080 /* DCS_ENA_CHAN_INL */ 642*4882a593Smuzhiyun #define WM8961_DCS_ENA_CHAN_INL_MASK 0x0080 /* DCS_ENA_CHAN_INL */ 643*4882a593Smuzhiyun #define WM8961_DCS_ENA_CHAN_INL_SHIFT 7 /* DCS_ENA_CHAN_INL */ 644*4882a593Smuzhiyun #define WM8961_DCS_ENA_CHAN_INL_WIDTH 1 /* DCS_ENA_CHAN_INL */ 645*4882a593Smuzhiyun #define WM8961_DCS_TRIG_STARTUP_INL 0x0040 /* DCS_TRIG_STARTUP_INL */ 646*4882a593Smuzhiyun #define WM8961_DCS_TRIG_STARTUP_INL_MASK 0x0040 /* DCS_TRIG_STARTUP_INL */ 647*4882a593Smuzhiyun #define WM8961_DCS_TRIG_STARTUP_INL_SHIFT 6 /* DCS_TRIG_STARTUP_INL */ 648*4882a593Smuzhiyun #define WM8961_DCS_TRIG_STARTUP_INL_WIDTH 1 /* DCS_TRIG_STARTUP_INL */ 649*4882a593Smuzhiyun #define WM8961_DCS_TRIG_SERIES_INL 0x0010 /* DCS_TRIG_SERIES_INL */ 650*4882a593Smuzhiyun #define WM8961_DCS_TRIG_SERIES_INL_MASK 0x0010 /* DCS_TRIG_SERIES_INL */ 651*4882a593Smuzhiyun #define WM8961_DCS_TRIG_SERIES_INL_SHIFT 4 /* DCS_TRIG_SERIES_INL */ 652*4882a593Smuzhiyun #define WM8961_DCS_TRIG_SERIES_INL_WIDTH 1 /* DCS_TRIG_SERIES_INL */ 653*4882a593Smuzhiyun #define WM8961_DCS_ENA_CHAN_INR 0x0008 /* DCS_ENA_CHAN_INR */ 654*4882a593Smuzhiyun #define WM8961_DCS_ENA_CHAN_INR_MASK 0x0008 /* DCS_ENA_CHAN_INR */ 655*4882a593Smuzhiyun #define WM8961_DCS_ENA_CHAN_INR_SHIFT 3 /* DCS_ENA_CHAN_INR */ 656*4882a593Smuzhiyun #define WM8961_DCS_ENA_CHAN_INR_WIDTH 1 /* DCS_ENA_CHAN_INR */ 657*4882a593Smuzhiyun #define WM8961_DCS_TRIG_STARTUP_INR 0x0004 /* DCS_TRIG_STARTUP_INR */ 658*4882a593Smuzhiyun #define WM8961_DCS_TRIG_STARTUP_INR_MASK 0x0004 /* DCS_TRIG_STARTUP_INR */ 659*4882a593Smuzhiyun #define WM8961_DCS_TRIG_STARTUP_INR_SHIFT 2 /* DCS_TRIG_STARTUP_INR */ 660*4882a593Smuzhiyun #define WM8961_DCS_TRIG_STARTUP_INR_WIDTH 1 /* DCS_TRIG_STARTUP_INR */ 661*4882a593Smuzhiyun #define WM8961_DCS_TRIG_SERIES_INR 0x0001 /* DCS_TRIG_SERIES_INR */ 662*4882a593Smuzhiyun #define WM8961_DCS_TRIG_SERIES_INR_MASK 0x0001 /* DCS_TRIG_SERIES_INR */ 663*4882a593Smuzhiyun #define WM8961_DCS_TRIG_SERIES_INR_SHIFT 0 /* DCS_TRIG_SERIES_INR */ 664*4882a593Smuzhiyun #define WM8961_DCS_TRIG_SERIES_INR_WIDTH 1 /* DCS_TRIG_SERIES_INR */ 665*4882a593Smuzhiyun 666*4882a593Smuzhiyun /* 667*4882a593Smuzhiyun * R61 (0x3D) - DC Servo 1 668*4882a593Smuzhiyun */ 669*4882a593Smuzhiyun #define WM8961_DCS_ENA_CHAN_HPL 0x0080 /* DCS_ENA_CHAN_HPL */ 670*4882a593Smuzhiyun #define WM8961_DCS_ENA_CHAN_HPL_MASK 0x0080 /* DCS_ENA_CHAN_HPL */ 671*4882a593Smuzhiyun #define WM8961_DCS_ENA_CHAN_HPL_SHIFT 7 /* DCS_ENA_CHAN_HPL */ 672*4882a593Smuzhiyun #define WM8961_DCS_ENA_CHAN_HPL_WIDTH 1 /* DCS_ENA_CHAN_HPL */ 673*4882a593Smuzhiyun #define WM8961_DCS_TRIG_STARTUP_HPL 0x0040 /* DCS_TRIG_STARTUP_HPL */ 674*4882a593Smuzhiyun #define WM8961_DCS_TRIG_STARTUP_HPL_MASK 0x0040 /* DCS_TRIG_STARTUP_HPL */ 675*4882a593Smuzhiyun #define WM8961_DCS_TRIG_STARTUP_HPL_SHIFT 6 /* DCS_TRIG_STARTUP_HPL */ 676*4882a593Smuzhiyun #define WM8961_DCS_TRIG_STARTUP_HPL_WIDTH 1 /* DCS_TRIG_STARTUP_HPL */ 677*4882a593Smuzhiyun #define WM8961_DCS_TRIG_SERIES_HPL 0x0010 /* DCS_TRIG_SERIES_HPL */ 678*4882a593Smuzhiyun #define WM8961_DCS_TRIG_SERIES_HPL_MASK 0x0010 /* DCS_TRIG_SERIES_HPL */ 679*4882a593Smuzhiyun #define WM8961_DCS_TRIG_SERIES_HPL_SHIFT 4 /* DCS_TRIG_SERIES_HPL */ 680*4882a593Smuzhiyun #define WM8961_DCS_TRIG_SERIES_HPL_WIDTH 1 /* DCS_TRIG_SERIES_HPL */ 681*4882a593Smuzhiyun #define WM8961_DCS_ENA_CHAN_HPR 0x0008 /* DCS_ENA_CHAN_HPR */ 682*4882a593Smuzhiyun #define WM8961_DCS_ENA_CHAN_HPR_MASK 0x0008 /* DCS_ENA_CHAN_HPR */ 683*4882a593Smuzhiyun #define WM8961_DCS_ENA_CHAN_HPR_SHIFT 3 /* DCS_ENA_CHAN_HPR */ 684*4882a593Smuzhiyun #define WM8961_DCS_ENA_CHAN_HPR_WIDTH 1 /* DCS_ENA_CHAN_HPR */ 685*4882a593Smuzhiyun #define WM8961_DCS_TRIG_STARTUP_HPR 0x0004 /* DCS_TRIG_STARTUP_HPR */ 686*4882a593Smuzhiyun #define WM8961_DCS_TRIG_STARTUP_HPR_MASK 0x0004 /* DCS_TRIG_STARTUP_HPR */ 687*4882a593Smuzhiyun #define WM8961_DCS_TRIG_STARTUP_HPR_SHIFT 2 /* DCS_TRIG_STARTUP_HPR */ 688*4882a593Smuzhiyun #define WM8961_DCS_TRIG_STARTUP_HPR_WIDTH 1 /* DCS_TRIG_STARTUP_HPR */ 689*4882a593Smuzhiyun #define WM8961_DCS_TRIG_SERIES_HPR 0x0001 /* DCS_TRIG_SERIES_HPR */ 690*4882a593Smuzhiyun #define WM8961_DCS_TRIG_SERIES_HPR_MASK 0x0001 /* DCS_TRIG_SERIES_HPR */ 691*4882a593Smuzhiyun #define WM8961_DCS_TRIG_SERIES_HPR_SHIFT 0 /* DCS_TRIG_SERIES_HPR */ 692*4882a593Smuzhiyun #define WM8961_DCS_TRIG_SERIES_HPR_WIDTH 1 /* DCS_TRIG_SERIES_HPR */ 693*4882a593Smuzhiyun 694*4882a593Smuzhiyun /* 695*4882a593Smuzhiyun * R63 (0x3F) - DC Servo 3 696*4882a593Smuzhiyun */ 697*4882a593Smuzhiyun #define WM8961_DCS_FILT_BW_SERIES_MASK 0x0030 /* DCS_FILT_BW_SERIES - [5:4] */ 698*4882a593Smuzhiyun #define WM8961_DCS_FILT_BW_SERIES_SHIFT 4 /* DCS_FILT_BW_SERIES - [5:4] */ 699*4882a593Smuzhiyun #define WM8961_DCS_FILT_BW_SERIES_WIDTH 2 /* DCS_FILT_BW_SERIES - [5:4] */ 700*4882a593Smuzhiyun 701*4882a593Smuzhiyun /* 702*4882a593Smuzhiyun * R65 (0x41) - DC Servo 5 703*4882a593Smuzhiyun */ 704*4882a593Smuzhiyun #define WM8961_DCS_SERIES_NO_HP_MASK 0x007F /* DCS_SERIES_NO_HP - [6:0] */ 705*4882a593Smuzhiyun #define WM8961_DCS_SERIES_NO_HP_SHIFT 0 /* DCS_SERIES_NO_HP - [6:0] */ 706*4882a593Smuzhiyun #define WM8961_DCS_SERIES_NO_HP_WIDTH 7 /* DCS_SERIES_NO_HP - [6:0] */ 707*4882a593Smuzhiyun 708*4882a593Smuzhiyun /* 709*4882a593Smuzhiyun * R68 (0x44) - Analogue PGA Bias 710*4882a593Smuzhiyun */ 711*4882a593Smuzhiyun #define WM8961_HP_PGAS_BIAS_MASK 0x0007 /* HP_PGAS_BIAS - [2:0] */ 712*4882a593Smuzhiyun #define WM8961_HP_PGAS_BIAS_SHIFT 0 /* HP_PGAS_BIAS - [2:0] */ 713*4882a593Smuzhiyun #define WM8961_HP_PGAS_BIAS_WIDTH 3 /* HP_PGAS_BIAS - [2:0] */ 714*4882a593Smuzhiyun 715*4882a593Smuzhiyun /* 716*4882a593Smuzhiyun * R69 (0x45) - Analogue HP 0 717*4882a593Smuzhiyun */ 718*4882a593Smuzhiyun #define WM8961_HPL_RMV_SHORT 0x0080 /* HPL_RMV_SHORT */ 719*4882a593Smuzhiyun #define WM8961_HPL_RMV_SHORT_MASK 0x0080 /* HPL_RMV_SHORT */ 720*4882a593Smuzhiyun #define WM8961_HPL_RMV_SHORT_SHIFT 7 /* HPL_RMV_SHORT */ 721*4882a593Smuzhiyun #define WM8961_HPL_RMV_SHORT_WIDTH 1 /* HPL_RMV_SHORT */ 722*4882a593Smuzhiyun #define WM8961_HPL_ENA_OUTP 0x0040 /* HPL_ENA_OUTP */ 723*4882a593Smuzhiyun #define WM8961_HPL_ENA_OUTP_MASK 0x0040 /* HPL_ENA_OUTP */ 724*4882a593Smuzhiyun #define WM8961_HPL_ENA_OUTP_SHIFT 6 /* HPL_ENA_OUTP */ 725*4882a593Smuzhiyun #define WM8961_HPL_ENA_OUTP_WIDTH 1 /* HPL_ENA_OUTP */ 726*4882a593Smuzhiyun #define WM8961_HPL_ENA_DLY 0x0020 /* HPL_ENA_DLY */ 727*4882a593Smuzhiyun #define WM8961_HPL_ENA_DLY_MASK 0x0020 /* HPL_ENA_DLY */ 728*4882a593Smuzhiyun #define WM8961_HPL_ENA_DLY_SHIFT 5 /* HPL_ENA_DLY */ 729*4882a593Smuzhiyun #define WM8961_HPL_ENA_DLY_WIDTH 1 /* HPL_ENA_DLY */ 730*4882a593Smuzhiyun #define WM8961_HPL_ENA 0x0010 /* HPL_ENA */ 731*4882a593Smuzhiyun #define WM8961_HPL_ENA_MASK 0x0010 /* HPL_ENA */ 732*4882a593Smuzhiyun #define WM8961_HPL_ENA_SHIFT 4 /* HPL_ENA */ 733*4882a593Smuzhiyun #define WM8961_HPL_ENA_WIDTH 1 /* HPL_ENA */ 734*4882a593Smuzhiyun #define WM8961_HPR_RMV_SHORT 0x0008 /* HPR_RMV_SHORT */ 735*4882a593Smuzhiyun #define WM8961_HPR_RMV_SHORT_MASK 0x0008 /* HPR_RMV_SHORT */ 736*4882a593Smuzhiyun #define WM8961_HPR_RMV_SHORT_SHIFT 3 /* HPR_RMV_SHORT */ 737*4882a593Smuzhiyun #define WM8961_HPR_RMV_SHORT_WIDTH 1 /* HPR_RMV_SHORT */ 738*4882a593Smuzhiyun #define WM8961_HPR_ENA_OUTP 0x0004 /* HPR_ENA_OUTP */ 739*4882a593Smuzhiyun #define WM8961_HPR_ENA_OUTP_MASK 0x0004 /* HPR_ENA_OUTP */ 740*4882a593Smuzhiyun #define WM8961_HPR_ENA_OUTP_SHIFT 2 /* HPR_ENA_OUTP */ 741*4882a593Smuzhiyun #define WM8961_HPR_ENA_OUTP_WIDTH 1 /* HPR_ENA_OUTP */ 742*4882a593Smuzhiyun #define WM8961_HPR_ENA_DLY 0x0002 /* HPR_ENA_DLY */ 743*4882a593Smuzhiyun #define WM8961_HPR_ENA_DLY_MASK 0x0002 /* HPR_ENA_DLY */ 744*4882a593Smuzhiyun #define WM8961_HPR_ENA_DLY_SHIFT 1 /* HPR_ENA_DLY */ 745*4882a593Smuzhiyun #define WM8961_HPR_ENA_DLY_WIDTH 1 /* HPR_ENA_DLY */ 746*4882a593Smuzhiyun #define WM8961_HPR_ENA 0x0001 /* HPR_ENA */ 747*4882a593Smuzhiyun #define WM8961_HPR_ENA_MASK 0x0001 /* HPR_ENA */ 748*4882a593Smuzhiyun #define WM8961_HPR_ENA_SHIFT 0 /* HPR_ENA */ 749*4882a593Smuzhiyun #define WM8961_HPR_ENA_WIDTH 1 /* HPR_ENA */ 750*4882a593Smuzhiyun 751*4882a593Smuzhiyun /* 752*4882a593Smuzhiyun * R71 (0x47) - Analogue HP 2 753*4882a593Smuzhiyun */ 754*4882a593Smuzhiyun #define WM8961_HPL_VOL_MASK 0x01C0 /* HPL_VOL - [8:6] */ 755*4882a593Smuzhiyun #define WM8961_HPL_VOL_SHIFT 6 /* HPL_VOL - [8:6] */ 756*4882a593Smuzhiyun #define WM8961_HPL_VOL_WIDTH 3 /* HPL_VOL - [8:6] */ 757*4882a593Smuzhiyun #define WM8961_HPR_VOL_MASK 0x0038 /* HPR_VOL - [5:3] */ 758*4882a593Smuzhiyun #define WM8961_HPR_VOL_SHIFT 3 /* HPR_VOL - [5:3] */ 759*4882a593Smuzhiyun #define WM8961_HPR_VOL_WIDTH 3 /* HPR_VOL - [5:3] */ 760*4882a593Smuzhiyun #define WM8961_HP_BIAS_BOOST_MASK 0x0007 /* HP_BIAS_BOOST - [2:0] */ 761*4882a593Smuzhiyun #define WM8961_HP_BIAS_BOOST_SHIFT 0 /* HP_BIAS_BOOST - [2:0] */ 762*4882a593Smuzhiyun #define WM8961_HP_BIAS_BOOST_WIDTH 3 /* HP_BIAS_BOOST - [2:0] */ 763*4882a593Smuzhiyun 764*4882a593Smuzhiyun /* 765*4882a593Smuzhiyun * R72 (0x48) - Charge Pump 1 766*4882a593Smuzhiyun */ 767*4882a593Smuzhiyun #define WM8961_CP_ENA 0x0001 /* CP_ENA */ 768*4882a593Smuzhiyun #define WM8961_CP_ENA_MASK 0x0001 /* CP_ENA */ 769*4882a593Smuzhiyun #define WM8961_CP_ENA_SHIFT 0 /* CP_ENA */ 770*4882a593Smuzhiyun #define WM8961_CP_ENA_WIDTH 1 /* CP_ENA */ 771*4882a593Smuzhiyun 772*4882a593Smuzhiyun /* 773*4882a593Smuzhiyun * R82 (0x52) - Charge Pump B 774*4882a593Smuzhiyun */ 775*4882a593Smuzhiyun #define WM8961_CP_DYN_PWR_MASK 0x0003 /* CP_DYN_PWR - [1:0] */ 776*4882a593Smuzhiyun #define WM8961_CP_DYN_PWR_SHIFT 0 /* CP_DYN_PWR - [1:0] */ 777*4882a593Smuzhiyun #define WM8961_CP_DYN_PWR_WIDTH 2 /* CP_DYN_PWR - [1:0] */ 778*4882a593Smuzhiyun 779*4882a593Smuzhiyun /* 780*4882a593Smuzhiyun * R87 (0x57) - Write Sequencer 1 781*4882a593Smuzhiyun */ 782*4882a593Smuzhiyun #define WM8961_WSEQ_ENA 0x0020 /* WSEQ_ENA */ 783*4882a593Smuzhiyun #define WM8961_WSEQ_ENA_MASK 0x0020 /* WSEQ_ENA */ 784*4882a593Smuzhiyun #define WM8961_WSEQ_ENA_SHIFT 5 /* WSEQ_ENA */ 785*4882a593Smuzhiyun #define WM8961_WSEQ_ENA_WIDTH 1 /* WSEQ_ENA */ 786*4882a593Smuzhiyun #define WM8961_WSEQ_WRITE_INDEX_MASK 0x001F /* WSEQ_WRITE_INDEX - [4:0] */ 787*4882a593Smuzhiyun #define WM8961_WSEQ_WRITE_INDEX_SHIFT 0 /* WSEQ_WRITE_INDEX - [4:0] */ 788*4882a593Smuzhiyun #define WM8961_WSEQ_WRITE_INDEX_WIDTH 5 /* WSEQ_WRITE_INDEX - [4:0] */ 789*4882a593Smuzhiyun 790*4882a593Smuzhiyun /* 791*4882a593Smuzhiyun * R88 (0x58) - Write Sequencer 2 792*4882a593Smuzhiyun */ 793*4882a593Smuzhiyun #define WM8961_WSEQ_EOS 0x0100 /* WSEQ_EOS */ 794*4882a593Smuzhiyun #define WM8961_WSEQ_EOS_MASK 0x0100 /* WSEQ_EOS */ 795*4882a593Smuzhiyun #define WM8961_WSEQ_EOS_SHIFT 8 /* WSEQ_EOS */ 796*4882a593Smuzhiyun #define WM8961_WSEQ_EOS_WIDTH 1 /* WSEQ_EOS */ 797*4882a593Smuzhiyun #define WM8961_WSEQ_ADDR_MASK 0x00FF /* WSEQ_ADDR - [7:0] */ 798*4882a593Smuzhiyun #define WM8961_WSEQ_ADDR_SHIFT 0 /* WSEQ_ADDR - [7:0] */ 799*4882a593Smuzhiyun #define WM8961_WSEQ_ADDR_WIDTH 8 /* WSEQ_ADDR - [7:0] */ 800*4882a593Smuzhiyun 801*4882a593Smuzhiyun /* 802*4882a593Smuzhiyun * R89 (0x59) - Write Sequencer 3 803*4882a593Smuzhiyun */ 804*4882a593Smuzhiyun #define WM8961_WSEQ_DATA_MASK 0x00FF /* WSEQ_DATA - [7:0] */ 805*4882a593Smuzhiyun #define WM8961_WSEQ_DATA_SHIFT 0 /* WSEQ_DATA - [7:0] */ 806*4882a593Smuzhiyun #define WM8961_WSEQ_DATA_WIDTH 8 /* WSEQ_DATA - [7:0] */ 807*4882a593Smuzhiyun 808*4882a593Smuzhiyun /* 809*4882a593Smuzhiyun * R90 (0x5A) - Write Sequencer 4 810*4882a593Smuzhiyun */ 811*4882a593Smuzhiyun #define WM8961_WSEQ_ABORT 0x0100 /* WSEQ_ABORT */ 812*4882a593Smuzhiyun #define WM8961_WSEQ_ABORT_MASK 0x0100 /* WSEQ_ABORT */ 813*4882a593Smuzhiyun #define WM8961_WSEQ_ABORT_SHIFT 8 /* WSEQ_ABORT */ 814*4882a593Smuzhiyun #define WM8961_WSEQ_ABORT_WIDTH 1 /* WSEQ_ABORT */ 815*4882a593Smuzhiyun #define WM8961_WSEQ_START 0x0080 /* WSEQ_START */ 816*4882a593Smuzhiyun #define WM8961_WSEQ_START_MASK 0x0080 /* WSEQ_START */ 817*4882a593Smuzhiyun #define WM8961_WSEQ_START_SHIFT 7 /* WSEQ_START */ 818*4882a593Smuzhiyun #define WM8961_WSEQ_START_WIDTH 1 /* WSEQ_START */ 819*4882a593Smuzhiyun #define WM8961_WSEQ_START_INDEX_MASK 0x003F /* WSEQ_START_INDEX - [5:0] */ 820*4882a593Smuzhiyun #define WM8961_WSEQ_START_INDEX_SHIFT 0 /* WSEQ_START_INDEX - [5:0] */ 821*4882a593Smuzhiyun #define WM8961_WSEQ_START_INDEX_WIDTH 6 /* WSEQ_START_INDEX - [5:0] */ 822*4882a593Smuzhiyun 823*4882a593Smuzhiyun /* 824*4882a593Smuzhiyun * R91 (0x5B) - Write Sequencer 5 825*4882a593Smuzhiyun */ 826*4882a593Smuzhiyun #define WM8961_WSEQ_DATA_WIDTH_MASK 0x0070 /* WSEQ_DATA_WIDTH - [6:4] */ 827*4882a593Smuzhiyun #define WM8961_WSEQ_DATA_WIDTH_SHIFT 4 /* WSEQ_DATA_WIDTH - [6:4] */ 828*4882a593Smuzhiyun #define WM8961_WSEQ_DATA_WIDTH_WIDTH 3 /* WSEQ_DATA_WIDTH - [6:4] */ 829*4882a593Smuzhiyun #define WM8961_WSEQ_DATA_START_MASK 0x000F /* WSEQ_DATA_START - [3:0] */ 830*4882a593Smuzhiyun #define WM8961_WSEQ_DATA_START_SHIFT 0 /* WSEQ_DATA_START - [3:0] */ 831*4882a593Smuzhiyun #define WM8961_WSEQ_DATA_START_WIDTH 4 /* WSEQ_DATA_START - [3:0] */ 832*4882a593Smuzhiyun 833*4882a593Smuzhiyun /* 834*4882a593Smuzhiyun * R92 (0x5C) - Write Sequencer 6 835*4882a593Smuzhiyun */ 836*4882a593Smuzhiyun #define WM8961_WSEQ_DELAY_MASK 0x000F /* WSEQ_DELAY - [3:0] */ 837*4882a593Smuzhiyun #define WM8961_WSEQ_DELAY_SHIFT 0 /* WSEQ_DELAY - [3:0] */ 838*4882a593Smuzhiyun #define WM8961_WSEQ_DELAY_WIDTH 4 /* WSEQ_DELAY - [3:0] */ 839*4882a593Smuzhiyun 840*4882a593Smuzhiyun /* 841*4882a593Smuzhiyun * R93 (0x5D) - Write Sequencer 7 842*4882a593Smuzhiyun */ 843*4882a593Smuzhiyun #define WM8961_WSEQ_BUSY 0x0001 /* WSEQ_BUSY */ 844*4882a593Smuzhiyun #define WM8961_WSEQ_BUSY_MASK 0x0001 /* WSEQ_BUSY */ 845*4882a593Smuzhiyun #define WM8961_WSEQ_BUSY_SHIFT 0 /* WSEQ_BUSY */ 846*4882a593Smuzhiyun #define WM8961_WSEQ_BUSY_WIDTH 1 /* WSEQ_BUSY */ 847*4882a593Smuzhiyun 848*4882a593Smuzhiyun /* 849*4882a593Smuzhiyun * R252 (0xFC) - General test 1 850*4882a593Smuzhiyun */ 851*4882a593Smuzhiyun #define WM8961_ARA_ENA 0x0002 /* ARA_ENA */ 852*4882a593Smuzhiyun #define WM8961_ARA_ENA_MASK 0x0002 /* ARA_ENA */ 853*4882a593Smuzhiyun #define WM8961_ARA_ENA_SHIFT 1 /* ARA_ENA */ 854*4882a593Smuzhiyun #define WM8961_ARA_ENA_WIDTH 1 /* ARA_ENA */ 855*4882a593Smuzhiyun #define WM8961_AUTO_INC 0x0001 /* AUTO_INC */ 856*4882a593Smuzhiyun #define WM8961_AUTO_INC_MASK 0x0001 /* AUTO_INC */ 857*4882a593Smuzhiyun #define WM8961_AUTO_INC_SHIFT 0 /* AUTO_INC */ 858*4882a593Smuzhiyun #define WM8961_AUTO_INC_WIDTH 1 /* AUTO_INC */ 859*4882a593Smuzhiyun 860*4882a593Smuzhiyun #endif 861