1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * wm8960.h -- WM8960 Soc Audio driver 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef _WM8960_H 7*4882a593Smuzhiyun #define _WM8960_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun /* WM8960 register space */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define WM8960_CACHEREGNUM 56 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define WM8960_LINVOL 0x0 15*4882a593Smuzhiyun #define WM8960_RINVOL 0x1 16*4882a593Smuzhiyun #define WM8960_LOUT1 0x2 17*4882a593Smuzhiyun #define WM8960_ROUT1 0x3 18*4882a593Smuzhiyun #define WM8960_CLOCK1 0x4 19*4882a593Smuzhiyun #define WM8960_DACCTL1 0x5 20*4882a593Smuzhiyun #define WM8960_DACCTL2 0x6 21*4882a593Smuzhiyun #define WM8960_IFACE1 0x7 22*4882a593Smuzhiyun #define WM8960_CLOCK2 0x8 23*4882a593Smuzhiyun #define WM8960_IFACE2 0x9 24*4882a593Smuzhiyun #define WM8960_LDAC 0xa 25*4882a593Smuzhiyun #define WM8960_RDAC 0xb 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #define WM8960_RESET 0xf 28*4882a593Smuzhiyun #define WM8960_3D 0x10 29*4882a593Smuzhiyun #define WM8960_ALC1 0x11 30*4882a593Smuzhiyun #define WM8960_ALC2 0x12 31*4882a593Smuzhiyun #define WM8960_ALC3 0x13 32*4882a593Smuzhiyun #define WM8960_NOISEG 0x14 33*4882a593Smuzhiyun #define WM8960_LADC 0x15 34*4882a593Smuzhiyun #define WM8960_RADC 0x16 35*4882a593Smuzhiyun #define WM8960_ADDCTL1 0x17 36*4882a593Smuzhiyun #define WM8960_ADDCTL2 0x18 37*4882a593Smuzhiyun #define WM8960_POWER1 0x19 38*4882a593Smuzhiyun #define WM8960_POWER2 0x1a 39*4882a593Smuzhiyun #define WM8960_ADDCTL3 0x1b 40*4882a593Smuzhiyun #define WM8960_APOP1 0x1c 41*4882a593Smuzhiyun #define WM8960_APOP2 0x1d 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #define WM8960_LINPATH 0x20 44*4882a593Smuzhiyun #define WM8960_RINPATH 0x21 45*4882a593Smuzhiyun #define WM8960_LOUTMIX 0x22 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun #define WM8960_ROUTMIX 0x25 48*4882a593Smuzhiyun #define WM8960_MONOMIX1 0x26 49*4882a593Smuzhiyun #define WM8960_MONOMIX2 0x27 50*4882a593Smuzhiyun #define WM8960_LOUT2 0x28 51*4882a593Smuzhiyun #define WM8960_ROUT2 0x29 52*4882a593Smuzhiyun #define WM8960_MONO 0x2a 53*4882a593Smuzhiyun #define WM8960_INBMIX1 0x2b 54*4882a593Smuzhiyun #define WM8960_INBMIX2 0x2c 55*4882a593Smuzhiyun #define WM8960_BYPASS1 0x2d 56*4882a593Smuzhiyun #define WM8960_BYPASS2 0x2e 57*4882a593Smuzhiyun #define WM8960_POWER3 0x2f 58*4882a593Smuzhiyun #define WM8960_ADDCTL4 0x30 59*4882a593Smuzhiyun #define WM8960_CLASSD1 0x31 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun #define WM8960_CLASSD3 0x33 62*4882a593Smuzhiyun #define WM8960_PLL1 0x34 63*4882a593Smuzhiyun #define WM8960_PLL2 0x35 64*4882a593Smuzhiyun #define WM8960_PLL3 0x36 65*4882a593Smuzhiyun #define WM8960_PLL4 0x37 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun /* 69*4882a593Smuzhiyun * WM8960 Clock dividers 70*4882a593Smuzhiyun */ 71*4882a593Smuzhiyun #define WM8960_SYSCLKDIV 0 72*4882a593Smuzhiyun #define WM8960_DACDIV 1 73*4882a593Smuzhiyun #define WM8960_OPCLKDIV 2 74*4882a593Smuzhiyun #define WM8960_DCLKDIV 3 75*4882a593Smuzhiyun #define WM8960_TOCLKSEL 4 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun #define WM8960_SYSCLK_DIV_1 (0 << 1) 78*4882a593Smuzhiyun #define WM8960_SYSCLK_DIV_2 (2 << 1) 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun #define WM8960_SYSCLK_MCLK (0 << 0) 81*4882a593Smuzhiyun #define WM8960_SYSCLK_PLL (1 << 0) 82*4882a593Smuzhiyun #define WM8960_SYSCLK_AUTO (2 << 0) 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun #define WM8960_DAC_DIV_1 (0 << 3) 85*4882a593Smuzhiyun #define WM8960_DAC_DIV_1_5 (1 << 3) 86*4882a593Smuzhiyun #define WM8960_DAC_DIV_2 (2 << 3) 87*4882a593Smuzhiyun #define WM8960_DAC_DIV_3 (3 << 3) 88*4882a593Smuzhiyun #define WM8960_DAC_DIV_4 (4 << 3) 89*4882a593Smuzhiyun #define WM8960_DAC_DIV_5_5 (5 << 3) 90*4882a593Smuzhiyun #define WM8960_DAC_DIV_6 (6 << 3) 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun #define WM8960_DCLK_DIV_1_5 (0 << 6) 93*4882a593Smuzhiyun #define WM8960_DCLK_DIV_2 (1 << 6) 94*4882a593Smuzhiyun #define WM8960_DCLK_DIV_3 (2 << 6) 95*4882a593Smuzhiyun #define WM8960_DCLK_DIV_4 (3 << 6) 96*4882a593Smuzhiyun #define WM8960_DCLK_DIV_6 (4 << 6) 97*4882a593Smuzhiyun #define WM8960_DCLK_DIV_8 (5 << 6) 98*4882a593Smuzhiyun #define WM8960_DCLK_DIV_12 (6 << 6) 99*4882a593Smuzhiyun #define WM8960_DCLK_DIV_16 (7 << 6) 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun #define WM8960_TOCLK_F19 (0 << 1) 102*4882a593Smuzhiyun #define WM8960_TOCLK_F21 (1 << 1) 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun #define WM8960_OPCLK_DIV_1 (0 << 0) 105*4882a593Smuzhiyun #define WM8960_OPCLK_DIV_2 (1 << 0) 106*4882a593Smuzhiyun #define WM8960_OPCLK_DIV_3 (2 << 0) 107*4882a593Smuzhiyun #define WM8960_OPCLK_DIV_4 (3 << 0) 108*4882a593Smuzhiyun #define WM8960_OPCLK_DIV_5_5 (4 << 0) 109*4882a593Smuzhiyun #define WM8960_OPCLK_DIV_6 (5 << 0) 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun #endif 112