1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * wm8958-dsp2.c -- WM8958 DSP2 support
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright 2011 Wolfson Microelectronics plc
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <linux/module.h>
11*4882a593Smuzhiyun #include <linux/moduleparam.h>
12*4882a593Smuzhiyun #include <linux/init.h>
13*4882a593Smuzhiyun #include <linux/delay.h>
14*4882a593Smuzhiyun #include <linux/pm.h>
15*4882a593Smuzhiyun #include <linux/i2c.h>
16*4882a593Smuzhiyun #include <linux/platform_device.h>
17*4882a593Smuzhiyun #include <linux/slab.h>
18*4882a593Smuzhiyun #include <sound/soc.h>
19*4882a593Smuzhiyun #include <sound/initval.h>
20*4882a593Smuzhiyun #include <sound/tlv.h>
21*4882a593Smuzhiyun #include <trace/events/asoc.h>
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun #include <linux/mfd/wm8994/core.h>
24*4882a593Smuzhiyun #include <linux/mfd/wm8994/registers.h>
25*4882a593Smuzhiyun #include <linux/mfd/wm8994/pdata.h>
26*4882a593Smuzhiyun #include <linux/mfd/wm8994/gpio.h>
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun #include <asm/unaligned.h>
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun #include "wm8994.h"
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun #define WM_FW_BLOCK_INFO 0xff
33*4882a593Smuzhiyun #define WM_FW_BLOCK_PM 0x00
34*4882a593Smuzhiyun #define WM_FW_BLOCK_X 0x01
35*4882a593Smuzhiyun #define WM_FW_BLOCK_Y 0x02
36*4882a593Smuzhiyun #define WM_FW_BLOCK_Z 0x03
37*4882a593Smuzhiyun #define WM_FW_BLOCK_I 0x06
38*4882a593Smuzhiyun #define WM_FW_BLOCK_A 0x08
39*4882a593Smuzhiyun #define WM_FW_BLOCK_C 0x0c
40*4882a593Smuzhiyun
wm8958_dsp2_fw(struct snd_soc_component * component,const char * name,const struct firmware * fw,bool check)41*4882a593Smuzhiyun static int wm8958_dsp2_fw(struct snd_soc_component *component, const char *name,
42*4882a593Smuzhiyun const struct firmware *fw, bool check)
43*4882a593Smuzhiyun {
44*4882a593Smuzhiyun struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
45*4882a593Smuzhiyun u64 data64;
46*4882a593Smuzhiyun u32 data32;
47*4882a593Smuzhiyun const u8 *data;
48*4882a593Smuzhiyun char *str;
49*4882a593Smuzhiyun size_t block_len, len;
50*4882a593Smuzhiyun int ret = 0;
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun /* Suppress unneeded downloads */
53*4882a593Smuzhiyun if (wm8994->cur_fw == fw)
54*4882a593Smuzhiyun return 0;
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun if (fw->size < 32) {
57*4882a593Smuzhiyun dev_err(component->dev, "%s: firmware too short (%zd bytes)\n",
58*4882a593Smuzhiyun name, fw->size);
59*4882a593Smuzhiyun goto err;
60*4882a593Smuzhiyun }
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun if (memcmp(fw->data, "WMFW", 4) != 0) {
63*4882a593Smuzhiyun data32 = get_unaligned_be32(fw->data);
64*4882a593Smuzhiyun dev_err(component->dev, "%s: firmware has bad file magic %08x\n",
65*4882a593Smuzhiyun name, data32);
66*4882a593Smuzhiyun goto err;
67*4882a593Smuzhiyun }
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun len = get_unaligned_be32(fw->data + 4);
70*4882a593Smuzhiyun data32 = get_unaligned_be32(fw->data + 8);
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun if ((data32 >> 24) & 0xff) {
73*4882a593Smuzhiyun dev_err(component->dev, "%s: unsupported firmware version %d\n",
74*4882a593Smuzhiyun name, (data32 >> 24) & 0xff);
75*4882a593Smuzhiyun goto err;
76*4882a593Smuzhiyun }
77*4882a593Smuzhiyun if ((data32 & 0xffff) != 8958) {
78*4882a593Smuzhiyun dev_err(component->dev, "%s: unsupported target device %d\n",
79*4882a593Smuzhiyun name, data32 & 0xffff);
80*4882a593Smuzhiyun goto err;
81*4882a593Smuzhiyun }
82*4882a593Smuzhiyun if (((data32 >> 16) & 0xff) != 0xc) {
83*4882a593Smuzhiyun dev_err(component->dev, "%s: unsupported target core %d\n",
84*4882a593Smuzhiyun name, (data32 >> 16) & 0xff);
85*4882a593Smuzhiyun goto err;
86*4882a593Smuzhiyun }
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun if (check) {
89*4882a593Smuzhiyun data64 = get_unaligned_be64(fw->data + 24);
90*4882a593Smuzhiyun dev_info(component->dev, "%s timestamp %llx\n", name, data64);
91*4882a593Smuzhiyun } else {
92*4882a593Smuzhiyun snd_soc_component_write(component, 0x102, 0x2);
93*4882a593Smuzhiyun snd_soc_component_write(component, 0x900, 0x2);
94*4882a593Smuzhiyun }
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun data = fw->data + len;
97*4882a593Smuzhiyun len = fw->size - len;
98*4882a593Smuzhiyun while (len) {
99*4882a593Smuzhiyun if (len < 12) {
100*4882a593Smuzhiyun dev_err(component->dev, "%s short data block of %zd\n",
101*4882a593Smuzhiyun name, len);
102*4882a593Smuzhiyun goto err;
103*4882a593Smuzhiyun }
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun block_len = get_unaligned_be32(data + 4);
106*4882a593Smuzhiyun if (block_len + 8 > len) {
107*4882a593Smuzhiyun dev_err(component->dev, "%zd byte block longer than file\n",
108*4882a593Smuzhiyun block_len);
109*4882a593Smuzhiyun goto err;
110*4882a593Smuzhiyun }
111*4882a593Smuzhiyun if (block_len == 0) {
112*4882a593Smuzhiyun dev_err(component->dev, "Zero length block\n");
113*4882a593Smuzhiyun goto err;
114*4882a593Smuzhiyun }
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun data32 = get_unaligned_be32(data);
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun switch ((data32 >> 24) & 0xff) {
119*4882a593Smuzhiyun case WM_FW_BLOCK_INFO:
120*4882a593Smuzhiyun /* Informational text */
121*4882a593Smuzhiyun if (!check)
122*4882a593Smuzhiyun break;
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun str = kzalloc(block_len + 1, GFP_KERNEL);
125*4882a593Smuzhiyun if (str) {
126*4882a593Smuzhiyun memcpy(str, data + 8, block_len);
127*4882a593Smuzhiyun dev_info(component->dev, "%s: %s\n", name, str);
128*4882a593Smuzhiyun kfree(str);
129*4882a593Smuzhiyun } else {
130*4882a593Smuzhiyun dev_err(component->dev, "Out of memory\n");
131*4882a593Smuzhiyun }
132*4882a593Smuzhiyun break;
133*4882a593Smuzhiyun case WM_FW_BLOCK_PM:
134*4882a593Smuzhiyun case WM_FW_BLOCK_X:
135*4882a593Smuzhiyun case WM_FW_BLOCK_Y:
136*4882a593Smuzhiyun case WM_FW_BLOCK_Z:
137*4882a593Smuzhiyun case WM_FW_BLOCK_I:
138*4882a593Smuzhiyun case WM_FW_BLOCK_A:
139*4882a593Smuzhiyun case WM_FW_BLOCK_C:
140*4882a593Smuzhiyun dev_dbg(component->dev, "%s: %zd bytes of %x@%x\n", name,
141*4882a593Smuzhiyun block_len, (data32 >> 24) & 0xff,
142*4882a593Smuzhiyun data32 & 0xffffff);
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun if (check)
145*4882a593Smuzhiyun break;
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun data32 &= 0xffffff;
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun wm8994_bulk_write(wm8994->wm8994,
150*4882a593Smuzhiyun data32 & 0xffffff,
151*4882a593Smuzhiyun block_len / 2,
152*4882a593Smuzhiyun (void *)(data + 8));
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun break;
155*4882a593Smuzhiyun default:
156*4882a593Smuzhiyun dev_warn(component->dev, "%s: unknown block type %d\n",
157*4882a593Smuzhiyun name, (data32 >> 24) & 0xff);
158*4882a593Smuzhiyun break;
159*4882a593Smuzhiyun }
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun /* Round up to the next 32 bit word */
162*4882a593Smuzhiyun block_len += block_len % 4;
163*4882a593Smuzhiyun
164*4882a593Smuzhiyun data += block_len + 8;
165*4882a593Smuzhiyun len -= block_len + 8;
166*4882a593Smuzhiyun }
167*4882a593Smuzhiyun
168*4882a593Smuzhiyun if (!check) {
169*4882a593Smuzhiyun dev_dbg(component->dev, "%s: download done\n", name);
170*4882a593Smuzhiyun wm8994->cur_fw = fw;
171*4882a593Smuzhiyun } else {
172*4882a593Smuzhiyun dev_info(component->dev, "%s: got firmware\n", name);
173*4882a593Smuzhiyun }
174*4882a593Smuzhiyun
175*4882a593Smuzhiyun goto ok;
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun err:
178*4882a593Smuzhiyun ret = -EINVAL;
179*4882a593Smuzhiyun ok:
180*4882a593Smuzhiyun if (!check) {
181*4882a593Smuzhiyun snd_soc_component_write(component, 0x900, 0x0);
182*4882a593Smuzhiyun snd_soc_component_write(component, 0x102, 0x0);
183*4882a593Smuzhiyun }
184*4882a593Smuzhiyun
185*4882a593Smuzhiyun return ret;
186*4882a593Smuzhiyun }
187*4882a593Smuzhiyun
wm8958_dsp_start_mbc(struct snd_soc_component * component,int path)188*4882a593Smuzhiyun static void wm8958_dsp_start_mbc(struct snd_soc_component *component, int path)
189*4882a593Smuzhiyun {
190*4882a593Smuzhiyun struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
191*4882a593Smuzhiyun struct wm8994 *control = wm8994->wm8994;
192*4882a593Smuzhiyun int i;
193*4882a593Smuzhiyun
194*4882a593Smuzhiyun /* If the DSP is already running then noop */
195*4882a593Smuzhiyun if (snd_soc_component_read(component, WM8958_DSP2_PROGRAM) & WM8958_DSP2_ENA)
196*4882a593Smuzhiyun return;
197*4882a593Smuzhiyun
198*4882a593Smuzhiyun /* If we have MBC firmware download it */
199*4882a593Smuzhiyun if (wm8994->mbc)
200*4882a593Smuzhiyun wm8958_dsp2_fw(component, "MBC", wm8994->mbc, false);
201*4882a593Smuzhiyun
202*4882a593Smuzhiyun snd_soc_component_update_bits(component, WM8958_DSP2_PROGRAM,
203*4882a593Smuzhiyun WM8958_DSP2_ENA, WM8958_DSP2_ENA);
204*4882a593Smuzhiyun
205*4882a593Smuzhiyun /* If we've got user supplied MBC settings use them */
206*4882a593Smuzhiyun if (control->pdata.num_mbc_cfgs) {
207*4882a593Smuzhiyun struct wm8958_mbc_cfg *cfg
208*4882a593Smuzhiyun = &control->pdata.mbc_cfgs[wm8994->mbc_cfg];
209*4882a593Smuzhiyun
210*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(cfg->coeff_regs); i++)
211*4882a593Smuzhiyun snd_soc_component_write(component, i + WM8958_MBC_BAND_1_K_1,
212*4882a593Smuzhiyun cfg->coeff_regs[i]);
213*4882a593Smuzhiyun
214*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(cfg->cutoff_regs); i++)
215*4882a593Smuzhiyun snd_soc_component_write(component,
216*4882a593Smuzhiyun i + WM8958_MBC_BAND_2_LOWER_CUTOFF_C1_1,
217*4882a593Smuzhiyun cfg->cutoff_regs[i]);
218*4882a593Smuzhiyun }
219*4882a593Smuzhiyun
220*4882a593Smuzhiyun /* Run the DSP */
221*4882a593Smuzhiyun snd_soc_component_write(component, WM8958_DSP2_EXECCONTROL,
222*4882a593Smuzhiyun WM8958_DSP2_RUNR);
223*4882a593Smuzhiyun
224*4882a593Smuzhiyun /* And we're off! */
225*4882a593Smuzhiyun snd_soc_component_update_bits(component, WM8958_DSP2_CONFIG,
226*4882a593Smuzhiyun WM8958_MBC_ENA |
227*4882a593Smuzhiyun WM8958_MBC_SEL_MASK,
228*4882a593Smuzhiyun path << WM8958_MBC_SEL_SHIFT |
229*4882a593Smuzhiyun WM8958_MBC_ENA);
230*4882a593Smuzhiyun }
231*4882a593Smuzhiyun
wm8958_dsp_start_vss(struct snd_soc_component * component,int path)232*4882a593Smuzhiyun static void wm8958_dsp_start_vss(struct snd_soc_component *component, int path)
233*4882a593Smuzhiyun {
234*4882a593Smuzhiyun struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
235*4882a593Smuzhiyun struct wm8994 *control = wm8994->wm8994;
236*4882a593Smuzhiyun int i, ena;
237*4882a593Smuzhiyun
238*4882a593Smuzhiyun if (wm8994->mbc_vss)
239*4882a593Smuzhiyun wm8958_dsp2_fw(component, "MBC+VSS", wm8994->mbc_vss, false);
240*4882a593Smuzhiyun
241*4882a593Smuzhiyun snd_soc_component_update_bits(component, WM8958_DSP2_PROGRAM,
242*4882a593Smuzhiyun WM8958_DSP2_ENA, WM8958_DSP2_ENA);
243*4882a593Smuzhiyun
244*4882a593Smuzhiyun /* If we've got user supplied settings use them */
245*4882a593Smuzhiyun if (control->pdata.num_mbc_cfgs) {
246*4882a593Smuzhiyun struct wm8958_mbc_cfg *cfg
247*4882a593Smuzhiyun = &control->pdata.mbc_cfgs[wm8994->mbc_cfg];
248*4882a593Smuzhiyun
249*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(cfg->combined_regs); i++)
250*4882a593Smuzhiyun snd_soc_component_write(component, i + 0x2800,
251*4882a593Smuzhiyun cfg->combined_regs[i]);
252*4882a593Smuzhiyun }
253*4882a593Smuzhiyun
254*4882a593Smuzhiyun if (control->pdata.num_vss_cfgs) {
255*4882a593Smuzhiyun struct wm8958_vss_cfg *cfg
256*4882a593Smuzhiyun = &control->pdata.vss_cfgs[wm8994->vss_cfg];
257*4882a593Smuzhiyun
258*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(cfg->regs); i++)
259*4882a593Smuzhiyun snd_soc_component_write(component, i + 0x2600, cfg->regs[i]);
260*4882a593Smuzhiyun }
261*4882a593Smuzhiyun
262*4882a593Smuzhiyun if (control->pdata.num_vss_hpf_cfgs) {
263*4882a593Smuzhiyun struct wm8958_vss_hpf_cfg *cfg
264*4882a593Smuzhiyun = &control->pdata.vss_hpf_cfgs[wm8994->vss_hpf_cfg];
265*4882a593Smuzhiyun
266*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(cfg->regs); i++)
267*4882a593Smuzhiyun snd_soc_component_write(component, i + 0x2400, cfg->regs[i]);
268*4882a593Smuzhiyun }
269*4882a593Smuzhiyun
270*4882a593Smuzhiyun /* Run the DSP */
271*4882a593Smuzhiyun snd_soc_component_write(component, WM8958_DSP2_EXECCONTROL,
272*4882a593Smuzhiyun WM8958_DSP2_RUNR);
273*4882a593Smuzhiyun
274*4882a593Smuzhiyun /* Enable the algorithms we've selected */
275*4882a593Smuzhiyun ena = 0;
276*4882a593Smuzhiyun if (wm8994->mbc_ena[path])
277*4882a593Smuzhiyun ena |= 0x8;
278*4882a593Smuzhiyun if (wm8994->hpf2_ena[path])
279*4882a593Smuzhiyun ena |= 0x4;
280*4882a593Smuzhiyun if (wm8994->hpf1_ena[path])
281*4882a593Smuzhiyun ena |= 0x2;
282*4882a593Smuzhiyun if (wm8994->vss_ena[path])
283*4882a593Smuzhiyun ena |= 0x1;
284*4882a593Smuzhiyun
285*4882a593Smuzhiyun snd_soc_component_write(component, 0x2201, ena);
286*4882a593Smuzhiyun
287*4882a593Smuzhiyun /* Switch the DSP into the data path */
288*4882a593Smuzhiyun snd_soc_component_update_bits(component, WM8958_DSP2_CONFIG,
289*4882a593Smuzhiyun WM8958_MBC_SEL_MASK | WM8958_MBC_ENA,
290*4882a593Smuzhiyun path << WM8958_MBC_SEL_SHIFT | WM8958_MBC_ENA);
291*4882a593Smuzhiyun }
292*4882a593Smuzhiyun
wm8958_dsp_start_enh_eq(struct snd_soc_component * component,int path)293*4882a593Smuzhiyun static void wm8958_dsp_start_enh_eq(struct snd_soc_component *component, int path)
294*4882a593Smuzhiyun {
295*4882a593Smuzhiyun struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
296*4882a593Smuzhiyun struct wm8994 *control = wm8994->wm8994;
297*4882a593Smuzhiyun int i;
298*4882a593Smuzhiyun
299*4882a593Smuzhiyun wm8958_dsp2_fw(component, "ENH_EQ", wm8994->enh_eq, false);
300*4882a593Smuzhiyun
301*4882a593Smuzhiyun snd_soc_component_update_bits(component, WM8958_DSP2_PROGRAM,
302*4882a593Smuzhiyun WM8958_DSP2_ENA, WM8958_DSP2_ENA);
303*4882a593Smuzhiyun
304*4882a593Smuzhiyun /* If we've got user supplied settings use them */
305*4882a593Smuzhiyun if (control->pdata.num_enh_eq_cfgs) {
306*4882a593Smuzhiyun struct wm8958_enh_eq_cfg *cfg
307*4882a593Smuzhiyun = &control->pdata.enh_eq_cfgs[wm8994->enh_eq_cfg];
308*4882a593Smuzhiyun
309*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(cfg->regs); i++)
310*4882a593Smuzhiyun snd_soc_component_write(component, i + 0x2200,
311*4882a593Smuzhiyun cfg->regs[i]);
312*4882a593Smuzhiyun }
313*4882a593Smuzhiyun
314*4882a593Smuzhiyun /* Run the DSP */
315*4882a593Smuzhiyun snd_soc_component_write(component, WM8958_DSP2_EXECCONTROL,
316*4882a593Smuzhiyun WM8958_DSP2_RUNR);
317*4882a593Smuzhiyun
318*4882a593Smuzhiyun /* Switch the DSP into the data path */
319*4882a593Smuzhiyun snd_soc_component_update_bits(component, WM8958_DSP2_CONFIG,
320*4882a593Smuzhiyun WM8958_MBC_SEL_MASK | WM8958_MBC_ENA,
321*4882a593Smuzhiyun path << WM8958_MBC_SEL_SHIFT | WM8958_MBC_ENA);
322*4882a593Smuzhiyun }
323*4882a593Smuzhiyun
wm8958_dsp_apply(struct snd_soc_component * component,int path,int start)324*4882a593Smuzhiyun static void wm8958_dsp_apply(struct snd_soc_component *component, int path, int start)
325*4882a593Smuzhiyun {
326*4882a593Smuzhiyun struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
327*4882a593Smuzhiyun int pwr_reg = snd_soc_component_read(component, WM8994_POWER_MANAGEMENT_5);
328*4882a593Smuzhiyun int ena, reg, aif;
329*4882a593Smuzhiyun
330*4882a593Smuzhiyun switch (path) {
331*4882a593Smuzhiyun case 0:
332*4882a593Smuzhiyun pwr_reg &= (WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC1R_ENA);
333*4882a593Smuzhiyun aif = 0;
334*4882a593Smuzhiyun break;
335*4882a593Smuzhiyun case 1:
336*4882a593Smuzhiyun pwr_reg &= (WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA);
337*4882a593Smuzhiyun aif = 0;
338*4882a593Smuzhiyun break;
339*4882a593Smuzhiyun case 2:
340*4882a593Smuzhiyun pwr_reg &= (WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA);
341*4882a593Smuzhiyun aif = 1;
342*4882a593Smuzhiyun break;
343*4882a593Smuzhiyun default:
344*4882a593Smuzhiyun WARN(1, "Invalid path %d\n", path);
345*4882a593Smuzhiyun return;
346*4882a593Smuzhiyun }
347*4882a593Smuzhiyun
348*4882a593Smuzhiyun /* Do we have both an active AIF and an active algorithm? */
349*4882a593Smuzhiyun ena = wm8994->mbc_ena[path] || wm8994->vss_ena[path] ||
350*4882a593Smuzhiyun wm8994->hpf1_ena[path] || wm8994->hpf2_ena[path] ||
351*4882a593Smuzhiyun wm8994->enh_eq_ena[path];
352*4882a593Smuzhiyun if (!pwr_reg)
353*4882a593Smuzhiyun ena = 0;
354*4882a593Smuzhiyun
355*4882a593Smuzhiyun reg = snd_soc_component_read(component, WM8958_DSP2_PROGRAM);
356*4882a593Smuzhiyun
357*4882a593Smuzhiyun dev_dbg(component->dev, "DSP path %d %d startup: %d, power: %x, DSP: %x\n",
358*4882a593Smuzhiyun path, wm8994->dsp_active, start, pwr_reg, reg);
359*4882a593Smuzhiyun
360*4882a593Smuzhiyun if (start && ena) {
361*4882a593Smuzhiyun /* If the DSP is already running then noop */
362*4882a593Smuzhiyun if (reg & WM8958_DSP2_ENA)
363*4882a593Smuzhiyun return;
364*4882a593Smuzhiyun
365*4882a593Smuzhiyun /* If either AIFnCLK is not yet enabled postpone */
366*4882a593Smuzhiyun if (!(snd_soc_component_read(component, WM8994_AIF1_CLOCKING_1)
367*4882a593Smuzhiyun & WM8994_AIF1CLK_ENA_MASK) &&
368*4882a593Smuzhiyun !(snd_soc_component_read(component, WM8994_AIF2_CLOCKING_1)
369*4882a593Smuzhiyun & WM8994_AIF2CLK_ENA_MASK))
370*4882a593Smuzhiyun return;
371*4882a593Smuzhiyun
372*4882a593Smuzhiyun /* Switch the clock over to the appropriate AIF */
373*4882a593Smuzhiyun snd_soc_component_update_bits(component, WM8994_CLOCKING_1,
374*4882a593Smuzhiyun WM8958_DSP2CLK_SRC | WM8958_DSP2CLK_ENA,
375*4882a593Smuzhiyun aif << WM8958_DSP2CLK_SRC_SHIFT |
376*4882a593Smuzhiyun WM8958_DSP2CLK_ENA);
377*4882a593Smuzhiyun
378*4882a593Smuzhiyun if (wm8994->enh_eq_ena[path])
379*4882a593Smuzhiyun wm8958_dsp_start_enh_eq(component, path);
380*4882a593Smuzhiyun else if (wm8994->vss_ena[path] || wm8994->hpf1_ena[path] ||
381*4882a593Smuzhiyun wm8994->hpf2_ena[path])
382*4882a593Smuzhiyun wm8958_dsp_start_vss(component, path);
383*4882a593Smuzhiyun else if (wm8994->mbc_ena[path])
384*4882a593Smuzhiyun wm8958_dsp_start_mbc(component, path);
385*4882a593Smuzhiyun
386*4882a593Smuzhiyun wm8994->dsp_active = path;
387*4882a593Smuzhiyun
388*4882a593Smuzhiyun dev_dbg(component->dev, "DSP running in path %d\n", path);
389*4882a593Smuzhiyun }
390*4882a593Smuzhiyun
391*4882a593Smuzhiyun if (!start && wm8994->dsp_active == path) {
392*4882a593Smuzhiyun /* If the DSP is already stopped then noop */
393*4882a593Smuzhiyun if (!(reg & WM8958_DSP2_ENA))
394*4882a593Smuzhiyun return;
395*4882a593Smuzhiyun
396*4882a593Smuzhiyun snd_soc_component_update_bits(component, WM8958_DSP2_CONFIG,
397*4882a593Smuzhiyun WM8958_MBC_ENA, 0);
398*4882a593Smuzhiyun snd_soc_component_write(component, WM8958_DSP2_EXECCONTROL,
399*4882a593Smuzhiyun WM8958_DSP2_STOP);
400*4882a593Smuzhiyun snd_soc_component_update_bits(component, WM8958_DSP2_PROGRAM,
401*4882a593Smuzhiyun WM8958_DSP2_ENA, 0);
402*4882a593Smuzhiyun snd_soc_component_update_bits(component, WM8994_CLOCKING_1,
403*4882a593Smuzhiyun WM8958_DSP2CLK_ENA, 0);
404*4882a593Smuzhiyun
405*4882a593Smuzhiyun wm8994->dsp_active = -1;
406*4882a593Smuzhiyun
407*4882a593Smuzhiyun dev_dbg(component->dev, "DSP stopped\n");
408*4882a593Smuzhiyun }
409*4882a593Smuzhiyun }
410*4882a593Smuzhiyun
wm8958_aif_ev(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)411*4882a593Smuzhiyun int wm8958_aif_ev(struct snd_soc_dapm_widget *w,
412*4882a593Smuzhiyun struct snd_kcontrol *kcontrol, int event)
413*4882a593Smuzhiyun {
414*4882a593Smuzhiyun struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
415*4882a593Smuzhiyun struct wm8994 *control = dev_get_drvdata(component->dev->parent);
416*4882a593Smuzhiyun int i;
417*4882a593Smuzhiyun
418*4882a593Smuzhiyun if (control->type != WM8958)
419*4882a593Smuzhiyun return 0;
420*4882a593Smuzhiyun
421*4882a593Smuzhiyun switch (event) {
422*4882a593Smuzhiyun case SND_SOC_DAPM_POST_PMU:
423*4882a593Smuzhiyun case SND_SOC_DAPM_PRE_PMU:
424*4882a593Smuzhiyun for (i = 0; i < 3; i++)
425*4882a593Smuzhiyun wm8958_dsp_apply(component, i, 1);
426*4882a593Smuzhiyun break;
427*4882a593Smuzhiyun case SND_SOC_DAPM_POST_PMD:
428*4882a593Smuzhiyun case SND_SOC_DAPM_PRE_PMD:
429*4882a593Smuzhiyun for (i = 0; i < 3; i++)
430*4882a593Smuzhiyun wm8958_dsp_apply(component, i, 0);
431*4882a593Smuzhiyun break;
432*4882a593Smuzhiyun }
433*4882a593Smuzhiyun
434*4882a593Smuzhiyun return 0;
435*4882a593Smuzhiyun }
436*4882a593Smuzhiyun
437*4882a593Smuzhiyun /* Check if DSP2 is in use on another AIF */
wm8958_dsp2_busy(struct wm8994_priv * wm8994,int aif)438*4882a593Smuzhiyun static int wm8958_dsp2_busy(struct wm8994_priv *wm8994, int aif)
439*4882a593Smuzhiyun {
440*4882a593Smuzhiyun int i;
441*4882a593Smuzhiyun
442*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(wm8994->mbc_ena); i++) {
443*4882a593Smuzhiyun if (i == aif)
444*4882a593Smuzhiyun continue;
445*4882a593Smuzhiyun if (wm8994->mbc_ena[i] || wm8994->vss_ena[i] ||
446*4882a593Smuzhiyun wm8994->hpf1_ena[i] || wm8994->hpf2_ena[i])
447*4882a593Smuzhiyun return 1;
448*4882a593Smuzhiyun }
449*4882a593Smuzhiyun
450*4882a593Smuzhiyun return 0;
451*4882a593Smuzhiyun }
452*4882a593Smuzhiyun
wm8958_put_mbc_enum(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)453*4882a593Smuzhiyun static int wm8958_put_mbc_enum(struct snd_kcontrol *kcontrol,
454*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
455*4882a593Smuzhiyun {
456*4882a593Smuzhiyun struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
457*4882a593Smuzhiyun struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
458*4882a593Smuzhiyun struct wm8994 *control = wm8994->wm8994;
459*4882a593Smuzhiyun int value = ucontrol->value.enumerated.item[0];
460*4882a593Smuzhiyun int reg;
461*4882a593Smuzhiyun
462*4882a593Smuzhiyun /* Don't allow on the fly reconfiguration */
463*4882a593Smuzhiyun reg = snd_soc_component_read(component, WM8994_CLOCKING_1);
464*4882a593Smuzhiyun if (reg < 0 || reg & WM8958_DSP2CLK_ENA)
465*4882a593Smuzhiyun return -EBUSY;
466*4882a593Smuzhiyun
467*4882a593Smuzhiyun if (value >= control->pdata.num_mbc_cfgs)
468*4882a593Smuzhiyun return -EINVAL;
469*4882a593Smuzhiyun
470*4882a593Smuzhiyun wm8994->mbc_cfg = value;
471*4882a593Smuzhiyun
472*4882a593Smuzhiyun return 0;
473*4882a593Smuzhiyun }
474*4882a593Smuzhiyun
wm8958_get_mbc_enum(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)475*4882a593Smuzhiyun static int wm8958_get_mbc_enum(struct snd_kcontrol *kcontrol,
476*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
477*4882a593Smuzhiyun {
478*4882a593Smuzhiyun struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
479*4882a593Smuzhiyun struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
480*4882a593Smuzhiyun
481*4882a593Smuzhiyun ucontrol->value.enumerated.item[0] = wm8994->mbc_cfg;
482*4882a593Smuzhiyun
483*4882a593Smuzhiyun return 0;
484*4882a593Smuzhiyun }
485*4882a593Smuzhiyun
wm8958_mbc_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)486*4882a593Smuzhiyun static int wm8958_mbc_info(struct snd_kcontrol *kcontrol,
487*4882a593Smuzhiyun struct snd_ctl_elem_info *uinfo)
488*4882a593Smuzhiyun {
489*4882a593Smuzhiyun uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
490*4882a593Smuzhiyun uinfo->count = 1;
491*4882a593Smuzhiyun uinfo->value.integer.min = 0;
492*4882a593Smuzhiyun uinfo->value.integer.max = 1;
493*4882a593Smuzhiyun return 0;
494*4882a593Smuzhiyun }
495*4882a593Smuzhiyun
wm8958_mbc_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)496*4882a593Smuzhiyun static int wm8958_mbc_get(struct snd_kcontrol *kcontrol,
497*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
498*4882a593Smuzhiyun {
499*4882a593Smuzhiyun int mbc = kcontrol->private_value;
500*4882a593Smuzhiyun struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
501*4882a593Smuzhiyun struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
502*4882a593Smuzhiyun
503*4882a593Smuzhiyun ucontrol->value.integer.value[0] = wm8994->mbc_ena[mbc];
504*4882a593Smuzhiyun
505*4882a593Smuzhiyun return 0;
506*4882a593Smuzhiyun }
507*4882a593Smuzhiyun
wm8958_mbc_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)508*4882a593Smuzhiyun static int wm8958_mbc_put(struct snd_kcontrol *kcontrol,
509*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
510*4882a593Smuzhiyun {
511*4882a593Smuzhiyun int mbc = kcontrol->private_value;
512*4882a593Smuzhiyun struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
513*4882a593Smuzhiyun struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
514*4882a593Smuzhiyun
515*4882a593Smuzhiyun if (wm8994->mbc_ena[mbc] == ucontrol->value.integer.value[0])
516*4882a593Smuzhiyun return 0;
517*4882a593Smuzhiyun
518*4882a593Smuzhiyun if (ucontrol->value.integer.value[0] > 1)
519*4882a593Smuzhiyun return -EINVAL;
520*4882a593Smuzhiyun
521*4882a593Smuzhiyun if (wm8958_dsp2_busy(wm8994, mbc)) {
522*4882a593Smuzhiyun dev_dbg(component->dev, "DSP2 active on %d already\n", mbc);
523*4882a593Smuzhiyun return -EBUSY;
524*4882a593Smuzhiyun }
525*4882a593Smuzhiyun
526*4882a593Smuzhiyun if (wm8994->enh_eq_ena[mbc])
527*4882a593Smuzhiyun return -EBUSY;
528*4882a593Smuzhiyun
529*4882a593Smuzhiyun wm8994->mbc_ena[mbc] = ucontrol->value.integer.value[0];
530*4882a593Smuzhiyun
531*4882a593Smuzhiyun wm8958_dsp_apply(component, mbc, wm8994->mbc_ena[mbc]);
532*4882a593Smuzhiyun
533*4882a593Smuzhiyun return 1;
534*4882a593Smuzhiyun }
535*4882a593Smuzhiyun
536*4882a593Smuzhiyun #define WM8958_MBC_SWITCH(xname, xval) {\
537*4882a593Smuzhiyun .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
538*4882a593Smuzhiyun .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,\
539*4882a593Smuzhiyun .info = wm8958_mbc_info, \
540*4882a593Smuzhiyun .get = wm8958_mbc_get, .put = wm8958_mbc_put, \
541*4882a593Smuzhiyun .private_value = xval }
542*4882a593Smuzhiyun
wm8958_put_vss_enum(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)543*4882a593Smuzhiyun static int wm8958_put_vss_enum(struct snd_kcontrol *kcontrol,
544*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
545*4882a593Smuzhiyun {
546*4882a593Smuzhiyun struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
547*4882a593Smuzhiyun struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
548*4882a593Smuzhiyun struct wm8994 *control = wm8994->wm8994;
549*4882a593Smuzhiyun int value = ucontrol->value.enumerated.item[0];
550*4882a593Smuzhiyun int reg;
551*4882a593Smuzhiyun
552*4882a593Smuzhiyun /* Don't allow on the fly reconfiguration */
553*4882a593Smuzhiyun reg = snd_soc_component_read(component, WM8994_CLOCKING_1);
554*4882a593Smuzhiyun if (reg < 0 || reg & WM8958_DSP2CLK_ENA)
555*4882a593Smuzhiyun return -EBUSY;
556*4882a593Smuzhiyun
557*4882a593Smuzhiyun if (value >= control->pdata.num_vss_cfgs)
558*4882a593Smuzhiyun return -EINVAL;
559*4882a593Smuzhiyun
560*4882a593Smuzhiyun wm8994->vss_cfg = value;
561*4882a593Smuzhiyun
562*4882a593Smuzhiyun return 0;
563*4882a593Smuzhiyun }
564*4882a593Smuzhiyun
wm8958_get_vss_enum(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)565*4882a593Smuzhiyun static int wm8958_get_vss_enum(struct snd_kcontrol *kcontrol,
566*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
567*4882a593Smuzhiyun {
568*4882a593Smuzhiyun struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
569*4882a593Smuzhiyun struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
570*4882a593Smuzhiyun
571*4882a593Smuzhiyun ucontrol->value.enumerated.item[0] = wm8994->vss_cfg;
572*4882a593Smuzhiyun
573*4882a593Smuzhiyun return 0;
574*4882a593Smuzhiyun }
575*4882a593Smuzhiyun
wm8958_put_vss_hpf_enum(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)576*4882a593Smuzhiyun static int wm8958_put_vss_hpf_enum(struct snd_kcontrol *kcontrol,
577*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
578*4882a593Smuzhiyun {
579*4882a593Smuzhiyun struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
580*4882a593Smuzhiyun struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
581*4882a593Smuzhiyun struct wm8994 *control = wm8994->wm8994;
582*4882a593Smuzhiyun int value = ucontrol->value.enumerated.item[0];
583*4882a593Smuzhiyun int reg;
584*4882a593Smuzhiyun
585*4882a593Smuzhiyun /* Don't allow on the fly reconfiguration */
586*4882a593Smuzhiyun reg = snd_soc_component_read(component, WM8994_CLOCKING_1);
587*4882a593Smuzhiyun if (reg < 0 || reg & WM8958_DSP2CLK_ENA)
588*4882a593Smuzhiyun return -EBUSY;
589*4882a593Smuzhiyun
590*4882a593Smuzhiyun if (value >= control->pdata.num_vss_hpf_cfgs)
591*4882a593Smuzhiyun return -EINVAL;
592*4882a593Smuzhiyun
593*4882a593Smuzhiyun wm8994->vss_hpf_cfg = value;
594*4882a593Smuzhiyun
595*4882a593Smuzhiyun return 0;
596*4882a593Smuzhiyun }
597*4882a593Smuzhiyun
wm8958_get_vss_hpf_enum(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)598*4882a593Smuzhiyun static int wm8958_get_vss_hpf_enum(struct snd_kcontrol *kcontrol,
599*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
600*4882a593Smuzhiyun {
601*4882a593Smuzhiyun struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
602*4882a593Smuzhiyun struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
603*4882a593Smuzhiyun
604*4882a593Smuzhiyun ucontrol->value.enumerated.item[0] = wm8994->vss_hpf_cfg;
605*4882a593Smuzhiyun
606*4882a593Smuzhiyun return 0;
607*4882a593Smuzhiyun }
608*4882a593Smuzhiyun
wm8958_vss_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)609*4882a593Smuzhiyun static int wm8958_vss_info(struct snd_kcontrol *kcontrol,
610*4882a593Smuzhiyun struct snd_ctl_elem_info *uinfo)
611*4882a593Smuzhiyun {
612*4882a593Smuzhiyun uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
613*4882a593Smuzhiyun uinfo->count = 1;
614*4882a593Smuzhiyun uinfo->value.integer.min = 0;
615*4882a593Smuzhiyun uinfo->value.integer.max = 1;
616*4882a593Smuzhiyun return 0;
617*4882a593Smuzhiyun }
618*4882a593Smuzhiyun
wm8958_vss_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)619*4882a593Smuzhiyun static int wm8958_vss_get(struct snd_kcontrol *kcontrol,
620*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
621*4882a593Smuzhiyun {
622*4882a593Smuzhiyun int vss = kcontrol->private_value;
623*4882a593Smuzhiyun struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
624*4882a593Smuzhiyun struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
625*4882a593Smuzhiyun
626*4882a593Smuzhiyun ucontrol->value.integer.value[0] = wm8994->vss_ena[vss];
627*4882a593Smuzhiyun
628*4882a593Smuzhiyun return 0;
629*4882a593Smuzhiyun }
630*4882a593Smuzhiyun
wm8958_vss_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)631*4882a593Smuzhiyun static int wm8958_vss_put(struct snd_kcontrol *kcontrol,
632*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
633*4882a593Smuzhiyun {
634*4882a593Smuzhiyun int vss = kcontrol->private_value;
635*4882a593Smuzhiyun struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
636*4882a593Smuzhiyun struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
637*4882a593Smuzhiyun
638*4882a593Smuzhiyun if (wm8994->vss_ena[vss] == ucontrol->value.integer.value[0])
639*4882a593Smuzhiyun return 0;
640*4882a593Smuzhiyun
641*4882a593Smuzhiyun if (ucontrol->value.integer.value[0] > 1)
642*4882a593Smuzhiyun return -EINVAL;
643*4882a593Smuzhiyun
644*4882a593Smuzhiyun if (!wm8994->mbc_vss)
645*4882a593Smuzhiyun return -ENODEV;
646*4882a593Smuzhiyun
647*4882a593Smuzhiyun if (wm8958_dsp2_busy(wm8994, vss)) {
648*4882a593Smuzhiyun dev_dbg(component->dev, "DSP2 active on %d already\n", vss);
649*4882a593Smuzhiyun return -EBUSY;
650*4882a593Smuzhiyun }
651*4882a593Smuzhiyun
652*4882a593Smuzhiyun if (wm8994->enh_eq_ena[vss])
653*4882a593Smuzhiyun return -EBUSY;
654*4882a593Smuzhiyun
655*4882a593Smuzhiyun wm8994->vss_ena[vss] = ucontrol->value.integer.value[0];
656*4882a593Smuzhiyun
657*4882a593Smuzhiyun wm8958_dsp_apply(component, vss, wm8994->vss_ena[vss]);
658*4882a593Smuzhiyun
659*4882a593Smuzhiyun return 1;
660*4882a593Smuzhiyun }
661*4882a593Smuzhiyun
662*4882a593Smuzhiyun
663*4882a593Smuzhiyun #define WM8958_VSS_SWITCH(xname, xval) {\
664*4882a593Smuzhiyun .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
665*4882a593Smuzhiyun .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,\
666*4882a593Smuzhiyun .info = wm8958_vss_info, \
667*4882a593Smuzhiyun .get = wm8958_vss_get, .put = wm8958_vss_put, \
668*4882a593Smuzhiyun .private_value = xval }
669*4882a593Smuzhiyun
wm8958_hpf_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)670*4882a593Smuzhiyun static int wm8958_hpf_info(struct snd_kcontrol *kcontrol,
671*4882a593Smuzhiyun struct snd_ctl_elem_info *uinfo)
672*4882a593Smuzhiyun {
673*4882a593Smuzhiyun uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
674*4882a593Smuzhiyun uinfo->count = 1;
675*4882a593Smuzhiyun uinfo->value.integer.min = 0;
676*4882a593Smuzhiyun uinfo->value.integer.max = 1;
677*4882a593Smuzhiyun return 0;
678*4882a593Smuzhiyun }
679*4882a593Smuzhiyun
wm8958_hpf_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)680*4882a593Smuzhiyun static int wm8958_hpf_get(struct snd_kcontrol *kcontrol,
681*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
682*4882a593Smuzhiyun {
683*4882a593Smuzhiyun int hpf = kcontrol->private_value;
684*4882a593Smuzhiyun struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
685*4882a593Smuzhiyun struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
686*4882a593Smuzhiyun
687*4882a593Smuzhiyun if (hpf < 3)
688*4882a593Smuzhiyun ucontrol->value.integer.value[0] = wm8994->hpf1_ena[hpf % 3];
689*4882a593Smuzhiyun else
690*4882a593Smuzhiyun ucontrol->value.integer.value[0] = wm8994->hpf2_ena[hpf % 3];
691*4882a593Smuzhiyun
692*4882a593Smuzhiyun return 0;
693*4882a593Smuzhiyun }
694*4882a593Smuzhiyun
wm8958_hpf_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)695*4882a593Smuzhiyun static int wm8958_hpf_put(struct snd_kcontrol *kcontrol,
696*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
697*4882a593Smuzhiyun {
698*4882a593Smuzhiyun int hpf = kcontrol->private_value;
699*4882a593Smuzhiyun struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
700*4882a593Smuzhiyun struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
701*4882a593Smuzhiyun
702*4882a593Smuzhiyun if (hpf < 3) {
703*4882a593Smuzhiyun if (wm8994->hpf1_ena[hpf % 3] ==
704*4882a593Smuzhiyun ucontrol->value.integer.value[0])
705*4882a593Smuzhiyun return 0;
706*4882a593Smuzhiyun } else {
707*4882a593Smuzhiyun if (wm8994->hpf2_ena[hpf % 3] ==
708*4882a593Smuzhiyun ucontrol->value.integer.value[0])
709*4882a593Smuzhiyun return 0;
710*4882a593Smuzhiyun }
711*4882a593Smuzhiyun
712*4882a593Smuzhiyun if (ucontrol->value.integer.value[0] > 1)
713*4882a593Smuzhiyun return -EINVAL;
714*4882a593Smuzhiyun
715*4882a593Smuzhiyun if (!wm8994->mbc_vss)
716*4882a593Smuzhiyun return -ENODEV;
717*4882a593Smuzhiyun
718*4882a593Smuzhiyun if (wm8958_dsp2_busy(wm8994, hpf % 3)) {
719*4882a593Smuzhiyun dev_dbg(component->dev, "DSP2 active on %d already\n", hpf);
720*4882a593Smuzhiyun return -EBUSY;
721*4882a593Smuzhiyun }
722*4882a593Smuzhiyun
723*4882a593Smuzhiyun if (wm8994->enh_eq_ena[hpf % 3])
724*4882a593Smuzhiyun return -EBUSY;
725*4882a593Smuzhiyun
726*4882a593Smuzhiyun if (hpf < 3)
727*4882a593Smuzhiyun wm8994->hpf1_ena[hpf % 3] = ucontrol->value.integer.value[0];
728*4882a593Smuzhiyun else
729*4882a593Smuzhiyun wm8994->hpf2_ena[hpf % 3] = ucontrol->value.integer.value[0];
730*4882a593Smuzhiyun
731*4882a593Smuzhiyun wm8958_dsp_apply(component, hpf % 3, ucontrol->value.integer.value[0]);
732*4882a593Smuzhiyun
733*4882a593Smuzhiyun return 1;
734*4882a593Smuzhiyun }
735*4882a593Smuzhiyun
736*4882a593Smuzhiyun #define WM8958_HPF_SWITCH(xname, xval) {\
737*4882a593Smuzhiyun .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
738*4882a593Smuzhiyun .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,\
739*4882a593Smuzhiyun .info = wm8958_hpf_info, \
740*4882a593Smuzhiyun .get = wm8958_hpf_get, .put = wm8958_hpf_put, \
741*4882a593Smuzhiyun .private_value = xval }
742*4882a593Smuzhiyun
wm8958_put_enh_eq_enum(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)743*4882a593Smuzhiyun static int wm8958_put_enh_eq_enum(struct snd_kcontrol *kcontrol,
744*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
745*4882a593Smuzhiyun {
746*4882a593Smuzhiyun struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
747*4882a593Smuzhiyun struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
748*4882a593Smuzhiyun struct wm8994 *control = wm8994->wm8994;
749*4882a593Smuzhiyun int value = ucontrol->value.enumerated.item[0];
750*4882a593Smuzhiyun int reg;
751*4882a593Smuzhiyun
752*4882a593Smuzhiyun /* Don't allow on the fly reconfiguration */
753*4882a593Smuzhiyun reg = snd_soc_component_read(component, WM8994_CLOCKING_1);
754*4882a593Smuzhiyun if (reg < 0 || reg & WM8958_DSP2CLK_ENA)
755*4882a593Smuzhiyun return -EBUSY;
756*4882a593Smuzhiyun
757*4882a593Smuzhiyun if (value >= control->pdata.num_enh_eq_cfgs)
758*4882a593Smuzhiyun return -EINVAL;
759*4882a593Smuzhiyun
760*4882a593Smuzhiyun wm8994->enh_eq_cfg = value;
761*4882a593Smuzhiyun
762*4882a593Smuzhiyun return 0;
763*4882a593Smuzhiyun }
764*4882a593Smuzhiyun
wm8958_get_enh_eq_enum(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)765*4882a593Smuzhiyun static int wm8958_get_enh_eq_enum(struct snd_kcontrol *kcontrol,
766*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
767*4882a593Smuzhiyun {
768*4882a593Smuzhiyun struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
769*4882a593Smuzhiyun struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
770*4882a593Smuzhiyun
771*4882a593Smuzhiyun ucontrol->value.enumerated.item[0] = wm8994->enh_eq_cfg;
772*4882a593Smuzhiyun
773*4882a593Smuzhiyun return 0;
774*4882a593Smuzhiyun }
775*4882a593Smuzhiyun
wm8958_enh_eq_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)776*4882a593Smuzhiyun static int wm8958_enh_eq_info(struct snd_kcontrol *kcontrol,
777*4882a593Smuzhiyun struct snd_ctl_elem_info *uinfo)
778*4882a593Smuzhiyun {
779*4882a593Smuzhiyun uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
780*4882a593Smuzhiyun uinfo->count = 1;
781*4882a593Smuzhiyun uinfo->value.integer.min = 0;
782*4882a593Smuzhiyun uinfo->value.integer.max = 1;
783*4882a593Smuzhiyun return 0;
784*4882a593Smuzhiyun }
785*4882a593Smuzhiyun
wm8958_enh_eq_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)786*4882a593Smuzhiyun static int wm8958_enh_eq_get(struct snd_kcontrol *kcontrol,
787*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
788*4882a593Smuzhiyun {
789*4882a593Smuzhiyun int eq = kcontrol->private_value;
790*4882a593Smuzhiyun struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
791*4882a593Smuzhiyun struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
792*4882a593Smuzhiyun
793*4882a593Smuzhiyun ucontrol->value.integer.value[0] = wm8994->enh_eq_ena[eq];
794*4882a593Smuzhiyun
795*4882a593Smuzhiyun return 0;
796*4882a593Smuzhiyun }
797*4882a593Smuzhiyun
wm8958_enh_eq_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)798*4882a593Smuzhiyun static int wm8958_enh_eq_put(struct snd_kcontrol *kcontrol,
799*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
800*4882a593Smuzhiyun {
801*4882a593Smuzhiyun int eq = kcontrol->private_value;
802*4882a593Smuzhiyun struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
803*4882a593Smuzhiyun struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
804*4882a593Smuzhiyun
805*4882a593Smuzhiyun if (wm8994->enh_eq_ena[eq] == ucontrol->value.integer.value[0])
806*4882a593Smuzhiyun return 0;
807*4882a593Smuzhiyun
808*4882a593Smuzhiyun if (ucontrol->value.integer.value[0] > 1)
809*4882a593Smuzhiyun return -EINVAL;
810*4882a593Smuzhiyun
811*4882a593Smuzhiyun if (!wm8994->enh_eq)
812*4882a593Smuzhiyun return -ENODEV;
813*4882a593Smuzhiyun
814*4882a593Smuzhiyun if (wm8958_dsp2_busy(wm8994, eq)) {
815*4882a593Smuzhiyun dev_dbg(component->dev, "DSP2 active on %d already\n", eq);
816*4882a593Smuzhiyun return -EBUSY;
817*4882a593Smuzhiyun }
818*4882a593Smuzhiyun
819*4882a593Smuzhiyun if (wm8994->mbc_ena[eq] || wm8994->vss_ena[eq] ||
820*4882a593Smuzhiyun wm8994->hpf1_ena[eq] || wm8994->hpf2_ena[eq])
821*4882a593Smuzhiyun return -EBUSY;
822*4882a593Smuzhiyun
823*4882a593Smuzhiyun wm8994->enh_eq_ena[eq] = ucontrol->value.integer.value[0];
824*4882a593Smuzhiyun
825*4882a593Smuzhiyun wm8958_dsp_apply(component, eq, ucontrol->value.integer.value[0]);
826*4882a593Smuzhiyun
827*4882a593Smuzhiyun return 1;
828*4882a593Smuzhiyun }
829*4882a593Smuzhiyun
830*4882a593Smuzhiyun #define WM8958_ENH_EQ_SWITCH(xname, xval) {\
831*4882a593Smuzhiyun .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
832*4882a593Smuzhiyun .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,\
833*4882a593Smuzhiyun .info = wm8958_enh_eq_info, \
834*4882a593Smuzhiyun .get = wm8958_enh_eq_get, .put = wm8958_enh_eq_put, \
835*4882a593Smuzhiyun .private_value = xval }
836*4882a593Smuzhiyun
837*4882a593Smuzhiyun static const struct snd_kcontrol_new wm8958_mbc_snd_controls[] = {
838*4882a593Smuzhiyun WM8958_MBC_SWITCH("AIF1DAC1 MBC Switch", 0),
839*4882a593Smuzhiyun WM8958_MBC_SWITCH("AIF1DAC2 MBC Switch", 1),
840*4882a593Smuzhiyun WM8958_MBC_SWITCH("AIF2DAC MBC Switch", 2),
841*4882a593Smuzhiyun };
842*4882a593Smuzhiyun
843*4882a593Smuzhiyun static const struct snd_kcontrol_new wm8958_vss_snd_controls[] = {
844*4882a593Smuzhiyun WM8958_VSS_SWITCH("AIF1DAC1 VSS Switch", 0),
845*4882a593Smuzhiyun WM8958_VSS_SWITCH("AIF1DAC2 VSS Switch", 1),
846*4882a593Smuzhiyun WM8958_VSS_SWITCH("AIF2DAC VSS Switch", 2),
847*4882a593Smuzhiyun WM8958_HPF_SWITCH("AIF1DAC1 HPF1 Switch", 0),
848*4882a593Smuzhiyun WM8958_HPF_SWITCH("AIF1DAC2 HPF1 Switch", 1),
849*4882a593Smuzhiyun WM8958_HPF_SWITCH("AIF2DAC HPF1 Switch", 2),
850*4882a593Smuzhiyun WM8958_HPF_SWITCH("AIF1DAC1 HPF2 Switch", 3),
851*4882a593Smuzhiyun WM8958_HPF_SWITCH("AIF1DAC2 HPF2 Switch", 4),
852*4882a593Smuzhiyun WM8958_HPF_SWITCH("AIF2DAC HPF2 Switch", 5),
853*4882a593Smuzhiyun };
854*4882a593Smuzhiyun
855*4882a593Smuzhiyun static const struct snd_kcontrol_new wm8958_enh_eq_snd_controls[] = {
856*4882a593Smuzhiyun WM8958_ENH_EQ_SWITCH("AIF1DAC1 Enhanced EQ Switch", 0),
857*4882a593Smuzhiyun WM8958_ENH_EQ_SWITCH("AIF1DAC2 Enhanced EQ Switch", 1),
858*4882a593Smuzhiyun WM8958_ENH_EQ_SWITCH("AIF2DAC Enhanced EQ Switch", 2),
859*4882a593Smuzhiyun };
860*4882a593Smuzhiyun
wm8958_enh_eq_loaded(const struct firmware * fw,void * context)861*4882a593Smuzhiyun static void wm8958_enh_eq_loaded(const struct firmware *fw, void *context)
862*4882a593Smuzhiyun {
863*4882a593Smuzhiyun struct snd_soc_component *component = context;
864*4882a593Smuzhiyun struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
865*4882a593Smuzhiyun
866*4882a593Smuzhiyun if (fw && (wm8958_dsp2_fw(component, "ENH_EQ", fw, true) == 0)) {
867*4882a593Smuzhiyun mutex_lock(&wm8994->fw_lock);
868*4882a593Smuzhiyun wm8994->enh_eq = fw;
869*4882a593Smuzhiyun mutex_unlock(&wm8994->fw_lock);
870*4882a593Smuzhiyun }
871*4882a593Smuzhiyun }
872*4882a593Smuzhiyun
wm8958_mbc_vss_loaded(const struct firmware * fw,void * context)873*4882a593Smuzhiyun static void wm8958_mbc_vss_loaded(const struct firmware *fw, void *context)
874*4882a593Smuzhiyun {
875*4882a593Smuzhiyun struct snd_soc_component *component = context;
876*4882a593Smuzhiyun struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
877*4882a593Smuzhiyun
878*4882a593Smuzhiyun if (fw && (wm8958_dsp2_fw(component, "MBC+VSS", fw, true) == 0)) {
879*4882a593Smuzhiyun mutex_lock(&wm8994->fw_lock);
880*4882a593Smuzhiyun wm8994->mbc_vss = fw;
881*4882a593Smuzhiyun mutex_unlock(&wm8994->fw_lock);
882*4882a593Smuzhiyun }
883*4882a593Smuzhiyun }
884*4882a593Smuzhiyun
wm8958_mbc_loaded(const struct firmware * fw,void * context)885*4882a593Smuzhiyun static void wm8958_mbc_loaded(const struct firmware *fw, void *context)
886*4882a593Smuzhiyun {
887*4882a593Smuzhiyun struct snd_soc_component *component = context;
888*4882a593Smuzhiyun struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
889*4882a593Smuzhiyun
890*4882a593Smuzhiyun if (fw && (wm8958_dsp2_fw(component, "MBC", fw, true) == 0)) {
891*4882a593Smuzhiyun mutex_lock(&wm8994->fw_lock);
892*4882a593Smuzhiyun wm8994->mbc = fw;
893*4882a593Smuzhiyun mutex_unlock(&wm8994->fw_lock);
894*4882a593Smuzhiyun }
895*4882a593Smuzhiyun }
896*4882a593Smuzhiyun
wm8958_dsp2_init(struct snd_soc_component * component)897*4882a593Smuzhiyun void wm8958_dsp2_init(struct snd_soc_component *component)
898*4882a593Smuzhiyun {
899*4882a593Smuzhiyun struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
900*4882a593Smuzhiyun struct wm8994 *control = wm8994->wm8994;
901*4882a593Smuzhiyun struct wm8994_pdata *pdata = &control->pdata;
902*4882a593Smuzhiyun int ret, i;
903*4882a593Smuzhiyun
904*4882a593Smuzhiyun wm8994->dsp_active = -1;
905*4882a593Smuzhiyun
906*4882a593Smuzhiyun snd_soc_add_component_controls(component, wm8958_mbc_snd_controls,
907*4882a593Smuzhiyun ARRAY_SIZE(wm8958_mbc_snd_controls));
908*4882a593Smuzhiyun snd_soc_add_component_controls(component, wm8958_vss_snd_controls,
909*4882a593Smuzhiyun ARRAY_SIZE(wm8958_vss_snd_controls));
910*4882a593Smuzhiyun snd_soc_add_component_controls(component, wm8958_enh_eq_snd_controls,
911*4882a593Smuzhiyun ARRAY_SIZE(wm8958_enh_eq_snd_controls));
912*4882a593Smuzhiyun
913*4882a593Smuzhiyun
914*4882a593Smuzhiyun /* We don't *require* firmware and don't want to delay boot */
915*4882a593Smuzhiyun request_firmware_nowait(THIS_MODULE, FW_ACTION_HOTPLUG,
916*4882a593Smuzhiyun "wm8958_mbc.wfw", component->dev, GFP_KERNEL,
917*4882a593Smuzhiyun component, wm8958_mbc_loaded);
918*4882a593Smuzhiyun request_firmware_nowait(THIS_MODULE, FW_ACTION_HOTPLUG,
919*4882a593Smuzhiyun "wm8958_mbc_vss.wfw", component->dev, GFP_KERNEL,
920*4882a593Smuzhiyun component, wm8958_mbc_vss_loaded);
921*4882a593Smuzhiyun request_firmware_nowait(THIS_MODULE, FW_ACTION_HOTPLUG,
922*4882a593Smuzhiyun "wm8958_enh_eq.wfw", component->dev, GFP_KERNEL,
923*4882a593Smuzhiyun component, wm8958_enh_eq_loaded);
924*4882a593Smuzhiyun
925*4882a593Smuzhiyun if (pdata->num_mbc_cfgs) {
926*4882a593Smuzhiyun struct snd_kcontrol_new control[] = {
927*4882a593Smuzhiyun SOC_ENUM_EXT("MBC Mode", wm8994->mbc_enum,
928*4882a593Smuzhiyun wm8958_get_mbc_enum, wm8958_put_mbc_enum),
929*4882a593Smuzhiyun };
930*4882a593Smuzhiyun
931*4882a593Smuzhiyun /* We need an array of texts for the enum API */
932*4882a593Smuzhiyun wm8994->mbc_texts = kmalloc_array(pdata->num_mbc_cfgs,
933*4882a593Smuzhiyun sizeof(char *),
934*4882a593Smuzhiyun GFP_KERNEL);
935*4882a593Smuzhiyun if (!wm8994->mbc_texts)
936*4882a593Smuzhiyun return;
937*4882a593Smuzhiyun
938*4882a593Smuzhiyun for (i = 0; i < pdata->num_mbc_cfgs; i++)
939*4882a593Smuzhiyun wm8994->mbc_texts[i] = pdata->mbc_cfgs[i].name;
940*4882a593Smuzhiyun
941*4882a593Smuzhiyun wm8994->mbc_enum.items = pdata->num_mbc_cfgs;
942*4882a593Smuzhiyun wm8994->mbc_enum.texts = wm8994->mbc_texts;
943*4882a593Smuzhiyun
944*4882a593Smuzhiyun ret = snd_soc_add_component_controls(wm8994->hubs.component,
945*4882a593Smuzhiyun control, 1);
946*4882a593Smuzhiyun if (ret != 0)
947*4882a593Smuzhiyun dev_err(wm8994->hubs.component->dev,
948*4882a593Smuzhiyun "Failed to add MBC mode controls: %d\n", ret);
949*4882a593Smuzhiyun }
950*4882a593Smuzhiyun
951*4882a593Smuzhiyun if (pdata->num_vss_cfgs) {
952*4882a593Smuzhiyun struct snd_kcontrol_new control[] = {
953*4882a593Smuzhiyun SOC_ENUM_EXT("VSS Mode", wm8994->vss_enum,
954*4882a593Smuzhiyun wm8958_get_vss_enum, wm8958_put_vss_enum),
955*4882a593Smuzhiyun };
956*4882a593Smuzhiyun
957*4882a593Smuzhiyun /* We need an array of texts for the enum API */
958*4882a593Smuzhiyun wm8994->vss_texts = kmalloc_array(pdata->num_vss_cfgs,
959*4882a593Smuzhiyun sizeof(char *),
960*4882a593Smuzhiyun GFP_KERNEL);
961*4882a593Smuzhiyun if (!wm8994->vss_texts)
962*4882a593Smuzhiyun return;
963*4882a593Smuzhiyun
964*4882a593Smuzhiyun for (i = 0; i < pdata->num_vss_cfgs; i++)
965*4882a593Smuzhiyun wm8994->vss_texts[i] = pdata->vss_cfgs[i].name;
966*4882a593Smuzhiyun
967*4882a593Smuzhiyun wm8994->vss_enum.items = pdata->num_vss_cfgs;
968*4882a593Smuzhiyun wm8994->vss_enum.texts = wm8994->vss_texts;
969*4882a593Smuzhiyun
970*4882a593Smuzhiyun ret = snd_soc_add_component_controls(wm8994->hubs.component,
971*4882a593Smuzhiyun control, 1);
972*4882a593Smuzhiyun if (ret != 0)
973*4882a593Smuzhiyun dev_err(wm8994->hubs.component->dev,
974*4882a593Smuzhiyun "Failed to add VSS mode controls: %d\n", ret);
975*4882a593Smuzhiyun }
976*4882a593Smuzhiyun
977*4882a593Smuzhiyun if (pdata->num_vss_hpf_cfgs) {
978*4882a593Smuzhiyun struct snd_kcontrol_new control[] = {
979*4882a593Smuzhiyun SOC_ENUM_EXT("VSS HPF Mode", wm8994->vss_hpf_enum,
980*4882a593Smuzhiyun wm8958_get_vss_hpf_enum,
981*4882a593Smuzhiyun wm8958_put_vss_hpf_enum),
982*4882a593Smuzhiyun };
983*4882a593Smuzhiyun
984*4882a593Smuzhiyun /* We need an array of texts for the enum API */
985*4882a593Smuzhiyun wm8994->vss_hpf_texts = kmalloc_array(pdata->num_vss_hpf_cfgs,
986*4882a593Smuzhiyun sizeof(char *),
987*4882a593Smuzhiyun GFP_KERNEL);
988*4882a593Smuzhiyun if (!wm8994->vss_hpf_texts)
989*4882a593Smuzhiyun return;
990*4882a593Smuzhiyun
991*4882a593Smuzhiyun for (i = 0; i < pdata->num_vss_hpf_cfgs; i++)
992*4882a593Smuzhiyun wm8994->vss_hpf_texts[i] = pdata->vss_hpf_cfgs[i].name;
993*4882a593Smuzhiyun
994*4882a593Smuzhiyun wm8994->vss_hpf_enum.items = pdata->num_vss_hpf_cfgs;
995*4882a593Smuzhiyun wm8994->vss_hpf_enum.texts = wm8994->vss_hpf_texts;
996*4882a593Smuzhiyun
997*4882a593Smuzhiyun ret = snd_soc_add_component_controls(wm8994->hubs.component,
998*4882a593Smuzhiyun control, 1);
999*4882a593Smuzhiyun if (ret != 0)
1000*4882a593Smuzhiyun dev_err(wm8994->hubs.component->dev,
1001*4882a593Smuzhiyun "Failed to add VSS HPFmode controls: %d\n",
1002*4882a593Smuzhiyun ret);
1003*4882a593Smuzhiyun }
1004*4882a593Smuzhiyun
1005*4882a593Smuzhiyun if (pdata->num_enh_eq_cfgs) {
1006*4882a593Smuzhiyun struct snd_kcontrol_new control[] = {
1007*4882a593Smuzhiyun SOC_ENUM_EXT("Enhanced EQ Mode", wm8994->enh_eq_enum,
1008*4882a593Smuzhiyun wm8958_get_enh_eq_enum,
1009*4882a593Smuzhiyun wm8958_put_enh_eq_enum),
1010*4882a593Smuzhiyun };
1011*4882a593Smuzhiyun
1012*4882a593Smuzhiyun /* We need an array of texts for the enum API */
1013*4882a593Smuzhiyun wm8994->enh_eq_texts = kmalloc_array(pdata->num_enh_eq_cfgs,
1014*4882a593Smuzhiyun sizeof(char *),
1015*4882a593Smuzhiyun GFP_KERNEL);
1016*4882a593Smuzhiyun if (!wm8994->enh_eq_texts)
1017*4882a593Smuzhiyun return;
1018*4882a593Smuzhiyun
1019*4882a593Smuzhiyun for (i = 0; i < pdata->num_enh_eq_cfgs; i++)
1020*4882a593Smuzhiyun wm8994->enh_eq_texts[i] = pdata->enh_eq_cfgs[i].name;
1021*4882a593Smuzhiyun
1022*4882a593Smuzhiyun wm8994->enh_eq_enum.items = pdata->num_enh_eq_cfgs;
1023*4882a593Smuzhiyun wm8994->enh_eq_enum.texts = wm8994->enh_eq_texts;
1024*4882a593Smuzhiyun
1025*4882a593Smuzhiyun ret = snd_soc_add_component_controls(wm8994->hubs.component,
1026*4882a593Smuzhiyun control, 1);
1027*4882a593Smuzhiyun if (ret != 0)
1028*4882a593Smuzhiyun dev_err(wm8994->hubs.component->dev,
1029*4882a593Smuzhiyun "Failed to add enhanced EQ controls: %d\n",
1030*4882a593Smuzhiyun ret);
1031*4882a593Smuzhiyun }
1032*4882a593Smuzhiyun }
1033