1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * wm8955.h -- WM8904 ASoC driver 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright 2009 Wolfson Microelectronics, plc 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef _WM8955_H 11*4882a593Smuzhiyun #define _WM8955_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define WM8955_CLK_MCLK 1 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /* 16*4882a593Smuzhiyun * Register values. 17*4882a593Smuzhiyun */ 18*4882a593Smuzhiyun #define WM8955_LOUT1_VOLUME 0x02 19*4882a593Smuzhiyun #define WM8955_ROUT1_VOLUME 0x03 20*4882a593Smuzhiyun #define WM8955_DAC_CONTROL 0x05 21*4882a593Smuzhiyun #define WM8955_AUDIO_INTERFACE 0x07 22*4882a593Smuzhiyun #define WM8955_SAMPLE_RATE 0x08 23*4882a593Smuzhiyun #define WM8955_LEFT_DAC_VOLUME 0x0A 24*4882a593Smuzhiyun #define WM8955_RIGHT_DAC_VOLUME 0x0B 25*4882a593Smuzhiyun #define WM8955_BASS_CONTROL 0x0C 26*4882a593Smuzhiyun #define WM8955_TREBLE_CONTROL 0x0D 27*4882a593Smuzhiyun #define WM8955_RESET 0x0F 28*4882a593Smuzhiyun #define WM8955_ADDITIONAL_CONTROL_1 0x17 29*4882a593Smuzhiyun #define WM8955_ADDITIONAL_CONTROL_2 0x18 30*4882a593Smuzhiyun #define WM8955_POWER_MANAGEMENT_1 0x19 31*4882a593Smuzhiyun #define WM8955_POWER_MANAGEMENT_2 0x1A 32*4882a593Smuzhiyun #define WM8955_ADDITIONAL_CONTROL_3 0x1B 33*4882a593Smuzhiyun #define WM8955_LEFT_OUT_MIX_1 0x22 34*4882a593Smuzhiyun #define WM8955_LEFT_OUT_MIX_2 0x23 35*4882a593Smuzhiyun #define WM8955_RIGHT_OUT_MIX_1 0x24 36*4882a593Smuzhiyun #define WM8955_RIGHT_OUT_MIX_2 0x25 37*4882a593Smuzhiyun #define WM8955_MONO_OUT_MIX_1 0x26 38*4882a593Smuzhiyun #define WM8955_MONO_OUT_MIX_2 0x27 39*4882a593Smuzhiyun #define WM8955_LOUT2_VOLUME 0x28 40*4882a593Smuzhiyun #define WM8955_ROUT2_VOLUME 0x29 41*4882a593Smuzhiyun #define WM8955_MONOOUT_VOLUME 0x2A 42*4882a593Smuzhiyun #define WM8955_CLOCKING_PLL 0x2B 43*4882a593Smuzhiyun #define WM8955_PLL_CONTROL_1 0x2C 44*4882a593Smuzhiyun #define WM8955_PLL_CONTROL_2 0x2D 45*4882a593Smuzhiyun #define WM8955_PLL_CONTROL_3 0x2E 46*4882a593Smuzhiyun #define WM8955_PLL_CONTROL_4 0x3B 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun #define WM8955_REGISTER_COUNT 29 49*4882a593Smuzhiyun #define WM8955_MAX_REGISTER 0x3B 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun /* 52*4882a593Smuzhiyun * Field Definitions. 53*4882a593Smuzhiyun */ 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun /* 56*4882a593Smuzhiyun * R2 (0x02) - LOUT1 volume 57*4882a593Smuzhiyun */ 58*4882a593Smuzhiyun #define WM8955_LO1VU 0x0100 /* LO1VU */ 59*4882a593Smuzhiyun #define WM8955_LO1VU_MASK 0x0100 /* LO1VU */ 60*4882a593Smuzhiyun #define WM8955_LO1VU_SHIFT 8 /* LO1VU */ 61*4882a593Smuzhiyun #define WM8955_LO1VU_WIDTH 1 /* LO1VU */ 62*4882a593Smuzhiyun #define WM8955_LO1ZC 0x0080 /* LO1ZC */ 63*4882a593Smuzhiyun #define WM8955_LO1ZC_MASK 0x0080 /* LO1ZC */ 64*4882a593Smuzhiyun #define WM8955_LO1ZC_SHIFT 7 /* LO1ZC */ 65*4882a593Smuzhiyun #define WM8955_LO1ZC_WIDTH 1 /* LO1ZC */ 66*4882a593Smuzhiyun #define WM8955_LOUTVOL_MASK 0x007F /* LOUTVOL - [6:0] */ 67*4882a593Smuzhiyun #define WM8955_LOUTVOL_SHIFT 0 /* LOUTVOL - [6:0] */ 68*4882a593Smuzhiyun #define WM8955_LOUTVOL_WIDTH 7 /* LOUTVOL - [6:0] */ 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun /* 71*4882a593Smuzhiyun * R3 (0x03) - ROUT1 volume 72*4882a593Smuzhiyun */ 73*4882a593Smuzhiyun #define WM8955_RO1VU 0x0100 /* RO1VU */ 74*4882a593Smuzhiyun #define WM8955_RO1VU_MASK 0x0100 /* RO1VU */ 75*4882a593Smuzhiyun #define WM8955_RO1VU_SHIFT 8 /* RO1VU */ 76*4882a593Smuzhiyun #define WM8955_RO1VU_WIDTH 1 /* RO1VU */ 77*4882a593Smuzhiyun #define WM8955_RO1ZC 0x0080 /* RO1ZC */ 78*4882a593Smuzhiyun #define WM8955_RO1ZC_MASK 0x0080 /* RO1ZC */ 79*4882a593Smuzhiyun #define WM8955_RO1ZC_SHIFT 7 /* RO1ZC */ 80*4882a593Smuzhiyun #define WM8955_RO1ZC_WIDTH 1 /* RO1ZC */ 81*4882a593Smuzhiyun #define WM8955_ROUTVOL_MASK 0x007F /* ROUTVOL - [6:0] */ 82*4882a593Smuzhiyun #define WM8955_ROUTVOL_SHIFT 0 /* ROUTVOL - [6:0] */ 83*4882a593Smuzhiyun #define WM8955_ROUTVOL_WIDTH 7 /* ROUTVOL - [6:0] */ 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun /* 86*4882a593Smuzhiyun * R5 (0x05) - DAC Control 87*4882a593Smuzhiyun */ 88*4882a593Smuzhiyun #define WM8955_DAT 0x0080 /* DAT */ 89*4882a593Smuzhiyun #define WM8955_DAT_MASK 0x0080 /* DAT */ 90*4882a593Smuzhiyun #define WM8955_DAT_SHIFT 7 /* DAT */ 91*4882a593Smuzhiyun #define WM8955_DAT_WIDTH 1 /* DAT */ 92*4882a593Smuzhiyun #define WM8955_DACMU 0x0008 /* DACMU */ 93*4882a593Smuzhiyun #define WM8955_DACMU_MASK 0x0008 /* DACMU */ 94*4882a593Smuzhiyun #define WM8955_DACMU_SHIFT 3 /* DACMU */ 95*4882a593Smuzhiyun #define WM8955_DACMU_WIDTH 1 /* DACMU */ 96*4882a593Smuzhiyun #define WM8955_DEEMPH_MASK 0x0006 /* DEEMPH - [2:1] */ 97*4882a593Smuzhiyun #define WM8955_DEEMPH_SHIFT 1 /* DEEMPH - [2:1] */ 98*4882a593Smuzhiyun #define WM8955_DEEMPH_WIDTH 2 /* DEEMPH - [2:1] */ 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun /* 101*4882a593Smuzhiyun * R7 (0x07) - Audio Interface 102*4882a593Smuzhiyun */ 103*4882a593Smuzhiyun #define WM8955_BCLKINV 0x0080 /* BCLKINV */ 104*4882a593Smuzhiyun #define WM8955_BCLKINV_MASK 0x0080 /* BCLKINV */ 105*4882a593Smuzhiyun #define WM8955_BCLKINV_SHIFT 7 /* BCLKINV */ 106*4882a593Smuzhiyun #define WM8955_BCLKINV_WIDTH 1 /* BCLKINV */ 107*4882a593Smuzhiyun #define WM8955_MS 0x0040 /* MS */ 108*4882a593Smuzhiyun #define WM8955_MS_MASK 0x0040 /* MS */ 109*4882a593Smuzhiyun #define WM8955_MS_SHIFT 6 /* MS */ 110*4882a593Smuzhiyun #define WM8955_MS_WIDTH 1 /* MS */ 111*4882a593Smuzhiyun #define WM8955_LRSWAP 0x0020 /* LRSWAP */ 112*4882a593Smuzhiyun #define WM8955_LRSWAP_MASK 0x0020 /* LRSWAP */ 113*4882a593Smuzhiyun #define WM8955_LRSWAP_SHIFT 5 /* LRSWAP */ 114*4882a593Smuzhiyun #define WM8955_LRSWAP_WIDTH 1 /* LRSWAP */ 115*4882a593Smuzhiyun #define WM8955_LRP 0x0010 /* LRP */ 116*4882a593Smuzhiyun #define WM8955_LRP_MASK 0x0010 /* LRP */ 117*4882a593Smuzhiyun #define WM8955_LRP_SHIFT 4 /* LRP */ 118*4882a593Smuzhiyun #define WM8955_LRP_WIDTH 1 /* LRP */ 119*4882a593Smuzhiyun #define WM8955_WL_MASK 0x000C /* WL - [3:2] */ 120*4882a593Smuzhiyun #define WM8955_WL_SHIFT 2 /* WL - [3:2] */ 121*4882a593Smuzhiyun #define WM8955_WL_WIDTH 2 /* WL - [3:2] */ 122*4882a593Smuzhiyun #define WM8955_FORMAT_MASK 0x0003 /* FORMAT - [1:0] */ 123*4882a593Smuzhiyun #define WM8955_FORMAT_SHIFT 0 /* FORMAT - [1:0] */ 124*4882a593Smuzhiyun #define WM8955_FORMAT_WIDTH 2 /* FORMAT - [1:0] */ 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun /* 127*4882a593Smuzhiyun * R8 (0x08) - Sample Rate 128*4882a593Smuzhiyun */ 129*4882a593Smuzhiyun #define WM8955_BCLKDIV2 0x0080 /* BCLKDIV2 */ 130*4882a593Smuzhiyun #define WM8955_BCLKDIV2_MASK 0x0080 /* BCLKDIV2 */ 131*4882a593Smuzhiyun #define WM8955_BCLKDIV2_SHIFT 7 /* BCLKDIV2 */ 132*4882a593Smuzhiyun #define WM8955_BCLKDIV2_WIDTH 1 /* BCLKDIV2 */ 133*4882a593Smuzhiyun #define WM8955_MCLKDIV2 0x0040 /* MCLKDIV2 */ 134*4882a593Smuzhiyun #define WM8955_MCLKDIV2_MASK 0x0040 /* MCLKDIV2 */ 135*4882a593Smuzhiyun #define WM8955_MCLKDIV2_SHIFT 6 /* MCLKDIV2 */ 136*4882a593Smuzhiyun #define WM8955_MCLKDIV2_WIDTH 1 /* MCLKDIV2 */ 137*4882a593Smuzhiyun #define WM8955_SR_MASK 0x003E /* SR - [5:1] */ 138*4882a593Smuzhiyun #define WM8955_SR_SHIFT 1 /* SR - [5:1] */ 139*4882a593Smuzhiyun #define WM8955_SR_WIDTH 5 /* SR - [5:1] */ 140*4882a593Smuzhiyun #define WM8955_USB 0x0001 /* USB */ 141*4882a593Smuzhiyun #define WM8955_USB_MASK 0x0001 /* USB */ 142*4882a593Smuzhiyun #define WM8955_USB_SHIFT 0 /* USB */ 143*4882a593Smuzhiyun #define WM8955_USB_WIDTH 1 /* USB */ 144*4882a593Smuzhiyun 145*4882a593Smuzhiyun /* 146*4882a593Smuzhiyun * R10 (0x0A) - Left DAC volume 147*4882a593Smuzhiyun */ 148*4882a593Smuzhiyun #define WM8955_LDVU 0x0100 /* LDVU */ 149*4882a593Smuzhiyun #define WM8955_LDVU_MASK 0x0100 /* LDVU */ 150*4882a593Smuzhiyun #define WM8955_LDVU_SHIFT 8 /* LDVU */ 151*4882a593Smuzhiyun #define WM8955_LDVU_WIDTH 1 /* LDVU */ 152*4882a593Smuzhiyun #define WM8955_LDACVOL_MASK 0x00FF /* LDACVOL - [7:0] */ 153*4882a593Smuzhiyun #define WM8955_LDACVOL_SHIFT 0 /* LDACVOL - [7:0] */ 154*4882a593Smuzhiyun #define WM8955_LDACVOL_WIDTH 8 /* LDACVOL - [7:0] */ 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun /* 157*4882a593Smuzhiyun * R11 (0x0B) - Right DAC volume 158*4882a593Smuzhiyun */ 159*4882a593Smuzhiyun #define WM8955_RDVU 0x0100 /* RDVU */ 160*4882a593Smuzhiyun #define WM8955_RDVU_MASK 0x0100 /* RDVU */ 161*4882a593Smuzhiyun #define WM8955_RDVU_SHIFT 8 /* RDVU */ 162*4882a593Smuzhiyun #define WM8955_RDVU_WIDTH 1 /* RDVU */ 163*4882a593Smuzhiyun #define WM8955_RDACVOL_MASK 0x00FF /* RDACVOL - [7:0] */ 164*4882a593Smuzhiyun #define WM8955_RDACVOL_SHIFT 0 /* RDACVOL - [7:0] */ 165*4882a593Smuzhiyun #define WM8955_RDACVOL_WIDTH 8 /* RDACVOL - [7:0] */ 166*4882a593Smuzhiyun 167*4882a593Smuzhiyun /* 168*4882a593Smuzhiyun * R12 (0x0C) - Bass control 169*4882a593Smuzhiyun */ 170*4882a593Smuzhiyun #define WM8955_BB 0x0080 /* BB */ 171*4882a593Smuzhiyun #define WM8955_BB_MASK 0x0080 /* BB */ 172*4882a593Smuzhiyun #define WM8955_BB_SHIFT 7 /* BB */ 173*4882a593Smuzhiyun #define WM8955_BB_WIDTH 1 /* BB */ 174*4882a593Smuzhiyun #define WM8955_BC 0x0040 /* BC */ 175*4882a593Smuzhiyun #define WM8955_BC_MASK 0x0040 /* BC */ 176*4882a593Smuzhiyun #define WM8955_BC_SHIFT 6 /* BC */ 177*4882a593Smuzhiyun #define WM8955_BC_WIDTH 1 /* BC */ 178*4882a593Smuzhiyun #define WM8955_BASS_MASK 0x000F /* BASS - [3:0] */ 179*4882a593Smuzhiyun #define WM8955_BASS_SHIFT 0 /* BASS - [3:0] */ 180*4882a593Smuzhiyun #define WM8955_BASS_WIDTH 4 /* BASS - [3:0] */ 181*4882a593Smuzhiyun 182*4882a593Smuzhiyun /* 183*4882a593Smuzhiyun * R13 (0x0D) - Treble control 184*4882a593Smuzhiyun */ 185*4882a593Smuzhiyun #define WM8955_TC 0x0040 /* TC */ 186*4882a593Smuzhiyun #define WM8955_TC_MASK 0x0040 /* TC */ 187*4882a593Smuzhiyun #define WM8955_TC_SHIFT 6 /* TC */ 188*4882a593Smuzhiyun #define WM8955_TC_WIDTH 1 /* TC */ 189*4882a593Smuzhiyun #define WM8955_TRBL_MASK 0x000F /* TRBL - [3:0] */ 190*4882a593Smuzhiyun #define WM8955_TRBL_SHIFT 0 /* TRBL - [3:0] */ 191*4882a593Smuzhiyun #define WM8955_TRBL_WIDTH 4 /* TRBL - [3:0] */ 192*4882a593Smuzhiyun 193*4882a593Smuzhiyun /* 194*4882a593Smuzhiyun * R15 (0x0F) - Reset 195*4882a593Smuzhiyun */ 196*4882a593Smuzhiyun #define WM8955_RESET_MASK 0x01FF /* RESET - [8:0] */ 197*4882a593Smuzhiyun #define WM8955_RESET_SHIFT 0 /* RESET - [8:0] */ 198*4882a593Smuzhiyun #define WM8955_RESET_WIDTH 9 /* RESET - [8:0] */ 199*4882a593Smuzhiyun 200*4882a593Smuzhiyun /* 201*4882a593Smuzhiyun * R23 (0x17) - Additional control (1) 202*4882a593Smuzhiyun */ 203*4882a593Smuzhiyun #define WM8955_TSDEN 0x0100 /* TSDEN */ 204*4882a593Smuzhiyun #define WM8955_TSDEN_MASK 0x0100 /* TSDEN */ 205*4882a593Smuzhiyun #define WM8955_TSDEN_SHIFT 8 /* TSDEN */ 206*4882a593Smuzhiyun #define WM8955_TSDEN_WIDTH 1 /* TSDEN */ 207*4882a593Smuzhiyun #define WM8955_VSEL_MASK 0x00C0 /* VSEL - [7:6] */ 208*4882a593Smuzhiyun #define WM8955_VSEL_SHIFT 6 /* VSEL - [7:6] */ 209*4882a593Smuzhiyun #define WM8955_VSEL_WIDTH 2 /* VSEL - [7:6] */ 210*4882a593Smuzhiyun #define WM8955_DMONOMIX_MASK 0x0030 /* DMONOMIX - [5:4] */ 211*4882a593Smuzhiyun #define WM8955_DMONOMIX_SHIFT 4 /* DMONOMIX - [5:4] */ 212*4882a593Smuzhiyun #define WM8955_DMONOMIX_WIDTH 2 /* DMONOMIX - [5:4] */ 213*4882a593Smuzhiyun #define WM8955_DACINV 0x0002 /* DACINV */ 214*4882a593Smuzhiyun #define WM8955_DACINV_MASK 0x0002 /* DACINV */ 215*4882a593Smuzhiyun #define WM8955_DACINV_SHIFT 1 /* DACINV */ 216*4882a593Smuzhiyun #define WM8955_DACINV_WIDTH 1 /* DACINV */ 217*4882a593Smuzhiyun #define WM8955_TOEN 0x0001 /* TOEN */ 218*4882a593Smuzhiyun #define WM8955_TOEN_MASK 0x0001 /* TOEN */ 219*4882a593Smuzhiyun #define WM8955_TOEN_SHIFT 0 /* TOEN */ 220*4882a593Smuzhiyun #define WM8955_TOEN_WIDTH 1 /* TOEN */ 221*4882a593Smuzhiyun 222*4882a593Smuzhiyun /* 223*4882a593Smuzhiyun * R24 (0x18) - Additional control (2) 224*4882a593Smuzhiyun */ 225*4882a593Smuzhiyun #define WM8955_OUT3SW_MASK 0x0180 /* OUT3SW - [8:7] */ 226*4882a593Smuzhiyun #define WM8955_OUT3SW_SHIFT 7 /* OUT3SW - [8:7] */ 227*4882a593Smuzhiyun #define WM8955_OUT3SW_WIDTH 2 /* OUT3SW - [8:7] */ 228*4882a593Smuzhiyun #define WM8955_ROUT2INV 0x0010 /* ROUT2INV */ 229*4882a593Smuzhiyun #define WM8955_ROUT2INV_MASK 0x0010 /* ROUT2INV */ 230*4882a593Smuzhiyun #define WM8955_ROUT2INV_SHIFT 4 /* ROUT2INV */ 231*4882a593Smuzhiyun #define WM8955_ROUT2INV_WIDTH 1 /* ROUT2INV */ 232*4882a593Smuzhiyun #define WM8955_DACOSR 0x0001 /* DACOSR */ 233*4882a593Smuzhiyun #define WM8955_DACOSR_MASK 0x0001 /* DACOSR */ 234*4882a593Smuzhiyun #define WM8955_DACOSR_SHIFT 0 /* DACOSR */ 235*4882a593Smuzhiyun #define WM8955_DACOSR_WIDTH 1 /* DACOSR */ 236*4882a593Smuzhiyun 237*4882a593Smuzhiyun /* 238*4882a593Smuzhiyun * R25 (0x19) - Power Management (1) 239*4882a593Smuzhiyun */ 240*4882a593Smuzhiyun #define WM8955_VMIDSEL_MASK 0x0180 /* VMIDSEL - [8:7] */ 241*4882a593Smuzhiyun #define WM8955_VMIDSEL_SHIFT 7 /* VMIDSEL - [8:7] */ 242*4882a593Smuzhiyun #define WM8955_VMIDSEL_WIDTH 2 /* VMIDSEL - [8:7] */ 243*4882a593Smuzhiyun #define WM8955_VREF 0x0040 /* VREF */ 244*4882a593Smuzhiyun #define WM8955_VREF_MASK 0x0040 /* VREF */ 245*4882a593Smuzhiyun #define WM8955_VREF_SHIFT 6 /* VREF */ 246*4882a593Smuzhiyun #define WM8955_VREF_WIDTH 1 /* VREF */ 247*4882a593Smuzhiyun #define WM8955_DIGENB 0x0001 /* DIGENB */ 248*4882a593Smuzhiyun #define WM8955_DIGENB_MASK 0x0001 /* DIGENB */ 249*4882a593Smuzhiyun #define WM8955_DIGENB_SHIFT 0 /* DIGENB */ 250*4882a593Smuzhiyun #define WM8955_DIGENB_WIDTH 1 /* DIGENB */ 251*4882a593Smuzhiyun 252*4882a593Smuzhiyun /* 253*4882a593Smuzhiyun * R26 (0x1A) - Power Management (2) 254*4882a593Smuzhiyun */ 255*4882a593Smuzhiyun #define WM8955_DACL 0x0100 /* DACL */ 256*4882a593Smuzhiyun #define WM8955_DACL_MASK 0x0100 /* DACL */ 257*4882a593Smuzhiyun #define WM8955_DACL_SHIFT 8 /* DACL */ 258*4882a593Smuzhiyun #define WM8955_DACL_WIDTH 1 /* DACL */ 259*4882a593Smuzhiyun #define WM8955_DACR 0x0080 /* DACR */ 260*4882a593Smuzhiyun #define WM8955_DACR_MASK 0x0080 /* DACR */ 261*4882a593Smuzhiyun #define WM8955_DACR_SHIFT 7 /* DACR */ 262*4882a593Smuzhiyun #define WM8955_DACR_WIDTH 1 /* DACR */ 263*4882a593Smuzhiyun #define WM8955_LOUT1 0x0040 /* LOUT1 */ 264*4882a593Smuzhiyun #define WM8955_LOUT1_MASK 0x0040 /* LOUT1 */ 265*4882a593Smuzhiyun #define WM8955_LOUT1_SHIFT 6 /* LOUT1 */ 266*4882a593Smuzhiyun #define WM8955_LOUT1_WIDTH 1 /* LOUT1 */ 267*4882a593Smuzhiyun #define WM8955_ROUT1 0x0020 /* ROUT1 */ 268*4882a593Smuzhiyun #define WM8955_ROUT1_MASK 0x0020 /* ROUT1 */ 269*4882a593Smuzhiyun #define WM8955_ROUT1_SHIFT 5 /* ROUT1 */ 270*4882a593Smuzhiyun #define WM8955_ROUT1_WIDTH 1 /* ROUT1 */ 271*4882a593Smuzhiyun #define WM8955_LOUT2 0x0010 /* LOUT2 */ 272*4882a593Smuzhiyun #define WM8955_LOUT2_MASK 0x0010 /* LOUT2 */ 273*4882a593Smuzhiyun #define WM8955_LOUT2_SHIFT 4 /* LOUT2 */ 274*4882a593Smuzhiyun #define WM8955_LOUT2_WIDTH 1 /* LOUT2 */ 275*4882a593Smuzhiyun #define WM8955_ROUT2 0x0008 /* ROUT2 */ 276*4882a593Smuzhiyun #define WM8955_ROUT2_MASK 0x0008 /* ROUT2 */ 277*4882a593Smuzhiyun #define WM8955_ROUT2_SHIFT 3 /* ROUT2 */ 278*4882a593Smuzhiyun #define WM8955_ROUT2_WIDTH 1 /* ROUT2 */ 279*4882a593Smuzhiyun #define WM8955_MONO 0x0004 /* MONO */ 280*4882a593Smuzhiyun #define WM8955_MONO_MASK 0x0004 /* MONO */ 281*4882a593Smuzhiyun #define WM8955_MONO_SHIFT 2 /* MONO */ 282*4882a593Smuzhiyun #define WM8955_MONO_WIDTH 1 /* MONO */ 283*4882a593Smuzhiyun #define WM8955_OUT3 0x0002 /* OUT3 */ 284*4882a593Smuzhiyun #define WM8955_OUT3_MASK 0x0002 /* OUT3 */ 285*4882a593Smuzhiyun #define WM8955_OUT3_SHIFT 1 /* OUT3 */ 286*4882a593Smuzhiyun #define WM8955_OUT3_WIDTH 1 /* OUT3 */ 287*4882a593Smuzhiyun 288*4882a593Smuzhiyun /* 289*4882a593Smuzhiyun * R27 (0x1B) - Additional Control (3) 290*4882a593Smuzhiyun */ 291*4882a593Smuzhiyun #define WM8955_VROI 0x0040 /* VROI */ 292*4882a593Smuzhiyun #define WM8955_VROI_MASK 0x0040 /* VROI */ 293*4882a593Smuzhiyun #define WM8955_VROI_SHIFT 6 /* VROI */ 294*4882a593Smuzhiyun #define WM8955_VROI_WIDTH 1 /* VROI */ 295*4882a593Smuzhiyun 296*4882a593Smuzhiyun /* 297*4882a593Smuzhiyun * R34 (0x22) - Left out Mix (1) 298*4882a593Smuzhiyun */ 299*4882a593Smuzhiyun #define WM8955_LD2LO 0x0100 /* LD2LO */ 300*4882a593Smuzhiyun #define WM8955_LD2LO_MASK 0x0100 /* LD2LO */ 301*4882a593Smuzhiyun #define WM8955_LD2LO_SHIFT 8 /* LD2LO */ 302*4882a593Smuzhiyun #define WM8955_LD2LO_WIDTH 1 /* LD2LO */ 303*4882a593Smuzhiyun #define WM8955_LI2LO 0x0080 /* LI2LO */ 304*4882a593Smuzhiyun #define WM8955_LI2LO_MASK 0x0080 /* LI2LO */ 305*4882a593Smuzhiyun #define WM8955_LI2LO_SHIFT 7 /* LI2LO */ 306*4882a593Smuzhiyun #define WM8955_LI2LO_WIDTH 1 /* LI2LO */ 307*4882a593Smuzhiyun #define WM8955_LI2LOVOL_MASK 0x0070 /* LI2LOVOL - [6:4] */ 308*4882a593Smuzhiyun #define WM8955_LI2LOVOL_SHIFT 4 /* LI2LOVOL - [6:4] */ 309*4882a593Smuzhiyun #define WM8955_LI2LOVOL_WIDTH 3 /* LI2LOVOL - [6:4] */ 310*4882a593Smuzhiyun 311*4882a593Smuzhiyun /* 312*4882a593Smuzhiyun * R35 (0x23) - Left out Mix (2) 313*4882a593Smuzhiyun */ 314*4882a593Smuzhiyun #define WM8955_RD2LO 0x0100 /* RD2LO */ 315*4882a593Smuzhiyun #define WM8955_RD2LO_MASK 0x0100 /* RD2LO */ 316*4882a593Smuzhiyun #define WM8955_RD2LO_SHIFT 8 /* RD2LO */ 317*4882a593Smuzhiyun #define WM8955_RD2LO_WIDTH 1 /* RD2LO */ 318*4882a593Smuzhiyun #define WM8955_RI2LO 0x0080 /* RI2LO */ 319*4882a593Smuzhiyun #define WM8955_RI2LO_MASK 0x0080 /* RI2LO */ 320*4882a593Smuzhiyun #define WM8955_RI2LO_SHIFT 7 /* RI2LO */ 321*4882a593Smuzhiyun #define WM8955_RI2LO_WIDTH 1 /* RI2LO */ 322*4882a593Smuzhiyun #define WM8955_RI2LOVOL_MASK 0x0070 /* RI2LOVOL - [6:4] */ 323*4882a593Smuzhiyun #define WM8955_RI2LOVOL_SHIFT 4 /* RI2LOVOL - [6:4] */ 324*4882a593Smuzhiyun #define WM8955_RI2LOVOL_WIDTH 3 /* RI2LOVOL - [6:4] */ 325*4882a593Smuzhiyun 326*4882a593Smuzhiyun /* 327*4882a593Smuzhiyun * R36 (0x24) - Right out Mix (1) 328*4882a593Smuzhiyun */ 329*4882a593Smuzhiyun #define WM8955_LD2RO 0x0100 /* LD2RO */ 330*4882a593Smuzhiyun #define WM8955_LD2RO_MASK 0x0100 /* LD2RO */ 331*4882a593Smuzhiyun #define WM8955_LD2RO_SHIFT 8 /* LD2RO */ 332*4882a593Smuzhiyun #define WM8955_LD2RO_WIDTH 1 /* LD2RO */ 333*4882a593Smuzhiyun #define WM8955_LI2RO 0x0080 /* LI2RO */ 334*4882a593Smuzhiyun #define WM8955_LI2RO_MASK 0x0080 /* LI2RO */ 335*4882a593Smuzhiyun #define WM8955_LI2RO_SHIFT 7 /* LI2RO */ 336*4882a593Smuzhiyun #define WM8955_LI2RO_WIDTH 1 /* LI2RO */ 337*4882a593Smuzhiyun #define WM8955_LI2ROVOL_MASK 0x0070 /* LI2ROVOL - [6:4] */ 338*4882a593Smuzhiyun #define WM8955_LI2ROVOL_SHIFT 4 /* LI2ROVOL - [6:4] */ 339*4882a593Smuzhiyun #define WM8955_LI2ROVOL_WIDTH 3 /* LI2ROVOL - [6:4] */ 340*4882a593Smuzhiyun 341*4882a593Smuzhiyun /* 342*4882a593Smuzhiyun * R37 (0x25) - Right Out Mix (2) 343*4882a593Smuzhiyun */ 344*4882a593Smuzhiyun #define WM8955_RD2RO 0x0100 /* RD2RO */ 345*4882a593Smuzhiyun #define WM8955_RD2RO_MASK 0x0100 /* RD2RO */ 346*4882a593Smuzhiyun #define WM8955_RD2RO_SHIFT 8 /* RD2RO */ 347*4882a593Smuzhiyun #define WM8955_RD2RO_WIDTH 1 /* RD2RO */ 348*4882a593Smuzhiyun #define WM8955_RI2RO 0x0080 /* RI2RO */ 349*4882a593Smuzhiyun #define WM8955_RI2RO_MASK 0x0080 /* RI2RO */ 350*4882a593Smuzhiyun #define WM8955_RI2RO_SHIFT 7 /* RI2RO */ 351*4882a593Smuzhiyun #define WM8955_RI2RO_WIDTH 1 /* RI2RO */ 352*4882a593Smuzhiyun #define WM8955_RI2ROVOL_MASK 0x0070 /* RI2ROVOL - [6:4] */ 353*4882a593Smuzhiyun #define WM8955_RI2ROVOL_SHIFT 4 /* RI2ROVOL - [6:4] */ 354*4882a593Smuzhiyun #define WM8955_RI2ROVOL_WIDTH 3 /* RI2ROVOL - [6:4] */ 355*4882a593Smuzhiyun 356*4882a593Smuzhiyun /* 357*4882a593Smuzhiyun * R38 (0x26) - Mono out Mix (1) 358*4882a593Smuzhiyun */ 359*4882a593Smuzhiyun #define WM8955_LD2MO 0x0100 /* LD2MO */ 360*4882a593Smuzhiyun #define WM8955_LD2MO_MASK 0x0100 /* LD2MO */ 361*4882a593Smuzhiyun #define WM8955_LD2MO_SHIFT 8 /* LD2MO */ 362*4882a593Smuzhiyun #define WM8955_LD2MO_WIDTH 1 /* LD2MO */ 363*4882a593Smuzhiyun #define WM8955_LI2MO 0x0080 /* LI2MO */ 364*4882a593Smuzhiyun #define WM8955_LI2MO_MASK 0x0080 /* LI2MO */ 365*4882a593Smuzhiyun #define WM8955_LI2MO_SHIFT 7 /* LI2MO */ 366*4882a593Smuzhiyun #define WM8955_LI2MO_WIDTH 1 /* LI2MO */ 367*4882a593Smuzhiyun #define WM8955_LI2MOVOL_MASK 0x0070 /* LI2MOVOL - [6:4] */ 368*4882a593Smuzhiyun #define WM8955_LI2MOVOL_SHIFT 4 /* LI2MOVOL - [6:4] */ 369*4882a593Smuzhiyun #define WM8955_LI2MOVOL_WIDTH 3 /* LI2MOVOL - [6:4] */ 370*4882a593Smuzhiyun #define WM8955_DMEN 0x0001 /* DMEN */ 371*4882a593Smuzhiyun #define WM8955_DMEN_MASK 0x0001 /* DMEN */ 372*4882a593Smuzhiyun #define WM8955_DMEN_SHIFT 0 /* DMEN */ 373*4882a593Smuzhiyun #define WM8955_DMEN_WIDTH 1 /* DMEN */ 374*4882a593Smuzhiyun 375*4882a593Smuzhiyun /* 376*4882a593Smuzhiyun * R39 (0x27) - Mono out Mix (2) 377*4882a593Smuzhiyun */ 378*4882a593Smuzhiyun #define WM8955_RD2MO 0x0100 /* RD2MO */ 379*4882a593Smuzhiyun #define WM8955_RD2MO_MASK 0x0100 /* RD2MO */ 380*4882a593Smuzhiyun #define WM8955_RD2MO_SHIFT 8 /* RD2MO */ 381*4882a593Smuzhiyun #define WM8955_RD2MO_WIDTH 1 /* RD2MO */ 382*4882a593Smuzhiyun #define WM8955_RI2MO 0x0080 /* RI2MO */ 383*4882a593Smuzhiyun #define WM8955_RI2MO_MASK 0x0080 /* RI2MO */ 384*4882a593Smuzhiyun #define WM8955_RI2MO_SHIFT 7 /* RI2MO */ 385*4882a593Smuzhiyun #define WM8955_RI2MO_WIDTH 1 /* RI2MO */ 386*4882a593Smuzhiyun #define WM8955_RI2MOVOL_MASK 0x0070 /* RI2MOVOL - [6:4] */ 387*4882a593Smuzhiyun #define WM8955_RI2MOVOL_SHIFT 4 /* RI2MOVOL - [6:4] */ 388*4882a593Smuzhiyun #define WM8955_RI2MOVOL_WIDTH 3 /* RI2MOVOL - [6:4] */ 389*4882a593Smuzhiyun 390*4882a593Smuzhiyun /* 391*4882a593Smuzhiyun * R40 (0x28) - LOUT2 volume 392*4882a593Smuzhiyun */ 393*4882a593Smuzhiyun #define WM8955_LO2VU 0x0100 /* LO2VU */ 394*4882a593Smuzhiyun #define WM8955_LO2VU_MASK 0x0100 /* LO2VU */ 395*4882a593Smuzhiyun #define WM8955_LO2VU_SHIFT 8 /* LO2VU */ 396*4882a593Smuzhiyun #define WM8955_LO2VU_WIDTH 1 /* LO2VU */ 397*4882a593Smuzhiyun #define WM8955_LO2ZC 0x0080 /* LO2ZC */ 398*4882a593Smuzhiyun #define WM8955_LO2ZC_MASK 0x0080 /* LO2ZC */ 399*4882a593Smuzhiyun #define WM8955_LO2ZC_SHIFT 7 /* LO2ZC */ 400*4882a593Smuzhiyun #define WM8955_LO2ZC_WIDTH 1 /* LO2ZC */ 401*4882a593Smuzhiyun #define WM8955_LOUT2VOL_MASK 0x007F /* LOUT2VOL - [6:0] */ 402*4882a593Smuzhiyun #define WM8955_LOUT2VOL_SHIFT 0 /* LOUT2VOL - [6:0] */ 403*4882a593Smuzhiyun #define WM8955_LOUT2VOL_WIDTH 7 /* LOUT2VOL - [6:0] */ 404*4882a593Smuzhiyun 405*4882a593Smuzhiyun /* 406*4882a593Smuzhiyun * R41 (0x29) - ROUT2 volume 407*4882a593Smuzhiyun */ 408*4882a593Smuzhiyun #define WM8955_RO2VU 0x0100 /* RO2VU */ 409*4882a593Smuzhiyun #define WM8955_RO2VU_MASK 0x0100 /* RO2VU */ 410*4882a593Smuzhiyun #define WM8955_RO2VU_SHIFT 8 /* RO2VU */ 411*4882a593Smuzhiyun #define WM8955_RO2VU_WIDTH 1 /* RO2VU */ 412*4882a593Smuzhiyun #define WM8955_RO2ZC 0x0080 /* RO2ZC */ 413*4882a593Smuzhiyun #define WM8955_RO2ZC_MASK 0x0080 /* RO2ZC */ 414*4882a593Smuzhiyun #define WM8955_RO2ZC_SHIFT 7 /* RO2ZC */ 415*4882a593Smuzhiyun #define WM8955_RO2ZC_WIDTH 1 /* RO2ZC */ 416*4882a593Smuzhiyun #define WM8955_ROUT2VOL_MASK 0x007F /* ROUT2VOL - [6:0] */ 417*4882a593Smuzhiyun #define WM8955_ROUT2VOL_SHIFT 0 /* ROUT2VOL - [6:0] */ 418*4882a593Smuzhiyun #define WM8955_ROUT2VOL_WIDTH 7 /* ROUT2VOL - [6:0] */ 419*4882a593Smuzhiyun 420*4882a593Smuzhiyun /* 421*4882a593Smuzhiyun * R42 (0x2A) - MONOOUT volume 422*4882a593Smuzhiyun */ 423*4882a593Smuzhiyun #define WM8955_MOZC 0x0080 /* MOZC */ 424*4882a593Smuzhiyun #define WM8955_MOZC_MASK 0x0080 /* MOZC */ 425*4882a593Smuzhiyun #define WM8955_MOZC_SHIFT 7 /* MOZC */ 426*4882a593Smuzhiyun #define WM8955_MOZC_WIDTH 1 /* MOZC */ 427*4882a593Smuzhiyun #define WM8955_MOUTVOL_MASK 0x007F /* MOUTVOL - [6:0] */ 428*4882a593Smuzhiyun #define WM8955_MOUTVOL_SHIFT 0 /* MOUTVOL - [6:0] */ 429*4882a593Smuzhiyun #define WM8955_MOUTVOL_WIDTH 7 /* MOUTVOL - [6:0] */ 430*4882a593Smuzhiyun 431*4882a593Smuzhiyun /* 432*4882a593Smuzhiyun * R43 (0x2B) - Clocking / PLL 433*4882a593Smuzhiyun */ 434*4882a593Smuzhiyun #define WM8955_MCLKSEL 0x0100 /* MCLKSEL */ 435*4882a593Smuzhiyun #define WM8955_MCLKSEL_MASK 0x0100 /* MCLKSEL */ 436*4882a593Smuzhiyun #define WM8955_MCLKSEL_SHIFT 8 /* MCLKSEL */ 437*4882a593Smuzhiyun #define WM8955_MCLKSEL_WIDTH 1 /* MCLKSEL */ 438*4882a593Smuzhiyun #define WM8955_PLLOUTDIV2 0x0020 /* PLLOUTDIV2 */ 439*4882a593Smuzhiyun #define WM8955_PLLOUTDIV2_MASK 0x0020 /* PLLOUTDIV2 */ 440*4882a593Smuzhiyun #define WM8955_PLLOUTDIV2_SHIFT 5 /* PLLOUTDIV2 */ 441*4882a593Smuzhiyun #define WM8955_PLLOUTDIV2_WIDTH 1 /* PLLOUTDIV2 */ 442*4882a593Smuzhiyun #define WM8955_PLL_RB 0x0010 /* PLL_RB */ 443*4882a593Smuzhiyun #define WM8955_PLL_RB_MASK 0x0010 /* PLL_RB */ 444*4882a593Smuzhiyun #define WM8955_PLL_RB_SHIFT 4 /* PLL_RB */ 445*4882a593Smuzhiyun #define WM8955_PLL_RB_WIDTH 1 /* PLL_RB */ 446*4882a593Smuzhiyun #define WM8955_PLLEN 0x0008 /* PLLEN */ 447*4882a593Smuzhiyun #define WM8955_PLLEN_MASK 0x0008 /* PLLEN */ 448*4882a593Smuzhiyun #define WM8955_PLLEN_SHIFT 3 /* PLLEN */ 449*4882a593Smuzhiyun #define WM8955_PLLEN_WIDTH 1 /* PLLEN */ 450*4882a593Smuzhiyun 451*4882a593Smuzhiyun /* 452*4882a593Smuzhiyun * R44 (0x2C) - PLL Control 1 453*4882a593Smuzhiyun */ 454*4882a593Smuzhiyun #define WM8955_N_MASK 0x01E0 /* N - [8:5] */ 455*4882a593Smuzhiyun #define WM8955_N_SHIFT 5 /* N - [8:5] */ 456*4882a593Smuzhiyun #define WM8955_N_WIDTH 4 /* N - [8:5] */ 457*4882a593Smuzhiyun #define WM8955_K_21_18_MASK 0x000F /* K(21:18) - [3:0] */ 458*4882a593Smuzhiyun #define WM8955_K_21_18_SHIFT 0 /* K(21:18) - [3:0] */ 459*4882a593Smuzhiyun #define WM8955_K_21_18_WIDTH 4 /* K(21:18) - [3:0] */ 460*4882a593Smuzhiyun 461*4882a593Smuzhiyun /* 462*4882a593Smuzhiyun * R45 (0x2D) - PLL Control 2 463*4882a593Smuzhiyun */ 464*4882a593Smuzhiyun #define WM8955_K_17_9_MASK 0x01FF /* K(17:9) - [8:0] */ 465*4882a593Smuzhiyun #define WM8955_K_17_9_SHIFT 0 /* K(17:9) - [8:0] */ 466*4882a593Smuzhiyun #define WM8955_K_17_9_WIDTH 9 /* K(17:9) - [8:0] */ 467*4882a593Smuzhiyun 468*4882a593Smuzhiyun /* 469*4882a593Smuzhiyun * R46 (0x2E) - PLL Control 3 470*4882a593Smuzhiyun */ 471*4882a593Smuzhiyun #define WM8955_K_8_0_MASK 0x01FF /* K(8:0) - [8:0] */ 472*4882a593Smuzhiyun #define WM8955_K_8_0_SHIFT 0 /* K(8:0) - [8:0] */ 473*4882a593Smuzhiyun #define WM8955_K_8_0_WIDTH 9 /* K(8:0) - [8:0] */ 474*4882a593Smuzhiyun 475*4882a593Smuzhiyun /* 476*4882a593Smuzhiyun * R59 (0x3B) - PLL Control 4 477*4882a593Smuzhiyun */ 478*4882a593Smuzhiyun #define WM8955_KEN 0x0080 /* KEN */ 479*4882a593Smuzhiyun #define WM8955_KEN_MASK 0x0080 /* KEN */ 480*4882a593Smuzhiyun #define WM8955_KEN_SHIFT 7 /* KEN */ 481*4882a593Smuzhiyun #define WM8955_KEN_WIDTH 1 /* KEN */ 482*4882a593Smuzhiyun 483*4882a593Smuzhiyun #endif 484