xref: /OK3568_Linux_fs/kernel/sound/soc/codecs/wm8940.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * wm8940.h -- WM8940 Soc Audio driver
4*4882a593Smuzhiyun  */
5*4882a593Smuzhiyun 
6*4882a593Smuzhiyun #ifndef _WM8940_H
7*4882a593Smuzhiyun #define _WM8940_H
8*4882a593Smuzhiyun 
9*4882a593Smuzhiyun struct wm8940_setup_data {
10*4882a593Smuzhiyun 	/* Vref to analogue output resistance */
11*4882a593Smuzhiyun #define WM8940_VROI_1K 0
12*4882a593Smuzhiyun #define WM8940_VROI_30K 1
13*4882a593Smuzhiyun 	unsigned int vroi:1;
14*4882a593Smuzhiyun };
15*4882a593Smuzhiyun 
16*4882a593Smuzhiyun /* WM8940 register space */
17*4882a593Smuzhiyun #define WM8940_SOFTRESET	0x00
18*4882a593Smuzhiyun #define WM8940_POWER1		0x01
19*4882a593Smuzhiyun #define WM8940_POWER2		0x02
20*4882a593Smuzhiyun #define WM8940_POWER3		0x03
21*4882a593Smuzhiyun #define WM8940_IFACE		0x04
22*4882a593Smuzhiyun #define WM8940_COMPANDINGCTL	0x05
23*4882a593Smuzhiyun #define WM8940_CLOCK		0x06
24*4882a593Smuzhiyun #define WM8940_ADDCNTRL		0x07
25*4882a593Smuzhiyun #define WM8940_GPIO		0x08
26*4882a593Smuzhiyun #define WM8940_CTLINT		0x09
27*4882a593Smuzhiyun #define WM8940_DAC		0x0A
28*4882a593Smuzhiyun #define WM8940_DACVOL		0x0B
29*4882a593Smuzhiyun 
30*4882a593Smuzhiyun #define WM8940_ADC		0x0E
31*4882a593Smuzhiyun #define WM8940_ADCVOL		0x0F
32*4882a593Smuzhiyun #define WM8940_NOTCH1		0x10
33*4882a593Smuzhiyun #define WM8940_NOTCH2		0x11
34*4882a593Smuzhiyun #define WM8940_NOTCH3		0x12
35*4882a593Smuzhiyun #define WM8940_NOTCH4		0x13
36*4882a593Smuzhiyun #define WM8940_NOTCH5		0x14
37*4882a593Smuzhiyun #define WM8940_NOTCH6		0x15
38*4882a593Smuzhiyun #define WM8940_NOTCH7		0x16
39*4882a593Smuzhiyun #define WM8940_NOTCH8		0x17
40*4882a593Smuzhiyun #define WM8940_DACLIM1		0x18
41*4882a593Smuzhiyun #define WM8940_DACLIM2		0x19
42*4882a593Smuzhiyun 
43*4882a593Smuzhiyun #define WM8940_ALC1		0x20
44*4882a593Smuzhiyun #define WM8940_ALC2		0x21
45*4882a593Smuzhiyun #define WM8940_ALC3		0x22
46*4882a593Smuzhiyun #define WM8940_NOISEGATE	0x23
47*4882a593Smuzhiyun #define WM8940_PLLN		0x24
48*4882a593Smuzhiyun #define WM8940_PLLK1		0x25
49*4882a593Smuzhiyun #define WM8940_PLLK2		0x26
50*4882a593Smuzhiyun #define WM8940_PLLK3		0x27
51*4882a593Smuzhiyun 
52*4882a593Smuzhiyun #define WM8940_ALC4		0x2A
53*4882a593Smuzhiyun 
54*4882a593Smuzhiyun #define WM8940_INPUTCTL		0x2C
55*4882a593Smuzhiyun #define WM8940_PGAGAIN		0x2D
56*4882a593Smuzhiyun 
57*4882a593Smuzhiyun #define WM8940_ADCBOOST		0x2F
58*4882a593Smuzhiyun 
59*4882a593Smuzhiyun #define WM8940_OUTPUTCTL	0x31
60*4882a593Smuzhiyun #define WM8940_SPKMIX		0x32
61*4882a593Smuzhiyun 
62*4882a593Smuzhiyun #define WM8940_SPKVOL		0x36
63*4882a593Smuzhiyun 
64*4882a593Smuzhiyun #define WM8940_MONOMIX		0x38
65*4882a593Smuzhiyun 
66*4882a593Smuzhiyun #define WM8940_CACHEREGNUM  0x57
67*4882a593Smuzhiyun 
68*4882a593Smuzhiyun 
69*4882a593Smuzhiyun /* Clock divider Id's */
70*4882a593Smuzhiyun #define WM8940_BCLKDIV 0
71*4882a593Smuzhiyun #define WM8940_MCLKDIV 1
72*4882a593Smuzhiyun #define WM8940_OPCLKDIV 2
73*4882a593Smuzhiyun 
74*4882a593Smuzhiyun /* MCLK clock dividers */
75*4882a593Smuzhiyun #define WM8940_MCLKDIV_1	0
76*4882a593Smuzhiyun #define WM8940_MCLKDIV_1_5	1
77*4882a593Smuzhiyun #define WM8940_MCLKDIV_2	2
78*4882a593Smuzhiyun #define WM8940_MCLKDIV_3	3
79*4882a593Smuzhiyun #define WM8940_MCLKDIV_4	4
80*4882a593Smuzhiyun #define WM8940_MCLKDIV_6	5
81*4882a593Smuzhiyun #define WM8940_MCLKDIV_8	6
82*4882a593Smuzhiyun #define WM8940_MCLKDIV_12	7
83*4882a593Smuzhiyun 
84*4882a593Smuzhiyun /* BCLK clock dividers */
85*4882a593Smuzhiyun #define WM8940_BCLKDIV_1 0
86*4882a593Smuzhiyun #define WM8940_BCLKDIV_2 1
87*4882a593Smuzhiyun #define WM8940_BCLKDIV_4 2
88*4882a593Smuzhiyun #define WM8940_BCLKDIV_8 3
89*4882a593Smuzhiyun #define WM8940_BCLKDIV_16 4
90*4882a593Smuzhiyun #define WM8940_BCLKDIV_32 5
91*4882a593Smuzhiyun 
92*4882a593Smuzhiyun /* PLL Out Dividers */
93*4882a593Smuzhiyun #define WM8940_OPCLKDIV_1 0
94*4882a593Smuzhiyun #define WM8940_OPCLKDIV_2 1
95*4882a593Smuzhiyun #define WM8940_OPCLKDIV_3 2
96*4882a593Smuzhiyun #define WM8940_OPCLKDIV_4 3
97*4882a593Smuzhiyun 
98*4882a593Smuzhiyun #endif /* _WM8940_H */
99*4882a593Smuzhiyun 
100