1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * wm8753.h -- audio driver for WM8753 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright 2003 Wolfson Microelectronics PLC. 6*4882a593Smuzhiyun * Author: Liam Girdwood <lrg@slimlogic.co.uk> 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef _WM8753_H 10*4882a593Smuzhiyun #define _WM8753_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* WM8753 register space */ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define WM8753_DAC 0x01 15*4882a593Smuzhiyun #define WM8753_ADC 0x02 16*4882a593Smuzhiyun #define WM8753_PCM 0x03 17*4882a593Smuzhiyun #define WM8753_HIFI 0x04 18*4882a593Smuzhiyun #define WM8753_IOCTL 0x05 19*4882a593Smuzhiyun #define WM8753_SRATE1 0x06 20*4882a593Smuzhiyun #define WM8753_SRATE2 0x07 21*4882a593Smuzhiyun #define WM8753_LDAC 0x08 22*4882a593Smuzhiyun #define WM8753_RDAC 0x09 23*4882a593Smuzhiyun #define WM8753_BASS 0x0a 24*4882a593Smuzhiyun #define WM8753_TREBLE 0x0b 25*4882a593Smuzhiyun #define WM8753_ALC1 0x0c 26*4882a593Smuzhiyun #define WM8753_ALC2 0x0d 27*4882a593Smuzhiyun #define WM8753_ALC3 0x0e 28*4882a593Smuzhiyun #define WM8753_NGATE 0x0f 29*4882a593Smuzhiyun #define WM8753_LADC 0x10 30*4882a593Smuzhiyun #define WM8753_RADC 0x11 31*4882a593Smuzhiyun #define WM8753_ADCTL1 0x12 32*4882a593Smuzhiyun #define WM8753_3D 0x13 33*4882a593Smuzhiyun #define WM8753_PWR1 0x14 34*4882a593Smuzhiyun #define WM8753_PWR2 0x15 35*4882a593Smuzhiyun #define WM8753_PWR3 0x16 36*4882a593Smuzhiyun #define WM8753_PWR4 0x17 37*4882a593Smuzhiyun #define WM8753_ID 0x18 38*4882a593Smuzhiyun #define WM8753_INTPOL 0x19 39*4882a593Smuzhiyun #define WM8753_INTEN 0x1a 40*4882a593Smuzhiyun #define WM8753_GPIO1 0x1b 41*4882a593Smuzhiyun #define WM8753_GPIO2 0x1c 42*4882a593Smuzhiyun #define WM8753_RESET 0x1f 43*4882a593Smuzhiyun #define WM8753_RECMIX1 0x20 44*4882a593Smuzhiyun #define WM8753_RECMIX2 0x21 45*4882a593Smuzhiyun #define WM8753_LOUTM1 0x22 46*4882a593Smuzhiyun #define WM8753_LOUTM2 0x23 47*4882a593Smuzhiyun #define WM8753_ROUTM1 0x24 48*4882a593Smuzhiyun #define WM8753_ROUTM2 0x25 49*4882a593Smuzhiyun #define WM8753_MOUTM1 0x26 50*4882a593Smuzhiyun #define WM8753_MOUTM2 0x27 51*4882a593Smuzhiyun #define WM8753_LOUT1V 0x28 52*4882a593Smuzhiyun #define WM8753_ROUT1V 0x29 53*4882a593Smuzhiyun #define WM8753_LOUT2V 0x2a 54*4882a593Smuzhiyun #define WM8753_ROUT2V 0x2b 55*4882a593Smuzhiyun #define WM8753_MOUTV 0x2c 56*4882a593Smuzhiyun #define WM8753_OUTCTL 0x2d 57*4882a593Smuzhiyun #define WM8753_ADCIN 0x2e 58*4882a593Smuzhiyun #define WM8753_INCTL1 0x2f 59*4882a593Smuzhiyun #define WM8753_INCTL2 0x30 60*4882a593Smuzhiyun #define WM8753_LINVOL 0x31 61*4882a593Smuzhiyun #define WM8753_RINVOL 0x32 62*4882a593Smuzhiyun #define WM8753_MICBIAS 0x33 63*4882a593Smuzhiyun #define WM8753_CLOCK 0x34 64*4882a593Smuzhiyun #define WM8753_PLL1CTL1 0x35 65*4882a593Smuzhiyun #define WM8753_PLL1CTL2 0x36 66*4882a593Smuzhiyun #define WM8753_PLL1CTL3 0x37 67*4882a593Smuzhiyun #define WM8753_PLL1CTL4 0x38 68*4882a593Smuzhiyun #define WM8753_PLL2CTL1 0x39 69*4882a593Smuzhiyun #define WM8753_PLL2CTL2 0x3a 70*4882a593Smuzhiyun #define WM8753_PLL2CTL3 0x3b 71*4882a593Smuzhiyun #define WM8753_PLL2CTL4 0x3c 72*4882a593Smuzhiyun #define WM8753_BIASCTL 0x3d 73*4882a593Smuzhiyun #define WM8753_ADCTL2 0x3f 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun #define WM8753_PLL1 0 76*4882a593Smuzhiyun #define WM8753_PLL2 1 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun /* clock inputs */ 79*4882a593Smuzhiyun #define WM8753_MCLK 0 80*4882a593Smuzhiyun #define WM8753_PCMCLK 1 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun /* clock divider id's */ 83*4882a593Smuzhiyun #define WM8753_PCMDIV 0 84*4882a593Smuzhiyun #define WM8753_BCLKDIV 1 85*4882a593Smuzhiyun #define WM8753_VXCLKDIV 2 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun /* PCM clock dividers */ 88*4882a593Smuzhiyun #define WM8753_PCM_DIV_1 (0 << 6) 89*4882a593Smuzhiyun #define WM8753_PCM_DIV_3 (2 << 6) 90*4882a593Smuzhiyun #define WM8753_PCM_DIV_5_5 (3 << 6) 91*4882a593Smuzhiyun #define WM8753_PCM_DIV_2 (4 << 6) 92*4882a593Smuzhiyun #define WM8753_PCM_DIV_4 (5 << 6) 93*4882a593Smuzhiyun #define WM8753_PCM_DIV_6 (6 << 6) 94*4882a593Smuzhiyun #define WM8753_PCM_DIV_8 (7 << 6) 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun /* BCLK clock dividers */ 97*4882a593Smuzhiyun #define WM8753_BCLK_DIV_1 (0 << 3) 98*4882a593Smuzhiyun #define WM8753_BCLK_DIV_2 (1 << 3) 99*4882a593Smuzhiyun #define WM8753_BCLK_DIV_4 (2 << 3) 100*4882a593Smuzhiyun #define WM8753_BCLK_DIV_8 (3 << 3) 101*4882a593Smuzhiyun #define WM8753_BCLK_DIV_16 (4 << 3) 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun /* VXCLK clock dividers */ 104*4882a593Smuzhiyun #define WM8753_VXCLK_DIV_1 (0 << 6) 105*4882a593Smuzhiyun #define WM8753_VXCLK_DIV_2 (1 << 6) 106*4882a593Smuzhiyun #define WM8753_VXCLK_DIV_4 (2 << 6) 107*4882a593Smuzhiyun #define WM8753_VXCLK_DIV_8 (3 << 6) 108*4882a593Smuzhiyun #define WM8753_VXCLK_DIV_16 (4 << 6) 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun #endif 111