1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * wm8750.c -- WM8750 ALSA SoC audio driver
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright 2005 Openedhand Ltd.
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Author: Richard Purdie <richard@openedhand.com>
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * Based on WM8753.c
10*4882a593Smuzhiyun */
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include <linux/module.h>
13*4882a593Smuzhiyun #include <linux/moduleparam.h>
14*4882a593Smuzhiyun #include <linux/init.h>
15*4882a593Smuzhiyun #include <linux/delay.h>
16*4882a593Smuzhiyun #include <linux/pm.h>
17*4882a593Smuzhiyun #include <linux/i2c.h>
18*4882a593Smuzhiyun #include <linux/regmap.h>
19*4882a593Smuzhiyun #include <linux/spi/spi.h>
20*4882a593Smuzhiyun #include <linux/slab.h>
21*4882a593Smuzhiyun #include <linux/of_device.h>
22*4882a593Smuzhiyun #include <sound/core.h>
23*4882a593Smuzhiyun #include <sound/pcm.h>
24*4882a593Smuzhiyun #include <sound/pcm_params.h>
25*4882a593Smuzhiyun #include <sound/soc.h>
26*4882a593Smuzhiyun #include <sound/initval.h>
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun #include "wm8750.h"
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun /*
31*4882a593Smuzhiyun * wm8750 register cache
32*4882a593Smuzhiyun * We can't read the WM8750 register space when we
33*4882a593Smuzhiyun * are using 2 wire for device control, so we cache them instead.
34*4882a593Smuzhiyun */
35*4882a593Smuzhiyun static const struct reg_default wm8750_reg_defaults[] = {
36*4882a593Smuzhiyun { 0, 0x0097 },
37*4882a593Smuzhiyun { 1, 0x0097 },
38*4882a593Smuzhiyun { 2, 0x0079 },
39*4882a593Smuzhiyun { 3, 0x0079 },
40*4882a593Smuzhiyun { 4, 0x0000 },
41*4882a593Smuzhiyun { 5, 0x0008 },
42*4882a593Smuzhiyun { 6, 0x0000 },
43*4882a593Smuzhiyun { 7, 0x000a },
44*4882a593Smuzhiyun { 8, 0x0000 },
45*4882a593Smuzhiyun { 9, 0x0000 },
46*4882a593Smuzhiyun { 10, 0x00ff },
47*4882a593Smuzhiyun { 11, 0x00ff },
48*4882a593Smuzhiyun { 12, 0x000f },
49*4882a593Smuzhiyun { 13, 0x000f },
50*4882a593Smuzhiyun { 14, 0x0000 },
51*4882a593Smuzhiyun { 15, 0x0000 },
52*4882a593Smuzhiyun { 16, 0x0000 },
53*4882a593Smuzhiyun { 17, 0x007b },
54*4882a593Smuzhiyun { 18, 0x0000 },
55*4882a593Smuzhiyun { 19, 0x0032 },
56*4882a593Smuzhiyun { 20, 0x0000 },
57*4882a593Smuzhiyun { 21, 0x00c3 },
58*4882a593Smuzhiyun { 22, 0x00c3 },
59*4882a593Smuzhiyun { 23, 0x00c0 },
60*4882a593Smuzhiyun { 24, 0x0000 },
61*4882a593Smuzhiyun { 25, 0x0000 },
62*4882a593Smuzhiyun { 26, 0x0000 },
63*4882a593Smuzhiyun { 27, 0x0000 },
64*4882a593Smuzhiyun { 28, 0x0000 },
65*4882a593Smuzhiyun { 29, 0x0000 },
66*4882a593Smuzhiyun { 30, 0x0000 },
67*4882a593Smuzhiyun { 31, 0x0000 },
68*4882a593Smuzhiyun { 32, 0x0000 },
69*4882a593Smuzhiyun { 33, 0x0000 },
70*4882a593Smuzhiyun { 34, 0x0050 },
71*4882a593Smuzhiyun { 35, 0x0050 },
72*4882a593Smuzhiyun { 36, 0x0050 },
73*4882a593Smuzhiyun { 37, 0x0050 },
74*4882a593Smuzhiyun { 38, 0x0050 },
75*4882a593Smuzhiyun { 39, 0x0050 },
76*4882a593Smuzhiyun { 40, 0x0079 },
77*4882a593Smuzhiyun { 41, 0x0079 },
78*4882a593Smuzhiyun { 42, 0x0079 },
79*4882a593Smuzhiyun };
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun /* codec private data */
82*4882a593Smuzhiyun struct wm8750_priv {
83*4882a593Smuzhiyun unsigned int sysclk;
84*4882a593Smuzhiyun };
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun #define wm8750_reset(c) snd_soc_component_write(c, WM8750_RESET, 0)
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun /*
89*4882a593Smuzhiyun * WM8750 Controls
90*4882a593Smuzhiyun */
91*4882a593Smuzhiyun static const char *wm8750_bass[] = {"Linear Control", "Adaptive Boost"};
92*4882a593Smuzhiyun static const char *wm8750_bass_filter[] = { "130Hz @ 48kHz", "200Hz @ 48kHz" };
93*4882a593Smuzhiyun static const char *wm8750_treble[] = {"8kHz", "4kHz"};
94*4882a593Smuzhiyun static const char *wm8750_3d_lc[] = {"200Hz", "500Hz"};
95*4882a593Smuzhiyun static const char *wm8750_3d_uc[] = {"2.2kHz", "1.5kHz"};
96*4882a593Smuzhiyun static const char *wm8750_3d_func[] = {"Capture", "Playback"};
97*4882a593Smuzhiyun static const char *wm8750_alc_func[] = {"Off", "Right", "Left", "Stereo"};
98*4882a593Smuzhiyun static const char *wm8750_ng_type[] = {"Constant PGA Gain",
99*4882a593Smuzhiyun "Mute ADC Output"};
100*4882a593Smuzhiyun static const char *wm8750_line_mux[] = {"Line 1", "Line 2", "Line 3", "PGA",
101*4882a593Smuzhiyun "Differential"};
102*4882a593Smuzhiyun static const char *wm8750_pga_sel[] = {"Line 1", "Line 2", "Line 3",
103*4882a593Smuzhiyun "Differential"};
104*4882a593Smuzhiyun static const char *wm8750_out3[] = {"VREF", "ROUT1 + Vol", "MonoOut",
105*4882a593Smuzhiyun "ROUT1"};
106*4882a593Smuzhiyun static const char *wm8750_diff_sel[] = {"Line 1", "Line 2"};
107*4882a593Smuzhiyun static const char *wm8750_adcpol[] = {"Normal", "L Invert", "R Invert",
108*4882a593Smuzhiyun "L + R Invert"};
109*4882a593Smuzhiyun static const char *wm8750_deemph[] = {"None", "32Khz", "44.1Khz", "48Khz"};
110*4882a593Smuzhiyun static const char *wm8750_mono_mux[] = {"Stereo", "Mono (Left)",
111*4882a593Smuzhiyun "Mono (Right)", "Digital Mono"};
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun static const struct soc_enum wm8750_enum[] = {
114*4882a593Smuzhiyun SOC_ENUM_SINGLE(WM8750_BASS, 7, 2, wm8750_bass),
115*4882a593Smuzhiyun SOC_ENUM_SINGLE(WM8750_BASS, 6, 2, wm8750_bass_filter),
116*4882a593Smuzhiyun SOC_ENUM_SINGLE(WM8750_TREBLE, 6, 2, wm8750_treble),
117*4882a593Smuzhiyun SOC_ENUM_SINGLE(WM8750_3D, 5, 2, wm8750_3d_lc),
118*4882a593Smuzhiyun SOC_ENUM_SINGLE(WM8750_3D, 6, 2, wm8750_3d_uc),
119*4882a593Smuzhiyun SOC_ENUM_SINGLE(WM8750_3D, 7, 2, wm8750_3d_func),
120*4882a593Smuzhiyun SOC_ENUM_SINGLE(WM8750_ALC1, 7, 4, wm8750_alc_func),
121*4882a593Smuzhiyun SOC_ENUM_SINGLE(WM8750_NGATE, 1, 2, wm8750_ng_type),
122*4882a593Smuzhiyun SOC_ENUM_SINGLE(WM8750_LOUTM1, 0, 5, wm8750_line_mux),
123*4882a593Smuzhiyun SOC_ENUM_SINGLE(WM8750_ROUTM1, 0, 5, wm8750_line_mux),
124*4882a593Smuzhiyun SOC_ENUM_SINGLE(WM8750_LADCIN, 6, 4, wm8750_pga_sel), /* 10 */
125*4882a593Smuzhiyun SOC_ENUM_SINGLE(WM8750_RADCIN, 6, 4, wm8750_pga_sel),
126*4882a593Smuzhiyun SOC_ENUM_SINGLE(WM8750_ADCTL2, 7, 4, wm8750_out3),
127*4882a593Smuzhiyun SOC_ENUM_SINGLE(WM8750_ADCIN, 8, 2, wm8750_diff_sel),
128*4882a593Smuzhiyun SOC_ENUM_SINGLE(WM8750_ADCDAC, 5, 4, wm8750_adcpol),
129*4882a593Smuzhiyun SOC_ENUM_SINGLE(WM8750_ADCDAC, 1, 4, wm8750_deemph),
130*4882a593Smuzhiyun SOC_ENUM_SINGLE(WM8750_ADCIN, 6, 4, wm8750_mono_mux), /* 16 */
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun };
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun static const struct snd_kcontrol_new wm8750_snd_controls[] = {
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun SOC_DOUBLE_R("Capture Volume", WM8750_LINVOL, WM8750_RINVOL, 0, 63, 0),
137*4882a593Smuzhiyun SOC_DOUBLE_R("Capture ZC Switch", WM8750_LINVOL, WM8750_RINVOL, 6, 1, 0),
138*4882a593Smuzhiyun SOC_DOUBLE_R("Capture Switch", WM8750_LINVOL, WM8750_RINVOL, 7, 1, 1),
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun SOC_DOUBLE_R("Headphone Playback ZC Switch", WM8750_LOUT1V,
141*4882a593Smuzhiyun WM8750_ROUT1V, 7, 1, 0),
142*4882a593Smuzhiyun SOC_DOUBLE_R("Speaker Playback ZC Switch", WM8750_LOUT2V,
143*4882a593Smuzhiyun WM8750_ROUT2V, 7, 1, 0),
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun SOC_ENUM("Playback De-emphasis", wm8750_enum[15]),
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun SOC_ENUM("Capture Polarity", wm8750_enum[14]),
148*4882a593Smuzhiyun SOC_SINGLE("Playback 6dB Attenuate", WM8750_ADCDAC, 7, 1, 0),
149*4882a593Smuzhiyun SOC_SINGLE("Capture 6dB Attenuate", WM8750_ADCDAC, 8, 1, 0),
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun SOC_DOUBLE_R("PCM Volume", WM8750_LDAC, WM8750_RDAC, 0, 255, 0),
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun SOC_ENUM("Bass Boost", wm8750_enum[0]),
154*4882a593Smuzhiyun SOC_ENUM("Bass Filter", wm8750_enum[1]),
155*4882a593Smuzhiyun SOC_SINGLE("Bass Volume", WM8750_BASS, 0, 15, 1),
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun SOC_SINGLE("Treble Volume", WM8750_TREBLE, 0, 15, 1),
158*4882a593Smuzhiyun SOC_ENUM("Treble Cut-off", wm8750_enum[2]),
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun SOC_SINGLE("3D Switch", WM8750_3D, 0, 1, 0),
161*4882a593Smuzhiyun SOC_SINGLE("3D Volume", WM8750_3D, 1, 15, 0),
162*4882a593Smuzhiyun SOC_ENUM("3D Lower Cut-off", wm8750_enum[3]),
163*4882a593Smuzhiyun SOC_ENUM("3D Upper Cut-off", wm8750_enum[4]),
164*4882a593Smuzhiyun SOC_ENUM("3D Mode", wm8750_enum[5]),
165*4882a593Smuzhiyun
166*4882a593Smuzhiyun SOC_SINGLE("ALC Capture Target Volume", WM8750_ALC1, 0, 7, 0),
167*4882a593Smuzhiyun SOC_SINGLE("ALC Capture Max Volume", WM8750_ALC1, 4, 7, 0),
168*4882a593Smuzhiyun SOC_ENUM("ALC Capture Function", wm8750_enum[6]),
169*4882a593Smuzhiyun SOC_SINGLE("ALC Capture ZC Switch", WM8750_ALC2, 7, 1, 0),
170*4882a593Smuzhiyun SOC_SINGLE("ALC Capture Hold Time", WM8750_ALC2, 0, 15, 0),
171*4882a593Smuzhiyun SOC_SINGLE("ALC Capture Decay Time", WM8750_ALC3, 4, 15, 0),
172*4882a593Smuzhiyun SOC_SINGLE("ALC Capture Attack Time", WM8750_ALC3, 0, 15, 0),
173*4882a593Smuzhiyun SOC_SINGLE("ALC Capture NG Threshold", WM8750_NGATE, 3, 31, 0),
174*4882a593Smuzhiyun SOC_ENUM("ALC Capture NG Type", wm8750_enum[4]),
175*4882a593Smuzhiyun SOC_SINGLE("ALC Capture NG Switch", WM8750_NGATE, 0, 1, 0),
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun SOC_SINGLE("Left ADC Capture Volume", WM8750_LADC, 0, 255, 0),
178*4882a593Smuzhiyun SOC_SINGLE("Right ADC Capture Volume", WM8750_RADC, 0, 255, 0),
179*4882a593Smuzhiyun
180*4882a593Smuzhiyun SOC_SINGLE("ZC Timeout Switch", WM8750_ADCTL1, 0, 1, 0),
181*4882a593Smuzhiyun SOC_SINGLE("Playback Invert Switch", WM8750_ADCTL1, 1, 1, 0),
182*4882a593Smuzhiyun
183*4882a593Smuzhiyun SOC_SINGLE("Right Speaker Playback Invert Switch", WM8750_ADCTL2, 4, 1, 0),
184*4882a593Smuzhiyun
185*4882a593Smuzhiyun /* Unimplemented */
186*4882a593Smuzhiyun /* ADCDAC Bit 0 - ADCHPD */
187*4882a593Smuzhiyun /* ADCDAC Bit 4 - HPOR */
188*4882a593Smuzhiyun /* ADCTL1 Bit 2,3 - DATSEL */
189*4882a593Smuzhiyun /* ADCTL1 Bit 4,5 - DMONOMIX */
190*4882a593Smuzhiyun /* ADCTL1 Bit 6,7 - VSEL */
191*4882a593Smuzhiyun /* ADCTL2 Bit 2 - LRCM */
192*4882a593Smuzhiyun /* ADCTL2 Bit 3 - TRI */
193*4882a593Smuzhiyun /* ADCTL3 Bit 5 - HPFLREN */
194*4882a593Smuzhiyun /* ADCTL3 Bit 6 - VROI */
195*4882a593Smuzhiyun /* ADCTL3 Bit 7,8 - ADCLRM */
196*4882a593Smuzhiyun /* ADCIN Bit 4 - LDCM */
197*4882a593Smuzhiyun /* ADCIN Bit 5 - RDCM */
198*4882a593Smuzhiyun
199*4882a593Smuzhiyun SOC_DOUBLE_R("Mic Boost", WM8750_LADCIN, WM8750_RADCIN, 4, 3, 0),
200*4882a593Smuzhiyun
201*4882a593Smuzhiyun SOC_DOUBLE_R("Bypass Left Playback Volume", WM8750_LOUTM1,
202*4882a593Smuzhiyun WM8750_LOUTM2, 4, 7, 1),
203*4882a593Smuzhiyun SOC_DOUBLE_R("Bypass Right Playback Volume", WM8750_ROUTM1,
204*4882a593Smuzhiyun WM8750_ROUTM2, 4, 7, 1),
205*4882a593Smuzhiyun SOC_DOUBLE_R("Bypass Mono Playback Volume", WM8750_MOUTM1,
206*4882a593Smuzhiyun WM8750_MOUTM2, 4, 7, 1),
207*4882a593Smuzhiyun
208*4882a593Smuzhiyun SOC_SINGLE("Mono Playback ZC Switch", WM8750_MOUTV, 7, 1, 0),
209*4882a593Smuzhiyun
210*4882a593Smuzhiyun SOC_DOUBLE_R("Headphone Playback Volume", WM8750_LOUT1V, WM8750_ROUT1V,
211*4882a593Smuzhiyun 0, 127, 0),
212*4882a593Smuzhiyun SOC_DOUBLE_R("Speaker Playback Volume", WM8750_LOUT2V, WM8750_ROUT2V,
213*4882a593Smuzhiyun 0, 127, 0),
214*4882a593Smuzhiyun
215*4882a593Smuzhiyun SOC_SINGLE("Mono Playback Volume", WM8750_MOUTV, 0, 127, 0),
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun };
218*4882a593Smuzhiyun
219*4882a593Smuzhiyun /*
220*4882a593Smuzhiyun * DAPM Controls
221*4882a593Smuzhiyun */
222*4882a593Smuzhiyun
223*4882a593Smuzhiyun /* Left Mixer */
224*4882a593Smuzhiyun static const struct snd_kcontrol_new wm8750_left_mixer_controls[] = {
225*4882a593Smuzhiyun SOC_DAPM_SINGLE("Playback Switch", WM8750_LOUTM1, 8, 1, 0),
226*4882a593Smuzhiyun SOC_DAPM_SINGLE("Left Bypass Switch", WM8750_LOUTM1, 7, 1, 0),
227*4882a593Smuzhiyun SOC_DAPM_SINGLE("Right Playback Switch", WM8750_LOUTM2, 8, 1, 0),
228*4882a593Smuzhiyun SOC_DAPM_SINGLE("Right Bypass Switch", WM8750_LOUTM2, 7, 1, 0),
229*4882a593Smuzhiyun };
230*4882a593Smuzhiyun
231*4882a593Smuzhiyun /* Right Mixer */
232*4882a593Smuzhiyun static const struct snd_kcontrol_new wm8750_right_mixer_controls[] = {
233*4882a593Smuzhiyun SOC_DAPM_SINGLE("Left Playback Switch", WM8750_ROUTM1, 8, 1, 0),
234*4882a593Smuzhiyun SOC_DAPM_SINGLE("Left Bypass Switch", WM8750_ROUTM1, 7, 1, 0),
235*4882a593Smuzhiyun SOC_DAPM_SINGLE("Playback Switch", WM8750_ROUTM2, 8, 1, 0),
236*4882a593Smuzhiyun SOC_DAPM_SINGLE("Right Bypass Switch", WM8750_ROUTM2, 7, 1, 0),
237*4882a593Smuzhiyun };
238*4882a593Smuzhiyun
239*4882a593Smuzhiyun /* Mono Mixer */
240*4882a593Smuzhiyun static const struct snd_kcontrol_new wm8750_mono_mixer_controls[] = {
241*4882a593Smuzhiyun SOC_DAPM_SINGLE("Left Playback Switch", WM8750_MOUTM1, 8, 1, 0),
242*4882a593Smuzhiyun SOC_DAPM_SINGLE("Left Bypass Switch", WM8750_MOUTM1, 7, 1, 0),
243*4882a593Smuzhiyun SOC_DAPM_SINGLE("Right Playback Switch", WM8750_MOUTM2, 8, 1, 0),
244*4882a593Smuzhiyun SOC_DAPM_SINGLE("Right Bypass Switch", WM8750_MOUTM2, 7, 1, 0),
245*4882a593Smuzhiyun };
246*4882a593Smuzhiyun
247*4882a593Smuzhiyun /* Left Line Mux */
248*4882a593Smuzhiyun static const struct snd_kcontrol_new wm8750_left_line_controls =
249*4882a593Smuzhiyun SOC_DAPM_ENUM("Route", wm8750_enum[8]);
250*4882a593Smuzhiyun
251*4882a593Smuzhiyun /* Right Line Mux */
252*4882a593Smuzhiyun static const struct snd_kcontrol_new wm8750_right_line_controls =
253*4882a593Smuzhiyun SOC_DAPM_ENUM("Route", wm8750_enum[9]);
254*4882a593Smuzhiyun
255*4882a593Smuzhiyun /* Left PGA Mux */
256*4882a593Smuzhiyun static const struct snd_kcontrol_new wm8750_left_pga_controls =
257*4882a593Smuzhiyun SOC_DAPM_ENUM("Route", wm8750_enum[10]);
258*4882a593Smuzhiyun
259*4882a593Smuzhiyun /* Right PGA Mux */
260*4882a593Smuzhiyun static const struct snd_kcontrol_new wm8750_right_pga_controls =
261*4882a593Smuzhiyun SOC_DAPM_ENUM("Route", wm8750_enum[11]);
262*4882a593Smuzhiyun
263*4882a593Smuzhiyun /* Out 3 Mux */
264*4882a593Smuzhiyun static const struct snd_kcontrol_new wm8750_out3_controls =
265*4882a593Smuzhiyun SOC_DAPM_ENUM("Route", wm8750_enum[12]);
266*4882a593Smuzhiyun
267*4882a593Smuzhiyun /* Differential Mux */
268*4882a593Smuzhiyun static const struct snd_kcontrol_new wm8750_diffmux_controls =
269*4882a593Smuzhiyun SOC_DAPM_ENUM("Route", wm8750_enum[13]);
270*4882a593Smuzhiyun
271*4882a593Smuzhiyun /* Mono ADC Mux */
272*4882a593Smuzhiyun static const struct snd_kcontrol_new wm8750_monomux_controls =
273*4882a593Smuzhiyun SOC_DAPM_ENUM("Route", wm8750_enum[16]);
274*4882a593Smuzhiyun
275*4882a593Smuzhiyun static const struct snd_soc_dapm_widget wm8750_dapm_widgets[] = {
276*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("Left Mixer", SND_SOC_NOPM, 0, 0,
277*4882a593Smuzhiyun &wm8750_left_mixer_controls[0],
278*4882a593Smuzhiyun ARRAY_SIZE(wm8750_left_mixer_controls)),
279*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("Right Mixer", SND_SOC_NOPM, 0, 0,
280*4882a593Smuzhiyun &wm8750_right_mixer_controls[0],
281*4882a593Smuzhiyun ARRAY_SIZE(wm8750_right_mixer_controls)),
282*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("Mono Mixer", WM8750_PWR2, 2, 0,
283*4882a593Smuzhiyun &wm8750_mono_mixer_controls[0],
284*4882a593Smuzhiyun ARRAY_SIZE(wm8750_mono_mixer_controls)),
285*4882a593Smuzhiyun
286*4882a593Smuzhiyun SND_SOC_DAPM_PGA("Right Out 2", WM8750_PWR2, 3, 0, NULL, 0),
287*4882a593Smuzhiyun SND_SOC_DAPM_PGA("Left Out 2", WM8750_PWR2, 4, 0, NULL, 0),
288*4882a593Smuzhiyun SND_SOC_DAPM_PGA("Right Out 1", WM8750_PWR2, 5, 0, NULL, 0),
289*4882a593Smuzhiyun SND_SOC_DAPM_PGA("Left Out 1", WM8750_PWR2, 6, 0, NULL, 0),
290*4882a593Smuzhiyun SND_SOC_DAPM_DAC("Right DAC", "Right Playback", WM8750_PWR2, 7, 0),
291*4882a593Smuzhiyun SND_SOC_DAPM_DAC("Left DAC", "Left Playback", WM8750_PWR2, 8, 0),
292*4882a593Smuzhiyun
293*4882a593Smuzhiyun SND_SOC_DAPM_MICBIAS("Mic Bias", WM8750_PWR1, 1, 0),
294*4882a593Smuzhiyun SND_SOC_DAPM_ADC("Right ADC", "Right Capture", WM8750_PWR1, 2, 0),
295*4882a593Smuzhiyun SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8750_PWR1, 3, 0),
296*4882a593Smuzhiyun
297*4882a593Smuzhiyun SND_SOC_DAPM_MUX("Left PGA Mux", WM8750_PWR1, 5, 0,
298*4882a593Smuzhiyun &wm8750_left_pga_controls),
299*4882a593Smuzhiyun SND_SOC_DAPM_MUX("Right PGA Mux", WM8750_PWR1, 4, 0,
300*4882a593Smuzhiyun &wm8750_right_pga_controls),
301*4882a593Smuzhiyun SND_SOC_DAPM_MUX("Left Line Mux", SND_SOC_NOPM, 0, 0,
302*4882a593Smuzhiyun &wm8750_left_line_controls),
303*4882a593Smuzhiyun SND_SOC_DAPM_MUX("Right Line Mux", SND_SOC_NOPM, 0, 0,
304*4882a593Smuzhiyun &wm8750_right_line_controls),
305*4882a593Smuzhiyun
306*4882a593Smuzhiyun SND_SOC_DAPM_MUX("Out3 Mux", SND_SOC_NOPM, 0, 0, &wm8750_out3_controls),
307*4882a593Smuzhiyun SND_SOC_DAPM_PGA("Out 3", WM8750_PWR2, 1, 0, NULL, 0),
308*4882a593Smuzhiyun SND_SOC_DAPM_PGA("Mono Out 1", WM8750_PWR2, 2, 0, NULL, 0),
309*4882a593Smuzhiyun
310*4882a593Smuzhiyun SND_SOC_DAPM_MUX("Differential Mux", SND_SOC_NOPM, 0, 0,
311*4882a593Smuzhiyun &wm8750_diffmux_controls),
312*4882a593Smuzhiyun SND_SOC_DAPM_MUX("Left ADC Mux", SND_SOC_NOPM, 0, 0,
313*4882a593Smuzhiyun &wm8750_monomux_controls),
314*4882a593Smuzhiyun SND_SOC_DAPM_MUX("Right ADC Mux", SND_SOC_NOPM, 0, 0,
315*4882a593Smuzhiyun &wm8750_monomux_controls),
316*4882a593Smuzhiyun
317*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("LOUT1"),
318*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("ROUT1"),
319*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("LOUT2"),
320*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("ROUT2"),
321*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("MONO1"),
322*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("OUT3"),
323*4882a593Smuzhiyun SND_SOC_DAPM_VMID("VREF"),
324*4882a593Smuzhiyun
325*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("LINPUT1"),
326*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("LINPUT2"),
327*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("LINPUT3"),
328*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("RINPUT1"),
329*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("RINPUT2"),
330*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("RINPUT3"),
331*4882a593Smuzhiyun };
332*4882a593Smuzhiyun
333*4882a593Smuzhiyun static const struct snd_soc_dapm_route wm8750_dapm_routes[] = {
334*4882a593Smuzhiyun /* left mixer */
335*4882a593Smuzhiyun {"Left Mixer", "Playback Switch", "Left DAC"},
336*4882a593Smuzhiyun {"Left Mixer", "Left Bypass Switch", "Left Line Mux"},
337*4882a593Smuzhiyun {"Left Mixer", "Right Playback Switch", "Right DAC"},
338*4882a593Smuzhiyun {"Left Mixer", "Right Bypass Switch", "Right Line Mux"},
339*4882a593Smuzhiyun
340*4882a593Smuzhiyun /* right mixer */
341*4882a593Smuzhiyun {"Right Mixer", "Left Playback Switch", "Left DAC"},
342*4882a593Smuzhiyun {"Right Mixer", "Left Bypass Switch", "Left Line Mux"},
343*4882a593Smuzhiyun {"Right Mixer", "Playback Switch", "Right DAC"},
344*4882a593Smuzhiyun {"Right Mixer", "Right Bypass Switch", "Right Line Mux"},
345*4882a593Smuzhiyun
346*4882a593Smuzhiyun /* left out 1 */
347*4882a593Smuzhiyun {"Left Out 1", NULL, "Left Mixer"},
348*4882a593Smuzhiyun {"LOUT1", NULL, "Left Out 1"},
349*4882a593Smuzhiyun
350*4882a593Smuzhiyun /* left out 2 */
351*4882a593Smuzhiyun {"Left Out 2", NULL, "Left Mixer"},
352*4882a593Smuzhiyun {"LOUT2", NULL, "Left Out 2"},
353*4882a593Smuzhiyun
354*4882a593Smuzhiyun /* right out 1 */
355*4882a593Smuzhiyun {"Right Out 1", NULL, "Right Mixer"},
356*4882a593Smuzhiyun {"ROUT1", NULL, "Right Out 1"},
357*4882a593Smuzhiyun
358*4882a593Smuzhiyun /* right out 2 */
359*4882a593Smuzhiyun {"Right Out 2", NULL, "Right Mixer"},
360*4882a593Smuzhiyun {"ROUT2", NULL, "Right Out 2"},
361*4882a593Smuzhiyun
362*4882a593Smuzhiyun /* mono mixer */
363*4882a593Smuzhiyun {"Mono Mixer", "Left Playback Switch", "Left DAC"},
364*4882a593Smuzhiyun {"Mono Mixer", "Left Bypass Switch", "Left Line Mux"},
365*4882a593Smuzhiyun {"Mono Mixer", "Right Playback Switch", "Right DAC"},
366*4882a593Smuzhiyun {"Mono Mixer", "Right Bypass Switch", "Right Line Mux"},
367*4882a593Smuzhiyun
368*4882a593Smuzhiyun /* mono out */
369*4882a593Smuzhiyun {"Mono Out 1", NULL, "Mono Mixer"},
370*4882a593Smuzhiyun {"MONO1", NULL, "Mono Out 1"},
371*4882a593Smuzhiyun
372*4882a593Smuzhiyun /* out 3 */
373*4882a593Smuzhiyun {"Out3 Mux", "VREF", "VREF"},
374*4882a593Smuzhiyun {"Out3 Mux", "ROUT1 + Vol", "ROUT1"},
375*4882a593Smuzhiyun {"Out3 Mux", "ROUT1", "Right Mixer"},
376*4882a593Smuzhiyun {"Out3 Mux", "MonoOut", "MONO1"},
377*4882a593Smuzhiyun {"Out 3", NULL, "Out3 Mux"},
378*4882a593Smuzhiyun {"OUT3", NULL, "Out 3"},
379*4882a593Smuzhiyun
380*4882a593Smuzhiyun /* Left Line Mux */
381*4882a593Smuzhiyun {"Left Line Mux", "Line 1", "LINPUT1"},
382*4882a593Smuzhiyun {"Left Line Mux", "Line 2", "LINPUT2"},
383*4882a593Smuzhiyun {"Left Line Mux", "Line 3", "LINPUT3"},
384*4882a593Smuzhiyun {"Left Line Mux", "PGA", "Left PGA Mux"},
385*4882a593Smuzhiyun {"Left Line Mux", "Differential", "Differential Mux"},
386*4882a593Smuzhiyun
387*4882a593Smuzhiyun /* Right Line Mux */
388*4882a593Smuzhiyun {"Right Line Mux", "Line 1", "RINPUT1"},
389*4882a593Smuzhiyun {"Right Line Mux", "Line 2", "RINPUT2"},
390*4882a593Smuzhiyun {"Right Line Mux", "Line 3", "RINPUT3"},
391*4882a593Smuzhiyun {"Right Line Mux", "PGA", "Right PGA Mux"},
392*4882a593Smuzhiyun {"Right Line Mux", "Differential", "Differential Mux"},
393*4882a593Smuzhiyun
394*4882a593Smuzhiyun /* Left PGA Mux */
395*4882a593Smuzhiyun {"Left PGA Mux", "Line 1", "LINPUT1"},
396*4882a593Smuzhiyun {"Left PGA Mux", "Line 2", "LINPUT2"},
397*4882a593Smuzhiyun {"Left PGA Mux", "Line 3", "LINPUT3"},
398*4882a593Smuzhiyun {"Left PGA Mux", "Differential", "Differential Mux"},
399*4882a593Smuzhiyun
400*4882a593Smuzhiyun /* Right PGA Mux */
401*4882a593Smuzhiyun {"Right PGA Mux", "Line 1", "RINPUT1"},
402*4882a593Smuzhiyun {"Right PGA Mux", "Line 2", "RINPUT2"},
403*4882a593Smuzhiyun {"Right PGA Mux", "Line 3", "RINPUT3"},
404*4882a593Smuzhiyun {"Right PGA Mux", "Differential", "Differential Mux"},
405*4882a593Smuzhiyun
406*4882a593Smuzhiyun /* Differential Mux */
407*4882a593Smuzhiyun {"Differential Mux", "Line 1", "LINPUT1"},
408*4882a593Smuzhiyun {"Differential Mux", "Line 1", "RINPUT1"},
409*4882a593Smuzhiyun {"Differential Mux", "Line 2", "LINPUT2"},
410*4882a593Smuzhiyun {"Differential Mux", "Line 2", "RINPUT2"},
411*4882a593Smuzhiyun
412*4882a593Smuzhiyun /* Left ADC Mux */
413*4882a593Smuzhiyun {"Left ADC Mux", "Stereo", "Left PGA Mux"},
414*4882a593Smuzhiyun {"Left ADC Mux", "Mono (Left)", "Left PGA Mux"},
415*4882a593Smuzhiyun {"Left ADC Mux", "Digital Mono", "Left PGA Mux"},
416*4882a593Smuzhiyun
417*4882a593Smuzhiyun /* Right ADC Mux */
418*4882a593Smuzhiyun {"Right ADC Mux", "Stereo", "Right PGA Mux"},
419*4882a593Smuzhiyun {"Right ADC Mux", "Mono (Right)", "Right PGA Mux"},
420*4882a593Smuzhiyun {"Right ADC Mux", "Digital Mono", "Right PGA Mux"},
421*4882a593Smuzhiyun
422*4882a593Smuzhiyun /* ADC */
423*4882a593Smuzhiyun {"Left ADC", NULL, "Left ADC Mux"},
424*4882a593Smuzhiyun {"Right ADC", NULL, "Right ADC Mux"},
425*4882a593Smuzhiyun };
426*4882a593Smuzhiyun
427*4882a593Smuzhiyun struct _coeff_div {
428*4882a593Smuzhiyun u32 mclk;
429*4882a593Smuzhiyun u32 rate;
430*4882a593Smuzhiyun u16 fs;
431*4882a593Smuzhiyun u8 sr:5;
432*4882a593Smuzhiyun u8 usb:1;
433*4882a593Smuzhiyun };
434*4882a593Smuzhiyun
435*4882a593Smuzhiyun /* codec hifi mclk clock divider coefficients */
436*4882a593Smuzhiyun static const struct _coeff_div coeff_div[] = {
437*4882a593Smuzhiyun /* 8k */
438*4882a593Smuzhiyun {12288000, 8000, 1536, 0x6, 0x0},
439*4882a593Smuzhiyun {11289600, 8000, 1408, 0x16, 0x0},
440*4882a593Smuzhiyun {18432000, 8000, 2304, 0x7, 0x0},
441*4882a593Smuzhiyun {16934400, 8000, 2112, 0x17, 0x0},
442*4882a593Smuzhiyun {12000000, 8000, 1500, 0x6, 0x1},
443*4882a593Smuzhiyun
444*4882a593Smuzhiyun /* 11.025k */
445*4882a593Smuzhiyun {11289600, 11025, 1024, 0x18, 0x0},
446*4882a593Smuzhiyun {16934400, 11025, 1536, 0x19, 0x0},
447*4882a593Smuzhiyun {12000000, 11025, 1088, 0x19, 0x1},
448*4882a593Smuzhiyun
449*4882a593Smuzhiyun /* 16k */
450*4882a593Smuzhiyun {12288000, 16000, 768, 0xa, 0x0},
451*4882a593Smuzhiyun {18432000, 16000, 1152, 0xb, 0x0},
452*4882a593Smuzhiyun {12000000, 16000, 750, 0xa, 0x1},
453*4882a593Smuzhiyun
454*4882a593Smuzhiyun /* 22.05k */
455*4882a593Smuzhiyun {11289600, 22050, 512, 0x1a, 0x0},
456*4882a593Smuzhiyun {16934400, 22050, 768, 0x1b, 0x0},
457*4882a593Smuzhiyun {12000000, 22050, 544, 0x1b, 0x1},
458*4882a593Smuzhiyun
459*4882a593Smuzhiyun /* 32k */
460*4882a593Smuzhiyun {12288000, 32000, 384, 0xc, 0x0},
461*4882a593Smuzhiyun {18432000, 32000, 576, 0xd, 0x0},
462*4882a593Smuzhiyun {12000000, 32000, 375, 0xa, 0x1},
463*4882a593Smuzhiyun
464*4882a593Smuzhiyun /* 44.1k */
465*4882a593Smuzhiyun {11289600, 44100, 256, 0x10, 0x0},
466*4882a593Smuzhiyun {16934400, 44100, 384, 0x11, 0x0},
467*4882a593Smuzhiyun {12000000, 44100, 272, 0x11, 0x1},
468*4882a593Smuzhiyun
469*4882a593Smuzhiyun /* 48k */
470*4882a593Smuzhiyun {12288000, 48000, 256, 0x0, 0x0},
471*4882a593Smuzhiyun {18432000, 48000, 384, 0x1, 0x0},
472*4882a593Smuzhiyun {12000000, 48000, 250, 0x0, 0x1},
473*4882a593Smuzhiyun
474*4882a593Smuzhiyun /* 88.2k */
475*4882a593Smuzhiyun {11289600, 88200, 128, 0x1e, 0x0},
476*4882a593Smuzhiyun {16934400, 88200, 192, 0x1f, 0x0},
477*4882a593Smuzhiyun {12000000, 88200, 136, 0x1f, 0x1},
478*4882a593Smuzhiyun
479*4882a593Smuzhiyun /* 96k */
480*4882a593Smuzhiyun {12288000, 96000, 128, 0xe, 0x0},
481*4882a593Smuzhiyun {18432000, 96000, 192, 0xf, 0x0},
482*4882a593Smuzhiyun {12000000, 96000, 125, 0xe, 0x1},
483*4882a593Smuzhiyun };
484*4882a593Smuzhiyun
get_coeff(int mclk,int rate)485*4882a593Smuzhiyun static inline int get_coeff(int mclk, int rate)
486*4882a593Smuzhiyun {
487*4882a593Smuzhiyun int i;
488*4882a593Smuzhiyun
489*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(coeff_div); i++) {
490*4882a593Smuzhiyun if (coeff_div[i].rate == rate && coeff_div[i].mclk == mclk)
491*4882a593Smuzhiyun return i;
492*4882a593Smuzhiyun }
493*4882a593Smuzhiyun
494*4882a593Smuzhiyun printk(KERN_ERR "wm8750: could not get coeff for mclk %d @ rate %d\n",
495*4882a593Smuzhiyun mclk, rate);
496*4882a593Smuzhiyun return -EINVAL;
497*4882a593Smuzhiyun }
498*4882a593Smuzhiyun
wm8750_set_dai_sysclk(struct snd_soc_dai * codec_dai,int clk_id,unsigned int freq,int dir)499*4882a593Smuzhiyun static int wm8750_set_dai_sysclk(struct snd_soc_dai *codec_dai,
500*4882a593Smuzhiyun int clk_id, unsigned int freq, int dir)
501*4882a593Smuzhiyun {
502*4882a593Smuzhiyun struct snd_soc_component *component = codec_dai->component;
503*4882a593Smuzhiyun struct wm8750_priv *wm8750 = snd_soc_component_get_drvdata(component);
504*4882a593Smuzhiyun
505*4882a593Smuzhiyun switch (freq) {
506*4882a593Smuzhiyun case 11289600:
507*4882a593Smuzhiyun case 12000000:
508*4882a593Smuzhiyun case 12288000:
509*4882a593Smuzhiyun case 16934400:
510*4882a593Smuzhiyun case 18432000:
511*4882a593Smuzhiyun wm8750->sysclk = freq;
512*4882a593Smuzhiyun return 0;
513*4882a593Smuzhiyun }
514*4882a593Smuzhiyun return -EINVAL;
515*4882a593Smuzhiyun }
516*4882a593Smuzhiyun
wm8750_set_dai_fmt(struct snd_soc_dai * codec_dai,unsigned int fmt)517*4882a593Smuzhiyun static int wm8750_set_dai_fmt(struct snd_soc_dai *codec_dai,
518*4882a593Smuzhiyun unsigned int fmt)
519*4882a593Smuzhiyun {
520*4882a593Smuzhiyun struct snd_soc_component *component = codec_dai->component;
521*4882a593Smuzhiyun u16 iface = 0;
522*4882a593Smuzhiyun
523*4882a593Smuzhiyun /* set master/slave audio interface */
524*4882a593Smuzhiyun switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
525*4882a593Smuzhiyun case SND_SOC_DAIFMT_CBM_CFM:
526*4882a593Smuzhiyun iface = 0x0040;
527*4882a593Smuzhiyun break;
528*4882a593Smuzhiyun case SND_SOC_DAIFMT_CBS_CFS:
529*4882a593Smuzhiyun break;
530*4882a593Smuzhiyun default:
531*4882a593Smuzhiyun return -EINVAL;
532*4882a593Smuzhiyun }
533*4882a593Smuzhiyun
534*4882a593Smuzhiyun /* interface format */
535*4882a593Smuzhiyun switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
536*4882a593Smuzhiyun case SND_SOC_DAIFMT_I2S:
537*4882a593Smuzhiyun iface |= 0x0002;
538*4882a593Smuzhiyun break;
539*4882a593Smuzhiyun case SND_SOC_DAIFMT_RIGHT_J:
540*4882a593Smuzhiyun break;
541*4882a593Smuzhiyun case SND_SOC_DAIFMT_LEFT_J:
542*4882a593Smuzhiyun iface |= 0x0001;
543*4882a593Smuzhiyun break;
544*4882a593Smuzhiyun case SND_SOC_DAIFMT_DSP_A:
545*4882a593Smuzhiyun iface |= 0x0003;
546*4882a593Smuzhiyun break;
547*4882a593Smuzhiyun case SND_SOC_DAIFMT_DSP_B:
548*4882a593Smuzhiyun iface |= 0x0013;
549*4882a593Smuzhiyun break;
550*4882a593Smuzhiyun default:
551*4882a593Smuzhiyun return -EINVAL;
552*4882a593Smuzhiyun }
553*4882a593Smuzhiyun
554*4882a593Smuzhiyun /* clock inversion */
555*4882a593Smuzhiyun switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
556*4882a593Smuzhiyun case SND_SOC_DAIFMT_NB_NF:
557*4882a593Smuzhiyun break;
558*4882a593Smuzhiyun case SND_SOC_DAIFMT_IB_IF:
559*4882a593Smuzhiyun iface |= 0x0090;
560*4882a593Smuzhiyun break;
561*4882a593Smuzhiyun case SND_SOC_DAIFMT_IB_NF:
562*4882a593Smuzhiyun iface |= 0x0080;
563*4882a593Smuzhiyun break;
564*4882a593Smuzhiyun case SND_SOC_DAIFMT_NB_IF:
565*4882a593Smuzhiyun iface |= 0x0010;
566*4882a593Smuzhiyun break;
567*4882a593Smuzhiyun default:
568*4882a593Smuzhiyun return -EINVAL;
569*4882a593Smuzhiyun }
570*4882a593Smuzhiyun
571*4882a593Smuzhiyun snd_soc_component_write(component, WM8750_IFACE, iface);
572*4882a593Smuzhiyun return 0;
573*4882a593Smuzhiyun }
574*4882a593Smuzhiyun
wm8750_pcm_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)575*4882a593Smuzhiyun static int wm8750_pcm_hw_params(struct snd_pcm_substream *substream,
576*4882a593Smuzhiyun struct snd_pcm_hw_params *params,
577*4882a593Smuzhiyun struct snd_soc_dai *dai)
578*4882a593Smuzhiyun {
579*4882a593Smuzhiyun struct snd_soc_component *component = dai->component;
580*4882a593Smuzhiyun struct wm8750_priv *wm8750 = snd_soc_component_get_drvdata(component);
581*4882a593Smuzhiyun u16 iface = snd_soc_component_read(component, WM8750_IFACE) & 0x1f3;
582*4882a593Smuzhiyun u16 srate = snd_soc_component_read(component, WM8750_SRATE) & 0x1c0;
583*4882a593Smuzhiyun int coeff = get_coeff(wm8750->sysclk, params_rate(params));
584*4882a593Smuzhiyun
585*4882a593Smuzhiyun /* bit size */
586*4882a593Smuzhiyun switch (params_width(params)) {
587*4882a593Smuzhiyun case 16:
588*4882a593Smuzhiyun break;
589*4882a593Smuzhiyun case 20:
590*4882a593Smuzhiyun iface |= 0x0004;
591*4882a593Smuzhiyun break;
592*4882a593Smuzhiyun case 24:
593*4882a593Smuzhiyun iface |= 0x0008;
594*4882a593Smuzhiyun break;
595*4882a593Smuzhiyun case 32:
596*4882a593Smuzhiyun iface |= 0x000c;
597*4882a593Smuzhiyun break;
598*4882a593Smuzhiyun }
599*4882a593Smuzhiyun
600*4882a593Smuzhiyun /* set iface & srate */
601*4882a593Smuzhiyun snd_soc_component_write(component, WM8750_IFACE, iface);
602*4882a593Smuzhiyun if (coeff >= 0)
603*4882a593Smuzhiyun snd_soc_component_write(component, WM8750_SRATE, srate |
604*4882a593Smuzhiyun (coeff_div[coeff].sr << 1) | coeff_div[coeff].usb);
605*4882a593Smuzhiyun
606*4882a593Smuzhiyun return 0;
607*4882a593Smuzhiyun }
608*4882a593Smuzhiyun
wm8750_mute(struct snd_soc_dai * dai,int mute,int direction)609*4882a593Smuzhiyun static int wm8750_mute(struct snd_soc_dai *dai, int mute, int direction)
610*4882a593Smuzhiyun {
611*4882a593Smuzhiyun struct snd_soc_component *component = dai->component;
612*4882a593Smuzhiyun u16 mute_reg = snd_soc_component_read(component, WM8750_ADCDAC) & 0xfff7;
613*4882a593Smuzhiyun
614*4882a593Smuzhiyun if (mute)
615*4882a593Smuzhiyun snd_soc_component_write(component, WM8750_ADCDAC, mute_reg | 0x8);
616*4882a593Smuzhiyun else
617*4882a593Smuzhiyun snd_soc_component_write(component, WM8750_ADCDAC, mute_reg);
618*4882a593Smuzhiyun return 0;
619*4882a593Smuzhiyun }
620*4882a593Smuzhiyun
wm8750_set_bias_level(struct snd_soc_component * component,enum snd_soc_bias_level level)621*4882a593Smuzhiyun static int wm8750_set_bias_level(struct snd_soc_component *component,
622*4882a593Smuzhiyun enum snd_soc_bias_level level)
623*4882a593Smuzhiyun {
624*4882a593Smuzhiyun u16 pwr_reg = snd_soc_component_read(component, WM8750_PWR1) & 0xfe3e;
625*4882a593Smuzhiyun
626*4882a593Smuzhiyun switch (level) {
627*4882a593Smuzhiyun case SND_SOC_BIAS_ON:
628*4882a593Smuzhiyun /* set vmid to 50k and unmute dac */
629*4882a593Smuzhiyun snd_soc_component_write(component, WM8750_PWR1, pwr_reg | 0x00c0);
630*4882a593Smuzhiyun break;
631*4882a593Smuzhiyun case SND_SOC_BIAS_PREPARE:
632*4882a593Smuzhiyun break;
633*4882a593Smuzhiyun case SND_SOC_BIAS_STANDBY:
634*4882a593Smuzhiyun if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
635*4882a593Smuzhiyun snd_soc_component_cache_sync(component);
636*4882a593Smuzhiyun
637*4882a593Smuzhiyun /* Set VMID to 5k */
638*4882a593Smuzhiyun snd_soc_component_write(component, WM8750_PWR1, pwr_reg | 0x01c1);
639*4882a593Smuzhiyun
640*4882a593Smuzhiyun /* ...and ramp */
641*4882a593Smuzhiyun msleep(1000);
642*4882a593Smuzhiyun }
643*4882a593Smuzhiyun
644*4882a593Smuzhiyun /* mute dac and set vmid to 500k, enable VREF */
645*4882a593Smuzhiyun snd_soc_component_write(component, WM8750_PWR1, pwr_reg | 0x0141);
646*4882a593Smuzhiyun break;
647*4882a593Smuzhiyun case SND_SOC_BIAS_OFF:
648*4882a593Smuzhiyun snd_soc_component_write(component, WM8750_PWR1, 0x0001);
649*4882a593Smuzhiyun break;
650*4882a593Smuzhiyun }
651*4882a593Smuzhiyun return 0;
652*4882a593Smuzhiyun }
653*4882a593Smuzhiyun
654*4882a593Smuzhiyun #define WM8750_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
655*4882a593Smuzhiyun SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_44100 | \
656*4882a593Smuzhiyun SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
657*4882a593Smuzhiyun
658*4882a593Smuzhiyun #define WM8750_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
659*4882a593Smuzhiyun SNDRV_PCM_FMTBIT_S24_LE)
660*4882a593Smuzhiyun
661*4882a593Smuzhiyun static const struct snd_soc_dai_ops wm8750_dai_ops = {
662*4882a593Smuzhiyun .hw_params = wm8750_pcm_hw_params,
663*4882a593Smuzhiyun .mute_stream = wm8750_mute,
664*4882a593Smuzhiyun .set_fmt = wm8750_set_dai_fmt,
665*4882a593Smuzhiyun .set_sysclk = wm8750_set_dai_sysclk,
666*4882a593Smuzhiyun .no_capture_mute = 1,
667*4882a593Smuzhiyun };
668*4882a593Smuzhiyun
669*4882a593Smuzhiyun static struct snd_soc_dai_driver wm8750_dai = {
670*4882a593Smuzhiyun .name = "wm8750-hifi",
671*4882a593Smuzhiyun .playback = {
672*4882a593Smuzhiyun .stream_name = "Playback",
673*4882a593Smuzhiyun .channels_min = 1,
674*4882a593Smuzhiyun .channels_max = 2,
675*4882a593Smuzhiyun .rates = WM8750_RATES,
676*4882a593Smuzhiyun .formats = WM8750_FORMATS,},
677*4882a593Smuzhiyun .capture = {
678*4882a593Smuzhiyun .stream_name = "Capture",
679*4882a593Smuzhiyun .channels_min = 1,
680*4882a593Smuzhiyun .channels_max = 2,
681*4882a593Smuzhiyun .rates = WM8750_RATES,
682*4882a593Smuzhiyun .formats = WM8750_FORMATS,},
683*4882a593Smuzhiyun .ops = &wm8750_dai_ops,
684*4882a593Smuzhiyun };
685*4882a593Smuzhiyun
wm8750_probe(struct snd_soc_component * component)686*4882a593Smuzhiyun static int wm8750_probe(struct snd_soc_component *component)
687*4882a593Smuzhiyun {
688*4882a593Smuzhiyun int ret;
689*4882a593Smuzhiyun
690*4882a593Smuzhiyun ret = wm8750_reset(component);
691*4882a593Smuzhiyun if (ret < 0) {
692*4882a593Smuzhiyun printk(KERN_ERR "wm8750: failed to reset: %d\n", ret);
693*4882a593Smuzhiyun return ret;
694*4882a593Smuzhiyun }
695*4882a593Smuzhiyun
696*4882a593Smuzhiyun /* set the update bits */
697*4882a593Smuzhiyun snd_soc_component_update_bits(component, WM8750_LDAC, 0x0100, 0x0100);
698*4882a593Smuzhiyun snd_soc_component_update_bits(component, WM8750_RDAC, 0x0100, 0x0100);
699*4882a593Smuzhiyun snd_soc_component_update_bits(component, WM8750_LOUT1V, 0x0100, 0x0100);
700*4882a593Smuzhiyun snd_soc_component_update_bits(component, WM8750_ROUT1V, 0x0100, 0x0100);
701*4882a593Smuzhiyun snd_soc_component_update_bits(component, WM8750_LOUT2V, 0x0100, 0x0100);
702*4882a593Smuzhiyun snd_soc_component_update_bits(component, WM8750_ROUT2V, 0x0100, 0x0100);
703*4882a593Smuzhiyun snd_soc_component_update_bits(component, WM8750_LINVOL, 0x0100, 0x0100);
704*4882a593Smuzhiyun snd_soc_component_update_bits(component, WM8750_RINVOL, 0x0100, 0x0100);
705*4882a593Smuzhiyun
706*4882a593Smuzhiyun return ret;
707*4882a593Smuzhiyun }
708*4882a593Smuzhiyun
709*4882a593Smuzhiyun static const struct snd_soc_component_driver soc_component_dev_wm8750 = {
710*4882a593Smuzhiyun .probe = wm8750_probe,
711*4882a593Smuzhiyun .set_bias_level = wm8750_set_bias_level,
712*4882a593Smuzhiyun .controls = wm8750_snd_controls,
713*4882a593Smuzhiyun .num_controls = ARRAY_SIZE(wm8750_snd_controls),
714*4882a593Smuzhiyun .dapm_widgets = wm8750_dapm_widgets,
715*4882a593Smuzhiyun .num_dapm_widgets = ARRAY_SIZE(wm8750_dapm_widgets),
716*4882a593Smuzhiyun .dapm_routes = wm8750_dapm_routes,
717*4882a593Smuzhiyun .num_dapm_routes = ARRAY_SIZE(wm8750_dapm_routes),
718*4882a593Smuzhiyun .suspend_bias_off = 1,
719*4882a593Smuzhiyun .idle_bias_on = 1,
720*4882a593Smuzhiyun .use_pmdown_time = 1,
721*4882a593Smuzhiyun .endianness = 1,
722*4882a593Smuzhiyun .non_legacy_dai_naming = 1,
723*4882a593Smuzhiyun };
724*4882a593Smuzhiyun
725*4882a593Smuzhiyun static const struct of_device_id wm8750_of_match[] = {
726*4882a593Smuzhiyun { .compatible = "wlf,wm8750", },
727*4882a593Smuzhiyun { .compatible = "wlf,wm8987", },
728*4882a593Smuzhiyun { }
729*4882a593Smuzhiyun };
730*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, wm8750_of_match);
731*4882a593Smuzhiyun
732*4882a593Smuzhiyun static const struct regmap_config wm8750_regmap = {
733*4882a593Smuzhiyun .reg_bits = 7,
734*4882a593Smuzhiyun .val_bits = 9,
735*4882a593Smuzhiyun .max_register = WM8750_MOUTV,
736*4882a593Smuzhiyun
737*4882a593Smuzhiyun .reg_defaults = wm8750_reg_defaults,
738*4882a593Smuzhiyun .num_reg_defaults = ARRAY_SIZE(wm8750_reg_defaults),
739*4882a593Smuzhiyun .cache_type = REGCACHE_RBTREE,
740*4882a593Smuzhiyun };
741*4882a593Smuzhiyun
742*4882a593Smuzhiyun #if defined(CONFIG_SPI_MASTER)
wm8750_spi_probe(struct spi_device * spi)743*4882a593Smuzhiyun static int wm8750_spi_probe(struct spi_device *spi)
744*4882a593Smuzhiyun {
745*4882a593Smuzhiyun struct wm8750_priv *wm8750;
746*4882a593Smuzhiyun struct regmap *regmap;
747*4882a593Smuzhiyun int ret;
748*4882a593Smuzhiyun
749*4882a593Smuzhiyun wm8750 = devm_kzalloc(&spi->dev, sizeof(struct wm8750_priv),
750*4882a593Smuzhiyun GFP_KERNEL);
751*4882a593Smuzhiyun if (wm8750 == NULL)
752*4882a593Smuzhiyun return -ENOMEM;
753*4882a593Smuzhiyun
754*4882a593Smuzhiyun regmap = devm_regmap_init_spi(spi, &wm8750_regmap);
755*4882a593Smuzhiyun if (IS_ERR(regmap))
756*4882a593Smuzhiyun return PTR_ERR(regmap);
757*4882a593Smuzhiyun
758*4882a593Smuzhiyun spi_set_drvdata(spi, wm8750);
759*4882a593Smuzhiyun
760*4882a593Smuzhiyun ret = devm_snd_soc_register_component(&spi->dev,
761*4882a593Smuzhiyun &soc_component_dev_wm8750, &wm8750_dai, 1);
762*4882a593Smuzhiyun return ret;
763*4882a593Smuzhiyun }
764*4882a593Smuzhiyun
765*4882a593Smuzhiyun static const struct spi_device_id wm8750_spi_ids[] = {
766*4882a593Smuzhiyun { "wm8750", 0 },
767*4882a593Smuzhiyun { "wm8987", 0 },
768*4882a593Smuzhiyun { },
769*4882a593Smuzhiyun };
770*4882a593Smuzhiyun MODULE_DEVICE_TABLE(spi, wm8750_spi_ids);
771*4882a593Smuzhiyun
772*4882a593Smuzhiyun static struct spi_driver wm8750_spi_driver = {
773*4882a593Smuzhiyun .driver = {
774*4882a593Smuzhiyun .name = "wm8750",
775*4882a593Smuzhiyun .of_match_table = wm8750_of_match,
776*4882a593Smuzhiyun },
777*4882a593Smuzhiyun .id_table = wm8750_spi_ids,
778*4882a593Smuzhiyun .probe = wm8750_spi_probe,
779*4882a593Smuzhiyun };
780*4882a593Smuzhiyun #endif /* CONFIG_SPI_MASTER */
781*4882a593Smuzhiyun
782*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_I2C)
wm8750_i2c_probe(struct i2c_client * i2c,const struct i2c_device_id * id)783*4882a593Smuzhiyun static int wm8750_i2c_probe(struct i2c_client *i2c,
784*4882a593Smuzhiyun const struct i2c_device_id *id)
785*4882a593Smuzhiyun {
786*4882a593Smuzhiyun struct wm8750_priv *wm8750;
787*4882a593Smuzhiyun struct regmap *regmap;
788*4882a593Smuzhiyun int ret;
789*4882a593Smuzhiyun
790*4882a593Smuzhiyun wm8750 = devm_kzalloc(&i2c->dev, sizeof(struct wm8750_priv),
791*4882a593Smuzhiyun GFP_KERNEL);
792*4882a593Smuzhiyun if (wm8750 == NULL)
793*4882a593Smuzhiyun return -ENOMEM;
794*4882a593Smuzhiyun
795*4882a593Smuzhiyun i2c_set_clientdata(i2c, wm8750);
796*4882a593Smuzhiyun
797*4882a593Smuzhiyun regmap = devm_regmap_init_i2c(i2c, &wm8750_regmap);
798*4882a593Smuzhiyun if (IS_ERR(regmap))
799*4882a593Smuzhiyun return PTR_ERR(regmap);
800*4882a593Smuzhiyun
801*4882a593Smuzhiyun ret = devm_snd_soc_register_component(&i2c->dev,
802*4882a593Smuzhiyun &soc_component_dev_wm8750, &wm8750_dai, 1);
803*4882a593Smuzhiyun return ret;
804*4882a593Smuzhiyun }
805*4882a593Smuzhiyun
806*4882a593Smuzhiyun static const struct i2c_device_id wm8750_i2c_id[] = {
807*4882a593Smuzhiyun { "wm8750", 0 },
808*4882a593Smuzhiyun { "wm8987", 0 },
809*4882a593Smuzhiyun { }
810*4882a593Smuzhiyun };
811*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, wm8750_i2c_id);
812*4882a593Smuzhiyun
813*4882a593Smuzhiyun static struct i2c_driver wm8750_i2c_driver = {
814*4882a593Smuzhiyun .driver = {
815*4882a593Smuzhiyun .name = "wm8750",
816*4882a593Smuzhiyun .of_match_table = wm8750_of_match,
817*4882a593Smuzhiyun },
818*4882a593Smuzhiyun .probe = wm8750_i2c_probe,
819*4882a593Smuzhiyun .id_table = wm8750_i2c_id,
820*4882a593Smuzhiyun };
821*4882a593Smuzhiyun #endif
822*4882a593Smuzhiyun
wm8750_modinit(void)823*4882a593Smuzhiyun static int __init wm8750_modinit(void)
824*4882a593Smuzhiyun {
825*4882a593Smuzhiyun int ret = 0;
826*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_I2C)
827*4882a593Smuzhiyun ret = i2c_add_driver(&wm8750_i2c_driver);
828*4882a593Smuzhiyun if (ret != 0) {
829*4882a593Smuzhiyun printk(KERN_ERR "Failed to register wm8750 I2C driver: %d\n",
830*4882a593Smuzhiyun ret);
831*4882a593Smuzhiyun }
832*4882a593Smuzhiyun #endif
833*4882a593Smuzhiyun #if defined(CONFIG_SPI_MASTER)
834*4882a593Smuzhiyun ret = spi_register_driver(&wm8750_spi_driver);
835*4882a593Smuzhiyun if (ret != 0) {
836*4882a593Smuzhiyun printk(KERN_ERR "Failed to register wm8750 SPI driver: %d\n",
837*4882a593Smuzhiyun ret);
838*4882a593Smuzhiyun }
839*4882a593Smuzhiyun #endif
840*4882a593Smuzhiyun return ret;
841*4882a593Smuzhiyun }
842*4882a593Smuzhiyun module_init(wm8750_modinit);
843*4882a593Smuzhiyun
wm8750_exit(void)844*4882a593Smuzhiyun static void __exit wm8750_exit(void)
845*4882a593Smuzhiyun {
846*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_I2C)
847*4882a593Smuzhiyun i2c_del_driver(&wm8750_i2c_driver);
848*4882a593Smuzhiyun #endif
849*4882a593Smuzhiyun #if defined(CONFIG_SPI_MASTER)
850*4882a593Smuzhiyun spi_unregister_driver(&wm8750_spi_driver);
851*4882a593Smuzhiyun #endif
852*4882a593Smuzhiyun }
853*4882a593Smuzhiyun module_exit(wm8750_exit);
854*4882a593Smuzhiyun
855*4882a593Smuzhiyun MODULE_DESCRIPTION("ASoC WM8750 driver");
856*4882a593Smuzhiyun MODULE_AUTHOR("Liam Girdwood");
857*4882a593Smuzhiyun MODULE_LICENSE("GPL");
858