1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * wm8741.h -- WM8423 ASoC driver 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright 2010 Wolfson Microelectronics, plc 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Author: Ian Lartey <ian@opensource.wolfsonmicro.com> 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * Based on wm8753.h 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #ifndef _WM8741_H 13*4882a593Smuzhiyun #define _WM8741_H 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /* 16*4882a593Smuzhiyun * Register values. 17*4882a593Smuzhiyun */ 18*4882a593Smuzhiyun #define WM8741_DACLLSB_ATTENUATION 0x00 19*4882a593Smuzhiyun #define WM8741_DACLMSB_ATTENUATION 0x01 20*4882a593Smuzhiyun #define WM8741_DACRLSB_ATTENUATION 0x02 21*4882a593Smuzhiyun #define WM8741_DACRMSB_ATTENUATION 0x03 22*4882a593Smuzhiyun #define WM8741_VOLUME_CONTROL 0x04 23*4882a593Smuzhiyun #define WM8741_FORMAT_CONTROL 0x05 24*4882a593Smuzhiyun #define WM8741_FILTER_CONTROL 0x06 25*4882a593Smuzhiyun #define WM8741_MODE_CONTROL_1 0x07 26*4882a593Smuzhiyun #define WM8741_MODE_CONTROL_2 0x08 27*4882a593Smuzhiyun #define WM8741_RESET 0x09 28*4882a593Smuzhiyun #define WM8741_ADDITIONAL_CONTROL_1 0x20 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #define WM8741_REGISTER_COUNT 11 31*4882a593Smuzhiyun #define WM8741_MAX_REGISTER 0x20 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /* 34*4882a593Smuzhiyun * Field Definitions. 35*4882a593Smuzhiyun */ 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /* 38*4882a593Smuzhiyun * R0 (0x00) - DACLLSB_ATTENUATION 39*4882a593Smuzhiyun */ 40*4882a593Smuzhiyun #define WM8741_UPDATELL 0x0020 /* UPDATELL */ 41*4882a593Smuzhiyun #define WM8741_UPDATELL_MASK 0x0020 /* UPDATELL */ 42*4882a593Smuzhiyun #define WM8741_UPDATELL_SHIFT 5 /* UPDATELL */ 43*4882a593Smuzhiyun #define WM8741_UPDATELL_WIDTH 1 /* UPDATELL */ 44*4882a593Smuzhiyun #define WM8741_LAT_4_0_MASK 0x001F /* LAT[4:0] - [4:0] */ 45*4882a593Smuzhiyun #define WM8741_LAT_4_0_SHIFT 0 /* LAT[4:0] - [4:0] */ 46*4882a593Smuzhiyun #define WM8741_LAT_4_0_WIDTH 5 /* LAT[4:0] - [4:0] */ 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun /* 49*4882a593Smuzhiyun * R1 (0x01) - DACLMSB_ATTENUATION 50*4882a593Smuzhiyun */ 51*4882a593Smuzhiyun #define WM8741_UPDATELM 0x0020 /* UPDATELM */ 52*4882a593Smuzhiyun #define WM8741_UPDATELM_MASK 0x0020 /* UPDATELM */ 53*4882a593Smuzhiyun #define WM8741_UPDATELM_SHIFT 5 /* UPDATELM */ 54*4882a593Smuzhiyun #define WM8741_UPDATELM_WIDTH 1 /* UPDATELM */ 55*4882a593Smuzhiyun #define WM8741_LAT_9_5_0_MASK 0x001F /* LAT[9:5] - [4:0] */ 56*4882a593Smuzhiyun #define WM8741_LAT_9_5_0_SHIFT 0 /* LAT[9:5] - [4:0] */ 57*4882a593Smuzhiyun #define WM8741_LAT_9_5_0_WIDTH 5 /* LAT[9:5] - [4:0] */ 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun /* 60*4882a593Smuzhiyun * R2 (0x02) - DACRLSB_ATTENUATION 61*4882a593Smuzhiyun */ 62*4882a593Smuzhiyun #define WM8741_UPDATERL 0x0020 /* UPDATERL */ 63*4882a593Smuzhiyun #define WM8741_UPDATERL_MASK 0x0020 /* UPDATERL */ 64*4882a593Smuzhiyun #define WM8741_UPDATERL_SHIFT 5 /* UPDATERL */ 65*4882a593Smuzhiyun #define WM8741_UPDATERL_WIDTH 1 /* UPDATERL */ 66*4882a593Smuzhiyun #define WM8741_RAT_4_0_MASK 0x001F /* RAT[4:0] - [4:0] */ 67*4882a593Smuzhiyun #define WM8741_RAT_4_0_SHIFT 0 /* RAT[4:0] - [4:0] */ 68*4882a593Smuzhiyun #define WM8741_RAT_4_0_WIDTH 5 /* RAT[4:0] - [4:0] */ 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun /* 71*4882a593Smuzhiyun * R3 (0x03) - DACRMSB_ATTENUATION 72*4882a593Smuzhiyun */ 73*4882a593Smuzhiyun #define WM8741_UPDATERM 0x0020 /* UPDATERM */ 74*4882a593Smuzhiyun #define WM8741_UPDATERM_MASK 0x0020 /* UPDATERM */ 75*4882a593Smuzhiyun #define WM8741_UPDATERM_SHIFT 5 /* UPDATERM */ 76*4882a593Smuzhiyun #define WM8741_UPDATERM_WIDTH 1 /* UPDATERM */ 77*4882a593Smuzhiyun #define WM8741_RAT_9_5_0_MASK 0x001F /* RAT[9:5] - [4:0] */ 78*4882a593Smuzhiyun #define WM8741_RAT_9_5_0_SHIFT 0 /* RAT[9:5] - [4:0] */ 79*4882a593Smuzhiyun #define WM8741_RAT_9_5_0_WIDTH 5 /* RAT[9:5] - [4:0] */ 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun /* 82*4882a593Smuzhiyun * R4 (0x04) - VOLUME_CONTROL 83*4882a593Smuzhiyun */ 84*4882a593Smuzhiyun #define WM8741_AMUTE 0x0080 /* AMUTE */ 85*4882a593Smuzhiyun #define WM8741_AMUTE_MASK 0x0080 /* AMUTE */ 86*4882a593Smuzhiyun #define WM8741_AMUTE_SHIFT 7 /* AMUTE */ 87*4882a593Smuzhiyun #define WM8741_AMUTE_WIDTH 1 /* AMUTE */ 88*4882a593Smuzhiyun #define WM8741_ZFLAG_MASK 0x0060 /* ZFLAG - [6:5] */ 89*4882a593Smuzhiyun #define WM8741_ZFLAG_SHIFT 5 /* ZFLAG - [6:5] */ 90*4882a593Smuzhiyun #define WM8741_ZFLAG_WIDTH 2 /* ZFLAG - [6:5] */ 91*4882a593Smuzhiyun #define WM8741_IZD 0x0010 /* IZD */ 92*4882a593Smuzhiyun #define WM8741_IZD_MASK 0x0010 /* IZD */ 93*4882a593Smuzhiyun #define WM8741_IZD_SHIFT 4 /* IZD */ 94*4882a593Smuzhiyun #define WM8741_IZD_WIDTH 1 /* IZD */ 95*4882a593Smuzhiyun #define WM8741_SOFT 0x0008 /* SOFT MUTE */ 96*4882a593Smuzhiyun #define WM8741_SOFT_MASK 0x0008 /* SOFT MUTE */ 97*4882a593Smuzhiyun #define WM8741_SOFT_SHIFT 3 /* SOFT MUTE */ 98*4882a593Smuzhiyun #define WM8741_SOFT_WIDTH 1 /* SOFT MUTE */ 99*4882a593Smuzhiyun #define WM8741_ATC 0x0004 /* ATC */ 100*4882a593Smuzhiyun #define WM8741_ATC_MASK 0x0004 /* ATC */ 101*4882a593Smuzhiyun #define WM8741_ATC_SHIFT 2 /* ATC */ 102*4882a593Smuzhiyun #define WM8741_ATC_WIDTH 1 /* ATC */ 103*4882a593Smuzhiyun #define WM8741_ATT2DB 0x0002 /* ATT2DB */ 104*4882a593Smuzhiyun #define WM8741_ATT2DB_MASK 0x0002 /* ATT2DB */ 105*4882a593Smuzhiyun #define WM8741_ATT2DB_SHIFT 1 /* ATT2DB */ 106*4882a593Smuzhiyun #define WM8741_ATT2DB_WIDTH 1 /* ATT2DB */ 107*4882a593Smuzhiyun #define WM8741_VOL_RAMP 0x0001 /* VOL_RAMP */ 108*4882a593Smuzhiyun #define WM8741_VOL_RAMP_MASK 0x0001 /* VOL_RAMP */ 109*4882a593Smuzhiyun #define WM8741_VOL_RAMP_SHIFT 0 /* VOL_RAMP */ 110*4882a593Smuzhiyun #define WM8741_VOL_RAMP_WIDTH 1 /* VOL_RAMP */ 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun /* 113*4882a593Smuzhiyun * R5 (0x05) - FORMAT_CONTROL 114*4882a593Smuzhiyun */ 115*4882a593Smuzhiyun #define WM8741_PWDN 0x0080 /* PWDN */ 116*4882a593Smuzhiyun #define WM8741_PWDN_MASK 0x0080 /* PWDN */ 117*4882a593Smuzhiyun #define WM8741_PWDN_SHIFT 7 /* PWDN */ 118*4882a593Smuzhiyun #define WM8741_PWDN_WIDTH 1 /* PWDN */ 119*4882a593Smuzhiyun #define WM8741_REV 0x0040 /* REV */ 120*4882a593Smuzhiyun #define WM8741_REV_MASK 0x0040 /* REV */ 121*4882a593Smuzhiyun #define WM8741_REV_SHIFT 6 /* REV */ 122*4882a593Smuzhiyun #define WM8741_REV_WIDTH 1 /* REV */ 123*4882a593Smuzhiyun #define WM8741_BCP 0x0020 /* BCP */ 124*4882a593Smuzhiyun #define WM8741_BCP_MASK 0x0020 /* BCP */ 125*4882a593Smuzhiyun #define WM8741_BCP_SHIFT 5 /* BCP */ 126*4882a593Smuzhiyun #define WM8741_BCP_WIDTH 1 /* BCP */ 127*4882a593Smuzhiyun #define WM8741_LRP 0x0010 /* LRP */ 128*4882a593Smuzhiyun #define WM8741_LRP_MASK 0x0010 /* LRP */ 129*4882a593Smuzhiyun #define WM8741_LRP_SHIFT 4 /* LRP */ 130*4882a593Smuzhiyun #define WM8741_LRP_WIDTH 1 /* LRP */ 131*4882a593Smuzhiyun #define WM8741_FMT_MASK 0x000C /* FMT - [3:2] */ 132*4882a593Smuzhiyun #define WM8741_FMT_SHIFT 2 /* FMT - [3:2] */ 133*4882a593Smuzhiyun #define WM8741_FMT_WIDTH 2 /* FMT - [3:2] */ 134*4882a593Smuzhiyun #define WM8741_IWL_MASK 0x0003 /* IWL - [1:0] */ 135*4882a593Smuzhiyun #define WM8741_IWL_SHIFT 0 /* IWL - [1:0] */ 136*4882a593Smuzhiyun #define WM8741_IWL_WIDTH 2 /* IWL - [1:0] */ 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun /* 139*4882a593Smuzhiyun * R6 (0x06) - FILTER_CONTROL 140*4882a593Smuzhiyun */ 141*4882a593Smuzhiyun #define WM8741_ZFLAG_HI 0x0080 /* ZFLAG_HI */ 142*4882a593Smuzhiyun #define WM8741_ZFLAG_HI_MASK 0x0080 /* ZFLAG_HI */ 143*4882a593Smuzhiyun #define WM8741_ZFLAG_HI_SHIFT 7 /* ZFLAG_HI */ 144*4882a593Smuzhiyun #define WM8741_ZFLAG_HI_WIDTH 1 /* ZFLAG_HI */ 145*4882a593Smuzhiyun #define WM8741_DEEMPH_MASK 0x0060 /* DEEMPH - [6:5] */ 146*4882a593Smuzhiyun #define WM8741_DEEMPH_SHIFT 5 /* DEEMPH - [6:5] */ 147*4882a593Smuzhiyun #define WM8741_DEEMPH_WIDTH 2 /* DEEMPH - [6:5] */ 148*4882a593Smuzhiyun #define WM8741_DSDFILT_MASK 0x0018 /* DSDFILT - [4:3] */ 149*4882a593Smuzhiyun #define WM8741_DSDFILT_SHIFT 3 /* DSDFILT - [4:3] */ 150*4882a593Smuzhiyun #define WM8741_DSDFILT_WIDTH 2 /* DSDFILT - [4:3] */ 151*4882a593Smuzhiyun #define WM8741_FIRSEL_MASK 0x0007 /* FIRSEL - [2:0] */ 152*4882a593Smuzhiyun #define WM8741_FIRSEL_SHIFT 0 /* FIRSEL - [2:0] */ 153*4882a593Smuzhiyun #define WM8741_FIRSEL_WIDTH 3 /* FIRSEL - [2:0] */ 154*4882a593Smuzhiyun 155*4882a593Smuzhiyun /* 156*4882a593Smuzhiyun * R7 (0x07) - MODE_CONTROL_1 157*4882a593Smuzhiyun */ 158*4882a593Smuzhiyun #define WM8741_MODE8X 0x0080 /* MODE8X */ 159*4882a593Smuzhiyun #define WM8741_MODE8X_MASK 0x0080 /* MODE8X */ 160*4882a593Smuzhiyun #define WM8741_MODE8X_SHIFT 7 /* MODE8X */ 161*4882a593Smuzhiyun #define WM8741_MODE8X_WIDTH 1 /* MODE8X */ 162*4882a593Smuzhiyun #define WM8741_OSR_MASK 0x0060 /* OSR - [6:5] */ 163*4882a593Smuzhiyun #define WM8741_OSR_SHIFT 5 /* OSR - [6:5] */ 164*4882a593Smuzhiyun #define WM8741_OSR_WIDTH 2 /* OSR - [6:5] */ 165*4882a593Smuzhiyun #define WM8741_SR_MASK 0x001C /* SR - [4:2] */ 166*4882a593Smuzhiyun #define WM8741_SR_SHIFT 2 /* SR - [4:2] */ 167*4882a593Smuzhiyun #define WM8741_SR_WIDTH 3 /* SR - [4:2] */ 168*4882a593Smuzhiyun #define WM8741_MODESEL_MASK 0x0003 /* MODESEL - [1:0] */ 169*4882a593Smuzhiyun #define WM8741_MODESEL_SHIFT 0 /* MODESEL - [1:0] */ 170*4882a593Smuzhiyun #define WM8741_MODESEL_WIDTH 2 /* MODESEL - [1:0] */ 171*4882a593Smuzhiyun 172*4882a593Smuzhiyun /* 173*4882a593Smuzhiyun * R8 (0x08) - MODE_CONTROL_2 174*4882a593Smuzhiyun */ 175*4882a593Smuzhiyun #define WM8741_DSD_GAIN 0x0040 /* DSD_GAIN */ 176*4882a593Smuzhiyun #define WM8741_DSD_GAIN_MASK 0x0040 /* DSD_GAIN */ 177*4882a593Smuzhiyun #define WM8741_DSD_GAIN_SHIFT 6 /* DSD_GAIN */ 178*4882a593Smuzhiyun #define WM8741_DSD_GAIN_WIDTH 1 /* DSD_GAIN */ 179*4882a593Smuzhiyun #define WM8741_SDOUT 0x0020 /* SDOUT */ 180*4882a593Smuzhiyun #define WM8741_SDOUT_MASK 0x0020 /* SDOUT */ 181*4882a593Smuzhiyun #define WM8741_SDOUT_SHIFT 5 /* SDOUT */ 182*4882a593Smuzhiyun #define WM8741_SDOUT_WIDTH 1 /* SDOUT */ 183*4882a593Smuzhiyun #define WM8741_DOUT 0x0010 /* DOUT */ 184*4882a593Smuzhiyun #define WM8741_DOUT_MASK 0x0010 /* DOUT */ 185*4882a593Smuzhiyun #define WM8741_DOUT_SHIFT 4 /* DOUT */ 186*4882a593Smuzhiyun #define WM8741_DOUT_WIDTH 1 /* DOUT */ 187*4882a593Smuzhiyun #define WM8741_DIFF_MASK 0x000C /* DIFF - [3:2] */ 188*4882a593Smuzhiyun #define WM8741_DIFF_SHIFT 2 /* DIFF - [3:2] */ 189*4882a593Smuzhiyun #define WM8741_DIFF_WIDTH 2 /* DIFF - [3:2] */ 190*4882a593Smuzhiyun #define WM8741_DITHER_MASK 0x0003 /* DITHER - [1:0] */ 191*4882a593Smuzhiyun #define WM8741_DITHER_SHIFT 0 /* DITHER - [1:0] */ 192*4882a593Smuzhiyun #define WM8741_DITHER_WIDTH 2 /* DITHER - [1:0] */ 193*4882a593Smuzhiyun 194*4882a593Smuzhiyun /* DIFF field values */ 195*4882a593Smuzhiyun #define WM8741_DIFF_MODE_STEREO 0 /* stereo normal */ 196*4882a593Smuzhiyun #define WM8741_DIFF_MODE_STEREO_REVERSED 2 /* stereo reversed */ 197*4882a593Smuzhiyun #define WM8741_DIFF_MODE_MONO_LEFT 1 /* mono left */ 198*4882a593Smuzhiyun #define WM8741_DIFF_MODE_MONO_RIGHT 3 /* mono right */ 199*4882a593Smuzhiyun 200*4882a593Smuzhiyun /* 201*4882a593Smuzhiyun * R32 (0x20) - ADDITONAL_CONTROL_1 202*4882a593Smuzhiyun */ 203*4882a593Smuzhiyun #define WM8741_DSD_LEVEL 0x0002 /* DSD_LEVEL */ 204*4882a593Smuzhiyun #define WM8741_DSD_LEVEL_MASK 0x0002 /* DSD_LEVEL */ 205*4882a593Smuzhiyun #define WM8741_DSD_LEVEL_SHIFT 1 /* DSD_LEVEL */ 206*4882a593Smuzhiyun #define WM8741_DSD_LEVEL_WIDTH 1 /* DSD_LEVEL */ 207*4882a593Smuzhiyun #define WM8741_DSD_NO_NOTCH 0x0001 /* DSD_NO_NOTCH */ 208*4882a593Smuzhiyun #define WM8741_DSD_NO_NOTCH_MASK 0x0001 /* DSD_NO_NOTCH */ 209*4882a593Smuzhiyun #define WM8741_DSD_NO_NOTCH_SHIFT 0 /* DSD_NO_NOTCH */ 210*4882a593Smuzhiyun #define WM8741_DSD_NO_NOTCH_WIDTH 1 /* DSD_NO_NOTCH */ 211*4882a593Smuzhiyun 212*4882a593Smuzhiyun #define WM8741_SYSCLK 0 213*4882a593Smuzhiyun 214*4882a593Smuzhiyun struct wm8741_platform_data { 215*4882a593Smuzhiyun u32 diff_mode; /* Differential Output Mode */ 216*4882a593Smuzhiyun }; 217*4882a593Smuzhiyun 218*4882a593Smuzhiyun #endif 219