1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun #ifndef _WM8737_H 3*4882a593Smuzhiyun #define _WM8737_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun /* 6*4882a593Smuzhiyun * wm8737.c -- WM8523 ALSA SoC Audio driver 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Copyright 2010 Wolfson Microelectronics plc 9*4882a593Smuzhiyun * 10*4882a593Smuzhiyun * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> 11*4882a593Smuzhiyun */ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* 14*4882a593Smuzhiyun * Register values. 15*4882a593Smuzhiyun */ 16*4882a593Smuzhiyun #define WM8737_LEFT_PGA_VOLUME 0x00 17*4882a593Smuzhiyun #define WM8737_RIGHT_PGA_VOLUME 0x01 18*4882a593Smuzhiyun #define WM8737_AUDIO_PATH_L 0x02 19*4882a593Smuzhiyun #define WM8737_AUDIO_PATH_R 0x03 20*4882a593Smuzhiyun #define WM8737_3D_ENHANCE 0x04 21*4882a593Smuzhiyun #define WM8737_ADC_CONTROL 0x05 22*4882a593Smuzhiyun #define WM8737_POWER_MANAGEMENT 0x06 23*4882a593Smuzhiyun #define WM8737_AUDIO_FORMAT 0x07 24*4882a593Smuzhiyun #define WM8737_CLOCKING 0x08 25*4882a593Smuzhiyun #define WM8737_MIC_PREAMP_CONTROL 0x09 26*4882a593Smuzhiyun #define WM8737_MISC_BIAS_CONTROL 0x0A 27*4882a593Smuzhiyun #define WM8737_NOISE_GATE 0x0B 28*4882a593Smuzhiyun #define WM8737_ALC1 0x0C 29*4882a593Smuzhiyun #define WM8737_ALC2 0x0D 30*4882a593Smuzhiyun #define WM8737_ALC3 0x0E 31*4882a593Smuzhiyun #define WM8737_RESET 0x0F 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #define WM8737_REGISTER_COUNT 16 34*4882a593Smuzhiyun #define WM8737_MAX_REGISTER 0x0F 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun /* 37*4882a593Smuzhiyun * Field Definitions. 38*4882a593Smuzhiyun */ 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun /* 41*4882a593Smuzhiyun * R0 (0x00) - Left PGA volume 42*4882a593Smuzhiyun */ 43*4882a593Smuzhiyun #define WM8737_LVU 0x0100 /* LVU */ 44*4882a593Smuzhiyun #define WM8737_LVU_MASK 0x0100 /* LVU */ 45*4882a593Smuzhiyun #define WM8737_LVU_SHIFT 8 /* LVU */ 46*4882a593Smuzhiyun #define WM8737_LVU_WIDTH 1 /* LVU */ 47*4882a593Smuzhiyun #define WM8737_LINVOL_MASK 0x00FF /* LINVOL - [7:0] */ 48*4882a593Smuzhiyun #define WM8737_LINVOL_SHIFT 0 /* LINVOL - [7:0] */ 49*4882a593Smuzhiyun #define WM8737_LINVOL_WIDTH 8 /* LINVOL - [7:0] */ 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun /* 52*4882a593Smuzhiyun * R1 (0x01) - Right PGA volume 53*4882a593Smuzhiyun */ 54*4882a593Smuzhiyun #define WM8737_RVU 0x0100 /* RVU */ 55*4882a593Smuzhiyun #define WM8737_RVU_MASK 0x0100 /* RVU */ 56*4882a593Smuzhiyun #define WM8737_RVU_SHIFT 8 /* RVU */ 57*4882a593Smuzhiyun #define WM8737_RVU_WIDTH 1 /* RVU */ 58*4882a593Smuzhiyun #define WM8737_RINVOL_MASK 0x00FF /* RINVOL - [7:0] */ 59*4882a593Smuzhiyun #define WM8737_RINVOL_SHIFT 0 /* RINVOL - [7:0] */ 60*4882a593Smuzhiyun #define WM8737_RINVOL_WIDTH 8 /* RINVOL - [7:0] */ 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun /* 63*4882a593Smuzhiyun * R2 (0x02) - AUDIO path L 64*4882a593Smuzhiyun */ 65*4882a593Smuzhiyun #define WM8737_LINSEL_MASK 0x0180 /* LINSEL - [8:7] */ 66*4882a593Smuzhiyun #define WM8737_LINSEL_SHIFT 7 /* LINSEL - [8:7] */ 67*4882a593Smuzhiyun #define WM8737_LINSEL_WIDTH 2 /* LINSEL - [8:7] */ 68*4882a593Smuzhiyun #define WM8737_LMICBOOST_MASK 0x0060 /* LMICBOOST - [6:5] */ 69*4882a593Smuzhiyun #define WM8737_LMICBOOST_SHIFT 5 /* LMICBOOST - [6:5] */ 70*4882a593Smuzhiyun #define WM8737_LMICBOOST_WIDTH 2 /* LMICBOOST - [6:5] */ 71*4882a593Smuzhiyun #define WM8737_LMBE 0x0010 /* LMBE */ 72*4882a593Smuzhiyun #define WM8737_LMBE_MASK 0x0010 /* LMBE */ 73*4882a593Smuzhiyun #define WM8737_LMBE_SHIFT 4 /* LMBE */ 74*4882a593Smuzhiyun #define WM8737_LMBE_WIDTH 1 /* LMBE */ 75*4882a593Smuzhiyun #define WM8737_LMZC 0x0008 /* LMZC */ 76*4882a593Smuzhiyun #define WM8737_LMZC_MASK 0x0008 /* LMZC */ 77*4882a593Smuzhiyun #define WM8737_LMZC_SHIFT 3 /* LMZC */ 78*4882a593Smuzhiyun #define WM8737_LMZC_WIDTH 1 /* LMZC */ 79*4882a593Smuzhiyun #define WM8737_LPZC 0x0004 /* LPZC */ 80*4882a593Smuzhiyun #define WM8737_LPZC_MASK 0x0004 /* LPZC */ 81*4882a593Smuzhiyun #define WM8737_LPZC_SHIFT 2 /* LPZC */ 82*4882a593Smuzhiyun #define WM8737_LPZC_WIDTH 1 /* LPZC */ 83*4882a593Smuzhiyun #define WM8737_LZCTO_MASK 0x0003 /* LZCTO - [1:0] */ 84*4882a593Smuzhiyun #define WM8737_LZCTO_SHIFT 0 /* LZCTO - [1:0] */ 85*4882a593Smuzhiyun #define WM8737_LZCTO_WIDTH 2 /* LZCTO - [1:0] */ 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun /* 88*4882a593Smuzhiyun * R3 (0x03) - AUDIO path R 89*4882a593Smuzhiyun */ 90*4882a593Smuzhiyun #define WM8737_RINSEL_MASK 0x0180 /* RINSEL - [8:7] */ 91*4882a593Smuzhiyun #define WM8737_RINSEL_SHIFT 7 /* RINSEL - [8:7] */ 92*4882a593Smuzhiyun #define WM8737_RINSEL_WIDTH 2 /* RINSEL - [8:7] */ 93*4882a593Smuzhiyun #define WM8737_RMICBOOST_MASK 0x0060 /* RMICBOOST - [6:5] */ 94*4882a593Smuzhiyun #define WM8737_RMICBOOST_SHIFT 5 /* RMICBOOST - [6:5] */ 95*4882a593Smuzhiyun #define WM8737_RMICBOOST_WIDTH 2 /* RMICBOOST - [6:5] */ 96*4882a593Smuzhiyun #define WM8737_RMBE 0x0010 /* RMBE */ 97*4882a593Smuzhiyun #define WM8737_RMBE_MASK 0x0010 /* RMBE */ 98*4882a593Smuzhiyun #define WM8737_RMBE_SHIFT 4 /* RMBE */ 99*4882a593Smuzhiyun #define WM8737_RMBE_WIDTH 1 /* RMBE */ 100*4882a593Smuzhiyun #define WM8737_RMZC 0x0008 /* RMZC */ 101*4882a593Smuzhiyun #define WM8737_RMZC_MASK 0x0008 /* RMZC */ 102*4882a593Smuzhiyun #define WM8737_RMZC_SHIFT 3 /* RMZC */ 103*4882a593Smuzhiyun #define WM8737_RMZC_WIDTH 1 /* RMZC */ 104*4882a593Smuzhiyun #define WM8737_RPZC 0x0004 /* RPZC */ 105*4882a593Smuzhiyun #define WM8737_RPZC_MASK 0x0004 /* RPZC */ 106*4882a593Smuzhiyun #define WM8737_RPZC_SHIFT 2 /* RPZC */ 107*4882a593Smuzhiyun #define WM8737_RPZC_WIDTH 1 /* RPZC */ 108*4882a593Smuzhiyun #define WM8737_RZCTO_MASK 0x0003 /* RZCTO - [1:0] */ 109*4882a593Smuzhiyun #define WM8737_RZCTO_SHIFT 0 /* RZCTO - [1:0] */ 110*4882a593Smuzhiyun #define WM8737_RZCTO_WIDTH 2 /* RZCTO - [1:0] */ 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun /* 113*4882a593Smuzhiyun * R4 (0x04) - 3D Enhance 114*4882a593Smuzhiyun */ 115*4882a593Smuzhiyun #define WM8737_DIV2 0x0080 /* DIV2 */ 116*4882a593Smuzhiyun #define WM8737_DIV2_MASK 0x0080 /* DIV2 */ 117*4882a593Smuzhiyun #define WM8737_DIV2_SHIFT 7 /* DIV2 */ 118*4882a593Smuzhiyun #define WM8737_DIV2_WIDTH 1 /* DIV2 */ 119*4882a593Smuzhiyun #define WM8737_3DLC 0x0040 /* 3DLC */ 120*4882a593Smuzhiyun #define WM8737_3DLC_MASK 0x0040 /* 3DLC */ 121*4882a593Smuzhiyun #define WM8737_3DLC_SHIFT 6 /* 3DLC */ 122*4882a593Smuzhiyun #define WM8737_3DLC_WIDTH 1 /* 3DLC */ 123*4882a593Smuzhiyun #define WM8737_3DUC 0x0020 /* 3DUC */ 124*4882a593Smuzhiyun #define WM8737_3DUC_MASK 0x0020 /* 3DUC */ 125*4882a593Smuzhiyun #define WM8737_3DUC_SHIFT 5 /* 3DUC */ 126*4882a593Smuzhiyun #define WM8737_3DUC_WIDTH 1 /* 3DUC */ 127*4882a593Smuzhiyun #define WM8737_3DDEPTH_MASK 0x001E /* 3DDEPTH - [4:1] */ 128*4882a593Smuzhiyun #define WM8737_3DDEPTH_SHIFT 1 /* 3DDEPTH - [4:1] */ 129*4882a593Smuzhiyun #define WM8737_3DDEPTH_WIDTH 4 /* 3DDEPTH - [4:1] */ 130*4882a593Smuzhiyun #define WM8737_3DE 0x0001 /* 3DE */ 131*4882a593Smuzhiyun #define WM8737_3DE_MASK 0x0001 /* 3DE */ 132*4882a593Smuzhiyun #define WM8737_3DE_SHIFT 0 /* 3DE */ 133*4882a593Smuzhiyun #define WM8737_3DE_WIDTH 1 /* 3DE */ 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun /* 136*4882a593Smuzhiyun * R5 (0x05) - ADC Control 137*4882a593Smuzhiyun */ 138*4882a593Smuzhiyun #define WM8737_MONOMIX_MASK 0x0180 /* MONOMIX - [8:7] */ 139*4882a593Smuzhiyun #define WM8737_MONOMIX_SHIFT 7 /* MONOMIX - [8:7] */ 140*4882a593Smuzhiyun #define WM8737_MONOMIX_WIDTH 2 /* MONOMIX - [8:7] */ 141*4882a593Smuzhiyun #define WM8737_POLARITY_MASK 0x0060 /* POLARITY - [6:5] */ 142*4882a593Smuzhiyun #define WM8737_POLARITY_SHIFT 5 /* POLARITY - [6:5] */ 143*4882a593Smuzhiyun #define WM8737_POLARITY_WIDTH 2 /* POLARITY - [6:5] */ 144*4882a593Smuzhiyun #define WM8737_HPOR 0x0010 /* HPOR */ 145*4882a593Smuzhiyun #define WM8737_HPOR_MASK 0x0010 /* HPOR */ 146*4882a593Smuzhiyun #define WM8737_HPOR_SHIFT 4 /* HPOR */ 147*4882a593Smuzhiyun #define WM8737_HPOR_WIDTH 1 /* HPOR */ 148*4882a593Smuzhiyun #define WM8737_LP 0x0004 /* LP */ 149*4882a593Smuzhiyun #define WM8737_LP_MASK 0x0004 /* LP */ 150*4882a593Smuzhiyun #define WM8737_LP_SHIFT 2 /* LP */ 151*4882a593Smuzhiyun #define WM8737_LP_WIDTH 1 /* LP */ 152*4882a593Smuzhiyun #define WM8737_MONOUT 0x0002 /* MONOUT */ 153*4882a593Smuzhiyun #define WM8737_MONOUT_MASK 0x0002 /* MONOUT */ 154*4882a593Smuzhiyun #define WM8737_MONOUT_SHIFT 1 /* MONOUT */ 155*4882a593Smuzhiyun #define WM8737_MONOUT_WIDTH 1 /* MONOUT */ 156*4882a593Smuzhiyun #define WM8737_ADCHPD 0x0001 /* ADCHPD */ 157*4882a593Smuzhiyun #define WM8737_ADCHPD_MASK 0x0001 /* ADCHPD */ 158*4882a593Smuzhiyun #define WM8737_ADCHPD_SHIFT 0 /* ADCHPD */ 159*4882a593Smuzhiyun #define WM8737_ADCHPD_WIDTH 1 /* ADCHPD */ 160*4882a593Smuzhiyun 161*4882a593Smuzhiyun /* 162*4882a593Smuzhiyun * R6 (0x06) - Power Management 163*4882a593Smuzhiyun */ 164*4882a593Smuzhiyun #define WM8737_VMID 0x0100 /* VMID */ 165*4882a593Smuzhiyun #define WM8737_VMID_MASK 0x0100 /* VMID */ 166*4882a593Smuzhiyun #define WM8737_VMID_SHIFT 8 /* VMID */ 167*4882a593Smuzhiyun #define WM8737_VMID_WIDTH 1 /* VMID */ 168*4882a593Smuzhiyun #define WM8737_VREF 0x0080 /* VREF */ 169*4882a593Smuzhiyun #define WM8737_VREF_MASK 0x0080 /* VREF */ 170*4882a593Smuzhiyun #define WM8737_VREF_SHIFT 7 /* VREF */ 171*4882a593Smuzhiyun #define WM8737_VREF_WIDTH 1 /* VREF */ 172*4882a593Smuzhiyun #define WM8737_AI 0x0040 /* AI */ 173*4882a593Smuzhiyun #define WM8737_AI_MASK 0x0040 /* AI */ 174*4882a593Smuzhiyun #define WM8737_AI_SHIFT 6 /* AI */ 175*4882a593Smuzhiyun #define WM8737_AI_WIDTH 1 /* AI */ 176*4882a593Smuzhiyun #define WM8737_PGL 0x0020 /* PGL */ 177*4882a593Smuzhiyun #define WM8737_PGL_MASK 0x0020 /* PGL */ 178*4882a593Smuzhiyun #define WM8737_PGL_SHIFT 5 /* PGL */ 179*4882a593Smuzhiyun #define WM8737_PGL_WIDTH 1 /* PGL */ 180*4882a593Smuzhiyun #define WM8737_PGR 0x0010 /* PGR */ 181*4882a593Smuzhiyun #define WM8737_PGR_MASK 0x0010 /* PGR */ 182*4882a593Smuzhiyun #define WM8737_PGR_SHIFT 4 /* PGR */ 183*4882a593Smuzhiyun #define WM8737_PGR_WIDTH 1 /* PGR */ 184*4882a593Smuzhiyun #define WM8737_ADL 0x0008 /* ADL */ 185*4882a593Smuzhiyun #define WM8737_ADL_MASK 0x0008 /* ADL */ 186*4882a593Smuzhiyun #define WM8737_ADL_SHIFT 3 /* ADL */ 187*4882a593Smuzhiyun #define WM8737_ADL_WIDTH 1 /* ADL */ 188*4882a593Smuzhiyun #define WM8737_ADR 0x0004 /* ADR */ 189*4882a593Smuzhiyun #define WM8737_ADR_MASK 0x0004 /* ADR */ 190*4882a593Smuzhiyun #define WM8737_ADR_SHIFT 2 /* ADR */ 191*4882a593Smuzhiyun #define WM8737_ADR_WIDTH 1 /* ADR */ 192*4882a593Smuzhiyun #define WM8737_MICBIAS_MASK 0x0003 /* MICBIAS - [1:0] */ 193*4882a593Smuzhiyun #define WM8737_MICBIAS_SHIFT 0 /* MICBIAS - [1:0] */ 194*4882a593Smuzhiyun #define WM8737_MICBIAS_WIDTH 2 /* MICBIAS - [1:0] */ 195*4882a593Smuzhiyun 196*4882a593Smuzhiyun /* 197*4882a593Smuzhiyun * R7 (0x07) - Audio Format 198*4882a593Smuzhiyun */ 199*4882a593Smuzhiyun #define WM8737_SDODIS 0x0080 /* SDODIS */ 200*4882a593Smuzhiyun #define WM8737_SDODIS_MASK 0x0080 /* SDODIS */ 201*4882a593Smuzhiyun #define WM8737_SDODIS_SHIFT 7 /* SDODIS */ 202*4882a593Smuzhiyun #define WM8737_SDODIS_WIDTH 1 /* SDODIS */ 203*4882a593Smuzhiyun #define WM8737_MS 0x0040 /* MS */ 204*4882a593Smuzhiyun #define WM8737_MS_MASK 0x0040 /* MS */ 205*4882a593Smuzhiyun #define WM8737_MS_SHIFT 6 /* MS */ 206*4882a593Smuzhiyun #define WM8737_MS_WIDTH 1 /* MS */ 207*4882a593Smuzhiyun #define WM8737_LRP 0x0010 /* LRP */ 208*4882a593Smuzhiyun #define WM8737_LRP_MASK 0x0010 /* LRP */ 209*4882a593Smuzhiyun #define WM8737_LRP_SHIFT 4 /* LRP */ 210*4882a593Smuzhiyun #define WM8737_LRP_WIDTH 1 /* LRP */ 211*4882a593Smuzhiyun #define WM8737_WL_MASK 0x000C /* WL - [3:2] */ 212*4882a593Smuzhiyun #define WM8737_WL_SHIFT 2 /* WL - [3:2] */ 213*4882a593Smuzhiyun #define WM8737_WL_WIDTH 2 /* WL - [3:2] */ 214*4882a593Smuzhiyun #define WM8737_FORMAT_MASK 0x0003 /* FORMAT - [1:0] */ 215*4882a593Smuzhiyun #define WM8737_FORMAT_SHIFT 0 /* FORMAT - [1:0] */ 216*4882a593Smuzhiyun #define WM8737_FORMAT_WIDTH 2 /* FORMAT - [1:0] */ 217*4882a593Smuzhiyun 218*4882a593Smuzhiyun /* 219*4882a593Smuzhiyun * R8 (0x08) - Clocking 220*4882a593Smuzhiyun */ 221*4882a593Smuzhiyun #define WM8737_AUTODETECT 0x0080 /* AUTODETECT */ 222*4882a593Smuzhiyun #define WM8737_AUTODETECT_MASK 0x0080 /* AUTODETECT */ 223*4882a593Smuzhiyun #define WM8737_AUTODETECT_SHIFT 7 /* AUTODETECT */ 224*4882a593Smuzhiyun #define WM8737_AUTODETECT_WIDTH 1 /* AUTODETECT */ 225*4882a593Smuzhiyun #define WM8737_CLKDIV2 0x0040 /* CLKDIV2 */ 226*4882a593Smuzhiyun #define WM8737_CLKDIV2_MASK 0x0040 /* CLKDIV2 */ 227*4882a593Smuzhiyun #define WM8737_CLKDIV2_SHIFT 6 /* CLKDIV2 */ 228*4882a593Smuzhiyun #define WM8737_CLKDIV2_WIDTH 1 /* CLKDIV2 */ 229*4882a593Smuzhiyun #define WM8737_SR_MASK 0x003E /* SR - [5:1] */ 230*4882a593Smuzhiyun #define WM8737_SR_SHIFT 1 /* SR - [5:1] */ 231*4882a593Smuzhiyun #define WM8737_SR_WIDTH 5 /* SR - [5:1] */ 232*4882a593Smuzhiyun #define WM8737_USB_MODE 0x0001 /* USB MODE */ 233*4882a593Smuzhiyun #define WM8737_USB_MODE_MASK 0x0001 /* USB MODE */ 234*4882a593Smuzhiyun #define WM8737_USB_MODE_SHIFT 0 /* USB MODE */ 235*4882a593Smuzhiyun #define WM8737_USB_MODE_WIDTH 1 /* USB MODE */ 236*4882a593Smuzhiyun 237*4882a593Smuzhiyun /* 238*4882a593Smuzhiyun * R9 (0x09) - MIC Preamp Control 239*4882a593Smuzhiyun */ 240*4882a593Smuzhiyun #define WM8737_RBYPEN 0x0008 /* RBYPEN */ 241*4882a593Smuzhiyun #define WM8737_RBYPEN_MASK 0x0008 /* RBYPEN */ 242*4882a593Smuzhiyun #define WM8737_RBYPEN_SHIFT 3 /* RBYPEN */ 243*4882a593Smuzhiyun #define WM8737_RBYPEN_WIDTH 1 /* RBYPEN */ 244*4882a593Smuzhiyun #define WM8737_LBYPEN 0x0004 /* LBYPEN */ 245*4882a593Smuzhiyun #define WM8737_LBYPEN_MASK 0x0004 /* LBYPEN */ 246*4882a593Smuzhiyun #define WM8737_LBYPEN_SHIFT 2 /* LBYPEN */ 247*4882a593Smuzhiyun #define WM8737_LBYPEN_WIDTH 1 /* LBYPEN */ 248*4882a593Smuzhiyun #define WM8737_MBCTRL_MASK 0x0003 /* MBCTRL - [1:0] */ 249*4882a593Smuzhiyun #define WM8737_MBCTRL_SHIFT 0 /* MBCTRL - [1:0] */ 250*4882a593Smuzhiyun #define WM8737_MBCTRL_WIDTH 2 /* MBCTRL - [1:0] */ 251*4882a593Smuzhiyun 252*4882a593Smuzhiyun /* 253*4882a593Smuzhiyun * R10 (0x0A) - Misc Bias Control 254*4882a593Smuzhiyun */ 255*4882a593Smuzhiyun #define WM8737_VMIDSEL_MASK 0x000C /* VMIDSEL - [3:2] */ 256*4882a593Smuzhiyun #define WM8737_VMIDSEL_SHIFT 2 /* VMIDSEL - [3:2] */ 257*4882a593Smuzhiyun #define WM8737_VMIDSEL_WIDTH 2 /* VMIDSEL - [3:2] */ 258*4882a593Smuzhiyun #define WM8737_LINPUT1_DC_BIAS_ENABLE 0x0002 /* LINPUT1 DC BIAS ENABLE */ 259*4882a593Smuzhiyun #define WM8737_LINPUT1_DC_BIAS_ENABLE_MASK 0x0002 /* LINPUT1 DC BIAS ENABLE */ 260*4882a593Smuzhiyun #define WM8737_LINPUT1_DC_BIAS_ENABLE_SHIFT 1 /* LINPUT1 DC BIAS ENABLE */ 261*4882a593Smuzhiyun #define WM8737_LINPUT1_DC_BIAS_ENABLE_WIDTH 1 /* LINPUT1 DC BIAS ENABLE */ 262*4882a593Smuzhiyun #define WM8737_RINPUT1_DC_BIAS_ENABLE 0x0001 /* RINPUT1 DC BIAS ENABLE */ 263*4882a593Smuzhiyun #define WM8737_RINPUT1_DC_BIAS_ENABLE_MASK 0x0001 /* RINPUT1 DC BIAS ENABLE */ 264*4882a593Smuzhiyun #define WM8737_RINPUT1_DC_BIAS_ENABLE_SHIFT 0 /* RINPUT1 DC BIAS ENABLE */ 265*4882a593Smuzhiyun #define WM8737_RINPUT1_DC_BIAS_ENABLE_WIDTH 1 /* RINPUT1 DC BIAS ENABLE */ 266*4882a593Smuzhiyun 267*4882a593Smuzhiyun /* 268*4882a593Smuzhiyun * R11 (0x0B) - Noise Gate 269*4882a593Smuzhiyun */ 270*4882a593Smuzhiyun #define WM8737_NGTH_MASK 0x001C /* NGTH - [4:2] */ 271*4882a593Smuzhiyun #define WM8737_NGTH_SHIFT 2 /* NGTH - [4:2] */ 272*4882a593Smuzhiyun #define WM8737_NGTH_WIDTH 3 /* NGTH - [4:2] */ 273*4882a593Smuzhiyun #define WM8737_NGAT 0x0001 /* NGAT */ 274*4882a593Smuzhiyun #define WM8737_NGAT_MASK 0x0001 /* NGAT */ 275*4882a593Smuzhiyun #define WM8737_NGAT_SHIFT 0 /* NGAT */ 276*4882a593Smuzhiyun #define WM8737_NGAT_WIDTH 1 /* NGAT */ 277*4882a593Smuzhiyun 278*4882a593Smuzhiyun /* 279*4882a593Smuzhiyun * R12 (0x0C) - ALC1 280*4882a593Smuzhiyun */ 281*4882a593Smuzhiyun #define WM8737_ALCSEL_MASK 0x0180 /* ALCSEL - [8:7] */ 282*4882a593Smuzhiyun #define WM8737_ALCSEL_SHIFT 7 /* ALCSEL - [8:7] */ 283*4882a593Smuzhiyun #define WM8737_ALCSEL_WIDTH 2 /* ALCSEL - [8:7] */ 284*4882a593Smuzhiyun #define WM8737_MAX_GAIN_MASK 0x0070 /* MAX GAIN - [6:4] */ 285*4882a593Smuzhiyun #define WM8737_MAX_GAIN_SHIFT 4 /* MAX GAIN - [6:4] */ 286*4882a593Smuzhiyun #define WM8737_MAX_GAIN_WIDTH 3 /* MAX GAIN - [6:4] */ 287*4882a593Smuzhiyun #define WM8737_ALCL_MASK 0x000F /* ALCL - [3:0] */ 288*4882a593Smuzhiyun #define WM8737_ALCL_SHIFT 0 /* ALCL - [3:0] */ 289*4882a593Smuzhiyun #define WM8737_ALCL_WIDTH 4 /* ALCL - [3:0] */ 290*4882a593Smuzhiyun 291*4882a593Smuzhiyun /* 292*4882a593Smuzhiyun * R13 (0x0D) - ALC2 293*4882a593Smuzhiyun */ 294*4882a593Smuzhiyun #define WM8737_ALCZCE 0x0010 /* ALCZCE */ 295*4882a593Smuzhiyun #define WM8737_ALCZCE_MASK 0x0010 /* ALCZCE */ 296*4882a593Smuzhiyun #define WM8737_ALCZCE_SHIFT 4 /* ALCZCE */ 297*4882a593Smuzhiyun #define WM8737_ALCZCE_WIDTH 1 /* ALCZCE */ 298*4882a593Smuzhiyun #define WM8737_HLD_MASK 0x000F /* HLD - [3:0] */ 299*4882a593Smuzhiyun #define WM8737_HLD_SHIFT 0 /* HLD - [3:0] */ 300*4882a593Smuzhiyun #define WM8737_HLD_WIDTH 4 /* HLD - [3:0] */ 301*4882a593Smuzhiyun 302*4882a593Smuzhiyun /* 303*4882a593Smuzhiyun * R14 (0x0E) - ALC3 304*4882a593Smuzhiyun */ 305*4882a593Smuzhiyun #define WM8737_DCY_MASK 0x00F0 /* DCY - [7:4] */ 306*4882a593Smuzhiyun #define WM8737_DCY_SHIFT 4 /* DCY - [7:4] */ 307*4882a593Smuzhiyun #define WM8737_DCY_WIDTH 4 /* DCY - [7:4] */ 308*4882a593Smuzhiyun #define WM8737_ATK_MASK 0x000F /* ATK - [3:0] */ 309*4882a593Smuzhiyun #define WM8737_ATK_SHIFT 0 /* ATK - [3:0] */ 310*4882a593Smuzhiyun #define WM8737_ATK_WIDTH 4 /* ATK - [3:0] */ 311*4882a593Smuzhiyun 312*4882a593Smuzhiyun /* 313*4882a593Smuzhiyun * R15 (0x0F) - Reset 314*4882a593Smuzhiyun */ 315*4882a593Smuzhiyun #define WM8737_RESET_MASK 0x01FF /* RESET - [8:0] */ 316*4882a593Smuzhiyun #define WM8737_RESET_SHIFT 0 /* RESET - [8:0] */ 317*4882a593Smuzhiyun #define WM8737_RESET_WIDTH 9 /* RESET - [8:0] */ 318*4882a593Smuzhiyun 319*4882a593Smuzhiyun #endif 320