1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * wm8523.h -- WM8523 ASoC driver 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright 2009 Wolfson Microelectronics, plc 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * Based on wm8753.h 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #ifndef _WM8523_H 13*4882a593Smuzhiyun #define _WM8523_H 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /* 16*4882a593Smuzhiyun * Register values. 17*4882a593Smuzhiyun */ 18*4882a593Smuzhiyun #define WM8523_DEVICE_ID 0x00 19*4882a593Smuzhiyun #define WM8523_REVISION 0x01 20*4882a593Smuzhiyun #define WM8523_PSCTRL1 0x02 21*4882a593Smuzhiyun #define WM8523_AIF_CTRL1 0x03 22*4882a593Smuzhiyun #define WM8523_AIF_CTRL2 0x04 23*4882a593Smuzhiyun #define WM8523_DAC_CTRL3 0x05 24*4882a593Smuzhiyun #define WM8523_DAC_GAINL 0x06 25*4882a593Smuzhiyun #define WM8523_DAC_GAINR 0x07 26*4882a593Smuzhiyun #define WM8523_ZERO_DETECT 0x08 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun #define WM8523_REGISTER_COUNT 9 29*4882a593Smuzhiyun #define WM8523_MAX_REGISTER 0x08 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /* 32*4882a593Smuzhiyun * Field Definitions. 33*4882a593Smuzhiyun */ 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* 36*4882a593Smuzhiyun * R0 (0x00) - DEVICE_ID 37*4882a593Smuzhiyun */ 38*4882a593Smuzhiyun #define WM8523_CHIP_ID_MASK 0xFFFF /* CHIP_ID - [15:0] */ 39*4882a593Smuzhiyun #define WM8523_CHIP_ID_SHIFT 0 /* CHIP_ID - [15:0] */ 40*4882a593Smuzhiyun #define WM8523_CHIP_ID_WIDTH 16 /* CHIP_ID - [15:0] */ 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun /* 43*4882a593Smuzhiyun * R1 (0x01) - REVISION 44*4882a593Smuzhiyun */ 45*4882a593Smuzhiyun #define WM8523_CHIP_REV_MASK 0x0007 /* CHIP_REV - [2:0] */ 46*4882a593Smuzhiyun #define WM8523_CHIP_REV_SHIFT 0 /* CHIP_REV - [2:0] */ 47*4882a593Smuzhiyun #define WM8523_CHIP_REV_WIDTH 3 /* CHIP_REV - [2:0] */ 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun /* 50*4882a593Smuzhiyun * R2 (0x02) - PSCTRL1 51*4882a593Smuzhiyun */ 52*4882a593Smuzhiyun #define WM8523_SYS_ENA_MASK 0x0003 /* SYS_ENA - [1:0] */ 53*4882a593Smuzhiyun #define WM8523_SYS_ENA_SHIFT 0 /* SYS_ENA - [1:0] */ 54*4882a593Smuzhiyun #define WM8523_SYS_ENA_WIDTH 2 /* SYS_ENA - [1:0] */ 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun /* 57*4882a593Smuzhiyun * R3 (0x03) - AIF_CTRL1 58*4882a593Smuzhiyun */ 59*4882a593Smuzhiyun #define WM8523_TDM_MODE_MASK 0x1800 /* TDM_MODE - [12:11] */ 60*4882a593Smuzhiyun #define WM8523_TDM_MODE_SHIFT 11 /* TDM_MODE - [12:11] */ 61*4882a593Smuzhiyun #define WM8523_TDM_MODE_WIDTH 2 /* TDM_MODE - [12:11] */ 62*4882a593Smuzhiyun #define WM8523_TDM_SLOT_MASK 0x0600 /* TDM_SLOT - [10:9] */ 63*4882a593Smuzhiyun #define WM8523_TDM_SLOT_SHIFT 9 /* TDM_SLOT - [10:9] */ 64*4882a593Smuzhiyun #define WM8523_TDM_SLOT_WIDTH 2 /* TDM_SLOT - [10:9] */ 65*4882a593Smuzhiyun #define WM8523_DEEMPH 0x0100 /* DEEMPH */ 66*4882a593Smuzhiyun #define WM8523_DEEMPH_MASK 0x0100 /* DEEMPH */ 67*4882a593Smuzhiyun #define WM8523_DEEMPH_SHIFT 8 /* DEEMPH */ 68*4882a593Smuzhiyun #define WM8523_DEEMPH_WIDTH 1 /* DEEMPH */ 69*4882a593Smuzhiyun #define WM8523_AIF_MSTR 0x0080 /* AIF_MSTR */ 70*4882a593Smuzhiyun #define WM8523_AIF_MSTR_MASK 0x0080 /* AIF_MSTR */ 71*4882a593Smuzhiyun #define WM8523_AIF_MSTR_SHIFT 7 /* AIF_MSTR */ 72*4882a593Smuzhiyun #define WM8523_AIF_MSTR_WIDTH 1 /* AIF_MSTR */ 73*4882a593Smuzhiyun #define WM8523_LRCLK_INV 0x0040 /* LRCLK_INV */ 74*4882a593Smuzhiyun #define WM8523_LRCLK_INV_MASK 0x0040 /* LRCLK_INV */ 75*4882a593Smuzhiyun #define WM8523_LRCLK_INV_SHIFT 6 /* LRCLK_INV */ 76*4882a593Smuzhiyun #define WM8523_LRCLK_INV_WIDTH 1 /* LRCLK_INV */ 77*4882a593Smuzhiyun #define WM8523_BCLK_INV 0x0020 /* BCLK_INV */ 78*4882a593Smuzhiyun #define WM8523_BCLK_INV_MASK 0x0020 /* BCLK_INV */ 79*4882a593Smuzhiyun #define WM8523_BCLK_INV_SHIFT 5 /* BCLK_INV */ 80*4882a593Smuzhiyun #define WM8523_BCLK_INV_WIDTH 1 /* BCLK_INV */ 81*4882a593Smuzhiyun #define WM8523_WL_MASK 0x0018 /* WL - [4:3] */ 82*4882a593Smuzhiyun #define WM8523_WL_SHIFT 3 /* WL - [4:3] */ 83*4882a593Smuzhiyun #define WM8523_WL_WIDTH 2 /* WL - [4:3] */ 84*4882a593Smuzhiyun #define WM8523_FMT_MASK 0x0007 /* FMT - [2:0] */ 85*4882a593Smuzhiyun #define WM8523_FMT_SHIFT 0 /* FMT - [2:0] */ 86*4882a593Smuzhiyun #define WM8523_FMT_WIDTH 3 /* FMT - [2:0] */ 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun /* 89*4882a593Smuzhiyun * R4 (0x04) - AIF_CTRL2 90*4882a593Smuzhiyun */ 91*4882a593Smuzhiyun #define WM8523_DAC_OP_MUX_MASK 0x00C0 /* DAC_OP_MUX - [7:6] */ 92*4882a593Smuzhiyun #define WM8523_DAC_OP_MUX_SHIFT 6 /* DAC_OP_MUX - [7:6] */ 93*4882a593Smuzhiyun #define WM8523_DAC_OP_MUX_WIDTH 2 /* DAC_OP_MUX - [7:6] */ 94*4882a593Smuzhiyun #define WM8523_BCLKDIV_MASK 0x0038 /* BCLKDIV - [5:3] */ 95*4882a593Smuzhiyun #define WM8523_BCLKDIV_SHIFT 3 /* BCLKDIV - [5:3] */ 96*4882a593Smuzhiyun #define WM8523_BCLKDIV_WIDTH 3 /* BCLKDIV - [5:3] */ 97*4882a593Smuzhiyun #define WM8523_SR_MASK 0x0007 /* SR - [2:0] */ 98*4882a593Smuzhiyun #define WM8523_SR_SHIFT 0 /* SR - [2:0] */ 99*4882a593Smuzhiyun #define WM8523_SR_WIDTH 3 /* SR - [2:0] */ 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun /* 102*4882a593Smuzhiyun * R5 (0x05) - DAC_CTRL3 103*4882a593Smuzhiyun */ 104*4882a593Smuzhiyun #define WM8523_ZC 0x0010 /* ZC */ 105*4882a593Smuzhiyun #define WM8523_ZC_MASK 0x0010 /* ZC */ 106*4882a593Smuzhiyun #define WM8523_ZC_SHIFT 4 /* ZC */ 107*4882a593Smuzhiyun #define WM8523_ZC_WIDTH 1 /* ZC */ 108*4882a593Smuzhiyun #define WM8523_DACR 0x0008 /* DACR */ 109*4882a593Smuzhiyun #define WM8523_DACR_MASK 0x0008 /* DACR */ 110*4882a593Smuzhiyun #define WM8523_DACR_SHIFT 3 /* DACR */ 111*4882a593Smuzhiyun #define WM8523_DACR_WIDTH 1 /* DACR */ 112*4882a593Smuzhiyun #define WM8523_DACL 0x0004 /* DACL */ 113*4882a593Smuzhiyun #define WM8523_DACL_MASK 0x0004 /* DACL */ 114*4882a593Smuzhiyun #define WM8523_DACL_SHIFT 2 /* DACL */ 115*4882a593Smuzhiyun #define WM8523_DACL_WIDTH 1 /* DACL */ 116*4882a593Smuzhiyun #define WM8523_VOL_UP_RAMP 0x0002 /* VOL_UP_RAMP */ 117*4882a593Smuzhiyun #define WM8523_VOL_UP_RAMP_MASK 0x0002 /* VOL_UP_RAMP */ 118*4882a593Smuzhiyun #define WM8523_VOL_UP_RAMP_SHIFT 1 /* VOL_UP_RAMP */ 119*4882a593Smuzhiyun #define WM8523_VOL_UP_RAMP_WIDTH 1 /* VOL_UP_RAMP */ 120*4882a593Smuzhiyun #define WM8523_VOL_DOWN_RAMP 0x0001 /* VOL_DOWN_RAMP */ 121*4882a593Smuzhiyun #define WM8523_VOL_DOWN_RAMP_MASK 0x0001 /* VOL_DOWN_RAMP */ 122*4882a593Smuzhiyun #define WM8523_VOL_DOWN_RAMP_SHIFT 0 /* VOL_DOWN_RAMP */ 123*4882a593Smuzhiyun #define WM8523_VOL_DOWN_RAMP_WIDTH 1 /* VOL_DOWN_RAMP */ 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun /* 126*4882a593Smuzhiyun * R6 (0x06) - DAC_GAINL 127*4882a593Smuzhiyun */ 128*4882a593Smuzhiyun #define WM8523_DACL_VU 0x0200 /* DACL_VU */ 129*4882a593Smuzhiyun #define WM8523_DACL_VU_MASK 0x0200 /* DACL_VU */ 130*4882a593Smuzhiyun #define WM8523_DACL_VU_SHIFT 9 /* DACL_VU */ 131*4882a593Smuzhiyun #define WM8523_DACL_VU_WIDTH 1 /* DACL_VU */ 132*4882a593Smuzhiyun #define WM8523_DACL_VOL_MASK 0x01FF /* DACL_VOL - [8:0] */ 133*4882a593Smuzhiyun #define WM8523_DACL_VOL_SHIFT 0 /* DACL_VOL - [8:0] */ 134*4882a593Smuzhiyun #define WM8523_DACL_VOL_WIDTH 9 /* DACL_VOL - [8:0] */ 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun /* 137*4882a593Smuzhiyun * R7 (0x07) - DAC_GAINR 138*4882a593Smuzhiyun */ 139*4882a593Smuzhiyun #define WM8523_DACR_VU 0x0200 /* DACR_VU */ 140*4882a593Smuzhiyun #define WM8523_DACR_VU_MASK 0x0200 /* DACR_VU */ 141*4882a593Smuzhiyun #define WM8523_DACR_VU_SHIFT 9 /* DACR_VU */ 142*4882a593Smuzhiyun #define WM8523_DACR_VU_WIDTH 1 /* DACR_VU */ 143*4882a593Smuzhiyun #define WM8523_DACR_VOL_MASK 0x01FF /* DACR_VOL - [8:0] */ 144*4882a593Smuzhiyun #define WM8523_DACR_VOL_SHIFT 0 /* DACR_VOL - [8:0] */ 145*4882a593Smuzhiyun #define WM8523_DACR_VOL_WIDTH 9 /* DACR_VOL - [8:0] */ 146*4882a593Smuzhiyun 147*4882a593Smuzhiyun /* 148*4882a593Smuzhiyun * R8 (0x08) - ZERO_DETECT 149*4882a593Smuzhiyun */ 150*4882a593Smuzhiyun #define WM8523_ZD_COUNT_MASK 0x0003 /* ZD_COUNT - [1:0] */ 151*4882a593Smuzhiyun #define WM8523_ZD_COUNT_SHIFT 0 /* ZD_COUNT - [1:0] */ 152*4882a593Smuzhiyun #define WM8523_ZD_COUNT_WIDTH 2 /* ZD_COUNT - [1:0] */ 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun #endif 155