1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * wm8510.h -- WM8510 Soc Audio driver 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef _WM8510_H 7*4882a593Smuzhiyun #define _WM8510_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun /* WM8510 register space */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define WM8510_RESET 0x0 12*4882a593Smuzhiyun #define WM8510_POWER1 0x1 13*4882a593Smuzhiyun #define WM8510_POWER2 0x2 14*4882a593Smuzhiyun #define WM8510_POWER3 0x3 15*4882a593Smuzhiyun #define WM8510_IFACE 0x4 16*4882a593Smuzhiyun #define WM8510_COMP 0x5 17*4882a593Smuzhiyun #define WM8510_CLOCK 0x6 18*4882a593Smuzhiyun #define WM8510_ADD 0x7 19*4882a593Smuzhiyun #define WM8510_GPIO 0x8 20*4882a593Smuzhiyun #define WM8510_DAC 0xa 21*4882a593Smuzhiyun #define WM8510_DACVOL 0xb 22*4882a593Smuzhiyun #define WM8510_ADC 0xe 23*4882a593Smuzhiyun #define WM8510_ADCVOL 0xf 24*4882a593Smuzhiyun #define WM8510_EQ1 0x12 25*4882a593Smuzhiyun #define WM8510_EQ2 0x13 26*4882a593Smuzhiyun #define WM8510_EQ3 0x14 27*4882a593Smuzhiyun #define WM8510_EQ4 0x15 28*4882a593Smuzhiyun #define WM8510_EQ5 0x16 29*4882a593Smuzhiyun #define WM8510_DACLIM1 0x18 30*4882a593Smuzhiyun #define WM8510_DACLIM2 0x19 31*4882a593Smuzhiyun #define WM8510_NOTCH1 0x1b 32*4882a593Smuzhiyun #define WM8510_NOTCH2 0x1c 33*4882a593Smuzhiyun #define WM8510_NOTCH3 0x1d 34*4882a593Smuzhiyun #define WM8510_NOTCH4 0x1e 35*4882a593Smuzhiyun #define WM8510_ALC1 0x20 36*4882a593Smuzhiyun #define WM8510_ALC2 0x21 37*4882a593Smuzhiyun #define WM8510_ALC3 0x22 38*4882a593Smuzhiyun #define WM8510_NGATE 0x23 39*4882a593Smuzhiyun #define WM8510_PLLN 0x24 40*4882a593Smuzhiyun #define WM8510_PLLK1 0x25 41*4882a593Smuzhiyun #define WM8510_PLLK2 0x26 42*4882a593Smuzhiyun #define WM8510_PLLK3 0x27 43*4882a593Smuzhiyun #define WM8510_ATTEN 0x28 44*4882a593Smuzhiyun #define WM8510_INPUT 0x2c 45*4882a593Smuzhiyun #define WM8510_INPPGA 0x2d 46*4882a593Smuzhiyun #define WM8510_ADCBOOST 0x2f 47*4882a593Smuzhiyun #define WM8510_OUTPUT 0x31 48*4882a593Smuzhiyun #define WM8510_SPKMIX 0x32 49*4882a593Smuzhiyun #define WM8510_SPKVOL 0x36 50*4882a593Smuzhiyun #define WM8510_MONOMIX 0x38 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun #define WM8510_CACHEREGNUM 57 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun /* Clock divider Id's */ 55*4882a593Smuzhiyun #define WM8510_OPCLKDIV 0 56*4882a593Smuzhiyun #define WM8510_MCLKDIV 1 57*4882a593Smuzhiyun #define WM8510_ADCCLK 2 58*4882a593Smuzhiyun #define WM8510_DACCLK 3 59*4882a593Smuzhiyun #define WM8510_BCLKDIV 4 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun /* DAC clock dividers */ 62*4882a593Smuzhiyun #define WM8510_DACCLK_F2 (1 << 3) 63*4882a593Smuzhiyun #define WM8510_DACCLK_F4 (0 << 3) 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun /* ADC clock dividers */ 66*4882a593Smuzhiyun #define WM8510_ADCCLK_F2 (1 << 3) 67*4882a593Smuzhiyun #define WM8510_ADCCLK_F4 (0 << 3) 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun /* PLL Out dividers */ 70*4882a593Smuzhiyun #define WM8510_OPCLKDIV_1 (0 << 4) 71*4882a593Smuzhiyun #define WM8510_OPCLKDIV_2 (1 << 4) 72*4882a593Smuzhiyun #define WM8510_OPCLKDIV_3 (2 << 4) 73*4882a593Smuzhiyun #define WM8510_OPCLKDIV_4 (3 << 4) 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun /* BCLK clock dividers */ 76*4882a593Smuzhiyun #define WM8510_BCLKDIV_1 (0 << 2) 77*4882a593Smuzhiyun #define WM8510_BCLKDIV_2 (1 << 2) 78*4882a593Smuzhiyun #define WM8510_BCLKDIV_4 (2 << 2) 79*4882a593Smuzhiyun #define WM8510_BCLKDIV_8 (3 << 2) 80*4882a593Smuzhiyun #define WM8510_BCLKDIV_16 (4 << 2) 81*4882a593Smuzhiyun #define WM8510_BCLKDIV_32 (5 << 2) 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun /* MCLK clock dividers */ 84*4882a593Smuzhiyun #define WM8510_MCLKDIV_1 (0 << 5) 85*4882a593Smuzhiyun #define WM8510_MCLKDIV_1_5 (1 << 5) 86*4882a593Smuzhiyun #define WM8510_MCLKDIV_2 (2 << 5) 87*4882a593Smuzhiyun #define WM8510_MCLKDIV_3 (3 << 5) 88*4882a593Smuzhiyun #define WM8510_MCLKDIV_4 (4 << 5) 89*4882a593Smuzhiyun #define WM8510_MCLKDIV_6 (5 << 5) 90*4882a593Smuzhiyun #define WM8510_MCLKDIV_8 (6 << 5) 91*4882a593Smuzhiyun #define WM8510_MCLKDIV_12 (7 << 5) 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun struct wm8510_setup_data { 94*4882a593Smuzhiyun int spi; 95*4882a593Smuzhiyun int i2c_bus; 96*4882a593Smuzhiyun unsigned short i2c_address; 97*4882a593Smuzhiyun }; 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun #endif 100