1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * wm8400.h -- audio driver for WM8400 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright 2008 Wolfson Microelectronics PLC. 6*4882a593Smuzhiyun * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef _WM8400_CODEC_H 10*4882a593Smuzhiyun #define _WM8400_CODEC_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define WM8400_MCLK_DIV 0 13*4882a593Smuzhiyun #define WM8400_DACCLK_DIV 1 14*4882a593Smuzhiyun #define WM8400_ADCCLK_DIV 2 15*4882a593Smuzhiyun #define WM8400_BCLK_DIV 3 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #define WM8400_MCLK_DIV_1 0x400 18*4882a593Smuzhiyun #define WM8400_MCLK_DIV_2 0x800 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define WM8400_DAC_CLKDIV_1 0x00 21*4882a593Smuzhiyun #define WM8400_DAC_CLKDIV_1_5 0x04 22*4882a593Smuzhiyun #define WM8400_DAC_CLKDIV_2 0x08 23*4882a593Smuzhiyun #define WM8400_DAC_CLKDIV_3 0x0c 24*4882a593Smuzhiyun #define WM8400_DAC_CLKDIV_4 0x10 25*4882a593Smuzhiyun #define WM8400_DAC_CLKDIV_5_5 0x14 26*4882a593Smuzhiyun #define WM8400_DAC_CLKDIV_6 0x18 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun #define WM8400_ADC_CLKDIV_1 0x00 29*4882a593Smuzhiyun #define WM8400_ADC_CLKDIV_1_5 0x20 30*4882a593Smuzhiyun #define WM8400_ADC_CLKDIV_2 0x40 31*4882a593Smuzhiyun #define WM8400_ADC_CLKDIV_3 0x60 32*4882a593Smuzhiyun #define WM8400_ADC_CLKDIV_4 0x80 33*4882a593Smuzhiyun #define WM8400_ADC_CLKDIV_5_5 0xa0 34*4882a593Smuzhiyun #define WM8400_ADC_CLKDIV_6 0xc0 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun #define WM8400_BCLK_DIV_1 (0x0 << 1) 38*4882a593Smuzhiyun #define WM8400_BCLK_DIV_1_5 (0x1 << 1) 39*4882a593Smuzhiyun #define WM8400_BCLK_DIV_2 (0x2 << 1) 40*4882a593Smuzhiyun #define WM8400_BCLK_DIV_3 (0x3 << 1) 41*4882a593Smuzhiyun #define WM8400_BCLK_DIV_4 (0x4 << 1) 42*4882a593Smuzhiyun #define WM8400_BCLK_DIV_5_5 (0x5 << 1) 43*4882a593Smuzhiyun #define WM8400_BCLK_DIV_6 (0x6 << 1) 44*4882a593Smuzhiyun #define WM8400_BCLK_DIV_8 (0x7 << 1) 45*4882a593Smuzhiyun #define WM8400_BCLK_DIV_11 (0x8 << 1) 46*4882a593Smuzhiyun #define WM8400_BCLK_DIV_12 (0x9 << 1) 47*4882a593Smuzhiyun #define WM8400_BCLK_DIV_16 (0xA << 1) 48*4882a593Smuzhiyun #define WM8400_BCLK_DIV_22 (0xB << 1) 49*4882a593Smuzhiyun #define WM8400_BCLK_DIV_24 (0xC << 1) 50*4882a593Smuzhiyun #define WM8400_BCLK_DIV_32 (0xD << 1) 51*4882a593Smuzhiyun #define WM8400_BCLK_DIV_44 (0xE << 1) 52*4882a593Smuzhiyun #define WM8400_BCLK_DIV_48 (0xF << 1) 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun #endif 55