1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * wm5100.h -- WM5100 ALSA SoC Audio driver 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright 2011 Wolfson Microelectronics plc 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef WM5100_ASOC_H 11*4882a593Smuzhiyun #define WM5100_ASOC_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #include <sound/soc.h> 14*4882a593Smuzhiyun #include <linux/regmap.h> 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun int wm5100_detect(struct snd_soc_component *component, struct snd_soc_jack *jack); 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #define WM5100_CLK_AIF1 1 19*4882a593Smuzhiyun #define WM5100_CLK_AIF2 2 20*4882a593Smuzhiyun #define WM5100_CLK_AIF3 3 21*4882a593Smuzhiyun #define WM5100_CLK_SYSCLK 4 22*4882a593Smuzhiyun #define WM5100_CLK_ASYNCCLK 5 23*4882a593Smuzhiyun #define WM5100_CLK_32KHZ 6 24*4882a593Smuzhiyun #define WM5100_CLK_OPCLK 7 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #define WM5100_CLKSRC_MCLK1 0 27*4882a593Smuzhiyun #define WM5100_CLKSRC_MCLK2 1 28*4882a593Smuzhiyun #define WM5100_CLKSRC_SYSCLK 2 29*4882a593Smuzhiyun #define WM5100_CLKSRC_FLL1 4 30*4882a593Smuzhiyun #define WM5100_CLKSRC_FLL2 5 31*4882a593Smuzhiyun #define WM5100_CLKSRC_AIF1BCLK 8 32*4882a593Smuzhiyun #define WM5100_CLKSRC_AIF2BCLK 9 33*4882a593Smuzhiyun #define WM5100_CLKSRC_AIF3BCLK 10 34*4882a593Smuzhiyun #define WM5100_CLKSRC_ASYNCCLK 0x100 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #define WM5100_FLL1 1 37*4882a593Smuzhiyun #define WM5100_FLL2 2 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #define WM5100_FLL_SRC_MCLK1 0x0 40*4882a593Smuzhiyun #define WM5100_FLL_SRC_MCLK2 0x1 41*4882a593Smuzhiyun #define WM5100_FLL_SRC_FLL1 0x4 42*4882a593Smuzhiyun #define WM5100_FLL_SRC_FLL2 0x5 43*4882a593Smuzhiyun #define WM5100_FLL_SRC_AIF1BCLK 0x8 44*4882a593Smuzhiyun #define WM5100_FLL_SRC_AIF2BCLK 0x9 45*4882a593Smuzhiyun #define WM5100_FLL_SRC_AIF3BCLK 0xa 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun /* 48*4882a593Smuzhiyun * Register values. 49*4882a593Smuzhiyun */ 50*4882a593Smuzhiyun #define WM5100_SOFTWARE_RESET 0x00 51*4882a593Smuzhiyun #define WM5100_DEVICE_REVISION 0x01 52*4882a593Smuzhiyun #define WM5100_CTRL_IF_1 0x10 53*4882a593Smuzhiyun #define WM5100_TONE_GENERATOR_1 0x20 54*4882a593Smuzhiyun #define WM5100_PWM_DRIVE_1 0x30 55*4882a593Smuzhiyun #define WM5100_PWM_DRIVE_2 0x31 56*4882a593Smuzhiyun #define WM5100_PWM_DRIVE_3 0x32 57*4882a593Smuzhiyun #define WM5100_CLOCKING_1 0x100 58*4882a593Smuzhiyun #define WM5100_CLOCKING_3 0x101 59*4882a593Smuzhiyun #define WM5100_CLOCKING_4 0x102 60*4882a593Smuzhiyun #define WM5100_CLOCKING_5 0x103 61*4882a593Smuzhiyun #define WM5100_CLOCKING_6 0x104 62*4882a593Smuzhiyun #define WM5100_CLOCKING_7 0x107 63*4882a593Smuzhiyun #define WM5100_CLOCKING_8 0x108 64*4882a593Smuzhiyun #define WM5100_ASRC_ENABLE 0x120 65*4882a593Smuzhiyun #define WM5100_ASRC_STATUS 0x121 66*4882a593Smuzhiyun #define WM5100_ASRC_RATE1 0x122 67*4882a593Smuzhiyun #define WM5100_ISRC_1_CTRL_1 0x141 68*4882a593Smuzhiyun #define WM5100_ISRC_1_CTRL_2 0x142 69*4882a593Smuzhiyun #define WM5100_ISRC_2_CTRL1 0x143 70*4882a593Smuzhiyun #define WM5100_ISRC_2_CTRL_2 0x144 71*4882a593Smuzhiyun #define WM5100_FLL1_CONTROL_1 0x182 72*4882a593Smuzhiyun #define WM5100_FLL1_CONTROL_2 0x183 73*4882a593Smuzhiyun #define WM5100_FLL1_CONTROL_3 0x184 74*4882a593Smuzhiyun #define WM5100_FLL1_CONTROL_5 0x186 75*4882a593Smuzhiyun #define WM5100_FLL1_CONTROL_6 0x187 76*4882a593Smuzhiyun #define WM5100_FLL1_EFS_1 0x188 77*4882a593Smuzhiyun #define WM5100_FLL2_CONTROL_1 0x1A2 78*4882a593Smuzhiyun #define WM5100_FLL2_CONTROL_2 0x1A3 79*4882a593Smuzhiyun #define WM5100_FLL2_CONTROL_3 0x1A4 80*4882a593Smuzhiyun #define WM5100_FLL2_CONTROL_5 0x1A6 81*4882a593Smuzhiyun #define WM5100_FLL2_CONTROL_6 0x1A7 82*4882a593Smuzhiyun #define WM5100_FLL2_EFS_1 0x1A8 83*4882a593Smuzhiyun #define WM5100_MIC_CHARGE_PUMP_1 0x200 84*4882a593Smuzhiyun #define WM5100_MIC_CHARGE_PUMP_2 0x201 85*4882a593Smuzhiyun #define WM5100_HP_CHARGE_PUMP_1 0x202 86*4882a593Smuzhiyun #define WM5100_LDO1_CONTROL 0x211 87*4882a593Smuzhiyun #define WM5100_MIC_BIAS_CTRL_1 0x215 88*4882a593Smuzhiyun #define WM5100_MIC_BIAS_CTRL_2 0x216 89*4882a593Smuzhiyun #define WM5100_MIC_BIAS_CTRL_3 0x217 90*4882a593Smuzhiyun #define WM5100_ACCESSORY_DETECT_MODE_1 0x280 91*4882a593Smuzhiyun #define WM5100_HEADPHONE_DETECT_1 0x288 92*4882a593Smuzhiyun #define WM5100_HEADPHONE_DETECT_2 0x289 93*4882a593Smuzhiyun #define WM5100_MIC_DETECT_1 0x290 94*4882a593Smuzhiyun #define WM5100_MIC_DETECT_2 0x291 95*4882a593Smuzhiyun #define WM5100_MIC_DETECT_3 0x292 96*4882a593Smuzhiyun #define WM5100_MISC_CONTROL 0x2BB 97*4882a593Smuzhiyun #define WM5100_INPUT_ENABLES 0x301 98*4882a593Smuzhiyun #define WM5100_INPUT_ENABLES_STATUS 0x302 99*4882a593Smuzhiyun #define WM5100_IN1L_CONTROL 0x310 100*4882a593Smuzhiyun #define WM5100_IN1R_CONTROL 0x311 101*4882a593Smuzhiyun #define WM5100_IN2L_CONTROL 0x312 102*4882a593Smuzhiyun #define WM5100_IN2R_CONTROL 0x313 103*4882a593Smuzhiyun #define WM5100_IN3L_CONTROL 0x314 104*4882a593Smuzhiyun #define WM5100_IN3R_CONTROL 0x315 105*4882a593Smuzhiyun #define WM5100_IN4L_CONTROL 0x316 106*4882a593Smuzhiyun #define WM5100_IN4R_CONTROL 0x317 107*4882a593Smuzhiyun #define WM5100_RXANC_SRC 0x318 108*4882a593Smuzhiyun #define WM5100_INPUT_VOLUME_RAMP 0x319 109*4882a593Smuzhiyun #define WM5100_ADC_DIGITAL_VOLUME_1L 0x320 110*4882a593Smuzhiyun #define WM5100_ADC_DIGITAL_VOLUME_1R 0x321 111*4882a593Smuzhiyun #define WM5100_ADC_DIGITAL_VOLUME_2L 0x322 112*4882a593Smuzhiyun #define WM5100_ADC_DIGITAL_VOLUME_2R 0x323 113*4882a593Smuzhiyun #define WM5100_ADC_DIGITAL_VOLUME_3L 0x324 114*4882a593Smuzhiyun #define WM5100_ADC_DIGITAL_VOLUME_3R 0x325 115*4882a593Smuzhiyun #define WM5100_ADC_DIGITAL_VOLUME_4L 0x326 116*4882a593Smuzhiyun #define WM5100_ADC_DIGITAL_VOLUME_4R 0x327 117*4882a593Smuzhiyun #define WM5100_OUTPUT_ENABLES_2 0x401 118*4882a593Smuzhiyun #define WM5100_OUTPUT_STATUS_1 0x402 119*4882a593Smuzhiyun #define WM5100_OUTPUT_STATUS_2 0x403 120*4882a593Smuzhiyun #define WM5100_CHANNEL_ENABLES_1 0x408 121*4882a593Smuzhiyun #define WM5100_OUT_VOLUME_1L 0x410 122*4882a593Smuzhiyun #define WM5100_OUT_VOLUME_1R 0x411 123*4882a593Smuzhiyun #define WM5100_DAC_VOLUME_LIMIT_1L 0x412 124*4882a593Smuzhiyun #define WM5100_DAC_VOLUME_LIMIT_1R 0x413 125*4882a593Smuzhiyun #define WM5100_OUT_VOLUME_2L 0x414 126*4882a593Smuzhiyun #define WM5100_OUT_VOLUME_2R 0x415 127*4882a593Smuzhiyun #define WM5100_DAC_VOLUME_LIMIT_2L 0x416 128*4882a593Smuzhiyun #define WM5100_DAC_VOLUME_LIMIT_2R 0x417 129*4882a593Smuzhiyun #define WM5100_OUT_VOLUME_3L 0x418 130*4882a593Smuzhiyun #define WM5100_OUT_VOLUME_3R 0x419 131*4882a593Smuzhiyun #define WM5100_DAC_VOLUME_LIMIT_3L 0x41A 132*4882a593Smuzhiyun #define WM5100_DAC_VOLUME_LIMIT_3R 0x41B 133*4882a593Smuzhiyun #define WM5100_OUT_VOLUME_4L 0x41C 134*4882a593Smuzhiyun #define WM5100_OUT_VOLUME_4R 0x41D 135*4882a593Smuzhiyun #define WM5100_DAC_VOLUME_LIMIT_5L 0x41E 136*4882a593Smuzhiyun #define WM5100_DAC_VOLUME_LIMIT_5R 0x41F 137*4882a593Smuzhiyun #define WM5100_DAC_VOLUME_LIMIT_6L 0x420 138*4882a593Smuzhiyun #define WM5100_DAC_VOLUME_LIMIT_6R 0x421 139*4882a593Smuzhiyun #define WM5100_DAC_AEC_CONTROL_1 0x440 140*4882a593Smuzhiyun #define WM5100_OUTPUT_VOLUME_RAMP 0x441 141*4882a593Smuzhiyun #define WM5100_DAC_DIGITAL_VOLUME_1L 0x480 142*4882a593Smuzhiyun #define WM5100_DAC_DIGITAL_VOLUME_1R 0x481 143*4882a593Smuzhiyun #define WM5100_DAC_DIGITAL_VOLUME_2L 0x482 144*4882a593Smuzhiyun #define WM5100_DAC_DIGITAL_VOLUME_2R 0x483 145*4882a593Smuzhiyun #define WM5100_DAC_DIGITAL_VOLUME_3L 0x484 146*4882a593Smuzhiyun #define WM5100_DAC_DIGITAL_VOLUME_3R 0x485 147*4882a593Smuzhiyun #define WM5100_DAC_DIGITAL_VOLUME_4L 0x486 148*4882a593Smuzhiyun #define WM5100_DAC_DIGITAL_VOLUME_4R 0x487 149*4882a593Smuzhiyun #define WM5100_DAC_DIGITAL_VOLUME_5L 0x488 150*4882a593Smuzhiyun #define WM5100_DAC_DIGITAL_VOLUME_5R 0x489 151*4882a593Smuzhiyun #define WM5100_DAC_DIGITAL_VOLUME_6L 0x48A 152*4882a593Smuzhiyun #define WM5100_DAC_DIGITAL_VOLUME_6R 0x48B 153*4882a593Smuzhiyun #define WM5100_PDM_SPK1_CTRL_1 0x4C0 154*4882a593Smuzhiyun #define WM5100_PDM_SPK1_CTRL_2 0x4C1 155*4882a593Smuzhiyun #define WM5100_PDM_SPK2_CTRL_1 0x4C2 156*4882a593Smuzhiyun #define WM5100_PDM_SPK2_CTRL_2 0x4C3 157*4882a593Smuzhiyun #define WM5100_AUDIO_IF_1_1 0x500 158*4882a593Smuzhiyun #define WM5100_AUDIO_IF_1_2 0x501 159*4882a593Smuzhiyun #define WM5100_AUDIO_IF_1_3 0x502 160*4882a593Smuzhiyun #define WM5100_AUDIO_IF_1_4 0x503 161*4882a593Smuzhiyun #define WM5100_AUDIO_IF_1_5 0x504 162*4882a593Smuzhiyun #define WM5100_AUDIO_IF_1_6 0x505 163*4882a593Smuzhiyun #define WM5100_AUDIO_IF_1_7 0x506 164*4882a593Smuzhiyun #define WM5100_AUDIO_IF_1_8 0x507 165*4882a593Smuzhiyun #define WM5100_AUDIO_IF_1_9 0x508 166*4882a593Smuzhiyun #define WM5100_AUDIO_IF_1_10 0x509 167*4882a593Smuzhiyun #define WM5100_AUDIO_IF_1_11 0x50A 168*4882a593Smuzhiyun #define WM5100_AUDIO_IF_1_12 0x50B 169*4882a593Smuzhiyun #define WM5100_AUDIO_IF_1_13 0x50C 170*4882a593Smuzhiyun #define WM5100_AUDIO_IF_1_14 0x50D 171*4882a593Smuzhiyun #define WM5100_AUDIO_IF_1_15 0x50E 172*4882a593Smuzhiyun #define WM5100_AUDIO_IF_1_16 0x50F 173*4882a593Smuzhiyun #define WM5100_AUDIO_IF_1_17 0x510 174*4882a593Smuzhiyun #define WM5100_AUDIO_IF_1_18 0x511 175*4882a593Smuzhiyun #define WM5100_AUDIO_IF_1_19 0x512 176*4882a593Smuzhiyun #define WM5100_AUDIO_IF_1_20 0x513 177*4882a593Smuzhiyun #define WM5100_AUDIO_IF_1_21 0x514 178*4882a593Smuzhiyun #define WM5100_AUDIO_IF_1_22 0x515 179*4882a593Smuzhiyun #define WM5100_AUDIO_IF_1_23 0x516 180*4882a593Smuzhiyun #define WM5100_AUDIO_IF_1_24 0x517 181*4882a593Smuzhiyun #define WM5100_AUDIO_IF_1_25 0x518 182*4882a593Smuzhiyun #define WM5100_AUDIO_IF_1_26 0x519 183*4882a593Smuzhiyun #define WM5100_AUDIO_IF_1_27 0x51A 184*4882a593Smuzhiyun #define WM5100_AUDIO_IF_2_1 0x540 185*4882a593Smuzhiyun #define WM5100_AUDIO_IF_2_2 0x541 186*4882a593Smuzhiyun #define WM5100_AUDIO_IF_2_3 0x542 187*4882a593Smuzhiyun #define WM5100_AUDIO_IF_2_4 0x543 188*4882a593Smuzhiyun #define WM5100_AUDIO_IF_2_5 0x544 189*4882a593Smuzhiyun #define WM5100_AUDIO_IF_2_6 0x545 190*4882a593Smuzhiyun #define WM5100_AUDIO_IF_2_7 0x546 191*4882a593Smuzhiyun #define WM5100_AUDIO_IF_2_8 0x547 192*4882a593Smuzhiyun #define WM5100_AUDIO_IF_2_9 0x548 193*4882a593Smuzhiyun #define WM5100_AUDIO_IF_2_10 0x549 194*4882a593Smuzhiyun #define WM5100_AUDIO_IF_2_11 0x54A 195*4882a593Smuzhiyun #define WM5100_AUDIO_IF_2_18 0x551 196*4882a593Smuzhiyun #define WM5100_AUDIO_IF_2_19 0x552 197*4882a593Smuzhiyun #define WM5100_AUDIO_IF_2_26 0x559 198*4882a593Smuzhiyun #define WM5100_AUDIO_IF_2_27 0x55A 199*4882a593Smuzhiyun #define WM5100_AUDIO_IF_3_1 0x580 200*4882a593Smuzhiyun #define WM5100_AUDIO_IF_3_2 0x581 201*4882a593Smuzhiyun #define WM5100_AUDIO_IF_3_3 0x582 202*4882a593Smuzhiyun #define WM5100_AUDIO_IF_3_4 0x583 203*4882a593Smuzhiyun #define WM5100_AUDIO_IF_3_5 0x584 204*4882a593Smuzhiyun #define WM5100_AUDIO_IF_3_6 0x585 205*4882a593Smuzhiyun #define WM5100_AUDIO_IF_3_7 0x586 206*4882a593Smuzhiyun #define WM5100_AUDIO_IF_3_8 0x587 207*4882a593Smuzhiyun #define WM5100_AUDIO_IF_3_9 0x588 208*4882a593Smuzhiyun #define WM5100_AUDIO_IF_3_10 0x589 209*4882a593Smuzhiyun #define WM5100_AUDIO_IF_3_11 0x58A 210*4882a593Smuzhiyun #define WM5100_AUDIO_IF_3_18 0x591 211*4882a593Smuzhiyun #define WM5100_AUDIO_IF_3_19 0x592 212*4882a593Smuzhiyun #define WM5100_AUDIO_IF_3_26 0x599 213*4882a593Smuzhiyun #define WM5100_AUDIO_IF_3_27 0x59A 214*4882a593Smuzhiyun #define WM5100_PWM1MIX_INPUT_1_SOURCE 0x640 215*4882a593Smuzhiyun #define WM5100_PWM1MIX_INPUT_1_VOLUME 0x641 216*4882a593Smuzhiyun #define WM5100_PWM1MIX_INPUT_2_SOURCE 0x642 217*4882a593Smuzhiyun #define WM5100_PWM1MIX_INPUT_2_VOLUME 0x643 218*4882a593Smuzhiyun #define WM5100_PWM1MIX_INPUT_3_SOURCE 0x644 219*4882a593Smuzhiyun #define WM5100_PWM1MIX_INPUT_3_VOLUME 0x645 220*4882a593Smuzhiyun #define WM5100_PWM1MIX_INPUT_4_SOURCE 0x646 221*4882a593Smuzhiyun #define WM5100_PWM1MIX_INPUT_4_VOLUME 0x647 222*4882a593Smuzhiyun #define WM5100_PWM2MIX_INPUT_1_SOURCE 0x648 223*4882a593Smuzhiyun #define WM5100_PWM2MIX_INPUT_1_VOLUME 0x649 224*4882a593Smuzhiyun #define WM5100_PWM2MIX_INPUT_2_SOURCE 0x64A 225*4882a593Smuzhiyun #define WM5100_PWM2MIX_INPUT_2_VOLUME 0x64B 226*4882a593Smuzhiyun #define WM5100_PWM2MIX_INPUT_3_SOURCE 0x64C 227*4882a593Smuzhiyun #define WM5100_PWM2MIX_INPUT_3_VOLUME 0x64D 228*4882a593Smuzhiyun #define WM5100_PWM2MIX_INPUT_4_SOURCE 0x64E 229*4882a593Smuzhiyun #define WM5100_PWM2MIX_INPUT_4_VOLUME 0x64F 230*4882a593Smuzhiyun #define WM5100_OUT1LMIX_INPUT_1_SOURCE 0x680 231*4882a593Smuzhiyun #define WM5100_OUT1LMIX_INPUT_1_VOLUME 0x681 232*4882a593Smuzhiyun #define WM5100_OUT1LMIX_INPUT_2_SOURCE 0x682 233*4882a593Smuzhiyun #define WM5100_OUT1LMIX_INPUT_2_VOLUME 0x683 234*4882a593Smuzhiyun #define WM5100_OUT1LMIX_INPUT_3_SOURCE 0x684 235*4882a593Smuzhiyun #define WM5100_OUT1LMIX_INPUT_3_VOLUME 0x685 236*4882a593Smuzhiyun #define WM5100_OUT1LMIX_INPUT_4_SOURCE 0x686 237*4882a593Smuzhiyun #define WM5100_OUT1LMIX_INPUT_4_VOLUME 0x687 238*4882a593Smuzhiyun #define WM5100_OUT1RMIX_INPUT_1_SOURCE 0x688 239*4882a593Smuzhiyun #define WM5100_OUT1RMIX_INPUT_1_VOLUME 0x689 240*4882a593Smuzhiyun #define WM5100_OUT1RMIX_INPUT_2_SOURCE 0x68A 241*4882a593Smuzhiyun #define WM5100_OUT1RMIX_INPUT_2_VOLUME 0x68B 242*4882a593Smuzhiyun #define WM5100_OUT1RMIX_INPUT_3_SOURCE 0x68C 243*4882a593Smuzhiyun #define WM5100_OUT1RMIX_INPUT_3_VOLUME 0x68D 244*4882a593Smuzhiyun #define WM5100_OUT1RMIX_INPUT_4_SOURCE 0x68E 245*4882a593Smuzhiyun #define WM5100_OUT1RMIX_INPUT_4_VOLUME 0x68F 246*4882a593Smuzhiyun #define WM5100_OUT2LMIX_INPUT_1_SOURCE 0x690 247*4882a593Smuzhiyun #define WM5100_OUT2LMIX_INPUT_1_VOLUME 0x691 248*4882a593Smuzhiyun #define WM5100_OUT2LMIX_INPUT_2_SOURCE 0x692 249*4882a593Smuzhiyun #define WM5100_OUT2LMIX_INPUT_2_VOLUME 0x693 250*4882a593Smuzhiyun #define WM5100_OUT2LMIX_INPUT_3_SOURCE 0x694 251*4882a593Smuzhiyun #define WM5100_OUT2LMIX_INPUT_3_VOLUME 0x695 252*4882a593Smuzhiyun #define WM5100_OUT2LMIX_INPUT_4_SOURCE 0x696 253*4882a593Smuzhiyun #define WM5100_OUT2LMIX_INPUT_4_VOLUME 0x697 254*4882a593Smuzhiyun #define WM5100_OUT2RMIX_INPUT_1_SOURCE 0x698 255*4882a593Smuzhiyun #define WM5100_OUT2RMIX_INPUT_1_VOLUME 0x699 256*4882a593Smuzhiyun #define WM5100_OUT2RMIX_INPUT_2_SOURCE 0x69A 257*4882a593Smuzhiyun #define WM5100_OUT2RMIX_INPUT_2_VOLUME 0x69B 258*4882a593Smuzhiyun #define WM5100_OUT2RMIX_INPUT_3_SOURCE 0x69C 259*4882a593Smuzhiyun #define WM5100_OUT2RMIX_INPUT_3_VOLUME 0x69D 260*4882a593Smuzhiyun #define WM5100_OUT2RMIX_INPUT_4_SOURCE 0x69E 261*4882a593Smuzhiyun #define WM5100_OUT2RMIX_INPUT_4_VOLUME 0x69F 262*4882a593Smuzhiyun #define WM5100_OUT3LMIX_INPUT_1_SOURCE 0x6A0 263*4882a593Smuzhiyun #define WM5100_OUT3LMIX_INPUT_1_VOLUME 0x6A1 264*4882a593Smuzhiyun #define WM5100_OUT3LMIX_INPUT_2_SOURCE 0x6A2 265*4882a593Smuzhiyun #define WM5100_OUT3LMIX_INPUT_2_VOLUME 0x6A3 266*4882a593Smuzhiyun #define WM5100_OUT3LMIX_INPUT_3_SOURCE 0x6A4 267*4882a593Smuzhiyun #define WM5100_OUT3LMIX_INPUT_3_VOLUME 0x6A5 268*4882a593Smuzhiyun #define WM5100_OUT3LMIX_INPUT_4_SOURCE 0x6A6 269*4882a593Smuzhiyun #define WM5100_OUT3LMIX_INPUT_4_VOLUME 0x6A7 270*4882a593Smuzhiyun #define WM5100_OUT3RMIX_INPUT_1_SOURCE 0x6A8 271*4882a593Smuzhiyun #define WM5100_OUT3RMIX_INPUT_1_VOLUME 0x6A9 272*4882a593Smuzhiyun #define WM5100_OUT3RMIX_INPUT_2_SOURCE 0x6AA 273*4882a593Smuzhiyun #define WM5100_OUT3RMIX_INPUT_2_VOLUME 0x6AB 274*4882a593Smuzhiyun #define WM5100_OUT3RMIX_INPUT_3_SOURCE 0x6AC 275*4882a593Smuzhiyun #define WM5100_OUT3RMIX_INPUT_3_VOLUME 0x6AD 276*4882a593Smuzhiyun #define WM5100_OUT3RMIX_INPUT_4_SOURCE 0x6AE 277*4882a593Smuzhiyun #define WM5100_OUT3RMIX_INPUT_4_VOLUME 0x6AF 278*4882a593Smuzhiyun #define WM5100_OUT4LMIX_INPUT_1_SOURCE 0x6B0 279*4882a593Smuzhiyun #define WM5100_OUT4LMIX_INPUT_1_VOLUME 0x6B1 280*4882a593Smuzhiyun #define WM5100_OUT4LMIX_INPUT_2_SOURCE 0x6B2 281*4882a593Smuzhiyun #define WM5100_OUT4LMIX_INPUT_2_VOLUME 0x6B3 282*4882a593Smuzhiyun #define WM5100_OUT4LMIX_INPUT_3_SOURCE 0x6B4 283*4882a593Smuzhiyun #define WM5100_OUT4LMIX_INPUT_3_VOLUME 0x6B5 284*4882a593Smuzhiyun #define WM5100_OUT4LMIX_INPUT_4_SOURCE 0x6B6 285*4882a593Smuzhiyun #define WM5100_OUT4LMIX_INPUT_4_VOLUME 0x6B7 286*4882a593Smuzhiyun #define WM5100_OUT4RMIX_INPUT_1_SOURCE 0x6B8 287*4882a593Smuzhiyun #define WM5100_OUT4RMIX_INPUT_1_VOLUME 0x6B9 288*4882a593Smuzhiyun #define WM5100_OUT4RMIX_INPUT_2_SOURCE 0x6BA 289*4882a593Smuzhiyun #define WM5100_OUT4RMIX_INPUT_2_VOLUME 0x6BB 290*4882a593Smuzhiyun #define WM5100_OUT4RMIX_INPUT_3_SOURCE 0x6BC 291*4882a593Smuzhiyun #define WM5100_OUT4RMIX_INPUT_3_VOLUME 0x6BD 292*4882a593Smuzhiyun #define WM5100_OUT4RMIX_INPUT_4_SOURCE 0x6BE 293*4882a593Smuzhiyun #define WM5100_OUT4RMIX_INPUT_4_VOLUME 0x6BF 294*4882a593Smuzhiyun #define WM5100_OUT5LMIX_INPUT_1_SOURCE 0x6C0 295*4882a593Smuzhiyun #define WM5100_OUT5LMIX_INPUT_1_VOLUME 0x6C1 296*4882a593Smuzhiyun #define WM5100_OUT5LMIX_INPUT_2_SOURCE 0x6C2 297*4882a593Smuzhiyun #define WM5100_OUT5LMIX_INPUT_2_VOLUME 0x6C3 298*4882a593Smuzhiyun #define WM5100_OUT5LMIX_INPUT_3_SOURCE 0x6C4 299*4882a593Smuzhiyun #define WM5100_OUT5LMIX_INPUT_3_VOLUME 0x6C5 300*4882a593Smuzhiyun #define WM5100_OUT5LMIX_INPUT_4_SOURCE 0x6C6 301*4882a593Smuzhiyun #define WM5100_OUT5LMIX_INPUT_4_VOLUME 0x6C7 302*4882a593Smuzhiyun #define WM5100_OUT5RMIX_INPUT_1_SOURCE 0x6C8 303*4882a593Smuzhiyun #define WM5100_OUT5RMIX_INPUT_1_VOLUME 0x6C9 304*4882a593Smuzhiyun #define WM5100_OUT5RMIX_INPUT_2_SOURCE 0x6CA 305*4882a593Smuzhiyun #define WM5100_OUT5RMIX_INPUT_2_VOLUME 0x6CB 306*4882a593Smuzhiyun #define WM5100_OUT5RMIX_INPUT_3_SOURCE 0x6CC 307*4882a593Smuzhiyun #define WM5100_OUT5RMIX_INPUT_3_VOLUME 0x6CD 308*4882a593Smuzhiyun #define WM5100_OUT5RMIX_INPUT_4_SOURCE 0x6CE 309*4882a593Smuzhiyun #define WM5100_OUT5RMIX_INPUT_4_VOLUME 0x6CF 310*4882a593Smuzhiyun #define WM5100_OUT6LMIX_INPUT_1_SOURCE 0x6D0 311*4882a593Smuzhiyun #define WM5100_OUT6LMIX_INPUT_1_VOLUME 0x6D1 312*4882a593Smuzhiyun #define WM5100_OUT6LMIX_INPUT_2_SOURCE 0x6D2 313*4882a593Smuzhiyun #define WM5100_OUT6LMIX_INPUT_2_VOLUME 0x6D3 314*4882a593Smuzhiyun #define WM5100_OUT6LMIX_INPUT_3_SOURCE 0x6D4 315*4882a593Smuzhiyun #define WM5100_OUT6LMIX_INPUT_3_VOLUME 0x6D5 316*4882a593Smuzhiyun #define WM5100_OUT6LMIX_INPUT_4_SOURCE 0x6D6 317*4882a593Smuzhiyun #define WM5100_OUT6LMIX_INPUT_4_VOLUME 0x6D7 318*4882a593Smuzhiyun #define WM5100_OUT6RMIX_INPUT_1_SOURCE 0x6D8 319*4882a593Smuzhiyun #define WM5100_OUT6RMIX_INPUT_1_VOLUME 0x6D9 320*4882a593Smuzhiyun #define WM5100_OUT6RMIX_INPUT_2_SOURCE 0x6DA 321*4882a593Smuzhiyun #define WM5100_OUT6RMIX_INPUT_2_VOLUME 0x6DB 322*4882a593Smuzhiyun #define WM5100_OUT6RMIX_INPUT_3_SOURCE 0x6DC 323*4882a593Smuzhiyun #define WM5100_OUT6RMIX_INPUT_3_VOLUME 0x6DD 324*4882a593Smuzhiyun #define WM5100_OUT6RMIX_INPUT_4_SOURCE 0x6DE 325*4882a593Smuzhiyun #define WM5100_OUT6RMIX_INPUT_4_VOLUME 0x6DF 326*4882a593Smuzhiyun #define WM5100_AIF1TX1MIX_INPUT_1_SOURCE 0x700 327*4882a593Smuzhiyun #define WM5100_AIF1TX1MIX_INPUT_1_VOLUME 0x701 328*4882a593Smuzhiyun #define WM5100_AIF1TX1MIX_INPUT_2_SOURCE 0x702 329*4882a593Smuzhiyun #define WM5100_AIF1TX1MIX_INPUT_2_VOLUME 0x703 330*4882a593Smuzhiyun #define WM5100_AIF1TX1MIX_INPUT_3_SOURCE 0x704 331*4882a593Smuzhiyun #define WM5100_AIF1TX1MIX_INPUT_3_VOLUME 0x705 332*4882a593Smuzhiyun #define WM5100_AIF1TX1MIX_INPUT_4_SOURCE 0x706 333*4882a593Smuzhiyun #define WM5100_AIF1TX1MIX_INPUT_4_VOLUME 0x707 334*4882a593Smuzhiyun #define WM5100_AIF1TX2MIX_INPUT_1_SOURCE 0x708 335*4882a593Smuzhiyun #define WM5100_AIF1TX2MIX_INPUT_1_VOLUME 0x709 336*4882a593Smuzhiyun #define WM5100_AIF1TX2MIX_INPUT_2_SOURCE 0x70A 337*4882a593Smuzhiyun #define WM5100_AIF1TX2MIX_INPUT_2_VOLUME 0x70B 338*4882a593Smuzhiyun #define WM5100_AIF1TX2MIX_INPUT_3_SOURCE 0x70C 339*4882a593Smuzhiyun #define WM5100_AIF1TX2MIX_INPUT_3_VOLUME 0x70D 340*4882a593Smuzhiyun #define WM5100_AIF1TX2MIX_INPUT_4_SOURCE 0x70E 341*4882a593Smuzhiyun #define WM5100_AIF1TX2MIX_INPUT_4_VOLUME 0x70F 342*4882a593Smuzhiyun #define WM5100_AIF1TX3MIX_INPUT_1_SOURCE 0x710 343*4882a593Smuzhiyun #define WM5100_AIF1TX3MIX_INPUT_1_VOLUME 0x711 344*4882a593Smuzhiyun #define WM5100_AIF1TX3MIX_INPUT_2_SOURCE 0x712 345*4882a593Smuzhiyun #define WM5100_AIF1TX3MIX_INPUT_2_VOLUME 0x713 346*4882a593Smuzhiyun #define WM5100_AIF1TX3MIX_INPUT_3_SOURCE 0x714 347*4882a593Smuzhiyun #define WM5100_AIF1TX3MIX_INPUT_3_VOLUME 0x715 348*4882a593Smuzhiyun #define WM5100_AIF1TX3MIX_INPUT_4_SOURCE 0x716 349*4882a593Smuzhiyun #define WM5100_AIF1TX3MIX_INPUT_4_VOLUME 0x717 350*4882a593Smuzhiyun #define WM5100_AIF1TX4MIX_INPUT_1_SOURCE 0x718 351*4882a593Smuzhiyun #define WM5100_AIF1TX4MIX_INPUT_1_VOLUME 0x719 352*4882a593Smuzhiyun #define WM5100_AIF1TX4MIX_INPUT_2_SOURCE 0x71A 353*4882a593Smuzhiyun #define WM5100_AIF1TX4MIX_INPUT_2_VOLUME 0x71B 354*4882a593Smuzhiyun #define WM5100_AIF1TX4MIX_INPUT_3_SOURCE 0x71C 355*4882a593Smuzhiyun #define WM5100_AIF1TX4MIX_INPUT_3_VOLUME 0x71D 356*4882a593Smuzhiyun #define WM5100_AIF1TX4MIX_INPUT_4_SOURCE 0x71E 357*4882a593Smuzhiyun #define WM5100_AIF1TX4MIX_INPUT_4_VOLUME 0x71F 358*4882a593Smuzhiyun #define WM5100_AIF1TX5MIX_INPUT_1_SOURCE 0x720 359*4882a593Smuzhiyun #define WM5100_AIF1TX5MIX_INPUT_1_VOLUME 0x721 360*4882a593Smuzhiyun #define WM5100_AIF1TX5MIX_INPUT_2_SOURCE 0x722 361*4882a593Smuzhiyun #define WM5100_AIF1TX5MIX_INPUT_2_VOLUME 0x723 362*4882a593Smuzhiyun #define WM5100_AIF1TX5MIX_INPUT_3_SOURCE 0x724 363*4882a593Smuzhiyun #define WM5100_AIF1TX5MIX_INPUT_3_VOLUME 0x725 364*4882a593Smuzhiyun #define WM5100_AIF1TX5MIX_INPUT_4_SOURCE 0x726 365*4882a593Smuzhiyun #define WM5100_AIF1TX5MIX_INPUT_4_VOLUME 0x727 366*4882a593Smuzhiyun #define WM5100_AIF1TX6MIX_INPUT_1_SOURCE 0x728 367*4882a593Smuzhiyun #define WM5100_AIF1TX6MIX_INPUT_1_VOLUME 0x729 368*4882a593Smuzhiyun #define WM5100_AIF1TX6MIX_INPUT_2_SOURCE 0x72A 369*4882a593Smuzhiyun #define WM5100_AIF1TX6MIX_INPUT_2_VOLUME 0x72B 370*4882a593Smuzhiyun #define WM5100_AIF1TX6MIX_INPUT_3_SOURCE 0x72C 371*4882a593Smuzhiyun #define WM5100_AIF1TX6MIX_INPUT_3_VOLUME 0x72D 372*4882a593Smuzhiyun #define WM5100_AIF1TX6MIX_INPUT_4_SOURCE 0x72E 373*4882a593Smuzhiyun #define WM5100_AIF1TX6MIX_INPUT_4_VOLUME 0x72F 374*4882a593Smuzhiyun #define WM5100_AIF1TX7MIX_INPUT_1_SOURCE 0x730 375*4882a593Smuzhiyun #define WM5100_AIF1TX7MIX_INPUT_1_VOLUME 0x731 376*4882a593Smuzhiyun #define WM5100_AIF1TX7MIX_INPUT_2_SOURCE 0x732 377*4882a593Smuzhiyun #define WM5100_AIF1TX7MIX_INPUT_2_VOLUME 0x733 378*4882a593Smuzhiyun #define WM5100_AIF1TX7MIX_INPUT_3_SOURCE 0x734 379*4882a593Smuzhiyun #define WM5100_AIF1TX7MIX_INPUT_3_VOLUME 0x735 380*4882a593Smuzhiyun #define WM5100_AIF1TX7MIX_INPUT_4_SOURCE 0x736 381*4882a593Smuzhiyun #define WM5100_AIF1TX7MIX_INPUT_4_VOLUME 0x737 382*4882a593Smuzhiyun #define WM5100_AIF1TX8MIX_INPUT_1_SOURCE 0x738 383*4882a593Smuzhiyun #define WM5100_AIF1TX8MIX_INPUT_1_VOLUME 0x739 384*4882a593Smuzhiyun #define WM5100_AIF1TX8MIX_INPUT_2_SOURCE 0x73A 385*4882a593Smuzhiyun #define WM5100_AIF1TX8MIX_INPUT_2_VOLUME 0x73B 386*4882a593Smuzhiyun #define WM5100_AIF1TX8MIX_INPUT_3_SOURCE 0x73C 387*4882a593Smuzhiyun #define WM5100_AIF1TX8MIX_INPUT_3_VOLUME 0x73D 388*4882a593Smuzhiyun #define WM5100_AIF1TX8MIX_INPUT_4_SOURCE 0x73E 389*4882a593Smuzhiyun #define WM5100_AIF1TX8MIX_INPUT_4_VOLUME 0x73F 390*4882a593Smuzhiyun #define WM5100_AIF2TX1MIX_INPUT_1_SOURCE 0x740 391*4882a593Smuzhiyun #define WM5100_AIF2TX1MIX_INPUT_1_VOLUME 0x741 392*4882a593Smuzhiyun #define WM5100_AIF2TX1MIX_INPUT_2_SOURCE 0x742 393*4882a593Smuzhiyun #define WM5100_AIF2TX1MIX_INPUT_2_VOLUME 0x743 394*4882a593Smuzhiyun #define WM5100_AIF2TX1MIX_INPUT_3_SOURCE 0x744 395*4882a593Smuzhiyun #define WM5100_AIF2TX1MIX_INPUT_3_VOLUME 0x745 396*4882a593Smuzhiyun #define WM5100_AIF2TX1MIX_INPUT_4_SOURCE 0x746 397*4882a593Smuzhiyun #define WM5100_AIF2TX1MIX_INPUT_4_VOLUME 0x747 398*4882a593Smuzhiyun #define WM5100_AIF2TX2MIX_INPUT_1_SOURCE 0x748 399*4882a593Smuzhiyun #define WM5100_AIF2TX2MIX_INPUT_1_VOLUME 0x749 400*4882a593Smuzhiyun #define WM5100_AIF2TX2MIX_INPUT_2_SOURCE 0x74A 401*4882a593Smuzhiyun #define WM5100_AIF2TX2MIX_INPUT_2_VOLUME 0x74B 402*4882a593Smuzhiyun #define WM5100_AIF2TX2MIX_INPUT_3_SOURCE 0x74C 403*4882a593Smuzhiyun #define WM5100_AIF2TX2MIX_INPUT_3_VOLUME 0x74D 404*4882a593Smuzhiyun #define WM5100_AIF2TX2MIX_INPUT_4_SOURCE 0x74E 405*4882a593Smuzhiyun #define WM5100_AIF2TX2MIX_INPUT_4_VOLUME 0x74F 406*4882a593Smuzhiyun #define WM5100_AIF3TX1MIX_INPUT_1_SOURCE 0x780 407*4882a593Smuzhiyun #define WM5100_AIF3TX1MIX_INPUT_1_VOLUME 0x781 408*4882a593Smuzhiyun #define WM5100_AIF3TX1MIX_INPUT_2_SOURCE 0x782 409*4882a593Smuzhiyun #define WM5100_AIF3TX1MIX_INPUT_2_VOLUME 0x783 410*4882a593Smuzhiyun #define WM5100_AIF3TX1MIX_INPUT_3_SOURCE 0x784 411*4882a593Smuzhiyun #define WM5100_AIF3TX1MIX_INPUT_3_VOLUME 0x785 412*4882a593Smuzhiyun #define WM5100_AIF3TX1MIX_INPUT_4_SOURCE 0x786 413*4882a593Smuzhiyun #define WM5100_AIF3TX1MIX_INPUT_4_VOLUME 0x787 414*4882a593Smuzhiyun #define WM5100_AIF3TX2MIX_INPUT_1_SOURCE 0x788 415*4882a593Smuzhiyun #define WM5100_AIF3TX2MIX_INPUT_1_VOLUME 0x789 416*4882a593Smuzhiyun #define WM5100_AIF3TX2MIX_INPUT_2_SOURCE 0x78A 417*4882a593Smuzhiyun #define WM5100_AIF3TX2MIX_INPUT_2_VOLUME 0x78B 418*4882a593Smuzhiyun #define WM5100_AIF3TX2MIX_INPUT_3_SOURCE 0x78C 419*4882a593Smuzhiyun #define WM5100_AIF3TX2MIX_INPUT_3_VOLUME 0x78D 420*4882a593Smuzhiyun #define WM5100_AIF3TX2MIX_INPUT_4_SOURCE 0x78E 421*4882a593Smuzhiyun #define WM5100_AIF3TX2MIX_INPUT_4_VOLUME 0x78F 422*4882a593Smuzhiyun #define WM5100_EQ1MIX_INPUT_1_SOURCE 0x880 423*4882a593Smuzhiyun #define WM5100_EQ1MIX_INPUT_1_VOLUME 0x881 424*4882a593Smuzhiyun #define WM5100_EQ1MIX_INPUT_2_SOURCE 0x882 425*4882a593Smuzhiyun #define WM5100_EQ1MIX_INPUT_2_VOLUME 0x883 426*4882a593Smuzhiyun #define WM5100_EQ1MIX_INPUT_3_SOURCE 0x884 427*4882a593Smuzhiyun #define WM5100_EQ1MIX_INPUT_3_VOLUME 0x885 428*4882a593Smuzhiyun #define WM5100_EQ1MIX_INPUT_4_SOURCE 0x886 429*4882a593Smuzhiyun #define WM5100_EQ1MIX_INPUT_4_VOLUME 0x887 430*4882a593Smuzhiyun #define WM5100_EQ2MIX_INPUT_1_SOURCE 0x888 431*4882a593Smuzhiyun #define WM5100_EQ2MIX_INPUT_1_VOLUME 0x889 432*4882a593Smuzhiyun #define WM5100_EQ2MIX_INPUT_2_SOURCE 0x88A 433*4882a593Smuzhiyun #define WM5100_EQ2MIX_INPUT_2_VOLUME 0x88B 434*4882a593Smuzhiyun #define WM5100_EQ2MIX_INPUT_3_SOURCE 0x88C 435*4882a593Smuzhiyun #define WM5100_EQ2MIX_INPUT_3_VOLUME 0x88D 436*4882a593Smuzhiyun #define WM5100_EQ2MIX_INPUT_4_SOURCE 0x88E 437*4882a593Smuzhiyun #define WM5100_EQ2MIX_INPUT_4_VOLUME 0x88F 438*4882a593Smuzhiyun #define WM5100_EQ3MIX_INPUT_1_SOURCE 0x890 439*4882a593Smuzhiyun #define WM5100_EQ3MIX_INPUT_1_VOLUME 0x891 440*4882a593Smuzhiyun #define WM5100_EQ3MIX_INPUT_2_SOURCE 0x892 441*4882a593Smuzhiyun #define WM5100_EQ3MIX_INPUT_2_VOLUME 0x893 442*4882a593Smuzhiyun #define WM5100_EQ3MIX_INPUT_3_SOURCE 0x894 443*4882a593Smuzhiyun #define WM5100_EQ3MIX_INPUT_3_VOLUME 0x895 444*4882a593Smuzhiyun #define WM5100_EQ3MIX_INPUT_4_SOURCE 0x896 445*4882a593Smuzhiyun #define WM5100_EQ3MIX_INPUT_4_VOLUME 0x897 446*4882a593Smuzhiyun #define WM5100_EQ4MIX_INPUT_1_SOURCE 0x898 447*4882a593Smuzhiyun #define WM5100_EQ4MIX_INPUT_1_VOLUME 0x899 448*4882a593Smuzhiyun #define WM5100_EQ4MIX_INPUT_2_SOURCE 0x89A 449*4882a593Smuzhiyun #define WM5100_EQ4MIX_INPUT_2_VOLUME 0x89B 450*4882a593Smuzhiyun #define WM5100_EQ4MIX_INPUT_3_SOURCE 0x89C 451*4882a593Smuzhiyun #define WM5100_EQ4MIX_INPUT_3_VOLUME 0x89D 452*4882a593Smuzhiyun #define WM5100_EQ4MIX_INPUT_4_SOURCE 0x89E 453*4882a593Smuzhiyun #define WM5100_EQ4MIX_INPUT_4_VOLUME 0x89F 454*4882a593Smuzhiyun #define WM5100_DRC1LMIX_INPUT_1_SOURCE 0x8C0 455*4882a593Smuzhiyun #define WM5100_DRC1LMIX_INPUT_1_VOLUME 0x8C1 456*4882a593Smuzhiyun #define WM5100_DRC1LMIX_INPUT_2_SOURCE 0x8C2 457*4882a593Smuzhiyun #define WM5100_DRC1LMIX_INPUT_2_VOLUME 0x8C3 458*4882a593Smuzhiyun #define WM5100_DRC1LMIX_INPUT_3_SOURCE 0x8C4 459*4882a593Smuzhiyun #define WM5100_DRC1LMIX_INPUT_3_VOLUME 0x8C5 460*4882a593Smuzhiyun #define WM5100_DRC1LMIX_INPUT_4_SOURCE 0x8C6 461*4882a593Smuzhiyun #define WM5100_DRC1LMIX_INPUT_4_VOLUME 0x8C7 462*4882a593Smuzhiyun #define WM5100_DRC1RMIX_INPUT_1_SOURCE 0x8C8 463*4882a593Smuzhiyun #define WM5100_DRC1RMIX_INPUT_1_VOLUME 0x8C9 464*4882a593Smuzhiyun #define WM5100_DRC1RMIX_INPUT_2_SOURCE 0x8CA 465*4882a593Smuzhiyun #define WM5100_DRC1RMIX_INPUT_2_VOLUME 0x8CB 466*4882a593Smuzhiyun #define WM5100_DRC1RMIX_INPUT_3_SOURCE 0x8CC 467*4882a593Smuzhiyun #define WM5100_DRC1RMIX_INPUT_3_VOLUME 0x8CD 468*4882a593Smuzhiyun #define WM5100_DRC1RMIX_INPUT_4_SOURCE 0x8CE 469*4882a593Smuzhiyun #define WM5100_DRC1RMIX_INPUT_4_VOLUME 0x8CF 470*4882a593Smuzhiyun #define WM5100_HPLP1MIX_INPUT_1_SOURCE 0x900 471*4882a593Smuzhiyun #define WM5100_HPLP1MIX_INPUT_1_VOLUME 0x901 472*4882a593Smuzhiyun #define WM5100_HPLP1MIX_INPUT_2_SOURCE 0x902 473*4882a593Smuzhiyun #define WM5100_HPLP1MIX_INPUT_2_VOLUME 0x903 474*4882a593Smuzhiyun #define WM5100_HPLP1MIX_INPUT_3_SOURCE 0x904 475*4882a593Smuzhiyun #define WM5100_HPLP1MIX_INPUT_3_VOLUME 0x905 476*4882a593Smuzhiyun #define WM5100_HPLP1MIX_INPUT_4_SOURCE 0x906 477*4882a593Smuzhiyun #define WM5100_HPLP1MIX_INPUT_4_VOLUME 0x907 478*4882a593Smuzhiyun #define WM5100_HPLP2MIX_INPUT_1_SOURCE 0x908 479*4882a593Smuzhiyun #define WM5100_HPLP2MIX_INPUT_1_VOLUME 0x909 480*4882a593Smuzhiyun #define WM5100_HPLP2MIX_INPUT_2_SOURCE 0x90A 481*4882a593Smuzhiyun #define WM5100_HPLP2MIX_INPUT_2_VOLUME 0x90B 482*4882a593Smuzhiyun #define WM5100_HPLP2MIX_INPUT_3_SOURCE 0x90C 483*4882a593Smuzhiyun #define WM5100_HPLP2MIX_INPUT_3_VOLUME 0x90D 484*4882a593Smuzhiyun #define WM5100_HPLP2MIX_INPUT_4_SOURCE 0x90E 485*4882a593Smuzhiyun #define WM5100_HPLP2MIX_INPUT_4_VOLUME 0x90F 486*4882a593Smuzhiyun #define WM5100_HPLP3MIX_INPUT_1_SOURCE 0x910 487*4882a593Smuzhiyun #define WM5100_HPLP3MIX_INPUT_1_VOLUME 0x911 488*4882a593Smuzhiyun #define WM5100_HPLP3MIX_INPUT_2_SOURCE 0x912 489*4882a593Smuzhiyun #define WM5100_HPLP3MIX_INPUT_2_VOLUME 0x913 490*4882a593Smuzhiyun #define WM5100_HPLP3MIX_INPUT_3_SOURCE 0x914 491*4882a593Smuzhiyun #define WM5100_HPLP3MIX_INPUT_3_VOLUME 0x915 492*4882a593Smuzhiyun #define WM5100_HPLP3MIX_INPUT_4_SOURCE 0x916 493*4882a593Smuzhiyun #define WM5100_HPLP3MIX_INPUT_4_VOLUME 0x917 494*4882a593Smuzhiyun #define WM5100_HPLP4MIX_INPUT_1_SOURCE 0x918 495*4882a593Smuzhiyun #define WM5100_HPLP4MIX_INPUT_1_VOLUME 0x919 496*4882a593Smuzhiyun #define WM5100_HPLP4MIX_INPUT_2_SOURCE 0x91A 497*4882a593Smuzhiyun #define WM5100_HPLP4MIX_INPUT_2_VOLUME 0x91B 498*4882a593Smuzhiyun #define WM5100_HPLP4MIX_INPUT_3_SOURCE 0x91C 499*4882a593Smuzhiyun #define WM5100_HPLP4MIX_INPUT_3_VOLUME 0x91D 500*4882a593Smuzhiyun #define WM5100_HPLP4MIX_INPUT_4_SOURCE 0x91E 501*4882a593Smuzhiyun #define WM5100_HPLP4MIX_INPUT_4_VOLUME 0x91F 502*4882a593Smuzhiyun #define WM5100_DSP1LMIX_INPUT_1_SOURCE 0x940 503*4882a593Smuzhiyun #define WM5100_DSP1LMIX_INPUT_1_VOLUME 0x941 504*4882a593Smuzhiyun #define WM5100_DSP1LMIX_INPUT_2_SOURCE 0x942 505*4882a593Smuzhiyun #define WM5100_DSP1LMIX_INPUT_2_VOLUME 0x943 506*4882a593Smuzhiyun #define WM5100_DSP1LMIX_INPUT_3_SOURCE 0x944 507*4882a593Smuzhiyun #define WM5100_DSP1LMIX_INPUT_3_VOLUME 0x945 508*4882a593Smuzhiyun #define WM5100_DSP1LMIX_INPUT_4_SOURCE 0x946 509*4882a593Smuzhiyun #define WM5100_DSP1LMIX_INPUT_4_VOLUME 0x947 510*4882a593Smuzhiyun #define WM5100_DSP1RMIX_INPUT_1_SOURCE 0x948 511*4882a593Smuzhiyun #define WM5100_DSP1RMIX_INPUT_1_VOLUME 0x949 512*4882a593Smuzhiyun #define WM5100_DSP1RMIX_INPUT_2_SOURCE 0x94A 513*4882a593Smuzhiyun #define WM5100_DSP1RMIX_INPUT_2_VOLUME 0x94B 514*4882a593Smuzhiyun #define WM5100_DSP1RMIX_INPUT_3_SOURCE 0x94C 515*4882a593Smuzhiyun #define WM5100_DSP1RMIX_INPUT_3_VOLUME 0x94D 516*4882a593Smuzhiyun #define WM5100_DSP1RMIX_INPUT_4_SOURCE 0x94E 517*4882a593Smuzhiyun #define WM5100_DSP1RMIX_INPUT_4_VOLUME 0x94F 518*4882a593Smuzhiyun #define WM5100_DSP1AUX1MIX_INPUT_1_SOURCE 0x950 519*4882a593Smuzhiyun #define WM5100_DSP1AUX2MIX_INPUT_1_SOURCE 0x958 520*4882a593Smuzhiyun #define WM5100_DSP1AUX3MIX_INPUT_1_SOURCE 0x960 521*4882a593Smuzhiyun #define WM5100_DSP1AUX4MIX_INPUT_1_SOURCE 0x968 522*4882a593Smuzhiyun #define WM5100_DSP1AUX5MIX_INPUT_1_SOURCE 0x970 523*4882a593Smuzhiyun #define WM5100_DSP1AUX6MIX_INPUT_1_SOURCE 0x978 524*4882a593Smuzhiyun #define WM5100_DSP2LMIX_INPUT_1_SOURCE 0x980 525*4882a593Smuzhiyun #define WM5100_DSP2LMIX_INPUT_1_VOLUME 0x981 526*4882a593Smuzhiyun #define WM5100_DSP2LMIX_INPUT_2_SOURCE 0x982 527*4882a593Smuzhiyun #define WM5100_DSP2LMIX_INPUT_2_VOLUME 0x983 528*4882a593Smuzhiyun #define WM5100_DSP2LMIX_INPUT_3_SOURCE 0x984 529*4882a593Smuzhiyun #define WM5100_DSP2LMIX_INPUT_3_VOLUME 0x985 530*4882a593Smuzhiyun #define WM5100_DSP2LMIX_INPUT_4_SOURCE 0x986 531*4882a593Smuzhiyun #define WM5100_DSP2LMIX_INPUT_4_VOLUME 0x987 532*4882a593Smuzhiyun #define WM5100_DSP2RMIX_INPUT_1_SOURCE 0x988 533*4882a593Smuzhiyun #define WM5100_DSP2RMIX_INPUT_1_VOLUME 0x989 534*4882a593Smuzhiyun #define WM5100_DSP2RMIX_INPUT_2_SOURCE 0x98A 535*4882a593Smuzhiyun #define WM5100_DSP2RMIX_INPUT_2_VOLUME 0x98B 536*4882a593Smuzhiyun #define WM5100_DSP2RMIX_INPUT_3_SOURCE 0x98C 537*4882a593Smuzhiyun #define WM5100_DSP2RMIX_INPUT_3_VOLUME 0x98D 538*4882a593Smuzhiyun #define WM5100_DSP2RMIX_INPUT_4_SOURCE 0x98E 539*4882a593Smuzhiyun #define WM5100_DSP2RMIX_INPUT_4_VOLUME 0x98F 540*4882a593Smuzhiyun #define WM5100_DSP2AUX1MIX_INPUT_1_SOURCE 0x990 541*4882a593Smuzhiyun #define WM5100_DSP2AUX2MIX_INPUT_1_SOURCE 0x998 542*4882a593Smuzhiyun #define WM5100_DSP2AUX3MIX_INPUT_1_SOURCE 0x9A0 543*4882a593Smuzhiyun #define WM5100_DSP2AUX4MIX_INPUT_1_SOURCE 0x9A8 544*4882a593Smuzhiyun #define WM5100_DSP2AUX5MIX_INPUT_1_SOURCE 0x9B0 545*4882a593Smuzhiyun #define WM5100_DSP2AUX6MIX_INPUT_1_SOURCE 0x9B8 546*4882a593Smuzhiyun #define WM5100_DSP3LMIX_INPUT_1_SOURCE 0x9C0 547*4882a593Smuzhiyun #define WM5100_DSP3LMIX_INPUT_1_VOLUME 0x9C1 548*4882a593Smuzhiyun #define WM5100_DSP3LMIX_INPUT_2_SOURCE 0x9C2 549*4882a593Smuzhiyun #define WM5100_DSP3LMIX_INPUT_2_VOLUME 0x9C3 550*4882a593Smuzhiyun #define WM5100_DSP3LMIX_INPUT_3_SOURCE 0x9C4 551*4882a593Smuzhiyun #define WM5100_DSP3LMIX_INPUT_3_VOLUME 0x9C5 552*4882a593Smuzhiyun #define WM5100_DSP3LMIX_INPUT_4_SOURCE 0x9C6 553*4882a593Smuzhiyun #define WM5100_DSP3LMIX_INPUT_4_VOLUME 0x9C7 554*4882a593Smuzhiyun #define WM5100_DSP3RMIX_INPUT_1_SOURCE 0x9C8 555*4882a593Smuzhiyun #define WM5100_DSP3RMIX_INPUT_1_VOLUME 0x9C9 556*4882a593Smuzhiyun #define WM5100_DSP3RMIX_INPUT_2_SOURCE 0x9CA 557*4882a593Smuzhiyun #define WM5100_DSP3RMIX_INPUT_2_VOLUME 0x9CB 558*4882a593Smuzhiyun #define WM5100_DSP3RMIX_INPUT_3_SOURCE 0x9CC 559*4882a593Smuzhiyun #define WM5100_DSP3RMIX_INPUT_3_VOLUME 0x9CD 560*4882a593Smuzhiyun #define WM5100_DSP3RMIX_INPUT_4_SOURCE 0x9CE 561*4882a593Smuzhiyun #define WM5100_DSP3RMIX_INPUT_4_VOLUME 0x9CF 562*4882a593Smuzhiyun #define WM5100_DSP3AUX1MIX_INPUT_1_SOURCE 0x9D0 563*4882a593Smuzhiyun #define WM5100_DSP3AUX2MIX_INPUT_1_SOURCE 0x9D8 564*4882a593Smuzhiyun #define WM5100_DSP3AUX3MIX_INPUT_1_SOURCE 0x9E0 565*4882a593Smuzhiyun #define WM5100_DSP3AUX4MIX_INPUT_1_SOURCE 0x9E8 566*4882a593Smuzhiyun #define WM5100_DSP3AUX5MIX_INPUT_1_SOURCE 0x9F0 567*4882a593Smuzhiyun #define WM5100_DSP3AUX6MIX_INPUT_1_SOURCE 0x9F8 568*4882a593Smuzhiyun #define WM5100_ASRC1LMIX_INPUT_1_SOURCE 0xA80 569*4882a593Smuzhiyun #define WM5100_ASRC1RMIX_INPUT_1_SOURCE 0xA88 570*4882a593Smuzhiyun #define WM5100_ASRC2LMIX_INPUT_1_SOURCE 0xA90 571*4882a593Smuzhiyun #define WM5100_ASRC2RMIX_INPUT_1_SOURCE 0xA98 572*4882a593Smuzhiyun #define WM5100_ISRC1DEC1MIX_INPUT_1_SOURCE 0xB00 573*4882a593Smuzhiyun #define WM5100_ISRC1DEC2MIX_INPUT_1_SOURCE 0xB08 574*4882a593Smuzhiyun #define WM5100_ISRC1DEC3MIX_INPUT_1_SOURCE 0xB10 575*4882a593Smuzhiyun #define WM5100_ISRC1DEC4MIX_INPUT_1_SOURCE 0xB18 576*4882a593Smuzhiyun #define WM5100_ISRC1INT1MIX_INPUT_1_SOURCE 0xB20 577*4882a593Smuzhiyun #define WM5100_ISRC1INT2MIX_INPUT_1_SOURCE 0xB28 578*4882a593Smuzhiyun #define WM5100_ISRC1INT3MIX_INPUT_1_SOURCE 0xB30 579*4882a593Smuzhiyun #define WM5100_ISRC1INT4MIX_INPUT_1_SOURCE 0xB38 580*4882a593Smuzhiyun #define WM5100_ISRC2DEC1MIX_INPUT_1_SOURCE 0xB40 581*4882a593Smuzhiyun #define WM5100_ISRC2DEC2MIX_INPUT_1_SOURCE 0xB48 582*4882a593Smuzhiyun #define WM5100_ISRC2DEC3MIX_INPUT_1_SOURCE 0xB50 583*4882a593Smuzhiyun #define WM5100_ISRC2DEC4MIX_INPUT_1_SOURCE 0xB58 584*4882a593Smuzhiyun #define WM5100_ISRC2INT1MIX_INPUT_1_SOURCE 0xB60 585*4882a593Smuzhiyun #define WM5100_ISRC2INT2MIX_INPUT_1_SOURCE 0xB68 586*4882a593Smuzhiyun #define WM5100_ISRC2INT3MIX_INPUT_1_SOURCE 0xB70 587*4882a593Smuzhiyun #define WM5100_ISRC2INT4MIX_INPUT_1_SOURCE 0xB78 588*4882a593Smuzhiyun #define WM5100_GPIO_CTRL_1 0xC00 589*4882a593Smuzhiyun #define WM5100_GPIO_CTRL_2 0xC01 590*4882a593Smuzhiyun #define WM5100_GPIO_CTRL_3 0xC02 591*4882a593Smuzhiyun #define WM5100_GPIO_CTRL_4 0xC03 592*4882a593Smuzhiyun #define WM5100_GPIO_CTRL_5 0xC04 593*4882a593Smuzhiyun #define WM5100_GPIO_CTRL_6 0xC05 594*4882a593Smuzhiyun #define WM5100_MISC_PAD_CTRL_1 0xC23 595*4882a593Smuzhiyun #define WM5100_MISC_PAD_CTRL_2 0xC24 596*4882a593Smuzhiyun #define WM5100_MISC_PAD_CTRL_3 0xC25 597*4882a593Smuzhiyun #define WM5100_MISC_PAD_CTRL_4 0xC26 598*4882a593Smuzhiyun #define WM5100_MISC_PAD_CTRL_5 0xC27 599*4882a593Smuzhiyun #define WM5100_MISC_GPIO_1 0xC28 600*4882a593Smuzhiyun #define WM5100_INTERRUPT_STATUS_1 0xD00 601*4882a593Smuzhiyun #define WM5100_INTERRUPT_STATUS_2 0xD01 602*4882a593Smuzhiyun #define WM5100_INTERRUPT_STATUS_3 0xD02 603*4882a593Smuzhiyun #define WM5100_INTERRUPT_STATUS_4 0xD03 604*4882a593Smuzhiyun #define WM5100_INTERRUPT_RAW_STATUS_2 0xD04 605*4882a593Smuzhiyun #define WM5100_INTERRUPT_RAW_STATUS_3 0xD05 606*4882a593Smuzhiyun #define WM5100_INTERRUPT_RAW_STATUS_4 0xD06 607*4882a593Smuzhiyun #define WM5100_INTERRUPT_STATUS_1_MASK 0xD07 608*4882a593Smuzhiyun #define WM5100_INTERRUPT_STATUS_2_MASK 0xD08 609*4882a593Smuzhiyun #define WM5100_INTERRUPT_STATUS_3_MASK 0xD09 610*4882a593Smuzhiyun #define WM5100_INTERRUPT_STATUS_4_MASK 0xD0A 611*4882a593Smuzhiyun #define WM5100_INTERRUPT_CONTROL 0xD1F 612*4882a593Smuzhiyun #define WM5100_IRQ_DEBOUNCE_1 0xD20 613*4882a593Smuzhiyun #define WM5100_IRQ_DEBOUNCE_2 0xD21 614*4882a593Smuzhiyun #define WM5100_FX_CTRL 0xE00 615*4882a593Smuzhiyun #define WM5100_EQ1_1 0xE10 616*4882a593Smuzhiyun #define WM5100_EQ1_2 0xE11 617*4882a593Smuzhiyun #define WM5100_EQ1_3 0xE12 618*4882a593Smuzhiyun #define WM5100_EQ1_4 0xE13 619*4882a593Smuzhiyun #define WM5100_EQ1_5 0xE14 620*4882a593Smuzhiyun #define WM5100_EQ1_6 0xE15 621*4882a593Smuzhiyun #define WM5100_EQ1_7 0xE16 622*4882a593Smuzhiyun #define WM5100_EQ1_8 0xE17 623*4882a593Smuzhiyun #define WM5100_EQ1_9 0xE18 624*4882a593Smuzhiyun #define WM5100_EQ1_10 0xE19 625*4882a593Smuzhiyun #define WM5100_EQ1_11 0xE1A 626*4882a593Smuzhiyun #define WM5100_EQ1_12 0xE1B 627*4882a593Smuzhiyun #define WM5100_EQ1_13 0xE1C 628*4882a593Smuzhiyun #define WM5100_EQ1_14 0xE1D 629*4882a593Smuzhiyun #define WM5100_EQ1_15 0xE1E 630*4882a593Smuzhiyun #define WM5100_EQ1_16 0xE1F 631*4882a593Smuzhiyun #define WM5100_EQ1_17 0xE20 632*4882a593Smuzhiyun #define WM5100_EQ1_18 0xE21 633*4882a593Smuzhiyun #define WM5100_EQ1_19 0xE22 634*4882a593Smuzhiyun #define WM5100_EQ1_20 0xE23 635*4882a593Smuzhiyun #define WM5100_EQ2_1 0xE26 636*4882a593Smuzhiyun #define WM5100_EQ2_2 0xE27 637*4882a593Smuzhiyun #define WM5100_EQ2_3 0xE28 638*4882a593Smuzhiyun #define WM5100_EQ2_4 0xE29 639*4882a593Smuzhiyun #define WM5100_EQ2_5 0xE2A 640*4882a593Smuzhiyun #define WM5100_EQ2_6 0xE2B 641*4882a593Smuzhiyun #define WM5100_EQ2_7 0xE2C 642*4882a593Smuzhiyun #define WM5100_EQ2_8 0xE2D 643*4882a593Smuzhiyun #define WM5100_EQ2_9 0xE2E 644*4882a593Smuzhiyun #define WM5100_EQ2_10 0xE2F 645*4882a593Smuzhiyun #define WM5100_EQ2_11 0xE30 646*4882a593Smuzhiyun #define WM5100_EQ2_12 0xE31 647*4882a593Smuzhiyun #define WM5100_EQ2_13 0xE32 648*4882a593Smuzhiyun #define WM5100_EQ2_14 0xE33 649*4882a593Smuzhiyun #define WM5100_EQ2_15 0xE34 650*4882a593Smuzhiyun #define WM5100_EQ2_16 0xE35 651*4882a593Smuzhiyun #define WM5100_EQ2_17 0xE36 652*4882a593Smuzhiyun #define WM5100_EQ2_18 0xE37 653*4882a593Smuzhiyun #define WM5100_EQ2_19 0xE38 654*4882a593Smuzhiyun #define WM5100_EQ2_20 0xE39 655*4882a593Smuzhiyun #define WM5100_EQ3_1 0xE3C 656*4882a593Smuzhiyun #define WM5100_EQ3_2 0xE3D 657*4882a593Smuzhiyun #define WM5100_EQ3_3 0xE3E 658*4882a593Smuzhiyun #define WM5100_EQ3_4 0xE3F 659*4882a593Smuzhiyun #define WM5100_EQ3_5 0xE40 660*4882a593Smuzhiyun #define WM5100_EQ3_6 0xE41 661*4882a593Smuzhiyun #define WM5100_EQ3_7 0xE42 662*4882a593Smuzhiyun #define WM5100_EQ3_8 0xE43 663*4882a593Smuzhiyun #define WM5100_EQ3_9 0xE44 664*4882a593Smuzhiyun #define WM5100_EQ3_10 0xE45 665*4882a593Smuzhiyun #define WM5100_EQ3_11 0xE46 666*4882a593Smuzhiyun #define WM5100_EQ3_12 0xE47 667*4882a593Smuzhiyun #define WM5100_EQ3_13 0xE48 668*4882a593Smuzhiyun #define WM5100_EQ3_14 0xE49 669*4882a593Smuzhiyun #define WM5100_EQ3_15 0xE4A 670*4882a593Smuzhiyun #define WM5100_EQ3_16 0xE4B 671*4882a593Smuzhiyun #define WM5100_EQ3_17 0xE4C 672*4882a593Smuzhiyun #define WM5100_EQ3_18 0xE4D 673*4882a593Smuzhiyun #define WM5100_EQ3_19 0xE4E 674*4882a593Smuzhiyun #define WM5100_EQ3_20 0xE4F 675*4882a593Smuzhiyun #define WM5100_EQ4_1 0xE52 676*4882a593Smuzhiyun #define WM5100_EQ4_2 0xE53 677*4882a593Smuzhiyun #define WM5100_EQ4_3 0xE54 678*4882a593Smuzhiyun #define WM5100_EQ4_4 0xE55 679*4882a593Smuzhiyun #define WM5100_EQ4_5 0xE56 680*4882a593Smuzhiyun #define WM5100_EQ4_6 0xE57 681*4882a593Smuzhiyun #define WM5100_EQ4_7 0xE58 682*4882a593Smuzhiyun #define WM5100_EQ4_8 0xE59 683*4882a593Smuzhiyun #define WM5100_EQ4_9 0xE5A 684*4882a593Smuzhiyun #define WM5100_EQ4_10 0xE5B 685*4882a593Smuzhiyun #define WM5100_EQ4_11 0xE5C 686*4882a593Smuzhiyun #define WM5100_EQ4_12 0xE5D 687*4882a593Smuzhiyun #define WM5100_EQ4_13 0xE5E 688*4882a593Smuzhiyun #define WM5100_EQ4_14 0xE5F 689*4882a593Smuzhiyun #define WM5100_EQ4_15 0xE60 690*4882a593Smuzhiyun #define WM5100_EQ4_16 0xE61 691*4882a593Smuzhiyun #define WM5100_EQ4_17 0xE62 692*4882a593Smuzhiyun #define WM5100_EQ4_18 0xE63 693*4882a593Smuzhiyun #define WM5100_EQ4_19 0xE64 694*4882a593Smuzhiyun #define WM5100_EQ4_20 0xE65 695*4882a593Smuzhiyun #define WM5100_DRC1_CTRL1 0xE80 696*4882a593Smuzhiyun #define WM5100_DRC1_CTRL2 0xE81 697*4882a593Smuzhiyun #define WM5100_DRC1_CTRL3 0xE82 698*4882a593Smuzhiyun #define WM5100_DRC1_CTRL4 0xE83 699*4882a593Smuzhiyun #define WM5100_DRC1_CTRL5 0xE84 700*4882a593Smuzhiyun #define WM5100_HPLPF1_1 0xEC0 701*4882a593Smuzhiyun #define WM5100_HPLPF1_2 0xEC1 702*4882a593Smuzhiyun #define WM5100_HPLPF2_1 0xEC4 703*4882a593Smuzhiyun #define WM5100_HPLPF2_2 0xEC5 704*4882a593Smuzhiyun #define WM5100_HPLPF3_1 0xEC8 705*4882a593Smuzhiyun #define WM5100_HPLPF3_2 0xEC9 706*4882a593Smuzhiyun #define WM5100_HPLPF4_1 0xECC 707*4882a593Smuzhiyun #define WM5100_HPLPF4_2 0xECD 708*4882a593Smuzhiyun #define WM5100_DSP1_CONTROL_1 0xF00 709*4882a593Smuzhiyun #define WM5100_DSP1_CONTROL_2 0xF02 710*4882a593Smuzhiyun #define WM5100_DSP1_CONTROL_3 0xF03 711*4882a593Smuzhiyun #define WM5100_DSP1_CONTROL_4 0xF04 712*4882a593Smuzhiyun #define WM5100_DSP1_CONTROL_5 0xF06 713*4882a593Smuzhiyun #define WM5100_DSP1_CONTROL_6 0xF07 714*4882a593Smuzhiyun #define WM5100_DSP1_CONTROL_7 0xF08 715*4882a593Smuzhiyun #define WM5100_DSP1_CONTROL_8 0xF09 716*4882a593Smuzhiyun #define WM5100_DSP1_CONTROL_9 0xF0A 717*4882a593Smuzhiyun #define WM5100_DSP1_CONTROL_10 0xF0B 718*4882a593Smuzhiyun #define WM5100_DSP1_CONTROL_11 0xF0C 719*4882a593Smuzhiyun #define WM5100_DSP1_CONTROL_12 0xF0D 720*4882a593Smuzhiyun #define WM5100_DSP1_CONTROL_13 0xF0F 721*4882a593Smuzhiyun #define WM5100_DSP1_CONTROL_14 0xF10 722*4882a593Smuzhiyun #define WM5100_DSP1_CONTROL_15 0xF11 723*4882a593Smuzhiyun #define WM5100_DSP1_CONTROL_16 0xF12 724*4882a593Smuzhiyun #define WM5100_DSP1_CONTROL_17 0xF13 725*4882a593Smuzhiyun #define WM5100_DSP1_CONTROL_18 0xF14 726*4882a593Smuzhiyun #define WM5100_DSP1_CONTROL_19 0xF16 727*4882a593Smuzhiyun #define WM5100_DSP1_CONTROL_20 0xF17 728*4882a593Smuzhiyun #define WM5100_DSP1_CONTROL_21 0xF18 729*4882a593Smuzhiyun #define WM5100_DSP1_CONTROL_22 0xF1A 730*4882a593Smuzhiyun #define WM5100_DSP1_CONTROL_23 0xF1B 731*4882a593Smuzhiyun #define WM5100_DSP1_CONTROL_24 0xF1C 732*4882a593Smuzhiyun #define WM5100_DSP1_CONTROL_25 0xF1E 733*4882a593Smuzhiyun #define WM5100_DSP1_CONTROL_26 0xF20 734*4882a593Smuzhiyun #define WM5100_DSP1_CONTROL_27 0xF21 735*4882a593Smuzhiyun #define WM5100_DSP1_CONTROL_28 0xF22 736*4882a593Smuzhiyun #define WM5100_DSP1_CONTROL_29 0xF23 737*4882a593Smuzhiyun #define WM5100_DSP1_CONTROL_30 0xF24 738*4882a593Smuzhiyun #define WM5100_DSP2_CONTROL_1 0x1000 739*4882a593Smuzhiyun #define WM5100_DSP2_CONTROL_2 0x1002 740*4882a593Smuzhiyun #define WM5100_DSP2_CONTROL_3 0x1003 741*4882a593Smuzhiyun #define WM5100_DSP2_CONTROL_4 0x1004 742*4882a593Smuzhiyun #define WM5100_DSP2_CONTROL_5 0x1006 743*4882a593Smuzhiyun #define WM5100_DSP2_CONTROL_6 0x1007 744*4882a593Smuzhiyun #define WM5100_DSP2_CONTROL_7 0x1008 745*4882a593Smuzhiyun #define WM5100_DSP2_CONTROL_8 0x1009 746*4882a593Smuzhiyun #define WM5100_DSP2_CONTROL_9 0x100A 747*4882a593Smuzhiyun #define WM5100_DSP2_CONTROL_10 0x100B 748*4882a593Smuzhiyun #define WM5100_DSP2_CONTROL_11 0x100C 749*4882a593Smuzhiyun #define WM5100_DSP2_CONTROL_12 0x100D 750*4882a593Smuzhiyun #define WM5100_DSP2_CONTROL_13 0x100F 751*4882a593Smuzhiyun #define WM5100_DSP2_CONTROL_14 0x1010 752*4882a593Smuzhiyun #define WM5100_DSP2_CONTROL_15 0x1011 753*4882a593Smuzhiyun #define WM5100_DSP2_CONTROL_16 0x1012 754*4882a593Smuzhiyun #define WM5100_DSP2_CONTROL_17 0x1013 755*4882a593Smuzhiyun #define WM5100_DSP2_CONTROL_18 0x1014 756*4882a593Smuzhiyun #define WM5100_DSP2_CONTROL_19 0x1016 757*4882a593Smuzhiyun #define WM5100_DSP2_CONTROL_20 0x1017 758*4882a593Smuzhiyun #define WM5100_DSP2_CONTROL_21 0x1018 759*4882a593Smuzhiyun #define WM5100_DSP2_CONTROL_22 0x101A 760*4882a593Smuzhiyun #define WM5100_DSP2_CONTROL_23 0x101B 761*4882a593Smuzhiyun #define WM5100_DSP2_CONTROL_24 0x101C 762*4882a593Smuzhiyun #define WM5100_DSP2_CONTROL_25 0x101E 763*4882a593Smuzhiyun #define WM5100_DSP2_CONTROL_26 0x1020 764*4882a593Smuzhiyun #define WM5100_DSP2_CONTROL_27 0x1021 765*4882a593Smuzhiyun #define WM5100_DSP2_CONTROL_28 0x1022 766*4882a593Smuzhiyun #define WM5100_DSP2_CONTROL_29 0x1023 767*4882a593Smuzhiyun #define WM5100_DSP2_CONTROL_30 0x1024 768*4882a593Smuzhiyun #define WM5100_DSP3_CONTROL_1 0x1100 769*4882a593Smuzhiyun #define WM5100_DSP3_CONTROL_2 0x1102 770*4882a593Smuzhiyun #define WM5100_DSP3_CONTROL_3 0x1103 771*4882a593Smuzhiyun #define WM5100_DSP3_CONTROL_4 0x1104 772*4882a593Smuzhiyun #define WM5100_DSP3_CONTROL_5 0x1106 773*4882a593Smuzhiyun #define WM5100_DSP3_CONTROL_6 0x1107 774*4882a593Smuzhiyun #define WM5100_DSP3_CONTROL_7 0x1108 775*4882a593Smuzhiyun #define WM5100_DSP3_CONTROL_8 0x1109 776*4882a593Smuzhiyun #define WM5100_DSP3_CONTROL_9 0x110A 777*4882a593Smuzhiyun #define WM5100_DSP3_CONTROL_10 0x110B 778*4882a593Smuzhiyun #define WM5100_DSP3_CONTROL_11 0x110C 779*4882a593Smuzhiyun #define WM5100_DSP3_CONTROL_12 0x110D 780*4882a593Smuzhiyun #define WM5100_DSP3_CONTROL_13 0x110F 781*4882a593Smuzhiyun #define WM5100_DSP3_CONTROL_14 0x1110 782*4882a593Smuzhiyun #define WM5100_DSP3_CONTROL_15 0x1111 783*4882a593Smuzhiyun #define WM5100_DSP3_CONTROL_16 0x1112 784*4882a593Smuzhiyun #define WM5100_DSP3_CONTROL_17 0x1113 785*4882a593Smuzhiyun #define WM5100_DSP3_CONTROL_18 0x1114 786*4882a593Smuzhiyun #define WM5100_DSP3_CONTROL_19 0x1116 787*4882a593Smuzhiyun #define WM5100_DSP3_CONTROL_20 0x1117 788*4882a593Smuzhiyun #define WM5100_DSP3_CONTROL_21 0x1118 789*4882a593Smuzhiyun #define WM5100_DSP3_CONTROL_22 0x111A 790*4882a593Smuzhiyun #define WM5100_DSP3_CONTROL_23 0x111B 791*4882a593Smuzhiyun #define WM5100_DSP3_CONTROL_24 0x111C 792*4882a593Smuzhiyun #define WM5100_DSP3_CONTROL_25 0x111E 793*4882a593Smuzhiyun #define WM5100_DSP3_CONTROL_26 0x1120 794*4882a593Smuzhiyun #define WM5100_DSP3_CONTROL_27 0x1121 795*4882a593Smuzhiyun #define WM5100_DSP3_CONTROL_28 0x1122 796*4882a593Smuzhiyun #define WM5100_DSP3_CONTROL_29 0x1123 797*4882a593Smuzhiyun #define WM5100_DSP3_CONTROL_30 0x1124 798*4882a593Smuzhiyun #define WM5100_DSP1_DM_0 0x4000 799*4882a593Smuzhiyun #define WM5100_DSP1_DM_1 0x4001 800*4882a593Smuzhiyun #define WM5100_DSP1_DM_2 0x4002 801*4882a593Smuzhiyun #define WM5100_DSP1_DM_3 0x4003 802*4882a593Smuzhiyun #define WM5100_DSP1_DM_508 0x41FC 803*4882a593Smuzhiyun #define WM5100_DSP1_DM_509 0x41FD 804*4882a593Smuzhiyun #define WM5100_DSP1_DM_510 0x41FE 805*4882a593Smuzhiyun #define WM5100_DSP1_DM_511 0x41FF 806*4882a593Smuzhiyun #define WM5100_DSP1_PM_0 0x4800 807*4882a593Smuzhiyun #define WM5100_DSP1_PM_1 0x4801 808*4882a593Smuzhiyun #define WM5100_DSP1_PM_2 0x4802 809*4882a593Smuzhiyun #define WM5100_DSP1_PM_3 0x4803 810*4882a593Smuzhiyun #define WM5100_DSP1_PM_4 0x4804 811*4882a593Smuzhiyun #define WM5100_DSP1_PM_5 0x4805 812*4882a593Smuzhiyun #define WM5100_DSP1_PM_1530 0x4DFA 813*4882a593Smuzhiyun #define WM5100_DSP1_PM_1531 0x4DFB 814*4882a593Smuzhiyun #define WM5100_DSP1_PM_1532 0x4DFC 815*4882a593Smuzhiyun #define WM5100_DSP1_PM_1533 0x4DFD 816*4882a593Smuzhiyun #define WM5100_DSP1_PM_1534 0x4DFE 817*4882a593Smuzhiyun #define WM5100_DSP1_PM_1535 0x4DFF 818*4882a593Smuzhiyun #define WM5100_DSP1_ZM_0 0x5000 819*4882a593Smuzhiyun #define WM5100_DSP1_ZM_1 0x5001 820*4882a593Smuzhiyun #define WM5100_DSP1_ZM_2 0x5002 821*4882a593Smuzhiyun #define WM5100_DSP1_ZM_3 0x5003 822*4882a593Smuzhiyun #define WM5100_DSP1_ZM_2044 0x57FC 823*4882a593Smuzhiyun #define WM5100_DSP1_ZM_2045 0x57FD 824*4882a593Smuzhiyun #define WM5100_DSP1_ZM_2046 0x57FE 825*4882a593Smuzhiyun #define WM5100_DSP1_ZM_2047 0x57FF 826*4882a593Smuzhiyun #define WM5100_DSP2_DM_0 0x6000 827*4882a593Smuzhiyun #define WM5100_DSP2_DM_1 0x6001 828*4882a593Smuzhiyun #define WM5100_DSP2_DM_2 0x6002 829*4882a593Smuzhiyun #define WM5100_DSP2_DM_3 0x6003 830*4882a593Smuzhiyun #define WM5100_DSP2_DM_508 0x61FC 831*4882a593Smuzhiyun #define WM5100_DSP2_DM_509 0x61FD 832*4882a593Smuzhiyun #define WM5100_DSP2_DM_510 0x61FE 833*4882a593Smuzhiyun #define WM5100_DSP2_DM_511 0x61FF 834*4882a593Smuzhiyun #define WM5100_DSP2_PM_0 0x6800 835*4882a593Smuzhiyun #define WM5100_DSP2_PM_1 0x6801 836*4882a593Smuzhiyun #define WM5100_DSP2_PM_2 0x6802 837*4882a593Smuzhiyun #define WM5100_DSP2_PM_3 0x6803 838*4882a593Smuzhiyun #define WM5100_DSP2_PM_4 0x6804 839*4882a593Smuzhiyun #define WM5100_DSP2_PM_5 0x6805 840*4882a593Smuzhiyun #define WM5100_DSP2_PM_1530 0x6DFA 841*4882a593Smuzhiyun #define WM5100_DSP2_PM_1531 0x6DFB 842*4882a593Smuzhiyun #define WM5100_DSP2_PM_1532 0x6DFC 843*4882a593Smuzhiyun #define WM5100_DSP2_PM_1533 0x6DFD 844*4882a593Smuzhiyun #define WM5100_DSP2_PM_1534 0x6DFE 845*4882a593Smuzhiyun #define WM5100_DSP2_PM_1535 0x6DFF 846*4882a593Smuzhiyun #define WM5100_DSP2_ZM_0 0x7000 847*4882a593Smuzhiyun #define WM5100_DSP2_ZM_1 0x7001 848*4882a593Smuzhiyun #define WM5100_DSP2_ZM_2 0x7002 849*4882a593Smuzhiyun #define WM5100_DSP2_ZM_3 0x7003 850*4882a593Smuzhiyun #define WM5100_DSP2_ZM_2044 0x77FC 851*4882a593Smuzhiyun #define WM5100_DSP2_ZM_2045 0x77FD 852*4882a593Smuzhiyun #define WM5100_DSP2_ZM_2046 0x77FE 853*4882a593Smuzhiyun #define WM5100_DSP2_ZM_2047 0x77FF 854*4882a593Smuzhiyun #define WM5100_DSP3_DM_0 0x8000 855*4882a593Smuzhiyun #define WM5100_DSP3_DM_1 0x8001 856*4882a593Smuzhiyun #define WM5100_DSP3_DM_2 0x8002 857*4882a593Smuzhiyun #define WM5100_DSP3_DM_3 0x8003 858*4882a593Smuzhiyun #define WM5100_DSP3_DM_508 0x81FC 859*4882a593Smuzhiyun #define WM5100_DSP3_DM_509 0x81FD 860*4882a593Smuzhiyun #define WM5100_DSP3_DM_510 0x81FE 861*4882a593Smuzhiyun #define WM5100_DSP3_DM_511 0x81FF 862*4882a593Smuzhiyun #define WM5100_DSP3_PM_0 0x8800 863*4882a593Smuzhiyun #define WM5100_DSP3_PM_1 0x8801 864*4882a593Smuzhiyun #define WM5100_DSP3_PM_2 0x8802 865*4882a593Smuzhiyun #define WM5100_DSP3_PM_3 0x8803 866*4882a593Smuzhiyun #define WM5100_DSP3_PM_4 0x8804 867*4882a593Smuzhiyun #define WM5100_DSP3_PM_5 0x8805 868*4882a593Smuzhiyun #define WM5100_DSP3_PM_1530 0x8DFA 869*4882a593Smuzhiyun #define WM5100_DSP3_PM_1531 0x8DFB 870*4882a593Smuzhiyun #define WM5100_DSP3_PM_1532 0x8DFC 871*4882a593Smuzhiyun #define WM5100_DSP3_PM_1533 0x8DFD 872*4882a593Smuzhiyun #define WM5100_DSP3_PM_1534 0x8DFE 873*4882a593Smuzhiyun #define WM5100_DSP3_PM_1535 0x8DFF 874*4882a593Smuzhiyun #define WM5100_DSP3_ZM_0 0x9000 875*4882a593Smuzhiyun #define WM5100_DSP3_ZM_1 0x9001 876*4882a593Smuzhiyun #define WM5100_DSP3_ZM_2 0x9002 877*4882a593Smuzhiyun #define WM5100_DSP3_ZM_3 0x9003 878*4882a593Smuzhiyun #define WM5100_DSP3_ZM_2044 0x97FC 879*4882a593Smuzhiyun #define WM5100_DSP3_ZM_2045 0x97FD 880*4882a593Smuzhiyun #define WM5100_DSP3_ZM_2046 0x97FE 881*4882a593Smuzhiyun #define WM5100_DSP3_ZM_2047 0x97FF 882*4882a593Smuzhiyun 883*4882a593Smuzhiyun #define WM5100_REGISTER_COUNT 1435 884*4882a593Smuzhiyun #define WM5100_MAX_REGISTER 0x97FF 885*4882a593Smuzhiyun 886*4882a593Smuzhiyun /* 887*4882a593Smuzhiyun * Field Definitions. 888*4882a593Smuzhiyun */ 889*4882a593Smuzhiyun 890*4882a593Smuzhiyun /* 891*4882a593Smuzhiyun * R0 (0x00) - software reset 892*4882a593Smuzhiyun */ 893*4882a593Smuzhiyun #define WM5100_SW_RST_DEV_ID1_MASK 0xFFFF /* SW_RST_DEV_ID1 - [15:0] */ 894*4882a593Smuzhiyun #define WM5100_SW_RST_DEV_ID1_SHIFT 0 /* SW_RST_DEV_ID1 - [15:0] */ 895*4882a593Smuzhiyun #define WM5100_SW_RST_DEV_ID1_WIDTH 16 /* SW_RST_DEV_ID1 - [15:0] */ 896*4882a593Smuzhiyun 897*4882a593Smuzhiyun /* 898*4882a593Smuzhiyun * R1 (0x01) - Device Revision 899*4882a593Smuzhiyun */ 900*4882a593Smuzhiyun #define WM5100_DEVICE_REVISION_MASK 0x000F /* DEVICE_REVISION - [3:0] */ 901*4882a593Smuzhiyun #define WM5100_DEVICE_REVISION_SHIFT 0 /* DEVICE_REVISION - [3:0] */ 902*4882a593Smuzhiyun #define WM5100_DEVICE_REVISION_WIDTH 4 /* DEVICE_REVISION - [3:0] */ 903*4882a593Smuzhiyun 904*4882a593Smuzhiyun /* 905*4882a593Smuzhiyun * R16 (0x10) - Ctrl IF 1 906*4882a593Smuzhiyun */ 907*4882a593Smuzhiyun #define WM5100_AUTO_INC 0x0001 /* AUTO_INC */ 908*4882a593Smuzhiyun #define WM5100_AUTO_INC_MASK 0x0001 /* AUTO_INC */ 909*4882a593Smuzhiyun #define WM5100_AUTO_INC_SHIFT 0 /* AUTO_INC */ 910*4882a593Smuzhiyun #define WM5100_AUTO_INC_WIDTH 1 /* AUTO_INC */ 911*4882a593Smuzhiyun 912*4882a593Smuzhiyun /* 913*4882a593Smuzhiyun * R32 (0x20) - Tone Generator 1 914*4882a593Smuzhiyun */ 915*4882a593Smuzhiyun #define WM5100_TONE_RATE_MASK 0x3000 /* TONE_RATE - [13:12] */ 916*4882a593Smuzhiyun #define WM5100_TONE_RATE_SHIFT 12 /* TONE_RATE - [13:12] */ 917*4882a593Smuzhiyun #define WM5100_TONE_RATE_WIDTH 2 /* TONE_RATE - [13:12] */ 918*4882a593Smuzhiyun #define WM5100_TONE_OFFSET_MASK 0x0300 /* TONE_OFFSET - [9:8] */ 919*4882a593Smuzhiyun #define WM5100_TONE_OFFSET_SHIFT 8 /* TONE_OFFSET - [9:8] */ 920*4882a593Smuzhiyun #define WM5100_TONE_OFFSET_WIDTH 2 /* TONE_OFFSET - [9:8] */ 921*4882a593Smuzhiyun #define WM5100_TONE2_ENA 0x0002 /* TONE2_ENA */ 922*4882a593Smuzhiyun #define WM5100_TONE2_ENA_MASK 0x0002 /* TONE2_ENA */ 923*4882a593Smuzhiyun #define WM5100_TONE2_ENA_SHIFT 1 /* TONE2_ENA */ 924*4882a593Smuzhiyun #define WM5100_TONE2_ENA_WIDTH 1 /* TONE2_ENA */ 925*4882a593Smuzhiyun #define WM5100_TONE1_ENA 0x0001 /* TONE1_ENA */ 926*4882a593Smuzhiyun #define WM5100_TONE1_ENA_MASK 0x0001 /* TONE1_ENA */ 927*4882a593Smuzhiyun #define WM5100_TONE1_ENA_SHIFT 0 /* TONE1_ENA */ 928*4882a593Smuzhiyun #define WM5100_TONE1_ENA_WIDTH 1 /* TONE1_ENA */ 929*4882a593Smuzhiyun 930*4882a593Smuzhiyun /* 931*4882a593Smuzhiyun * R48 (0x30) - PWM Drive 1 932*4882a593Smuzhiyun */ 933*4882a593Smuzhiyun #define WM5100_PWM_RATE_MASK 0x3000 /* PWM_RATE - [13:12] */ 934*4882a593Smuzhiyun #define WM5100_PWM_RATE_SHIFT 12 /* PWM_RATE - [13:12] */ 935*4882a593Smuzhiyun #define WM5100_PWM_RATE_WIDTH 2 /* PWM_RATE - [13:12] */ 936*4882a593Smuzhiyun #define WM5100_PWM_CLK_SEL_MASK 0x0300 /* PWM_CLK_SEL - [9:8] */ 937*4882a593Smuzhiyun #define WM5100_PWM_CLK_SEL_SHIFT 8 /* PWM_CLK_SEL - [9:8] */ 938*4882a593Smuzhiyun #define WM5100_PWM_CLK_SEL_WIDTH 2 /* PWM_CLK_SEL - [9:8] */ 939*4882a593Smuzhiyun #define WM5100_PWM2_OVD 0x0020 /* PWM2_OVD */ 940*4882a593Smuzhiyun #define WM5100_PWM2_OVD_MASK 0x0020 /* PWM2_OVD */ 941*4882a593Smuzhiyun #define WM5100_PWM2_OVD_SHIFT 5 /* PWM2_OVD */ 942*4882a593Smuzhiyun #define WM5100_PWM2_OVD_WIDTH 1 /* PWM2_OVD */ 943*4882a593Smuzhiyun #define WM5100_PWM1_OVD 0x0010 /* PWM1_OVD */ 944*4882a593Smuzhiyun #define WM5100_PWM1_OVD_MASK 0x0010 /* PWM1_OVD */ 945*4882a593Smuzhiyun #define WM5100_PWM1_OVD_SHIFT 4 /* PWM1_OVD */ 946*4882a593Smuzhiyun #define WM5100_PWM1_OVD_WIDTH 1 /* PWM1_OVD */ 947*4882a593Smuzhiyun #define WM5100_PWM2_ENA 0x0002 /* PWM2_ENA */ 948*4882a593Smuzhiyun #define WM5100_PWM2_ENA_MASK 0x0002 /* PWM2_ENA */ 949*4882a593Smuzhiyun #define WM5100_PWM2_ENA_SHIFT 1 /* PWM2_ENA */ 950*4882a593Smuzhiyun #define WM5100_PWM2_ENA_WIDTH 1 /* PWM2_ENA */ 951*4882a593Smuzhiyun #define WM5100_PWM1_ENA 0x0001 /* PWM1_ENA */ 952*4882a593Smuzhiyun #define WM5100_PWM1_ENA_MASK 0x0001 /* PWM1_ENA */ 953*4882a593Smuzhiyun #define WM5100_PWM1_ENA_SHIFT 0 /* PWM1_ENA */ 954*4882a593Smuzhiyun #define WM5100_PWM1_ENA_WIDTH 1 /* PWM1_ENA */ 955*4882a593Smuzhiyun 956*4882a593Smuzhiyun /* 957*4882a593Smuzhiyun * R49 (0x31) - PWM Drive 2 958*4882a593Smuzhiyun */ 959*4882a593Smuzhiyun #define WM5100_PWM1_LVL_MASK 0x03FF /* PWM1_LVL - [9:0] */ 960*4882a593Smuzhiyun #define WM5100_PWM1_LVL_SHIFT 0 /* PWM1_LVL - [9:0] */ 961*4882a593Smuzhiyun #define WM5100_PWM1_LVL_WIDTH 10 /* PWM1_LVL - [9:0] */ 962*4882a593Smuzhiyun 963*4882a593Smuzhiyun /* 964*4882a593Smuzhiyun * R50 (0x32) - PWM Drive 3 965*4882a593Smuzhiyun */ 966*4882a593Smuzhiyun #define WM5100_PWM2_LVL_MASK 0x03FF /* PWM2_LVL - [9:0] */ 967*4882a593Smuzhiyun #define WM5100_PWM2_LVL_SHIFT 0 /* PWM2_LVL - [9:0] */ 968*4882a593Smuzhiyun #define WM5100_PWM2_LVL_WIDTH 10 /* PWM2_LVL - [9:0] */ 969*4882a593Smuzhiyun 970*4882a593Smuzhiyun /* 971*4882a593Smuzhiyun * R256 (0x100) - Clocking 1 972*4882a593Smuzhiyun */ 973*4882a593Smuzhiyun #define WM5100_CLK_32K_SRC_MASK 0x000F /* CLK_32K_SRC - [3:0] */ 974*4882a593Smuzhiyun #define WM5100_CLK_32K_SRC_SHIFT 0 /* CLK_32K_SRC - [3:0] */ 975*4882a593Smuzhiyun #define WM5100_CLK_32K_SRC_WIDTH 4 /* CLK_32K_SRC - [3:0] */ 976*4882a593Smuzhiyun 977*4882a593Smuzhiyun /* 978*4882a593Smuzhiyun * R257 (0x101) - Clocking 3 979*4882a593Smuzhiyun */ 980*4882a593Smuzhiyun #define WM5100_SYSCLK_FREQ_MASK 0x0700 /* SYSCLK_FREQ - [10:8] */ 981*4882a593Smuzhiyun #define WM5100_SYSCLK_FREQ_SHIFT 8 /* SYSCLK_FREQ - [10:8] */ 982*4882a593Smuzhiyun #define WM5100_SYSCLK_FREQ_WIDTH 3 /* SYSCLK_FREQ - [10:8] */ 983*4882a593Smuzhiyun #define WM5100_SYSCLK_ENA 0x0040 /* SYSCLK_ENA */ 984*4882a593Smuzhiyun #define WM5100_SYSCLK_ENA_MASK 0x0040 /* SYSCLK_ENA */ 985*4882a593Smuzhiyun #define WM5100_SYSCLK_ENA_SHIFT 6 /* SYSCLK_ENA */ 986*4882a593Smuzhiyun #define WM5100_SYSCLK_ENA_WIDTH 1 /* SYSCLK_ENA */ 987*4882a593Smuzhiyun #define WM5100_SYSCLK_SRC_MASK 0x000F /* SYSCLK_SRC - [3:0] */ 988*4882a593Smuzhiyun #define WM5100_SYSCLK_SRC_SHIFT 0 /* SYSCLK_SRC - [3:0] */ 989*4882a593Smuzhiyun #define WM5100_SYSCLK_SRC_WIDTH 4 /* SYSCLK_SRC - [3:0] */ 990*4882a593Smuzhiyun 991*4882a593Smuzhiyun /* 992*4882a593Smuzhiyun * R258 (0x102) - Clocking 4 993*4882a593Smuzhiyun */ 994*4882a593Smuzhiyun #define WM5100_SAMPLE_RATE_1_MASK 0x001F /* SAMPLE_RATE_1 - [4:0] */ 995*4882a593Smuzhiyun #define WM5100_SAMPLE_RATE_1_SHIFT 0 /* SAMPLE_RATE_1 - [4:0] */ 996*4882a593Smuzhiyun #define WM5100_SAMPLE_RATE_1_WIDTH 5 /* SAMPLE_RATE_1 - [4:0] */ 997*4882a593Smuzhiyun 998*4882a593Smuzhiyun /* 999*4882a593Smuzhiyun * R259 (0x103) - Clocking 5 1000*4882a593Smuzhiyun */ 1001*4882a593Smuzhiyun #define WM5100_SAMPLE_RATE_2_MASK 0x001F /* SAMPLE_RATE_2 - [4:0] */ 1002*4882a593Smuzhiyun #define WM5100_SAMPLE_RATE_2_SHIFT 0 /* SAMPLE_RATE_2 - [4:0] */ 1003*4882a593Smuzhiyun #define WM5100_SAMPLE_RATE_2_WIDTH 5 /* SAMPLE_RATE_2 - [4:0] */ 1004*4882a593Smuzhiyun 1005*4882a593Smuzhiyun /* 1006*4882a593Smuzhiyun * R260 (0x104) - Clocking 6 1007*4882a593Smuzhiyun */ 1008*4882a593Smuzhiyun #define WM5100_SAMPLE_RATE_3_MASK 0x001F /* SAMPLE_RATE_3 - [4:0] */ 1009*4882a593Smuzhiyun #define WM5100_SAMPLE_RATE_3_SHIFT 0 /* SAMPLE_RATE_3 - [4:0] */ 1010*4882a593Smuzhiyun #define WM5100_SAMPLE_RATE_3_WIDTH 5 /* SAMPLE_RATE_3 - [4:0] */ 1011*4882a593Smuzhiyun 1012*4882a593Smuzhiyun /* 1013*4882a593Smuzhiyun * R263 (0x107) - Clocking 7 1014*4882a593Smuzhiyun */ 1015*4882a593Smuzhiyun #define WM5100_ASYNC_CLK_FREQ_MASK 0x0700 /* ASYNC_CLK_FREQ - [10:8] */ 1016*4882a593Smuzhiyun #define WM5100_ASYNC_CLK_FREQ_SHIFT 8 /* ASYNC_CLK_FREQ - [10:8] */ 1017*4882a593Smuzhiyun #define WM5100_ASYNC_CLK_FREQ_WIDTH 3 /* ASYNC_CLK_FREQ - [10:8] */ 1018*4882a593Smuzhiyun #define WM5100_ASYNC_CLK_ENA 0x0040 /* ASYNC_CLK_ENA */ 1019*4882a593Smuzhiyun #define WM5100_ASYNC_CLK_ENA_MASK 0x0040 /* ASYNC_CLK_ENA */ 1020*4882a593Smuzhiyun #define WM5100_ASYNC_CLK_ENA_SHIFT 6 /* ASYNC_CLK_ENA */ 1021*4882a593Smuzhiyun #define WM5100_ASYNC_CLK_ENA_WIDTH 1 /* ASYNC_CLK_ENA */ 1022*4882a593Smuzhiyun #define WM5100_ASYNC_CLK_SRC_MASK 0x000F /* ASYNC_CLK_SRC - [3:0] */ 1023*4882a593Smuzhiyun #define WM5100_ASYNC_CLK_SRC_SHIFT 0 /* ASYNC_CLK_SRC - [3:0] */ 1024*4882a593Smuzhiyun #define WM5100_ASYNC_CLK_SRC_WIDTH 4 /* ASYNC_CLK_SRC - [3:0] */ 1025*4882a593Smuzhiyun 1026*4882a593Smuzhiyun /* 1027*4882a593Smuzhiyun * R264 (0x108) - Clocking 8 1028*4882a593Smuzhiyun */ 1029*4882a593Smuzhiyun #define WM5100_ASYNC_SAMPLE_RATE_MASK 0x001F /* ASYNC_SAMPLE_RATE - [4:0] */ 1030*4882a593Smuzhiyun #define WM5100_ASYNC_SAMPLE_RATE_SHIFT 0 /* ASYNC_SAMPLE_RATE - [4:0] */ 1031*4882a593Smuzhiyun #define WM5100_ASYNC_SAMPLE_RATE_WIDTH 5 /* ASYNC_SAMPLE_RATE - [4:0] */ 1032*4882a593Smuzhiyun 1033*4882a593Smuzhiyun /* 1034*4882a593Smuzhiyun * R288 (0x120) - ASRC_ENABLE 1035*4882a593Smuzhiyun */ 1036*4882a593Smuzhiyun #define WM5100_ASRC2L_ENA 0x0008 /* ASRC2L_ENA */ 1037*4882a593Smuzhiyun #define WM5100_ASRC2L_ENA_MASK 0x0008 /* ASRC2L_ENA */ 1038*4882a593Smuzhiyun #define WM5100_ASRC2L_ENA_SHIFT 3 /* ASRC2L_ENA */ 1039*4882a593Smuzhiyun #define WM5100_ASRC2L_ENA_WIDTH 1 /* ASRC2L_ENA */ 1040*4882a593Smuzhiyun #define WM5100_ASRC2R_ENA 0x0004 /* ASRC2R_ENA */ 1041*4882a593Smuzhiyun #define WM5100_ASRC2R_ENA_MASK 0x0004 /* ASRC2R_ENA */ 1042*4882a593Smuzhiyun #define WM5100_ASRC2R_ENA_SHIFT 2 /* ASRC2R_ENA */ 1043*4882a593Smuzhiyun #define WM5100_ASRC2R_ENA_WIDTH 1 /* ASRC2R_ENA */ 1044*4882a593Smuzhiyun #define WM5100_ASRC1L_ENA 0x0002 /* ASRC1L_ENA */ 1045*4882a593Smuzhiyun #define WM5100_ASRC1L_ENA_MASK 0x0002 /* ASRC1L_ENA */ 1046*4882a593Smuzhiyun #define WM5100_ASRC1L_ENA_SHIFT 1 /* ASRC1L_ENA */ 1047*4882a593Smuzhiyun #define WM5100_ASRC1L_ENA_WIDTH 1 /* ASRC1L_ENA */ 1048*4882a593Smuzhiyun #define WM5100_ASRC1R_ENA 0x0001 /* ASRC1R_ENA */ 1049*4882a593Smuzhiyun #define WM5100_ASRC1R_ENA_MASK 0x0001 /* ASRC1R_ENA */ 1050*4882a593Smuzhiyun #define WM5100_ASRC1R_ENA_SHIFT 0 /* ASRC1R_ENA */ 1051*4882a593Smuzhiyun #define WM5100_ASRC1R_ENA_WIDTH 1 /* ASRC1R_ENA */ 1052*4882a593Smuzhiyun 1053*4882a593Smuzhiyun /* 1054*4882a593Smuzhiyun * R289 (0x121) - ASRC_STATUS 1055*4882a593Smuzhiyun */ 1056*4882a593Smuzhiyun #define WM5100_ASRC2L_ENA_STS 0x0008 /* ASRC2L_ENA_STS */ 1057*4882a593Smuzhiyun #define WM5100_ASRC2L_ENA_STS_MASK 0x0008 /* ASRC2L_ENA_STS */ 1058*4882a593Smuzhiyun #define WM5100_ASRC2L_ENA_STS_SHIFT 3 /* ASRC2L_ENA_STS */ 1059*4882a593Smuzhiyun #define WM5100_ASRC2L_ENA_STS_WIDTH 1 /* ASRC2L_ENA_STS */ 1060*4882a593Smuzhiyun #define WM5100_ASRC2R_ENA_STS 0x0004 /* ASRC2R_ENA_STS */ 1061*4882a593Smuzhiyun #define WM5100_ASRC2R_ENA_STS_MASK 0x0004 /* ASRC2R_ENA_STS */ 1062*4882a593Smuzhiyun #define WM5100_ASRC2R_ENA_STS_SHIFT 2 /* ASRC2R_ENA_STS */ 1063*4882a593Smuzhiyun #define WM5100_ASRC2R_ENA_STS_WIDTH 1 /* ASRC2R_ENA_STS */ 1064*4882a593Smuzhiyun #define WM5100_ASRC1L_ENA_STS 0x0002 /* ASRC1L_ENA_STS */ 1065*4882a593Smuzhiyun #define WM5100_ASRC1L_ENA_STS_MASK 0x0002 /* ASRC1L_ENA_STS */ 1066*4882a593Smuzhiyun #define WM5100_ASRC1L_ENA_STS_SHIFT 1 /* ASRC1L_ENA_STS */ 1067*4882a593Smuzhiyun #define WM5100_ASRC1L_ENA_STS_WIDTH 1 /* ASRC1L_ENA_STS */ 1068*4882a593Smuzhiyun #define WM5100_ASRC1R_ENA_STS 0x0001 /* ASRC1R_ENA_STS */ 1069*4882a593Smuzhiyun #define WM5100_ASRC1R_ENA_STS_MASK 0x0001 /* ASRC1R_ENA_STS */ 1070*4882a593Smuzhiyun #define WM5100_ASRC1R_ENA_STS_SHIFT 0 /* ASRC1R_ENA_STS */ 1071*4882a593Smuzhiyun #define WM5100_ASRC1R_ENA_STS_WIDTH 1 /* ASRC1R_ENA_STS */ 1072*4882a593Smuzhiyun 1073*4882a593Smuzhiyun /* 1074*4882a593Smuzhiyun * R290 (0x122) - ASRC_RATE1 1075*4882a593Smuzhiyun */ 1076*4882a593Smuzhiyun #define WM5100_ASRC_RATE1_MASK 0x0006 /* ASRC_RATE1 - [2:1] */ 1077*4882a593Smuzhiyun #define WM5100_ASRC_RATE1_SHIFT 1 /* ASRC_RATE1 - [2:1] */ 1078*4882a593Smuzhiyun #define WM5100_ASRC_RATE1_WIDTH 2 /* ASRC_RATE1 - [2:1] */ 1079*4882a593Smuzhiyun 1080*4882a593Smuzhiyun /* 1081*4882a593Smuzhiyun * R321 (0x141) - ISRC 1 CTRL 1 1082*4882a593Smuzhiyun */ 1083*4882a593Smuzhiyun #define WM5100_ISRC1_DFS_ENA 0x2000 /* ISRC1_DFS_ENA */ 1084*4882a593Smuzhiyun #define WM5100_ISRC1_DFS_ENA_MASK 0x2000 /* ISRC1_DFS_ENA */ 1085*4882a593Smuzhiyun #define WM5100_ISRC1_DFS_ENA_SHIFT 13 /* ISRC1_DFS_ENA */ 1086*4882a593Smuzhiyun #define WM5100_ISRC1_DFS_ENA_WIDTH 1 /* ISRC1_DFS_ENA */ 1087*4882a593Smuzhiyun #define WM5100_ISRC1_CLK_SEL_MASK 0x0300 /* ISRC1_CLK_SEL - [9:8] */ 1088*4882a593Smuzhiyun #define WM5100_ISRC1_CLK_SEL_SHIFT 8 /* ISRC1_CLK_SEL - [9:8] */ 1089*4882a593Smuzhiyun #define WM5100_ISRC1_CLK_SEL_WIDTH 2 /* ISRC1_CLK_SEL - [9:8] */ 1090*4882a593Smuzhiyun #define WM5100_ISRC1_FSH_MASK 0x000C /* ISRC1_FSH - [3:2] */ 1091*4882a593Smuzhiyun #define WM5100_ISRC1_FSH_SHIFT 2 /* ISRC1_FSH - [3:2] */ 1092*4882a593Smuzhiyun #define WM5100_ISRC1_FSH_WIDTH 2 /* ISRC1_FSH - [3:2] */ 1093*4882a593Smuzhiyun #define WM5100_ISRC1_FSL_MASK 0x0003 /* ISRC1_FSL - [1:0] */ 1094*4882a593Smuzhiyun #define WM5100_ISRC1_FSL_SHIFT 0 /* ISRC1_FSL - [1:0] */ 1095*4882a593Smuzhiyun #define WM5100_ISRC1_FSL_WIDTH 2 /* ISRC1_FSL - [1:0] */ 1096*4882a593Smuzhiyun 1097*4882a593Smuzhiyun /* 1098*4882a593Smuzhiyun * R322 (0x142) - ISRC 1 CTRL 2 1099*4882a593Smuzhiyun */ 1100*4882a593Smuzhiyun #define WM5100_ISRC1_INT1_ENA 0x8000 /* ISRC1_INT1_ENA */ 1101*4882a593Smuzhiyun #define WM5100_ISRC1_INT1_ENA_MASK 0x8000 /* ISRC1_INT1_ENA */ 1102*4882a593Smuzhiyun #define WM5100_ISRC1_INT1_ENA_SHIFT 15 /* ISRC1_INT1_ENA */ 1103*4882a593Smuzhiyun #define WM5100_ISRC1_INT1_ENA_WIDTH 1 /* ISRC1_INT1_ENA */ 1104*4882a593Smuzhiyun #define WM5100_ISRC1_INT2_ENA 0x4000 /* ISRC1_INT2_ENA */ 1105*4882a593Smuzhiyun #define WM5100_ISRC1_INT2_ENA_MASK 0x4000 /* ISRC1_INT2_ENA */ 1106*4882a593Smuzhiyun #define WM5100_ISRC1_INT2_ENA_SHIFT 14 /* ISRC1_INT2_ENA */ 1107*4882a593Smuzhiyun #define WM5100_ISRC1_INT2_ENA_WIDTH 1 /* ISRC1_INT2_ENA */ 1108*4882a593Smuzhiyun #define WM5100_ISRC1_INT3_ENA 0x2000 /* ISRC1_INT3_ENA */ 1109*4882a593Smuzhiyun #define WM5100_ISRC1_INT3_ENA_MASK 0x2000 /* ISRC1_INT3_ENA */ 1110*4882a593Smuzhiyun #define WM5100_ISRC1_INT3_ENA_SHIFT 13 /* ISRC1_INT3_ENA */ 1111*4882a593Smuzhiyun #define WM5100_ISRC1_INT3_ENA_WIDTH 1 /* ISRC1_INT3_ENA */ 1112*4882a593Smuzhiyun #define WM5100_ISRC1_INT4_ENA 0x1000 /* ISRC1_INT4_ENA */ 1113*4882a593Smuzhiyun #define WM5100_ISRC1_INT4_ENA_MASK 0x1000 /* ISRC1_INT4_ENA */ 1114*4882a593Smuzhiyun #define WM5100_ISRC1_INT4_ENA_SHIFT 12 /* ISRC1_INT4_ENA */ 1115*4882a593Smuzhiyun #define WM5100_ISRC1_INT4_ENA_WIDTH 1 /* ISRC1_INT4_ENA */ 1116*4882a593Smuzhiyun #define WM5100_ISRC1_DEC1_ENA 0x0200 /* ISRC1_DEC1_ENA */ 1117*4882a593Smuzhiyun #define WM5100_ISRC1_DEC1_ENA_MASK 0x0200 /* ISRC1_DEC1_ENA */ 1118*4882a593Smuzhiyun #define WM5100_ISRC1_DEC1_ENA_SHIFT 9 /* ISRC1_DEC1_ENA */ 1119*4882a593Smuzhiyun #define WM5100_ISRC1_DEC1_ENA_WIDTH 1 /* ISRC1_DEC1_ENA */ 1120*4882a593Smuzhiyun #define WM5100_ISRC1_DEC2_ENA 0x0100 /* ISRC1_DEC2_ENA */ 1121*4882a593Smuzhiyun #define WM5100_ISRC1_DEC2_ENA_MASK 0x0100 /* ISRC1_DEC2_ENA */ 1122*4882a593Smuzhiyun #define WM5100_ISRC1_DEC2_ENA_SHIFT 8 /* ISRC1_DEC2_ENA */ 1123*4882a593Smuzhiyun #define WM5100_ISRC1_DEC2_ENA_WIDTH 1 /* ISRC1_DEC2_ENA */ 1124*4882a593Smuzhiyun #define WM5100_ISRC1_DEC3_ENA 0x0080 /* ISRC1_DEC3_ENA */ 1125*4882a593Smuzhiyun #define WM5100_ISRC1_DEC3_ENA_MASK 0x0080 /* ISRC1_DEC3_ENA */ 1126*4882a593Smuzhiyun #define WM5100_ISRC1_DEC3_ENA_SHIFT 7 /* ISRC1_DEC3_ENA */ 1127*4882a593Smuzhiyun #define WM5100_ISRC1_DEC3_ENA_WIDTH 1 /* ISRC1_DEC3_ENA */ 1128*4882a593Smuzhiyun #define WM5100_ISRC1_DEC4_ENA 0x0040 /* ISRC1_DEC4_ENA */ 1129*4882a593Smuzhiyun #define WM5100_ISRC1_DEC4_ENA_MASK 0x0040 /* ISRC1_DEC4_ENA */ 1130*4882a593Smuzhiyun #define WM5100_ISRC1_DEC4_ENA_SHIFT 6 /* ISRC1_DEC4_ENA */ 1131*4882a593Smuzhiyun #define WM5100_ISRC1_DEC4_ENA_WIDTH 1 /* ISRC1_DEC4_ENA */ 1132*4882a593Smuzhiyun #define WM5100_ISRC1_NOTCH_ENA 0x0001 /* ISRC1_NOTCH_ENA */ 1133*4882a593Smuzhiyun #define WM5100_ISRC1_NOTCH_ENA_MASK 0x0001 /* ISRC1_NOTCH_ENA */ 1134*4882a593Smuzhiyun #define WM5100_ISRC1_NOTCH_ENA_SHIFT 0 /* ISRC1_NOTCH_ENA */ 1135*4882a593Smuzhiyun #define WM5100_ISRC1_NOTCH_ENA_WIDTH 1 /* ISRC1_NOTCH_ENA */ 1136*4882a593Smuzhiyun 1137*4882a593Smuzhiyun /* 1138*4882a593Smuzhiyun * R323 (0x143) - ISRC 2 CTRL1 1139*4882a593Smuzhiyun */ 1140*4882a593Smuzhiyun #define WM5100_ISRC2_DFS_ENA 0x2000 /* ISRC2_DFS_ENA */ 1141*4882a593Smuzhiyun #define WM5100_ISRC2_DFS_ENA_MASK 0x2000 /* ISRC2_DFS_ENA */ 1142*4882a593Smuzhiyun #define WM5100_ISRC2_DFS_ENA_SHIFT 13 /* ISRC2_DFS_ENA */ 1143*4882a593Smuzhiyun #define WM5100_ISRC2_DFS_ENA_WIDTH 1 /* ISRC2_DFS_ENA */ 1144*4882a593Smuzhiyun #define WM5100_ISRC2_CLK_SEL_MASK 0x0300 /* ISRC2_CLK_SEL - [9:8] */ 1145*4882a593Smuzhiyun #define WM5100_ISRC2_CLK_SEL_SHIFT 8 /* ISRC2_CLK_SEL - [9:8] */ 1146*4882a593Smuzhiyun #define WM5100_ISRC2_CLK_SEL_WIDTH 2 /* ISRC2_CLK_SEL - [9:8] */ 1147*4882a593Smuzhiyun #define WM5100_ISRC2_FSH_MASK 0x000C /* ISRC2_FSH - [3:2] */ 1148*4882a593Smuzhiyun #define WM5100_ISRC2_FSH_SHIFT 2 /* ISRC2_FSH - [3:2] */ 1149*4882a593Smuzhiyun #define WM5100_ISRC2_FSH_WIDTH 2 /* ISRC2_FSH - [3:2] */ 1150*4882a593Smuzhiyun #define WM5100_ISRC2_FSL_MASK 0x0003 /* ISRC2_FSL - [1:0] */ 1151*4882a593Smuzhiyun #define WM5100_ISRC2_FSL_SHIFT 0 /* ISRC2_FSL - [1:0] */ 1152*4882a593Smuzhiyun #define WM5100_ISRC2_FSL_WIDTH 2 /* ISRC2_FSL - [1:0] */ 1153*4882a593Smuzhiyun 1154*4882a593Smuzhiyun /* 1155*4882a593Smuzhiyun * R324 (0x144) - ISRC 2 CTRL 2 1156*4882a593Smuzhiyun */ 1157*4882a593Smuzhiyun #define WM5100_ISRC2_INT1_ENA 0x8000 /* ISRC2_INT1_ENA */ 1158*4882a593Smuzhiyun #define WM5100_ISRC2_INT1_ENA_MASK 0x8000 /* ISRC2_INT1_ENA */ 1159*4882a593Smuzhiyun #define WM5100_ISRC2_INT1_ENA_SHIFT 15 /* ISRC2_INT1_ENA */ 1160*4882a593Smuzhiyun #define WM5100_ISRC2_INT1_ENA_WIDTH 1 /* ISRC2_INT1_ENA */ 1161*4882a593Smuzhiyun #define WM5100_ISRC2_INT2_ENA 0x4000 /* ISRC2_INT2_ENA */ 1162*4882a593Smuzhiyun #define WM5100_ISRC2_INT2_ENA_MASK 0x4000 /* ISRC2_INT2_ENA */ 1163*4882a593Smuzhiyun #define WM5100_ISRC2_INT2_ENA_SHIFT 14 /* ISRC2_INT2_ENA */ 1164*4882a593Smuzhiyun #define WM5100_ISRC2_INT2_ENA_WIDTH 1 /* ISRC2_INT2_ENA */ 1165*4882a593Smuzhiyun #define WM5100_ISRC2_INT3_ENA 0x2000 /* ISRC2_INT3_ENA */ 1166*4882a593Smuzhiyun #define WM5100_ISRC2_INT3_ENA_MASK 0x2000 /* ISRC2_INT3_ENA */ 1167*4882a593Smuzhiyun #define WM5100_ISRC2_INT3_ENA_SHIFT 13 /* ISRC2_INT3_ENA */ 1168*4882a593Smuzhiyun #define WM5100_ISRC2_INT3_ENA_WIDTH 1 /* ISRC2_INT3_ENA */ 1169*4882a593Smuzhiyun #define WM5100_ISRC2_INT4_ENA 0x1000 /* ISRC2_INT4_ENA */ 1170*4882a593Smuzhiyun #define WM5100_ISRC2_INT4_ENA_MASK 0x1000 /* ISRC2_INT4_ENA */ 1171*4882a593Smuzhiyun #define WM5100_ISRC2_INT4_ENA_SHIFT 12 /* ISRC2_INT4_ENA */ 1172*4882a593Smuzhiyun #define WM5100_ISRC2_INT4_ENA_WIDTH 1 /* ISRC2_INT4_ENA */ 1173*4882a593Smuzhiyun #define WM5100_ISRC2_DEC1_ENA 0x0200 /* ISRC2_DEC1_ENA */ 1174*4882a593Smuzhiyun #define WM5100_ISRC2_DEC1_ENA_MASK 0x0200 /* ISRC2_DEC1_ENA */ 1175*4882a593Smuzhiyun #define WM5100_ISRC2_DEC1_ENA_SHIFT 9 /* ISRC2_DEC1_ENA */ 1176*4882a593Smuzhiyun #define WM5100_ISRC2_DEC1_ENA_WIDTH 1 /* ISRC2_DEC1_ENA */ 1177*4882a593Smuzhiyun #define WM5100_ISRC2_DEC2_ENA 0x0100 /* ISRC2_DEC2_ENA */ 1178*4882a593Smuzhiyun #define WM5100_ISRC2_DEC2_ENA_MASK 0x0100 /* ISRC2_DEC2_ENA */ 1179*4882a593Smuzhiyun #define WM5100_ISRC2_DEC2_ENA_SHIFT 8 /* ISRC2_DEC2_ENA */ 1180*4882a593Smuzhiyun #define WM5100_ISRC2_DEC2_ENA_WIDTH 1 /* ISRC2_DEC2_ENA */ 1181*4882a593Smuzhiyun #define WM5100_ISRC2_DEC3_ENA 0x0080 /* ISRC2_DEC3_ENA */ 1182*4882a593Smuzhiyun #define WM5100_ISRC2_DEC3_ENA_MASK 0x0080 /* ISRC2_DEC3_ENA */ 1183*4882a593Smuzhiyun #define WM5100_ISRC2_DEC3_ENA_SHIFT 7 /* ISRC2_DEC3_ENA */ 1184*4882a593Smuzhiyun #define WM5100_ISRC2_DEC3_ENA_WIDTH 1 /* ISRC2_DEC3_ENA */ 1185*4882a593Smuzhiyun #define WM5100_ISRC2_DEC4_ENA 0x0040 /* ISRC2_DEC4_ENA */ 1186*4882a593Smuzhiyun #define WM5100_ISRC2_DEC4_ENA_MASK 0x0040 /* ISRC2_DEC4_ENA */ 1187*4882a593Smuzhiyun #define WM5100_ISRC2_DEC4_ENA_SHIFT 6 /* ISRC2_DEC4_ENA */ 1188*4882a593Smuzhiyun #define WM5100_ISRC2_DEC4_ENA_WIDTH 1 /* ISRC2_DEC4_ENA */ 1189*4882a593Smuzhiyun #define WM5100_ISRC2_NOTCH_ENA 0x0001 /* ISRC2_NOTCH_ENA */ 1190*4882a593Smuzhiyun #define WM5100_ISRC2_NOTCH_ENA_MASK 0x0001 /* ISRC2_NOTCH_ENA */ 1191*4882a593Smuzhiyun #define WM5100_ISRC2_NOTCH_ENA_SHIFT 0 /* ISRC2_NOTCH_ENA */ 1192*4882a593Smuzhiyun #define WM5100_ISRC2_NOTCH_ENA_WIDTH 1 /* ISRC2_NOTCH_ENA */ 1193*4882a593Smuzhiyun 1194*4882a593Smuzhiyun /* 1195*4882a593Smuzhiyun * R386 (0x182) - FLL1 Control 1 1196*4882a593Smuzhiyun */ 1197*4882a593Smuzhiyun #define WM5100_FLL1_ENA 0x0001 /* FLL1_ENA */ 1198*4882a593Smuzhiyun #define WM5100_FLL1_ENA_MASK 0x0001 /* FLL1_ENA */ 1199*4882a593Smuzhiyun #define WM5100_FLL1_ENA_SHIFT 0 /* FLL1_ENA */ 1200*4882a593Smuzhiyun #define WM5100_FLL1_ENA_WIDTH 1 /* FLL1_ENA */ 1201*4882a593Smuzhiyun 1202*4882a593Smuzhiyun /* 1203*4882a593Smuzhiyun * R387 (0x183) - FLL1 Control 2 1204*4882a593Smuzhiyun */ 1205*4882a593Smuzhiyun #define WM5100_FLL1_OUTDIV_MASK 0x3F00 /* FLL1_OUTDIV - [13:8] */ 1206*4882a593Smuzhiyun #define WM5100_FLL1_OUTDIV_SHIFT 8 /* FLL1_OUTDIV - [13:8] */ 1207*4882a593Smuzhiyun #define WM5100_FLL1_OUTDIV_WIDTH 6 /* FLL1_OUTDIV - [13:8] */ 1208*4882a593Smuzhiyun #define WM5100_FLL1_FRATIO_MASK 0x0007 /* FLL1_FRATIO - [2:0] */ 1209*4882a593Smuzhiyun #define WM5100_FLL1_FRATIO_SHIFT 0 /* FLL1_FRATIO - [2:0] */ 1210*4882a593Smuzhiyun #define WM5100_FLL1_FRATIO_WIDTH 3 /* FLL1_FRATIO - [2:0] */ 1211*4882a593Smuzhiyun 1212*4882a593Smuzhiyun /* 1213*4882a593Smuzhiyun * R388 (0x184) - FLL1 Control 3 1214*4882a593Smuzhiyun */ 1215*4882a593Smuzhiyun #define WM5100_FLL1_THETA_MASK 0xFFFF /* FLL1_THETA - [15:0] */ 1216*4882a593Smuzhiyun #define WM5100_FLL1_THETA_SHIFT 0 /* FLL1_THETA - [15:0] */ 1217*4882a593Smuzhiyun #define WM5100_FLL1_THETA_WIDTH 16 /* FLL1_THETA - [15:0] */ 1218*4882a593Smuzhiyun 1219*4882a593Smuzhiyun /* 1220*4882a593Smuzhiyun * R390 (0x186) - FLL1 Control 5 1221*4882a593Smuzhiyun */ 1222*4882a593Smuzhiyun #define WM5100_FLL1_N_MASK 0x03FF /* FLL1_N - [9:0] */ 1223*4882a593Smuzhiyun #define WM5100_FLL1_N_SHIFT 0 /* FLL1_N - [9:0] */ 1224*4882a593Smuzhiyun #define WM5100_FLL1_N_WIDTH 10 /* FLL1_N - [9:0] */ 1225*4882a593Smuzhiyun 1226*4882a593Smuzhiyun /* 1227*4882a593Smuzhiyun * R391 (0x187) - FLL1 Control 6 1228*4882a593Smuzhiyun */ 1229*4882a593Smuzhiyun #define WM5100_FLL1_REFCLK_DIV_MASK 0x00C0 /* FLL1_REFCLK_DIV - [7:6] */ 1230*4882a593Smuzhiyun #define WM5100_FLL1_REFCLK_DIV_SHIFT 6 /* FLL1_REFCLK_DIV - [7:6] */ 1231*4882a593Smuzhiyun #define WM5100_FLL1_REFCLK_DIV_WIDTH 2 /* FLL1_REFCLK_DIV - [7:6] */ 1232*4882a593Smuzhiyun #define WM5100_FLL1_REFCLK_SRC_MASK 0x000F /* FLL1_REFCLK_SRC - [3:0] */ 1233*4882a593Smuzhiyun #define WM5100_FLL1_REFCLK_SRC_SHIFT 0 /* FLL1_REFCLK_SRC - [3:0] */ 1234*4882a593Smuzhiyun #define WM5100_FLL1_REFCLK_SRC_WIDTH 4 /* FLL1_REFCLK_SRC - [3:0] */ 1235*4882a593Smuzhiyun 1236*4882a593Smuzhiyun /* 1237*4882a593Smuzhiyun * R392 (0x188) - FLL1 EFS 1 1238*4882a593Smuzhiyun */ 1239*4882a593Smuzhiyun #define WM5100_FLL1_LAMBDA_MASK 0xFFFF /* FLL1_LAMBDA - [15:0] */ 1240*4882a593Smuzhiyun #define WM5100_FLL1_LAMBDA_SHIFT 0 /* FLL1_LAMBDA - [15:0] */ 1241*4882a593Smuzhiyun #define WM5100_FLL1_LAMBDA_WIDTH 16 /* FLL1_LAMBDA - [15:0] */ 1242*4882a593Smuzhiyun 1243*4882a593Smuzhiyun /* 1244*4882a593Smuzhiyun * R418 (0x1A2) - FLL2 Control 1 1245*4882a593Smuzhiyun */ 1246*4882a593Smuzhiyun #define WM5100_FLL2_ENA 0x0001 /* FLL2_ENA */ 1247*4882a593Smuzhiyun #define WM5100_FLL2_ENA_MASK 0x0001 /* FLL2_ENA */ 1248*4882a593Smuzhiyun #define WM5100_FLL2_ENA_SHIFT 0 /* FLL2_ENA */ 1249*4882a593Smuzhiyun #define WM5100_FLL2_ENA_WIDTH 1 /* FLL2_ENA */ 1250*4882a593Smuzhiyun 1251*4882a593Smuzhiyun /* 1252*4882a593Smuzhiyun * R419 (0x1A3) - FLL2 Control 2 1253*4882a593Smuzhiyun */ 1254*4882a593Smuzhiyun #define WM5100_FLL2_OUTDIV_MASK 0x3F00 /* FLL2_OUTDIV - [13:8] */ 1255*4882a593Smuzhiyun #define WM5100_FLL2_OUTDIV_SHIFT 8 /* FLL2_OUTDIV - [13:8] */ 1256*4882a593Smuzhiyun #define WM5100_FLL2_OUTDIV_WIDTH 6 /* FLL2_OUTDIV - [13:8] */ 1257*4882a593Smuzhiyun #define WM5100_FLL2_FRATIO_MASK 0x0007 /* FLL2_FRATIO - [2:0] */ 1258*4882a593Smuzhiyun #define WM5100_FLL2_FRATIO_SHIFT 0 /* FLL2_FRATIO - [2:0] */ 1259*4882a593Smuzhiyun #define WM5100_FLL2_FRATIO_WIDTH 3 /* FLL2_FRATIO - [2:0] */ 1260*4882a593Smuzhiyun 1261*4882a593Smuzhiyun /* 1262*4882a593Smuzhiyun * R420 (0x1A4) - FLL2 Control 3 1263*4882a593Smuzhiyun */ 1264*4882a593Smuzhiyun #define WM5100_FLL2_THETA_MASK 0xFFFF /* FLL2_THETA - [15:0] */ 1265*4882a593Smuzhiyun #define WM5100_FLL2_THETA_SHIFT 0 /* FLL2_THETA - [15:0] */ 1266*4882a593Smuzhiyun #define WM5100_FLL2_THETA_WIDTH 16 /* FLL2_THETA - [15:0] */ 1267*4882a593Smuzhiyun 1268*4882a593Smuzhiyun /* 1269*4882a593Smuzhiyun * R422 (0x1A6) - FLL2 Control 5 1270*4882a593Smuzhiyun */ 1271*4882a593Smuzhiyun #define WM5100_FLL2_N_MASK 0x03FF /* FLL2_N - [9:0] */ 1272*4882a593Smuzhiyun #define WM5100_FLL2_N_SHIFT 0 /* FLL2_N - [9:0] */ 1273*4882a593Smuzhiyun #define WM5100_FLL2_N_WIDTH 10 /* FLL2_N - [9:0] */ 1274*4882a593Smuzhiyun 1275*4882a593Smuzhiyun /* 1276*4882a593Smuzhiyun * R423 (0x1A7) - FLL2 Control 6 1277*4882a593Smuzhiyun */ 1278*4882a593Smuzhiyun #define WM5100_FLL2_REFCLK_DIV_MASK 0x00C0 /* FLL2_REFCLK_DIV - [7:6] */ 1279*4882a593Smuzhiyun #define WM5100_FLL2_REFCLK_DIV_SHIFT 6 /* FLL2_REFCLK_DIV - [7:6] */ 1280*4882a593Smuzhiyun #define WM5100_FLL2_REFCLK_DIV_WIDTH 2 /* FLL2_REFCLK_DIV - [7:6] */ 1281*4882a593Smuzhiyun #define WM5100_FLL2_REFCLK_SRC_MASK 0x000F /* FLL2_REFCLK_SRC - [3:0] */ 1282*4882a593Smuzhiyun #define WM5100_FLL2_REFCLK_SRC_SHIFT 0 /* FLL2_REFCLK_SRC - [3:0] */ 1283*4882a593Smuzhiyun #define WM5100_FLL2_REFCLK_SRC_WIDTH 4 /* FLL2_REFCLK_SRC - [3:0] */ 1284*4882a593Smuzhiyun 1285*4882a593Smuzhiyun /* 1286*4882a593Smuzhiyun * R424 (0x1A8) - FLL2 EFS 1 1287*4882a593Smuzhiyun */ 1288*4882a593Smuzhiyun #define WM5100_FLL2_LAMBDA_MASK 0xFFFF /* FLL2_LAMBDA - [15:0] */ 1289*4882a593Smuzhiyun #define WM5100_FLL2_LAMBDA_SHIFT 0 /* FLL2_LAMBDA - [15:0] */ 1290*4882a593Smuzhiyun #define WM5100_FLL2_LAMBDA_WIDTH 16 /* FLL2_LAMBDA - [15:0] */ 1291*4882a593Smuzhiyun 1292*4882a593Smuzhiyun /* 1293*4882a593Smuzhiyun * R512 (0x200) - Mic Charge Pump 1 1294*4882a593Smuzhiyun */ 1295*4882a593Smuzhiyun #define WM5100_CP2_BYPASS 0x0020 /* CP2_BYPASS */ 1296*4882a593Smuzhiyun #define WM5100_CP2_BYPASS_MASK 0x0020 /* CP2_BYPASS */ 1297*4882a593Smuzhiyun #define WM5100_CP2_BYPASS_SHIFT 5 /* CP2_BYPASS */ 1298*4882a593Smuzhiyun #define WM5100_CP2_BYPASS_WIDTH 1 /* CP2_BYPASS */ 1299*4882a593Smuzhiyun #define WM5100_CP2_ENA 0x0001 /* CP2_ENA */ 1300*4882a593Smuzhiyun #define WM5100_CP2_ENA_MASK 0x0001 /* CP2_ENA */ 1301*4882a593Smuzhiyun #define WM5100_CP2_ENA_SHIFT 0 /* CP2_ENA */ 1302*4882a593Smuzhiyun #define WM5100_CP2_ENA_WIDTH 1 /* CP2_ENA */ 1303*4882a593Smuzhiyun 1304*4882a593Smuzhiyun /* 1305*4882a593Smuzhiyun * R513 (0x201) - Mic Charge Pump 2 1306*4882a593Smuzhiyun */ 1307*4882a593Smuzhiyun #define WM5100_LDO2_VSEL_MASK 0xF800 /* LDO2_VSEL - [15:11] */ 1308*4882a593Smuzhiyun #define WM5100_LDO2_VSEL_SHIFT 11 /* LDO2_VSEL - [15:11] */ 1309*4882a593Smuzhiyun #define WM5100_LDO2_VSEL_WIDTH 5 /* LDO2_VSEL - [15:11] */ 1310*4882a593Smuzhiyun 1311*4882a593Smuzhiyun /* 1312*4882a593Smuzhiyun * R514 (0x202) - HP Charge Pump 1 1313*4882a593Smuzhiyun */ 1314*4882a593Smuzhiyun #define WM5100_CP1_ENA 0x0001 /* CP1_ENA */ 1315*4882a593Smuzhiyun #define WM5100_CP1_ENA_MASK 0x0001 /* CP1_ENA */ 1316*4882a593Smuzhiyun #define WM5100_CP1_ENA_SHIFT 0 /* CP1_ENA */ 1317*4882a593Smuzhiyun #define WM5100_CP1_ENA_WIDTH 1 /* CP1_ENA */ 1318*4882a593Smuzhiyun 1319*4882a593Smuzhiyun /* 1320*4882a593Smuzhiyun * R529 (0x211) - LDO1 Control 1321*4882a593Smuzhiyun */ 1322*4882a593Smuzhiyun #define WM5100_LDO1_BYPASS 0x0002 /* LDO1_BYPASS */ 1323*4882a593Smuzhiyun #define WM5100_LDO1_BYPASS_MASK 0x0002 /* LDO1_BYPASS */ 1324*4882a593Smuzhiyun #define WM5100_LDO1_BYPASS_SHIFT 1 /* LDO1_BYPASS */ 1325*4882a593Smuzhiyun #define WM5100_LDO1_BYPASS_WIDTH 1 /* LDO1_BYPASS */ 1326*4882a593Smuzhiyun 1327*4882a593Smuzhiyun /* 1328*4882a593Smuzhiyun * R533 (0x215) - Mic Bias Ctrl 1 1329*4882a593Smuzhiyun */ 1330*4882a593Smuzhiyun #define WM5100_MICB1_DISCH 0x0040 /* MICB1_DISCH */ 1331*4882a593Smuzhiyun #define WM5100_MICB1_DISCH_MASK 0x0040 /* MICB1_DISCH */ 1332*4882a593Smuzhiyun #define WM5100_MICB1_DISCH_SHIFT 6 /* MICB1_DISCH */ 1333*4882a593Smuzhiyun #define WM5100_MICB1_DISCH_WIDTH 1 /* MICB1_DISCH */ 1334*4882a593Smuzhiyun #define WM5100_MICB1_RATE 0x0020 /* MICB1_RATE */ 1335*4882a593Smuzhiyun #define WM5100_MICB1_RATE_MASK 0x0020 /* MICB1_RATE */ 1336*4882a593Smuzhiyun #define WM5100_MICB1_RATE_SHIFT 5 /* MICB1_RATE */ 1337*4882a593Smuzhiyun #define WM5100_MICB1_RATE_WIDTH 1 /* MICB1_RATE */ 1338*4882a593Smuzhiyun #define WM5100_MICB1_LVL_MASK 0x001C /* MICB1_LVL - [4:2] */ 1339*4882a593Smuzhiyun #define WM5100_MICB1_LVL_SHIFT 2 /* MICB1_LVL - [4:2] */ 1340*4882a593Smuzhiyun #define WM5100_MICB1_LVL_WIDTH 3 /* MICB1_LVL - [4:2] */ 1341*4882a593Smuzhiyun #define WM5100_MICB1_BYPASS 0x0002 /* MICB1_BYPASS */ 1342*4882a593Smuzhiyun #define WM5100_MICB1_BYPASS_MASK 0x0002 /* MICB1_BYPASS */ 1343*4882a593Smuzhiyun #define WM5100_MICB1_BYPASS_SHIFT 1 /* MICB1_BYPASS */ 1344*4882a593Smuzhiyun #define WM5100_MICB1_BYPASS_WIDTH 1 /* MICB1_BYPASS */ 1345*4882a593Smuzhiyun #define WM5100_MICB1_ENA 0x0001 /* MICB1_ENA */ 1346*4882a593Smuzhiyun #define WM5100_MICB1_ENA_MASK 0x0001 /* MICB1_ENA */ 1347*4882a593Smuzhiyun #define WM5100_MICB1_ENA_SHIFT 0 /* MICB1_ENA */ 1348*4882a593Smuzhiyun #define WM5100_MICB1_ENA_WIDTH 1 /* MICB1_ENA */ 1349*4882a593Smuzhiyun 1350*4882a593Smuzhiyun /* 1351*4882a593Smuzhiyun * R534 (0x216) - Mic Bias Ctrl 2 1352*4882a593Smuzhiyun */ 1353*4882a593Smuzhiyun #define WM5100_MICB2_DISCH 0x0040 /* MICB2_DISCH */ 1354*4882a593Smuzhiyun #define WM5100_MICB2_DISCH_MASK 0x0040 /* MICB2_DISCH */ 1355*4882a593Smuzhiyun #define WM5100_MICB2_DISCH_SHIFT 6 /* MICB2_DISCH */ 1356*4882a593Smuzhiyun #define WM5100_MICB2_DISCH_WIDTH 1 /* MICB2_DISCH */ 1357*4882a593Smuzhiyun #define WM5100_MICB2_RATE 0x0020 /* MICB2_RATE */ 1358*4882a593Smuzhiyun #define WM5100_MICB2_RATE_MASK 0x0020 /* MICB2_RATE */ 1359*4882a593Smuzhiyun #define WM5100_MICB2_RATE_SHIFT 5 /* MICB2_RATE */ 1360*4882a593Smuzhiyun #define WM5100_MICB2_RATE_WIDTH 1 /* MICB2_RATE */ 1361*4882a593Smuzhiyun #define WM5100_MICB2_LVL_MASK 0x001C /* MICB2_LVL - [4:2] */ 1362*4882a593Smuzhiyun #define WM5100_MICB2_LVL_SHIFT 2 /* MICB2_LVL - [4:2] */ 1363*4882a593Smuzhiyun #define WM5100_MICB2_LVL_WIDTH 3 /* MICB2_LVL - [4:2] */ 1364*4882a593Smuzhiyun #define WM5100_MICB2_BYPASS 0x0002 /* MICB2_BYPASS */ 1365*4882a593Smuzhiyun #define WM5100_MICB2_BYPASS_MASK 0x0002 /* MICB2_BYPASS */ 1366*4882a593Smuzhiyun #define WM5100_MICB2_BYPASS_SHIFT 1 /* MICB2_BYPASS */ 1367*4882a593Smuzhiyun #define WM5100_MICB2_BYPASS_WIDTH 1 /* MICB2_BYPASS */ 1368*4882a593Smuzhiyun #define WM5100_MICB2_ENA 0x0001 /* MICB2_ENA */ 1369*4882a593Smuzhiyun #define WM5100_MICB2_ENA_MASK 0x0001 /* MICB2_ENA */ 1370*4882a593Smuzhiyun #define WM5100_MICB2_ENA_SHIFT 0 /* MICB2_ENA */ 1371*4882a593Smuzhiyun #define WM5100_MICB2_ENA_WIDTH 1 /* MICB2_ENA */ 1372*4882a593Smuzhiyun 1373*4882a593Smuzhiyun /* 1374*4882a593Smuzhiyun * R535 (0x217) - Mic Bias Ctrl 3 1375*4882a593Smuzhiyun */ 1376*4882a593Smuzhiyun #define WM5100_MICB3_DISCH 0x0040 /* MICB3_DISCH */ 1377*4882a593Smuzhiyun #define WM5100_MICB3_DISCH_MASK 0x0040 /* MICB3_DISCH */ 1378*4882a593Smuzhiyun #define WM5100_MICB3_DISCH_SHIFT 6 /* MICB3_DISCH */ 1379*4882a593Smuzhiyun #define WM5100_MICB3_DISCH_WIDTH 1 /* MICB3_DISCH */ 1380*4882a593Smuzhiyun #define WM5100_MICB3_RATE 0x0020 /* MICB3_RATE */ 1381*4882a593Smuzhiyun #define WM5100_MICB3_RATE_MASK 0x0020 /* MICB3_RATE */ 1382*4882a593Smuzhiyun #define WM5100_MICB3_RATE_SHIFT 5 /* MICB3_RATE */ 1383*4882a593Smuzhiyun #define WM5100_MICB3_RATE_WIDTH 1 /* MICB3_RATE */ 1384*4882a593Smuzhiyun #define WM5100_MICB3_LVL_MASK 0x001C /* MICB3_LVL - [4:2] */ 1385*4882a593Smuzhiyun #define WM5100_MICB3_LVL_SHIFT 2 /* MICB3_LVL - [4:2] */ 1386*4882a593Smuzhiyun #define WM5100_MICB3_LVL_WIDTH 3 /* MICB3_LVL - [4:2] */ 1387*4882a593Smuzhiyun #define WM5100_MICB3_BYPASS 0x0002 /* MICB3_BYPASS */ 1388*4882a593Smuzhiyun #define WM5100_MICB3_BYPASS_MASK 0x0002 /* MICB3_BYPASS */ 1389*4882a593Smuzhiyun #define WM5100_MICB3_BYPASS_SHIFT 1 /* MICB3_BYPASS */ 1390*4882a593Smuzhiyun #define WM5100_MICB3_BYPASS_WIDTH 1 /* MICB3_BYPASS */ 1391*4882a593Smuzhiyun #define WM5100_MICB3_ENA 0x0001 /* MICB3_ENA */ 1392*4882a593Smuzhiyun #define WM5100_MICB3_ENA_MASK 0x0001 /* MICB3_ENA */ 1393*4882a593Smuzhiyun #define WM5100_MICB3_ENA_SHIFT 0 /* MICB3_ENA */ 1394*4882a593Smuzhiyun #define WM5100_MICB3_ENA_WIDTH 1 /* MICB3_ENA */ 1395*4882a593Smuzhiyun 1396*4882a593Smuzhiyun /* 1397*4882a593Smuzhiyun * R640 (0x280) - Accessory Detect Mode 1 1398*4882a593Smuzhiyun */ 1399*4882a593Smuzhiyun #define WM5100_ACCDET_BIAS_SRC_MASK 0xC000 /* ACCDET_BIAS_SRC - [15:14] */ 1400*4882a593Smuzhiyun #define WM5100_ACCDET_BIAS_SRC_SHIFT 14 /* ACCDET_BIAS_SRC - [15:14] */ 1401*4882a593Smuzhiyun #define WM5100_ACCDET_BIAS_SRC_WIDTH 2 /* ACCDET_BIAS_SRC - [15:14] */ 1402*4882a593Smuzhiyun #define WM5100_ACCDET_SRC 0x2000 /* ACCDET_SRC */ 1403*4882a593Smuzhiyun #define WM5100_ACCDET_SRC_MASK 0x2000 /* ACCDET_SRC */ 1404*4882a593Smuzhiyun #define WM5100_ACCDET_SRC_SHIFT 13 /* ACCDET_SRC */ 1405*4882a593Smuzhiyun #define WM5100_ACCDET_SRC_WIDTH 1 /* ACCDET_SRC */ 1406*4882a593Smuzhiyun #define WM5100_ACCDET_MODE_MASK 0x0003 /* ACCDET_MODE - [1:0] */ 1407*4882a593Smuzhiyun #define WM5100_ACCDET_MODE_SHIFT 0 /* ACCDET_MODE - [1:0] */ 1408*4882a593Smuzhiyun #define WM5100_ACCDET_MODE_WIDTH 2 /* ACCDET_MODE - [1:0] */ 1409*4882a593Smuzhiyun 1410*4882a593Smuzhiyun /* 1411*4882a593Smuzhiyun * R648 (0x288) - Headphone Detect 1 1412*4882a593Smuzhiyun */ 1413*4882a593Smuzhiyun #define WM5100_HP_HOLDTIME_MASK 0x00E0 /* HP_HOLDTIME - [7:5] */ 1414*4882a593Smuzhiyun #define WM5100_HP_HOLDTIME_SHIFT 5 /* HP_HOLDTIME - [7:5] */ 1415*4882a593Smuzhiyun #define WM5100_HP_HOLDTIME_WIDTH 3 /* HP_HOLDTIME - [7:5] */ 1416*4882a593Smuzhiyun #define WM5100_HP_CLK_DIV_MASK 0x0018 /* HP_CLK_DIV - [4:3] */ 1417*4882a593Smuzhiyun #define WM5100_HP_CLK_DIV_SHIFT 3 /* HP_CLK_DIV - [4:3] */ 1418*4882a593Smuzhiyun #define WM5100_HP_CLK_DIV_WIDTH 2 /* HP_CLK_DIV - [4:3] */ 1419*4882a593Smuzhiyun #define WM5100_HP_STEP_SIZE 0x0002 /* HP_STEP_SIZE */ 1420*4882a593Smuzhiyun #define WM5100_HP_STEP_SIZE_MASK 0x0002 /* HP_STEP_SIZE */ 1421*4882a593Smuzhiyun #define WM5100_HP_STEP_SIZE_SHIFT 1 /* HP_STEP_SIZE */ 1422*4882a593Smuzhiyun #define WM5100_HP_STEP_SIZE_WIDTH 1 /* HP_STEP_SIZE */ 1423*4882a593Smuzhiyun #define WM5100_HP_POLL 0x0001 /* HP_POLL */ 1424*4882a593Smuzhiyun #define WM5100_HP_POLL_MASK 0x0001 /* HP_POLL */ 1425*4882a593Smuzhiyun #define WM5100_HP_POLL_SHIFT 0 /* HP_POLL */ 1426*4882a593Smuzhiyun #define WM5100_HP_POLL_WIDTH 1 /* HP_POLL */ 1427*4882a593Smuzhiyun 1428*4882a593Smuzhiyun /* 1429*4882a593Smuzhiyun * R649 (0x289) - Headphone Detect 2 1430*4882a593Smuzhiyun */ 1431*4882a593Smuzhiyun #define WM5100_HP_DONE 0x0080 /* HP_DONE */ 1432*4882a593Smuzhiyun #define WM5100_HP_DONE_MASK 0x0080 /* HP_DONE */ 1433*4882a593Smuzhiyun #define WM5100_HP_DONE_SHIFT 7 /* HP_DONE */ 1434*4882a593Smuzhiyun #define WM5100_HP_DONE_WIDTH 1 /* HP_DONE */ 1435*4882a593Smuzhiyun #define WM5100_HP_LVL_MASK 0x007F /* HP_LVL - [6:0] */ 1436*4882a593Smuzhiyun #define WM5100_HP_LVL_SHIFT 0 /* HP_LVL - [6:0] */ 1437*4882a593Smuzhiyun #define WM5100_HP_LVL_WIDTH 7 /* HP_LVL - [6:0] */ 1438*4882a593Smuzhiyun 1439*4882a593Smuzhiyun /* 1440*4882a593Smuzhiyun * R656 (0x290) - Mic Detect 1 1441*4882a593Smuzhiyun */ 1442*4882a593Smuzhiyun #define WM5100_ACCDET_BIAS_STARTTIME_MASK 0xF000 /* ACCDET_BIAS_STARTTIME - [15:12] */ 1443*4882a593Smuzhiyun #define WM5100_ACCDET_BIAS_STARTTIME_SHIFT 12 /* ACCDET_BIAS_STARTTIME - [15:12] */ 1444*4882a593Smuzhiyun #define WM5100_ACCDET_BIAS_STARTTIME_WIDTH 4 /* ACCDET_BIAS_STARTTIME - [15:12] */ 1445*4882a593Smuzhiyun #define WM5100_ACCDET_RATE_MASK 0x0F00 /* ACCDET_RATE - [11:8] */ 1446*4882a593Smuzhiyun #define WM5100_ACCDET_RATE_SHIFT 8 /* ACCDET_RATE - [11:8] */ 1447*4882a593Smuzhiyun #define WM5100_ACCDET_RATE_WIDTH 4 /* ACCDET_RATE - [11:8] */ 1448*4882a593Smuzhiyun #define WM5100_ACCDET_DBTIME 0x0002 /* ACCDET_DBTIME */ 1449*4882a593Smuzhiyun #define WM5100_ACCDET_DBTIME_MASK 0x0002 /* ACCDET_DBTIME */ 1450*4882a593Smuzhiyun #define WM5100_ACCDET_DBTIME_SHIFT 1 /* ACCDET_DBTIME */ 1451*4882a593Smuzhiyun #define WM5100_ACCDET_DBTIME_WIDTH 1 /* ACCDET_DBTIME */ 1452*4882a593Smuzhiyun #define WM5100_ACCDET_ENA 0x0001 /* ACCDET_ENA */ 1453*4882a593Smuzhiyun #define WM5100_ACCDET_ENA_MASK 0x0001 /* ACCDET_ENA */ 1454*4882a593Smuzhiyun #define WM5100_ACCDET_ENA_SHIFT 0 /* ACCDET_ENA */ 1455*4882a593Smuzhiyun #define WM5100_ACCDET_ENA_WIDTH 1 /* ACCDET_ENA */ 1456*4882a593Smuzhiyun 1457*4882a593Smuzhiyun /* 1458*4882a593Smuzhiyun * R657 (0x291) - Mic Detect 2 1459*4882a593Smuzhiyun */ 1460*4882a593Smuzhiyun #define WM5100_ACCDET_LVL_SEL_MASK 0x00FF /* ACCDET_LVL_SEL - [7:0] */ 1461*4882a593Smuzhiyun #define WM5100_ACCDET_LVL_SEL_SHIFT 0 /* ACCDET_LVL_SEL - [7:0] */ 1462*4882a593Smuzhiyun #define WM5100_ACCDET_LVL_SEL_WIDTH 8 /* ACCDET_LVL_SEL - [7:0] */ 1463*4882a593Smuzhiyun 1464*4882a593Smuzhiyun /* 1465*4882a593Smuzhiyun * R658 (0x292) - Mic Detect 3 1466*4882a593Smuzhiyun */ 1467*4882a593Smuzhiyun #define WM5100_ACCDET_LVL_MASK 0x07FC /* ACCDET_LVL - [10:2] */ 1468*4882a593Smuzhiyun #define WM5100_ACCDET_LVL_SHIFT 2 /* ACCDET_LVL - [10:2] */ 1469*4882a593Smuzhiyun #define WM5100_ACCDET_LVL_WIDTH 9 /* ACCDET_LVL - [10:2] */ 1470*4882a593Smuzhiyun #define WM5100_ACCDET_VALID 0x0002 /* ACCDET_VALID */ 1471*4882a593Smuzhiyun #define WM5100_ACCDET_VALID_MASK 0x0002 /* ACCDET_VALID */ 1472*4882a593Smuzhiyun #define WM5100_ACCDET_VALID_SHIFT 1 /* ACCDET_VALID */ 1473*4882a593Smuzhiyun #define WM5100_ACCDET_VALID_WIDTH 1 /* ACCDET_VALID */ 1474*4882a593Smuzhiyun #define WM5100_ACCDET_STS 0x0001 /* ACCDET_STS */ 1475*4882a593Smuzhiyun #define WM5100_ACCDET_STS_MASK 0x0001 /* ACCDET_STS */ 1476*4882a593Smuzhiyun #define WM5100_ACCDET_STS_SHIFT 0 /* ACCDET_STS */ 1477*4882a593Smuzhiyun #define WM5100_ACCDET_STS_WIDTH 1 /* ACCDET_STS */ 1478*4882a593Smuzhiyun 1479*4882a593Smuzhiyun /* 1480*4882a593Smuzhiyun * R699 (0x2BB) - Misc Control 1481*4882a593Smuzhiyun */ 1482*4882a593Smuzhiyun #define WM5100_HPCOM_SRC 0x200 /* HPCOM_SRC */ 1483*4882a593Smuzhiyun #define WM5100_HPCOM_SRC_SHIFT 9 /* HPCOM_SRC */ 1484*4882a593Smuzhiyun 1485*4882a593Smuzhiyun /* 1486*4882a593Smuzhiyun * R769 (0x301) - Input Enables 1487*4882a593Smuzhiyun */ 1488*4882a593Smuzhiyun #define WM5100_IN4L_ENA 0x0080 /* IN4L_ENA */ 1489*4882a593Smuzhiyun #define WM5100_IN4L_ENA_MASK 0x0080 /* IN4L_ENA */ 1490*4882a593Smuzhiyun #define WM5100_IN4L_ENA_SHIFT 7 /* IN4L_ENA */ 1491*4882a593Smuzhiyun #define WM5100_IN4L_ENA_WIDTH 1 /* IN4L_ENA */ 1492*4882a593Smuzhiyun #define WM5100_IN4R_ENA 0x0040 /* IN4R_ENA */ 1493*4882a593Smuzhiyun #define WM5100_IN4R_ENA_MASK 0x0040 /* IN4R_ENA */ 1494*4882a593Smuzhiyun #define WM5100_IN4R_ENA_SHIFT 6 /* IN4R_ENA */ 1495*4882a593Smuzhiyun #define WM5100_IN4R_ENA_WIDTH 1 /* IN4R_ENA */ 1496*4882a593Smuzhiyun #define WM5100_IN3L_ENA 0x0020 /* IN3L_ENA */ 1497*4882a593Smuzhiyun #define WM5100_IN3L_ENA_MASK 0x0020 /* IN3L_ENA */ 1498*4882a593Smuzhiyun #define WM5100_IN3L_ENA_SHIFT 5 /* IN3L_ENA */ 1499*4882a593Smuzhiyun #define WM5100_IN3L_ENA_WIDTH 1 /* IN3L_ENA */ 1500*4882a593Smuzhiyun #define WM5100_IN3R_ENA 0x0010 /* IN3R_ENA */ 1501*4882a593Smuzhiyun #define WM5100_IN3R_ENA_MASK 0x0010 /* IN3R_ENA */ 1502*4882a593Smuzhiyun #define WM5100_IN3R_ENA_SHIFT 4 /* IN3R_ENA */ 1503*4882a593Smuzhiyun #define WM5100_IN3R_ENA_WIDTH 1 /* IN3R_ENA */ 1504*4882a593Smuzhiyun #define WM5100_IN2L_ENA 0x0008 /* IN2L_ENA */ 1505*4882a593Smuzhiyun #define WM5100_IN2L_ENA_MASK 0x0008 /* IN2L_ENA */ 1506*4882a593Smuzhiyun #define WM5100_IN2L_ENA_SHIFT 3 /* IN2L_ENA */ 1507*4882a593Smuzhiyun #define WM5100_IN2L_ENA_WIDTH 1 /* IN2L_ENA */ 1508*4882a593Smuzhiyun #define WM5100_IN2R_ENA 0x0004 /* IN2R_ENA */ 1509*4882a593Smuzhiyun #define WM5100_IN2R_ENA_MASK 0x0004 /* IN2R_ENA */ 1510*4882a593Smuzhiyun #define WM5100_IN2R_ENA_SHIFT 2 /* IN2R_ENA */ 1511*4882a593Smuzhiyun #define WM5100_IN2R_ENA_WIDTH 1 /* IN2R_ENA */ 1512*4882a593Smuzhiyun #define WM5100_IN1L_ENA 0x0002 /* IN1L_ENA */ 1513*4882a593Smuzhiyun #define WM5100_IN1L_ENA_MASK 0x0002 /* IN1L_ENA */ 1514*4882a593Smuzhiyun #define WM5100_IN1L_ENA_SHIFT 1 /* IN1L_ENA */ 1515*4882a593Smuzhiyun #define WM5100_IN1L_ENA_WIDTH 1 /* IN1L_ENA */ 1516*4882a593Smuzhiyun #define WM5100_IN1R_ENA 0x0001 /* IN1R_ENA */ 1517*4882a593Smuzhiyun #define WM5100_IN1R_ENA_MASK 0x0001 /* IN1R_ENA */ 1518*4882a593Smuzhiyun #define WM5100_IN1R_ENA_SHIFT 0 /* IN1R_ENA */ 1519*4882a593Smuzhiyun #define WM5100_IN1R_ENA_WIDTH 1 /* IN1R_ENA */ 1520*4882a593Smuzhiyun 1521*4882a593Smuzhiyun /* 1522*4882a593Smuzhiyun * R770 (0x302) - Input Enables Status 1523*4882a593Smuzhiyun */ 1524*4882a593Smuzhiyun #define WM5100_IN4L_ENA_STS 0x0080 /* IN4L_ENA_STS */ 1525*4882a593Smuzhiyun #define WM5100_IN4L_ENA_STS_MASK 0x0080 /* IN4L_ENA_STS */ 1526*4882a593Smuzhiyun #define WM5100_IN4L_ENA_STS_SHIFT 7 /* IN4L_ENA_STS */ 1527*4882a593Smuzhiyun #define WM5100_IN4L_ENA_STS_WIDTH 1 /* IN4L_ENA_STS */ 1528*4882a593Smuzhiyun #define WM5100_IN4R_ENA_STS 0x0040 /* IN4R_ENA_STS */ 1529*4882a593Smuzhiyun #define WM5100_IN4R_ENA_STS_MASK 0x0040 /* IN4R_ENA_STS */ 1530*4882a593Smuzhiyun #define WM5100_IN4R_ENA_STS_SHIFT 6 /* IN4R_ENA_STS */ 1531*4882a593Smuzhiyun #define WM5100_IN4R_ENA_STS_WIDTH 1 /* IN4R_ENA_STS */ 1532*4882a593Smuzhiyun #define WM5100_IN3L_ENA_STS 0x0020 /* IN3L_ENA_STS */ 1533*4882a593Smuzhiyun #define WM5100_IN3L_ENA_STS_MASK 0x0020 /* IN3L_ENA_STS */ 1534*4882a593Smuzhiyun #define WM5100_IN3L_ENA_STS_SHIFT 5 /* IN3L_ENA_STS */ 1535*4882a593Smuzhiyun #define WM5100_IN3L_ENA_STS_WIDTH 1 /* IN3L_ENA_STS */ 1536*4882a593Smuzhiyun #define WM5100_IN3R_ENA_STS 0x0010 /* IN3R_ENA_STS */ 1537*4882a593Smuzhiyun #define WM5100_IN3R_ENA_STS_MASK 0x0010 /* IN3R_ENA_STS */ 1538*4882a593Smuzhiyun #define WM5100_IN3R_ENA_STS_SHIFT 4 /* IN3R_ENA_STS */ 1539*4882a593Smuzhiyun #define WM5100_IN3R_ENA_STS_WIDTH 1 /* IN3R_ENA_STS */ 1540*4882a593Smuzhiyun #define WM5100_IN2L_ENA_STS 0x0008 /* IN2L_ENA_STS */ 1541*4882a593Smuzhiyun #define WM5100_IN2L_ENA_STS_MASK 0x0008 /* IN2L_ENA_STS */ 1542*4882a593Smuzhiyun #define WM5100_IN2L_ENA_STS_SHIFT 3 /* IN2L_ENA_STS */ 1543*4882a593Smuzhiyun #define WM5100_IN2L_ENA_STS_WIDTH 1 /* IN2L_ENA_STS */ 1544*4882a593Smuzhiyun #define WM5100_IN2R_ENA_STS 0x0004 /* IN2R_ENA_STS */ 1545*4882a593Smuzhiyun #define WM5100_IN2R_ENA_STS_MASK 0x0004 /* IN2R_ENA_STS */ 1546*4882a593Smuzhiyun #define WM5100_IN2R_ENA_STS_SHIFT 2 /* IN2R_ENA_STS */ 1547*4882a593Smuzhiyun #define WM5100_IN2R_ENA_STS_WIDTH 1 /* IN2R_ENA_STS */ 1548*4882a593Smuzhiyun #define WM5100_IN1L_ENA_STS 0x0002 /* IN1L_ENA_STS */ 1549*4882a593Smuzhiyun #define WM5100_IN1L_ENA_STS_MASK 0x0002 /* IN1L_ENA_STS */ 1550*4882a593Smuzhiyun #define WM5100_IN1L_ENA_STS_SHIFT 1 /* IN1L_ENA_STS */ 1551*4882a593Smuzhiyun #define WM5100_IN1L_ENA_STS_WIDTH 1 /* IN1L_ENA_STS */ 1552*4882a593Smuzhiyun #define WM5100_IN1R_ENA_STS 0x0001 /* IN1R_ENA_STS */ 1553*4882a593Smuzhiyun #define WM5100_IN1R_ENA_STS_MASK 0x0001 /* IN1R_ENA_STS */ 1554*4882a593Smuzhiyun #define WM5100_IN1R_ENA_STS_SHIFT 0 /* IN1R_ENA_STS */ 1555*4882a593Smuzhiyun #define WM5100_IN1R_ENA_STS_WIDTH 1 /* IN1R_ENA_STS */ 1556*4882a593Smuzhiyun 1557*4882a593Smuzhiyun /* 1558*4882a593Smuzhiyun * R784 (0x310) - IN1L Control 1559*4882a593Smuzhiyun */ 1560*4882a593Smuzhiyun #define WM5100_IN_RATE_MASK 0xC000 /* IN_RATE - [15:14] */ 1561*4882a593Smuzhiyun #define WM5100_IN_RATE_SHIFT 14 /* IN_RATE - [15:14] */ 1562*4882a593Smuzhiyun #define WM5100_IN_RATE_WIDTH 2 /* IN_RATE - [15:14] */ 1563*4882a593Smuzhiyun #define WM5100_IN1_OSR 0x2000 /* IN1_OSR */ 1564*4882a593Smuzhiyun #define WM5100_IN1_OSR_MASK 0x2000 /* IN1_OSR */ 1565*4882a593Smuzhiyun #define WM5100_IN1_OSR_SHIFT 13 /* IN1_OSR */ 1566*4882a593Smuzhiyun #define WM5100_IN1_OSR_WIDTH 1 /* IN1_OSR */ 1567*4882a593Smuzhiyun #define WM5100_IN1_DMIC_SUP_MASK 0x1800 /* IN1_DMIC_SUP - [12:11] */ 1568*4882a593Smuzhiyun #define WM5100_IN1_DMIC_SUP_SHIFT 11 /* IN1_DMIC_SUP - [12:11] */ 1569*4882a593Smuzhiyun #define WM5100_IN1_DMIC_SUP_WIDTH 2 /* IN1_DMIC_SUP - [12:11] */ 1570*4882a593Smuzhiyun #define WM5100_IN1_MODE_MASK 0x0600 /* IN1_MODE - [10:9] */ 1571*4882a593Smuzhiyun #define WM5100_IN1_MODE_SHIFT 9 /* IN1_MODE - [10:9] */ 1572*4882a593Smuzhiyun #define WM5100_IN1_MODE_WIDTH 2 /* IN1_MODE - [10:9] */ 1573*4882a593Smuzhiyun #define WM5100_IN1L_PGA_VOL_MASK 0x00FE /* IN1L_PGA_VOL - [7:1] */ 1574*4882a593Smuzhiyun #define WM5100_IN1L_PGA_VOL_SHIFT 1 /* IN1L_PGA_VOL - [7:1] */ 1575*4882a593Smuzhiyun #define WM5100_IN1L_PGA_VOL_WIDTH 7 /* IN1L_PGA_VOL - [7:1] */ 1576*4882a593Smuzhiyun 1577*4882a593Smuzhiyun /* 1578*4882a593Smuzhiyun * R785 (0x311) - IN1R Control 1579*4882a593Smuzhiyun */ 1580*4882a593Smuzhiyun #define WM5100_IN1R_PGA_VOL_MASK 0x00FE /* IN1R_PGA_VOL - [7:1] */ 1581*4882a593Smuzhiyun #define WM5100_IN1R_PGA_VOL_SHIFT 1 /* IN1R_PGA_VOL - [7:1] */ 1582*4882a593Smuzhiyun #define WM5100_IN1R_PGA_VOL_WIDTH 7 /* IN1R_PGA_VOL - [7:1] */ 1583*4882a593Smuzhiyun 1584*4882a593Smuzhiyun /* 1585*4882a593Smuzhiyun * R786 (0x312) - IN2L Control 1586*4882a593Smuzhiyun */ 1587*4882a593Smuzhiyun #define WM5100_IN2_OSR 0x2000 /* IN2_OSR */ 1588*4882a593Smuzhiyun #define WM5100_IN2_OSR_MASK 0x2000 /* IN2_OSR */ 1589*4882a593Smuzhiyun #define WM5100_IN2_OSR_SHIFT 13 /* IN2_OSR */ 1590*4882a593Smuzhiyun #define WM5100_IN2_OSR_WIDTH 1 /* IN2_OSR */ 1591*4882a593Smuzhiyun #define WM5100_IN2_DMIC_SUP_MASK 0x1800 /* IN2_DMIC_SUP - [12:11] */ 1592*4882a593Smuzhiyun #define WM5100_IN2_DMIC_SUP_SHIFT 11 /* IN2_DMIC_SUP - [12:11] */ 1593*4882a593Smuzhiyun #define WM5100_IN2_DMIC_SUP_WIDTH 2 /* IN2_DMIC_SUP - [12:11] */ 1594*4882a593Smuzhiyun #define WM5100_IN2_MODE_MASK 0x0600 /* IN2_MODE - [10:9] */ 1595*4882a593Smuzhiyun #define WM5100_IN2_MODE_SHIFT 9 /* IN2_MODE - [10:9] */ 1596*4882a593Smuzhiyun #define WM5100_IN2_MODE_WIDTH 2 /* IN2_MODE - [10:9] */ 1597*4882a593Smuzhiyun #define WM5100_IN2L_PGA_VOL_MASK 0x00FE /* IN2L_PGA_VOL - [7:1] */ 1598*4882a593Smuzhiyun #define WM5100_IN2L_PGA_VOL_SHIFT 1 /* IN2L_PGA_VOL - [7:1] */ 1599*4882a593Smuzhiyun #define WM5100_IN2L_PGA_VOL_WIDTH 7 /* IN2L_PGA_VOL - [7:1] */ 1600*4882a593Smuzhiyun 1601*4882a593Smuzhiyun /* 1602*4882a593Smuzhiyun * R787 (0x313) - IN2R Control 1603*4882a593Smuzhiyun */ 1604*4882a593Smuzhiyun #define WM5100_IN2R_PGA_VOL_MASK 0x00FE /* IN2R_PGA_VOL - [7:1] */ 1605*4882a593Smuzhiyun #define WM5100_IN2R_PGA_VOL_SHIFT 1 /* IN2R_PGA_VOL - [7:1] */ 1606*4882a593Smuzhiyun #define WM5100_IN2R_PGA_VOL_WIDTH 7 /* IN2R_PGA_VOL - [7:1] */ 1607*4882a593Smuzhiyun 1608*4882a593Smuzhiyun /* 1609*4882a593Smuzhiyun * R788 (0x314) - IN3L Control 1610*4882a593Smuzhiyun */ 1611*4882a593Smuzhiyun #define WM5100_IN3_OSR 0x2000 /* IN3_OSR */ 1612*4882a593Smuzhiyun #define WM5100_IN3_OSR_MASK 0x2000 /* IN3_OSR */ 1613*4882a593Smuzhiyun #define WM5100_IN3_OSR_SHIFT 13 /* IN3_OSR */ 1614*4882a593Smuzhiyun #define WM5100_IN3_OSR_WIDTH 1 /* IN3_OSR */ 1615*4882a593Smuzhiyun #define WM5100_IN3_DMIC_SUP_MASK 0x1800 /* IN3_DMIC_SUP - [12:11] */ 1616*4882a593Smuzhiyun #define WM5100_IN3_DMIC_SUP_SHIFT 11 /* IN3_DMIC_SUP - [12:11] */ 1617*4882a593Smuzhiyun #define WM5100_IN3_DMIC_SUP_WIDTH 2 /* IN3_DMIC_SUP - [12:11] */ 1618*4882a593Smuzhiyun #define WM5100_IN3_MODE_MASK 0x0600 /* IN3_MODE - [10:9] */ 1619*4882a593Smuzhiyun #define WM5100_IN3_MODE_SHIFT 9 /* IN3_MODE - [10:9] */ 1620*4882a593Smuzhiyun #define WM5100_IN3_MODE_WIDTH 2 /* IN3_MODE - [10:9] */ 1621*4882a593Smuzhiyun #define WM5100_IN3L_PGA_VOL_MASK 0x00FE /* IN3L_PGA_VOL - [7:1] */ 1622*4882a593Smuzhiyun #define WM5100_IN3L_PGA_VOL_SHIFT 1 /* IN3L_PGA_VOL - [7:1] */ 1623*4882a593Smuzhiyun #define WM5100_IN3L_PGA_VOL_WIDTH 7 /* IN3L_PGA_VOL - [7:1] */ 1624*4882a593Smuzhiyun 1625*4882a593Smuzhiyun /* 1626*4882a593Smuzhiyun * R789 (0x315) - IN3R Control 1627*4882a593Smuzhiyun */ 1628*4882a593Smuzhiyun #define WM5100_IN3R_PGA_VOL_MASK 0x00FE /* IN3R_PGA_VOL - [7:1] */ 1629*4882a593Smuzhiyun #define WM5100_IN3R_PGA_VOL_SHIFT 1 /* IN3R_PGA_VOL - [7:1] */ 1630*4882a593Smuzhiyun #define WM5100_IN3R_PGA_VOL_WIDTH 7 /* IN3R_PGA_VOL - [7:1] */ 1631*4882a593Smuzhiyun 1632*4882a593Smuzhiyun /* 1633*4882a593Smuzhiyun * R790 (0x316) - IN4L Control 1634*4882a593Smuzhiyun */ 1635*4882a593Smuzhiyun #define WM5100_IN4_OSR 0x2000 /* IN4_OSR */ 1636*4882a593Smuzhiyun #define WM5100_IN4_OSR_MASK 0x2000 /* IN4_OSR */ 1637*4882a593Smuzhiyun #define WM5100_IN4_OSR_SHIFT 13 /* IN4_OSR */ 1638*4882a593Smuzhiyun #define WM5100_IN4_OSR_WIDTH 1 /* IN4_OSR */ 1639*4882a593Smuzhiyun #define WM5100_IN4_DMIC_SUP_MASK 0x1800 /* IN4_DMIC_SUP - [12:11] */ 1640*4882a593Smuzhiyun #define WM5100_IN4_DMIC_SUP_SHIFT 11 /* IN4_DMIC_SUP - [12:11] */ 1641*4882a593Smuzhiyun #define WM5100_IN4_DMIC_SUP_WIDTH 2 /* IN4_DMIC_SUP - [12:11] */ 1642*4882a593Smuzhiyun #define WM5100_IN4_MODE_MASK 0x0600 /* IN4_MODE - [10:9] */ 1643*4882a593Smuzhiyun #define WM5100_IN4_MODE_SHIFT 9 /* IN4_MODE - [10:9] */ 1644*4882a593Smuzhiyun #define WM5100_IN4_MODE_WIDTH 2 /* IN4_MODE - [10:9] */ 1645*4882a593Smuzhiyun #define WM5100_IN4L_PGA_VOL_MASK 0x00FE /* IN4L_PGA_VOL - [7:1] */ 1646*4882a593Smuzhiyun #define WM5100_IN4L_PGA_VOL_SHIFT 1 /* IN4L_PGA_VOL - [7:1] */ 1647*4882a593Smuzhiyun #define WM5100_IN4L_PGA_VOL_WIDTH 7 /* IN4L_PGA_VOL - [7:1] */ 1648*4882a593Smuzhiyun 1649*4882a593Smuzhiyun /* 1650*4882a593Smuzhiyun * R791 (0x317) - IN4R Control 1651*4882a593Smuzhiyun */ 1652*4882a593Smuzhiyun #define WM5100_IN4R_PGA_VOL_MASK 0x00FE /* IN4R_PGA_VOL - [7:1] */ 1653*4882a593Smuzhiyun #define WM5100_IN4R_PGA_VOL_SHIFT 1 /* IN4R_PGA_VOL - [7:1] */ 1654*4882a593Smuzhiyun #define WM5100_IN4R_PGA_VOL_WIDTH 7 /* IN4R_PGA_VOL - [7:1] */ 1655*4882a593Smuzhiyun 1656*4882a593Smuzhiyun /* 1657*4882a593Smuzhiyun * R792 (0x318) - RXANC_SRC 1658*4882a593Smuzhiyun */ 1659*4882a593Smuzhiyun #define WM5100_IN_RXANC_SEL_MASK 0x0007 /* IN_RXANC_SEL - [2:0] */ 1660*4882a593Smuzhiyun #define WM5100_IN_RXANC_SEL_SHIFT 0 /* IN_RXANC_SEL - [2:0] */ 1661*4882a593Smuzhiyun #define WM5100_IN_RXANC_SEL_WIDTH 3 /* IN_RXANC_SEL - [2:0] */ 1662*4882a593Smuzhiyun 1663*4882a593Smuzhiyun /* 1664*4882a593Smuzhiyun * R793 (0x319) - Input Volume Ramp 1665*4882a593Smuzhiyun */ 1666*4882a593Smuzhiyun #define WM5100_IN_VD_RAMP_MASK 0x0070 /* IN_VD_RAMP - [6:4] */ 1667*4882a593Smuzhiyun #define WM5100_IN_VD_RAMP_SHIFT 4 /* IN_VD_RAMP - [6:4] */ 1668*4882a593Smuzhiyun #define WM5100_IN_VD_RAMP_WIDTH 3 /* IN_VD_RAMP - [6:4] */ 1669*4882a593Smuzhiyun #define WM5100_IN_VI_RAMP_MASK 0x0007 /* IN_VI_RAMP - [2:0] */ 1670*4882a593Smuzhiyun #define WM5100_IN_VI_RAMP_SHIFT 0 /* IN_VI_RAMP - [2:0] */ 1671*4882a593Smuzhiyun #define WM5100_IN_VI_RAMP_WIDTH 3 /* IN_VI_RAMP - [2:0] */ 1672*4882a593Smuzhiyun 1673*4882a593Smuzhiyun /* 1674*4882a593Smuzhiyun * R800 (0x320) - ADC Digital Volume 1L 1675*4882a593Smuzhiyun */ 1676*4882a593Smuzhiyun #define WM5100_IN_VU 0x0200 /* IN_VU */ 1677*4882a593Smuzhiyun #define WM5100_IN_VU_MASK 0x0200 /* IN_VU */ 1678*4882a593Smuzhiyun #define WM5100_IN_VU_SHIFT 9 /* IN_VU */ 1679*4882a593Smuzhiyun #define WM5100_IN_VU_WIDTH 1 /* IN_VU */ 1680*4882a593Smuzhiyun #define WM5100_IN1L_MUTE 0x0100 /* IN1L_MUTE */ 1681*4882a593Smuzhiyun #define WM5100_IN1L_MUTE_MASK 0x0100 /* IN1L_MUTE */ 1682*4882a593Smuzhiyun #define WM5100_IN1L_MUTE_SHIFT 8 /* IN1L_MUTE */ 1683*4882a593Smuzhiyun #define WM5100_IN1L_MUTE_WIDTH 1 /* IN1L_MUTE */ 1684*4882a593Smuzhiyun #define WM5100_IN1L_VOL_MASK 0x00FF /* IN1L_VOL - [7:0] */ 1685*4882a593Smuzhiyun #define WM5100_IN1L_VOL_SHIFT 0 /* IN1L_VOL - [7:0] */ 1686*4882a593Smuzhiyun #define WM5100_IN1L_VOL_WIDTH 8 /* IN1L_VOL - [7:0] */ 1687*4882a593Smuzhiyun 1688*4882a593Smuzhiyun /* 1689*4882a593Smuzhiyun * R801 (0x321) - ADC Digital Volume 1R 1690*4882a593Smuzhiyun */ 1691*4882a593Smuzhiyun #define WM5100_IN_VU 0x0200 /* IN_VU */ 1692*4882a593Smuzhiyun #define WM5100_IN_VU_MASK 0x0200 /* IN_VU */ 1693*4882a593Smuzhiyun #define WM5100_IN_VU_SHIFT 9 /* IN_VU */ 1694*4882a593Smuzhiyun #define WM5100_IN_VU_WIDTH 1 /* IN_VU */ 1695*4882a593Smuzhiyun #define WM5100_IN1R_MUTE 0x0100 /* IN1R_MUTE */ 1696*4882a593Smuzhiyun #define WM5100_IN1R_MUTE_MASK 0x0100 /* IN1R_MUTE */ 1697*4882a593Smuzhiyun #define WM5100_IN1R_MUTE_SHIFT 8 /* IN1R_MUTE */ 1698*4882a593Smuzhiyun #define WM5100_IN1R_MUTE_WIDTH 1 /* IN1R_MUTE */ 1699*4882a593Smuzhiyun #define WM5100_IN1R_VOL_MASK 0x00FF /* IN1R_VOL - [7:0] */ 1700*4882a593Smuzhiyun #define WM5100_IN1R_VOL_SHIFT 0 /* IN1R_VOL - [7:0] */ 1701*4882a593Smuzhiyun #define WM5100_IN1R_VOL_WIDTH 8 /* IN1R_VOL - [7:0] */ 1702*4882a593Smuzhiyun 1703*4882a593Smuzhiyun /* 1704*4882a593Smuzhiyun * R802 (0x322) - ADC Digital Volume 2L 1705*4882a593Smuzhiyun */ 1706*4882a593Smuzhiyun #define WM5100_IN_VU 0x0200 /* IN_VU */ 1707*4882a593Smuzhiyun #define WM5100_IN_VU_MASK 0x0200 /* IN_VU */ 1708*4882a593Smuzhiyun #define WM5100_IN_VU_SHIFT 9 /* IN_VU */ 1709*4882a593Smuzhiyun #define WM5100_IN_VU_WIDTH 1 /* IN_VU */ 1710*4882a593Smuzhiyun #define WM5100_IN2L_MUTE 0x0100 /* IN2L_MUTE */ 1711*4882a593Smuzhiyun #define WM5100_IN2L_MUTE_MASK 0x0100 /* IN2L_MUTE */ 1712*4882a593Smuzhiyun #define WM5100_IN2L_MUTE_SHIFT 8 /* IN2L_MUTE */ 1713*4882a593Smuzhiyun #define WM5100_IN2L_MUTE_WIDTH 1 /* IN2L_MUTE */ 1714*4882a593Smuzhiyun #define WM5100_IN2L_VOL_MASK 0x00FF /* IN2L_VOL - [7:0] */ 1715*4882a593Smuzhiyun #define WM5100_IN2L_VOL_SHIFT 0 /* IN2L_VOL - [7:0] */ 1716*4882a593Smuzhiyun #define WM5100_IN2L_VOL_WIDTH 8 /* IN2L_VOL - [7:0] */ 1717*4882a593Smuzhiyun 1718*4882a593Smuzhiyun /* 1719*4882a593Smuzhiyun * R803 (0x323) - ADC Digital Volume 2R 1720*4882a593Smuzhiyun */ 1721*4882a593Smuzhiyun #define WM5100_IN_VU 0x0200 /* IN_VU */ 1722*4882a593Smuzhiyun #define WM5100_IN_VU_MASK 0x0200 /* IN_VU */ 1723*4882a593Smuzhiyun #define WM5100_IN_VU_SHIFT 9 /* IN_VU */ 1724*4882a593Smuzhiyun #define WM5100_IN_VU_WIDTH 1 /* IN_VU */ 1725*4882a593Smuzhiyun #define WM5100_IN2R_MUTE 0x0100 /* IN2R_MUTE */ 1726*4882a593Smuzhiyun #define WM5100_IN2R_MUTE_MASK 0x0100 /* IN2R_MUTE */ 1727*4882a593Smuzhiyun #define WM5100_IN2R_MUTE_SHIFT 8 /* IN2R_MUTE */ 1728*4882a593Smuzhiyun #define WM5100_IN2R_MUTE_WIDTH 1 /* IN2R_MUTE */ 1729*4882a593Smuzhiyun #define WM5100_IN2R_VOL_MASK 0x00FF /* IN2R_VOL - [7:0] */ 1730*4882a593Smuzhiyun #define WM5100_IN2R_VOL_SHIFT 0 /* IN2R_VOL - [7:0] */ 1731*4882a593Smuzhiyun #define WM5100_IN2R_VOL_WIDTH 8 /* IN2R_VOL - [7:0] */ 1732*4882a593Smuzhiyun 1733*4882a593Smuzhiyun /* 1734*4882a593Smuzhiyun * R804 (0x324) - ADC Digital Volume 3L 1735*4882a593Smuzhiyun */ 1736*4882a593Smuzhiyun #define WM5100_IN_VU 0x0200 /* IN_VU */ 1737*4882a593Smuzhiyun #define WM5100_IN_VU_MASK 0x0200 /* IN_VU */ 1738*4882a593Smuzhiyun #define WM5100_IN_VU_SHIFT 9 /* IN_VU */ 1739*4882a593Smuzhiyun #define WM5100_IN_VU_WIDTH 1 /* IN_VU */ 1740*4882a593Smuzhiyun #define WM5100_IN3L_MUTE 0x0100 /* IN3L_MUTE */ 1741*4882a593Smuzhiyun #define WM5100_IN3L_MUTE_MASK 0x0100 /* IN3L_MUTE */ 1742*4882a593Smuzhiyun #define WM5100_IN3L_MUTE_SHIFT 8 /* IN3L_MUTE */ 1743*4882a593Smuzhiyun #define WM5100_IN3L_MUTE_WIDTH 1 /* IN3L_MUTE */ 1744*4882a593Smuzhiyun #define WM5100_IN3L_VOL_MASK 0x00FF /* IN3L_VOL - [7:0] */ 1745*4882a593Smuzhiyun #define WM5100_IN3L_VOL_SHIFT 0 /* IN3L_VOL - [7:0] */ 1746*4882a593Smuzhiyun #define WM5100_IN3L_VOL_WIDTH 8 /* IN3L_VOL - [7:0] */ 1747*4882a593Smuzhiyun 1748*4882a593Smuzhiyun /* 1749*4882a593Smuzhiyun * R805 (0x325) - ADC Digital Volume 3R 1750*4882a593Smuzhiyun */ 1751*4882a593Smuzhiyun #define WM5100_IN_VU 0x0200 /* IN_VU */ 1752*4882a593Smuzhiyun #define WM5100_IN_VU_MASK 0x0200 /* IN_VU */ 1753*4882a593Smuzhiyun #define WM5100_IN_VU_SHIFT 9 /* IN_VU */ 1754*4882a593Smuzhiyun #define WM5100_IN_VU_WIDTH 1 /* IN_VU */ 1755*4882a593Smuzhiyun #define WM5100_IN3R_MUTE 0x0100 /* IN3R_MUTE */ 1756*4882a593Smuzhiyun #define WM5100_IN3R_MUTE_MASK 0x0100 /* IN3R_MUTE */ 1757*4882a593Smuzhiyun #define WM5100_IN3R_MUTE_SHIFT 8 /* IN3R_MUTE */ 1758*4882a593Smuzhiyun #define WM5100_IN3R_MUTE_WIDTH 1 /* IN3R_MUTE */ 1759*4882a593Smuzhiyun #define WM5100_IN3R_VOL_MASK 0x00FF /* IN3R_VOL - [7:0] */ 1760*4882a593Smuzhiyun #define WM5100_IN3R_VOL_SHIFT 0 /* IN3R_VOL - [7:0] */ 1761*4882a593Smuzhiyun #define WM5100_IN3R_VOL_WIDTH 8 /* IN3R_VOL - [7:0] */ 1762*4882a593Smuzhiyun 1763*4882a593Smuzhiyun /* 1764*4882a593Smuzhiyun * R806 (0x326) - ADC Digital Volume 4L 1765*4882a593Smuzhiyun */ 1766*4882a593Smuzhiyun #define WM5100_IN_VU 0x0200 /* IN_VU */ 1767*4882a593Smuzhiyun #define WM5100_IN_VU_MASK 0x0200 /* IN_VU */ 1768*4882a593Smuzhiyun #define WM5100_IN_VU_SHIFT 9 /* IN_VU */ 1769*4882a593Smuzhiyun #define WM5100_IN_VU_WIDTH 1 /* IN_VU */ 1770*4882a593Smuzhiyun #define WM5100_IN4L_MUTE 0x0100 /* IN4L_MUTE */ 1771*4882a593Smuzhiyun #define WM5100_IN4L_MUTE_MASK 0x0100 /* IN4L_MUTE */ 1772*4882a593Smuzhiyun #define WM5100_IN4L_MUTE_SHIFT 8 /* IN4L_MUTE */ 1773*4882a593Smuzhiyun #define WM5100_IN4L_MUTE_WIDTH 1 /* IN4L_MUTE */ 1774*4882a593Smuzhiyun #define WM5100_IN4L_VOL_MASK 0x00FF /* IN4L_VOL - [7:0] */ 1775*4882a593Smuzhiyun #define WM5100_IN4L_VOL_SHIFT 0 /* IN4L_VOL - [7:0] */ 1776*4882a593Smuzhiyun #define WM5100_IN4L_VOL_WIDTH 8 /* IN4L_VOL - [7:0] */ 1777*4882a593Smuzhiyun 1778*4882a593Smuzhiyun /* 1779*4882a593Smuzhiyun * R807 (0x327) - ADC Digital Volume 4R 1780*4882a593Smuzhiyun */ 1781*4882a593Smuzhiyun #define WM5100_IN_VU 0x0200 /* IN_VU */ 1782*4882a593Smuzhiyun #define WM5100_IN_VU_MASK 0x0200 /* IN_VU */ 1783*4882a593Smuzhiyun #define WM5100_IN_VU_SHIFT 9 /* IN_VU */ 1784*4882a593Smuzhiyun #define WM5100_IN_VU_WIDTH 1 /* IN_VU */ 1785*4882a593Smuzhiyun #define WM5100_IN4R_MUTE 0x0100 /* IN4R_MUTE */ 1786*4882a593Smuzhiyun #define WM5100_IN4R_MUTE_MASK 0x0100 /* IN4R_MUTE */ 1787*4882a593Smuzhiyun #define WM5100_IN4R_MUTE_SHIFT 8 /* IN4R_MUTE */ 1788*4882a593Smuzhiyun #define WM5100_IN4R_MUTE_WIDTH 1 /* IN4R_MUTE */ 1789*4882a593Smuzhiyun #define WM5100_IN4R_VOL_MASK 0x00FF /* IN4R_VOL - [7:0] */ 1790*4882a593Smuzhiyun #define WM5100_IN4R_VOL_SHIFT 0 /* IN4R_VOL - [7:0] */ 1791*4882a593Smuzhiyun #define WM5100_IN4R_VOL_WIDTH 8 /* IN4R_VOL - [7:0] */ 1792*4882a593Smuzhiyun 1793*4882a593Smuzhiyun /* 1794*4882a593Smuzhiyun * R1025 (0x401) - Output Enables 2 1795*4882a593Smuzhiyun */ 1796*4882a593Smuzhiyun #define WM5100_OUT6L_ENA 0x0800 /* OUT6L_ENA */ 1797*4882a593Smuzhiyun #define WM5100_OUT6L_ENA_MASK 0x0800 /* OUT6L_ENA */ 1798*4882a593Smuzhiyun #define WM5100_OUT6L_ENA_SHIFT 11 /* OUT6L_ENA */ 1799*4882a593Smuzhiyun #define WM5100_OUT6L_ENA_WIDTH 1 /* OUT6L_ENA */ 1800*4882a593Smuzhiyun #define WM5100_OUT6R_ENA 0x0400 /* OUT6R_ENA */ 1801*4882a593Smuzhiyun #define WM5100_OUT6R_ENA_MASK 0x0400 /* OUT6R_ENA */ 1802*4882a593Smuzhiyun #define WM5100_OUT6R_ENA_SHIFT 10 /* OUT6R_ENA */ 1803*4882a593Smuzhiyun #define WM5100_OUT6R_ENA_WIDTH 1 /* OUT6R_ENA */ 1804*4882a593Smuzhiyun #define WM5100_OUT5L_ENA 0x0200 /* OUT5L_ENA */ 1805*4882a593Smuzhiyun #define WM5100_OUT5L_ENA_MASK 0x0200 /* OUT5L_ENA */ 1806*4882a593Smuzhiyun #define WM5100_OUT5L_ENA_SHIFT 9 /* OUT5L_ENA */ 1807*4882a593Smuzhiyun #define WM5100_OUT5L_ENA_WIDTH 1 /* OUT5L_ENA */ 1808*4882a593Smuzhiyun #define WM5100_OUT5R_ENA 0x0100 /* OUT5R_ENA */ 1809*4882a593Smuzhiyun #define WM5100_OUT5R_ENA_MASK 0x0100 /* OUT5R_ENA */ 1810*4882a593Smuzhiyun #define WM5100_OUT5R_ENA_SHIFT 8 /* OUT5R_ENA */ 1811*4882a593Smuzhiyun #define WM5100_OUT5R_ENA_WIDTH 1 /* OUT5R_ENA */ 1812*4882a593Smuzhiyun #define WM5100_OUT4L_ENA 0x0080 /* OUT4L_ENA */ 1813*4882a593Smuzhiyun #define WM5100_OUT4L_ENA_MASK 0x0080 /* OUT4L_ENA */ 1814*4882a593Smuzhiyun #define WM5100_OUT4L_ENA_SHIFT 7 /* OUT4L_ENA */ 1815*4882a593Smuzhiyun #define WM5100_OUT4L_ENA_WIDTH 1 /* OUT4L_ENA */ 1816*4882a593Smuzhiyun #define WM5100_OUT4R_ENA 0x0040 /* OUT4R_ENA */ 1817*4882a593Smuzhiyun #define WM5100_OUT4R_ENA_MASK 0x0040 /* OUT4R_ENA */ 1818*4882a593Smuzhiyun #define WM5100_OUT4R_ENA_SHIFT 6 /* OUT4R_ENA */ 1819*4882a593Smuzhiyun #define WM5100_OUT4R_ENA_WIDTH 1 /* OUT4R_ENA */ 1820*4882a593Smuzhiyun 1821*4882a593Smuzhiyun /* 1822*4882a593Smuzhiyun * R1026 (0x402) - Output Status 1 1823*4882a593Smuzhiyun */ 1824*4882a593Smuzhiyun #define WM5100_OUT3L_ENA_STS 0x0020 /* OUT3L_ENA_STS */ 1825*4882a593Smuzhiyun #define WM5100_OUT3L_ENA_STS_MASK 0x0020 /* OUT3L_ENA_STS */ 1826*4882a593Smuzhiyun #define WM5100_OUT3L_ENA_STS_SHIFT 5 /* OUT3L_ENA_STS */ 1827*4882a593Smuzhiyun #define WM5100_OUT3L_ENA_STS_WIDTH 1 /* OUT3L_ENA_STS */ 1828*4882a593Smuzhiyun #define WM5100_OUT3R_ENA_STS 0x0010 /* OUT3R_ENA_STS */ 1829*4882a593Smuzhiyun #define WM5100_OUT3R_ENA_STS_MASK 0x0010 /* OUT3R_ENA_STS */ 1830*4882a593Smuzhiyun #define WM5100_OUT3R_ENA_STS_SHIFT 4 /* OUT3R_ENA_STS */ 1831*4882a593Smuzhiyun #define WM5100_OUT3R_ENA_STS_WIDTH 1 /* OUT3R_ENA_STS */ 1832*4882a593Smuzhiyun #define WM5100_OUT2L_ENA_STS 0x0008 /* OUT2L_ENA_STS */ 1833*4882a593Smuzhiyun #define WM5100_OUT2L_ENA_STS_MASK 0x0008 /* OUT2L_ENA_STS */ 1834*4882a593Smuzhiyun #define WM5100_OUT2L_ENA_STS_SHIFT 3 /* OUT2L_ENA_STS */ 1835*4882a593Smuzhiyun #define WM5100_OUT2L_ENA_STS_WIDTH 1 /* OUT2L_ENA_STS */ 1836*4882a593Smuzhiyun #define WM5100_OUT2R_ENA_STS 0x0004 /* OUT2R_ENA_STS */ 1837*4882a593Smuzhiyun #define WM5100_OUT2R_ENA_STS_MASK 0x0004 /* OUT2R_ENA_STS */ 1838*4882a593Smuzhiyun #define WM5100_OUT2R_ENA_STS_SHIFT 2 /* OUT2R_ENA_STS */ 1839*4882a593Smuzhiyun #define WM5100_OUT2R_ENA_STS_WIDTH 1 /* OUT2R_ENA_STS */ 1840*4882a593Smuzhiyun #define WM5100_OUT1L_ENA_STS 0x0002 /* OUT1L_ENA_STS */ 1841*4882a593Smuzhiyun #define WM5100_OUT1L_ENA_STS_MASK 0x0002 /* OUT1L_ENA_STS */ 1842*4882a593Smuzhiyun #define WM5100_OUT1L_ENA_STS_SHIFT 1 /* OUT1L_ENA_STS */ 1843*4882a593Smuzhiyun #define WM5100_OUT1L_ENA_STS_WIDTH 1 /* OUT1L_ENA_STS */ 1844*4882a593Smuzhiyun #define WM5100_OUT1R_ENA_STS 0x0001 /* OUT1R_ENA_STS */ 1845*4882a593Smuzhiyun #define WM5100_OUT1R_ENA_STS_MASK 0x0001 /* OUT1R_ENA_STS */ 1846*4882a593Smuzhiyun #define WM5100_OUT1R_ENA_STS_SHIFT 0 /* OUT1R_ENA_STS */ 1847*4882a593Smuzhiyun #define WM5100_OUT1R_ENA_STS_WIDTH 1 /* OUT1R_ENA_STS */ 1848*4882a593Smuzhiyun 1849*4882a593Smuzhiyun /* 1850*4882a593Smuzhiyun * R1027 (0x403) - Output Status 2 1851*4882a593Smuzhiyun */ 1852*4882a593Smuzhiyun #define WM5100_OUT6L_ENA_STS 0x0800 /* OUT6L_ENA_STS */ 1853*4882a593Smuzhiyun #define WM5100_OUT6L_ENA_STS_MASK 0x0800 /* OUT6L_ENA_STS */ 1854*4882a593Smuzhiyun #define WM5100_OUT6L_ENA_STS_SHIFT 11 /* OUT6L_ENA_STS */ 1855*4882a593Smuzhiyun #define WM5100_OUT6L_ENA_STS_WIDTH 1 /* OUT6L_ENA_STS */ 1856*4882a593Smuzhiyun #define WM5100_OUT6R_ENA_STS 0x0400 /* OUT6R_ENA_STS */ 1857*4882a593Smuzhiyun #define WM5100_OUT6R_ENA_STS_MASK 0x0400 /* OUT6R_ENA_STS */ 1858*4882a593Smuzhiyun #define WM5100_OUT6R_ENA_STS_SHIFT 10 /* OUT6R_ENA_STS */ 1859*4882a593Smuzhiyun #define WM5100_OUT6R_ENA_STS_WIDTH 1 /* OUT6R_ENA_STS */ 1860*4882a593Smuzhiyun #define WM5100_OUT5L_ENA_STS 0x0200 /* OUT5L_ENA_STS */ 1861*4882a593Smuzhiyun #define WM5100_OUT5L_ENA_STS_MASK 0x0200 /* OUT5L_ENA_STS */ 1862*4882a593Smuzhiyun #define WM5100_OUT5L_ENA_STS_SHIFT 9 /* OUT5L_ENA_STS */ 1863*4882a593Smuzhiyun #define WM5100_OUT5L_ENA_STS_WIDTH 1 /* OUT5L_ENA_STS */ 1864*4882a593Smuzhiyun #define WM5100_OUT5R_ENA_STS 0x0100 /* OUT5R_ENA_STS */ 1865*4882a593Smuzhiyun #define WM5100_OUT5R_ENA_STS_MASK 0x0100 /* OUT5R_ENA_STS */ 1866*4882a593Smuzhiyun #define WM5100_OUT5R_ENA_STS_SHIFT 8 /* OUT5R_ENA_STS */ 1867*4882a593Smuzhiyun #define WM5100_OUT5R_ENA_STS_WIDTH 1 /* OUT5R_ENA_STS */ 1868*4882a593Smuzhiyun #define WM5100_OUT4L_ENA_STS 0x0080 /* OUT4L_ENA_STS */ 1869*4882a593Smuzhiyun #define WM5100_OUT4L_ENA_STS_MASK 0x0080 /* OUT4L_ENA_STS */ 1870*4882a593Smuzhiyun #define WM5100_OUT4L_ENA_STS_SHIFT 7 /* OUT4L_ENA_STS */ 1871*4882a593Smuzhiyun #define WM5100_OUT4L_ENA_STS_WIDTH 1 /* OUT4L_ENA_STS */ 1872*4882a593Smuzhiyun #define WM5100_OUT4R_ENA_STS 0x0040 /* OUT4R_ENA_STS */ 1873*4882a593Smuzhiyun #define WM5100_OUT4R_ENA_STS_MASK 0x0040 /* OUT4R_ENA_STS */ 1874*4882a593Smuzhiyun #define WM5100_OUT4R_ENA_STS_SHIFT 6 /* OUT4R_ENA_STS */ 1875*4882a593Smuzhiyun #define WM5100_OUT4R_ENA_STS_WIDTH 1 /* OUT4R_ENA_STS */ 1876*4882a593Smuzhiyun 1877*4882a593Smuzhiyun /* 1878*4882a593Smuzhiyun * R1032 (0x408) - Channel Enables 1 1879*4882a593Smuzhiyun */ 1880*4882a593Smuzhiyun #define WM5100_HP3L_ENA 0x0020 /* HP3L_ENA */ 1881*4882a593Smuzhiyun #define WM5100_HP3L_ENA_MASK 0x0020 /* HP3L_ENA */ 1882*4882a593Smuzhiyun #define WM5100_HP3L_ENA_SHIFT 5 /* HP3L_ENA */ 1883*4882a593Smuzhiyun #define WM5100_HP3L_ENA_WIDTH 1 /* HP3L_ENA */ 1884*4882a593Smuzhiyun #define WM5100_HP3R_ENA 0x0010 /* HP3R_ENA */ 1885*4882a593Smuzhiyun #define WM5100_HP3R_ENA_MASK 0x0010 /* HP3R_ENA */ 1886*4882a593Smuzhiyun #define WM5100_HP3R_ENA_SHIFT 4 /* HP3R_ENA */ 1887*4882a593Smuzhiyun #define WM5100_HP3R_ENA_WIDTH 1 /* HP3R_ENA */ 1888*4882a593Smuzhiyun #define WM5100_HP2L_ENA 0x0008 /* HP2L_ENA */ 1889*4882a593Smuzhiyun #define WM5100_HP2L_ENA_MASK 0x0008 /* HP2L_ENA */ 1890*4882a593Smuzhiyun #define WM5100_HP2L_ENA_SHIFT 3 /* HP2L_ENA */ 1891*4882a593Smuzhiyun #define WM5100_HP2L_ENA_WIDTH 1 /* HP2L_ENA */ 1892*4882a593Smuzhiyun #define WM5100_HP2R_ENA 0x0004 /* HP2R_ENA */ 1893*4882a593Smuzhiyun #define WM5100_HP2R_ENA_MASK 0x0004 /* HP2R_ENA */ 1894*4882a593Smuzhiyun #define WM5100_HP2R_ENA_SHIFT 2 /* HP2R_ENA */ 1895*4882a593Smuzhiyun #define WM5100_HP2R_ENA_WIDTH 1 /* HP2R_ENA */ 1896*4882a593Smuzhiyun #define WM5100_HP1L_ENA 0x0002 /* HP1L_ENA */ 1897*4882a593Smuzhiyun #define WM5100_HP1L_ENA_MASK 0x0002 /* HP1L_ENA */ 1898*4882a593Smuzhiyun #define WM5100_HP1L_ENA_SHIFT 1 /* HP1L_ENA */ 1899*4882a593Smuzhiyun #define WM5100_HP1L_ENA_WIDTH 1 /* HP1L_ENA */ 1900*4882a593Smuzhiyun #define WM5100_HP1R_ENA 0x0001 /* HP1R_ENA */ 1901*4882a593Smuzhiyun #define WM5100_HP1R_ENA_MASK 0x0001 /* HP1R_ENA */ 1902*4882a593Smuzhiyun #define WM5100_HP1R_ENA_SHIFT 0 /* HP1R_ENA */ 1903*4882a593Smuzhiyun #define WM5100_HP1R_ENA_WIDTH 1 /* HP1R_ENA */ 1904*4882a593Smuzhiyun 1905*4882a593Smuzhiyun /* 1906*4882a593Smuzhiyun * R1040 (0x410) - Out Volume 1L 1907*4882a593Smuzhiyun */ 1908*4882a593Smuzhiyun #define WM5100_OUT_RATE_MASK 0xC000 /* OUT_RATE - [15:14] */ 1909*4882a593Smuzhiyun #define WM5100_OUT_RATE_SHIFT 14 /* OUT_RATE - [15:14] */ 1910*4882a593Smuzhiyun #define WM5100_OUT_RATE_WIDTH 2 /* OUT_RATE - [15:14] */ 1911*4882a593Smuzhiyun #define WM5100_OUT1_OSR 0x2000 /* OUT1_OSR */ 1912*4882a593Smuzhiyun #define WM5100_OUT1_OSR_MASK 0x2000 /* OUT1_OSR */ 1913*4882a593Smuzhiyun #define WM5100_OUT1_OSR_SHIFT 13 /* OUT1_OSR */ 1914*4882a593Smuzhiyun #define WM5100_OUT1_OSR_WIDTH 1 /* OUT1_OSR */ 1915*4882a593Smuzhiyun #define WM5100_OUT1_MONO 0x1000 /* OUT1_MONO */ 1916*4882a593Smuzhiyun #define WM5100_OUT1_MONO_MASK 0x1000 /* OUT1_MONO */ 1917*4882a593Smuzhiyun #define WM5100_OUT1_MONO_SHIFT 12 /* OUT1_MONO */ 1918*4882a593Smuzhiyun #define WM5100_OUT1_MONO_WIDTH 1 /* OUT1_MONO */ 1919*4882a593Smuzhiyun #define WM5100_OUT1L_ANC_SRC 0x0800 /* OUT1L_ANC_SRC */ 1920*4882a593Smuzhiyun #define WM5100_OUT1L_ANC_SRC_MASK 0x0800 /* OUT1L_ANC_SRC */ 1921*4882a593Smuzhiyun #define WM5100_OUT1L_ANC_SRC_SHIFT 11 /* OUT1L_ANC_SRC */ 1922*4882a593Smuzhiyun #define WM5100_OUT1L_ANC_SRC_WIDTH 1 /* OUT1L_ANC_SRC */ 1923*4882a593Smuzhiyun #define WM5100_OUT1L_PGA_VOL_MASK 0x00FE /* OUT1L_PGA_VOL - [7:1] */ 1924*4882a593Smuzhiyun #define WM5100_OUT1L_PGA_VOL_SHIFT 1 /* OUT1L_PGA_VOL - [7:1] */ 1925*4882a593Smuzhiyun #define WM5100_OUT1L_PGA_VOL_WIDTH 7 /* OUT1L_PGA_VOL - [7:1] */ 1926*4882a593Smuzhiyun 1927*4882a593Smuzhiyun /* 1928*4882a593Smuzhiyun * R1041 (0x411) - Out Volume 1R 1929*4882a593Smuzhiyun */ 1930*4882a593Smuzhiyun #define WM5100_OUT1R_ANC_SRC 0x0800 /* OUT1R_ANC_SRC */ 1931*4882a593Smuzhiyun #define WM5100_OUT1R_ANC_SRC_MASK 0x0800 /* OUT1R_ANC_SRC */ 1932*4882a593Smuzhiyun #define WM5100_OUT1R_ANC_SRC_SHIFT 11 /* OUT1R_ANC_SRC */ 1933*4882a593Smuzhiyun #define WM5100_OUT1R_ANC_SRC_WIDTH 1 /* OUT1R_ANC_SRC */ 1934*4882a593Smuzhiyun #define WM5100_OUT1R_PGA_VOL_MASK 0x00FE /* OUT1R_PGA_VOL - [7:1] */ 1935*4882a593Smuzhiyun #define WM5100_OUT1R_PGA_VOL_SHIFT 1 /* OUT1R_PGA_VOL - [7:1] */ 1936*4882a593Smuzhiyun #define WM5100_OUT1R_PGA_VOL_WIDTH 7 /* OUT1R_PGA_VOL - [7:1] */ 1937*4882a593Smuzhiyun 1938*4882a593Smuzhiyun /* 1939*4882a593Smuzhiyun * R1042 (0x412) - DAC Volume Limit 1L 1940*4882a593Smuzhiyun */ 1941*4882a593Smuzhiyun #define WM5100_OUT1L_VOL_LIM_MASK 0x00FF /* OUT1L_VOL_LIM - [7:0] */ 1942*4882a593Smuzhiyun #define WM5100_OUT1L_VOL_LIM_SHIFT 0 /* OUT1L_VOL_LIM - [7:0] */ 1943*4882a593Smuzhiyun #define WM5100_OUT1L_VOL_LIM_WIDTH 8 /* OUT1L_VOL_LIM - [7:0] */ 1944*4882a593Smuzhiyun 1945*4882a593Smuzhiyun /* 1946*4882a593Smuzhiyun * R1043 (0x413) - DAC Volume Limit 1R 1947*4882a593Smuzhiyun */ 1948*4882a593Smuzhiyun #define WM5100_OUT1R_VOL_LIM_MASK 0x00FF /* OUT1R_VOL_LIM - [7:0] */ 1949*4882a593Smuzhiyun #define WM5100_OUT1R_VOL_LIM_SHIFT 0 /* OUT1R_VOL_LIM - [7:0] */ 1950*4882a593Smuzhiyun #define WM5100_OUT1R_VOL_LIM_WIDTH 8 /* OUT1R_VOL_LIM - [7:0] */ 1951*4882a593Smuzhiyun 1952*4882a593Smuzhiyun /* 1953*4882a593Smuzhiyun * R1044 (0x414) - Out Volume 2L 1954*4882a593Smuzhiyun */ 1955*4882a593Smuzhiyun #define WM5100_OUT2_OSR 0x2000 /* OUT2_OSR */ 1956*4882a593Smuzhiyun #define WM5100_OUT2_OSR_MASK 0x2000 /* OUT2_OSR */ 1957*4882a593Smuzhiyun #define WM5100_OUT2_OSR_SHIFT 13 /* OUT2_OSR */ 1958*4882a593Smuzhiyun #define WM5100_OUT2_OSR_WIDTH 1 /* OUT2_OSR */ 1959*4882a593Smuzhiyun #define WM5100_OUT2_MONO 0x1000 /* OUT2_MONO */ 1960*4882a593Smuzhiyun #define WM5100_OUT2_MONO_MASK 0x1000 /* OUT2_MONO */ 1961*4882a593Smuzhiyun #define WM5100_OUT2_MONO_SHIFT 12 /* OUT2_MONO */ 1962*4882a593Smuzhiyun #define WM5100_OUT2_MONO_WIDTH 1 /* OUT2_MONO */ 1963*4882a593Smuzhiyun #define WM5100_OUT2L_ANC_SRC 0x0800 /* OUT2L_ANC_SRC */ 1964*4882a593Smuzhiyun #define WM5100_OUT2L_ANC_SRC_MASK 0x0800 /* OUT2L_ANC_SRC */ 1965*4882a593Smuzhiyun #define WM5100_OUT2L_ANC_SRC_SHIFT 11 /* OUT2L_ANC_SRC */ 1966*4882a593Smuzhiyun #define WM5100_OUT2L_ANC_SRC_WIDTH 1 /* OUT2L_ANC_SRC */ 1967*4882a593Smuzhiyun #define WM5100_OUT2L_PGA_VOL_MASK 0x00FE /* OUT2L_PGA_VOL - [7:1] */ 1968*4882a593Smuzhiyun #define WM5100_OUT2L_PGA_VOL_SHIFT 1 /* OUT2L_PGA_VOL - [7:1] */ 1969*4882a593Smuzhiyun #define WM5100_OUT2L_PGA_VOL_WIDTH 7 /* OUT2L_PGA_VOL - [7:1] */ 1970*4882a593Smuzhiyun 1971*4882a593Smuzhiyun /* 1972*4882a593Smuzhiyun * R1045 (0x415) - Out Volume 2R 1973*4882a593Smuzhiyun */ 1974*4882a593Smuzhiyun #define WM5100_OUT2R_ANC_SRC 0x0800 /* OUT2R_ANC_SRC */ 1975*4882a593Smuzhiyun #define WM5100_OUT2R_ANC_SRC_MASK 0x0800 /* OUT2R_ANC_SRC */ 1976*4882a593Smuzhiyun #define WM5100_OUT2R_ANC_SRC_SHIFT 11 /* OUT2R_ANC_SRC */ 1977*4882a593Smuzhiyun #define WM5100_OUT2R_ANC_SRC_WIDTH 1 /* OUT2R_ANC_SRC */ 1978*4882a593Smuzhiyun #define WM5100_OUT2R_PGA_VOL_MASK 0x00FE /* OUT2R_PGA_VOL - [7:1] */ 1979*4882a593Smuzhiyun #define WM5100_OUT2R_PGA_VOL_SHIFT 1 /* OUT2R_PGA_VOL - [7:1] */ 1980*4882a593Smuzhiyun #define WM5100_OUT2R_PGA_VOL_WIDTH 7 /* OUT2R_PGA_VOL - [7:1] */ 1981*4882a593Smuzhiyun 1982*4882a593Smuzhiyun /* 1983*4882a593Smuzhiyun * R1046 (0x416) - DAC Volume Limit 2L 1984*4882a593Smuzhiyun */ 1985*4882a593Smuzhiyun #define WM5100_OUT2L_VOL_LIM_MASK 0x00FF /* OUT2L_VOL_LIM - [7:0] */ 1986*4882a593Smuzhiyun #define WM5100_OUT2L_VOL_LIM_SHIFT 0 /* OUT2L_VOL_LIM - [7:0] */ 1987*4882a593Smuzhiyun #define WM5100_OUT2L_VOL_LIM_WIDTH 8 /* OUT2L_VOL_LIM - [7:0] */ 1988*4882a593Smuzhiyun 1989*4882a593Smuzhiyun /* 1990*4882a593Smuzhiyun * R1047 (0x417) - DAC Volume Limit 2R 1991*4882a593Smuzhiyun */ 1992*4882a593Smuzhiyun #define WM5100_OUT2R_VOL_LIM_MASK 0x00FF /* OUT2R_VOL_LIM - [7:0] */ 1993*4882a593Smuzhiyun #define WM5100_OUT2R_VOL_LIM_SHIFT 0 /* OUT2R_VOL_LIM - [7:0] */ 1994*4882a593Smuzhiyun #define WM5100_OUT2R_VOL_LIM_WIDTH 8 /* OUT2R_VOL_LIM - [7:0] */ 1995*4882a593Smuzhiyun 1996*4882a593Smuzhiyun /* 1997*4882a593Smuzhiyun * R1048 (0x418) - Out Volume 3L 1998*4882a593Smuzhiyun */ 1999*4882a593Smuzhiyun #define WM5100_OUT3_OSR 0x2000 /* OUT3_OSR */ 2000*4882a593Smuzhiyun #define WM5100_OUT3_OSR_MASK 0x2000 /* OUT3_OSR */ 2001*4882a593Smuzhiyun #define WM5100_OUT3_OSR_SHIFT 13 /* OUT3_OSR */ 2002*4882a593Smuzhiyun #define WM5100_OUT3_OSR_WIDTH 1 /* OUT3_OSR */ 2003*4882a593Smuzhiyun #define WM5100_OUT3_MONO 0x1000 /* OUT3_MONO */ 2004*4882a593Smuzhiyun #define WM5100_OUT3_MONO_MASK 0x1000 /* OUT3_MONO */ 2005*4882a593Smuzhiyun #define WM5100_OUT3_MONO_SHIFT 12 /* OUT3_MONO */ 2006*4882a593Smuzhiyun #define WM5100_OUT3_MONO_WIDTH 1 /* OUT3_MONO */ 2007*4882a593Smuzhiyun #define WM5100_OUT3L_ANC_SRC 0x0800 /* OUT3L_ANC_SRC */ 2008*4882a593Smuzhiyun #define WM5100_OUT3L_ANC_SRC_MASK 0x0800 /* OUT3L_ANC_SRC */ 2009*4882a593Smuzhiyun #define WM5100_OUT3L_ANC_SRC_SHIFT 11 /* OUT3L_ANC_SRC */ 2010*4882a593Smuzhiyun #define WM5100_OUT3L_ANC_SRC_WIDTH 1 /* OUT3L_ANC_SRC */ 2011*4882a593Smuzhiyun #define WM5100_OUT3L_PGA_VOL_MASK 0x00FE /* OUT3L_PGA_VOL - [7:1] */ 2012*4882a593Smuzhiyun #define WM5100_OUT3L_PGA_VOL_SHIFT 1 /* OUT3L_PGA_VOL - [7:1] */ 2013*4882a593Smuzhiyun #define WM5100_OUT3L_PGA_VOL_WIDTH 7 /* OUT3L_PGA_VOL - [7:1] */ 2014*4882a593Smuzhiyun 2015*4882a593Smuzhiyun /* 2016*4882a593Smuzhiyun * R1049 (0x419) - Out Volume 3R 2017*4882a593Smuzhiyun */ 2018*4882a593Smuzhiyun #define WM5100_OUT3R_ANC_SRC 0x0800 /* OUT3R_ANC_SRC */ 2019*4882a593Smuzhiyun #define WM5100_OUT3R_ANC_SRC_MASK 0x0800 /* OUT3R_ANC_SRC */ 2020*4882a593Smuzhiyun #define WM5100_OUT3R_ANC_SRC_SHIFT 11 /* OUT3R_ANC_SRC */ 2021*4882a593Smuzhiyun #define WM5100_OUT3R_ANC_SRC_WIDTH 1 /* OUT3R_ANC_SRC */ 2022*4882a593Smuzhiyun #define WM5100_OUT3R_PGA_VOL_MASK 0x00FE /* OUT3R_PGA_VOL - [7:1] */ 2023*4882a593Smuzhiyun #define WM5100_OUT3R_PGA_VOL_SHIFT 1 /* OUT3R_PGA_VOL - [7:1] */ 2024*4882a593Smuzhiyun #define WM5100_OUT3R_PGA_VOL_WIDTH 7 /* OUT3R_PGA_VOL - [7:1] */ 2025*4882a593Smuzhiyun 2026*4882a593Smuzhiyun /* 2027*4882a593Smuzhiyun * R1050 (0x41A) - DAC Volume Limit 3L 2028*4882a593Smuzhiyun */ 2029*4882a593Smuzhiyun #define WM5100_OUT3L_VOL_LIM_MASK 0x00FF /* OUT3L_VOL_LIM - [7:0] */ 2030*4882a593Smuzhiyun #define WM5100_OUT3L_VOL_LIM_SHIFT 0 /* OUT3L_VOL_LIM - [7:0] */ 2031*4882a593Smuzhiyun #define WM5100_OUT3L_VOL_LIM_WIDTH 8 /* OUT3L_VOL_LIM - [7:0] */ 2032*4882a593Smuzhiyun 2033*4882a593Smuzhiyun /* 2034*4882a593Smuzhiyun * R1051 (0x41B) - DAC Volume Limit 3R 2035*4882a593Smuzhiyun */ 2036*4882a593Smuzhiyun #define WM5100_OUT3R_VOL_LIM_MASK 0x00FF /* OUT3R_VOL_LIM - [7:0] */ 2037*4882a593Smuzhiyun #define WM5100_OUT3R_VOL_LIM_SHIFT 0 /* OUT3R_VOL_LIM - [7:0] */ 2038*4882a593Smuzhiyun #define WM5100_OUT3R_VOL_LIM_WIDTH 8 /* OUT3R_VOL_LIM - [7:0] */ 2039*4882a593Smuzhiyun 2040*4882a593Smuzhiyun /* 2041*4882a593Smuzhiyun * R1052 (0x41C) - Out Volume 4L 2042*4882a593Smuzhiyun */ 2043*4882a593Smuzhiyun #define WM5100_OUT4_OSR 0x2000 /* OUT4_OSR */ 2044*4882a593Smuzhiyun #define WM5100_OUT4_OSR_MASK 0x2000 /* OUT4_OSR */ 2045*4882a593Smuzhiyun #define WM5100_OUT4_OSR_SHIFT 13 /* OUT4_OSR */ 2046*4882a593Smuzhiyun #define WM5100_OUT4_OSR_WIDTH 1 /* OUT4_OSR */ 2047*4882a593Smuzhiyun #define WM5100_OUT4L_ANC_SRC 0x0800 /* OUT4L_ANC_SRC */ 2048*4882a593Smuzhiyun #define WM5100_OUT4L_ANC_SRC_MASK 0x0800 /* OUT4L_ANC_SRC */ 2049*4882a593Smuzhiyun #define WM5100_OUT4L_ANC_SRC_SHIFT 11 /* OUT4L_ANC_SRC */ 2050*4882a593Smuzhiyun #define WM5100_OUT4L_ANC_SRC_WIDTH 1 /* OUT4L_ANC_SRC */ 2051*4882a593Smuzhiyun #define WM5100_OUT4L_VOL_LIM_MASK 0x00FF /* OUT4L_VOL_LIM - [7:0] */ 2052*4882a593Smuzhiyun #define WM5100_OUT4L_VOL_LIM_SHIFT 0 /* OUT4L_VOL_LIM - [7:0] */ 2053*4882a593Smuzhiyun #define WM5100_OUT4L_VOL_LIM_WIDTH 8 /* OUT4L_VOL_LIM - [7:0] */ 2054*4882a593Smuzhiyun 2055*4882a593Smuzhiyun /* 2056*4882a593Smuzhiyun * R1053 (0x41D) - Out Volume 4R 2057*4882a593Smuzhiyun */ 2058*4882a593Smuzhiyun #define WM5100_OUT4R_ANC_SRC 0x0800 /* OUT4R_ANC_SRC */ 2059*4882a593Smuzhiyun #define WM5100_OUT4R_ANC_SRC_MASK 0x0800 /* OUT4R_ANC_SRC */ 2060*4882a593Smuzhiyun #define WM5100_OUT4R_ANC_SRC_SHIFT 11 /* OUT4R_ANC_SRC */ 2061*4882a593Smuzhiyun #define WM5100_OUT4R_ANC_SRC_WIDTH 1 /* OUT4R_ANC_SRC */ 2062*4882a593Smuzhiyun #define WM5100_OUT4R_VOL_LIM_MASK 0x00FF /* OUT4R_VOL_LIM - [7:0] */ 2063*4882a593Smuzhiyun #define WM5100_OUT4R_VOL_LIM_SHIFT 0 /* OUT4R_VOL_LIM - [7:0] */ 2064*4882a593Smuzhiyun #define WM5100_OUT4R_VOL_LIM_WIDTH 8 /* OUT4R_VOL_LIM - [7:0] */ 2065*4882a593Smuzhiyun 2066*4882a593Smuzhiyun /* 2067*4882a593Smuzhiyun * R1054 (0x41E) - DAC Volume Limit 5L 2068*4882a593Smuzhiyun */ 2069*4882a593Smuzhiyun #define WM5100_OUT5_OSR 0x2000 /* OUT5_OSR */ 2070*4882a593Smuzhiyun #define WM5100_OUT5_OSR_MASK 0x2000 /* OUT5_OSR */ 2071*4882a593Smuzhiyun #define WM5100_OUT5_OSR_SHIFT 13 /* OUT5_OSR */ 2072*4882a593Smuzhiyun #define WM5100_OUT5_OSR_WIDTH 1 /* OUT5_OSR */ 2073*4882a593Smuzhiyun #define WM5100_OUT5L_ANC_SRC 0x0800 /* OUT5L_ANC_SRC */ 2074*4882a593Smuzhiyun #define WM5100_OUT5L_ANC_SRC_MASK 0x0800 /* OUT5L_ANC_SRC */ 2075*4882a593Smuzhiyun #define WM5100_OUT5L_ANC_SRC_SHIFT 11 /* OUT5L_ANC_SRC */ 2076*4882a593Smuzhiyun #define WM5100_OUT5L_ANC_SRC_WIDTH 1 /* OUT5L_ANC_SRC */ 2077*4882a593Smuzhiyun #define WM5100_OUT5L_VOL_LIM_MASK 0x00FF /* OUT5L_VOL_LIM - [7:0] */ 2078*4882a593Smuzhiyun #define WM5100_OUT5L_VOL_LIM_SHIFT 0 /* OUT5L_VOL_LIM - [7:0] */ 2079*4882a593Smuzhiyun #define WM5100_OUT5L_VOL_LIM_WIDTH 8 /* OUT5L_VOL_LIM - [7:0] */ 2080*4882a593Smuzhiyun 2081*4882a593Smuzhiyun /* 2082*4882a593Smuzhiyun * R1055 (0x41F) - DAC Volume Limit 5R 2083*4882a593Smuzhiyun */ 2084*4882a593Smuzhiyun #define WM5100_OUT5R_ANC_SRC 0x0800 /* OUT5R_ANC_SRC */ 2085*4882a593Smuzhiyun #define WM5100_OUT5R_ANC_SRC_MASK 0x0800 /* OUT5R_ANC_SRC */ 2086*4882a593Smuzhiyun #define WM5100_OUT5R_ANC_SRC_SHIFT 11 /* OUT5R_ANC_SRC */ 2087*4882a593Smuzhiyun #define WM5100_OUT5R_ANC_SRC_WIDTH 1 /* OUT5R_ANC_SRC */ 2088*4882a593Smuzhiyun #define WM5100_OUT5R_VOL_LIM_MASK 0x00FF /* OUT5R_VOL_LIM - [7:0] */ 2089*4882a593Smuzhiyun #define WM5100_OUT5R_VOL_LIM_SHIFT 0 /* OUT5R_VOL_LIM - [7:0] */ 2090*4882a593Smuzhiyun #define WM5100_OUT5R_VOL_LIM_WIDTH 8 /* OUT5R_VOL_LIM - [7:0] */ 2091*4882a593Smuzhiyun 2092*4882a593Smuzhiyun /* 2093*4882a593Smuzhiyun * R1056 (0x420) - DAC Volume Limit 6L 2094*4882a593Smuzhiyun */ 2095*4882a593Smuzhiyun #define WM5100_OUT6_OSR 0x2000 /* OUT6_OSR */ 2096*4882a593Smuzhiyun #define WM5100_OUT6_OSR_MASK 0x2000 /* OUT6_OSR */ 2097*4882a593Smuzhiyun #define WM5100_OUT6_OSR_SHIFT 13 /* OUT6_OSR */ 2098*4882a593Smuzhiyun #define WM5100_OUT6_OSR_WIDTH 1 /* OUT6_OSR */ 2099*4882a593Smuzhiyun #define WM5100_OUT6L_ANC_SRC 0x0800 /* OUT6L_ANC_SRC */ 2100*4882a593Smuzhiyun #define WM5100_OUT6L_ANC_SRC_MASK 0x0800 /* OUT6L_ANC_SRC */ 2101*4882a593Smuzhiyun #define WM5100_OUT6L_ANC_SRC_SHIFT 11 /* OUT6L_ANC_SRC */ 2102*4882a593Smuzhiyun #define WM5100_OUT6L_ANC_SRC_WIDTH 1 /* OUT6L_ANC_SRC */ 2103*4882a593Smuzhiyun #define WM5100_OUT6L_VOL_LIM_MASK 0x00FF /* OUT6L_VOL_LIM - [7:0] */ 2104*4882a593Smuzhiyun #define WM5100_OUT6L_VOL_LIM_SHIFT 0 /* OUT6L_VOL_LIM - [7:0] */ 2105*4882a593Smuzhiyun #define WM5100_OUT6L_VOL_LIM_WIDTH 8 /* OUT6L_VOL_LIM - [7:0] */ 2106*4882a593Smuzhiyun 2107*4882a593Smuzhiyun /* 2108*4882a593Smuzhiyun * R1057 (0x421) - DAC Volume Limit 6R 2109*4882a593Smuzhiyun */ 2110*4882a593Smuzhiyun #define WM5100_OUT6R_ANC_SRC 0x0800 /* OUT6R_ANC_SRC */ 2111*4882a593Smuzhiyun #define WM5100_OUT6R_ANC_SRC_MASK 0x0800 /* OUT6R_ANC_SRC */ 2112*4882a593Smuzhiyun #define WM5100_OUT6R_ANC_SRC_SHIFT 11 /* OUT6R_ANC_SRC */ 2113*4882a593Smuzhiyun #define WM5100_OUT6R_ANC_SRC_WIDTH 1 /* OUT6R_ANC_SRC */ 2114*4882a593Smuzhiyun #define WM5100_OUT6R_VOL_LIM_MASK 0x00FF /* OUT6R_VOL_LIM - [7:0] */ 2115*4882a593Smuzhiyun #define WM5100_OUT6R_VOL_LIM_SHIFT 0 /* OUT6R_VOL_LIM - [7:0] */ 2116*4882a593Smuzhiyun #define WM5100_OUT6R_VOL_LIM_WIDTH 8 /* OUT6R_VOL_LIM - [7:0] */ 2117*4882a593Smuzhiyun 2118*4882a593Smuzhiyun /* 2119*4882a593Smuzhiyun * R1088 (0x440) - DAC AEC Control 1 2120*4882a593Smuzhiyun */ 2121*4882a593Smuzhiyun #define WM5100_AEC_LOOPBACK_SRC_MASK 0x003C /* AEC_LOOPBACK_SRC - [5:2] */ 2122*4882a593Smuzhiyun #define WM5100_AEC_LOOPBACK_SRC_SHIFT 2 /* AEC_LOOPBACK_SRC - [5:2] */ 2123*4882a593Smuzhiyun #define WM5100_AEC_LOOPBACK_SRC_WIDTH 4 /* AEC_LOOPBACK_SRC - [5:2] */ 2124*4882a593Smuzhiyun #define WM5100_AEC_ENA_STS 0x0002 /* AEC_ENA_STS */ 2125*4882a593Smuzhiyun #define WM5100_AEC_ENA_STS_MASK 0x0002 /* AEC_ENA_STS */ 2126*4882a593Smuzhiyun #define WM5100_AEC_ENA_STS_SHIFT 1 /* AEC_ENA_STS */ 2127*4882a593Smuzhiyun #define WM5100_AEC_ENA_STS_WIDTH 1 /* AEC_ENA_STS */ 2128*4882a593Smuzhiyun #define WM5100_AEC_LOOPBACK_ENA 0x0001 /* AEC_LOOPBACK_ENA */ 2129*4882a593Smuzhiyun #define WM5100_AEC_LOOPBACK_ENA_MASK 0x0001 /* AEC_LOOPBACK_ENA */ 2130*4882a593Smuzhiyun #define WM5100_AEC_LOOPBACK_ENA_SHIFT 0 /* AEC_LOOPBACK_ENA */ 2131*4882a593Smuzhiyun #define WM5100_AEC_LOOPBACK_ENA_WIDTH 1 /* AEC_LOOPBACK_ENA */ 2132*4882a593Smuzhiyun 2133*4882a593Smuzhiyun /* 2134*4882a593Smuzhiyun * R1089 (0x441) - Output Volume Ramp 2135*4882a593Smuzhiyun */ 2136*4882a593Smuzhiyun #define WM5100_OUT_VD_RAMP_MASK 0x0070 /* OUT_VD_RAMP - [6:4] */ 2137*4882a593Smuzhiyun #define WM5100_OUT_VD_RAMP_SHIFT 4 /* OUT_VD_RAMP - [6:4] */ 2138*4882a593Smuzhiyun #define WM5100_OUT_VD_RAMP_WIDTH 3 /* OUT_VD_RAMP - [6:4] */ 2139*4882a593Smuzhiyun #define WM5100_OUT_VI_RAMP_MASK 0x0007 /* OUT_VI_RAMP - [2:0] */ 2140*4882a593Smuzhiyun #define WM5100_OUT_VI_RAMP_SHIFT 0 /* OUT_VI_RAMP - [2:0] */ 2141*4882a593Smuzhiyun #define WM5100_OUT_VI_RAMP_WIDTH 3 /* OUT_VI_RAMP - [2:0] */ 2142*4882a593Smuzhiyun 2143*4882a593Smuzhiyun /* 2144*4882a593Smuzhiyun * R1152 (0x480) - DAC Digital Volume 1L 2145*4882a593Smuzhiyun */ 2146*4882a593Smuzhiyun #define WM5100_OUT_VU 0x0200 /* OUT_VU */ 2147*4882a593Smuzhiyun #define WM5100_OUT_VU_MASK 0x0200 /* OUT_VU */ 2148*4882a593Smuzhiyun #define WM5100_OUT_VU_SHIFT 9 /* OUT_VU */ 2149*4882a593Smuzhiyun #define WM5100_OUT_VU_WIDTH 1 /* OUT_VU */ 2150*4882a593Smuzhiyun #define WM5100_OUT1L_MUTE 0x0100 /* OUT1L_MUTE */ 2151*4882a593Smuzhiyun #define WM5100_OUT1L_MUTE_MASK 0x0100 /* OUT1L_MUTE */ 2152*4882a593Smuzhiyun #define WM5100_OUT1L_MUTE_SHIFT 8 /* OUT1L_MUTE */ 2153*4882a593Smuzhiyun #define WM5100_OUT1L_MUTE_WIDTH 1 /* OUT1L_MUTE */ 2154*4882a593Smuzhiyun #define WM5100_OUT1L_VOL_MASK 0x00FF /* OUT1L_VOL - [7:0] */ 2155*4882a593Smuzhiyun #define WM5100_OUT1L_VOL_SHIFT 0 /* OUT1L_VOL - [7:0] */ 2156*4882a593Smuzhiyun #define WM5100_OUT1L_VOL_WIDTH 8 /* OUT1L_VOL - [7:0] */ 2157*4882a593Smuzhiyun 2158*4882a593Smuzhiyun /* 2159*4882a593Smuzhiyun * R1153 (0x481) - DAC Digital Volume 1R 2160*4882a593Smuzhiyun */ 2161*4882a593Smuzhiyun #define WM5100_OUT_VU 0x0200 /* OUT_VU */ 2162*4882a593Smuzhiyun #define WM5100_OUT_VU_MASK 0x0200 /* OUT_VU */ 2163*4882a593Smuzhiyun #define WM5100_OUT_VU_SHIFT 9 /* OUT_VU */ 2164*4882a593Smuzhiyun #define WM5100_OUT_VU_WIDTH 1 /* OUT_VU */ 2165*4882a593Smuzhiyun #define WM5100_OUT1R_MUTE 0x0100 /* OUT1R_MUTE */ 2166*4882a593Smuzhiyun #define WM5100_OUT1R_MUTE_MASK 0x0100 /* OUT1R_MUTE */ 2167*4882a593Smuzhiyun #define WM5100_OUT1R_MUTE_SHIFT 8 /* OUT1R_MUTE */ 2168*4882a593Smuzhiyun #define WM5100_OUT1R_MUTE_WIDTH 1 /* OUT1R_MUTE */ 2169*4882a593Smuzhiyun #define WM5100_OUT1R_VOL_MASK 0x00FF /* OUT1R_VOL - [7:0] */ 2170*4882a593Smuzhiyun #define WM5100_OUT1R_VOL_SHIFT 0 /* OUT1R_VOL - [7:0] */ 2171*4882a593Smuzhiyun #define WM5100_OUT1R_VOL_WIDTH 8 /* OUT1R_VOL - [7:0] */ 2172*4882a593Smuzhiyun 2173*4882a593Smuzhiyun /* 2174*4882a593Smuzhiyun * R1154 (0x482) - DAC Digital Volume 2L 2175*4882a593Smuzhiyun */ 2176*4882a593Smuzhiyun #define WM5100_OUT_VU 0x0200 /* OUT_VU */ 2177*4882a593Smuzhiyun #define WM5100_OUT_VU_MASK 0x0200 /* OUT_VU */ 2178*4882a593Smuzhiyun #define WM5100_OUT_VU_SHIFT 9 /* OUT_VU */ 2179*4882a593Smuzhiyun #define WM5100_OUT_VU_WIDTH 1 /* OUT_VU */ 2180*4882a593Smuzhiyun #define WM5100_OUT2L_MUTE 0x0100 /* OUT2L_MUTE */ 2181*4882a593Smuzhiyun #define WM5100_OUT2L_MUTE_MASK 0x0100 /* OUT2L_MUTE */ 2182*4882a593Smuzhiyun #define WM5100_OUT2L_MUTE_SHIFT 8 /* OUT2L_MUTE */ 2183*4882a593Smuzhiyun #define WM5100_OUT2L_MUTE_WIDTH 1 /* OUT2L_MUTE */ 2184*4882a593Smuzhiyun #define WM5100_OUT2L_VOL_MASK 0x00FF /* OUT2L_VOL - [7:0] */ 2185*4882a593Smuzhiyun #define WM5100_OUT2L_VOL_SHIFT 0 /* OUT2L_VOL - [7:0] */ 2186*4882a593Smuzhiyun #define WM5100_OUT2L_VOL_WIDTH 8 /* OUT2L_VOL - [7:0] */ 2187*4882a593Smuzhiyun 2188*4882a593Smuzhiyun /* 2189*4882a593Smuzhiyun * R1155 (0x483) - DAC Digital Volume 2R 2190*4882a593Smuzhiyun */ 2191*4882a593Smuzhiyun #define WM5100_OUT_VU 0x0200 /* OUT_VU */ 2192*4882a593Smuzhiyun #define WM5100_OUT_VU_MASK 0x0200 /* OUT_VU */ 2193*4882a593Smuzhiyun #define WM5100_OUT_VU_SHIFT 9 /* OUT_VU */ 2194*4882a593Smuzhiyun #define WM5100_OUT_VU_WIDTH 1 /* OUT_VU */ 2195*4882a593Smuzhiyun #define WM5100_OUT2R_MUTE 0x0100 /* OUT2R_MUTE */ 2196*4882a593Smuzhiyun #define WM5100_OUT2R_MUTE_MASK 0x0100 /* OUT2R_MUTE */ 2197*4882a593Smuzhiyun #define WM5100_OUT2R_MUTE_SHIFT 8 /* OUT2R_MUTE */ 2198*4882a593Smuzhiyun #define WM5100_OUT2R_MUTE_WIDTH 1 /* OUT2R_MUTE */ 2199*4882a593Smuzhiyun #define WM5100_OUT2R_VOL_MASK 0x00FF /* OUT2R_VOL - [7:0] */ 2200*4882a593Smuzhiyun #define WM5100_OUT2R_VOL_SHIFT 0 /* OUT2R_VOL - [7:0] */ 2201*4882a593Smuzhiyun #define WM5100_OUT2R_VOL_WIDTH 8 /* OUT2R_VOL - [7:0] */ 2202*4882a593Smuzhiyun 2203*4882a593Smuzhiyun /* 2204*4882a593Smuzhiyun * R1156 (0x484) - DAC Digital Volume 3L 2205*4882a593Smuzhiyun */ 2206*4882a593Smuzhiyun #define WM5100_OUT_VU 0x0200 /* OUT_VU */ 2207*4882a593Smuzhiyun #define WM5100_OUT_VU_MASK 0x0200 /* OUT_VU */ 2208*4882a593Smuzhiyun #define WM5100_OUT_VU_SHIFT 9 /* OUT_VU */ 2209*4882a593Smuzhiyun #define WM5100_OUT_VU_WIDTH 1 /* OUT_VU */ 2210*4882a593Smuzhiyun #define WM5100_OUT3L_MUTE 0x0100 /* OUT3L_MUTE */ 2211*4882a593Smuzhiyun #define WM5100_OUT3L_MUTE_MASK 0x0100 /* OUT3L_MUTE */ 2212*4882a593Smuzhiyun #define WM5100_OUT3L_MUTE_SHIFT 8 /* OUT3L_MUTE */ 2213*4882a593Smuzhiyun #define WM5100_OUT3L_MUTE_WIDTH 1 /* OUT3L_MUTE */ 2214*4882a593Smuzhiyun #define WM5100_OUT3L_VOL_MASK 0x00FF /* OUT3L_VOL - [7:0] */ 2215*4882a593Smuzhiyun #define WM5100_OUT3L_VOL_SHIFT 0 /* OUT3L_VOL - [7:0] */ 2216*4882a593Smuzhiyun #define WM5100_OUT3L_VOL_WIDTH 8 /* OUT3L_VOL - [7:0] */ 2217*4882a593Smuzhiyun 2218*4882a593Smuzhiyun /* 2219*4882a593Smuzhiyun * R1157 (0x485) - DAC Digital Volume 3R 2220*4882a593Smuzhiyun */ 2221*4882a593Smuzhiyun #define WM5100_OUT_VU 0x0200 /* OUT_VU */ 2222*4882a593Smuzhiyun #define WM5100_OUT_VU_MASK 0x0200 /* OUT_VU */ 2223*4882a593Smuzhiyun #define WM5100_OUT_VU_SHIFT 9 /* OUT_VU */ 2224*4882a593Smuzhiyun #define WM5100_OUT_VU_WIDTH 1 /* OUT_VU */ 2225*4882a593Smuzhiyun #define WM5100_OUT3R_MUTE 0x0100 /* OUT3R_MUTE */ 2226*4882a593Smuzhiyun #define WM5100_OUT3R_MUTE_MASK 0x0100 /* OUT3R_MUTE */ 2227*4882a593Smuzhiyun #define WM5100_OUT3R_MUTE_SHIFT 8 /* OUT3R_MUTE */ 2228*4882a593Smuzhiyun #define WM5100_OUT3R_MUTE_WIDTH 1 /* OUT3R_MUTE */ 2229*4882a593Smuzhiyun #define WM5100_OUT3R_VOL_MASK 0x00FF /* OUT3R_VOL - [7:0] */ 2230*4882a593Smuzhiyun #define WM5100_OUT3R_VOL_SHIFT 0 /* OUT3R_VOL - [7:0] */ 2231*4882a593Smuzhiyun #define WM5100_OUT3R_VOL_WIDTH 8 /* OUT3R_VOL - [7:0] */ 2232*4882a593Smuzhiyun 2233*4882a593Smuzhiyun /* 2234*4882a593Smuzhiyun * R1158 (0x486) - DAC Digital Volume 4L 2235*4882a593Smuzhiyun */ 2236*4882a593Smuzhiyun #define WM5100_OUT_VU 0x0200 /* OUT_VU */ 2237*4882a593Smuzhiyun #define WM5100_OUT_VU_MASK 0x0200 /* OUT_VU */ 2238*4882a593Smuzhiyun #define WM5100_OUT_VU_SHIFT 9 /* OUT_VU */ 2239*4882a593Smuzhiyun #define WM5100_OUT_VU_WIDTH 1 /* OUT_VU */ 2240*4882a593Smuzhiyun #define WM5100_OUT4L_MUTE 0x0100 /* OUT4L_MUTE */ 2241*4882a593Smuzhiyun #define WM5100_OUT4L_MUTE_MASK 0x0100 /* OUT4L_MUTE */ 2242*4882a593Smuzhiyun #define WM5100_OUT4L_MUTE_SHIFT 8 /* OUT4L_MUTE */ 2243*4882a593Smuzhiyun #define WM5100_OUT4L_MUTE_WIDTH 1 /* OUT4L_MUTE */ 2244*4882a593Smuzhiyun #define WM5100_OUT4L_VOL_MASK 0x00FF /* OUT4L_VOL - [7:0] */ 2245*4882a593Smuzhiyun #define WM5100_OUT4L_VOL_SHIFT 0 /* OUT4L_VOL - [7:0] */ 2246*4882a593Smuzhiyun #define WM5100_OUT4L_VOL_WIDTH 8 /* OUT4L_VOL - [7:0] */ 2247*4882a593Smuzhiyun 2248*4882a593Smuzhiyun /* 2249*4882a593Smuzhiyun * R1159 (0x487) - DAC Digital Volume 4R 2250*4882a593Smuzhiyun */ 2251*4882a593Smuzhiyun #define WM5100_OUT_VU 0x0200 /* OUT_VU */ 2252*4882a593Smuzhiyun #define WM5100_OUT_VU_MASK 0x0200 /* OUT_VU */ 2253*4882a593Smuzhiyun #define WM5100_OUT_VU_SHIFT 9 /* OUT_VU */ 2254*4882a593Smuzhiyun #define WM5100_OUT_VU_WIDTH 1 /* OUT_VU */ 2255*4882a593Smuzhiyun #define WM5100_OUT4R_MUTE 0x0100 /* OUT4R_MUTE */ 2256*4882a593Smuzhiyun #define WM5100_OUT4R_MUTE_MASK 0x0100 /* OUT4R_MUTE */ 2257*4882a593Smuzhiyun #define WM5100_OUT4R_MUTE_SHIFT 8 /* OUT4R_MUTE */ 2258*4882a593Smuzhiyun #define WM5100_OUT4R_MUTE_WIDTH 1 /* OUT4R_MUTE */ 2259*4882a593Smuzhiyun #define WM5100_OUT4R_VOL_MASK 0x00FF /* OUT4R_VOL - [7:0] */ 2260*4882a593Smuzhiyun #define WM5100_OUT4R_VOL_SHIFT 0 /* OUT4R_VOL - [7:0] */ 2261*4882a593Smuzhiyun #define WM5100_OUT4R_VOL_WIDTH 8 /* OUT4R_VOL - [7:0] */ 2262*4882a593Smuzhiyun 2263*4882a593Smuzhiyun /* 2264*4882a593Smuzhiyun * R1160 (0x488) - DAC Digital Volume 5L 2265*4882a593Smuzhiyun */ 2266*4882a593Smuzhiyun #define WM5100_OUT_VU 0x0200 /* OUT_VU */ 2267*4882a593Smuzhiyun #define WM5100_OUT_VU_MASK 0x0200 /* OUT_VU */ 2268*4882a593Smuzhiyun #define WM5100_OUT_VU_SHIFT 9 /* OUT_VU */ 2269*4882a593Smuzhiyun #define WM5100_OUT_VU_WIDTH 1 /* OUT_VU */ 2270*4882a593Smuzhiyun #define WM5100_OUT5L_MUTE 0x0100 /* OUT5L_MUTE */ 2271*4882a593Smuzhiyun #define WM5100_OUT5L_MUTE_MASK 0x0100 /* OUT5L_MUTE */ 2272*4882a593Smuzhiyun #define WM5100_OUT5L_MUTE_SHIFT 8 /* OUT5L_MUTE */ 2273*4882a593Smuzhiyun #define WM5100_OUT5L_MUTE_WIDTH 1 /* OUT5L_MUTE */ 2274*4882a593Smuzhiyun #define WM5100_OUT5L_VOL_MASK 0x00FF /* OUT5L_VOL - [7:0] */ 2275*4882a593Smuzhiyun #define WM5100_OUT5L_VOL_SHIFT 0 /* OUT5L_VOL - [7:0] */ 2276*4882a593Smuzhiyun #define WM5100_OUT5L_VOL_WIDTH 8 /* OUT5L_VOL - [7:0] */ 2277*4882a593Smuzhiyun 2278*4882a593Smuzhiyun /* 2279*4882a593Smuzhiyun * R1161 (0x489) - DAC Digital Volume 5R 2280*4882a593Smuzhiyun */ 2281*4882a593Smuzhiyun #define WM5100_OUT_VU 0x0200 /* OUT_VU */ 2282*4882a593Smuzhiyun #define WM5100_OUT_VU_MASK 0x0200 /* OUT_VU */ 2283*4882a593Smuzhiyun #define WM5100_OUT_VU_SHIFT 9 /* OUT_VU */ 2284*4882a593Smuzhiyun #define WM5100_OUT_VU_WIDTH 1 /* OUT_VU */ 2285*4882a593Smuzhiyun #define WM5100_OUT5R_MUTE 0x0100 /* OUT5R_MUTE */ 2286*4882a593Smuzhiyun #define WM5100_OUT5R_MUTE_MASK 0x0100 /* OUT5R_MUTE */ 2287*4882a593Smuzhiyun #define WM5100_OUT5R_MUTE_SHIFT 8 /* OUT5R_MUTE */ 2288*4882a593Smuzhiyun #define WM5100_OUT5R_MUTE_WIDTH 1 /* OUT5R_MUTE */ 2289*4882a593Smuzhiyun #define WM5100_OUT5R_VOL_MASK 0x00FF /* OUT5R_VOL - [7:0] */ 2290*4882a593Smuzhiyun #define WM5100_OUT5R_VOL_SHIFT 0 /* OUT5R_VOL - [7:0] */ 2291*4882a593Smuzhiyun #define WM5100_OUT5R_VOL_WIDTH 8 /* OUT5R_VOL - [7:0] */ 2292*4882a593Smuzhiyun 2293*4882a593Smuzhiyun /* 2294*4882a593Smuzhiyun * R1162 (0x48A) - DAC Digital Volume 6L 2295*4882a593Smuzhiyun */ 2296*4882a593Smuzhiyun #define WM5100_OUT_VU 0x0200 /* OUT_VU */ 2297*4882a593Smuzhiyun #define WM5100_OUT_VU_MASK 0x0200 /* OUT_VU */ 2298*4882a593Smuzhiyun #define WM5100_OUT_VU_SHIFT 9 /* OUT_VU */ 2299*4882a593Smuzhiyun #define WM5100_OUT_VU_WIDTH 1 /* OUT_VU */ 2300*4882a593Smuzhiyun #define WM5100_OUT6L_MUTE 0x0100 /* OUT6L_MUTE */ 2301*4882a593Smuzhiyun #define WM5100_OUT6L_MUTE_MASK 0x0100 /* OUT6L_MUTE */ 2302*4882a593Smuzhiyun #define WM5100_OUT6L_MUTE_SHIFT 8 /* OUT6L_MUTE */ 2303*4882a593Smuzhiyun #define WM5100_OUT6L_MUTE_WIDTH 1 /* OUT6L_MUTE */ 2304*4882a593Smuzhiyun #define WM5100_OUT6L_VOL_MASK 0x00FF /* OUT6L_VOL - [7:0] */ 2305*4882a593Smuzhiyun #define WM5100_OUT6L_VOL_SHIFT 0 /* OUT6L_VOL - [7:0] */ 2306*4882a593Smuzhiyun #define WM5100_OUT6L_VOL_WIDTH 8 /* OUT6L_VOL - [7:0] */ 2307*4882a593Smuzhiyun 2308*4882a593Smuzhiyun /* 2309*4882a593Smuzhiyun * R1163 (0x48B) - DAC Digital Volume 6R 2310*4882a593Smuzhiyun */ 2311*4882a593Smuzhiyun #define WM5100_OUT_VU 0x0200 /* OUT_VU */ 2312*4882a593Smuzhiyun #define WM5100_OUT_VU_MASK 0x0200 /* OUT_VU */ 2313*4882a593Smuzhiyun #define WM5100_OUT_VU_SHIFT 9 /* OUT_VU */ 2314*4882a593Smuzhiyun #define WM5100_OUT_VU_WIDTH 1 /* OUT_VU */ 2315*4882a593Smuzhiyun #define WM5100_OUT6R_MUTE 0x0100 /* OUT6R_MUTE */ 2316*4882a593Smuzhiyun #define WM5100_OUT6R_MUTE_MASK 0x0100 /* OUT6R_MUTE */ 2317*4882a593Smuzhiyun #define WM5100_OUT6R_MUTE_SHIFT 8 /* OUT6R_MUTE */ 2318*4882a593Smuzhiyun #define WM5100_OUT6R_MUTE_WIDTH 1 /* OUT6R_MUTE */ 2319*4882a593Smuzhiyun #define WM5100_OUT6R_VOL_MASK 0x00FF /* OUT6R_VOL - [7:0] */ 2320*4882a593Smuzhiyun #define WM5100_OUT6R_VOL_SHIFT 0 /* OUT6R_VOL - [7:0] */ 2321*4882a593Smuzhiyun #define WM5100_OUT6R_VOL_WIDTH 8 /* OUT6R_VOL - [7:0] */ 2322*4882a593Smuzhiyun 2323*4882a593Smuzhiyun /* 2324*4882a593Smuzhiyun * R1216 (0x4C0) - PDM SPK1 CTRL 1 2325*4882a593Smuzhiyun */ 2326*4882a593Smuzhiyun #define WM5100_SPK1R_MUTE 0x2000 /* SPK1R_MUTE */ 2327*4882a593Smuzhiyun #define WM5100_SPK1R_MUTE_MASK 0x2000 /* SPK1R_MUTE */ 2328*4882a593Smuzhiyun #define WM5100_SPK1R_MUTE_SHIFT 13 /* SPK1R_MUTE */ 2329*4882a593Smuzhiyun #define WM5100_SPK1R_MUTE_WIDTH 1 /* SPK1R_MUTE */ 2330*4882a593Smuzhiyun #define WM5100_SPK1L_MUTE 0x1000 /* SPK1L_MUTE */ 2331*4882a593Smuzhiyun #define WM5100_SPK1L_MUTE_MASK 0x1000 /* SPK1L_MUTE */ 2332*4882a593Smuzhiyun #define WM5100_SPK1L_MUTE_SHIFT 12 /* SPK1L_MUTE */ 2333*4882a593Smuzhiyun #define WM5100_SPK1L_MUTE_WIDTH 1 /* SPK1L_MUTE */ 2334*4882a593Smuzhiyun #define WM5100_SPK1_MUTE_ENDIAN 0x0100 /* SPK1_MUTE_ENDIAN */ 2335*4882a593Smuzhiyun #define WM5100_SPK1_MUTE_ENDIAN_MASK 0x0100 /* SPK1_MUTE_ENDIAN */ 2336*4882a593Smuzhiyun #define WM5100_SPK1_MUTE_ENDIAN_SHIFT 8 /* SPK1_MUTE_ENDIAN */ 2337*4882a593Smuzhiyun #define WM5100_SPK1_MUTE_ENDIAN_WIDTH 1 /* SPK1_MUTE_ENDIAN */ 2338*4882a593Smuzhiyun #define WM5100_SPK1_MUTE_SEQ1_MASK 0x00FF /* SPK1_MUTE_SEQ1 - [7:0] */ 2339*4882a593Smuzhiyun #define WM5100_SPK1_MUTE_SEQ1_SHIFT 0 /* SPK1_MUTE_SEQ1 - [7:0] */ 2340*4882a593Smuzhiyun #define WM5100_SPK1_MUTE_SEQ1_WIDTH 8 /* SPK1_MUTE_SEQ1 - [7:0] */ 2341*4882a593Smuzhiyun 2342*4882a593Smuzhiyun /* 2343*4882a593Smuzhiyun * R1217 (0x4C1) - PDM SPK1 CTRL 2 2344*4882a593Smuzhiyun */ 2345*4882a593Smuzhiyun #define WM5100_SPK1_FMT 0x0001 /* SPK1_FMT */ 2346*4882a593Smuzhiyun #define WM5100_SPK1_FMT_MASK 0x0001 /* SPK1_FMT */ 2347*4882a593Smuzhiyun #define WM5100_SPK1_FMT_SHIFT 0 /* SPK1_FMT */ 2348*4882a593Smuzhiyun #define WM5100_SPK1_FMT_WIDTH 1 /* SPK1_FMT */ 2349*4882a593Smuzhiyun 2350*4882a593Smuzhiyun /* 2351*4882a593Smuzhiyun * R1218 (0x4C2) - PDM SPK2 CTRL 1 2352*4882a593Smuzhiyun */ 2353*4882a593Smuzhiyun #define WM5100_SPK2R_MUTE 0x2000 /* SPK2R_MUTE */ 2354*4882a593Smuzhiyun #define WM5100_SPK2R_MUTE_MASK 0x2000 /* SPK2R_MUTE */ 2355*4882a593Smuzhiyun #define WM5100_SPK2R_MUTE_SHIFT 13 /* SPK2R_MUTE */ 2356*4882a593Smuzhiyun #define WM5100_SPK2R_MUTE_WIDTH 1 /* SPK2R_MUTE */ 2357*4882a593Smuzhiyun #define WM5100_SPK2L_MUTE 0x1000 /* SPK2L_MUTE */ 2358*4882a593Smuzhiyun #define WM5100_SPK2L_MUTE_MASK 0x1000 /* SPK2L_MUTE */ 2359*4882a593Smuzhiyun #define WM5100_SPK2L_MUTE_SHIFT 12 /* SPK2L_MUTE */ 2360*4882a593Smuzhiyun #define WM5100_SPK2L_MUTE_WIDTH 1 /* SPK2L_MUTE */ 2361*4882a593Smuzhiyun #define WM5100_SPK2_MUTE_ENDIAN 0x0100 /* SPK2_MUTE_ENDIAN */ 2362*4882a593Smuzhiyun #define WM5100_SPK2_MUTE_ENDIAN_MASK 0x0100 /* SPK2_MUTE_ENDIAN */ 2363*4882a593Smuzhiyun #define WM5100_SPK2_MUTE_ENDIAN_SHIFT 8 /* SPK2_MUTE_ENDIAN */ 2364*4882a593Smuzhiyun #define WM5100_SPK2_MUTE_ENDIAN_WIDTH 1 /* SPK2_MUTE_ENDIAN */ 2365*4882a593Smuzhiyun #define WM5100_SPK2_MUTE_SEQ1_MASK 0x00FF /* SPK2_MUTE_SEQ1 - [7:0] */ 2366*4882a593Smuzhiyun #define WM5100_SPK2_MUTE_SEQ1_SHIFT 0 /* SPK2_MUTE_SEQ1 - [7:0] */ 2367*4882a593Smuzhiyun #define WM5100_SPK2_MUTE_SEQ1_WIDTH 8 /* SPK2_MUTE_SEQ1 - [7:0] */ 2368*4882a593Smuzhiyun 2369*4882a593Smuzhiyun /* 2370*4882a593Smuzhiyun * R1219 (0x4C3) - PDM SPK2 CTRL 2 2371*4882a593Smuzhiyun */ 2372*4882a593Smuzhiyun #define WM5100_SPK2_FMT 0x0001 /* SPK2_FMT */ 2373*4882a593Smuzhiyun #define WM5100_SPK2_FMT_MASK 0x0001 /* SPK2_FMT */ 2374*4882a593Smuzhiyun #define WM5100_SPK2_FMT_SHIFT 0 /* SPK2_FMT */ 2375*4882a593Smuzhiyun #define WM5100_SPK2_FMT_WIDTH 1 /* SPK2_FMT */ 2376*4882a593Smuzhiyun 2377*4882a593Smuzhiyun /* 2378*4882a593Smuzhiyun * R1280 (0x500) - Audio IF 1_1 2379*4882a593Smuzhiyun */ 2380*4882a593Smuzhiyun #define WM5100_AIF1_BCLK_INV 0x0080 /* AIF1_BCLK_INV */ 2381*4882a593Smuzhiyun #define WM5100_AIF1_BCLK_INV_MASK 0x0080 /* AIF1_BCLK_INV */ 2382*4882a593Smuzhiyun #define WM5100_AIF1_BCLK_INV_SHIFT 7 /* AIF1_BCLK_INV */ 2383*4882a593Smuzhiyun #define WM5100_AIF1_BCLK_INV_WIDTH 1 /* AIF1_BCLK_INV */ 2384*4882a593Smuzhiyun #define WM5100_AIF1_BCLK_FRC 0x0040 /* AIF1_BCLK_FRC */ 2385*4882a593Smuzhiyun #define WM5100_AIF1_BCLK_FRC_MASK 0x0040 /* AIF1_BCLK_FRC */ 2386*4882a593Smuzhiyun #define WM5100_AIF1_BCLK_FRC_SHIFT 6 /* AIF1_BCLK_FRC */ 2387*4882a593Smuzhiyun #define WM5100_AIF1_BCLK_FRC_WIDTH 1 /* AIF1_BCLK_FRC */ 2388*4882a593Smuzhiyun #define WM5100_AIF1_BCLK_MSTR 0x0020 /* AIF1_BCLK_MSTR */ 2389*4882a593Smuzhiyun #define WM5100_AIF1_BCLK_MSTR_MASK 0x0020 /* AIF1_BCLK_MSTR */ 2390*4882a593Smuzhiyun #define WM5100_AIF1_BCLK_MSTR_SHIFT 5 /* AIF1_BCLK_MSTR */ 2391*4882a593Smuzhiyun #define WM5100_AIF1_BCLK_MSTR_WIDTH 1 /* AIF1_BCLK_MSTR */ 2392*4882a593Smuzhiyun #define WM5100_AIF1_BCLK_FREQ_MASK 0x001F /* AIF1_BCLK_FREQ - [4:0] */ 2393*4882a593Smuzhiyun #define WM5100_AIF1_BCLK_FREQ_SHIFT 0 /* AIF1_BCLK_FREQ - [4:0] */ 2394*4882a593Smuzhiyun #define WM5100_AIF1_BCLK_FREQ_WIDTH 5 /* AIF1_BCLK_FREQ - [4:0] */ 2395*4882a593Smuzhiyun 2396*4882a593Smuzhiyun /* 2397*4882a593Smuzhiyun * R1281 (0x501) - Audio IF 1_2 2398*4882a593Smuzhiyun */ 2399*4882a593Smuzhiyun #define WM5100_AIF1TX_DAT_TRI 0x0020 /* AIF1TX_DAT_TRI */ 2400*4882a593Smuzhiyun #define WM5100_AIF1TX_DAT_TRI_MASK 0x0020 /* AIF1TX_DAT_TRI */ 2401*4882a593Smuzhiyun #define WM5100_AIF1TX_DAT_TRI_SHIFT 5 /* AIF1TX_DAT_TRI */ 2402*4882a593Smuzhiyun #define WM5100_AIF1TX_DAT_TRI_WIDTH 1 /* AIF1TX_DAT_TRI */ 2403*4882a593Smuzhiyun #define WM5100_AIF1TX_LRCLK_SRC 0x0008 /* AIF1TX_LRCLK_SRC */ 2404*4882a593Smuzhiyun #define WM5100_AIF1TX_LRCLK_SRC_MASK 0x0008 /* AIF1TX_LRCLK_SRC */ 2405*4882a593Smuzhiyun #define WM5100_AIF1TX_LRCLK_SRC_SHIFT 3 /* AIF1TX_LRCLK_SRC */ 2406*4882a593Smuzhiyun #define WM5100_AIF1TX_LRCLK_SRC_WIDTH 1 /* AIF1TX_LRCLK_SRC */ 2407*4882a593Smuzhiyun #define WM5100_AIF1TX_LRCLK_INV 0x0004 /* AIF1TX_LRCLK_INV */ 2408*4882a593Smuzhiyun #define WM5100_AIF1TX_LRCLK_INV_MASK 0x0004 /* AIF1TX_LRCLK_INV */ 2409*4882a593Smuzhiyun #define WM5100_AIF1TX_LRCLK_INV_SHIFT 2 /* AIF1TX_LRCLK_INV */ 2410*4882a593Smuzhiyun #define WM5100_AIF1TX_LRCLK_INV_WIDTH 1 /* AIF1TX_LRCLK_INV */ 2411*4882a593Smuzhiyun #define WM5100_AIF1TX_LRCLK_FRC 0x0002 /* AIF1TX_LRCLK_FRC */ 2412*4882a593Smuzhiyun #define WM5100_AIF1TX_LRCLK_FRC_MASK 0x0002 /* AIF1TX_LRCLK_FRC */ 2413*4882a593Smuzhiyun #define WM5100_AIF1TX_LRCLK_FRC_SHIFT 1 /* AIF1TX_LRCLK_FRC */ 2414*4882a593Smuzhiyun #define WM5100_AIF1TX_LRCLK_FRC_WIDTH 1 /* AIF1TX_LRCLK_FRC */ 2415*4882a593Smuzhiyun #define WM5100_AIF1TX_LRCLK_MSTR 0x0001 /* AIF1TX_LRCLK_MSTR */ 2416*4882a593Smuzhiyun #define WM5100_AIF1TX_LRCLK_MSTR_MASK 0x0001 /* AIF1TX_LRCLK_MSTR */ 2417*4882a593Smuzhiyun #define WM5100_AIF1TX_LRCLK_MSTR_SHIFT 0 /* AIF1TX_LRCLK_MSTR */ 2418*4882a593Smuzhiyun #define WM5100_AIF1TX_LRCLK_MSTR_WIDTH 1 /* AIF1TX_LRCLK_MSTR */ 2419*4882a593Smuzhiyun 2420*4882a593Smuzhiyun /* 2421*4882a593Smuzhiyun * R1282 (0x502) - Audio IF 1_3 2422*4882a593Smuzhiyun */ 2423*4882a593Smuzhiyun #define WM5100_AIF1RX_LRCLK_INV 0x0004 /* AIF1RX_LRCLK_INV */ 2424*4882a593Smuzhiyun #define WM5100_AIF1RX_LRCLK_INV_MASK 0x0004 /* AIF1RX_LRCLK_INV */ 2425*4882a593Smuzhiyun #define WM5100_AIF1RX_LRCLK_INV_SHIFT 2 /* AIF1RX_LRCLK_INV */ 2426*4882a593Smuzhiyun #define WM5100_AIF1RX_LRCLK_INV_WIDTH 1 /* AIF1RX_LRCLK_INV */ 2427*4882a593Smuzhiyun #define WM5100_AIF1RX_LRCLK_FRC 0x0002 /* AIF1RX_LRCLK_FRC */ 2428*4882a593Smuzhiyun #define WM5100_AIF1RX_LRCLK_FRC_MASK 0x0002 /* AIF1RX_LRCLK_FRC */ 2429*4882a593Smuzhiyun #define WM5100_AIF1RX_LRCLK_FRC_SHIFT 1 /* AIF1RX_LRCLK_FRC */ 2430*4882a593Smuzhiyun #define WM5100_AIF1RX_LRCLK_FRC_WIDTH 1 /* AIF1RX_LRCLK_FRC */ 2431*4882a593Smuzhiyun #define WM5100_AIF1RX_LRCLK_MSTR 0x0001 /* AIF1RX_LRCLK_MSTR */ 2432*4882a593Smuzhiyun #define WM5100_AIF1RX_LRCLK_MSTR_MASK 0x0001 /* AIF1RX_LRCLK_MSTR */ 2433*4882a593Smuzhiyun #define WM5100_AIF1RX_LRCLK_MSTR_SHIFT 0 /* AIF1RX_LRCLK_MSTR */ 2434*4882a593Smuzhiyun #define WM5100_AIF1RX_LRCLK_MSTR_WIDTH 1 /* AIF1RX_LRCLK_MSTR */ 2435*4882a593Smuzhiyun 2436*4882a593Smuzhiyun /* 2437*4882a593Smuzhiyun * R1283 (0x503) - Audio IF 1_4 2438*4882a593Smuzhiyun */ 2439*4882a593Smuzhiyun #define WM5100_AIF1_TRI 0x0040 /* AIF1_TRI */ 2440*4882a593Smuzhiyun #define WM5100_AIF1_TRI_MASK 0x0040 /* AIF1_TRI */ 2441*4882a593Smuzhiyun #define WM5100_AIF1_TRI_SHIFT 6 /* AIF1_TRI */ 2442*4882a593Smuzhiyun #define WM5100_AIF1_TRI_WIDTH 1 /* AIF1_TRI */ 2443*4882a593Smuzhiyun #define WM5100_AIF1_RATE_MASK 0x0003 /* AIF1_RATE - [1:0] */ 2444*4882a593Smuzhiyun #define WM5100_AIF1_RATE_SHIFT 0 /* AIF1_RATE - [1:0] */ 2445*4882a593Smuzhiyun #define WM5100_AIF1_RATE_WIDTH 2 /* AIF1_RATE - [1:0] */ 2446*4882a593Smuzhiyun 2447*4882a593Smuzhiyun /* 2448*4882a593Smuzhiyun * R1284 (0x504) - Audio IF 1_5 2449*4882a593Smuzhiyun */ 2450*4882a593Smuzhiyun #define WM5100_AIF1_FMT_MASK 0x0007 /* AIF1_FMT - [2:0] */ 2451*4882a593Smuzhiyun #define WM5100_AIF1_FMT_SHIFT 0 /* AIF1_FMT - [2:0] */ 2452*4882a593Smuzhiyun #define WM5100_AIF1_FMT_WIDTH 3 /* AIF1_FMT - [2:0] */ 2453*4882a593Smuzhiyun 2454*4882a593Smuzhiyun /* 2455*4882a593Smuzhiyun * R1285 (0x505) - Audio IF 1_6 2456*4882a593Smuzhiyun */ 2457*4882a593Smuzhiyun #define WM5100_AIF1TX_BCPF_MASK 0x1FFF /* AIF1TX_BCPF - [12:0] */ 2458*4882a593Smuzhiyun #define WM5100_AIF1TX_BCPF_SHIFT 0 /* AIF1TX_BCPF - [12:0] */ 2459*4882a593Smuzhiyun #define WM5100_AIF1TX_BCPF_WIDTH 13 /* AIF1TX_BCPF - [12:0] */ 2460*4882a593Smuzhiyun 2461*4882a593Smuzhiyun /* 2462*4882a593Smuzhiyun * R1286 (0x506) - Audio IF 1_7 2463*4882a593Smuzhiyun */ 2464*4882a593Smuzhiyun #define WM5100_AIF1RX_BCPF_MASK 0x1FFF /* AIF1RX_BCPF - [12:0] */ 2465*4882a593Smuzhiyun #define WM5100_AIF1RX_BCPF_SHIFT 0 /* AIF1RX_BCPF - [12:0] */ 2466*4882a593Smuzhiyun #define WM5100_AIF1RX_BCPF_WIDTH 13 /* AIF1RX_BCPF - [12:0] */ 2467*4882a593Smuzhiyun 2468*4882a593Smuzhiyun /* 2469*4882a593Smuzhiyun * R1287 (0x507) - Audio IF 1_8 2470*4882a593Smuzhiyun */ 2471*4882a593Smuzhiyun #define WM5100_AIF1TX_WL_MASK 0x3F00 /* AIF1TX_WL - [13:8] */ 2472*4882a593Smuzhiyun #define WM5100_AIF1TX_WL_SHIFT 8 /* AIF1TX_WL - [13:8] */ 2473*4882a593Smuzhiyun #define WM5100_AIF1TX_WL_WIDTH 6 /* AIF1TX_WL - [13:8] */ 2474*4882a593Smuzhiyun #define WM5100_AIF1TX_SLOT_LEN_MASK 0x00FF /* AIF1TX_SLOT_LEN - [7:0] */ 2475*4882a593Smuzhiyun #define WM5100_AIF1TX_SLOT_LEN_SHIFT 0 /* AIF1TX_SLOT_LEN - [7:0] */ 2476*4882a593Smuzhiyun #define WM5100_AIF1TX_SLOT_LEN_WIDTH 8 /* AIF1TX_SLOT_LEN - [7:0] */ 2477*4882a593Smuzhiyun 2478*4882a593Smuzhiyun /* 2479*4882a593Smuzhiyun * R1288 (0x508) - Audio IF 1_9 2480*4882a593Smuzhiyun */ 2481*4882a593Smuzhiyun #define WM5100_AIF1RX_WL_MASK 0x3F00 /* AIF1RX_WL - [13:8] */ 2482*4882a593Smuzhiyun #define WM5100_AIF1RX_WL_SHIFT 8 /* AIF1RX_WL - [13:8] */ 2483*4882a593Smuzhiyun #define WM5100_AIF1RX_WL_WIDTH 6 /* AIF1RX_WL - [13:8] */ 2484*4882a593Smuzhiyun #define WM5100_AIF1RX_SLOT_LEN_MASK 0x00FF /* AIF1RX_SLOT_LEN - [7:0] */ 2485*4882a593Smuzhiyun #define WM5100_AIF1RX_SLOT_LEN_SHIFT 0 /* AIF1RX_SLOT_LEN - [7:0] */ 2486*4882a593Smuzhiyun #define WM5100_AIF1RX_SLOT_LEN_WIDTH 8 /* AIF1RX_SLOT_LEN - [7:0] */ 2487*4882a593Smuzhiyun 2488*4882a593Smuzhiyun /* 2489*4882a593Smuzhiyun * R1289 (0x509) - Audio IF 1_10 2490*4882a593Smuzhiyun */ 2491*4882a593Smuzhiyun #define WM5100_AIF1TX1_SLOT_MASK 0x003F /* AIF1TX1_SLOT - [5:0] */ 2492*4882a593Smuzhiyun #define WM5100_AIF1TX1_SLOT_SHIFT 0 /* AIF1TX1_SLOT - [5:0] */ 2493*4882a593Smuzhiyun #define WM5100_AIF1TX1_SLOT_WIDTH 6 /* AIF1TX1_SLOT - [5:0] */ 2494*4882a593Smuzhiyun 2495*4882a593Smuzhiyun /* 2496*4882a593Smuzhiyun * R1290 (0x50A) - Audio IF 1_11 2497*4882a593Smuzhiyun */ 2498*4882a593Smuzhiyun #define WM5100_AIF1TX2_SLOT_MASK 0x003F /* AIF1TX2_SLOT - [5:0] */ 2499*4882a593Smuzhiyun #define WM5100_AIF1TX2_SLOT_SHIFT 0 /* AIF1TX2_SLOT - [5:0] */ 2500*4882a593Smuzhiyun #define WM5100_AIF1TX2_SLOT_WIDTH 6 /* AIF1TX2_SLOT - [5:0] */ 2501*4882a593Smuzhiyun 2502*4882a593Smuzhiyun /* 2503*4882a593Smuzhiyun * R1291 (0x50B) - Audio IF 1_12 2504*4882a593Smuzhiyun */ 2505*4882a593Smuzhiyun #define WM5100_AIF1TX3_SLOT_MASK 0x003F /* AIF1TX3_SLOT - [5:0] */ 2506*4882a593Smuzhiyun #define WM5100_AIF1TX3_SLOT_SHIFT 0 /* AIF1TX3_SLOT - [5:0] */ 2507*4882a593Smuzhiyun #define WM5100_AIF1TX3_SLOT_WIDTH 6 /* AIF1TX3_SLOT - [5:0] */ 2508*4882a593Smuzhiyun 2509*4882a593Smuzhiyun /* 2510*4882a593Smuzhiyun * R1292 (0x50C) - Audio IF 1_13 2511*4882a593Smuzhiyun */ 2512*4882a593Smuzhiyun #define WM5100_AIF1TX4_SLOT_MASK 0x003F /* AIF1TX4_SLOT - [5:0] */ 2513*4882a593Smuzhiyun #define WM5100_AIF1TX4_SLOT_SHIFT 0 /* AIF1TX4_SLOT - [5:0] */ 2514*4882a593Smuzhiyun #define WM5100_AIF1TX4_SLOT_WIDTH 6 /* AIF1TX4_SLOT - [5:0] */ 2515*4882a593Smuzhiyun 2516*4882a593Smuzhiyun /* 2517*4882a593Smuzhiyun * R1293 (0x50D) - Audio IF 1_14 2518*4882a593Smuzhiyun */ 2519*4882a593Smuzhiyun #define WM5100_AIF1TX5_SLOT_MASK 0x003F /* AIF1TX5_SLOT - [5:0] */ 2520*4882a593Smuzhiyun #define WM5100_AIF1TX5_SLOT_SHIFT 0 /* AIF1TX5_SLOT - [5:0] */ 2521*4882a593Smuzhiyun #define WM5100_AIF1TX5_SLOT_WIDTH 6 /* AIF1TX5_SLOT - [5:0] */ 2522*4882a593Smuzhiyun 2523*4882a593Smuzhiyun /* 2524*4882a593Smuzhiyun * R1294 (0x50E) - Audio IF 1_15 2525*4882a593Smuzhiyun */ 2526*4882a593Smuzhiyun #define WM5100_AIF1TX6_SLOT_MASK 0x003F /* AIF1TX6_SLOT - [5:0] */ 2527*4882a593Smuzhiyun #define WM5100_AIF1TX6_SLOT_SHIFT 0 /* AIF1TX6_SLOT - [5:0] */ 2528*4882a593Smuzhiyun #define WM5100_AIF1TX6_SLOT_WIDTH 6 /* AIF1TX6_SLOT - [5:0] */ 2529*4882a593Smuzhiyun 2530*4882a593Smuzhiyun /* 2531*4882a593Smuzhiyun * R1295 (0x50F) - Audio IF 1_16 2532*4882a593Smuzhiyun */ 2533*4882a593Smuzhiyun #define WM5100_AIF1TX7_SLOT_MASK 0x003F /* AIF1TX7_SLOT - [5:0] */ 2534*4882a593Smuzhiyun #define WM5100_AIF1TX7_SLOT_SHIFT 0 /* AIF1TX7_SLOT - [5:0] */ 2535*4882a593Smuzhiyun #define WM5100_AIF1TX7_SLOT_WIDTH 6 /* AIF1TX7_SLOT - [5:0] */ 2536*4882a593Smuzhiyun 2537*4882a593Smuzhiyun /* 2538*4882a593Smuzhiyun * R1296 (0x510) - Audio IF 1_17 2539*4882a593Smuzhiyun */ 2540*4882a593Smuzhiyun #define WM5100_AIF1TX8_SLOT_MASK 0x003F /* AIF1TX8_SLOT - [5:0] */ 2541*4882a593Smuzhiyun #define WM5100_AIF1TX8_SLOT_SHIFT 0 /* AIF1TX8_SLOT - [5:0] */ 2542*4882a593Smuzhiyun #define WM5100_AIF1TX8_SLOT_WIDTH 6 /* AIF1TX8_SLOT - [5:0] */ 2543*4882a593Smuzhiyun 2544*4882a593Smuzhiyun /* 2545*4882a593Smuzhiyun * R1297 (0x511) - Audio IF 1_18 2546*4882a593Smuzhiyun */ 2547*4882a593Smuzhiyun #define WM5100_AIF1RX1_SLOT_MASK 0x003F /* AIF1RX1_SLOT - [5:0] */ 2548*4882a593Smuzhiyun #define WM5100_AIF1RX1_SLOT_SHIFT 0 /* AIF1RX1_SLOT - [5:0] */ 2549*4882a593Smuzhiyun #define WM5100_AIF1RX1_SLOT_WIDTH 6 /* AIF1RX1_SLOT - [5:0] */ 2550*4882a593Smuzhiyun 2551*4882a593Smuzhiyun /* 2552*4882a593Smuzhiyun * R1298 (0x512) - Audio IF 1_19 2553*4882a593Smuzhiyun */ 2554*4882a593Smuzhiyun #define WM5100_AIF1RX2_SLOT_MASK 0x003F /* AIF1RX2_SLOT - [5:0] */ 2555*4882a593Smuzhiyun #define WM5100_AIF1RX2_SLOT_SHIFT 0 /* AIF1RX2_SLOT - [5:0] */ 2556*4882a593Smuzhiyun #define WM5100_AIF1RX2_SLOT_WIDTH 6 /* AIF1RX2_SLOT - [5:0] */ 2557*4882a593Smuzhiyun 2558*4882a593Smuzhiyun /* 2559*4882a593Smuzhiyun * R1299 (0x513) - Audio IF 1_20 2560*4882a593Smuzhiyun */ 2561*4882a593Smuzhiyun #define WM5100_AIF1RX3_SLOT_MASK 0x003F /* AIF1RX3_SLOT - [5:0] */ 2562*4882a593Smuzhiyun #define WM5100_AIF1RX3_SLOT_SHIFT 0 /* AIF1RX3_SLOT - [5:0] */ 2563*4882a593Smuzhiyun #define WM5100_AIF1RX3_SLOT_WIDTH 6 /* AIF1RX3_SLOT - [5:0] */ 2564*4882a593Smuzhiyun 2565*4882a593Smuzhiyun /* 2566*4882a593Smuzhiyun * R1300 (0x514) - Audio IF 1_21 2567*4882a593Smuzhiyun */ 2568*4882a593Smuzhiyun #define WM5100_AIF1RX4_SLOT_MASK 0x003F /* AIF1RX4_SLOT - [5:0] */ 2569*4882a593Smuzhiyun #define WM5100_AIF1RX4_SLOT_SHIFT 0 /* AIF1RX4_SLOT - [5:0] */ 2570*4882a593Smuzhiyun #define WM5100_AIF1RX4_SLOT_WIDTH 6 /* AIF1RX4_SLOT - [5:0] */ 2571*4882a593Smuzhiyun 2572*4882a593Smuzhiyun /* 2573*4882a593Smuzhiyun * R1301 (0x515) - Audio IF 1_22 2574*4882a593Smuzhiyun */ 2575*4882a593Smuzhiyun #define WM5100_AIF1RX5_SLOT_MASK 0x003F /* AIF1RX5_SLOT - [5:0] */ 2576*4882a593Smuzhiyun #define WM5100_AIF1RX5_SLOT_SHIFT 0 /* AIF1RX5_SLOT - [5:0] */ 2577*4882a593Smuzhiyun #define WM5100_AIF1RX5_SLOT_WIDTH 6 /* AIF1RX5_SLOT - [5:0] */ 2578*4882a593Smuzhiyun 2579*4882a593Smuzhiyun /* 2580*4882a593Smuzhiyun * R1302 (0x516) - Audio IF 1_23 2581*4882a593Smuzhiyun */ 2582*4882a593Smuzhiyun #define WM5100_AIF1RX6_SLOT_MASK 0x003F /* AIF1RX6_SLOT - [5:0] */ 2583*4882a593Smuzhiyun #define WM5100_AIF1RX6_SLOT_SHIFT 0 /* AIF1RX6_SLOT - [5:0] */ 2584*4882a593Smuzhiyun #define WM5100_AIF1RX6_SLOT_WIDTH 6 /* AIF1RX6_SLOT - [5:0] */ 2585*4882a593Smuzhiyun 2586*4882a593Smuzhiyun /* 2587*4882a593Smuzhiyun * R1303 (0x517) - Audio IF 1_24 2588*4882a593Smuzhiyun */ 2589*4882a593Smuzhiyun #define WM5100_AIF1RX7_SLOT_MASK 0x003F /* AIF1RX7_SLOT - [5:0] */ 2590*4882a593Smuzhiyun #define WM5100_AIF1RX7_SLOT_SHIFT 0 /* AIF1RX7_SLOT - [5:0] */ 2591*4882a593Smuzhiyun #define WM5100_AIF1RX7_SLOT_WIDTH 6 /* AIF1RX7_SLOT - [5:0] */ 2592*4882a593Smuzhiyun 2593*4882a593Smuzhiyun /* 2594*4882a593Smuzhiyun * R1304 (0x518) - Audio IF 1_25 2595*4882a593Smuzhiyun */ 2596*4882a593Smuzhiyun #define WM5100_AIF1RX8_SLOT_MASK 0x003F /* AIF1RX8_SLOT - [5:0] */ 2597*4882a593Smuzhiyun #define WM5100_AIF1RX8_SLOT_SHIFT 0 /* AIF1RX8_SLOT - [5:0] */ 2598*4882a593Smuzhiyun #define WM5100_AIF1RX8_SLOT_WIDTH 6 /* AIF1RX8_SLOT - [5:0] */ 2599*4882a593Smuzhiyun 2600*4882a593Smuzhiyun /* 2601*4882a593Smuzhiyun * R1305 (0x519) - Audio IF 1_26 2602*4882a593Smuzhiyun */ 2603*4882a593Smuzhiyun #define WM5100_AIF1TX8_ENA 0x0080 /* AIF1TX8_ENA */ 2604*4882a593Smuzhiyun #define WM5100_AIF1TX8_ENA_MASK 0x0080 /* AIF1TX8_ENA */ 2605*4882a593Smuzhiyun #define WM5100_AIF1TX8_ENA_SHIFT 7 /* AIF1TX8_ENA */ 2606*4882a593Smuzhiyun #define WM5100_AIF1TX8_ENA_WIDTH 1 /* AIF1TX8_ENA */ 2607*4882a593Smuzhiyun #define WM5100_AIF1TX7_ENA 0x0040 /* AIF1TX7_ENA */ 2608*4882a593Smuzhiyun #define WM5100_AIF1TX7_ENA_MASK 0x0040 /* AIF1TX7_ENA */ 2609*4882a593Smuzhiyun #define WM5100_AIF1TX7_ENA_SHIFT 6 /* AIF1TX7_ENA */ 2610*4882a593Smuzhiyun #define WM5100_AIF1TX7_ENA_WIDTH 1 /* AIF1TX7_ENA */ 2611*4882a593Smuzhiyun #define WM5100_AIF1TX6_ENA 0x0020 /* AIF1TX6_ENA */ 2612*4882a593Smuzhiyun #define WM5100_AIF1TX6_ENA_MASK 0x0020 /* AIF1TX6_ENA */ 2613*4882a593Smuzhiyun #define WM5100_AIF1TX6_ENA_SHIFT 5 /* AIF1TX6_ENA */ 2614*4882a593Smuzhiyun #define WM5100_AIF1TX6_ENA_WIDTH 1 /* AIF1TX6_ENA */ 2615*4882a593Smuzhiyun #define WM5100_AIF1TX5_ENA 0x0010 /* AIF1TX5_ENA */ 2616*4882a593Smuzhiyun #define WM5100_AIF1TX5_ENA_MASK 0x0010 /* AIF1TX5_ENA */ 2617*4882a593Smuzhiyun #define WM5100_AIF1TX5_ENA_SHIFT 4 /* AIF1TX5_ENA */ 2618*4882a593Smuzhiyun #define WM5100_AIF1TX5_ENA_WIDTH 1 /* AIF1TX5_ENA */ 2619*4882a593Smuzhiyun #define WM5100_AIF1TX4_ENA 0x0008 /* AIF1TX4_ENA */ 2620*4882a593Smuzhiyun #define WM5100_AIF1TX4_ENA_MASK 0x0008 /* AIF1TX4_ENA */ 2621*4882a593Smuzhiyun #define WM5100_AIF1TX4_ENA_SHIFT 3 /* AIF1TX4_ENA */ 2622*4882a593Smuzhiyun #define WM5100_AIF1TX4_ENA_WIDTH 1 /* AIF1TX4_ENA */ 2623*4882a593Smuzhiyun #define WM5100_AIF1TX3_ENA 0x0004 /* AIF1TX3_ENA */ 2624*4882a593Smuzhiyun #define WM5100_AIF1TX3_ENA_MASK 0x0004 /* AIF1TX3_ENA */ 2625*4882a593Smuzhiyun #define WM5100_AIF1TX3_ENA_SHIFT 2 /* AIF1TX3_ENA */ 2626*4882a593Smuzhiyun #define WM5100_AIF1TX3_ENA_WIDTH 1 /* AIF1TX3_ENA */ 2627*4882a593Smuzhiyun #define WM5100_AIF1TX2_ENA 0x0002 /* AIF1TX2_ENA */ 2628*4882a593Smuzhiyun #define WM5100_AIF1TX2_ENA_MASK 0x0002 /* AIF1TX2_ENA */ 2629*4882a593Smuzhiyun #define WM5100_AIF1TX2_ENA_SHIFT 1 /* AIF1TX2_ENA */ 2630*4882a593Smuzhiyun #define WM5100_AIF1TX2_ENA_WIDTH 1 /* AIF1TX2_ENA */ 2631*4882a593Smuzhiyun #define WM5100_AIF1TX1_ENA 0x0001 /* AIF1TX1_ENA */ 2632*4882a593Smuzhiyun #define WM5100_AIF1TX1_ENA_MASK 0x0001 /* AIF1TX1_ENA */ 2633*4882a593Smuzhiyun #define WM5100_AIF1TX1_ENA_SHIFT 0 /* AIF1TX1_ENA */ 2634*4882a593Smuzhiyun #define WM5100_AIF1TX1_ENA_WIDTH 1 /* AIF1TX1_ENA */ 2635*4882a593Smuzhiyun 2636*4882a593Smuzhiyun /* 2637*4882a593Smuzhiyun * R1306 (0x51A) - Audio IF 1_27 2638*4882a593Smuzhiyun */ 2639*4882a593Smuzhiyun #define WM5100_AIF1RX8_ENA 0x0080 /* AIF1RX8_ENA */ 2640*4882a593Smuzhiyun #define WM5100_AIF1RX8_ENA_MASK 0x0080 /* AIF1RX8_ENA */ 2641*4882a593Smuzhiyun #define WM5100_AIF1RX8_ENA_SHIFT 7 /* AIF1RX8_ENA */ 2642*4882a593Smuzhiyun #define WM5100_AIF1RX8_ENA_WIDTH 1 /* AIF1RX8_ENA */ 2643*4882a593Smuzhiyun #define WM5100_AIF1RX7_ENA 0x0040 /* AIF1RX7_ENA */ 2644*4882a593Smuzhiyun #define WM5100_AIF1RX7_ENA_MASK 0x0040 /* AIF1RX7_ENA */ 2645*4882a593Smuzhiyun #define WM5100_AIF1RX7_ENA_SHIFT 6 /* AIF1RX7_ENA */ 2646*4882a593Smuzhiyun #define WM5100_AIF1RX7_ENA_WIDTH 1 /* AIF1RX7_ENA */ 2647*4882a593Smuzhiyun #define WM5100_AIF1RX6_ENA 0x0020 /* AIF1RX6_ENA */ 2648*4882a593Smuzhiyun #define WM5100_AIF1RX6_ENA_MASK 0x0020 /* AIF1RX6_ENA */ 2649*4882a593Smuzhiyun #define WM5100_AIF1RX6_ENA_SHIFT 5 /* AIF1RX6_ENA */ 2650*4882a593Smuzhiyun #define WM5100_AIF1RX6_ENA_WIDTH 1 /* AIF1RX6_ENA */ 2651*4882a593Smuzhiyun #define WM5100_AIF1RX5_ENA 0x0010 /* AIF1RX5_ENA */ 2652*4882a593Smuzhiyun #define WM5100_AIF1RX5_ENA_MASK 0x0010 /* AIF1RX5_ENA */ 2653*4882a593Smuzhiyun #define WM5100_AIF1RX5_ENA_SHIFT 4 /* AIF1RX5_ENA */ 2654*4882a593Smuzhiyun #define WM5100_AIF1RX5_ENA_WIDTH 1 /* AIF1RX5_ENA */ 2655*4882a593Smuzhiyun #define WM5100_AIF1RX4_ENA 0x0008 /* AIF1RX4_ENA */ 2656*4882a593Smuzhiyun #define WM5100_AIF1RX4_ENA_MASK 0x0008 /* AIF1RX4_ENA */ 2657*4882a593Smuzhiyun #define WM5100_AIF1RX4_ENA_SHIFT 3 /* AIF1RX4_ENA */ 2658*4882a593Smuzhiyun #define WM5100_AIF1RX4_ENA_WIDTH 1 /* AIF1RX4_ENA */ 2659*4882a593Smuzhiyun #define WM5100_AIF1RX3_ENA 0x0004 /* AIF1RX3_ENA */ 2660*4882a593Smuzhiyun #define WM5100_AIF1RX3_ENA_MASK 0x0004 /* AIF1RX3_ENA */ 2661*4882a593Smuzhiyun #define WM5100_AIF1RX3_ENA_SHIFT 2 /* AIF1RX3_ENA */ 2662*4882a593Smuzhiyun #define WM5100_AIF1RX3_ENA_WIDTH 1 /* AIF1RX3_ENA */ 2663*4882a593Smuzhiyun #define WM5100_AIF1RX2_ENA 0x0002 /* AIF1RX2_ENA */ 2664*4882a593Smuzhiyun #define WM5100_AIF1RX2_ENA_MASK 0x0002 /* AIF1RX2_ENA */ 2665*4882a593Smuzhiyun #define WM5100_AIF1RX2_ENA_SHIFT 1 /* AIF1RX2_ENA */ 2666*4882a593Smuzhiyun #define WM5100_AIF1RX2_ENA_WIDTH 1 /* AIF1RX2_ENA */ 2667*4882a593Smuzhiyun #define WM5100_AIF1RX1_ENA 0x0001 /* AIF1RX1_ENA */ 2668*4882a593Smuzhiyun #define WM5100_AIF1RX1_ENA_MASK 0x0001 /* AIF1RX1_ENA */ 2669*4882a593Smuzhiyun #define WM5100_AIF1RX1_ENA_SHIFT 0 /* AIF1RX1_ENA */ 2670*4882a593Smuzhiyun #define WM5100_AIF1RX1_ENA_WIDTH 1 /* AIF1RX1_ENA */ 2671*4882a593Smuzhiyun 2672*4882a593Smuzhiyun /* 2673*4882a593Smuzhiyun * R1344 (0x540) - Audio IF 2_1 2674*4882a593Smuzhiyun */ 2675*4882a593Smuzhiyun #define WM5100_AIF2_BCLK_INV 0x0080 /* AIF2_BCLK_INV */ 2676*4882a593Smuzhiyun #define WM5100_AIF2_BCLK_INV_MASK 0x0080 /* AIF2_BCLK_INV */ 2677*4882a593Smuzhiyun #define WM5100_AIF2_BCLK_INV_SHIFT 7 /* AIF2_BCLK_INV */ 2678*4882a593Smuzhiyun #define WM5100_AIF2_BCLK_INV_WIDTH 1 /* AIF2_BCLK_INV */ 2679*4882a593Smuzhiyun #define WM5100_AIF2_BCLK_FRC 0x0040 /* AIF2_BCLK_FRC */ 2680*4882a593Smuzhiyun #define WM5100_AIF2_BCLK_FRC_MASK 0x0040 /* AIF2_BCLK_FRC */ 2681*4882a593Smuzhiyun #define WM5100_AIF2_BCLK_FRC_SHIFT 6 /* AIF2_BCLK_FRC */ 2682*4882a593Smuzhiyun #define WM5100_AIF2_BCLK_FRC_WIDTH 1 /* AIF2_BCLK_FRC */ 2683*4882a593Smuzhiyun #define WM5100_AIF2_BCLK_MSTR 0x0020 /* AIF2_BCLK_MSTR */ 2684*4882a593Smuzhiyun #define WM5100_AIF2_BCLK_MSTR_MASK 0x0020 /* AIF2_BCLK_MSTR */ 2685*4882a593Smuzhiyun #define WM5100_AIF2_BCLK_MSTR_SHIFT 5 /* AIF2_BCLK_MSTR */ 2686*4882a593Smuzhiyun #define WM5100_AIF2_BCLK_MSTR_WIDTH 1 /* AIF2_BCLK_MSTR */ 2687*4882a593Smuzhiyun #define WM5100_AIF2_BCLK_FREQ_MASK 0x001F /* AIF2_BCLK_FREQ - [4:0] */ 2688*4882a593Smuzhiyun #define WM5100_AIF2_BCLK_FREQ_SHIFT 0 /* AIF2_BCLK_FREQ - [4:0] */ 2689*4882a593Smuzhiyun #define WM5100_AIF2_BCLK_FREQ_WIDTH 5 /* AIF2_BCLK_FREQ - [4:0] */ 2690*4882a593Smuzhiyun 2691*4882a593Smuzhiyun /* 2692*4882a593Smuzhiyun * R1345 (0x541) - Audio IF 2_2 2693*4882a593Smuzhiyun */ 2694*4882a593Smuzhiyun #define WM5100_AIF2TX_DAT_TRI 0x0020 /* AIF2TX_DAT_TRI */ 2695*4882a593Smuzhiyun #define WM5100_AIF2TX_DAT_TRI_MASK 0x0020 /* AIF2TX_DAT_TRI */ 2696*4882a593Smuzhiyun #define WM5100_AIF2TX_DAT_TRI_SHIFT 5 /* AIF2TX_DAT_TRI */ 2697*4882a593Smuzhiyun #define WM5100_AIF2TX_DAT_TRI_WIDTH 1 /* AIF2TX_DAT_TRI */ 2698*4882a593Smuzhiyun #define WM5100_AIF2TX_LRCLK_SRC 0x0008 /* AIF2TX_LRCLK_SRC */ 2699*4882a593Smuzhiyun #define WM5100_AIF2TX_LRCLK_SRC_MASK 0x0008 /* AIF2TX_LRCLK_SRC */ 2700*4882a593Smuzhiyun #define WM5100_AIF2TX_LRCLK_SRC_SHIFT 3 /* AIF2TX_LRCLK_SRC */ 2701*4882a593Smuzhiyun #define WM5100_AIF2TX_LRCLK_SRC_WIDTH 1 /* AIF2TX_LRCLK_SRC */ 2702*4882a593Smuzhiyun #define WM5100_AIF2TX_LRCLK_INV 0x0004 /* AIF2TX_LRCLK_INV */ 2703*4882a593Smuzhiyun #define WM5100_AIF2TX_LRCLK_INV_MASK 0x0004 /* AIF2TX_LRCLK_INV */ 2704*4882a593Smuzhiyun #define WM5100_AIF2TX_LRCLK_INV_SHIFT 2 /* AIF2TX_LRCLK_INV */ 2705*4882a593Smuzhiyun #define WM5100_AIF2TX_LRCLK_INV_WIDTH 1 /* AIF2TX_LRCLK_INV */ 2706*4882a593Smuzhiyun #define WM5100_AIF2TX_LRCLK_FRC 0x0002 /* AIF2TX_LRCLK_FRC */ 2707*4882a593Smuzhiyun #define WM5100_AIF2TX_LRCLK_FRC_MASK 0x0002 /* AIF2TX_LRCLK_FRC */ 2708*4882a593Smuzhiyun #define WM5100_AIF2TX_LRCLK_FRC_SHIFT 1 /* AIF2TX_LRCLK_FRC */ 2709*4882a593Smuzhiyun #define WM5100_AIF2TX_LRCLK_FRC_WIDTH 1 /* AIF2TX_LRCLK_FRC */ 2710*4882a593Smuzhiyun #define WM5100_AIF2TX_LRCLK_MSTR 0x0001 /* AIF2TX_LRCLK_MSTR */ 2711*4882a593Smuzhiyun #define WM5100_AIF2TX_LRCLK_MSTR_MASK 0x0001 /* AIF2TX_LRCLK_MSTR */ 2712*4882a593Smuzhiyun #define WM5100_AIF2TX_LRCLK_MSTR_SHIFT 0 /* AIF2TX_LRCLK_MSTR */ 2713*4882a593Smuzhiyun #define WM5100_AIF2TX_LRCLK_MSTR_WIDTH 1 /* AIF2TX_LRCLK_MSTR */ 2714*4882a593Smuzhiyun 2715*4882a593Smuzhiyun /* 2716*4882a593Smuzhiyun * R1346 (0x542) - Audio IF 2_3 2717*4882a593Smuzhiyun */ 2718*4882a593Smuzhiyun #define WM5100_AIF2RX_LRCLK_INV 0x0004 /* AIF2RX_LRCLK_INV */ 2719*4882a593Smuzhiyun #define WM5100_AIF2RX_LRCLK_INV_MASK 0x0004 /* AIF2RX_LRCLK_INV */ 2720*4882a593Smuzhiyun #define WM5100_AIF2RX_LRCLK_INV_SHIFT 2 /* AIF2RX_LRCLK_INV */ 2721*4882a593Smuzhiyun #define WM5100_AIF2RX_LRCLK_INV_WIDTH 1 /* AIF2RX_LRCLK_INV */ 2722*4882a593Smuzhiyun #define WM5100_AIF2RX_LRCLK_FRC 0x0002 /* AIF2RX_LRCLK_FRC */ 2723*4882a593Smuzhiyun #define WM5100_AIF2RX_LRCLK_FRC_MASK 0x0002 /* AIF2RX_LRCLK_FRC */ 2724*4882a593Smuzhiyun #define WM5100_AIF2RX_LRCLK_FRC_SHIFT 1 /* AIF2RX_LRCLK_FRC */ 2725*4882a593Smuzhiyun #define WM5100_AIF2RX_LRCLK_FRC_WIDTH 1 /* AIF2RX_LRCLK_FRC */ 2726*4882a593Smuzhiyun #define WM5100_AIF2RX_LRCLK_MSTR 0x0001 /* AIF2RX_LRCLK_MSTR */ 2727*4882a593Smuzhiyun #define WM5100_AIF2RX_LRCLK_MSTR_MASK 0x0001 /* AIF2RX_LRCLK_MSTR */ 2728*4882a593Smuzhiyun #define WM5100_AIF2RX_LRCLK_MSTR_SHIFT 0 /* AIF2RX_LRCLK_MSTR */ 2729*4882a593Smuzhiyun #define WM5100_AIF2RX_LRCLK_MSTR_WIDTH 1 /* AIF2RX_LRCLK_MSTR */ 2730*4882a593Smuzhiyun 2731*4882a593Smuzhiyun /* 2732*4882a593Smuzhiyun * R1347 (0x543) - Audio IF 2_4 2733*4882a593Smuzhiyun */ 2734*4882a593Smuzhiyun #define WM5100_AIF2_TRI 0x0040 /* AIF2_TRI */ 2735*4882a593Smuzhiyun #define WM5100_AIF2_TRI_MASK 0x0040 /* AIF2_TRI */ 2736*4882a593Smuzhiyun #define WM5100_AIF2_TRI_SHIFT 6 /* AIF2_TRI */ 2737*4882a593Smuzhiyun #define WM5100_AIF2_TRI_WIDTH 1 /* AIF2_TRI */ 2738*4882a593Smuzhiyun #define WM5100_AIF2_RATE_MASK 0x0003 /* AIF2_RATE - [1:0] */ 2739*4882a593Smuzhiyun #define WM5100_AIF2_RATE_SHIFT 0 /* AIF2_RATE - [1:0] */ 2740*4882a593Smuzhiyun #define WM5100_AIF2_RATE_WIDTH 2 /* AIF2_RATE - [1:0] */ 2741*4882a593Smuzhiyun 2742*4882a593Smuzhiyun /* 2743*4882a593Smuzhiyun * R1348 (0x544) - Audio IF 2_5 2744*4882a593Smuzhiyun */ 2745*4882a593Smuzhiyun #define WM5100_AIF2_FMT_MASK 0x0007 /* AIF2_FMT - [2:0] */ 2746*4882a593Smuzhiyun #define WM5100_AIF2_FMT_SHIFT 0 /* AIF2_FMT - [2:0] */ 2747*4882a593Smuzhiyun #define WM5100_AIF2_FMT_WIDTH 3 /* AIF2_FMT - [2:0] */ 2748*4882a593Smuzhiyun 2749*4882a593Smuzhiyun /* 2750*4882a593Smuzhiyun * R1349 (0x545) - Audio IF 2_6 2751*4882a593Smuzhiyun */ 2752*4882a593Smuzhiyun #define WM5100_AIF2TX_BCPF_MASK 0x1FFF /* AIF2TX_BCPF - [12:0] */ 2753*4882a593Smuzhiyun #define WM5100_AIF2TX_BCPF_SHIFT 0 /* AIF2TX_BCPF - [12:0] */ 2754*4882a593Smuzhiyun #define WM5100_AIF2TX_BCPF_WIDTH 13 /* AIF2TX_BCPF - [12:0] */ 2755*4882a593Smuzhiyun 2756*4882a593Smuzhiyun /* 2757*4882a593Smuzhiyun * R1350 (0x546) - Audio IF 2_7 2758*4882a593Smuzhiyun */ 2759*4882a593Smuzhiyun #define WM5100_AIF2RX_BCPF_MASK 0x1FFF /* AIF2RX_BCPF - [12:0] */ 2760*4882a593Smuzhiyun #define WM5100_AIF2RX_BCPF_SHIFT 0 /* AIF2RX_BCPF - [12:0] */ 2761*4882a593Smuzhiyun #define WM5100_AIF2RX_BCPF_WIDTH 13 /* AIF2RX_BCPF - [12:0] */ 2762*4882a593Smuzhiyun 2763*4882a593Smuzhiyun /* 2764*4882a593Smuzhiyun * R1351 (0x547) - Audio IF 2_8 2765*4882a593Smuzhiyun */ 2766*4882a593Smuzhiyun #define WM5100_AIF2TX_WL_MASK 0x3F00 /* AIF2TX_WL - [13:8] */ 2767*4882a593Smuzhiyun #define WM5100_AIF2TX_WL_SHIFT 8 /* AIF2TX_WL - [13:8] */ 2768*4882a593Smuzhiyun #define WM5100_AIF2TX_WL_WIDTH 6 /* AIF2TX_WL - [13:8] */ 2769*4882a593Smuzhiyun #define WM5100_AIF2TX_SLOT_LEN_MASK 0x00FF /* AIF2TX_SLOT_LEN - [7:0] */ 2770*4882a593Smuzhiyun #define WM5100_AIF2TX_SLOT_LEN_SHIFT 0 /* AIF2TX_SLOT_LEN - [7:0] */ 2771*4882a593Smuzhiyun #define WM5100_AIF2TX_SLOT_LEN_WIDTH 8 /* AIF2TX_SLOT_LEN - [7:0] */ 2772*4882a593Smuzhiyun 2773*4882a593Smuzhiyun /* 2774*4882a593Smuzhiyun * R1352 (0x548) - Audio IF 2_9 2775*4882a593Smuzhiyun */ 2776*4882a593Smuzhiyun #define WM5100_AIF2RX_WL_MASK 0x3F00 /* AIF2RX_WL - [13:8] */ 2777*4882a593Smuzhiyun #define WM5100_AIF2RX_WL_SHIFT 8 /* AIF2RX_WL - [13:8] */ 2778*4882a593Smuzhiyun #define WM5100_AIF2RX_WL_WIDTH 6 /* AIF2RX_WL - [13:8] */ 2779*4882a593Smuzhiyun #define WM5100_AIF2RX_SLOT_LEN_MASK 0x00FF /* AIF2RX_SLOT_LEN - [7:0] */ 2780*4882a593Smuzhiyun #define WM5100_AIF2RX_SLOT_LEN_SHIFT 0 /* AIF2RX_SLOT_LEN - [7:0] */ 2781*4882a593Smuzhiyun #define WM5100_AIF2RX_SLOT_LEN_WIDTH 8 /* AIF2RX_SLOT_LEN - [7:0] */ 2782*4882a593Smuzhiyun 2783*4882a593Smuzhiyun /* 2784*4882a593Smuzhiyun * R1353 (0x549) - Audio IF 2_10 2785*4882a593Smuzhiyun */ 2786*4882a593Smuzhiyun #define WM5100_AIF2TX1_SLOT_MASK 0x003F /* AIF2TX1_SLOT - [5:0] */ 2787*4882a593Smuzhiyun #define WM5100_AIF2TX1_SLOT_SHIFT 0 /* AIF2TX1_SLOT - [5:0] */ 2788*4882a593Smuzhiyun #define WM5100_AIF2TX1_SLOT_WIDTH 6 /* AIF2TX1_SLOT - [5:0] */ 2789*4882a593Smuzhiyun 2790*4882a593Smuzhiyun /* 2791*4882a593Smuzhiyun * R1354 (0x54A) - Audio IF 2_11 2792*4882a593Smuzhiyun */ 2793*4882a593Smuzhiyun #define WM5100_AIF2TX2_SLOT_MASK 0x003F /* AIF2TX2_SLOT - [5:0] */ 2794*4882a593Smuzhiyun #define WM5100_AIF2TX2_SLOT_SHIFT 0 /* AIF2TX2_SLOT - [5:0] */ 2795*4882a593Smuzhiyun #define WM5100_AIF2TX2_SLOT_WIDTH 6 /* AIF2TX2_SLOT - [5:0] */ 2796*4882a593Smuzhiyun 2797*4882a593Smuzhiyun /* 2798*4882a593Smuzhiyun * R1361 (0x551) - Audio IF 2_18 2799*4882a593Smuzhiyun */ 2800*4882a593Smuzhiyun #define WM5100_AIF2RX1_SLOT_MASK 0x003F /* AIF2RX1_SLOT - [5:0] */ 2801*4882a593Smuzhiyun #define WM5100_AIF2RX1_SLOT_SHIFT 0 /* AIF2RX1_SLOT - [5:0] */ 2802*4882a593Smuzhiyun #define WM5100_AIF2RX1_SLOT_WIDTH 6 /* AIF2RX1_SLOT - [5:0] */ 2803*4882a593Smuzhiyun 2804*4882a593Smuzhiyun /* 2805*4882a593Smuzhiyun * R1362 (0x552) - Audio IF 2_19 2806*4882a593Smuzhiyun */ 2807*4882a593Smuzhiyun #define WM5100_AIF2RX2_SLOT_MASK 0x003F /* AIF2RX2_SLOT - [5:0] */ 2808*4882a593Smuzhiyun #define WM5100_AIF2RX2_SLOT_SHIFT 0 /* AIF2RX2_SLOT - [5:0] */ 2809*4882a593Smuzhiyun #define WM5100_AIF2RX2_SLOT_WIDTH 6 /* AIF2RX2_SLOT - [5:0] */ 2810*4882a593Smuzhiyun 2811*4882a593Smuzhiyun /* 2812*4882a593Smuzhiyun * R1369 (0x559) - Audio IF 2_26 2813*4882a593Smuzhiyun */ 2814*4882a593Smuzhiyun #define WM5100_AIF2TX2_ENA 0x0002 /* AIF2TX2_ENA */ 2815*4882a593Smuzhiyun #define WM5100_AIF2TX2_ENA_MASK 0x0002 /* AIF2TX2_ENA */ 2816*4882a593Smuzhiyun #define WM5100_AIF2TX2_ENA_SHIFT 1 /* AIF2TX2_ENA */ 2817*4882a593Smuzhiyun #define WM5100_AIF2TX2_ENA_WIDTH 1 /* AIF2TX2_ENA */ 2818*4882a593Smuzhiyun #define WM5100_AIF2TX1_ENA 0x0001 /* AIF2TX1_ENA */ 2819*4882a593Smuzhiyun #define WM5100_AIF2TX1_ENA_MASK 0x0001 /* AIF2TX1_ENA */ 2820*4882a593Smuzhiyun #define WM5100_AIF2TX1_ENA_SHIFT 0 /* AIF2TX1_ENA */ 2821*4882a593Smuzhiyun #define WM5100_AIF2TX1_ENA_WIDTH 1 /* AIF2TX1_ENA */ 2822*4882a593Smuzhiyun 2823*4882a593Smuzhiyun /* 2824*4882a593Smuzhiyun * R1370 (0x55A) - Audio IF 2_27 2825*4882a593Smuzhiyun */ 2826*4882a593Smuzhiyun #define WM5100_AIF2RX2_ENA 0x0002 /* AIF2RX2_ENA */ 2827*4882a593Smuzhiyun #define WM5100_AIF2RX2_ENA_MASK 0x0002 /* AIF2RX2_ENA */ 2828*4882a593Smuzhiyun #define WM5100_AIF2RX2_ENA_SHIFT 1 /* AIF2RX2_ENA */ 2829*4882a593Smuzhiyun #define WM5100_AIF2RX2_ENA_WIDTH 1 /* AIF2RX2_ENA */ 2830*4882a593Smuzhiyun #define WM5100_AIF2RX1_ENA 0x0001 /* AIF2RX1_ENA */ 2831*4882a593Smuzhiyun #define WM5100_AIF2RX1_ENA_MASK 0x0001 /* AIF2RX1_ENA */ 2832*4882a593Smuzhiyun #define WM5100_AIF2RX1_ENA_SHIFT 0 /* AIF2RX1_ENA */ 2833*4882a593Smuzhiyun #define WM5100_AIF2RX1_ENA_WIDTH 1 /* AIF2RX1_ENA */ 2834*4882a593Smuzhiyun 2835*4882a593Smuzhiyun /* 2836*4882a593Smuzhiyun * R1408 (0x580) - Audio IF 3_1 2837*4882a593Smuzhiyun */ 2838*4882a593Smuzhiyun #define WM5100_AIF3_BCLK_INV 0x0080 /* AIF3_BCLK_INV */ 2839*4882a593Smuzhiyun #define WM5100_AIF3_BCLK_INV_MASK 0x0080 /* AIF3_BCLK_INV */ 2840*4882a593Smuzhiyun #define WM5100_AIF3_BCLK_INV_SHIFT 7 /* AIF3_BCLK_INV */ 2841*4882a593Smuzhiyun #define WM5100_AIF3_BCLK_INV_WIDTH 1 /* AIF3_BCLK_INV */ 2842*4882a593Smuzhiyun #define WM5100_AIF3_BCLK_FRC 0x0040 /* AIF3_BCLK_FRC */ 2843*4882a593Smuzhiyun #define WM5100_AIF3_BCLK_FRC_MASK 0x0040 /* AIF3_BCLK_FRC */ 2844*4882a593Smuzhiyun #define WM5100_AIF3_BCLK_FRC_SHIFT 6 /* AIF3_BCLK_FRC */ 2845*4882a593Smuzhiyun #define WM5100_AIF3_BCLK_FRC_WIDTH 1 /* AIF3_BCLK_FRC */ 2846*4882a593Smuzhiyun #define WM5100_AIF3_BCLK_MSTR 0x0020 /* AIF3_BCLK_MSTR */ 2847*4882a593Smuzhiyun #define WM5100_AIF3_BCLK_MSTR_MASK 0x0020 /* AIF3_BCLK_MSTR */ 2848*4882a593Smuzhiyun #define WM5100_AIF3_BCLK_MSTR_SHIFT 5 /* AIF3_BCLK_MSTR */ 2849*4882a593Smuzhiyun #define WM5100_AIF3_BCLK_MSTR_WIDTH 1 /* AIF3_BCLK_MSTR */ 2850*4882a593Smuzhiyun #define WM5100_AIF3_BCLK_FREQ_MASK 0x001F /* AIF3_BCLK_FREQ - [4:0] */ 2851*4882a593Smuzhiyun #define WM5100_AIF3_BCLK_FREQ_SHIFT 0 /* AIF3_BCLK_FREQ - [4:0] */ 2852*4882a593Smuzhiyun #define WM5100_AIF3_BCLK_FREQ_WIDTH 5 /* AIF3_BCLK_FREQ - [4:0] */ 2853*4882a593Smuzhiyun 2854*4882a593Smuzhiyun /* 2855*4882a593Smuzhiyun * R1409 (0x581) - Audio IF 3_2 2856*4882a593Smuzhiyun */ 2857*4882a593Smuzhiyun #define WM5100_AIF3TX_DAT_TRI 0x0020 /* AIF3TX_DAT_TRI */ 2858*4882a593Smuzhiyun #define WM5100_AIF3TX_DAT_TRI_MASK 0x0020 /* AIF3TX_DAT_TRI */ 2859*4882a593Smuzhiyun #define WM5100_AIF3TX_DAT_TRI_SHIFT 5 /* AIF3TX_DAT_TRI */ 2860*4882a593Smuzhiyun #define WM5100_AIF3TX_DAT_TRI_WIDTH 1 /* AIF3TX_DAT_TRI */ 2861*4882a593Smuzhiyun #define WM5100_AIF3TX_LRCLK_SRC 0x0008 /* AIF3TX_LRCLK_SRC */ 2862*4882a593Smuzhiyun #define WM5100_AIF3TX_LRCLK_SRC_MASK 0x0008 /* AIF3TX_LRCLK_SRC */ 2863*4882a593Smuzhiyun #define WM5100_AIF3TX_LRCLK_SRC_SHIFT 3 /* AIF3TX_LRCLK_SRC */ 2864*4882a593Smuzhiyun #define WM5100_AIF3TX_LRCLK_SRC_WIDTH 1 /* AIF3TX_LRCLK_SRC */ 2865*4882a593Smuzhiyun #define WM5100_AIF3TX_LRCLK_INV 0x0004 /* AIF3TX_LRCLK_INV */ 2866*4882a593Smuzhiyun #define WM5100_AIF3TX_LRCLK_INV_MASK 0x0004 /* AIF3TX_LRCLK_INV */ 2867*4882a593Smuzhiyun #define WM5100_AIF3TX_LRCLK_INV_SHIFT 2 /* AIF3TX_LRCLK_INV */ 2868*4882a593Smuzhiyun #define WM5100_AIF3TX_LRCLK_INV_WIDTH 1 /* AIF3TX_LRCLK_INV */ 2869*4882a593Smuzhiyun #define WM5100_AIF3TX_LRCLK_FRC 0x0002 /* AIF3TX_LRCLK_FRC */ 2870*4882a593Smuzhiyun #define WM5100_AIF3TX_LRCLK_FRC_MASK 0x0002 /* AIF3TX_LRCLK_FRC */ 2871*4882a593Smuzhiyun #define WM5100_AIF3TX_LRCLK_FRC_SHIFT 1 /* AIF3TX_LRCLK_FRC */ 2872*4882a593Smuzhiyun #define WM5100_AIF3TX_LRCLK_FRC_WIDTH 1 /* AIF3TX_LRCLK_FRC */ 2873*4882a593Smuzhiyun #define WM5100_AIF3TX_LRCLK_MSTR 0x0001 /* AIF3TX_LRCLK_MSTR */ 2874*4882a593Smuzhiyun #define WM5100_AIF3TX_LRCLK_MSTR_MASK 0x0001 /* AIF3TX_LRCLK_MSTR */ 2875*4882a593Smuzhiyun #define WM5100_AIF3TX_LRCLK_MSTR_SHIFT 0 /* AIF3TX_LRCLK_MSTR */ 2876*4882a593Smuzhiyun #define WM5100_AIF3TX_LRCLK_MSTR_WIDTH 1 /* AIF3TX_LRCLK_MSTR */ 2877*4882a593Smuzhiyun 2878*4882a593Smuzhiyun /* 2879*4882a593Smuzhiyun * R1410 (0x582) - Audio IF 3_3 2880*4882a593Smuzhiyun */ 2881*4882a593Smuzhiyun #define WM5100_AIF3RX_LRCLK_INV 0x0004 /* AIF3RX_LRCLK_INV */ 2882*4882a593Smuzhiyun #define WM5100_AIF3RX_LRCLK_INV_MASK 0x0004 /* AIF3RX_LRCLK_INV */ 2883*4882a593Smuzhiyun #define WM5100_AIF3RX_LRCLK_INV_SHIFT 2 /* AIF3RX_LRCLK_INV */ 2884*4882a593Smuzhiyun #define WM5100_AIF3RX_LRCLK_INV_WIDTH 1 /* AIF3RX_LRCLK_INV */ 2885*4882a593Smuzhiyun #define WM5100_AIF3RX_LRCLK_FRC 0x0002 /* AIF3RX_LRCLK_FRC */ 2886*4882a593Smuzhiyun #define WM5100_AIF3RX_LRCLK_FRC_MASK 0x0002 /* AIF3RX_LRCLK_FRC */ 2887*4882a593Smuzhiyun #define WM5100_AIF3RX_LRCLK_FRC_SHIFT 1 /* AIF3RX_LRCLK_FRC */ 2888*4882a593Smuzhiyun #define WM5100_AIF3RX_LRCLK_FRC_WIDTH 1 /* AIF3RX_LRCLK_FRC */ 2889*4882a593Smuzhiyun #define WM5100_AIF3RX_LRCLK_MSTR 0x0001 /* AIF3RX_LRCLK_MSTR */ 2890*4882a593Smuzhiyun #define WM5100_AIF3RX_LRCLK_MSTR_MASK 0x0001 /* AIF3RX_LRCLK_MSTR */ 2891*4882a593Smuzhiyun #define WM5100_AIF3RX_LRCLK_MSTR_SHIFT 0 /* AIF3RX_LRCLK_MSTR */ 2892*4882a593Smuzhiyun #define WM5100_AIF3RX_LRCLK_MSTR_WIDTH 1 /* AIF3RX_LRCLK_MSTR */ 2893*4882a593Smuzhiyun 2894*4882a593Smuzhiyun /* 2895*4882a593Smuzhiyun * R1411 (0x583) - Audio IF 3_4 2896*4882a593Smuzhiyun */ 2897*4882a593Smuzhiyun #define WM5100_AIF3_TRI 0x0040 /* AIF3_TRI */ 2898*4882a593Smuzhiyun #define WM5100_AIF3_TRI_MASK 0x0040 /* AIF3_TRI */ 2899*4882a593Smuzhiyun #define WM5100_AIF3_TRI_SHIFT 6 /* AIF3_TRI */ 2900*4882a593Smuzhiyun #define WM5100_AIF3_TRI_WIDTH 1 /* AIF3_TRI */ 2901*4882a593Smuzhiyun #define WM5100_AIF3_RATE_MASK 0x0003 /* AIF3_RATE - [1:0] */ 2902*4882a593Smuzhiyun #define WM5100_AIF3_RATE_SHIFT 0 /* AIF3_RATE - [1:0] */ 2903*4882a593Smuzhiyun #define WM5100_AIF3_RATE_WIDTH 2 /* AIF3_RATE - [1:0] */ 2904*4882a593Smuzhiyun 2905*4882a593Smuzhiyun /* 2906*4882a593Smuzhiyun * R1412 (0x584) - Audio IF 3_5 2907*4882a593Smuzhiyun */ 2908*4882a593Smuzhiyun #define WM5100_AIF3_FMT_MASK 0x0007 /* AIF3_FMT - [2:0] */ 2909*4882a593Smuzhiyun #define WM5100_AIF3_FMT_SHIFT 0 /* AIF3_FMT - [2:0] */ 2910*4882a593Smuzhiyun #define WM5100_AIF3_FMT_WIDTH 3 /* AIF3_FMT - [2:0] */ 2911*4882a593Smuzhiyun 2912*4882a593Smuzhiyun /* 2913*4882a593Smuzhiyun * R1413 (0x585) - Audio IF 3_6 2914*4882a593Smuzhiyun */ 2915*4882a593Smuzhiyun #define WM5100_AIF3TX_BCPF_MASK 0x1FFF /* AIF3TX_BCPF - [12:0] */ 2916*4882a593Smuzhiyun #define WM5100_AIF3TX_BCPF_SHIFT 0 /* AIF3TX_BCPF - [12:0] */ 2917*4882a593Smuzhiyun #define WM5100_AIF3TX_BCPF_WIDTH 13 /* AIF3TX_BCPF - [12:0] */ 2918*4882a593Smuzhiyun 2919*4882a593Smuzhiyun /* 2920*4882a593Smuzhiyun * R1414 (0x586) - Audio IF 3_7 2921*4882a593Smuzhiyun */ 2922*4882a593Smuzhiyun #define WM5100_AIF3RX_BCPF_MASK 0x1FFF /* AIF3RX_BCPF - [12:0] */ 2923*4882a593Smuzhiyun #define WM5100_AIF3RX_BCPF_SHIFT 0 /* AIF3RX_BCPF - [12:0] */ 2924*4882a593Smuzhiyun #define WM5100_AIF3RX_BCPF_WIDTH 13 /* AIF3RX_BCPF - [12:0] */ 2925*4882a593Smuzhiyun 2926*4882a593Smuzhiyun /* 2927*4882a593Smuzhiyun * R1415 (0x587) - Audio IF 3_8 2928*4882a593Smuzhiyun */ 2929*4882a593Smuzhiyun #define WM5100_AIF3TX_WL_MASK 0x3F00 /* AIF3TX_WL - [13:8] */ 2930*4882a593Smuzhiyun #define WM5100_AIF3TX_WL_SHIFT 8 /* AIF3TX_WL - [13:8] */ 2931*4882a593Smuzhiyun #define WM5100_AIF3TX_WL_WIDTH 6 /* AIF3TX_WL - [13:8] */ 2932*4882a593Smuzhiyun #define WM5100_AIF3TX_SLOT_LEN_MASK 0x00FF /* AIF3TX_SLOT_LEN - [7:0] */ 2933*4882a593Smuzhiyun #define WM5100_AIF3TX_SLOT_LEN_SHIFT 0 /* AIF3TX_SLOT_LEN - [7:0] */ 2934*4882a593Smuzhiyun #define WM5100_AIF3TX_SLOT_LEN_WIDTH 8 /* AIF3TX_SLOT_LEN - [7:0] */ 2935*4882a593Smuzhiyun 2936*4882a593Smuzhiyun /* 2937*4882a593Smuzhiyun * R1416 (0x588) - Audio IF 3_9 2938*4882a593Smuzhiyun */ 2939*4882a593Smuzhiyun #define WM5100_AIF3RX_WL_MASK 0x3F00 /* AIF3RX_WL - [13:8] */ 2940*4882a593Smuzhiyun #define WM5100_AIF3RX_WL_SHIFT 8 /* AIF3RX_WL - [13:8] */ 2941*4882a593Smuzhiyun #define WM5100_AIF3RX_WL_WIDTH 6 /* AIF3RX_WL - [13:8] */ 2942*4882a593Smuzhiyun #define WM5100_AIF3RX_SLOT_LEN_MASK 0x00FF /* AIF3RX_SLOT_LEN - [7:0] */ 2943*4882a593Smuzhiyun #define WM5100_AIF3RX_SLOT_LEN_SHIFT 0 /* AIF3RX_SLOT_LEN - [7:0] */ 2944*4882a593Smuzhiyun #define WM5100_AIF3RX_SLOT_LEN_WIDTH 8 /* AIF3RX_SLOT_LEN - [7:0] */ 2945*4882a593Smuzhiyun 2946*4882a593Smuzhiyun /* 2947*4882a593Smuzhiyun * R1417 (0x589) - Audio IF 3_10 2948*4882a593Smuzhiyun */ 2949*4882a593Smuzhiyun #define WM5100_AIF3TX1_SLOT_MASK 0x003F /* AIF3TX1_SLOT - [5:0] */ 2950*4882a593Smuzhiyun #define WM5100_AIF3TX1_SLOT_SHIFT 0 /* AIF3TX1_SLOT - [5:0] */ 2951*4882a593Smuzhiyun #define WM5100_AIF3TX1_SLOT_WIDTH 6 /* AIF3TX1_SLOT - [5:0] */ 2952*4882a593Smuzhiyun 2953*4882a593Smuzhiyun /* 2954*4882a593Smuzhiyun * R1418 (0x58A) - Audio IF 3_11 2955*4882a593Smuzhiyun */ 2956*4882a593Smuzhiyun #define WM5100_AIF3TX2_SLOT_MASK 0x003F /* AIF3TX2_SLOT - [5:0] */ 2957*4882a593Smuzhiyun #define WM5100_AIF3TX2_SLOT_SHIFT 0 /* AIF3TX2_SLOT - [5:0] */ 2958*4882a593Smuzhiyun #define WM5100_AIF3TX2_SLOT_WIDTH 6 /* AIF3TX2_SLOT - [5:0] */ 2959*4882a593Smuzhiyun 2960*4882a593Smuzhiyun /* 2961*4882a593Smuzhiyun * R1425 (0x591) - Audio IF 3_18 2962*4882a593Smuzhiyun */ 2963*4882a593Smuzhiyun #define WM5100_AIF3RX1_SLOT_MASK 0x003F /* AIF3RX1_SLOT - [5:0] */ 2964*4882a593Smuzhiyun #define WM5100_AIF3RX1_SLOT_SHIFT 0 /* AIF3RX1_SLOT - [5:0] */ 2965*4882a593Smuzhiyun #define WM5100_AIF3RX1_SLOT_WIDTH 6 /* AIF3RX1_SLOT - [5:0] */ 2966*4882a593Smuzhiyun 2967*4882a593Smuzhiyun /* 2968*4882a593Smuzhiyun * R1426 (0x592) - Audio IF 3_19 2969*4882a593Smuzhiyun */ 2970*4882a593Smuzhiyun #define WM5100_AIF3RX2_SLOT_MASK 0x003F /* AIF3RX2_SLOT - [5:0] */ 2971*4882a593Smuzhiyun #define WM5100_AIF3RX2_SLOT_SHIFT 0 /* AIF3RX2_SLOT - [5:0] */ 2972*4882a593Smuzhiyun #define WM5100_AIF3RX2_SLOT_WIDTH 6 /* AIF3RX2_SLOT - [5:0] */ 2973*4882a593Smuzhiyun 2974*4882a593Smuzhiyun /* 2975*4882a593Smuzhiyun * R1433 (0x599) - Audio IF 3_26 2976*4882a593Smuzhiyun */ 2977*4882a593Smuzhiyun #define WM5100_AIF3TX2_ENA 0x0002 /* AIF3TX2_ENA */ 2978*4882a593Smuzhiyun #define WM5100_AIF3TX2_ENA_MASK 0x0002 /* AIF3TX2_ENA */ 2979*4882a593Smuzhiyun #define WM5100_AIF3TX2_ENA_SHIFT 1 /* AIF3TX2_ENA */ 2980*4882a593Smuzhiyun #define WM5100_AIF3TX2_ENA_WIDTH 1 /* AIF3TX2_ENA */ 2981*4882a593Smuzhiyun #define WM5100_AIF3TX1_ENA 0x0001 /* AIF3TX1_ENA */ 2982*4882a593Smuzhiyun #define WM5100_AIF3TX1_ENA_MASK 0x0001 /* AIF3TX1_ENA */ 2983*4882a593Smuzhiyun #define WM5100_AIF3TX1_ENA_SHIFT 0 /* AIF3TX1_ENA */ 2984*4882a593Smuzhiyun #define WM5100_AIF3TX1_ENA_WIDTH 1 /* AIF3TX1_ENA */ 2985*4882a593Smuzhiyun 2986*4882a593Smuzhiyun /* 2987*4882a593Smuzhiyun * R1434 (0x59A) - Audio IF 3_27 2988*4882a593Smuzhiyun */ 2989*4882a593Smuzhiyun #define WM5100_AIF3RX2_ENA 0x0002 /* AIF3RX2_ENA */ 2990*4882a593Smuzhiyun #define WM5100_AIF3RX2_ENA_MASK 0x0002 /* AIF3RX2_ENA */ 2991*4882a593Smuzhiyun #define WM5100_AIF3RX2_ENA_SHIFT 1 /* AIF3RX2_ENA */ 2992*4882a593Smuzhiyun #define WM5100_AIF3RX2_ENA_WIDTH 1 /* AIF3RX2_ENA */ 2993*4882a593Smuzhiyun #define WM5100_AIF3RX1_ENA 0x0001 /* AIF3RX1_ENA */ 2994*4882a593Smuzhiyun #define WM5100_AIF3RX1_ENA_MASK 0x0001 /* AIF3RX1_ENA */ 2995*4882a593Smuzhiyun #define WM5100_AIF3RX1_ENA_SHIFT 0 /* AIF3RX1_ENA */ 2996*4882a593Smuzhiyun #define WM5100_AIF3RX1_ENA_WIDTH 1 /* AIF3RX1_ENA */ 2997*4882a593Smuzhiyun 2998*4882a593Smuzhiyun #define WM5100_MIXER_VOL_MASK 0x00FE /* MIXER_VOL - [7:1] */ 2999*4882a593Smuzhiyun #define WM5100_MIXER_VOL_SHIFT 1 /* MIXER_VOL - [7:1] */ 3000*4882a593Smuzhiyun #define WM5100_MIXER_VOL_WIDTH 7 /* MIXER_VOL - [7:1] */ 3001*4882a593Smuzhiyun 3002*4882a593Smuzhiyun /* 3003*4882a593Smuzhiyun * R3072 (0xC00) - GPIO CTRL 1 3004*4882a593Smuzhiyun */ 3005*4882a593Smuzhiyun #define WM5100_GP1_DIR 0x8000 /* GP1_DIR */ 3006*4882a593Smuzhiyun #define WM5100_GP1_DIR_MASK 0x8000 /* GP1_DIR */ 3007*4882a593Smuzhiyun #define WM5100_GP1_DIR_SHIFT 15 /* GP1_DIR */ 3008*4882a593Smuzhiyun #define WM5100_GP1_DIR_WIDTH 1 /* GP1_DIR */ 3009*4882a593Smuzhiyun #define WM5100_GP1_PU 0x4000 /* GP1_PU */ 3010*4882a593Smuzhiyun #define WM5100_GP1_PU_MASK 0x4000 /* GP1_PU */ 3011*4882a593Smuzhiyun #define WM5100_GP1_PU_SHIFT 14 /* GP1_PU */ 3012*4882a593Smuzhiyun #define WM5100_GP1_PU_WIDTH 1 /* GP1_PU */ 3013*4882a593Smuzhiyun #define WM5100_GP1_PD 0x2000 /* GP1_PD */ 3014*4882a593Smuzhiyun #define WM5100_GP1_PD_MASK 0x2000 /* GP1_PD */ 3015*4882a593Smuzhiyun #define WM5100_GP1_PD_SHIFT 13 /* GP1_PD */ 3016*4882a593Smuzhiyun #define WM5100_GP1_PD_WIDTH 1 /* GP1_PD */ 3017*4882a593Smuzhiyun #define WM5100_GP1_POL 0x0400 /* GP1_POL */ 3018*4882a593Smuzhiyun #define WM5100_GP1_POL_MASK 0x0400 /* GP1_POL */ 3019*4882a593Smuzhiyun #define WM5100_GP1_POL_SHIFT 10 /* GP1_POL */ 3020*4882a593Smuzhiyun #define WM5100_GP1_POL_WIDTH 1 /* GP1_POL */ 3021*4882a593Smuzhiyun #define WM5100_GP1_OP_CFG 0x0200 /* GP1_OP_CFG */ 3022*4882a593Smuzhiyun #define WM5100_GP1_OP_CFG_MASK 0x0200 /* GP1_OP_CFG */ 3023*4882a593Smuzhiyun #define WM5100_GP1_OP_CFG_SHIFT 9 /* GP1_OP_CFG */ 3024*4882a593Smuzhiyun #define WM5100_GP1_OP_CFG_WIDTH 1 /* GP1_OP_CFG */ 3025*4882a593Smuzhiyun #define WM5100_GP1_DB 0x0100 /* GP1_DB */ 3026*4882a593Smuzhiyun #define WM5100_GP1_DB_MASK 0x0100 /* GP1_DB */ 3027*4882a593Smuzhiyun #define WM5100_GP1_DB_SHIFT 8 /* GP1_DB */ 3028*4882a593Smuzhiyun #define WM5100_GP1_DB_WIDTH 1 /* GP1_DB */ 3029*4882a593Smuzhiyun #define WM5100_GP1_LVL 0x0040 /* GP1_LVL */ 3030*4882a593Smuzhiyun #define WM5100_GP1_LVL_MASK 0x0040 /* GP1_LVL */ 3031*4882a593Smuzhiyun #define WM5100_GP1_LVL_SHIFT 6 /* GP1_LVL */ 3032*4882a593Smuzhiyun #define WM5100_GP1_LVL_WIDTH 1 /* GP1_LVL */ 3033*4882a593Smuzhiyun #define WM5100_GP1_FN_MASK 0x003F /* GP1_FN - [5:0] */ 3034*4882a593Smuzhiyun #define WM5100_GP1_FN_SHIFT 0 /* GP1_FN - [5:0] */ 3035*4882a593Smuzhiyun #define WM5100_GP1_FN_WIDTH 6 /* GP1_FN - [5:0] */ 3036*4882a593Smuzhiyun 3037*4882a593Smuzhiyun /* 3038*4882a593Smuzhiyun * R3073 (0xC01) - GPIO CTRL 2 3039*4882a593Smuzhiyun */ 3040*4882a593Smuzhiyun #define WM5100_GP2_DIR 0x8000 /* GP2_DIR */ 3041*4882a593Smuzhiyun #define WM5100_GP2_DIR_MASK 0x8000 /* GP2_DIR */ 3042*4882a593Smuzhiyun #define WM5100_GP2_DIR_SHIFT 15 /* GP2_DIR */ 3043*4882a593Smuzhiyun #define WM5100_GP2_DIR_WIDTH 1 /* GP2_DIR */ 3044*4882a593Smuzhiyun #define WM5100_GP2_PU 0x4000 /* GP2_PU */ 3045*4882a593Smuzhiyun #define WM5100_GP2_PU_MASK 0x4000 /* GP2_PU */ 3046*4882a593Smuzhiyun #define WM5100_GP2_PU_SHIFT 14 /* GP2_PU */ 3047*4882a593Smuzhiyun #define WM5100_GP2_PU_WIDTH 1 /* GP2_PU */ 3048*4882a593Smuzhiyun #define WM5100_GP2_PD 0x2000 /* GP2_PD */ 3049*4882a593Smuzhiyun #define WM5100_GP2_PD_MASK 0x2000 /* GP2_PD */ 3050*4882a593Smuzhiyun #define WM5100_GP2_PD_SHIFT 13 /* GP2_PD */ 3051*4882a593Smuzhiyun #define WM5100_GP2_PD_WIDTH 1 /* GP2_PD */ 3052*4882a593Smuzhiyun #define WM5100_GP2_POL 0x0400 /* GP2_POL */ 3053*4882a593Smuzhiyun #define WM5100_GP2_POL_MASK 0x0400 /* GP2_POL */ 3054*4882a593Smuzhiyun #define WM5100_GP2_POL_SHIFT 10 /* GP2_POL */ 3055*4882a593Smuzhiyun #define WM5100_GP2_POL_WIDTH 1 /* GP2_POL */ 3056*4882a593Smuzhiyun #define WM5100_GP2_OP_CFG 0x0200 /* GP2_OP_CFG */ 3057*4882a593Smuzhiyun #define WM5100_GP2_OP_CFG_MASK 0x0200 /* GP2_OP_CFG */ 3058*4882a593Smuzhiyun #define WM5100_GP2_OP_CFG_SHIFT 9 /* GP2_OP_CFG */ 3059*4882a593Smuzhiyun #define WM5100_GP2_OP_CFG_WIDTH 1 /* GP2_OP_CFG */ 3060*4882a593Smuzhiyun #define WM5100_GP2_DB 0x0100 /* GP2_DB */ 3061*4882a593Smuzhiyun #define WM5100_GP2_DB_MASK 0x0100 /* GP2_DB */ 3062*4882a593Smuzhiyun #define WM5100_GP2_DB_SHIFT 8 /* GP2_DB */ 3063*4882a593Smuzhiyun #define WM5100_GP2_DB_WIDTH 1 /* GP2_DB */ 3064*4882a593Smuzhiyun #define WM5100_GP2_LVL 0x0040 /* GP2_LVL */ 3065*4882a593Smuzhiyun #define WM5100_GP2_LVL_MASK 0x0040 /* GP2_LVL */ 3066*4882a593Smuzhiyun #define WM5100_GP2_LVL_SHIFT 6 /* GP2_LVL */ 3067*4882a593Smuzhiyun #define WM5100_GP2_LVL_WIDTH 1 /* GP2_LVL */ 3068*4882a593Smuzhiyun #define WM5100_GP2_FN_MASK 0x003F /* GP2_FN - [5:0] */ 3069*4882a593Smuzhiyun #define WM5100_GP2_FN_SHIFT 0 /* GP2_FN - [5:0] */ 3070*4882a593Smuzhiyun #define WM5100_GP2_FN_WIDTH 6 /* GP2_FN - [5:0] */ 3071*4882a593Smuzhiyun 3072*4882a593Smuzhiyun /* 3073*4882a593Smuzhiyun * R3074 (0xC02) - GPIO CTRL 3 3074*4882a593Smuzhiyun */ 3075*4882a593Smuzhiyun #define WM5100_GP3_DIR 0x8000 /* GP3_DIR */ 3076*4882a593Smuzhiyun #define WM5100_GP3_DIR_MASK 0x8000 /* GP3_DIR */ 3077*4882a593Smuzhiyun #define WM5100_GP3_DIR_SHIFT 15 /* GP3_DIR */ 3078*4882a593Smuzhiyun #define WM5100_GP3_DIR_WIDTH 1 /* GP3_DIR */ 3079*4882a593Smuzhiyun #define WM5100_GP3_PU 0x4000 /* GP3_PU */ 3080*4882a593Smuzhiyun #define WM5100_GP3_PU_MASK 0x4000 /* GP3_PU */ 3081*4882a593Smuzhiyun #define WM5100_GP3_PU_SHIFT 14 /* GP3_PU */ 3082*4882a593Smuzhiyun #define WM5100_GP3_PU_WIDTH 1 /* GP3_PU */ 3083*4882a593Smuzhiyun #define WM5100_GP3_PD 0x2000 /* GP3_PD */ 3084*4882a593Smuzhiyun #define WM5100_GP3_PD_MASK 0x2000 /* GP3_PD */ 3085*4882a593Smuzhiyun #define WM5100_GP3_PD_SHIFT 13 /* GP3_PD */ 3086*4882a593Smuzhiyun #define WM5100_GP3_PD_WIDTH 1 /* GP3_PD */ 3087*4882a593Smuzhiyun #define WM5100_GP3_POL 0x0400 /* GP3_POL */ 3088*4882a593Smuzhiyun #define WM5100_GP3_POL_MASK 0x0400 /* GP3_POL */ 3089*4882a593Smuzhiyun #define WM5100_GP3_POL_SHIFT 10 /* GP3_POL */ 3090*4882a593Smuzhiyun #define WM5100_GP3_POL_WIDTH 1 /* GP3_POL */ 3091*4882a593Smuzhiyun #define WM5100_GP3_OP_CFG 0x0200 /* GP3_OP_CFG */ 3092*4882a593Smuzhiyun #define WM5100_GP3_OP_CFG_MASK 0x0200 /* GP3_OP_CFG */ 3093*4882a593Smuzhiyun #define WM5100_GP3_OP_CFG_SHIFT 9 /* GP3_OP_CFG */ 3094*4882a593Smuzhiyun #define WM5100_GP3_OP_CFG_WIDTH 1 /* GP3_OP_CFG */ 3095*4882a593Smuzhiyun #define WM5100_GP3_DB 0x0100 /* GP3_DB */ 3096*4882a593Smuzhiyun #define WM5100_GP3_DB_MASK 0x0100 /* GP3_DB */ 3097*4882a593Smuzhiyun #define WM5100_GP3_DB_SHIFT 8 /* GP3_DB */ 3098*4882a593Smuzhiyun #define WM5100_GP3_DB_WIDTH 1 /* GP3_DB */ 3099*4882a593Smuzhiyun #define WM5100_GP3_LVL 0x0040 /* GP3_LVL */ 3100*4882a593Smuzhiyun #define WM5100_GP3_LVL_MASK 0x0040 /* GP3_LVL */ 3101*4882a593Smuzhiyun #define WM5100_GP3_LVL_SHIFT 6 /* GP3_LVL */ 3102*4882a593Smuzhiyun #define WM5100_GP3_LVL_WIDTH 1 /* GP3_LVL */ 3103*4882a593Smuzhiyun #define WM5100_GP3_FN_MASK 0x003F /* GP3_FN - [5:0] */ 3104*4882a593Smuzhiyun #define WM5100_GP3_FN_SHIFT 0 /* GP3_FN - [5:0] */ 3105*4882a593Smuzhiyun #define WM5100_GP3_FN_WIDTH 6 /* GP3_FN - [5:0] */ 3106*4882a593Smuzhiyun 3107*4882a593Smuzhiyun /* 3108*4882a593Smuzhiyun * R3075 (0xC03) - GPIO CTRL 4 3109*4882a593Smuzhiyun */ 3110*4882a593Smuzhiyun #define WM5100_GP4_DIR 0x8000 /* GP4_DIR */ 3111*4882a593Smuzhiyun #define WM5100_GP4_DIR_MASK 0x8000 /* GP4_DIR */ 3112*4882a593Smuzhiyun #define WM5100_GP4_DIR_SHIFT 15 /* GP4_DIR */ 3113*4882a593Smuzhiyun #define WM5100_GP4_DIR_WIDTH 1 /* GP4_DIR */ 3114*4882a593Smuzhiyun #define WM5100_GP4_PU 0x4000 /* GP4_PU */ 3115*4882a593Smuzhiyun #define WM5100_GP4_PU_MASK 0x4000 /* GP4_PU */ 3116*4882a593Smuzhiyun #define WM5100_GP4_PU_SHIFT 14 /* GP4_PU */ 3117*4882a593Smuzhiyun #define WM5100_GP4_PU_WIDTH 1 /* GP4_PU */ 3118*4882a593Smuzhiyun #define WM5100_GP4_PD 0x2000 /* GP4_PD */ 3119*4882a593Smuzhiyun #define WM5100_GP4_PD_MASK 0x2000 /* GP4_PD */ 3120*4882a593Smuzhiyun #define WM5100_GP4_PD_SHIFT 13 /* GP4_PD */ 3121*4882a593Smuzhiyun #define WM5100_GP4_PD_WIDTH 1 /* GP4_PD */ 3122*4882a593Smuzhiyun #define WM5100_GP4_POL 0x0400 /* GP4_POL */ 3123*4882a593Smuzhiyun #define WM5100_GP4_POL_MASK 0x0400 /* GP4_POL */ 3124*4882a593Smuzhiyun #define WM5100_GP4_POL_SHIFT 10 /* GP4_POL */ 3125*4882a593Smuzhiyun #define WM5100_GP4_POL_WIDTH 1 /* GP4_POL */ 3126*4882a593Smuzhiyun #define WM5100_GP4_OP_CFG 0x0200 /* GP4_OP_CFG */ 3127*4882a593Smuzhiyun #define WM5100_GP4_OP_CFG_MASK 0x0200 /* GP4_OP_CFG */ 3128*4882a593Smuzhiyun #define WM5100_GP4_OP_CFG_SHIFT 9 /* GP4_OP_CFG */ 3129*4882a593Smuzhiyun #define WM5100_GP4_OP_CFG_WIDTH 1 /* GP4_OP_CFG */ 3130*4882a593Smuzhiyun #define WM5100_GP4_DB 0x0100 /* GP4_DB */ 3131*4882a593Smuzhiyun #define WM5100_GP4_DB_MASK 0x0100 /* GP4_DB */ 3132*4882a593Smuzhiyun #define WM5100_GP4_DB_SHIFT 8 /* GP4_DB */ 3133*4882a593Smuzhiyun #define WM5100_GP4_DB_WIDTH 1 /* GP4_DB */ 3134*4882a593Smuzhiyun #define WM5100_GP4_LVL 0x0040 /* GP4_LVL */ 3135*4882a593Smuzhiyun #define WM5100_GP4_LVL_MASK 0x0040 /* GP4_LVL */ 3136*4882a593Smuzhiyun #define WM5100_GP4_LVL_SHIFT 6 /* GP4_LVL */ 3137*4882a593Smuzhiyun #define WM5100_GP4_LVL_WIDTH 1 /* GP4_LVL */ 3138*4882a593Smuzhiyun #define WM5100_GP4_FN_MASK 0x003F /* GP4_FN - [5:0] */ 3139*4882a593Smuzhiyun #define WM5100_GP4_FN_SHIFT 0 /* GP4_FN - [5:0] */ 3140*4882a593Smuzhiyun #define WM5100_GP4_FN_WIDTH 6 /* GP4_FN - [5:0] */ 3141*4882a593Smuzhiyun 3142*4882a593Smuzhiyun /* 3143*4882a593Smuzhiyun * R3076 (0xC04) - GPIO CTRL 5 3144*4882a593Smuzhiyun */ 3145*4882a593Smuzhiyun #define WM5100_GP5_DIR 0x8000 /* GP5_DIR */ 3146*4882a593Smuzhiyun #define WM5100_GP5_DIR_MASK 0x8000 /* GP5_DIR */ 3147*4882a593Smuzhiyun #define WM5100_GP5_DIR_SHIFT 15 /* GP5_DIR */ 3148*4882a593Smuzhiyun #define WM5100_GP5_DIR_WIDTH 1 /* GP5_DIR */ 3149*4882a593Smuzhiyun #define WM5100_GP5_PU 0x4000 /* GP5_PU */ 3150*4882a593Smuzhiyun #define WM5100_GP5_PU_MASK 0x4000 /* GP5_PU */ 3151*4882a593Smuzhiyun #define WM5100_GP5_PU_SHIFT 14 /* GP5_PU */ 3152*4882a593Smuzhiyun #define WM5100_GP5_PU_WIDTH 1 /* GP5_PU */ 3153*4882a593Smuzhiyun #define WM5100_GP5_PD 0x2000 /* GP5_PD */ 3154*4882a593Smuzhiyun #define WM5100_GP5_PD_MASK 0x2000 /* GP5_PD */ 3155*4882a593Smuzhiyun #define WM5100_GP5_PD_SHIFT 13 /* GP5_PD */ 3156*4882a593Smuzhiyun #define WM5100_GP5_PD_WIDTH 1 /* GP5_PD */ 3157*4882a593Smuzhiyun #define WM5100_GP5_POL 0x0400 /* GP5_POL */ 3158*4882a593Smuzhiyun #define WM5100_GP5_POL_MASK 0x0400 /* GP5_POL */ 3159*4882a593Smuzhiyun #define WM5100_GP5_POL_SHIFT 10 /* GP5_POL */ 3160*4882a593Smuzhiyun #define WM5100_GP5_POL_WIDTH 1 /* GP5_POL */ 3161*4882a593Smuzhiyun #define WM5100_GP5_OP_CFG 0x0200 /* GP5_OP_CFG */ 3162*4882a593Smuzhiyun #define WM5100_GP5_OP_CFG_MASK 0x0200 /* GP5_OP_CFG */ 3163*4882a593Smuzhiyun #define WM5100_GP5_OP_CFG_SHIFT 9 /* GP5_OP_CFG */ 3164*4882a593Smuzhiyun #define WM5100_GP5_OP_CFG_WIDTH 1 /* GP5_OP_CFG */ 3165*4882a593Smuzhiyun #define WM5100_GP5_DB 0x0100 /* GP5_DB */ 3166*4882a593Smuzhiyun #define WM5100_GP5_DB_MASK 0x0100 /* GP5_DB */ 3167*4882a593Smuzhiyun #define WM5100_GP5_DB_SHIFT 8 /* GP5_DB */ 3168*4882a593Smuzhiyun #define WM5100_GP5_DB_WIDTH 1 /* GP5_DB */ 3169*4882a593Smuzhiyun #define WM5100_GP5_LVL 0x0040 /* GP5_LVL */ 3170*4882a593Smuzhiyun #define WM5100_GP5_LVL_MASK 0x0040 /* GP5_LVL */ 3171*4882a593Smuzhiyun #define WM5100_GP5_LVL_SHIFT 6 /* GP5_LVL */ 3172*4882a593Smuzhiyun #define WM5100_GP5_LVL_WIDTH 1 /* GP5_LVL */ 3173*4882a593Smuzhiyun #define WM5100_GP5_FN_MASK 0x003F /* GP5_FN - [5:0] */ 3174*4882a593Smuzhiyun #define WM5100_GP5_FN_SHIFT 0 /* GP5_FN - [5:0] */ 3175*4882a593Smuzhiyun #define WM5100_GP5_FN_WIDTH 6 /* GP5_FN - [5:0] */ 3176*4882a593Smuzhiyun 3177*4882a593Smuzhiyun /* 3178*4882a593Smuzhiyun * R3077 (0xC05) - GPIO CTRL 6 3179*4882a593Smuzhiyun */ 3180*4882a593Smuzhiyun #define WM5100_GP6_DIR 0x8000 /* GP6_DIR */ 3181*4882a593Smuzhiyun #define WM5100_GP6_DIR_MASK 0x8000 /* GP6_DIR */ 3182*4882a593Smuzhiyun #define WM5100_GP6_DIR_SHIFT 15 /* GP6_DIR */ 3183*4882a593Smuzhiyun #define WM5100_GP6_DIR_WIDTH 1 /* GP6_DIR */ 3184*4882a593Smuzhiyun #define WM5100_GP6_PU 0x4000 /* GP6_PU */ 3185*4882a593Smuzhiyun #define WM5100_GP6_PU_MASK 0x4000 /* GP6_PU */ 3186*4882a593Smuzhiyun #define WM5100_GP6_PU_SHIFT 14 /* GP6_PU */ 3187*4882a593Smuzhiyun #define WM5100_GP6_PU_WIDTH 1 /* GP6_PU */ 3188*4882a593Smuzhiyun #define WM5100_GP6_PD 0x2000 /* GP6_PD */ 3189*4882a593Smuzhiyun #define WM5100_GP6_PD_MASK 0x2000 /* GP6_PD */ 3190*4882a593Smuzhiyun #define WM5100_GP6_PD_SHIFT 13 /* GP6_PD */ 3191*4882a593Smuzhiyun #define WM5100_GP6_PD_WIDTH 1 /* GP6_PD */ 3192*4882a593Smuzhiyun #define WM5100_GP6_POL 0x0400 /* GP6_POL */ 3193*4882a593Smuzhiyun #define WM5100_GP6_POL_MASK 0x0400 /* GP6_POL */ 3194*4882a593Smuzhiyun #define WM5100_GP6_POL_SHIFT 10 /* GP6_POL */ 3195*4882a593Smuzhiyun #define WM5100_GP6_POL_WIDTH 1 /* GP6_POL */ 3196*4882a593Smuzhiyun #define WM5100_GP6_OP_CFG 0x0200 /* GP6_OP_CFG */ 3197*4882a593Smuzhiyun #define WM5100_GP6_OP_CFG_MASK 0x0200 /* GP6_OP_CFG */ 3198*4882a593Smuzhiyun #define WM5100_GP6_OP_CFG_SHIFT 9 /* GP6_OP_CFG */ 3199*4882a593Smuzhiyun #define WM5100_GP6_OP_CFG_WIDTH 1 /* GP6_OP_CFG */ 3200*4882a593Smuzhiyun #define WM5100_GP6_DB 0x0100 /* GP6_DB */ 3201*4882a593Smuzhiyun #define WM5100_GP6_DB_MASK 0x0100 /* GP6_DB */ 3202*4882a593Smuzhiyun #define WM5100_GP6_DB_SHIFT 8 /* GP6_DB */ 3203*4882a593Smuzhiyun #define WM5100_GP6_DB_WIDTH 1 /* GP6_DB */ 3204*4882a593Smuzhiyun #define WM5100_GP6_LVL 0x0040 /* GP6_LVL */ 3205*4882a593Smuzhiyun #define WM5100_GP6_LVL_MASK 0x0040 /* GP6_LVL */ 3206*4882a593Smuzhiyun #define WM5100_GP6_LVL_SHIFT 6 /* GP6_LVL */ 3207*4882a593Smuzhiyun #define WM5100_GP6_LVL_WIDTH 1 /* GP6_LVL */ 3208*4882a593Smuzhiyun #define WM5100_GP6_FN_MASK 0x003F /* GP6_FN - [5:0] */ 3209*4882a593Smuzhiyun #define WM5100_GP6_FN_SHIFT 0 /* GP6_FN - [5:0] */ 3210*4882a593Smuzhiyun #define WM5100_GP6_FN_WIDTH 6 /* GP6_FN - [5:0] */ 3211*4882a593Smuzhiyun 3212*4882a593Smuzhiyun /* 3213*4882a593Smuzhiyun * R3107 (0xC23) - Misc Pad Ctrl 1 3214*4882a593Smuzhiyun */ 3215*4882a593Smuzhiyun #define WM5100_LDO1ENA_PD 0x8000 /* LDO1ENA_PD */ 3216*4882a593Smuzhiyun #define WM5100_LDO1ENA_PD_MASK 0x8000 /* LDO1ENA_PD */ 3217*4882a593Smuzhiyun #define WM5100_LDO1ENA_PD_SHIFT 15 /* LDO1ENA_PD */ 3218*4882a593Smuzhiyun #define WM5100_LDO1ENA_PD_WIDTH 1 /* LDO1ENA_PD */ 3219*4882a593Smuzhiyun #define WM5100_MCLK2_PD 0x2000 /* MCLK2_PD */ 3220*4882a593Smuzhiyun #define WM5100_MCLK2_PD_MASK 0x2000 /* MCLK2_PD */ 3221*4882a593Smuzhiyun #define WM5100_MCLK2_PD_SHIFT 13 /* MCLK2_PD */ 3222*4882a593Smuzhiyun #define WM5100_MCLK2_PD_WIDTH 1 /* MCLK2_PD */ 3223*4882a593Smuzhiyun #define WM5100_MCLK1_PD 0x1000 /* MCLK1_PD */ 3224*4882a593Smuzhiyun #define WM5100_MCLK1_PD_MASK 0x1000 /* MCLK1_PD */ 3225*4882a593Smuzhiyun #define WM5100_MCLK1_PD_SHIFT 12 /* MCLK1_PD */ 3226*4882a593Smuzhiyun #define WM5100_MCLK1_PD_WIDTH 1 /* MCLK1_PD */ 3227*4882a593Smuzhiyun #define WM5100_RESET_PU 0x0002 /* RESET_PU */ 3228*4882a593Smuzhiyun #define WM5100_RESET_PU_MASK 0x0002 /* RESET_PU */ 3229*4882a593Smuzhiyun #define WM5100_RESET_PU_SHIFT 1 /* RESET_PU */ 3230*4882a593Smuzhiyun #define WM5100_RESET_PU_WIDTH 1 /* RESET_PU */ 3231*4882a593Smuzhiyun #define WM5100_ADDR_PD 0x0001 /* ADDR_PD */ 3232*4882a593Smuzhiyun #define WM5100_ADDR_PD_MASK 0x0001 /* ADDR_PD */ 3233*4882a593Smuzhiyun #define WM5100_ADDR_PD_SHIFT 0 /* ADDR_PD */ 3234*4882a593Smuzhiyun #define WM5100_ADDR_PD_WIDTH 1 /* ADDR_PD */ 3235*4882a593Smuzhiyun 3236*4882a593Smuzhiyun /* 3237*4882a593Smuzhiyun * R3108 (0xC24) - Misc Pad Ctrl 2 3238*4882a593Smuzhiyun */ 3239*4882a593Smuzhiyun #define WM5100_DMICDAT4_PD 0x0008 /* DMICDAT4_PD */ 3240*4882a593Smuzhiyun #define WM5100_DMICDAT4_PD_MASK 0x0008 /* DMICDAT4_PD */ 3241*4882a593Smuzhiyun #define WM5100_DMICDAT4_PD_SHIFT 3 /* DMICDAT4_PD */ 3242*4882a593Smuzhiyun #define WM5100_DMICDAT4_PD_WIDTH 1 /* DMICDAT4_PD */ 3243*4882a593Smuzhiyun #define WM5100_DMICDAT3_PD 0x0004 /* DMICDAT3_PD */ 3244*4882a593Smuzhiyun #define WM5100_DMICDAT3_PD_MASK 0x0004 /* DMICDAT3_PD */ 3245*4882a593Smuzhiyun #define WM5100_DMICDAT3_PD_SHIFT 2 /* DMICDAT3_PD */ 3246*4882a593Smuzhiyun #define WM5100_DMICDAT3_PD_WIDTH 1 /* DMICDAT3_PD */ 3247*4882a593Smuzhiyun #define WM5100_DMICDAT2_PD 0x0002 /* DMICDAT2_PD */ 3248*4882a593Smuzhiyun #define WM5100_DMICDAT2_PD_MASK 0x0002 /* DMICDAT2_PD */ 3249*4882a593Smuzhiyun #define WM5100_DMICDAT2_PD_SHIFT 1 /* DMICDAT2_PD */ 3250*4882a593Smuzhiyun #define WM5100_DMICDAT2_PD_WIDTH 1 /* DMICDAT2_PD */ 3251*4882a593Smuzhiyun #define WM5100_DMICDAT1_PD 0x0001 /* DMICDAT1_PD */ 3252*4882a593Smuzhiyun #define WM5100_DMICDAT1_PD_MASK 0x0001 /* DMICDAT1_PD */ 3253*4882a593Smuzhiyun #define WM5100_DMICDAT1_PD_SHIFT 0 /* DMICDAT1_PD */ 3254*4882a593Smuzhiyun #define WM5100_DMICDAT1_PD_WIDTH 1 /* DMICDAT1_PD */ 3255*4882a593Smuzhiyun 3256*4882a593Smuzhiyun /* 3257*4882a593Smuzhiyun * R3109 (0xC25) - Misc Pad Ctrl 3 3258*4882a593Smuzhiyun */ 3259*4882a593Smuzhiyun #define WM5100_AIF1RXLRCLK_PU 0x0020 /* AIF1RXLRCLK_PU */ 3260*4882a593Smuzhiyun #define WM5100_AIF1RXLRCLK_PU_MASK 0x0020 /* AIF1RXLRCLK_PU */ 3261*4882a593Smuzhiyun #define WM5100_AIF1RXLRCLK_PU_SHIFT 5 /* AIF1RXLRCLK_PU */ 3262*4882a593Smuzhiyun #define WM5100_AIF1RXLRCLK_PU_WIDTH 1 /* AIF1RXLRCLK_PU */ 3263*4882a593Smuzhiyun #define WM5100_AIF1RXLRCLK_PD 0x0010 /* AIF1RXLRCLK_PD */ 3264*4882a593Smuzhiyun #define WM5100_AIF1RXLRCLK_PD_MASK 0x0010 /* AIF1RXLRCLK_PD */ 3265*4882a593Smuzhiyun #define WM5100_AIF1RXLRCLK_PD_SHIFT 4 /* AIF1RXLRCLK_PD */ 3266*4882a593Smuzhiyun #define WM5100_AIF1RXLRCLK_PD_WIDTH 1 /* AIF1RXLRCLK_PD */ 3267*4882a593Smuzhiyun #define WM5100_AIF1BCLK_PU 0x0008 /* AIF1BCLK_PU */ 3268*4882a593Smuzhiyun #define WM5100_AIF1BCLK_PU_MASK 0x0008 /* AIF1BCLK_PU */ 3269*4882a593Smuzhiyun #define WM5100_AIF1BCLK_PU_SHIFT 3 /* AIF1BCLK_PU */ 3270*4882a593Smuzhiyun #define WM5100_AIF1BCLK_PU_WIDTH 1 /* AIF1BCLK_PU */ 3271*4882a593Smuzhiyun #define WM5100_AIF1BCLK_PD 0x0004 /* AIF1BCLK_PD */ 3272*4882a593Smuzhiyun #define WM5100_AIF1BCLK_PD_MASK 0x0004 /* AIF1BCLK_PD */ 3273*4882a593Smuzhiyun #define WM5100_AIF1BCLK_PD_SHIFT 2 /* AIF1BCLK_PD */ 3274*4882a593Smuzhiyun #define WM5100_AIF1BCLK_PD_WIDTH 1 /* AIF1BCLK_PD */ 3275*4882a593Smuzhiyun #define WM5100_AIF1RXDAT_PU 0x0002 /* AIF1RXDAT_PU */ 3276*4882a593Smuzhiyun #define WM5100_AIF1RXDAT_PU_MASK 0x0002 /* AIF1RXDAT_PU */ 3277*4882a593Smuzhiyun #define WM5100_AIF1RXDAT_PU_SHIFT 1 /* AIF1RXDAT_PU */ 3278*4882a593Smuzhiyun #define WM5100_AIF1RXDAT_PU_WIDTH 1 /* AIF1RXDAT_PU */ 3279*4882a593Smuzhiyun #define WM5100_AIF1RXDAT_PD 0x0001 /* AIF1RXDAT_PD */ 3280*4882a593Smuzhiyun #define WM5100_AIF1RXDAT_PD_MASK 0x0001 /* AIF1RXDAT_PD */ 3281*4882a593Smuzhiyun #define WM5100_AIF1RXDAT_PD_SHIFT 0 /* AIF1RXDAT_PD */ 3282*4882a593Smuzhiyun #define WM5100_AIF1RXDAT_PD_WIDTH 1 /* AIF1RXDAT_PD */ 3283*4882a593Smuzhiyun 3284*4882a593Smuzhiyun /* 3285*4882a593Smuzhiyun * R3110 (0xC26) - Misc Pad Ctrl 4 3286*4882a593Smuzhiyun */ 3287*4882a593Smuzhiyun #define WM5100_AIF2RXLRCLK_PU 0x0020 /* AIF2RXLRCLK_PU */ 3288*4882a593Smuzhiyun #define WM5100_AIF2RXLRCLK_PU_MASK 0x0020 /* AIF2RXLRCLK_PU */ 3289*4882a593Smuzhiyun #define WM5100_AIF2RXLRCLK_PU_SHIFT 5 /* AIF2RXLRCLK_PU */ 3290*4882a593Smuzhiyun #define WM5100_AIF2RXLRCLK_PU_WIDTH 1 /* AIF2RXLRCLK_PU */ 3291*4882a593Smuzhiyun #define WM5100_AIF2RXLRCLK_PD 0x0010 /* AIF2RXLRCLK_PD */ 3292*4882a593Smuzhiyun #define WM5100_AIF2RXLRCLK_PD_MASK 0x0010 /* AIF2RXLRCLK_PD */ 3293*4882a593Smuzhiyun #define WM5100_AIF2RXLRCLK_PD_SHIFT 4 /* AIF2RXLRCLK_PD */ 3294*4882a593Smuzhiyun #define WM5100_AIF2RXLRCLK_PD_WIDTH 1 /* AIF2RXLRCLK_PD */ 3295*4882a593Smuzhiyun #define WM5100_AIF2BCLK_PU 0x0008 /* AIF2BCLK_PU */ 3296*4882a593Smuzhiyun #define WM5100_AIF2BCLK_PU_MASK 0x0008 /* AIF2BCLK_PU */ 3297*4882a593Smuzhiyun #define WM5100_AIF2BCLK_PU_SHIFT 3 /* AIF2BCLK_PU */ 3298*4882a593Smuzhiyun #define WM5100_AIF2BCLK_PU_WIDTH 1 /* AIF2BCLK_PU */ 3299*4882a593Smuzhiyun #define WM5100_AIF2BCLK_PD 0x0004 /* AIF2BCLK_PD */ 3300*4882a593Smuzhiyun #define WM5100_AIF2BCLK_PD_MASK 0x0004 /* AIF2BCLK_PD */ 3301*4882a593Smuzhiyun #define WM5100_AIF2BCLK_PD_SHIFT 2 /* AIF2BCLK_PD */ 3302*4882a593Smuzhiyun #define WM5100_AIF2BCLK_PD_WIDTH 1 /* AIF2BCLK_PD */ 3303*4882a593Smuzhiyun #define WM5100_AIF2RXDAT_PU 0x0002 /* AIF2RXDAT_PU */ 3304*4882a593Smuzhiyun #define WM5100_AIF2RXDAT_PU_MASK 0x0002 /* AIF2RXDAT_PU */ 3305*4882a593Smuzhiyun #define WM5100_AIF2RXDAT_PU_SHIFT 1 /* AIF2RXDAT_PU */ 3306*4882a593Smuzhiyun #define WM5100_AIF2RXDAT_PU_WIDTH 1 /* AIF2RXDAT_PU */ 3307*4882a593Smuzhiyun #define WM5100_AIF2RXDAT_PD 0x0001 /* AIF2RXDAT_PD */ 3308*4882a593Smuzhiyun #define WM5100_AIF2RXDAT_PD_MASK 0x0001 /* AIF2RXDAT_PD */ 3309*4882a593Smuzhiyun #define WM5100_AIF2RXDAT_PD_SHIFT 0 /* AIF2RXDAT_PD */ 3310*4882a593Smuzhiyun #define WM5100_AIF2RXDAT_PD_WIDTH 1 /* AIF2RXDAT_PD */ 3311*4882a593Smuzhiyun 3312*4882a593Smuzhiyun /* 3313*4882a593Smuzhiyun * R3111 (0xC27) - Misc Pad Ctrl 5 3314*4882a593Smuzhiyun */ 3315*4882a593Smuzhiyun #define WM5100_AIF3RXLRCLK_PU 0x0020 /* AIF3RXLRCLK_PU */ 3316*4882a593Smuzhiyun #define WM5100_AIF3RXLRCLK_PU_MASK 0x0020 /* AIF3RXLRCLK_PU */ 3317*4882a593Smuzhiyun #define WM5100_AIF3RXLRCLK_PU_SHIFT 5 /* AIF3RXLRCLK_PU */ 3318*4882a593Smuzhiyun #define WM5100_AIF3RXLRCLK_PU_WIDTH 1 /* AIF3RXLRCLK_PU */ 3319*4882a593Smuzhiyun #define WM5100_AIF3RXLRCLK_PD 0x0010 /* AIF3RXLRCLK_PD */ 3320*4882a593Smuzhiyun #define WM5100_AIF3RXLRCLK_PD_MASK 0x0010 /* AIF3RXLRCLK_PD */ 3321*4882a593Smuzhiyun #define WM5100_AIF3RXLRCLK_PD_SHIFT 4 /* AIF3RXLRCLK_PD */ 3322*4882a593Smuzhiyun #define WM5100_AIF3RXLRCLK_PD_WIDTH 1 /* AIF3RXLRCLK_PD */ 3323*4882a593Smuzhiyun #define WM5100_AIF3BCLK_PU 0x0008 /* AIF3BCLK_PU */ 3324*4882a593Smuzhiyun #define WM5100_AIF3BCLK_PU_MASK 0x0008 /* AIF3BCLK_PU */ 3325*4882a593Smuzhiyun #define WM5100_AIF3BCLK_PU_SHIFT 3 /* AIF3BCLK_PU */ 3326*4882a593Smuzhiyun #define WM5100_AIF3BCLK_PU_WIDTH 1 /* AIF3BCLK_PU */ 3327*4882a593Smuzhiyun #define WM5100_AIF3BCLK_PD 0x0004 /* AIF3BCLK_PD */ 3328*4882a593Smuzhiyun #define WM5100_AIF3BCLK_PD_MASK 0x0004 /* AIF3BCLK_PD */ 3329*4882a593Smuzhiyun #define WM5100_AIF3BCLK_PD_SHIFT 2 /* AIF3BCLK_PD */ 3330*4882a593Smuzhiyun #define WM5100_AIF3BCLK_PD_WIDTH 1 /* AIF3BCLK_PD */ 3331*4882a593Smuzhiyun #define WM5100_AIF3RXDAT_PU 0x0002 /* AIF3RXDAT_PU */ 3332*4882a593Smuzhiyun #define WM5100_AIF3RXDAT_PU_MASK 0x0002 /* AIF3RXDAT_PU */ 3333*4882a593Smuzhiyun #define WM5100_AIF3RXDAT_PU_SHIFT 1 /* AIF3RXDAT_PU */ 3334*4882a593Smuzhiyun #define WM5100_AIF3RXDAT_PU_WIDTH 1 /* AIF3RXDAT_PU */ 3335*4882a593Smuzhiyun #define WM5100_AIF3RXDAT_PD 0x0001 /* AIF3RXDAT_PD */ 3336*4882a593Smuzhiyun #define WM5100_AIF3RXDAT_PD_MASK 0x0001 /* AIF3RXDAT_PD */ 3337*4882a593Smuzhiyun #define WM5100_AIF3RXDAT_PD_SHIFT 0 /* AIF3RXDAT_PD */ 3338*4882a593Smuzhiyun #define WM5100_AIF3RXDAT_PD_WIDTH 1 /* AIF3RXDAT_PD */ 3339*4882a593Smuzhiyun 3340*4882a593Smuzhiyun /* 3341*4882a593Smuzhiyun * R3112 (0xC28) - Misc GPIO 1 3342*4882a593Smuzhiyun */ 3343*4882a593Smuzhiyun #define WM5100_OPCLK_SEL_MASK 0x0003 /* OPCLK_SEL - [1:0] */ 3344*4882a593Smuzhiyun #define WM5100_OPCLK_SEL_SHIFT 0 /* OPCLK_SEL - [1:0] */ 3345*4882a593Smuzhiyun #define WM5100_OPCLK_SEL_WIDTH 2 /* OPCLK_SEL - [1:0] */ 3346*4882a593Smuzhiyun 3347*4882a593Smuzhiyun /* 3348*4882a593Smuzhiyun * R3328 (0xD00) - Interrupt Status 1 3349*4882a593Smuzhiyun */ 3350*4882a593Smuzhiyun #define WM5100_GP6_EINT 0x0020 /* GP6_EINT */ 3351*4882a593Smuzhiyun #define WM5100_GP6_EINT_MASK 0x0020 /* GP6_EINT */ 3352*4882a593Smuzhiyun #define WM5100_GP6_EINT_SHIFT 5 /* GP6_EINT */ 3353*4882a593Smuzhiyun #define WM5100_GP6_EINT_WIDTH 1 /* GP6_EINT */ 3354*4882a593Smuzhiyun #define WM5100_GP5_EINT 0x0010 /* GP5_EINT */ 3355*4882a593Smuzhiyun #define WM5100_GP5_EINT_MASK 0x0010 /* GP5_EINT */ 3356*4882a593Smuzhiyun #define WM5100_GP5_EINT_SHIFT 4 /* GP5_EINT */ 3357*4882a593Smuzhiyun #define WM5100_GP5_EINT_WIDTH 1 /* GP5_EINT */ 3358*4882a593Smuzhiyun #define WM5100_GP4_EINT 0x0008 /* GP4_EINT */ 3359*4882a593Smuzhiyun #define WM5100_GP4_EINT_MASK 0x0008 /* GP4_EINT */ 3360*4882a593Smuzhiyun #define WM5100_GP4_EINT_SHIFT 3 /* GP4_EINT */ 3361*4882a593Smuzhiyun #define WM5100_GP4_EINT_WIDTH 1 /* GP4_EINT */ 3362*4882a593Smuzhiyun #define WM5100_GP3_EINT 0x0004 /* GP3_EINT */ 3363*4882a593Smuzhiyun #define WM5100_GP3_EINT_MASK 0x0004 /* GP3_EINT */ 3364*4882a593Smuzhiyun #define WM5100_GP3_EINT_SHIFT 2 /* GP3_EINT */ 3365*4882a593Smuzhiyun #define WM5100_GP3_EINT_WIDTH 1 /* GP3_EINT */ 3366*4882a593Smuzhiyun #define WM5100_GP2_EINT 0x0002 /* GP2_EINT */ 3367*4882a593Smuzhiyun #define WM5100_GP2_EINT_MASK 0x0002 /* GP2_EINT */ 3368*4882a593Smuzhiyun #define WM5100_GP2_EINT_SHIFT 1 /* GP2_EINT */ 3369*4882a593Smuzhiyun #define WM5100_GP2_EINT_WIDTH 1 /* GP2_EINT */ 3370*4882a593Smuzhiyun #define WM5100_GP1_EINT 0x0001 /* GP1_EINT */ 3371*4882a593Smuzhiyun #define WM5100_GP1_EINT_MASK 0x0001 /* GP1_EINT */ 3372*4882a593Smuzhiyun #define WM5100_GP1_EINT_SHIFT 0 /* GP1_EINT */ 3373*4882a593Smuzhiyun #define WM5100_GP1_EINT_WIDTH 1 /* GP1_EINT */ 3374*4882a593Smuzhiyun 3375*4882a593Smuzhiyun /* 3376*4882a593Smuzhiyun * R3329 (0xD01) - Interrupt Status 2 3377*4882a593Smuzhiyun */ 3378*4882a593Smuzhiyun #define WM5100_DSP_IRQ6_EINT 0x0020 /* DSP_IRQ6_EINT */ 3379*4882a593Smuzhiyun #define WM5100_DSP_IRQ6_EINT_MASK 0x0020 /* DSP_IRQ6_EINT */ 3380*4882a593Smuzhiyun #define WM5100_DSP_IRQ6_EINT_SHIFT 5 /* DSP_IRQ6_EINT */ 3381*4882a593Smuzhiyun #define WM5100_DSP_IRQ6_EINT_WIDTH 1 /* DSP_IRQ6_EINT */ 3382*4882a593Smuzhiyun #define WM5100_DSP_IRQ5_EINT 0x0010 /* DSP_IRQ5_EINT */ 3383*4882a593Smuzhiyun #define WM5100_DSP_IRQ5_EINT_MASK 0x0010 /* DSP_IRQ5_EINT */ 3384*4882a593Smuzhiyun #define WM5100_DSP_IRQ5_EINT_SHIFT 4 /* DSP_IRQ5_EINT */ 3385*4882a593Smuzhiyun #define WM5100_DSP_IRQ5_EINT_WIDTH 1 /* DSP_IRQ5_EINT */ 3386*4882a593Smuzhiyun #define WM5100_DSP_IRQ4_EINT 0x0008 /* DSP_IRQ4_EINT */ 3387*4882a593Smuzhiyun #define WM5100_DSP_IRQ4_EINT_MASK 0x0008 /* DSP_IRQ4_EINT */ 3388*4882a593Smuzhiyun #define WM5100_DSP_IRQ4_EINT_SHIFT 3 /* DSP_IRQ4_EINT */ 3389*4882a593Smuzhiyun #define WM5100_DSP_IRQ4_EINT_WIDTH 1 /* DSP_IRQ4_EINT */ 3390*4882a593Smuzhiyun #define WM5100_DSP_IRQ3_EINT 0x0004 /* DSP_IRQ3_EINT */ 3391*4882a593Smuzhiyun #define WM5100_DSP_IRQ3_EINT_MASK 0x0004 /* DSP_IRQ3_EINT */ 3392*4882a593Smuzhiyun #define WM5100_DSP_IRQ3_EINT_SHIFT 2 /* DSP_IRQ3_EINT */ 3393*4882a593Smuzhiyun #define WM5100_DSP_IRQ3_EINT_WIDTH 1 /* DSP_IRQ3_EINT */ 3394*4882a593Smuzhiyun #define WM5100_DSP_IRQ2_EINT 0x0002 /* DSP_IRQ2_EINT */ 3395*4882a593Smuzhiyun #define WM5100_DSP_IRQ2_EINT_MASK 0x0002 /* DSP_IRQ2_EINT */ 3396*4882a593Smuzhiyun #define WM5100_DSP_IRQ2_EINT_SHIFT 1 /* DSP_IRQ2_EINT */ 3397*4882a593Smuzhiyun #define WM5100_DSP_IRQ2_EINT_WIDTH 1 /* DSP_IRQ2_EINT */ 3398*4882a593Smuzhiyun #define WM5100_DSP_IRQ1_EINT 0x0001 /* DSP_IRQ1_EINT */ 3399*4882a593Smuzhiyun #define WM5100_DSP_IRQ1_EINT_MASK 0x0001 /* DSP_IRQ1_EINT */ 3400*4882a593Smuzhiyun #define WM5100_DSP_IRQ1_EINT_SHIFT 0 /* DSP_IRQ1_EINT */ 3401*4882a593Smuzhiyun #define WM5100_DSP_IRQ1_EINT_WIDTH 1 /* DSP_IRQ1_EINT */ 3402*4882a593Smuzhiyun 3403*4882a593Smuzhiyun /* 3404*4882a593Smuzhiyun * R3330 (0xD02) - Interrupt Status 3 3405*4882a593Smuzhiyun */ 3406*4882a593Smuzhiyun #define WM5100_SPK_SHUTDOWN_WARN_EINT 0x8000 /* SPK_SHUTDOWN_WARN_EINT */ 3407*4882a593Smuzhiyun #define WM5100_SPK_SHUTDOWN_WARN_EINT_MASK 0x8000 /* SPK_SHUTDOWN_WARN_EINT */ 3408*4882a593Smuzhiyun #define WM5100_SPK_SHUTDOWN_WARN_EINT_SHIFT 15 /* SPK_SHUTDOWN_WARN_EINT */ 3409*4882a593Smuzhiyun #define WM5100_SPK_SHUTDOWN_WARN_EINT_WIDTH 1 /* SPK_SHUTDOWN_WARN_EINT */ 3410*4882a593Smuzhiyun #define WM5100_SPK_SHUTDOWN_EINT 0x4000 /* SPK_SHUTDOWN_EINT */ 3411*4882a593Smuzhiyun #define WM5100_SPK_SHUTDOWN_EINT_MASK 0x4000 /* SPK_SHUTDOWN_EINT */ 3412*4882a593Smuzhiyun #define WM5100_SPK_SHUTDOWN_EINT_SHIFT 14 /* SPK_SHUTDOWN_EINT */ 3413*4882a593Smuzhiyun #define WM5100_SPK_SHUTDOWN_EINT_WIDTH 1 /* SPK_SHUTDOWN_EINT */ 3414*4882a593Smuzhiyun #define WM5100_HPDET_EINT 0x2000 /* HPDET_EINT */ 3415*4882a593Smuzhiyun #define WM5100_HPDET_EINT_MASK 0x2000 /* HPDET_EINT */ 3416*4882a593Smuzhiyun #define WM5100_HPDET_EINT_SHIFT 13 /* HPDET_EINT */ 3417*4882a593Smuzhiyun #define WM5100_HPDET_EINT_WIDTH 1 /* HPDET_EINT */ 3418*4882a593Smuzhiyun #define WM5100_ACCDET_EINT 0x1000 /* ACCDET_EINT */ 3419*4882a593Smuzhiyun #define WM5100_ACCDET_EINT_MASK 0x1000 /* ACCDET_EINT */ 3420*4882a593Smuzhiyun #define WM5100_ACCDET_EINT_SHIFT 12 /* ACCDET_EINT */ 3421*4882a593Smuzhiyun #define WM5100_ACCDET_EINT_WIDTH 1 /* ACCDET_EINT */ 3422*4882a593Smuzhiyun #define WM5100_DRC_SIG_DET_EINT 0x0200 /* DRC_SIG_DET_EINT */ 3423*4882a593Smuzhiyun #define WM5100_DRC_SIG_DET_EINT_MASK 0x0200 /* DRC_SIG_DET_EINT */ 3424*4882a593Smuzhiyun #define WM5100_DRC_SIG_DET_EINT_SHIFT 9 /* DRC_SIG_DET_EINT */ 3425*4882a593Smuzhiyun #define WM5100_DRC_SIG_DET_EINT_WIDTH 1 /* DRC_SIG_DET_EINT */ 3426*4882a593Smuzhiyun #define WM5100_ASRC2_LOCK_EINT 0x0100 /* ASRC2_LOCK_EINT */ 3427*4882a593Smuzhiyun #define WM5100_ASRC2_LOCK_EINT_MASK 0x0100 /* ASRC2_LOCK_EINT */ 3428*4882a593Smuzhiyun #define WM5100_ASRC2_LOCK_EINT_SHIFT 8 /* ASRC2_LOCK_EINT */ 3429*4882a593Smuzhiyun #define WM5100_ASRC2_LOCK_EINT_WIDTH 1 /* ASRC2_LOCK_EINT */ 3430*4882a593Smuzhiyun #define WM5100_ASRC1_LOCK_EINT 0x0080 /* ASRC1_LOCK_EINT */ 3431*4882a593Smuzhiyun #define WM5100_ASRC1_LOCK_EINT_MASK 0x0080 /* ASRC1_LOCK_EINT */ 3432*4882a593Smuzhiyun #define WM5100_ASRC1_LOCK_EINT_SHIFT 7 /* ASRC1_LOCK_EINT */ 3433*4882a593Smuzhiyun #define WM5100_ASRC1_LOCK_EINT_WIDTH 1 /* ASRC1_LOCK_EINT */ 3434*4882a593Smuzhiyun #define WM5100_FLL2_LOCK_EINT 0x0008 /* FLL2_LOCK_EINT */ 3435*4882a593Smuzhiyun #define WM5100_FLL2_LOCK_EINT_MASK 0x0008 /* FLL2_LOCK_EINT */ 3436*4882a593Smuzhiyun #define WM5100_FLL2_LOCK_EINT_SHIFT 3 /* FLL2_LOCK_EINT */ 3437*4882a593Smuzhiyun #define WM5100_FLL2_LOCK_EINT_WIDTH 1 /* FLL2_LOCK_EINT */ 3438*4882a593Smuzhiyun #define WM5100_FLL1_LOCK_EINT 0x0004 /* FLL1_LOCK_EINT */ 3439*4882a593Smuzhiyun #define WM5100_FLL1_LOCK_EINT_MASK 0x0004 /* FLL1_LOCK_EINT */ 3440*4882a593Smuzhiyun #define WM5100_FLL1_LOCK_EINT_SHIFT 2 /* FLL1_LOCK_EINT */ 3441*4882a593Smuzhiyun #define WM5100_FLL1_LOCK_EINT_WIDTH 1 /* FLL1_LOCK_EINT */ 3442*4882a593Smuzhiyun #define WM5100_CLKGEN_ERR_EINT 0x0002 /* CLKGEN_ERR_EINT */ 3443*4882a593Smuzhiyun #define WM5100_CLKGEN_ERR_EINT_MASK 0x0002 /* CLKGEN_ERR_EINT */ 3444*4882a593Smuzhiyun #define WM5100_CLKGEN_ERR_EINT_SHIFT 1 /* CLKGEN_ERR_EINT */ 3445*4882a593Smuzhiyun #define WM5100_CLKGEN_ERR_EINT_WIDTH 1 /* CLKGEN_ERR_EINT */ 3446*4882a593Smuzhiyun #define WM5100_CLKGEN_ERR_ASYNC_EINT 0x0001 /* CLKGEN_ERR_ASYNC_EINT */ 3447*4882a593Smuzhiyun #define WM5100_CLKGEN_ERR_ASYNC_EINT_MASK 0x0001 /* CLKGEN_ERR_ASYNC_EINT */ 3448*4882a593Smuzhiyun #define WM5100_CLKGEN_ERR_ASYNC_EINT_SHIFT 0 /* CLKGEN_ERR_ASYNC_EINT */ 3449*4882a593Smuzhiyun #define WM5100_CLKGEN_ERR_ASYNC_EINT_WIDTH 1 /* CLKGEN_ERR_ASYNC_EINT */ 3450*4882a593Smuzhiyun 3451*4882a593Smuzhiyun /* 3452*4882a593Smuzhiyun * R3331 (0xD03) - Interrupt Status 4 3453*4882a593Smuzhiyun */ 3454*4882a593Smuzhiyun #define WM5100_AIF3_ERR_EINT 0x2000 /* AIF3_ERR_EINT */ 3455*4882a593Smuzhiyun #define WM5100_AIF3_ERR_EINT_MASK 0x2000 /* AIF3_ERR_EINT */ 3456*4882a593Smuzhiyun #define WM5100_AIF3_ERR_EINT_SHIFT 13 /* AIF3_ERR_EINT */ 3457*4882a593Smuzhiyun #define WM5100_AIF3_ERR_EINT_WIDTH 1 /* AIF3_ERR_EINT */ 3458*4882a593Smuzhiyun #define WM5100_AIF2_ERR_EINT 0x1000 /* AIF2_ERR_EINT */ 3459*4882a593Smuzhiyun #define WM5100_AIF2_ERR_EINT_MASK 0x1000 /* AIF2_ERR_EINT */ 3460*4882a593Smuzhiyun #define WM5100_AIF2_ERR_EINT_SHIFT 12 /* AIF2_ERR_EINT */ 3461*4882a593Smuzhiyun #define WM5100_AIF2_ERR_EINT_WIDTH 1 /* AIF2_ERR_EINT */ 3462*4882a593Smuzhiyun #define WM5100_AIF1_ERR_EINT 0x0800 /* AIF1_ERR_EINT */ 3463*4882a593Smuzhiyun #define WM5100_AIF1_ERR_EINT_MASK 0x0800 /* AIF1_ERR_EINT */ 3464*4882a593Smuzhiyun #define WM5100_AIF1_ERR_EINT_SHIFT 11 /* AIF1_ERR_EINT */ 3465*4882a593Smuzhiyun #define WM5100_AIF1_ERR_EINT_WIDTH 1 /* AIF1_ERR_EINT */ 3466*4882a593Smuzhiyun #define WM5100_CTRLIF_ERR_EINT 0x0400 /* CTRLIF_ERR_EINT */ 3467*4882a593Smuzhiyun #define WM5100_CTRLIF_ERR_EINT_MASK 0x0400 /* CTRLIF_ERR_EINT */ 3468*4882a593Smuzhiyun #define WM5100_CTRLIF_ERR_EINT_SHIFT 10 /* CTRLIF_ERR_EINT */ 3469*4882a593Smuzhiyun #define WM5100_CTRLIF_ERR_EINT_WIDTH 1 /* CTRLIF_ERR_EINT */ 3470*4882a593Smuzhiyun #define WM5100_ISRC2_UNDERCLOCKED_EINT 0x0200 /* ISRC2_UNDERCLOCKED_EINT */ 3471*4882a593Smuzhiyun #define WM5100_ISRC2_UNDERCLOCKED_EINT_MASK 0x0200 /* ISRC2_UNDERCLOCKED_EINT */ 3472*4882a593Smuzhiyun #define WM5100_ISRC2_UNDERCLOCKED_EINT_SHIFT 9 /* ISRC2_UNDERCLOCKED_EINT */ 3473*4882a593Smuzhiyun #define WM5100_ISRC2_UNDERCLOCKED_EINT_WIDTH 1 /* ISRC2_UNDERCLOCKED_EINT */ 3474*4882a593Smuzhiyun #define WM5100_ISRC1_UNDERCLOCKED_EINT 0x0100 /* ISRC1_UNDERCLOCKED_EINT */ 3475*4882a593Smuzhiyun #define WM5100_ISRC1_UNDERCLOCKED_EINT_MASK 0x0100 /* ISRC1_UNDERCLOCKED_EINT */ 3476*4882a593Smuzhiyun #define WM5100_ISRC1_UNDERCLOCKED_EINT_SHIFT 8 /* ISRC1_UNDERCLOCKED_EINT */ 3477*4882a593Smuzhiyun #define WM5100_ISRC1_UNDERCLOCKED_EINT_WIDTH 1 /* ISRC1_UNDERCLOCKED_EINT */ 3478*4882a593Smuzhiyun #define WM5100_FX_UNDERCLOCKED_EINT 0x0080 /* FX_UNDERCLOCKED_EINT */ 3479*4882a593Smuzhiyun #define WM5100_FX_UNDERCLOCKED_EINT_MASK 0x0080 /* FX_UNDERCLOCKED_EINT */ 3480*4882a593Smuzhiyun #define WM5100_FX_UNDERCLOCKED_EINT_SHIFT 7 /* FX_UNDERCLOCKED_EINT */ 3481*4882a593Smuzhiyun #define WM5100_FX_UNDERCLOCKED_EINT_WIDTH 1 /* FX_UNDERCLOCKED_EINT */ 3482*4882a593Smuzhiyun #define WM5100_AIF3_UNDERCLOCKED_EINT 0x0040 /* AIF3_UNDERCLOCKED_EINT */ 3483*4882a593Smuzhiyun #define WM5100_AIF3_UNDERCLOCKED_EINT_MASK 0x0040 /* AIF3_UNDERCLOCKED_EINT */ 3484*4882a593Smuzhiyun #define WM5100_AIF3_UNDERCLOCKED_EINT_SHIFT 6 /* AIF3_UNDERCLOCKED_EINT */ 3485*4882a593Smuzhiyun #define WM5100_AIF3_UNDERCLOCKED_EINT_WIDTH 1 /* AIF3_UNDERCLOCKED_EINT */ 3486*4882a593Smuzhiyun #define WM5100_AIF2_UNDERCLOCKED_EINT 0x0020 /* AIF2_UNDERCLOCKED_EINT */ 3487*4882a593Smuzhiyun #define WM5100_AIF2_UNDERCLOCKED_EINT_MASK 0x0020 /* AIF2_UNDERCLOCKED_EINT */ 3488*4882a593Smuzhiyun #define WM5100_AIF2_UNDERCLOCKED_EINT_SHIFT 5 /* AIF2_UNDERCLOCKED_EINT */ 3489*4882a593Smuzhiyun #define WM5100_AIF2_UNDERCLOCKED_EINT_WIDTH 1 /* AIF2_UNDERCLOCKED_EINT */ 3490*4882a593Smuzhiyun #define WM5100_AIF1_UNDERCLOCKED_EINT 0x0010 /* AIF1_UNDERCLOCKED_EINT */ 3491*4882a593Smuzhiyun #define WM5100_AIF1_UNDERCLOCKED_EINT_MASK 0x0010 /* AIF1_UNDERCLOCKED_EINT */ 3492*4882a593Smuzhiyun #define WM5100_AIF1_UNDERCLOCKED_EINT_SHIFT 4 /* AIF1_UNDERCLOCKED_EINT */ 3493*4882a593Smuzhiyun #define WM5100_AIF1_UNDERCLOCKED_EINT_WIDTH 1 /* AIF1_UNDERCLOCKED_EINT */ 3494*4882a593Smuzhiyun #define WM5100_ASRC_UNDERCLOCKED_EINT 0x0008 /* ASRC_UNDERCLOCKED_EINT */ 3495*4882a593Smuzhiyun #define WM5100_ASRC_UNDERCLOCKED_EINT_MASK 0x0008 /* ASRC_UNDERCLOCKED_EINT */ 3496*4882a593Smuzhiyun #define WM5100_ASRC_UNDERCLOCKED_EINT_SHIFT 3 /* ASRC_UNDERCLOCKED_EINT */ 3497*4882a593Smuzhiyun #define WM5100_ASRC_UNDERCLOCKED_EINT_WIDTH 1 /* ASRC_UNDERCLOCKED_EINT */ 3498*4882a593Smuzhiyun #define WM5100_DAC_UNDERCLOCKED_EINT 0x0004 /* DAC_UNDERCLOCKED_EINT */ 3499*4882a593Smuzhiyun #define WM5100_DAC_UNDERCLOCKED_EINT_MASK 0x0004 /* DAC_UNDERCLOCKED_EINT */ 3500*4882a593Smuzhiyun #define WM5100_DAC_UNDERCLOCKED_EINT_SHIFT 2 /* DAC_UNDERCLOCKED_EINT */ 3501*4882a593Smuzhiyun #define WM5100_DAC_UNDERCLOCKED_EINT_WIDTH 1 /* DAC_UNDERCLOCKED_EINT */ 3502*4882a593Smuzhiyun #define WM5100_ADC_UNDERCLOCKED_EINT 0x0002 /* ADC_UNDERCLOCKED_EINT */ 3503*4882a593Smuzhiyun #define WM5100_ADC_UNDERCLOCKED_EINT_MASK 0x0002 /* ADC_UNDERCLOCKED_EINT */ 3504*4882a593Smuzhiyun #define WM5100_ADC_UNDERCLOCKED_EINT_SHIFT 1 /* ADC_UNDERCLOCKED_EINT */ 3505*4882a593Smuzhiyun #define WM5100_ADC_UNDERCLOCKED_EINT_WIDTH 1 /* ADC_UNDERCLOCKED_EINT */ 3506*4882a593Smuzhiyun #define WM5100_MIXER_UNDERCLOCKED_EINT 0x0001 /* MIXER_UNDERCLOCKED_EINT */ 3507*4882a593Smuzhiyun #define WM5100_MIXER_UNDERCLOCKED_EINT_MASK 0x0001 /* MIXER_UNDERCLOCKED_EINT */ 3508*4882a593Smuzhiyun #define WM5100_MIXER_UNDERCLOCKED_EINT_SHIFT 0 /* MIXER_UNDERCLOCKED_EINT */ 3509*4882a593Smuzhiyun #define WM5100_MIXER_UNDERCLOCKED_EINT_WIDTH 1 /* MIXER_UNDERCLOCKED_EINT */ 3510*4882a593Smuzhiyun 3511*4882a593Smuzhiyun /* 3512*4882a593Smuzhiyun * R3332 (0xD04) - Interrupt Raw Status 2 3513*4882a593Smuzhiyun */ 3514*4882a593Smuzhiyun #define WM5100_DSP_IRQ6_STS 0x0020 /* DSP_IRQ6_STS */ 3515*4882a593Smuzhiyun #define WM5100_DSP_IRQ6_STS_MASK 0x0020 /* DSP_IRQ6_STS */ 3516*4882a593Smuzhiyun #define WM5100_DSP_IRQ6_STS_SHIFT 5 /* DSP_IRQ6_STS */ 3517*4882a593Smuzhiyun #define WM5100_DSP_IRQ6_STS_WIDTH 1 /* DSP_IRQ6_STS */ 3518*4882a593Smuzhiyun #define WM5100_DSP_IRQ5_STS 0x0010 /* DSP_IRQ5_STS */ 3519*4882a593Smuzhiyun #define WM5100_DSP_IRQ5_STS_MASK 0x0010 /* DSP_IRQ5_STS */ 3520*4882a593Smuzhiyun #define WM5100_DSP_IRQ5_STS_SHIFT 4 /* DSP_IRQ5_STS */ 3521*4882a593Smuzhiyun #define WM5100_DSP_IRQ5_STS_WIDTH 1 /* DSP_IRQ5_STS */ 3522*4882a593Smuzhiyun #define WM5100_DSP_IRQ4_STS 0x0008 /* DSP_IRQ4_STS */ 3523*4882a593Smuzhiyun #define WM5100_DSP_IRQ4_STS_MASK 0x0008 /* DSP_IRQ4_STS */ 3524*4882a593Smuzhiyun #define WM5100_DSP_IRQ4_STS_SHIFT 3 /* DSP_IRQ4_STS */ 3525*4882a593Smuzhiyun #define WM5100_DSP_IRQ4_STS_WIDTH 1 /* DSP_IRQ4_STS */ 3526*4882a593Smuzhiyun #define WM5100_DSP_IRQ3_STS 0x0004 /* DSP_IRQ3_STS */ 3527*4882a593Smuzhiyun #define WM5100_DSP_IRQ3_STS_MASK 0x0004 /* DSP_IRQ3_STS */ 3528*4882a593Smuzhiyun #define WM5100_DSP_IRQ3_STS_SHIFT 2 /* DSP_IRQ3_STS */ 3529*4882a593Smuzhiyun #define WM5100_DSP_IRQ3_STS_WIDTH 1 /* DSP_IRQ3_STS */ 3530*4882a593Smuzhiyun #define WM5100_DSP_IRQ2_STS 0x0002 /* DSP_IRQ2_STS */ 3531*4882a593Smuzhiyun #define WM5100_DSP_IRQ2_STS_MASK 0x0002 /* DSP_IRQ2_STS */ 3532*4882a593Smuzhiyun #define WM5100_DSP_IRQ2_STS_SHIFT 1 /* DSP_IRQ2_STS */ 3533*4882a593Smuzhiyun #define WM5100_DSP_IRQ2_STS_WIDTH 1 /* DSP_IRQ2_STS */ 3534*4882a593Smuzhiyun #define WM5100_DSP_IRQ1_STS 0x0001 /* DSP_IRQ1_STS */ 3535*4882a593Smuzhiyun #define WM5100_DSP_IRQ1_STS_MASK 0x0001 /* DSP_IRQ1_STS */ 3536*4882a593Smuzhiyun #define WM5100_DSP_IRQ1_STS_SHIFT 0 /* DSP_IRQ1_STS */ 3537*4882a593Smuzhiyun #define WM5100_DSP_IRQ1_STS_WIDTH 1 /* DSP_IRQ1_STS */ 3538*4882a593Smuzhiyun 3539*4882a593Smuzhiyun /* 3540*4882a593Smuzhiyun * R3333 (0xD05) - Interrupt Raw Status 3 3541*4882a593Smuzhiyun */ 3542*4882a593Smuzhiyun #define WM5100_SPK_SHUTDOWN_WARN_STS 0x8000 /* SPK_SHUTDOWN_WARN_STS */ 3543*4882a593Smuzhiyun #define WM5100_SPK_SHUTDOWN_WARN_STS_MASK 0x8000 /* SPK_SHUTDOWN_WARN_STS */ 3544*4882a593Smuzhiyun #define WM5100_SPK_SHUTDOWN_WARN_STS_SHIFT 15 /* SPK_SHUTDOWN_WARN_STS */ 3545*4882a593Smuzhiyun #define WM5100_SPK_SHUTDOWN_WARN_STS_WIDTH 1 /* SPK_SHUTDOWN_WARN_STS */ 3546*4882a593Smuzhiyun #define WM5100_SPK_SHUTDOWN_STS 0x4000 /* SPK_SHUTDOWN_STS */ 3547*4882a593Smuzhiyun #define WM5100_SPK_SHUTDOWN_STS_MASK 0x4000 /* SPK_SHUTDOWN_STS */ 3548*4882a593Smuzhiyun #define WM5100_SPK_SHUTDOWN_STS_SHIFT 14 /* SPK_SHUTDOWN_STS */ 3549*4882a593Smuzhiyun #define WM5100_SPK_SHUTDOWN_STS_WIDTH 1 /* SPK_SHUTDOWN_STS */ 3550*4882a593Smuzhiyun #define WM5100_HPDET_STS 0x2000 /* HPDET_STS */ 3551*4882a593Smuzhiyun #define WM5100_HPDET_STS_MASK 0x2000 /* HPDET_STS */ 3552*4882a593Smuzhiyun #define WM5100_HPDET_STS_SHIFT 13 /* HPDET_STS */ 3553*4882a593Smuzhiyun #define WM5100_HPDET_STS_WIDTH 1 /* HPDET_STS */ 3554*4882a593Smuzhiyun #define WM5100_DRC_SID_DET_STS 0x0200 /* DRC_SID_DET_STS */ 3555*4882a593Smuzhiyun #define WM5100_DRC_SID_DET_STS_MASK 0x0200 /* DRC_SID_DET_STS */ 3556*4882a593Smuzhiyun #define WM5100_DRC_SID_DET_STS_SHIFT 9 /* DRC_SID_DET_STS */ 3557*4882a593Smuzhiyun #define WM5100_DRC_SID_DET_STS_WIDTH 1 /* DRC_SID_DET_STS */ 3558*4882a593Smuzhiyun #define WM5100_ASRC2_LOCK_STS 0x0100 /* ASRC2_LOCK_STS */ 3559*4882a593Smuzhiyun #define WM5100_ASRC2_LOCK_STS_MASK 0x0100 /* ASRC2_LOCK_STS */ 3560*4882a593Smuzhiyun #define WM5100_ASRC2_LOCK_STS_SHIFT 8 /* ASRC2_LOCK_STS */ 3561*4882a593Smuzhiyun #define WM5100_ASRC2_LOCK_STS_WIDTH 1 /* ASRC2_LOCK_STS */ 3562*4882a593Smuzhiyun #define WM5100_ASRC1_LOCK_STS 0x0080 /* ASRC1_LOCK_STS */ 3563*4882a593Smuzhiyun #define WM5100_ASRC1_LOCK_STS_MASK 0x0080 /* ASRC1_LOCK_STS */ 3564*4882a593Smuzhiyun #define WM5100_ASRC1_LOCK_STS_SHIFT 7 /* ASRC1_LOCK_STS */ 3565*4882a593Smuzhiyun #define WM5100_ASRC1_LOCK_STS_WIDTH 1 /* ASRC1_LOCK_STS */ 3566*4882a593Smuzhiyun #define WM5100_FLL2_LOCK_STS 0x0008 /* FLL2_LOCK_STS */ 3567*4882a593Smuzhiyun #define WM5100_FLL2_LOCK_STS_MASK 0x0008 /* FLL2_LOCK_STS */ 3568*4882a593Smuzhiyun #define WM5100_FLL2_LOCK_STS_SHIFT 3 /* FLL2_LOCK_STS */ 3569*4882a593Smuzhiyun #define WM5100_FLL2_LOCK_STS_WIDTH 1 /* FLL2_LOCK_STS */ 3570*4882a593Smuzhiyun #define WM5100_FLL1_LOCK_STS 0x0004 /* FLL1_LOCK_STS */ 3571*4882a593Smuzhiyun #define WM5100_FLL1_LOCK_STS_MASK 0x0004 /* FLL1_LOCK_STS */ 3572*4882a593Smuzhiyun #define WM5100_FLL1_LOCK_STS_SHIFT 2 /* FLL1_LOCK_STS */ 3573*4882a593Smuzhiyun #define WM5100_FLL1_LOCK_STS_WIDTH 1 /* FLL1_LOCK_STS */ 3574*4882a593Smuzhiyun #define WM5100_CLKGEN_ERR_STS 0x0002 /* CLKGEN_ERR_STS */ 3575*4882a593Smuzhiyun #define WM5100_CLKGEN_ERR_STS_MASK 0x0002 /* CLKGEN_ERR_STS */ 3576*4882a593Smuzhiyun #define WM5100_CLKGEN_ERR_STS_SHIFT 1 /* CLKGEN_ERR_STS */ 3577*4882a593Smuzhiyun #define WM5100_CLKGEN_ERR_STS_WIDTH 1 /* CLKGEN_ERR_STS */ 3578*4882a593Smuzhiyun #define WM5100_CLKGEN_ERR_ASYNC_STS 0x0001 /* CLKGEN_ERR_ASYNC_STS */ 3579*4882a593Smuzhiyun #define WM5100_CLKGEN_ERR_ASYNC_STS_MASK 0x0001 /* CLKGEN_ERR_ASYNC_STS */ 3580*4882a593Smuzhiyun #define WM5100_CLKGEN_ERR_ASYNC_STS_SHIFT 0 /* CLKGEN_ERR_ASYNC_STS */ 3581*4882a593Smuzhiyun #define WM5100_CLKGEN_ERR_ASYNC_STS_WIDTH 1 /* CLKGEN_ERR_ASYNC_STS */ 3582*4882a593Smuzhiyun 3583*4882a593Smuzhiyun /* 3584*4882a593Smuzhiyun * R3334 (0xD06) - Interrupt Raw Status 4 3585*4882a593Smuzhiyun */ 3586*4882a593Smuzhiyun #define WM5100_AIF3_ERR_STS 0x2000 /* AIF3_ERR_STS */ 3587*4882a593Smuzhiyun #define WM5100_AIF3_ERR_STS_MASK 0x2000 /* AIF3_ERR_STS */ 3588*4882a593Smuzhiyun #define WM5100_AIF3_ERR_STS_SHIFT 13 /* AIF3_ERR_STS */ 3589*4882a593Smuzhiyun #define WM5100_AIF3_ERR_STS_WIDTH 1 /* AIF3_ERR_STS */ 3590*4882a593Smuzhiyun #define WM5100_AIF2_ERR_STS 0x1000 /* AIF2_ERR_STS */ 3591*4882a593Smuzhiyun #define WM5100_AIF2_ERR_STS_MASK 0x1000 /* AIF2_ERR_STS */ 3592*4882a593Smuzhiyun #define WM5100_AIF2_ERR_STS_SHIFT 12 /* AIF2_ERR_STS */ 3593*4882a593Smuzhiyun #define WM5100_AIF2_ERR_STS_WIDTH 1 /* AIF2_ERR_STS */ 3594*4882a593Smuzhiyun #define WM5100_AIF1_ERR_STS 0x0800 /* AIF1_ERR_STS */ 3595*4882a593Smuzhiyun #define WM5100_AIF1_ERR_STS_MASK 0x0800 /* AIF1_ERR_STS */ 3596*4882a593Smuzhiyun #define WM5100_AIF1_ERR_STS_SHIFT 11 /* AIF1_ERR_STS */ 3597*4882a593Smuzhiyun #define WM5100_AIF1_ERR_STS_WIDTH 1 /* AIF1_ERR_STS */ 3598*4882a593Smuzhiyun #define WM5100_CTRLIF_ERR_STS 0x0400 /* CTRLIF_ERR_STS */ 3599*4882a593Smuzhiyun #define WM5100_CTRLIF_ERR_STS_MASK 0x0400 /* CTRLIF_ERR_STS */ 3600*4882a593Smuzhiyun #define WM5100_CTRLIF_ERR_STS_SHIFT 10 /* CTRLIF_ERR_STS */ 3601*4882a593Smuzhiyun #define WM5100_CTRLIF_ERR_STS_WIDTH 1 /* CTRLIF_ERR_STS */ 3602*4882a593Smuzhiyun #define WM5100_ISRC2_UNDERCLOCKED_STS 0x0200 /* ISRC2_UNDERCLOCKED_STS */ 3603*4882a593Smuzhiyun #define WM5100_ISRC2_UNDERCLOCKED_STS_MASK 0x0200 /* ISRC2_UNDERCLOCKED_STS */ 3604*4882a593Smuzhiyun #define WM5100_ISRC2_UNDERCLOCKED_STS_SHIFT 9 /* ISRC2_UNDERCLOCKED_STS */ 3605*4882a593Smuzhiyun #define WM5100_ISRC2_UNDERCLOCKED_STS_WIDTH 1 /* ISRC2_UNDERCLOCKED_STS */ 3606*4882a593Smuzhiyun #define WM5100_ISRC1_UNDERCLOCKED_STS 0x0100 /* ISRC1_UNDERCLOCKED_STS */ 3607*4882a593Smuzhiyun #define WM5100_ISRC1_UNDERCLOCKED_STS_MASK 0x0100 /* ISRC1_UNDERCLOCKED_STS */ 3608*4882a593Smuzhiyun #define WM5100_ISRC1_UNDERCLOCKED_STS_SHIFT 8 /* ISRC1_UNDERCLOCKED_STS */ 3609*4882a593Smuzhiyun #define WM5100_ISRC1_UNDERCLOCKED_STS_WIDTH 1 /* ISRC1_UNDERCLOCKED_STS */ 3610*4882a593Smuzhiyun #define WM5100_FX_UNDERCLOCKED_STS 0x0080 /* FX_UNDERCLOCKED_STS */ 3611*4882a593Smuzhiyun #define WM5100_FX_UNDERCLOCKED_STS_MASK 0x0080 /* FX_UNDERCLOCKED_STS */ 3612*4882a593Smuzhiyun #define WM5100_FX_UNDERCLOCKED_STS_SHIFT 7 /* FX_UNDERCLOCKED_STS */ 3613*4882a593Smuzhiyun #define WM5100_FX_UNDERCLOCKED_STS_WIDTH 1 /* FX_UNDERCLOCKED_STS */ 3614*4882a593Smuzhiyun #define WM5100_AIF3_UNDERCLOCKED_STS 0x0040 /* AIF3_UNDERCLOCKED_STS */ 3615*4882a593Smuzhiyun #define WM5100_AIF3_UNDERCLOCKED_STS_MASK 0x0040 /* AIF3_UNDERCLOCKED_STS */ 3616*4882a593Smuzhiyun #define WM5100_AIF3_UNDERCLOCKED_STS_SHIFT 6 /* AIF3_UNDERCLOCKED_STS */ 3617*4882a593Smuzhiyun #define WM5100_AIF3_UNDERCLOCKED_STS_WIDTH 1 /* AIF3_UNDERCLOCKED_STS */ 3618*4882a593Smuzhiyun #define WM5100_AIF2_UNDERCLOCKED_STS 0x0020 /* AIF2_UNDERCLOCKED_STS */ 3619*4882a593Smuzhiyun #define WM5100_AIF2_UNDERCLOCKED_STS_MASK 0x0020 /* AIF2_UNDERCLOCKED_STS */ 3620*4882a593Smuzhiyun #define WM5100_AIF2_UNDERCLOCKED_STS_SHIFT 5 /* AIF2_UNDERCLOCKED_STS */ 3621*4882a593Smuzhiyun #define WM5100_AIF2_UNDERCLOCKED_STS_WIDTH 1 /* AIF2_UNDERCLOCKED_STS */ 3622*4882a593Smuzhiyun #define WM5100_AIF1_UNDERCLOCKED_STS 0x0010 /* AIF1_UNDERCLOCKED_STS */ 3623*4882a593Smuzhiyun #define WM5100_AIF1_UNDERCLOCKED_STS_MASK 0x0010 /* AIF1_UNDERCLOCKED_STS */ 3624*4882a593Smuzhiyun #define WM5100_AIF1_UNDERCLOCKED_STS_SHIFT 4 /* AIF1_UNDERCLOCKED_STS */ 3625*4882a593Smuzhiyun #define WM5100_AIF1_UNDERCLOCKED_STS_WIDTH 1 /* AIF1_UNDERCLOCKED_STS */ 3626*4882a593Smuzhiyun #define WM5100_ASRC_UNDERCLOCKED_STS 0x0008 /* ASRC_UNDERCLOCKED_STS */ 3627*4882a593Smuzhiyun #define WM5100_ASRC_UNDERCLOCKED_STS_MASK 0x0008 /* ASRC_UNDERCLOCKED_STS */ 3628*4882a593Smuzhiyun #define WM5100_ASRC_UNDERCLOCKED_STS_SHIFT 3 /* ASRC_UNDERCLOCKED_STS */ 3629*4882a593Smuzhiyun #define WM5100_ASRC_UNDERCLOCKED_STS_WIDTH 1 /* ASRC_UNDERCLOCKED_STS */ 3630*4882a593Smuzhiyun #define WM5100_DAC_UNDERCLOCKED_STS 0x0004 /* DAC_UNDERCLOCKED_STS */ 3631*4882a593Smuzhiyun #define WM5100_DAC_UNDERCLOCKED_STS_MASK 0x0004 /* DAC_UNDERCLOCKED_STS */ 3632*4882a593Smuzhiyun #define WM5100_DAC_UNDERCLOCKED_STS_SHIFT 2 /* DAC_UNDERCLOCKED_STS */ 3633*4882a593Smuzhiyun #define WM5100_DAC_UNDERCLOCKED_STS_WIDTH 1 /* DAC_UNDERCLOCKED_STS */ 3634*4882a593Smuzhiyun #define WM5100_ADC_UNDERCLOCKED_STS 0x0002 /* ADC_UNDERCLOCKED_STS */ 3635*4882a593Smuzhiyun #define WM5100_ADC_UNDERCLOCKED_STS_MASK 0x0002 /* ADC_UNDERCLOCKED_STS */ 3636*4882a593Smuzhiyun #define WM5100_ADC_UNDERCLOCKED_STS_SHIFT 1 /* ADC_UNDERCLOCKED_STS */ 3637*4882a593Smuzhiyun #define WM5100_ADC_UNDERCLOCKED_STS_WIDTH 1 /* ADC_UNDERCLOCKED_STS */ 3638*4882a593Smuzhiyun #define WM5100_MIXER_UNDERCLOCKED_STS 0x0001 /* MIXER_UNDERCLOCKED_STS */ 3639*4882a593Smuzhiyun #define WM5100_MIXER_UNDERCLOCKED_STS_MASK 0x0001 /* MIXER_UNDERCLOCKED_STS */ 3640*4882a593Smuzhiyun #define WM5100_MIXER_UNDERCLOCKED_STS_SHIFT 0 /* MIXER_UNDERCLOCKED_STS */ 3641*4882a593Smuzhiyun #define WM5100_MIXER_UNDERCLOCKED_STS_WIDTH 1 /* MIXER_UNDERCLOCKED_STS */ 3642*4882a593Smuzhiyun 3643*4882a593Smuzhiyun /* 3644*4882a593Smuzhiyun * R3335 (0xD07) - Interrupt Status 1 Mask 3645*4882a593Smuzhiyun */ 3646*4882a593Smuzhiyun #define WM5100_IM_GP6_EINT 0x0020 /* IM_GP6_EINT */ 3647*4882a593Smuzhiyun #define WM5100_IM_GP6_EINT_MASK 0x0020 /* IM_GP6_EINT */ 3648*4882a593Smuzhiyun #define WM5100_IM_GP6_EINT_SHIFT 5 /* IM_GP6_EINT */ 3649*4882a593Smuzhiyun #define WM5100_IM_GP6_EINT_WIDTH 1 /* IM_GP6_EINT */ 3650*4882a593Smuzhiyun #define WM5100_IM_GP5_EINT 0x0010 /* IM_GP5_EINT */ 3651*4882a593Smuzhiyun #define WM5100_IM_GP5_EINT_MASK 0x0010 /* IM_GP5_EINT */ 3652*4882a593Smuzhiyun #define WM5100_IM_GP5_EINT_SHIFT 4 /* IM_GP5_EINT */ 3653*4882a593Smuzhiyun #define WM5100_IM_GP5_EINT_WIDTH 1 /* IM_GP5_EINT */ 3654*4882a593Smuzhiyun #define WM5100_IM_GP4_EINT 0x0008 /* IM_GP4_EINT */ 3655*4882a593Smuzhiyun #define WM5100_IM_GP4_EINT_MASK 0x0008 /* IM_GP4_EINT */ 3656*4882a593Smuzhiyun #define WM5100_IM_GP4_EINT_SHIFT 3 /* IM_GP4_EINT */ 3657*4882a593Smuzhiyun #define WM5100_IM_GP4_EINT_WIDTH 1 /* IM_GP4_EINT */ 3658*4882a593Smuzhiyun #define WM5100_IM_GP3_EINT 0x0004 /* IM_GP3_EINT */ 3659*4882a593Smuzhiyun #define WM5100_IM_GP3_EINT_MASK 0x0004 /* IM_GP3_EINT */ 3660*4882a593Smuzhiyun #define WM5100_IM_GP3_EINT_SHIFT 2 /* IM_GP3_EINT */ 3661*4882a593Smuzhiyun #define WM5100_IM_GP3_EINT_WIDTH 1 /* IM_GP3_EINT */ 3662*4882a593Smuzhiyun #define WM5100_IM_GP2_EINT 0x0002 /* IM_GP2_EINT */ 3663*4882a593Smuzhiyun #define WM5100_IM_GP2_EINT_MASK 0x0002 /* IM_GP2_EINT */ 3664*4882a593Smuzhiyun #define WM5100_IM_GP2_EINT_SHIFT 1 /* IM_GP2_EINT */ 3665*4882a593Smuzhiyun #define WM5100_IM_GP2_EINT_WIDTH 1 /* IM_GP2_EINT */ 3666*4882a593Smuzhiyun #define WM5100_IM_GP1_EINT 0x0001 /* IM_GP1_EINT */ 3667*4882a593Smuzhiyun #define WM5100_IM_GP1_EINT_MASK 0x0001 /* IM_GP1_EINT */ 3668*4882a593Smuzhiyun #define WM5100_IM_GP1_EINT_SHIFT 0 /* IM_GP1_EINT */ 3669*4882a593Smuzhiyun #define WM5100_IM_GP1_EINT_WIDTH 1 /* IM_GP1_EINT */ 3670*4882a593Smuzhiyun 3671*4882a593Smuzhiyun /* 3672*4882a593Smuzhiyun * R3336 (0xD08) - Interrupt Status 2 Mask 3673*4882a593Smuzhiyun */ 3674*4882a593Smuzhiyun #define WM5100_IM_DSP_IRQ6_EINT 0x0020 /* IM_DSP_IRQ6_EINT */ 3675*4882a593Smuzhiyun #define WM5100_IM_DSP_IRQ6_EINT_MASK 0x0020 /* IM_DSP_IRQ6_EINT */ 3676*4882a593Smuzhiyun #define WM5100_IM_DSP_IRQ6_EINT_SHIFT 5 /* IM_DSP_IRQ6_EINT */ 3677*4882a593Smuzhiyun #define WM5100_IM_DSP_IRQ6_EINT_WIDTH 1 /* IM_DSP_IRQ6_EINT */ 3678*4882a593Smuzhiyun #define WM5100_IM_DSP_IRQ5_EINT 0x0010 /* IM_DSP_IRQ5_EINT */ 3679*4882a593Smuzhiyun #define WM5100_IM_DSP_IRQ5_EINT_MASK 0x0010 /* IM_DSP_IRQ5_EINT */ 3680*4882a593Smuzhiyun #define WM5100_IM_DSP_IRQ5_EINT_SHIFT 4 /* IM_DSP_IRQ5_EINT */ 3681*4882a593Smuzhiyun #define WM5100_IM_DSP_IRQ5_EINT_WIDTH 1 /* IM_DSP_IRQ5_EINT */ 3682*4882a593Smuzhiyun #define WM5100_IM_DSP_IRQ4_EINT 0x0008 /* IM_DSP_IRQ4_EINT */ 3683*4882a593Smuzhiyun #define WM5100_IM_DSP_IRQ4_EINT_MASK 0x0008 /* IM_DSP_IRQ4_EINT */ 3684*4882a593Smuzhiyun #define WM5100_IM_DSP_IRQ4_EINT_SHIFT 3 /* IM_DSP_IRQ4_EINT */ 3685*4882a593Smuzhiyun #define WM5100_IM_DSP_IRQ4_EINT_WIDTH 1 /* IM_DSP_IRQ4_EINT */ 3686*4882a593Smuzhiyun #define WM5100_IM_DSP_IRQ3_EINT 0x0004 /* IM_DSP_IRQ3_EINT */ 3687*4882a593Smuzhiyun #define WM5100_IM_DSP_IRQ3_EINT_MASK 0x0004 /* IM_DSP_IRQ3_EINT */ 3688*4882a593Smuzhiyun #define WM5100_IM_DSP_IRQ3_EINT_SHIFT 2 /* IM_DSP_IRQ3_EINT */ 3689*4882a593Smuzhiyun #define WM5100_IM_DSP_IRQ3_EINT_WIDTH 1 /* IM_DSP_IRQ3_EINT */ 3690*4882a593Smuzhiyun #define WM5100_IM_DSP_IRQ2_EINT 0x0002 /* IM_DSP_IRQ2_EINT */ 3691*4882a593Smuzhiyun #define WM5100_IM_DSP_IRQ2_EINT_MASK 0x0002 /* IM_DSP_IRQ2_EINT */ 3692*4882a593Smuzhiyun #define WM5100_IM_DSP_IRQ2_EINT_SHIFT 1 /* IM_DSP_IRQ2_EINT */ 3693*4882a593Smuzhiyun #define WM5100_IM_DSP_IRQ2_EINT_WIDTH 1 /* IM_DSP_IRQ2_EINT */ 3694*4882a593Smuzhiyun #define WM5100_IM_DSP_IRQ1_EINT 0x0001 /* IM_DSP_IRQ1_EINT */ 3695*4882a593Smuzhiyun #define WM5100_IM_DSP_IRQ1_EINT_MASK 0x0001 /* IM_DSP_IRQ1_EINT */ 3696*4882a593Smuzhiyun #define WM5100_IM_DSP_IRQ1_EINT_SHIFT 0 /* IM_DSP_IRQ1_EINT */ 3697*4882a593Smuzhiyun #define WM5100_IM_DSP_IRQ1_EINT_WIDTH 1 /* IM_DSP_IRQ1_EINT */ 3698*4882a593Smuzhiyun 3699*4882a593Smuzhiyun /* 3700*4882a593Smuzhiyun * R3337 (0xD09) - Interrupt Status 3 Mask 3701*4882a593Smuzhiyun */ 3702*4882a593Smuzhiyun #define WM5100_IM_SPK_SHUTDOWN_WARN_EINT 0x8000 /* IM_SPK_SHUTDOWN_WARN_EINT */ 3703*4882a593Smuzhiyun #define WM5100_IM_SPK_SHUTDOWN_WARN_EINT_MASK 0x8000 /* IM_SPK_SHUTDOWN_WARN_EINT */ 3704*4882a593Smuzhiyun #define WM5100_IM_SPK_SHUTDOWN_WARN_EINT_SHIFT 15 /* IM_SPK_SHUTDOWN_WARN_EINT */ 3705*4882a593Smuzhiyun #define WM5100_IM_SPK_SHUTDOWN_WARN_EINT_WIDTH 1 /* IM_SPK_SHUTDOWN_WARN_EINT */ 3706*4882a593Smuzhiyun #define WM5100_IM_SPK_SHUTDOWN_EINT 0x4000 /* IM_SPK_SHUTDOWN_EINT */ 3707*4882a593Smuzhiyun #define WM5100_IM_SPK_SHUTDOWN_EINT_MASK 0x4000 /* IM_SPK_SHUTDOWN_EINT */ 3708*4882a593Smuzhiyun #define WM5100_IM_SPK_SHUTDOWN_EINT_SHIFT 14 /* IM_SPK_SHUTDOWN_EINT */ 3709*4882a593Smuzhiyun #define WM5100_IM_SPK_SHUTDOWN_EINT_WIDTH 1 /* IM_SPK_SHUTDOWN_EINT */ 3710*4882a593Smuzhiyun #define WM5100_IM_HPDET_EINT 0x2000 /* IM_HPDET_EINT */ 3711*4882a593Smuzhiyun #define WM5100_IM_HPDET_EINT_MASK 0x2000 /* IM_HPDET_EINT */ 3712*4882a593Smuzhiyun #define WM5100_IM_HPDET_EINT_SHIFT 13 /* IM_HPDET_EINT */ 3713*4882a593Smuzhiyun #define WM5100_IM_HPDET_EINT_WIDTH 1 /* IM_HPDET_EINT */ 3714*4882a593Smuzhiyun #define WM5100_IM_ACCDET_EINT 0x1000 /* IM_ACCDET_EINT */ 3715*4882a593Smuzhiyun #define WM5100_IM_ACCDET_EINT_MASK 0x1000 /* IM_ACCDET_EINT */ 3716*4882a593Smuzhiyun #define WM5100_IM_ACCDET_EINT_SHIFT 12 /* IM_ACCDET_EINT */ 3717*4882a593Smuzhiyun #define WM5100_IM_ACCDET_EINT_WIDTH 1 /* IM_ACCDET_EINT */ 3718*4882a593Smuzhiyun #define WM5100_IM_DRC_SIG_DET_EINT 0x0200 /* IM_DRC_SIG_DET_EINT */ 3719*4882a593Smuzhiyun #define WM5100_IM_DRC_SIG_DET_EINT_MASK 0x0200 /* IM_DRC_SIG_DET_EINT */ 3720*4882a593Smuzhiyun #define WM5100_IM_DRC_SIG_DET_EINT_SHIFT 9 /* IM_DRC_SIG_DET_EINT */ 3721*4882a593Smuzhiyun #define WM5100_IM_DRC_SIG_DET_EINT_WIDTH 1 /* IM_DRC_SIG_DET_EINT */ 3722*4882a593Smuzhiyun #define WM5100_IM_ASRC2_LOCK_EINT 0x0100 /* IM_ASRC2_LOCK_EINT */ 3723*4882a593Smuzhiyun #define WM5100_IM_ASRC2_LOCK_EINT_MASK 0x0100 /* IM_ASRC2_LOCK_EINT */ 3724*4882a593Smuzhiyun #define WM5100_IM_ASRC2_LOCK_EINT_SHIFT 8 /* IM_ASRC2_LOCK_EINT */ 3725*4882a593Smuzhiyun #define WM5100_IM_ASRC2_LOCK_EINT_WIDTH 1 /* IM_ASRC2_LOCK_EINT */ 3726*4882a593Smuzhiyun #define WM5100_IM_ASRC1_LOCK_EINT 0x0080 /* IM_ASRC1_LOCK_EINT */ 3727*4882a593Smuzhiyun #define WM5100_IM_ASRC1_LOCK_EINT_MASK 0x0080 /* IM_ASRC1_LOCK_EINT */ 3728*4882a593Smuzhiyun #define WM5100_IM_ASRC1_LOCK_EINT_SHIFT 7 /* IM_ASRC1_LOCK_EINT */ 3729*4882a593Smuzhiyun #define WM5100_IM_ASRC1_LOCK_EINT_WIDTH 1 /* IM_ASRC1_LOCK_EINT */ 3730*4882a593Smuzhiyun #define WM5100_IM_FLL2_LOCK_EINT 0x0008 /* IM_FLL2_LOCK_EINT */ 3731*4882a593Smuzhiyun #define WM5100_IM_FLL2_LOCK_EINT_MASK 0x0008 /* IM_FLL2_LOCK_EINT */ 3732*4882a593Smuzhiyun #define WM5100_IM_FLL2_LOCK_EINT_SHIFT 3 /* IM_FLL2_LOCK_EINT */ 3733*4882a593Smuzhiyun #define WM5100_IM_FLL2_LOCK_EINT_WIDTH 1 /* IM_FLL2_LOCK_EINT */ 3734*4882a593Smuzhiyun #define WM5100_IM_FLL1_LOCK_EINT 0x0004 /* IM_FLL1_LOCK_EINT */ 3735*4882a593Smuzhiyun #define WM5100_IM_FLL1_LOCK_EINT_MASK 0x0004 /* IM_FLL1_LOCK_EINT */ 3736*4882a593Smuzhiyun #define WM5100_IM_FLL1_LOCK_EINT_SHIFT 2 /* IM_FLL1_LOCK_EINT */ 3737*4882a593Smuzhiyun #define WM5100_IM_FLL1_LOCK_EINT_WIDTH 1 /* IM_FLL1_LOCK_EINT */ 3738*4882a593Smuzhiyun #define WM5100_IM_CLKGEN_ERR_EINT 0x0002 /* IM_CLKGEN_ERR_EINT */ 3739*4882a593Smuzhiyun #define WM5100_IM_CLKGEN_ERR_EINT_MASK 0x0002 /* IM_CLKGEN_ERR_EINT */ 3740*4882a593Smuzhiyun #define WM5100_IM_CLKGEN_ERR_EINT_SHIFT 1 /* IM_CLKGEN_ERR_EINT */ 3741*4882a593Smuzhiyun #define WM5100_IM_CLKGEN_ERR_EINT_WIDTH 1 /* IM_CLKGEN_ERR_EINT */ 3742*4882a593Smuzhiyun #define WM5100_IM_CLKGEN_ERR_ASYNC_EINT 0x0001 /* IM_CLKGEN_ERR_ASYNC_EINT */ 3743*4882a593Smuzhiyun #define WM5100_IM_CLKGEN_ERR_ASYNC_EINT_MASK 0x0001 /* IM_CLKGEN_ERR_ASYNC_EINT */ 3744*4882a593Smuzhiyun #define WM5100_IM_CLKGEN_ERR_ASYNC_EINT_SHIFT 0 /* IM_CLKGEN_ERR_ASYNC_EINT */ 3745*4882a593Smuzhiyun #define WM5100_IM_CLKGEN_ERR_ASYNC_EINT_WIDTH 1 /* IM_CLKGEN_ERR_ASYNC_EINT */ 3746*4882a593Smuzhiyun 3747*4882a593Smuzhiyun /* 3748*4882a593Smuzhiyun * R3338 (0xD0A) - Interrupt Status 4 Mask 3749*4882a593Smuzhiyun */ 3750*4882a593Smuzhiyun #define WM5100_IM_AIF3_ERR_EINT 0x2000 /* IM_AIF3_ERR_EINT */ 3751*4882a593Smuzhiyun #define WM5100_IM_AIF3_ERR_EINT_MASK 0x2000 /* IM_AIF3_ERR_EINT */ 3752*4882a593Smuzhiyun #define WM5100_IM_AIF3_ERR_EINT_SHIFT 13 /* IM_AIF3_ERR_EINT */ 3753*4882a593Smuzhiyun #define WM5100_IM_AIF3_ERR_EINT_WIDTH 1 /* IM_AIF3_ERR_EINT */ 3754*4882a593Smuzhiyun #define WM5100_IM_AIF2_ERR_EINT 0x1000 /* IM_AIF2_ERR_EINT */ 3755*4882a593Smuzhiyun #define WM5100_IM_AIF2_ERR_EINT_MASK 0x1000 /* IM_AIF2_ERR_EINT */ 3756*4882a593Smuzhiyun #define WM5100_IM_AIF2_ERR_EINT_SHIFT 12 /* IM_AIF2_ERR_EINT */ 3757*4882a593Smuzhiyun #define WM5100_IM_AIF2_ERR_EINT_WIDTH 1 /* IM_AIF2_ERR_EINT */ 3758*4882a593Smuzhiyun #define WM5100_IM_AIF1_ERR_EINT 0x0800 /* IM_AIF1_ERR_EINT */ 3759*4882a593Smuzhiyun #define WM5100_IM_AIF1_ERR_EINT_MASK 0x0800 /* IM_AIF1_ERR_EINT */ 3760*4882a593Smuzhiyun #define WM5100_IM_AIF1_ERR_EINT_SHIFT 11 /* IM_AIF1_ERR_EINT */ 3761*4882a593Smuzhiyun #define WM5100_IM_AIF1_ERR_EINT_WIDTH 1 /* IM_AIF1_ERR_EINT */ 3762*4882a593Smuzhiyun #define WM5100_IM_CTRLIF_ERR_EINT 0x0400 /* IM_CTRLIF_ERR_EINT */ 3763*4882a593Smuzhiyun #define WM5100_IM_CTRLIF_ERR_EINT_MASK 0x0400 /* IM_CTRLIF_ERR_EINT */ 3764*4882a593Smuzhiyun #define WM5100_IM_CTRLIF_ERR_EINT_SHIFT 10 /* IM_CTRLIF_ERR_EINT */ 3765*4882a593Smuzhiyun #define WM5100_IM_CTRLIF_ERR_EINT_WIDTH 1 /* IM_CTRLIF_ERR_EINT */ 3766*4882a593Smuzhiyun #define WM5100_IM_ISRC2_UNDERCLOCKED_EINT 0x0200 /* IM_ISRC2_UNDERCLOCKED_EINT */ 3767*4882a593Smuzhiyun #define WM5100_IM_ISRC2_UNDERCLOCKED_EINT_MASK 0x0200 /* IM_ISRC2_UNDERCLOCKED_EINT */ 3768*4882a593Smuzhiyun #define WM5100_IM_ISRC2_UNDERCLOCKED_EINT_SHIFT 9 /* IM_ISRC2_UNDERCLOCKED_EINT */ 3769*4882a593Smuzhiyun #define WM5100_IM_ISRC2_UNDERCLOCKED_EINT_WIDTH 1 /* IM_ISRC2_UNDERCLOCKED_EINT */ 3770*4882a593Smuzhiyun #define WM5100_IM_ISRC1_UNDERCLOCKED_EINT 0x0100 /* IM_ISRC1_UNDERCLOCKED_EINT */ 3771*4882a593Smuzhiyun #define WM5100_IM_ISRC1_UNDERCLOCKED_EINT_MASK 0x0100 /* IM_ISRC1_UNDERCLOCKED_EINT */ 3772*4882a593Smuzhiyun #define WM5100_IM_ISRC1_UNDERCLOCKED_EINT_SHIFT 8 /* IM_ISRC1_UNDERCLOCKED_EINT */ 3773*4882a593Smuzhiyun #define WM5100_IM_ISRC1_UNDERCLOCKED_EINT_WIDTH 1 /* IM_ISRC1_UNDERCLOCKED_EINT */ 3774*4882a593Smuzhiyun #define WM5100_IM_FX_UNDERCLOCKED_EINT 0x0080 /* IM_FX_UNDERCLOCKED_EINT */ 3775*4882a593Smuzhiyun #define WM5100_IM_FX_UNDERCLOCKED_EINT_MASK 0x0080 /* IM_FX_UNDERCLOCKED_EINT */ 3776*4882a593Smuzhiyun #define WM5100_IM_FX_UNDERCLOCKED_EINT_SHIFT 7 /* IM_FX_UNDERCLOCKED_EINT */ 3777*4882a593Smuzhiyun #define WM5100_IM_FX_UNDERCLOCKED_EINT_WIDTH 1 /* IM_FX_UNDERCLOCKED_EINT */ 3778*4882a593Smuzhiyun #define WM5100_IM_AIF3_UNDERCLOCKED_EINT 0x0040 /* IM_AIF3_UNDERCLOCKED_EINT */ 3779*4882a593Smuzhiyun #define WM5100_IM_AIF3_UNDERCLOCKED_EINT_MASK 0x0040 /* IM_AIF3_UNDERCLOCKED_EINT */ 3780*4882a593Smuzhiyun #define WM5100_IM_AIF3_UNDERCLOCKED_EINT_SHIFT 6 /* IM_AIF3_UNDERCLOCKED_EINT */ 3781*4882a593Smuzhiyun #define WM5100_IM_AIF3_UNDERCLOCKED_EINT_WIDTH 1 /* IM_AIF3_UNDERCLOCKED_EINT */ 3782*4882a593Smuzhiyun #define WM5100_IM_AIF2_UNDERCLOCKED_EINT 0x0020 /* IM_AIF2_UNDERCLOCKED_EINT */ 3783*4882a593Smuzhiyun #define WM5100_IM_AIF2_UNDERCLOCKED_EINT_MASK 0x0020 /* IM_AIF2_UNDERCLOCKED_EINT */ 3784*4882a593Smuzhiyun #define WM5100_IM_AIF2_UNDERCLOCKED_EINT_SHIFT 5 /* IM_AIF2_UNDERCLOCKED_EINT */ 3785*4882a593Smuzhiyun #define WM5100_IM_AIF2_UNDERCLOCKED_EINT_WIDTH 1 /* IM_AIF2_UNDERCLOCKED_EINT */ 3786*4882a593Smuzhiyun #define WM5100_IM_AIF1_UNDERCLOCKED_EINT 0x0010 /* IM_AIF1_UNDERCLOCKED_EINT */ 3787*4882a593Smuzhiyun #define WM5100_IM_AIF1_UNDERCLOCKED_EINT_MASK 0x0010 /* IM_AIF1_UNDERCLOCKED_EINT */ 3788*4882a593Smuzhiyun #define WM5100_IM_AIF1_UNDERCLOCKED_EINT_SHIFT 4 /* IM_AIF1_UNDERCLOCKED_EINT */ 3789*4882a593Smuzhiyun #define WM5100_IM_AIF1_UNDERCLOCKED_EINT_WIDTH 1 /* IM_AIF1_UNDERCLOCKED_EINT */ 3790*4882a593Smuzhiyun #define WM5100_IM_ASRC_UNDERCLOCKED_EINT 0x0008 /* IM_ASRC_UNDERCLOCKED_EINT */ 3791*4882a593Smuzhiyun #define WM5100_IM_ASRC_UNDERCLOCKED_EINT_MASK 0x0008 /* IM_ASRC_UNDERCLOCKED_EINT */ 3792*4882a593Smuzhiyun #define WM5100_IM_ASRC_UNDERCLOCKED_EINT_SHIFT 3 /* IM_ASRC_UNDERCLOCKED_EINT */ 3793*4882a593Smuzhiyun #define WM5100_IM_ASRC_UNDERCLOCKED_EINT_WIDTH 1 /* IM_ASRC_UNDERCLOCKED_EINT */ 3794*4882a593Smuzhiyun #define WM5100_IM_DAC_UNDERCLOCKED_EINT 0x0004 /* IM_DAC_UNDERCLOCKED_EINT */ 3795*4882a593Smuzhiyun #define WM5100_IM_DAC_UNDERCLOCKED_EINT_MASK 0x0004 /* IM_DAC_UNDERCLOCKED_EINT */ 3796*4882a593Smuzhiyun #define WM5100_IM_DAC_UNDERCLOCKED_EINT_SHIFT 2 /* IM_DAC_UNDERCLOCKED_EINT */ 3797*4882a593Smuzhiyun #define WM5100_IM_DAC_UNDERCLOCKED_EINT_WIDTH 1 /* IM_DAC_UNDERCLOCKED_EINT */ 3798*4882a593Smuzhiyun #define WM5100_IM_ADC_UNDERCLOCKED_EINT 0x0002 /* IM_ADC_UNDERCLOCKED_EINT */ 3799*4882a593Smuzhiyun #define WM5100_IM_ADC_UNDERCLOCKED_EINT_MASK 0x0002 /* IM_ADC_UNDERCLOCKED_EINT */ 3800*4882a593Smuzhiyun #define WM5100_IM_ADC_UNDERCLOCKED_EINT_SHIFT 1 /* IM_ADC_UNDERCLOCKED_EINT */ 3801*4882a593Smuzhiyun #define WM5100_IM_ADC_UNDERCLOCKED_EINT_WIDTH 1 /* IM_ADC_UNDERCLOCKED_EINT */ 3802*4882a593Smuzhiyun #define WM5100_IM_MIXER_UNDERCLOCKED_EINT 0x0001 /* IM_MIXER_UNDERCLOCKED_EINT */ 3803*4882a593Smuzhiyun #define WM5100_IM_MIXER_UNDERCLOCKED_EINT_MASK 0x0001 /* IM_MIXER_UNDERCLOCKED_EINT */ 3804*4882a593Smuzhiyun #define WM5100_IM_MIXER_UNDERCLOCKED_EINT_SHIFT 0 /* IM_MIXER_UNDERCLOCKED_EINT */ 3805*4882a593Smuzhiyun #define WM5100_IM_MIXER_UNDERCLOCKED_EINT_WIDTH 1 /* IM_MIXER_UNDERCLOCKED_EINT */ 3806*4882a593Smuzhiyun 3807*4882a593Smuzhiyun /* 3808*4882a593Smuzhiyun * R3359 (0xD1F) - Interrupt Control 3809*4882a593Smuzhiyun */ 3810*4882a593Smuzhiyun #define WM5100_IM_IRQ 0x0001 /* IM_IRQ */ 3811*4882a593Smuzhiyun #define WM5100_IM_IRQ_MASK 0x0001 /* IM_IRQ */ 3812*4882a593Smuzhiyun #define WM5100_IM_IRQ_SHIFT 0 /* IM_IRQ */ 3813*4882a593Smuzhiyun #define WM5100_IM_IRQ_WIDTH 1 /* IM_IRQ */ 3814*4882a593Smuzhiyun 3815*4882a593Smuzhiyun /* 3816*4882a593Smuzhiyun * R3360 (0xD20) - IRQ Debounce 1 3817*4882a593Smuzhiyun */ 3818*4882a593Smuzhiyun #define WM5100_SPK_SHUTDOWN_WARN_DB 0x0200 /* SPK_SHUTDOWN_WARN_DB */ 3819*4882a593Smuzhiyun #define WM5100_SPK_SHUTDOWN_WARN_DB_MASK 0x0200 /* SPK_SHUTDOWN_WARN_DB */ 3820*4882a593Smuzhiyun #define WM5100_SPK_SHUTDOWN_WARN_DB_SHIFT 9 /* SPK_SHUTDOWN_WARN_DB */ 3821*4882a593Smuzhiyun #define WM5100_SPK_SHUTDOWN_WARN_DB_WIDTH 1 /* SPK_SHUTDOWN_WARN_DB */ 3822*4882a593Smuzhiyun #define WM5100_SPK_SHUTDOWN_DB 0x0100 /* SPK_SHUTDOWN_DB */ 3823*4882a593Smuzhiyun #define WM5100_SPK_SHUTDOWN_DB_MASK 0x0100 /* SPK_SHUTDOWN_DB */ 3824*4882a593Smuzhiyun #define WM5100_SPK_SHUTDOWN_DB_SHIFT 8 /* SPK_SHUTDOWN_DB */ 3825*4882a593Smuzhiyun #define WM5100_SPK_SHUTDOWN_DB_WIDTH 1 /* SPK_SHUTDOWN_DB */ 3826*4882a593Smuzhiyun #define WM5100_FLL1_LOCK_IRQ_DB 0x0008 /* FLL1_LOCK_IRQ_DB */ 3827*4882a593Smuzhiyun #define WM5100_FLL1_LOCK_IRQ_DB_MASK 0x0008 /* FLL1_LOCK_IRQ_DB */ 3828*4882a593Smuzhiyun #define WM5100_FLL1_LOCK_IRQ_DB_SHIFT 3 /* FLL1_LOCK_IRQ_DB */ 3829*4882a593Smuzhiyun #define WM5100_FLL1_LOCK_IRQ_DB_WIDTH 1 /* FLL1_LOCK_IRQ_DB */ 3830*4882a593Smuzhiyun #define WM5100_FLL2_LOCK_IRQ_DB 0x0004 /* FLL2_LOCK_IRQ_DB */ 3831*4882a593Smuzhiyun #define WM5100_FLL2_LOCK_IRQ_DB_MASK 0x0004 /* FLL2_LOCK_IRQ_DB */ 3832*4882a593Smuzhiyun #define WM5100_FLL2_LOCK_IRQ_DB_SHIFT 2 /* FLL2_LOCK_IRQ_DB */ 3833*4882a593Smuzhiyun #define WM5100_FLL2_LOCK_IRQ_DB_WIDTH 1 /* FLL2_LOCK_IRQ_DB */ 3834*4882a593Smuzhiyun #define WM5100_CLKGEN_ERR_IRQ_DB 0x0002 /* CLKGEN_ERR_IRQ_DB */ 3835*4882a593Smuzhiyun #define WM5100_CLKGEN_ERR_IRQ_DB_MASK 0x0002 /* CLKGEN_ERR_IRQ_DB */ 3836*4882a593Smuzhiyun #define WM5100_CLKGEN_ERR_IRQ_DB_SHIFT 1 /* CLKGEN_ERR_IRQ_DB */ 3837*4882a593Smuzhiyun #define WM5100_CLKGEN_ERR_IRQ_DB_WIDTH 1 /* CLKGEN_ERR_IRQ_DB */ 3838*4882a593Smuzhiyun #define WM5100_CLKGEN_ERR_ASYNC_IRQ_DB 0x0001 /* CLKGEN_ERR_ASYNC_IRQ_DB */ 3839*4882a593Smuzhiyun #define WM5100_CLKGEN_ERR_ASYNC_IRQ_DB_MASK 0x0001 /* CLKGEN_ERR_ASYNC_IRQ_DB */ 3840*4882a593Smuzhiyun #define WM5100_CLKGEN_ERR_ASYNC_IRQ_DB_SHIFT 0 /* CLKGEN_ERR_ASYNC_IRQ_DB */ 3841*4882a593Smuzhiyun #define WM5100_CLKGEN_ERR_ASYNC_IRQ_DB_WIDTH 1 /* CLKGEN_ERR_ASYNC_IRQ_DB */ 3842*4882a593Smuzhiyun 3843*4882a593Smuzhiyun /* 3844*4882a593Smuzhiyun * R3361 (0xD21) - IRQ Debounce 2 3845*4882a593Smuzhiyun */ 3846*4882a593Smuzhiyun #define WM5100_AIF_ERR_DB 0x0001 /* AIF_ERR_DB */ 3847*4882a593Smuzhiyun #define WM5100_AIF_ERR_DB_MASK 0x0001 /* AIF_ERR_DB */ 3848*4882a593Smuzhiyun #define WM5100_AIF_ERR_DB_SHIFT 0 /* AIF_ERR_DB */ 3849*4882a593Smuzhiyun #define WM5100_AIF_ERR_DB_WIDTH 1 /* AIF_ERR_DB */ 3850*4882a593Smuzhiyun 3851*4882a593Smuzhiyun /* 3852*4882a593Smuzhiyun * R3584 (0xE00) - FX_Ctrl 3853*4882a593Smuzhiyun */ 3854*4882a593Smuzhiyun #define WM5100_FX_STS_MASK 0xFFC0 /* FX_STS - [15:6] */ 3855*4882a593Smuzhiyun #define WM5100_FX_STS_SHIFT 6 /* FX_STS - [15:6] */ 3856*4882a593Smuzhiyun #define WM5100_FX_STS_WIDTH 10 /* FX_STS - [15:6] */ 3857*4882a593Smuzhiyun #define WM5100_FX_RATE_MASK 0x0003 /* FX_RATE - [1:0] */ 3858*4882a593Smuzhiyun #define WM5100_FX_RATE_SHIFT 0 /* FX_RATE - [1:0] */ 3859*4882a593Smuzhiyun #define WM5100_FX_RATE_WIDTH 2 /* FX_RATE - [1:0] */ 3860*4882a593Smuzhiyun 3861*4882a593Smuzhiyun /* 3862*4882a593Smuzhiyun * R3600 (0xE10) - EQ1_1 3863*4882a593Smuzhiyun */ 3864*4882a593Smuzhiyun #define WM5100_EQ1_B1_GAIN_MASK 0xF800 /* EQ1_B1_GAIN - [15:11] */ 3865*4882a593Smuzhiyun #define WM5100_EQ1_B1_GAIN_SHIFT 11 /* EQ1_B1_GAIN - [15:11] */ 3866*4882a593Smuzhiyun #define WM5100_EQ1_B1_GAIN_WIDTH 5 /* EQ1_B1_GAIN - [15:11] */ 3867*4882a593Smuzhiyun #define WM5100_EQ1_B2_GAIN_MASK 0x07C0 /* EQ1_B2_GAIN - [10:6] */ 3868*4882a593Smuzhiyun #define WM5100_EQ1_B2_GAIN_SHIFT 6 /* EQ1_B2_GAIN - [10:6] */ 3869*4882a593Smuzhiyun #define WM5100_EQ1_B2_GAIN_WIDTH 5 /* EQ1_B2_GAIN - [10:6] */ 3870*4882a593Smuzhiyun #define WM5100_EQ1_B3_GAIN_MASK 0x003E /* EQ1_B3_GAIN - [5:1] */ 3871*4882a593Smuzhiyun #define WM5100_EQ1_B3_GAIN_SHIFT 1 /* EQ1_B3_GAIN - [5:1] */ 3872*4882a593Smuzhiyun #define WM5100_EQ1_B3_GAIN_WIDTH 5 /* EQ1_B3_GAIN - [5:1] */ 3873*4882a593Smuzhiyun #define WM5100_EQ1_ENA 0x0001 /* EQ1_ENA */ 3874*4882a593Smuzhiyun #define WM5100_EQ1_ENA_MASK 0x0001 /* EQ1_ENA */ 3875*4882a593Smuzhiyun #define WM5100_EQ1_ENA_SHIFT 0 /* EQ1_ENA */ 3876*4882a593Smuzhiyun #define WM5100_EQ1_ENA_WIDTH 1 /* EQ1_ENA */ 3877*4882a593Smuzhiyun 3878*4882a593Smuzhiyun /* 3879*4882a593Smuzhiyun * R3601 (0xE11) - EQ1_2 3880*4882a593Smuzhiyun */ 3881*4882a593Smuzhiyun #define WM5100_EQ1_B4_GAIN_MASK 0xF800 /* EQ1_B4_GAIN - [15:11] */ 3882*4882a593Smuzhiyun #define WM5100_EQ1_B4_GAIN_SHIFT 11 /* EQ1_B4_GAIN - [15:11] */ 3883*4882a593Smuzhiyun #define WM5100_EQ1_B4_GAIN_WIDTH 5 /* EQ1_B4_GAIN - [15:11] */ 3884*4882a593Smuzhiyun #define WM5100_EQ1_B5_GAIN_MASK 0x07C0 /* EQ1_B5_GAIN - [10:6] */ 3885*4882a593Smuzhiyun #define WM5100_EQ1_B5_GAIN_SHIFT 6 /* EQ1_B5_GAIN - [10:6] */ 3886*4882a593Smuzhiyun #define WM5100_EQ1_B5_GAIN_WIDTH 5 /* EQ1_B5_GAIN - [10:6] */ 3887*4882a593Smuzhiyun 3888*4882a593Smuzhiyun /* 3889*4882a593Smuzhiyun * R3602 (0xE12) - EQ1_3 3890*4882a593Smuzhiyun */ 3891*4882a593Smuzhiyun #define WM5100_EQ1_B1_A_MASK 0xFFFF /* EQ1_B1_A - [15:0] */ 3892*4882a593Smuzhiyun #define WM5100_EQ1_B1_A_SHIFT 0 /* EQ1_B1_A - [15:0] */ 3893*4882a593Smuzhiyun #define WM5100_EQ1_B1_A_WIDTH 16 /* EQ1_B1_A - [15:0] */ 3894*4882a593Smuzhiyun 3895*4882a593Smuzhiyun /* 3896*4882a593Smuzhiyun * R3603 (0xE13) - EQ1_4 3897*4882a593Smuzhiyun */ 3898*4882a593Smuzhiyun #define WM5100_EQ1_B1_B_MASK 0xFFFF /* EQ1_B1_B - [15:0] */ 3899*4882a593Smuzhiyun #define WM5100_EQ1_B1_B_SHIFT 0 /* EQ1_B1_B - [15:0] */ 3900*4882a593Smuzhiyun #define WM5100_EQ1_B1_B_WIDTH 16 /* EQ1_B1_B - [15:0] */ 3901*4882a593Smuzhiyun 3902*4882a593Smuzhiyun /* 3903*4882a593Smuzhiyun * R3604 (0xE14) - EQ1_5 3904*4882a593Smuzhiyun */ 3905*4882a593Smuzhiyun #define WM5100_EQ1_B1_PG_MASK 0xFFFF /* EQ1_B1_PG - [15:0] */ 3906*4882a593Smuzhiyun #define WM5100_EQ1_B1_PG_SHIFT 0 /* EQ1_B1_PG - [15:0] */ 3907*4882a593Smuzhiyun #define WM5100_EQ1_B1_PG_WIDTH 16 /* EQ1_B1_PG - [15:0] */ 3908*4882a593Smuzhiyun 3909*4882a593Smuzhiyun /* 3910*4882a593Smuzhiyun * R3605 (0xE15) - EQ1_6 3911*4882a593Smuzhiyun */ 3912*4882a593Smuzhiyun #define WM5100_EQ1_B2_A_MASK 0xFFFF /* EQ1_B2_A - [15:0] */ 3913*4882a593Smuzhiyun #define WM5100_EQ1_B2_A_SHIFT 0 /* EQ1_B2_A - [15:0] */ 3914*4882a593Smuzhiyun #define WM5100_EQ1_B2_A_WIDTH 16 /* EQ1_B2_A - [15:0] */ 3915*4882a593Smuzhiyun 3916*4882a593Smuzhiyun /* 3917*4882a593Smuzhiyun * R3606 (0xE16) - EQ1_7 3918*4882a593Smuzhiyun */ 3919*4882a593Smuzhiyun #define WM5100_EQ1_B2_B_MASK 0xFFFF /* EQ1_B2_B - [15:0] */ 3920*4882a593Smuzhiyun #define WM5100_EQ1_B2_B_SHIFT 0 /* EQ1_B2_B - [15:0] */ 3921*4882a593Smuzhiyun #define WM5100_EQ1_B2_B_WIDTH 16 /* EQ1_B2_B - [15:0] */ 3922*4882a593Smuzhiyun 3923*4882a593Smuzhiyun /* 3924*4882a593Smuzhiyun * R3607 (0xE17) - EQ1_8 3925*4882a593Smuzhiyun */ 3926*4882a593Smuzhiyun #define WM5100_EQ1_B2_C_MASK 0xFFFF /* EQ1_B2_C - [15:0] */ 3927*4882a593Smuzhiyun #define WM5100_EQ1_B2_C_SHIFT 0 /* EQ1_B2_C - [15:0] */ 3928*4882a593Smuzhiyun #define WM5100_EQ1_B2_C_WIDTH 16 /* EQ1_B2_C - [15:0] */ 3929*4882a593Smuzhiyun 3930*4882a593Smuzhiyun /* 3931*4882a593Smuzhiyun * R3608 (0xE18) - EQ1_9 3932*4882a593Smuzhiyun */ 3933*4882a593Smuzhiyun #define WM5100_EQ1_B2_PG_MASK 0xFFFF /* EQ1_B2_PG - [15:0] */ 3934*4882a593Smuzhiyun #define WM5100_EQ1_B2_PG_SHIFT 0 /* EQ1_B2_PG - [15:0] */ 3935*4882a593Smuzhiyun #define WM5100_EQ1_B2_PG_WIDTH 16 /* EQ1_B2_PG - [15:0] */ 3936*4882a593Smuzhiyun 3937*4882a593Smuzhiyun /* 3938*4882a593Smuzhiyun * R3609 (0xE19) - EQ1_10 3939*4882a593Smuzhiyun */ 3940*4882a593Smuzhiyun #define WM5100_EQ1_B3_A_MASK 0xFFFF /* EQ1_B3_A - [15:0] */ 3941*4882a593Smuzhiyun #define WM5100_EQ1_B3_A_SHIFT 0 /* EQ1_B3_A - [15:0] */ 3942*4882a593Smuzhiyun #define WM5100_EQ1_B3_A_WIDTH 16 /* EQ1_B3_A - [15:0] */ 3943*4882a593Smuzhiyun 3944*4882a593Smuzhiyun /* 3945*4882a593Smuzhiyun * R3610 (0xE1A) - EQ1_11 3946*4882a593Smuzhiyun */ 3947*4882a593Smuzhiyun #define WM5100_EQ1_B3_B_MASK 0xFFFF /* EQ1_B3_B - [15:0] */ 3948*4882a593Smuzhiyun #define WM5100_EQ1_B3_B_SHIFT 0 /* EQ1_B3_B - [15:0] */ 3949*4882a593Smuzhiyun #define WM5100_EQ1_B3_B_WIDTH 16 /* EQ1_B3_B - [15:0] */ 3950*4882a593Smuzhiyun 3951*4882a593Smuzhiyun /* 3952*4882a593Smuzhiyun * R3611 (0xE1B) - EQ1_12 3953*4882a593Smuzhiyun */ 3954*4882a593Smuzhiyun #define WM5100_EQ1_B3_C_MASK 0xFFFF /* EQ1_B3_C - [15:0] */ 3955*4882a593Smuzhiyun #define WM5100_EQ1_B3_C_SHIFT 0 /* EQ1_B3_C - [15:0] */ 3956*4882a593Smuzhiyun #define WM5100_EQ1_B3_C_WIDTH 16 /* EQ1_B3_C - [15:0] */ 3957*4882a593Smuzhiyun 3958*4882a593Smuzhiyun /* 3959*4882a593Smuzhiyun * R3612 (0xE1C) - EQ1_13 3960*4882a593Smuzhiyun */ 3961*4882a593Smuzhiyun #define WM5100_EQ1_B3_PG_MASK 0xFFFF /* EQ1_B3_PG - [15:0] */ 3962*4882a593Smuzhiyun #define WM5100_EQ1_B3_PG_SHIFT 0 /* EQ1_B3_PG - [15:0] */ 3963*4882a593Smuzhiyun #define WM5100_EQ1_B3_PG_WIDTH 16 /* EQ1_B3_PG - [15:0] */ 3964*4882a593Smuzhiyun 3965*4882a593Smuzhiyun /* 3966*4882a593Smuzhiyun * R3613 (0xE1D) - EQ1_14 3967*4882a593Smuzhiyun */ 3968*4882a593Smuzhiyun #define WM5100_EQ1_B4_A_MASK 0xFFFF /* EQ1_B4_A - [15:0] */ 3969*4882a593Smuzhiyun #define WM5100_EQ1_B4_A_SHIFT 0 /* EQ1_B4_A - [15:0] */ 3970*4882a593Smuzhiyun #define WM5100_EQ1_B4_A_WIDTH 16 /* EQ1_B4_A - [15:0] */ 3971*4882a593Smuzhiyun 3972*4882a593Smuzhiyun /* 3973*4882a593Smuzhiyun * R3614 (0xE1E) - EQ1_15 3974*4882a593Smuzhiyun */ 3975*4882a593Smuzhiyun #define WM5100_EQ1_B4_B_MASK 0xFFFF /* EQ1_B4_B - [15:0] */ 3976*4882a593Smuzhiyun #define WM5100_EQ1_B4_B_SHIFT 0 /* EQ1_B4_B - [15:0] */ 3977*4882a593Smuzhiyun #define WM5100_EQ1_B4_B_WIDTH 16 /* EQ1_B4_B - [15:0] */ 3978*4882a593Smuzhiyun 3979*4882a593Smuzhiyun /* 3980*4882a593Smuzhiyun * R3615 (0xE1F) - EQ1_16 3981*4882a593Smuzhiyun */ 3982*4882a593Smuzhiyun #define WM5100_EQ1_B4_C_MASK 0xFFFF /* EQ1_B4_C - [15:0] */ 3983*4882a593Smuzhiyun #define WM5100_EQ1_B4_C_SHIFT 0 /* EQ1_B4_C - [15:0] */ 3984*4882a593Smuzhiyun #define WM5100_EQ1_B4_C_WIDTH 16 /* EQ1_B4_C - [15:0] */ 3985*4882a593Smuzhiyun 3986*4882a593Smuzhiyun /* 3987*4882a593Smuzhiyun * R3616 (0xE20) - EQ1_17 3988*4882a593Smuzhiyun */ 3989*4882a593Smuzhiyun #define WM5100_EQ1_B4_PG_MASK 0xFFFF /* EQ1_B4_PG - [15:0] */ 3990*4882a593Smuzhiyun #define WM5100_EQ1_B4_PG_SHIFT 0 /* EQ1_B4_PG - [15:0] */ 3991*4882a593Smuzhiyun #define WM5100_EQ1_B4_PG_WIDTH 16 /* EQ1_B4_PG - [15:0] */ 3992*4882a593Smuzhiyun 3993*4882a593Smuzhiyun /* 3994*4882a593Smuzhiyun * R3617 (0xE21) - EQ1_18 3995*4882a593Smuzhiyun */ 3996*4882a593Smuzhiyun #define WM5100_EQ1_B5_A_MASK 0xFFFF /* EQ1_B5_A - [15:0] */ 3997*4882a593Smuzhiyun #define WM5100_EQ1_B5_A_SHIFT 0 /* EQ1_B5_A - [15:0] */ 3998*4882a593Smuzhiyun #define WM5100_EQ1_B5_A_WIDTH 16 /* EQ1_B5_A - [15:0] */ 3999*4882a593Smuzhiyun 4000*4882a593Smuzhiyun /* 4001*4882a593Smuzhiyun * R3618 (0xE22) - EQ1_19 4002*4882a593Smuzhiyun */ 4003*4882a593Smuzhiyun #define WM5100_EQ1_B5_B_MASK 0xFFFF /* EQ1_B5_B - [15:0] */ 4004*4882a593Smuzhiyun #define WM5100_EQ1_B5_B_SHIFT 0 /* EQ1_B5_B - [15:0] */ 4005*4882a593Smuzhiyun #define WM5100_EQ1_B5_B_WIDTH 16 /* EQ1_B5_B - [15:0] */ 4006*4882a593Smuzhiyun 4007*4882a593Smuzhiyun /* 4008*4882a593Smuzhiyun * R3619 (0xE23) - EQ1_20 4009*4882a593Smuzhiyun */ 4010*4882a593Smuzhiyun #define WM5100_EQ1_B5_PG_MASK 0xFFFF /* EQ1_B5_PG - [15:0] */ 4011*4882a593Smuzhiyun #define WM5100_EQ1_B5_PG_SHIFT 0 /* EQ1_B5_PG - [15:0] */ 4012*4882a593Smuzhiyun #define WM5100_EQ1_B5_PG_WIDTH 16 /* EQ1_B5_PG - [15:0] */ 4013*4882a593Smuzhiyun 4014*4882a593Smuzhiyun /* 4015*4882a593Smuzhiyun * R3622 (0xE26) - EQ2_1 4016*4882a593Smuzhiyun */ 4017*4882a593Smuzhiyun #define WM5100_EQ2_B1_GAIN_MASK 0xF800 /* EQ2_B1_GAIN - [15:11] */ 4018*4882a593Smuzhiyun #define WM5100_EQ2_B1_GAIN_SHIFT 11 /* EQ2_B1_GAIN - [15:11] */ 4019*4882a593Smuzhiyun #define WM5100_EQ2_B1_GAIN_WIDTH 5 /* EQ2_B1_GAIN - [15:11] */ 4020*4882a593Smuzhiyun #define WM5100_EQ2_B2_GAIN_MASK 0x07C0 /* EQ2_B2_GAIN - [10:6] */ 4021*4882a593Smuzhiyun #define WM5100_EQ2_B2_GAIN_SHIFT 6 /* EQ2_B2_GAIN - [10:6] */ 4022*4882a593Smuzhiyun #define WM5100_EQ2_B2_GAIN_WIDTH 5 /* EQ2_B2_GAIN - [10:6] */ 4023*4882a593Smuzhiyun #define WM5100_EQ2_B3_GAIN_MASK 0x003E /* EQ2_B3_GAIN - [5:1] */ 4024*4882a593Smuzhiyun #define WM5100_EQ2_B3_GAIN_SHIFT 1 /* EQ2_B3_GAIN - [5:1] */ 4025*4882a593Smuzhiyun #define WM5100_EQ2_B3_GAIN_WIDTH 5 /* EQ2_B3_GAIN - [5:1] */ 4026*4882a593Smuzhiyun #define WM5100_EQ2_ENA 0x0001 /* EQ2_ENA */ 4027*4882a593Smuzhiyun #define WM5100_EQ2_ENA_MASK 0x0001 /* EQ2_ENA */ 4028*4882a593Smuzhiyun #define WM5100_EQ2_ENA_SHIFT 0 /* EQ2_ENA */ 4029*4882a593Smuzhiyun #define WM5100_EQ2_ENA_WIDTH 1 /* EQ2_ENA */ 4030*4882a593Smuzhiyun 4031*4882a593Smuzhiyun /* 4032*4882a593Smuzhiyun * R3623 (0xE27) - EQ2_2 4033*4882a593Smuzhiyun */ 4034*4882a593Smuzhiyun #define WM5100_EQ2_B4_GAIN_MASK 0xF800 /* EQ2_B4_GAIN - [15:11] */ 4035*4882a593Smuzhiyun #define WM5100_EQ2_B4_GAIN_SHIFT 11 /* EQ2_B4_GAIN - [15:11] */ 4036*4882a593Smuzhiyun #define WM5100_EQ2_B4_GAIN_WIDTH 5 /* EQ2_B4_GAIN - [15:11] */ 4037*4882a593Smuzhiyun #define WM5100_EQ2_B5_GAIN_MASK 0x07C0 /* EQ2_B5_GAIN - [10:6] */ 4038*4882a593Smuzhiyun #define WM5100_EQ2_B5_GAIN_SHIFT 6 /* EQ2_B5_GAIN - [10:6] */ 4039*4882a593Smuzhiyun #define WM5100_EQ2_B5_GAIN_WIDTH 5 /* EQ2_B5_GAIN - [10:6] */ 4040*4882a593Smuzhiyun 4041*4882a593Smuzhiyun /* 4042*4882a593Smuzhiyun * R3624 (0xE28) - EQ2_3 4043*4882a593Smuzhiyun */ 4044*4882a593Smuzhiyun #define WM5100_EQ2_B1_A_MASK 0xFFFF /* EQ2_B1_A - [15:0] */ 4045*4882a593Smuzhiyun #define WM5100_EQ2_B1_A_SHIFT 0 /* EQ2_B1_A - [15:0] */ 4046*4882a593Smuzhiyun #define WM5100_EQ2_B1_A_WIDTH 16 /* EQ2_B1_A - [15:0] */ 4047*4882a593Smuzhiyun 4048*4882a593Smuzhiyun /* 4049*4882a593Smuzhiyun * R3625 (0xE29) - EQ2_4 4050*4882a593Smuzhiyun */ 4051*4882a593Smuzhiyun #define WM5100_EQ2_B1_B_MASK 0xFFFF /* EQ2_B1_B - [15:0] */ 4052*4882a593Smuzhiyun #define WM5100_EQ2_B1_B_SHIFT 0 /* EQ2_B1_B - [15:0] */ 4053*4882a593Smuzhiyun #define WM5100_EQ2_B1_B_WIDTH 16 /* EQ2_B1_B - [15:0] */ 4054*4882a593Smuzhiyun 4055*4882a593Smuzhiyun /* 4056*4882a593Smuzhiyun * R3626 (0xE2A) - EQ2_5 4057*4882a593Smuzhiyun */ 4058*4882a593Smuzhiyun #define WM5100_EQ2_B1_PG_MASK 0xFFFF /* EQ2_B1_PG - [15:0] */ 4059*4882a593Smuzhiyun #define WM5100_EQ2_B1_PG_SHIFT 0 /* EQ2_B1_PG - [15:0] */ 4060*4882a593Smuzhiyun #define WM5100_EQ2_B1_PG_WIDTH 16 /* EQ2_B1_PG - [15:0] */ 4061*4882a593Smuzhiyun 4062*4882a593Smuzhiyun /* 4063*4882a593Smuzhiyun * R3627 (0xE2B) - EQ2_6 4064*4882a593Smuzhiyun */ 4065*4882a593Smuzhiyun #define WM5100_EQ2_B2_A_MASK 0xFFFF /* EQ2_B2_A - [15:0] */ 4066*4882a593Smuzhiyun #define WM5100_EQ2_B2_A_SHIFT 0 /* EQ2_B2_A - [15:0] */ 4067*4882a593Smuzhiyun #define WM5100_EQ2_B2_A_WIDTH 16 /* EQ2_B2_A - [15:0] */ 4068*4882a593Smuzhiyun 4069*4882a593Smuzhiyun /* 4070*4882a593Smuzhiyun * R3628 (0xE2C) - EQ2_7 4071*4882a593Smuzhiyun */ 4072*4882a593Smuzhiyun #define WM5100_EQ2_B2_B_MASK 0xFFFF /* EQ2_B2_B - [15:0] */ 4073*4882a593Smuzhiyun #define WM5100_EQ2_B2_B_SHIFT 0 /* EQ2_B2_B - [15:0] */ 4074*4882a593Smuzhiyun #define WM5100_EQ2_B2_B_WIDTH 16 /* EQ2_B2_B - [15:0] */ 4075*4882a593Smuzhiyun 4076*4882a593Smuzhiyun /* 4077*4882a593Smuzhiyun * R3629 (0xE2D) - EQ2_8 4078*4882a593Smuzhiyun */ 4079*4882a593Smuzhiyun #define WM5100_EQ2_B2_C_MASK 0xFFFF /* EQ2_B2_C - [15:0] */ 4080*4882a593Smuzhiyun #define WM5100_EQ2_B2_C_SHIFT 0 /* EQ2_B2_C - [15:0] */ 4081*4882a593Smuzhiyun #define WM5100_EQ2_B2_C_WIDTH 16 /* EQ2_B2_C - [15:0] */ 4082*4882a593Smuzhiyun 4083*4882a593Smuzhiyun /* 4084*4882a593Smuzhiyun * R3630 (0xE2E) - EQ2_9 4085*4882a593Smuzhiyun */ 4086*4882a593Smuzhiyun #define WM5100_EQ2_B2_PG_MASK 0xFFFF /* EQ2_B2_PG - [15:0] */ 4087*4882a593Smuzhiyun #define WM5100_EQ2_B2_PG_SHIFT 0 /* EQ2_B2_PG - [15:0] */ 4088*4882a593Smuzhiyun #define WM5100_EQ2_B2_PG_WIDTH 16 /* EQ2_B2_PG - [15:0] */ 4089*4882a593Smuzhiyun 4090*4882a593Smuzhiyun /* 4091*4882a593Smuzhiyun * R3631 (0xE2F) - EQ2_10 4092*4882a593Smuzhiyun */ 4093*4882a593Smuzhiyun #define WM5100_EQ2_B3_A_MASK 0xFFFF /* EQ2_B3_A - [15:0] */ 4094*4882a593Smuzhiyun #define WM5100_EQ2_B3_A_SHIFT 0 /* EQ2_B3_A - [15:0] */ 4095*4882a593Smuzhiyun #define WM5100_EQ2_B3_A_WIDTH 16 /* EQ2_B3_A - [15:0] */ 4096*4882a593Smuzhiyun 4097*4882a593Smuzhiyun /* 4098*4882a593Smuzhiyun * R3632 (0xE30) - EQ2_11 4099*4882a593Smuzhiyun */ 4100*4882a593Smuzhiyun #define WM5100_EQ2_B3_B_MASK 0xFFFF /* EQ2_B3_B - [15:0] */ 4101*4882a593Smuzhiyun #define WM5100_EQ2_B3_B_SHIFT 0 /* EQ2_B3_B - [15:0] */ 4102*4882a593Smuzhiyun #define WM5100_EQ2_B3_B_WIDTH 16 /* EQ2_B3_B - [15:0] */ 4103*4882a593Smuzhiyun 4104*4882a593Smuzhiyun /* 4105*4882a593Smuzhiyun * R3633 (0xE31) - EQ2_12 4106*4882a593Smuzhiyun */ 4107*4882a593Smuzhiyun #define WM5100_EQ2_B3_C_MASK 0xFFFF /* EQ2_B3_C - [15:0] */ 4108*4882a593Smuzhiyun #define WM5100_EQ2_B3_C_SHIFT 0 /* EQ2_B3_C - [15:0] */ 4109*4882a593Smuzhiyun #define WM5100_EQ2_B3_C_WIDTH 16 /* EQ2_B3_C - [15:0] */ 4110*4882a593Smuzhiyun 4111*4882a593Smuzhiyun /* 4112*4882a593Smuzhiyun * R3634 (0xE32) - EQ2_13 4113*4882a593Smuzhiyun */ 4114*4882a593Smuzhiyun #define WM5100_EQ2_B3_PG_MASK 0xFFFF /* EQ2_B3_PG - [15:0] */ 4115*4882a593Smuzhiyun #define WM5100_EQ2_B3_PG_SHIFT 0 /* EQ2_B3_PG - [15:0] */ 4116*4882a593Smuzhiyun #define WM5100_EQ2_B3_PG_WIDTH 16 /* EQ2_B3_PG - [15:0] */ 4117*4882a593Smuzhiyun 4118*4882a593Smuzhiyun /* 4119*4882a593Smuzhiyun * R3635 (0xE33) - EQ2_14 4120*4882a593Smuzhiyun */ 4121*4882a593Smuzhiyun #define WM5100_EQ2_B4_A_MASK 0xFFFF /* EQ2_B4_A - [15:0] */ 4122*4882a593Smuzhiyun #define WM5100_EQ2_B4_A_SHIFT 0 /* EQ2_B4_A - [15:0] */ 4123*4882a593Smuzhiyun #define WM5100_EQ2_B4_A_WIDTH 16 /* EQ2_B4_A - [15:0] */ 4124*4882a593Smuzhiyun 4125*4882a593Smuzhiyun /* 4126*4882a593Smuzhiyun * R3636 (0xE34) - EQ2_15 4127*4882a593Smuzhiyun */ 4128*4882a593Smuzhiyun #define WM5100_EQ2_B4_B_MASK 0xFFFF /* EQ2_B4_B - [15:0] */ 4129*4882a593Smuzhiyun #define WM5100_EQ2_B4_B_SHIFT 0 /* EQ2_B4_B - [15:0] */ 4130*4882a593Smuzhiyun #define WM5100_EQ2_B4_B_WIDTH 16 /* EQ2_B4_B - [15:0] */ 4131*4882a593Smuzhiyun 4132*4882a593Smuzhiyun /* 4133*4882a593Smuzhiyun * R3637 (0xE35) - EQ2_16 4134*4882a593Smuzhiyun */ 4135*4882a593Smuzhiyun #define WM5100_EQ2_B4_C_MASK 0xFFFF /* EQ2_B4_C - [15:0] */ 4136*4882a593Smuzhiyun #define WM5100_EQ2_B4_C_SHIFT 0 /* EQ2_B4_C - [15:0] */ 4137*4882a593Smuzhiyun #define WM5100_EQ2_B4_C_WIDTH 16 /* EQ2_B4_C - [15:0] */ 4138*4882a593Smuzhiyun 4139*4882a593Smuzhiyun /* 4140*4882a593Smuzhiyun * R3638 (0xE36) - EQ2_17 4141*4882a593Smuzhiyun */ 4142*4882a593Smuzhiyun #define WM5100_EQ2_B4_PG_MASK 0xFFFF /* EQ2_B4_PG - [15:0] */ 4143*4882a593Smuzhiyun #define WM5100_EQ2_B4_PG_SHIFT 0 /* EQ2_B4_PG - [15:0] */ 4144*4882a593Smuzhiyun #define WM5100_EQ2_B4_PG_WIDTH 16 /* EQ2_B4_PG - [15:0] */ 4145*4882a593Smuzhiyun 4146*4882a593Smuzhiyun /* 4147*4882a593Smuzhiyun * R3639 (0xE37) - EQ2_18 4148*4882a593Smuzhiyun */ 4149*4882a593Smuzhiyun #define WM5100_EQ2_B5_A_MASK 0xFFFF /* EQ2_B5_A - [15:0] */ 4150*4882a593Smuzhiyun #define WM5100_EQ2_B5_A_SHIFT 0 /* EQ2_B5_A - [15:0] */ 4151*4882a593Smuzhiyun #define WM5100_EQ2_B5_A_WIDTH 16 /* EQ2_B5_A - [15:0] */ 4152*4882a593Smuzhiyun 4153*4882a593Smuzhiyun /* 4154*4882a593Smuzhiyun * R3640 (0xE38) - EQ2_19 4155*4882a593Smuzhiyun */ 4156*4882a593Smuzhiyun #define WM5100_EQ2_B5_B_MASK 0xFFFF /* EQ2_B5_B - [15:0] */ 4157*4882a593Smuzhiyun #define WM5100_EQ2_B5_B_SHIFT 0 /* EQ2_B5_B - [15:0] */ 4158*4882a593Smuzhiyun #define WM5100_EQ2_B5_B_WIDTH 16 /* EQ2_B5_B - [15:0] */ 4159*4882a593Smuzhiyun 4160*4882a593Smuzhiyun /* 4161*4882a593Smuzhiyun * R3641 (0xE39) - EQ2_20 4162*4882a593Smuzhiyun */ 4163*4882a593Smuzhiyun #define WM5100_EQ2_B5_PG_MASK 0xFFFF /* EQ2_B5_PG - [15:0] */ 4164*4882a593Smuzhiyun #define WM5100_EQ2_B5_PG_SHIFT 0 /* EQ2_B5_PG - [15:0] */ 4165*4882a593Smuzhiyun #define WM5100_EQ2_B5_PG_WIDTH 16 /* EQ2_B5_PG - [15:0] */ 4166*4882a593Smuzhiyun 4167*4882a593Smuzhiyun /* 4168*4882a593Smuzhiyun * R3644 (0xE3C) - EQ3_1 4169*4882a593Smuzhiyun */ 4170*4882a593Smuzhiyun #define WM5100_EQ3_B1_GAIN_MASK 0xF800 /* EQ3_B1_GAIN - [15:11] */ 4171*4882a593Smuzhiyun #define WM5100_EQ3_B1_GAIN_SHIFT 11 /* EQ3_B1_GAIN - [15:11] */ 4172*4882a593Smuzhiyun #define WM5100_EQ3_B1_GAIN_WIDTH 5 /* EQ3_B1_GAIN - [15:11] */ 4173*4882a593Smuzhiyun #define WM5100_EQ3_B2_GAIN_MASK 0x07C0 /* EQ3_B2_GAIN - [10:6] */ 4174*4882a593Smuzhiyun #define WM5100_EQ3_B2_GAIN_SHIFT 6 /* EQ3_B2_GAIN - [10:6] */ 4175*4882a593Smuzhiyun #define WM5100_EQ3_B2_GAIN_WIDTH 5 /* EQ3_B2_GAIN - [10:6] */ 4176*4882a593Smuzhiyun #define WM5100_EQ3_B3_GAIN_MASK 0x003E /* EQ3_B3_GAIN - [5:1] */ 4177*4882a593Smuzhiyun #define WM5100_EQ3_B3_GAIN_SHIFT 1 /* EQ3_B3_GAIN - [5:1] */ 4178*4882a593Smuzhiyun #define WM5100_EQ3_B3_GAIN_WIDTH 5 /* EQ3_B3_GAIN - [5:1] */ 4179*4882a593Smuzhiyun #define WM5100_EQ3_ENA 0x0001 /* EQ3_ENA */ 4180*4882a593Smuzhiyun #define WM5100_EQ3_ENA_MASK 0x0001 /* EQ3_ENA */ 4181*4882a593Smuzhiyun #define WM5100_EQ3_ENA_SHIFT 0 /* EQ3_ENA */ 4182*4882a593Smuzhiyun #define WM5100_EQ3_ENA_WIDTH 1 /* EQ3_ENA */ 4183*4882a593Smuzhiyun 4184*4882a593Smuzhiyun /* 4185*4882a593Smuzhiyun * R3645 (0xE3D) - EQ3_2 4186*4882a593Smuzhiyun */ 4187*4882a593Smuzhiyun #define WM5100_EQ3_B4_GAIN_MASK 0xF800 /* EQ3_B4_GAIN - [15:11] */ 4188*4882a593Smuzhiyun #define WM5100_EQ3_B4_GAIN_SHIFT 11 /* EQ3_B4_GAIN - [15:11] */ 4189*4882a593Smuzhiyun #define WM5100_EQ3_B4_GAIN_WIDTH 5 /* EQ3_B4_GAIN - [15:11] */ 4190*4882a593Smuzhiyun #define WM5100_EQ3_B5_GAIN_MASK 0x07C0 /* EQ3_B5_GAIN - [10:6] */ 4191*4882a593Smuzhiyun #define WM5100_EQ3_B5_GAIN_SHIFT 6 /* EQ3_B5_GAIN - [10:6] */ 4192*4882a593Smuzhiyun #define WM5100_EQ3_B5_GAIN_WIDTH 5 /* EQ3_B5_GAIN - [10:6] */ 4193*4882a593Smuzhiyun 4194*4882a593Smuzhiyun /* 4195*4882a593Smuzhiyun * R3646 (0xE3E) - EQ3_3 4196*4882a593Smuzhiyun */ 4197*4882a593Smuzhiyun #define WM5100_EQ3_B1_A_MASK 0xFFFF /* EQ3_B1_A - [15:0] */ 4198*4882a593Smuzhiyun #define WM5100_EQ3_B1_A_SHIFT 0 /* EQ3_B1_A - [15:0] */ 4199*4882a593Smuzhiyun #define WM5100_EQ3_B1_A_WIDTH 16 /* EQ3_B1_A - [15:0] */ 4200*4882a593Smuzhiyun 4201*4882a593Smuzhiyun /* 4202*4882a593Smuzhiyun * R3647 (0xE3F) - EQ3_4 4203*4882a593Smuzhiyun */ 4204*4882a593Smuzhiyun #define WM5100_EQ3_B1_B_MASK 0xFFFF /* EQ3_B1_B - [15:0] */ 4205*4882a593Smuzhiyun #define WM5100_EQ3_B1_B_SHIFT 0 /* EQ3_B1_B - [15:0] */ 4206*4882a593Smuzhiyun #define WM5100_EQ3_B1_B_WIDTH 16 /* EQ3_B1_B - [15:0] */ 4207*4882a593Smuzhiyun 4208*4882a593Smuzhiyun /* 4209*4882a593Smuzhiyun * R3648 (0xE40) - EQ3_5 4210*4882a593Smuzhiyun */ 4211*4882a593Smuzhiyun #define WM5100_EQ3_B1_PG_MASK 0xFFFF /* EQ3_B1_PG - [15:0] */ 4212*4882a593Smuzhiyun #define WM5100_EQ3_B1_PG_SHIFT 0 /* EQ3_B1_PG - [15:0] */ 4213*4882a593Smuzhiyun #define WM5100_EQ3_B1_PG_WIDTH 16 /* EQ3_B1_PG - [15:0] */ 4214*4882a593Smuzhiyun 4215*4882a593Smuzhiyun /* 4216*4882a593Smuzhiyun * R3649 (0xE41) - EQ3_6 4217*4882a593Smuzhiyun */ 4218*4882a593Smuzhiyun #define WM5100_EQ3_B2_A_MASK 0xFFFF /* EQ3_B2_A - [15:0] */ 4219*4882a593Smuzhiyun #define WM5100_EQ3_B2_A_SHIFT 0 /* EQ3_B2_A - [15:0] */ 4220*4882a593Smuzhiyun #define WM5100_EQ3_B2_A_WIDTH 16 /* EQ3_B2_A - [15:0] */ 4221*4882a593Smuzhiyun 4222*4882a593Smuzhiyun /* 4223*4882a593Smuzhiyun * R3650 (0xE42) - EQ3_7 4224*4882a593Smuzhiyun */ 4225*4882a593Smuzhiyun #define WM5100_EQ3_B2_B_MASK 0xFFFF /* EQ3_B2_B - [15:0] */ 4226*4882a593Smuzhiyun #define WM5100_EQ3_B2_B_SHIFT 0 /* EQ3_B2_B - [15:0] */ 4227*4882a593Smuzhiyun #define WM5100_EQ3_B2_B_WIDTH 16 /* EQ3_B2_B - [15:0] */ 4228*4882a593Smuzhiyun 4229*4882a593Smuzhiyun /* 4230*4882a593Smuzhiyun * R3651 (0xE43) - EQ3_8 4231*4882a593Smuzhiyun */ 4232*4882a593Smuzhiyun #define WM5100_EQ3_B2_C_MASK 0xFFFF /* EQ3_B2_C - [15:0] */ 4233*4882a593Smuzhiyun #define WM5100_EQ3_B2_C_SHIFT 0 /* EQ3_B2_C - [15:0] */ 4234*4882a593Smuzhiyun #define WM5100_EQ3_B2_C_WIDTH 16 /* EQ3_B2_C - [15:0] */ 4235*4882a593Smuzhiyun 4236*4882a593Smuzhiyun /* 4237*4882a593Smuzhiyun * R3652 (0xE44) - EQ3_9 4238*4882a593Smuzhiyun */ 4239*4882a593Smuzhiyun #define WM5100_EQ3_B2_PG_MASK 0xFFFF /* EQ3_B2_PG - [15:0] */ 4240*4882a593Smuzhiyun #define WM5100_EQ3_B2_PG_SHIFT 0 /* EQ3_B2_PG - [15:0] */ 4241*4882a593Smuzhiyun #define WM5100_EQ3_B2_PG_WIDTH 16 /* EQ3_B2_PG - [15:0] */ 4242*4882a593Smuzhiyun 4243*4882a593Smuzhiyun /* 4244*4882a593Smuzhiyun * R3653 (0xE45) - EQ3_10 4245*4882a593Smuzhiyun */ 4246*4882a593Smuzhiyun #define WM5100_EQ3_B3_A_MASK 0xFFFF /* EQ3_B3_A - [15:0] */ 4247*4882a593Smuzhiyun #define WM5100_EQ3_B3_A_SHIFT 0 /* EQ3_B3_A - [15:0] */ 4248*4882a593Smuzhiyun #define WM5100_EQ3_B3_A_WIDTH 16 /* EQ3_B3_A - [15:0] */ 4249*4882a593Smuzhiyun 4250*4882a593Smuzhiyun /* 4251*4882a593Smuzhiyun * R3654 (0xE46) - EQ3_11 4252*4882a593Smuzhiyun */ 4253*4882a593Smuzhiyun #define WM5100_EQ3_B3_B_MASK 0xFFFF /* EQ3_B3_B - [15:0] */ 4254*4882a593Smuzhiyun #define WM5100_EQ3_B3_B_SHIFT 0 /* EQ3_B3_B - [15:0] */ 4255*4882a593Smuzhiyun #define WM5100_EQ3_B3_B_WIDTH 16 /* EQ3_B3_B - [15:0] */ 4256*4882a593Smuzhiyun 4257*4882a593Smuzhiyun /* 4258*4882a593Smuzhiyun * R3655 (0xE47) - EQ3_12 4259*4882a593Smuzhiyun */ 4260*4882a593Smuzhiyun #define WM5100_EQ3_B3_C_MASK 0xFFFF /* EQ3_B3_C - [15:0] */ 4261*4882a593Smuzhiyun #define WM5100_EQ3_B3_C_SHIFT 0 /* EQ3_B3_C - [15:0] */ 4262*4882a593Smuzhiyun #define WM5100_EQ3_B3_C_WIDTH 16 /* EQ3_B3_C - [15:0] */ 4263*4882a593Smuzhiyun 4264*4882a593Smuzhiyun /* 4265*4882a593Smuzhiyun * R3656 (0xE48) - EQ3_13 4266*4882a593Smuzhiyun */ 4267*4882a593Smuzhiyun #define WM5100_EQ3_B3_PG_MASK 0xFFFF /* EQ3_B3_PG - [15:0] */ 4268*4882a593Smuzhiyun #define WM5100_EQ3_B3_PG_SHIFT 0 /* EQ3_B3_PG - [15:0] */ 4269*4882a593Smuzhiyun #define WM5100_EQ3_B3_PG_WIDTH 16 /* EQ3_B3_PG - [15:0] */ 4270*4882a593Smuzhiyun 4271*4882a593Smuzhiyun /* 4272*4882a593Smuzhiyun * R3657 (0xE49) - EQ3_14 4273*4882a593Smuzhiyun */ 4274*4882a593Smuzhiyun #define WM5100_EQ3_B4_A_MASK 0xFFFF /* EQ3_B4_A - [15:0] */ 4275*4882a593Smuzhiyun #define WM5100_EQ3_B4_A_SHIFT 0 /* EQ3_B4_A - [15:0] */ 4276*4882a593Smuzhiyun #define WM5100_EQ3_B4_A_WIDTH 16 /* EQ3_B4_A - [15:0] */ 4277*4882a593Smuzhiyun 4278*4882a593Smuzhiyun /* 4279*4882a593Smuzhiyun * R3658 (0xE4A) - EQ3_15 4280*4882a593Smuzhiyun */ 4281*4882a593Smuzhiyun #define WM5100_EQ3_B4_B_MASK 0xFFFF /* EQ3_B4_B - [15:0] */ 4282*4882a593Smuzhiyun #define WM5100_EQ3_B4_B_SHIFT 0 /* EQ3_B4_B - [15:0] */ 4283*4882a593Smuzhiyun #define WM5100_EQ3_B4_B_WIDTH 16 /* EQ3_B4_B - [15:0] */ 4284*4882a593Smuzhiyun 4285*4882a593Smuzhiyun /* 4286*4882a593Smuzhiyun * R3659 (0xE4B) - EQ3_16 4287*4882a593Smuzhiyun */ 4288*4882a593Smuzhiyun #define WM5100_EQ3_B4_C_MASK 0xFFFF /* EQ3_B4_C - [15:0] */ 4289*4882a593Smuzhiyun #define WM5100_EQ3_B4_C_SHIFT 0 /* EQ3_B4_C - [15:0] */ 4290*4882a593Smuzhiyun #define WM5100_EQ3_B4_C_WIDTH 16 /* EQ3_B4_C - [15:0] */ 4291*4882a593Smuzhiyun 4292*4882a593Smuzhiyun /* 4293*4882a593Smuzhiyun * R3660 (0xE4C) - EQ3_17 4294*4882a593Smuzhiyun */ 4295*4882a593Smuzhiyun #define WM5100_EQ3_B4_PG_MASK 0xFFFF /* EQ3_B4_PG - [15:0] */ 4296*4882a593Smuzhiyun #define WM5100_EQ3_B4_PG_SHIFT 0 /* EQ3_B4_PG - [15:0] */ 4297*4882a593Smuzhiyun #define WM5100_EQ3_B4_PG_WIDTH 16 /* EQ3_B4_PG - [15:0] */ 4298*4882a593Smuzhiyun 4299*4882a593Smuzhiyun /* 4300*4882a593Smuzhiyun * R3661 (0xE4D) - EQ3_18 4301*4882a593Smuzhiyun */ 4302*4882a593Smuzhiyun #define WM5100_EQ3_B5_A_MASK 0xFFFF /* EQ3_B5_A - [15:0] */ 4303*4882a593Smuzhiyun #define WM5100_EQ3_B5_A_SHIFT 0 /* EQ3_B5_A - [15:0] */ 4304*4882a593Smuzhiyun #define WM5100_EQ3_B5_A_WIDTH 16 /* EQ3_B5_A - [15:0] */ 4305*4882a593Smuzhiyun 4306*4882a593Smuzhiyun /* 4307*4882a593Smuzhiyun * R3662 (0xE4E) - EQ3_19 4308*4882a593Smuzhiyun */ 4309*4882a593Smuzhiyun #define WM5100_EQ3_B5_B_MASK 0xFFFF /* EQ3_B5_B - [15:0] */ 4310*4882a593Smuzhiyun #define WM5100_EQ3_B5_B_SHIFT 0 /* EQ3_B5_B - [15:0] */ 4311*4882a593Smuzhiyun #define WM5100_EQ3_B5_B_WIDTH 16 /* EQ3_B5_B - [15:0] */ 4312*4882a593Smuzhiyun 4313*4882a593Smuzhiyun /* 4314*4882a593Smuzhiyun * R3663 (0xE4F) - EQ3_20 4315*4882a593Smuzhiyun */ 4316*4882a593Smuzhiyun #define WM5100_EQ3_B5_PG_MASK 0xFFFF /* EQ3_B5_PG - [15:0] */ 4317*4882a593Smuzhiyun #define WM5100_EQ3_B5_PG_SHIFT 0 /* EQ3_B5_PG - [15:0] */ 4318*4882a593Smuzhiyun #define WM5100_EQ3_B5_PG_WIDTH 16 /* EQ3_B5_PG - [15:0] */ 4319*4882a593Smuzhiyun 4320*4882a593Smuzhiyun /* 4321*4882a593Smuzhiyun * R3666 (0xE52) - EQ4_1 4322*4882a593Smuzhiyun */ 4323*4882a593Smuzhiyun #define WM5100_EQ4_B1_GAIN_MASK 0xF800 /* EQ4_B1_GAIN - [15:11] */ 4324*4882a593Smuzhiyun #define WM5100_EQ4_B1_GAIN_SHIFT 11 /* EQ4_B1_GAIN - [15:11] */ 4325*4882a593Smuzhiyun #define WM5100_EQ4_B1_GAIN_WIDTH 5 /* EQ4_B1_GAIN - [15:11] */ 4326*4882a593Smuzhiyun #define WM5100_EQ4_B2_GAIN_MASK 0x07C0 /* EQ4_B2_GAIN - [10:6] */ 4327*4882a593Smuzhiyun #define WM5100_EQ4_B2_GAIN_SHIFT 6 /* EQ4_B2_GAIN - [10:6] */ 4328*4882a593Smuzhiyun #define WM5100_EQ4_B2_GAIN_WIDTH 5 /* EQ4_B2_GAIN - [10:6] */ 4329*4882a593Smuzhiyun #define WM5100_EQ4_B3_GAIN_MASK 0x003E /* EQ4_B3_GAIN - [5:1] */ 4330*4882a593Smuzhiyun #define WM5100_EQ4_B3_GAIN_SHIFT 1 /* EQ4_B3_GAIN - [5:1] */ 4331*4882a593Smuzhiyun #define WM5100_EQ4_B3_GAIN_WIDTH 5 /* EQ4_B3_GAIN - [5:1] */ 4332*4882a593Smuzhiyun #define WM5100_EQ4_ENA 0x0001 /* EQ4_ENA */ 4333*4882a593Smuzhiyun #define WM5100_EQ4_ENA_MASK 0x0001 /* EQ4_ENA */ 4334*4882a593Smuzhiyun #define WM5100_EQ4_ENA_SHIFT 0 /* EQ4_ENA */ 4335*4882a593Smuzhiyun #define WM5100_EQ4_ENA_WIDTH 1 /* EQ4_ENA */ 4336*4882a593Smuzhiyun 4337*4882a593Smuzhiyun /* 4338*4882a593Smuzhiyun * R3667 (0xE53) - EQ4_2 4339*4882a593Smuzhiyun */ 4340*4882a593Smuzhiyun #define WM5100_EQ4_B4_GAIN_MASK 0xF800 /* EQ4_B4_GAIN - [15:11] */ 4341*4882a593Smuzhiyun #define WM5100_EQ4_B4_GAIN_SHIFT 11 /* EQ4_B4_GAIN - [15:11] */ 4342*4882a593Smuzhiyun #define WM5100_EQ4_B4_GAIN_WIDTH 5 /* EQ4_B4_GAIN - [15:11] */ 4343*4882a593Smuzhiyun #define WM5100_EQ4_B5_GAIN_MASK 0x07C0 /* EQ4_B5_GAIN - [10:6] */ 4344*4882a593Smuzhiyun #define WM5100_EQ4_B5_GAIN_SHIFT 6 /* EQ4_B5_GAIN - [10:6] */ 4345*4882a593Smuzhiyun #define WM5100_EQ4_B5_GAIN_WIDTH 5 /* EQ4_B5_GAIN - [10:6] */ 4346*4882a593Smuzhiyun 4347*4882a593Smuzhiyun /* 4348*4882a593Smuzhiyun * R3668 (0xE54) - EQ4_3 4349*4882a593Smuzhiyun */ 4350*4882a593Smuzhiyun #define WM5100_EQ4_B1_A_MASK 0xFFFF /* EQ4_B1_A - [15:0] */ 4351*4882a593Smuzhiyun #define WM5100_EQ4_B1_A_SHIFT 0 /* EQ4_B1_A - [15:0] */ 4352*4882a593Smuzhiyun #define WM5100_EQ4_B1_A_WIDTH 16 /* EQ4_B1_A - [15:0] */ 4353*4882a593Smuzhiyun 4354*4882a593Smuzhiyun /* 4355*4882a593Smuzhiyun * R3669 (0xE55) - EQ4_4 4356*4882a593Smuzhiyun */ 4357*4882a593Smuzhiyun #define WM5100_EQ4_B1_B_MASK 0xFFFF /* EQ4_B1_B - [15:0] */ 4358*4882a593Smuzhiyun #define WM5100_EQ4_B1_B_SHIFT 0 /* EQ4_B1_B - [15:0] */ 4359*4882a593Smuzhiyun #define WM5100_EQ4_B1_B_WIDTH 16 /* EQ4_B1_B - [15:0] */ 4360*4882a593Smuzhiyun 4361*4882a593Smuzhiyun /* 4362*4882a593Smuzhiyun * R3670 (0xE56) - EQ4_5 4363*4882a593Smuzhiyun */ 4364*4882a593Smuzhiyun #define WM5100_EQ4_B1_PG_MASK 0xFFFF /* EQ4_B1_PG - [15:0] */ 4365*4882a593Smuzhiyun #define WM5100_EQ4_B1_PG_SHIFT 0 /* EQ4_B1_PG - [15:0] */ 4366*4882a593Smuzhiyun #define WM5100_EQ4_B1_PG_WIDTH 16 /* EQ4_B1_PG - [15:0] */ 4367*4882a593Smuzhiyun 4368*4882a593Smuzhiyun /* 4369*4882a593Smuzhiyun * R3671 (0xE57) - EQ4_6 4370*4882a593Smuzhiyun */ 4371*4882a593Smuzhiyun #define WM5100_EQ4_B2_A_MASK 0xFFFF /* EQ4_B2_A - [15:0] */ 4372*4882a593Smuzhiyun #define WM5100_EQ4_B2_A_SHIFT 0 /* EQ4_B2_A - [15:0] */ 4373*4882a593Smuzhiyun #define WM5100_EQ4_B2_A_WIDTH 16 /* EQ4_B2_A - [15:0] */ 4374*4882a593Smuzhiyun 4375*4882a593Smuzhiyun /* 4376*4882a593Smuzhiyun * R3672 (0xE58) - EQ4_7 4377*4882a593Smuzhiyun */ 4378*4882a593Smuzhiyun #define WM5100_EQ4_B2_B_MASK 0xFFFF /* EQ4_B2_B - [15:0] */ 4379*4882a593Smuzhiyun #define WM5100_EQ4_B2_B_SHIFT 0 /* EQ4_B2_B - [15:0] */ 4380*4882a593Smuzhiyun #define WM5100_EQ4_B2_B_WIDTH 16 /* EQ4_B2_B - [15:0] */ 4381*4882a593Smuzhiyun 4382*4882a593Smuzhiyun /* 4383*4882a593Smuzhiyun * R3673 (0xE59) - EQ4_8 4384*4882a593Smuzhiyun */ 4385*4882a593Smuzhiyun #define WM5100_EQ4_B2_C_MASK 0xFFFF /* EQ4_B2_C - [15:0] */ 4386*4882a593Smuzhiyun #define WM5100_EQ4_B2_C_SHIFT 0 /* EQ4_B2_C - [15:0] */ 4387*4882a593Smuzhiyun #define WM5100_EQ4_B2_C_WIDTH 16 /* EQ4_B2_C - [15:0] */ 4388*4882a593Smuzhiyun 4389*4882a593Smuzhiyun /* 4390*4882a593Smuzhiyun * R3674 (0xE5A) - EQ4_9 4391*4882a593Smuzhiyun */ 4392*4882a593Smuzhiyun #define WM5100_EQ4_B2_PG_MASK 0xFFFF /* EQ4_B2_PG - [15:0] */ 4393*4882a593Smuzhiyun #define WM5100_EQ4_B2_PG_SHIFT 0 /* EQ4_B2_PG - [15:0] */ 4394*4882a593Smuzhiyun #define WM5100_EQ4_B2_PG_WIDTH 16 /* EQ4_B2_PG - [15:0] */ 4395*4882a593Smuzhiyun 4396*4882a593Smuzhiyun /* 4397*4882a593Smuzhiyun * R3675 (0xE5B) - EQ4_10 4398*4882a593Smuzhiyun */ 4399*4882a593Smuzhiyun #define WM5100_EQ4_B3_A_MASK 0xFFFF /* EQ4_B3_A - [15:0] */ 4400*4882a593Smuzhiyun #define WM5100_EQ4_B3_A_SHIFT 0 /* EQ4_B3_A - [15:0] */ 4401*4882a593Smuzhiyun #define WM5100_EQ4_B3_A_WIDTH 16 /* EQ4_B3_A - [15:0] */ 4402*4882a593Smuzhiyun 4403*4882a593Smuzhiyun /* 4404*4882a593Smuzhiyun * R3676 (0xE5C) - EQ4_11 4405*4882a593Smuzhiyun */ 4406*4882a593Smuzhiyun #define WM5100_EQ4_B3_B_MASK 0xFFFF /* EQ4_B3_B - [15:0] */ 4407*4882a593Smuzhiyun #define WM5100_EQ4_B3_B_SHIFT 0 /* EQ4_B3_B - [15:0] */ 4408*4882a593Smuzhiyun #define WM5100_EQ4_B3_B_WIDTH 16 /* EQ4_B3_B - [15:0] */ 4409*4882a593Smuzhiyun 4410*4882a593Smuzhiyun /* 4411*4882a593Smuzhiyun * R3677 (0xE5D) - EQ4_12 4412*4882a593Smuzhiyun */ 4413*4882a593Smuzhiyun #define WM5100_EQ4_B3_C_MASK 0xFFFF /* EQ4_B3_C - [15:0] */ 4414*4882a593Smuzhiyun #define WM5100_EQ4_B3_C_SHIFT 0 /* EQ4_B3_C - [15:0] */ 4415*4882a593Smuzhiyun #define WM5100_EQ4_B3_C_WIDTH 16 /* EQ4_B3_C - [15:0] */ 4416*4882a593Smuzhiyun 4417*4882a593Smuzhiyun /* 4418*4882a593Smuzhiyun * R3678 (0xE5E) - EQ4_13 4419*4882a593Smuzhiyun */ 4420*4882a593Smuzhiyun #define WM5100_EQ4_B3_PG_MASK 0xFFFF /* EQ4_B3_PG - [15:0] */ 4421*4882a593Smuzhiyun #define WM5100_EQ4_B3_PG_SHIFT 0 /* EQ4_B3_PG - [15:0] */ 4422*4882a593Smuzhiyun #define WM5100_EQ4_B3_PG_WIDTH 16 /* EQ4_B3_PG - [15:0] */ 4423*4882a593Smuzhiyun 4424*4882a593Smuzhiyun /* 4425*4882a593Smuzhiyun * R3679 (0xE5F) - EQ4_14 4426*4882a593Smuzhiyun */ 4427*4882a593Smuzhiyun #define WM5100_EQ4_B4_A_MASK 0xFFFF /* EQ4_B4_A - [15:0] */ 4428*4882a593Smuzhiyun #define WM5100_EQ4_B4_A_SHIFT 0 /* EQ4_B4_A - [15:0] */ 4429*4882a593Smuzhiyun #define WM5100_EQ4_B4_A_WIDTH 16 /* EQ4_B4_A - [15:0] */ 4430*4882a593Smuzhiyun 4431*4882a593Smuzhiyun /* 4432*4882a593Smuzhiyun * R3680 (0xE60) - EQ4_15 4433*4882a593Smuzhiyun */ 4434*4882a593Smuzhiyun #define WM5100_EQ4_B4_B_MASK 0xFFFF /* EQ4_B4_B - [15:0] */ 4435*4882a593Smuzhiyun #define WM5100_EQ4_B4_B_SHIFT 0 /* EQ4_B4_B - [15:0] */ 4436*4882a593Smuzhiyun #define WM5100_EQ4_B4_B_WIDTH 16 /* EQ4_B4_B - [15:0] */ 4437*4882a593Smuzhiyun 4438*4882a593Smuzhiyun /* 4439*4882a593Smuzhiyun * R3681 (0xE61) - EQ4_16 4440*4882a593Smuzhiyun */ 4441*4882a593Smuzhiyun #define WM5100_EQ4_B4_C_MASK 0xFFFF /* EQ4_B4_C - [15:0] */ 4442*4882a593Smuzhiyun #define WM5100_EQ4_B4_C_SHIFT 0 /* EQ4_B4_C - [15:0] */ 4443*4882a593Smuzhiyun #define WM5100_EQ4_B4_C_WIDTH 16 /* EQ4_B4_C - [15:0] */ 4444*4882a593Smuzhiyun 4445*4882a593Smuzhiyun /* 4446*4882a593Smuzhiyun * R3682 (0xE62) - EQ4_17 4447*4882a593Smuzhiyun */ 4448*4882a593Smuzhiyun #define WM5100_EQ4_B4_PG_MASK 0xFFFF /* EQ4_B4_PG - [15:0] */ 4449*4882a593Smuzhiyun #define WM5100_EQ4_B4_PG_SHIFT 0 /* EQ4_B4_PG - [15:0] */ 4450*4882a593Smuzhiyun #define WM5100_EQ4_B4_PG_WIDTH 16 /* EQ4_B4_PG - [15:0] */ 4451*4882a593Smuzhiyun 4452*4882a593Smuzhiyun /* 4453*4882a593Smuzhiyun * R3683 (0xE63) - EQ4_18 4454*4882a593Smuzhiyun */ 4455*4882a593Smuzhiyun #define WM5100_EQ4_B5_A_MASK 0xFFFF /* EQ4_B5_A - [15:0] */ 4456*4882a593Smuzhiyun #define WM5100_EQ4_B5_A_SHIFT 0 /* EQ4_B5_A - [15:0] */ 4457*4882a593Smuzhiyun #define WM5100_EQ4_B5_A_WIDTH 16 /* EQ4_B5_A - [15:0] */ 4458*4882a593Smuzhiyun 4459*4882a593Smuzhiyun /* 4460*4882a593Smuzhiyun * R3684 (0xE64) - EQ4_19 4461*4882a593Smuzhiyun */ 4462*4882a593Smuzhiyun #define WM5100_EQ4_B5_B_MASK 0xFFFF /* EQ4_B5_B - [15:0] */ 4463*4882a593Smuzhiyun #define WM5100_EQ4_B5_B_SHIFT 0 /* EQ4_B5_B - [15:0] */ 4464*4882a593Smuzhiyun #define WM5100_EQ4_B5_B_WIDTH 16 /* EQ4_B5_B - [15:0] */ 4465*4882a593Smuzhiyun 4466*4882a593Smuzhiyun /* 4467*4882a593Smuzhiyun * R3685 (0xE65) - EQ4_20 4468*4882a593Smuzhiyun */ 4469*4882a593Smuzhiyun #define WM5100_EQ4_B5_PG_MASK 0xFFFF /* EQ4_B5_PG - [15:0] */ 4470*4882a593Smuzhiyun #define WM5100_EQ4_B5_PG_SHIFT 0 /* EQ4_B5_PG - [15:0] */ 4471*4882a593Smuzhiyun #define WM5100_EQ4_B5_PG_WIDTH 16 /* EQ4_B5_PG - [15:0] */ 4472*4882a593Smuzhiyun 4473*4882a593Smuzhiyun /* 4474*4882a593Smuzhiyun * R3712 (0xE80) - DRC1 ctrl1 4475*4882a593Smuzhiyun */ 4476*4882a593Smuzhiyun #define WM5100_DRC_SIG_DET_RMS_MASK 0xF800 /* DRC_SIG_DET_RMS - [15:11] */ 4477*4882a593Smuzhiyun #define WM5100_DRC_SIG_DET_RMS_SHIFT 11 /* DRC_SIG_DET_RMS - [15:11] */ 4478*4882a593Smuzhiyun #define WM5100_DRC_SIG_DET_RMS_WIDTH 5 /* DRC_SIG_DET_RMS - [15:11] */ 4479*4882a593Smuzhiyun #define WM5100_DRC_SIG_DET_PK_MASK 0x0600 /* DRC_SIG_DET_PK - [10:9] */ 4480*4882a593Smuzhiyun #define WM5100_DRC_SIG_DET_PK_SHIFT 9 /* DRC_SIG_DET_PK - [10:9] */ 4481*4882a593Smuzhiyun #define WM5100_DRC_SIG_DET_PK_WIDTH 2 /* DRC_SIG_DET_PK - [10:9] */ 4482*4882a593Smuzhiyun #define WM5100_DRC_NG_ENA 0x0100 /* DRC_NG_ENA */ 4483*4882a593Smuzhiyun #define WM5100_DRC_NG_ENA_MASK 0x0100 /* DRC_NG_ENA */ 4484*4882a593Smuzhiyun #define WM5100_DRC_NG_ENA_SHIFT 8 /* DRC_NG_ENA */ 4485*4882a593Smuzhiyun #define WM5100_DRC_NG_ENA_WIDTH 1 /* DRC_NG_ENA */ 4486*4882a593Smuzhiyun #define WM5100_DRC_SIG_DET_MODE 0x0080 /* DRC_SIG_DET_MODE */ 4487*4882a593Smuzhiyun #define WM5100_DRC_SIG_DET_MODE_MASK 0x0080 /* DRC_SIG_DET_MODE */ 4488*4882a593Smuzhiyun #define WM5100_DRC_SIG_DET_MODE_SHIFT 7 /* DRC_SIG_DET_MODE */ 4489*4882a593Smuzhiyun #define WM5100_DRC_SIG_DET_MODE_WIDTH 1 /* DRC_SIG_DET_MODE */ 4490*4882a593Smuzhiyun #define WM5100_DRC_SIG_DET 0x0040 /* DRC_SIG_DET */ 4491*4882a593Smuzhiyun #define WM5100_DRC_SIG_DET_MASK 0x0040 /* DRC_SIG_DET */ 4492*4882a593Smuzhiyun #define WM5100_DRC_SIG_DET_SHIFT 6 /* DRC_SIG_DET */ 4493*4882a593Smuzhiyun #define WM5100_DRC_SIG_DET_WIDTH 1 /* DRC_SIG_DET */ 4494*4882a593Smuzhiyun #define WM5100_DRC_KNEE2_OP_ENA 0x0020 /* DRC_KNEE2_OP_ENA */ 4495*4882a593Smuzhiyun #define WM5100_DRC_KNEE2_OP_ENA_MASK 0x0020 /* DRC_KNEE2_OP_ENA */ 4496*4882a593Smuzhiyun #define WM5100_DRC_KNEE2_OP_ENA_SHIFT 5 /* DRC_KNEE2_OP_ENA */ 4497*4882a593Smuzhiyun #define WM5100_DRC_KNEE2_OP_ENA_WIDTH 1 /* DRC_KNEE2_OP_ENA */ 4498*4882a593Smuzhiyun #define WM5100_DRC_QR 0x0010 /* DRC_QR */ 4499*4882a593Smuzhiyun #define WM5100_DRC_QR_MASK 0x0010 /* DRC_QR */ 4500*4882a593Smuzhiyun #define WM5100_DRC_QR_SHIFT 4 /* DRC_QR */ 4501*4882a593Smuzhiyun #define WM5100_DRC_QR_WIDTH 1 /* DRC_QR */ 4502*4882a593Smuzhiyun #define WM5100_DRC_ANTICLIP 0x0008 /* DRC_ANTICLIP */ 4503*4882a593Smuzhiyun #define WM5100_DRC_ANTICLIP_MASK 0x0008 /* DRC_ANTICLIP */ 4504*4882a593Smuzhiyun #define WM5100_DRC_ANTICLIP_SHIFT 3 /* DRC_ANTICLIP */ 4505*4882a593Smuzhiyun #define WM5100_DRC_ANTICLIP_WIDTH 1 /* DRC_ANTICLIP */ 4506*4882a593Smuzhiyun #define WM5100_DRCL_ENA 0x0002 /* DRCL_ENA */ 4507*4882a593Smuzhiyun #define WM5100_DRCL_ENA_MASK 0x0002 /* DRCL_ENA */ 4508*4882a593Smuzhiyun #define WM5100_DRCL_ENA_SHIFT 1 /* DRCL_ENA */ 4509*4882a593Smuzhiyun #define WM5100_DRCL_ENA_WIDTH 1 /* DRCL_ENA */ 4510*4882a593Smuzhiyun #define WM5100_DRCR_ENA 0x0001 /* DRCR_ENA */ 4511*4882a593Smuzhiyun #define WM5100_DRCR_ENA_MASK 0x0001 /* DRCR_ENA */ 4512*4882a593Smuzhiyun #define WM5100_DRCR_ENA_SHIFT 0 /* DRCR_ENA */ 4513*4882a593Smuzhiyun #define WM5100_DRCR_ENA_WIDTH 1 /* DRCR_ENA */ 4514*4882a593Smuzhiyun 4515*4882a593Smuzhiyun /* 4516*4882a593Smuzhiyun * R3713 (0xE81) - DRC1 ctrl2 4517*4882a593Smuzhiyun */ 4518*4882a593Smuzhiyun #define WM5100_DRC_ATK_MASK 0x1E00 /* DRC_ATK - [12:9] */ 4519*4882a593Smuzhiyun #define WM5100_DRC_ATK_SHIFT 9 /* DRC_ATK - [12:9] */ 4520*4882a593Smuzhiyun #define WM5100_DRC_ATK_WIDTH 4 /* DRC_ATK - [12:9] */ 4521*4882a593Smuzhiyun #define WM5100_DRC_DCY_MASK 0x01E0 /* DRC_DCY - [8:5] */ 4522*4882a593Smuzhiyun #define WM5100_DRC_DCY_SHIFT 5 /* DRC_DCY - [8:5] */ 4523*4882a593Smuzhiyun #define WM5100_DRC_DCY_WIDTH 4 /* DRC_DCY - [8:5] */ 4524*4882a593Smuzhiyun #define WM5100_DRC_MINGAIN_MASK 0x001C /* DRC_MINGAIN - [4:2] */ 4525*4882a593Smuzhiyun #define WM5100_DRC_MINGAIN_SHIFT 2 /* DRC_MINGAIN - [4:2] */ 4526*4882a593Smuzhiyun #define WM5100_DRC_MINGAIN_WIDTH 3 /* DRC_MINGAIN - [4:2] */ 4527*4882a593Smuzhiyun #define WM5100_DRC_MAXGAIN_MASK 0x0003 /* DRC_MAXGAIN - [1:0] */ 4528*4882a593Smuzhiyun #define WM5100_DRC_MAXGAIN_SHIFT 0 /* DRC_MAXGAIN - [1:0] */ 4529*4882a593Smuzhiyun #define WM5100_DRC_MAXGAIN_WIDTH 2 /* DRC_MAXGAIN - [1:0] */ 4530*4882a593Smuzhiyun 4531*4882a593Smuzhiyun /* 4532*4882a593Smuzhiyun * R3714 (0xE82) - DRC1 ctrl3 4533*4882a593Smuzhiyun */ 4534*4882a593Smuzhiyun #define WM5100_DRC_NG_MINGAIN_MASK 0xF000 /* DRC_NG_MINGAIN - [15:12] */ 4535*4882a593Smuzhiyun #define WM5100_DRC_NG_MINGAIN_SHIFT 12 /* DRC_NG_MINGAIN - [15:12] */ 4536*4882a593Smuzhiyun #define WM5100_DRC_NG_MINGAIN_WIDTH 4 /* DRC_NG_MINGAIN - [15:12] */ 4537*4882a593Smuzhiyun #define WM5100_DRC_NG_EXP_MASK 0x0C00 /* DRC_NG_EXP - [11:10] */ 4538*4882a593Smuzhiyun #define WM5100_DRC_NG_EXP_SHIFT 10 /* DRC_NG_EXP - [11:10] */ 4539*4882a593Smuzhiyun #define WM5100_DRC_NG_EXP_WIDTH 2 /* DRC_NG_EXP - [11:10] */ 4540*4882a593Smuzhiyun #define WM5100_DRC_QR_THR_MASK 0x0300 /* DRC_QR_THR - [9:8] */ 4541*4882a593Smuzhiyun #define WM5100_DRC_QR_THR_SHIFT 8 /* DRC_QR_THR - [9:8] */ 4542*4882a593Smuzhiyun #define WM5100_DRC_QR_THR_WIDTH 2 /* DRC_QR_THR - [9:8] */ 4543*4882a593Smuzhiyun #define WM5100_DRC_QR_DCY_MASK 0x00C0 /* DRC_QR_DCY - [7:6] */ 4544*4882a593Smuzhiyun #define WM5100_DRC_QR_DCY_SHIFT 6 /* DRC_QR_DCY - [7:6] */ 4545*4882a593Smuzhiyun #define WM5100_DRC_QR_DCY_WIDTH 2 /* DRC_QR_DCY - [7:6] */ 4546*4882a593Smuzhiyun #define WM5100_DRC_HI_COMP_MASK 0x0038 /* DRC_HI_COMP - [5:3] */ 4547*4882a593Smuzhiyun #define WM5100_DRC_HI_COMP_SHIFT 3 /* DRC_HI_COMP - [5:3] */ 4548*4882a593Smuzhiyun #define WM5100_DRC_HI_COMP_WIDTH 3 /* DRC_HI_COMP - [5:3] */ 4549*4882a593Smuzhiyun #define WM5100_DRC_LO_COMP_MASK 0x0007 /* DRC_LO_COMP - [2:0] */ 4550*4882a593Smuzhiyun #define WM5100_DRC_LO_COMP_SHIFT 0 /* DRC_LO_COMP - [2:0] */ 4551*4882a593Smuzhiyun #define WM5100_DRC_LO_COMP_WIDTH 3 /* DRC_LO_COMP - [2:0] */ 4552*4882a593Smuzhiyun 4553*4882a593Smuzhiyun /* 4554*4882a593Smuzhiyun * R3715 (0xE83) - DRC1 ctrl4 4555*4882a593Smuzhiyun */ 4556*4882a593Smuzhiyun #define WM5100_DRC_KNEE_IP_MASK 0x07E0 /* DRC_KNEE_IP - [10:5] */ 4557*4882a593Smuzhiyun #define WM5100_DRC_KNEE_IP_SHIFT 5 /* DRC_KNEE_IP - [10:5] */ 4558*4882a593Smuzhiyun #define WM5100_DRC_KNEE_IP_WIDTH 6 /* DRC_KNEE_IP - [10:5] */ 4559*4882a593Smuzhiyun #define WM5100_DRC_KNEE_OP_MASK 0x001F /* DRC_KNEE_OP - [4:0] */ 4560*4882a593Smuzhiyun #define WM5100_DRC_KNEE_OP_SHIFT 0 /* DRC_KNEE_OP - [4:0] */ 4561*4882a593Smuzhiyun #define WM5100_DRC_KNEE_OP_WIDTH 5 /* DRC_KNEE_OP - [4:0] */ 4562*4882a593Smuzhiyun 4563*4882a593Smuzhiyun /* 4564*4882a593Smuzhiyun * R3716 (0xE84) - DRC1 ctrl5 4565*4882a593Smuzhiyun */ 4566*4882a593Smuzhiyun #define WM5100_DRC_KNEE2_IP_MASK 0x03E0 /* DRC_KNEE2_IP - [9:5] */ 4567*4882a593Smuzhiyun #define WM5100_DRC_KNEE2_IP_SHIFT 5 /* DRC_KNEE2_IP - [9:5] */ 4568*4882a593Smuzhiyun #define WM5100_DRC_KNEE2_IP_WIDTH 5 /* DRC_KNEE2_IP - [9:5] */ 4569*4882a593Smuzhiyun #define WM5100_DRC_KNEE2_OP_MASK 0x001F /* DRC_KNEE2_OP - [4:0] */ 4570*4882a593Smuzhiyun #define WM5100_DRC_KNEE2_OP_SHIFT 0 /* DRC_KNEE2_OP - [4:0] */ 4571*4882a593Smuzhiyun #define WM5100_DRC_KNEE2_OP_WIDTH 5 /* DRC_KNEE2_OP - [4:0] */ 4572*4882a593Smuzhiyun 4573*4882a593Smuzhiyun /* 4574*4882a593Smuzhiyun * R3776 (0xEC0) - HPLPF1_1 4575*4882a593Smuzhiyun */ 4576*4882a593Smuzhiyun #define WM5100_LHPF1_MODE 0x0002 /* LHPF1_MODE */ 4577*4882a593Smuzhiyun #define WM5100_LHPF1_MODE_MASK 0x0002 /* LHPF1_MODE */ 4578*4882a593Smuzhiyun #define WM5100_LHPF1_MODE_SHIFT 1 /* LHPF1_MODE */ 4579*4882a593Smuzhiyun #define WM5100_LHPF1_MODE_WIDTH 1 /* LHPF1_MODE */ 4580*4882a593Smuzhiyun #define WM5100_LHPF1_ENA 0x0001 /* LHPF1_ENA */ 4581*4882a593Smuzhiyun #define WM5100_LHPF1_ENA_MASK 0x0001 /* LHPF1_ENA */ 4582*4882a593Smuzhiyun #define WM5100_LHPF1_ENA_SHIFT 0 /* LHPF1_ENA */ 4583*4882a593Smuzhiyun #define WM5100_LHPF1_ENA_WIDTH 1 /* LHPF1_ENA */ 4584*4882a593Smuzhiyun 4585*4882a593Smuzhiyun /* 4586*4882a593Smuzhiyun * R3777 (0xEC1) - HPLPF1_2 4587*4882a593Smuzhiyun */ 4588*4882a593Smuzhiyun #define WM5100_LHPF1_COEFF_MASK 0xFFFF /* LHPF1_COEFF - [15:0] */ 4589*4882a593Smuzhiyun #define WM5100_LHPF1_COEFF_SHIFT 0 /* LHPF1_COEFF - [15:0] */ 4590*4882a593Smuzhiyun #define WM5100_LHPF1_COEFF_WIDTH 16 /* LHPF1_COEFF - [15:0] */ 4591*4882a593Smuzhiyun 4592*4882a593Smuzhiyun /* 4593*4882a593Smuzhiyun * R3780 (0xEC4) - HPLPF2_1 4594*4882a593Smuzhiyun */ 4595*4882a593Smuzhiyun #define WM5100_LHPF2_MODE 0x0002 /* LHPF2_MODE */ 4596*4882a593Smuzhiyun #define WM5100_LHPF2_MODE_MASK 0x0002 /* LHPF2_MODE */ 4597*4882a593Smuzhiyun #define WM5100_LHPF2_MODE_SHIFT 1 /* LHPF2_MODE */ 4598*4882a593Smuzhiyun #define WM5100_LHPF2_MODE_WIDTH 1 /* LHPF2_MODE */ 4599*4882a593Smuzhiyun #define WM5100_LHPF2_ENA 0x0001 /* LHPF2_ENA */ 4600*4882a593Smuzhiyun #define WM5100_LHPF2_ENA_MASK 0x0001 /* LHPF2_ENA */ 4601*4882a593Smuzhiyun #define WM5100_LHPF2_ENA_SHIFT 0 /* LHPF2_ENA */ 4602*4882a593Smuzhiyun #define WM5100_LHPF2_ENA_WIDTH 1 /* LHPF2_ENA */ 4603*4882a593Smuzhiyun 4604*4882a593Smuzhiyun /* 4605*4882a593Smuzhiyun * R3781 (0xEC5) - HPLPF2_2 4606*4882a593Smuzhiyun */ 4607*4882a593Smuzhiyun #define WM5100_LHPF2_COEFF_MASK 0xFFFF /* LHPF2_COEFF - [15:0] */ 4608*4882a593Smuzhiyun #define WM5100_LHPF2_COEFF_SHIFT 0 /* LHPF2_COEFF - [15:0] */ 4609*4882a593Smuzhiyun #define WM5100_LHPF2_COEFF_WIDTH 16 /* LHPF2_COEFF - [15:0] */ 4610*4882a593Smuzhiyun 4611*4882a593Smuzhiyun /* 4612*4882a593Smuzhiyun * R3784 (0xEC8) - HPLPF3_1 4613*4882a593Smuzhiyun */ 4614*4882a593Smuzhiyun #define WM5100_LHPF3_MODE 0x0002 /* LHPF3_MODE */ 4615*4882a593Smuzhiyun #define WM5100_LHPF3_MODE_MASK 0x0002 /* LHPF3_MODE */ 4616*4882a593Smuzhiyun #define WM5100_LHPF3_MODE_SHIFT 1 /* LHPF3_MODE */ 4617*4882a593Smuzhiyun #define WM5100_LHPF3_MODE_WIDTH 1 /* LHPF3_MODE */ 4618*4882a593Smuzhiyun #define WM5100_LHPF3_ENA 0x0001 /* LHPF3_ENA */ 4619*4882a593Smuzhiyun #define WM5100_LHPF3_ENA_MASK 0x0001 /* LHPF3_ENA */ 4620*4882a593Smuzhiyun #define WM5100_LHPF3_ENA_SHIFT 0 /* LHPF3_ENA */ 4621*4882a593Smuzhiyun #define WM5100_LHPF3_ENA_WIDTH 1 /* LHPF3_ENA */ 4622*4882a593Smuzhiyun 4623*4882a593Smuzhiyun /* 4624*4882a593Smuzhiyun * R3785 (0xEC9) - HPLPF3_2 4625*4882a593Smuzhiyun */ 4626*4882a593Smuzhiyun #define WM5100_LHPF3_COEFF_MASK 0xFFFF /* LHPF3_COEFF - [15:0] */ 4627*4882a593Smuzhiyun #define WM5100_LHPF3_COEFF_SHIFT 0 /* LHPF3_COEFF - [15:0] */ 4628*4882a593Smuzhiyun #define WM5100_LHPF3_COEFF_WIDTH 16 /* LHPF3_COEFF - [15:0] */ 4629*4882a593Smuzhiyun 4630*4882a593Smuzhiyun /* 4631*4882a593Smuzhiyun * R3788 (0xECC) - HPLPF4_1 4632*4882a593Smuzhiyun */ 4633*4882a593Smuzhiyun #define WM5100_LHPF4_MODE 0x0002 /* LHPF4_MODE */ 4634*4882a593Smuzhiyun #define WM5100_LHPF4_MODE_MASK 0x0002 /* LHPF4_MODE */ 4635*4882a593Smuzhiyun #define WM5100_LHPF4_MODE_SHIFT 1 /* LHPF4_MODE */ 4636*4882a593Smuzhiyun #define WM5100_LHPF4_MODE_WIDTH 1 /* LHPF4_MODE */ 4637*4882a593Smuzhiyun #define WM5100_LHPF4_ENA 0x0001 /* LHPF4_ENA */ 4638*4882a593Smuzhiyun #define WM5100_LHPF4_ENA_MASK 0x0001 /* LHPF4_ENA */ 4639*4882a593Smuzhiyun #define WM5100_LHPF4_ENA_SHIFT 0 /* LHPF4_ENA */ 4640*4882a593Smuzhiyun #define WM5100_LHPF4_ENA_WIDTH 1 /* LHPF4_ENA */ 4641*4882a593Smuzhiyun 4642*4882a593Smuzhiyun /* 4643*4882a593Smuzhiyun * R3789 (0xECD) - HPLPF4_2 4644*4882a593Smuzhiyun */ 4645*4882a593Smuzhiyun #define WM5100_LHPF4_COEFF_MASK 0xFFFF /* LHPF4_COEFF - [15:0] */ 4646*4882a593Smuzhiyun #define WM5100_LHPF4_COEFF_SHIFT 0 /* LHPF4_COEFF - [15:0] */ 4647*4882a593Smuzhiyun #define WM5100_LHPF4_COEFF_WIDTH 16 /* LHPF4_COEFF - [15:0] */ 4648*4882a593Smuzhiyun 4649*4882a593Smuzhiyun /* 4650*4882a593Smuzhiyun * R4132 (0x1024) - DSP2 Control 30 4651*4882a593Smuzhiyun */ 4652*4882a593Smuzhiyun #define WM5100_DSP2_RATE_MASK 0xC000 /* DSP2_RATE - [15:14] */ 4653*4882a593Smuzhiyun #define WM5100_DSP2_RATE_SHIFT 14 /* DSP2_RATE - [15:14] */ 4654*4882a593Smuzhiyun #define WM5100_DSP2_RATE_WIDTH 2 /* DSP2_RATE - [15:14] */ 4655*4882a593Smuzhiyun #define WM5100_DSP2_DBG_CLK_ENA 0x0008 /* DSP2_DBG_CLK_ENA */ 4656*4882a593Smuzhiyun #define WM5100_DSP2_DBG_CLK_ENA_MASK 0x0008 /* DSP2_DBG_CLK_ENA */ 4657*4882a593Smuzhiyun #define WM5100_DSP2_DBG_CLK_ENA_SHIFT 3 /* DSP2_DBG_CLK_ENA */ 4658*4882a593Smuzhiyun #define WM5100_DSP2_DBG_CLK_ENA_WIDTH 1 /* DSP2_DBG_CLK_ENA */ 4659*4882a593Smuzhiyun #define WM5100_DSP2_SYS_ENA 0x0004 /* DSP2_SYS_ENA */ 4660*4882a593Smuzhiyun #define WM5100_DSP2_SYS_ENA_MASK 0x0004 /* DSP2_SYS_ENA */ 4661*4882a593Smuzhiyun #define WM5100_DSP2_SYS_ENA_SHIFT 2 /* DSP2_SYS_ENA */ 4662*4882a593Smuzhiyun #define WM5100_DSP2_SYS_ENA_WIDTH 1 /* DSP2_SYS_ENA */ 4663*4882a593Smuzhiyun #define WM5100_DSP2_CORE_ENA 0x0002 /* DSP2_CORE_ENA */ 4664*4882a593Smuzhiyun #define WM5100_DSP2_CORE_ENA_MASK 0x0002 /* DSP2_CORE_ENA */ 4665*4882a593Smuzhiyun #define WM5100_DSP2_CORE_ENA_SHIFT 1 /* DSP2_CORE_ENA */ 4666*4882a593Smuzhiyun #define WM5100_DSP2_CORE_ENA_WIDTH 1 /* DSP2_CORE_ENA */ 4667*4882a593Smuzhiyun #define WM5100_DSP2_START 0x0001 /* DSP2_START */ 4668*4882a593Smuzhiyun #define WM5100_DSP2_START_MASK 0x0001 /* DSP2_START */ 4669*4882a593Smuzhiyun #define WM5100_DSP2_START_SHIFT 0 /* DSP2_START */ 4670*4882a593Smuzhiyun #define WM5100_DSP2_START_WIDTH 1 /* DSP2_START */ 4671*4882a593Smuzhiyun 4672*4882a593Smuzhiyun /* 4673*4882a593Smuzhiyun * R3876 (0xF24) - DSP1 Control 30 4674*4882a593Smuzhiyun */ 4675*4882a593Smuzhiyun #define WM5100_DSP1_RATE_MASK 0xC000 /* DSP1_RATE - [15:14] */ 4676*4882a593Smuzhiyun #define WM5100_DSP1_RATE_SHIFT 14 /* DSP1_RATE - [15:14] */ 4677*4882a593Smuzhiyun #define WM5100_DSP1_RATE_WIDTH 2 /* DSP1_RATE - [15:14] */ 4678*4882a593Smuzhiyun #define WM5100_DSP1_DBG_CLK_ENA 0x0008 /* DSP1_DBG_CLK_ENA */ 4679*4882a593Smuzhiyun #define WM5100_DSP1_DBG_CLK_ENA_MASK 0x0008 /* DSP1_DBG_CLK_ENA */ 4680*4882a593Smuzhiyun #define WM5100_DSP1_DBG_CLK_ENA_SHIFT 3 /* DSP1_DBG_CLK_ENA */ 4681*4882a593Smuzhiyun #define WM5100_DSP1_DBG_CLK_ENA_WIDTH 1 /* DSP1_DBG_CLK_ENA */ 4682*4882a593Smuzhiyun #define WM5100_DSP1_SYS_ENA 0x0004 /* DSP1_SYS_ENA */ 4683*4882a593Smuzhiyun #define WM5100_DSP1_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */ 4684*4882a593Smuzhiyun #define WM5100_DSP1_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */ 4685*4882a593Smuzhiyun #define WM5100_DSP1_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */ 4686*4882a593Smuzhiyun #define WM5100_DSP1_CORE_ENA 0x0002 /* DSP1_CORE_ENA */ 4687*4882a593Smuzhiyun #define WM5100_DSP1_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */ 4688*4882a593Smuzhiyun #define WM5100_DSP1_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */ 4689*4882a593Smuzhiyun #define WM5100_DSP1_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */ 4690*4882a593Smuzhiyun #define WM5100_DSP1_START 0x0001 /* DSP1_START */ 4691*4882a593Smuzhiyun #define WM5100_DSP1_START_MASK 0x0001 /* DSP1_START */ 4692*4882a593Smuzhiyun #define WM5100_DSP1_START_SHIFT 0 /* DSP1_START */ 4693*4882a593Smuzhiyun #define WM5100_DSP1_START_WIDTH 1 /* DSP1_START */ 4694*4882a593Smuzhiyun 4695*4882a593Smuzhiyun /* 4696*4882a593Smuzhiyun * R4388 (0x1124) - DSP3 Control 30 4697*4882a593Smuzhiyun */ 4698*4882a593Smuzhiyun #define WM5100_DSP3_RATE_MASK 0xC000 /* DSP3_RATE - [15:14] */ 4699*4882a593Smuzhiyun #define WM5100_DSP3_RATE_SHIFT 14 /* DSP3_RATE - [15:14] */ 4700*4882a593Smuzhiyun #define WM5100_DSP3_RATE_WIDTH 2 /* DSP3_RATE - [15:14] */ 4701*4882a593Smuzhiyun #define WM5100_DSP3_DBG_CLK_ENA 0x0008 /* DSP3_DBG_CLK_ENA */ 4702*4882a593Smuzhiyun #define WM5100_DSP3_DBG_CLK_ENA_MASK 0x0008 /* DSP3_DBG_CLK_ENA */ 4703*4882a593Smuzhiyun #define WM5100_DSP3_DBG_CLK_ENA_SHIFT 3 /* DSP3_DBG_CLK_ENA */ 4704*4882a593Smuzhiyun #define WM5100_DSP3_DBG_CLK_ENA_WIDTH 1 /* DSP3_DBG_CLK_ENA */ 4705*4882a593Smuzhiyun #define WM5100_DSP3_SYS_ENA 0x0004 /* DSP3_SYS_ENA */ 4706*4882a593Smuzhiyun #define WM5100_DSP3_SYS_ENA_MASK 0x0004 /* DSP3_SYS_ENA */ 4707*4882a593Smuzhiyun #define WM5100_DSP3_SYS_ENA_SHIFT 2 /* DSP3_SYS_ENA */ 4708*4882a593Smuzhiyun #define WM5100_DSP3_SYS_ENA_WIDTH 1 /* DSP3_SYS_ENA */ 4709*4882a593Smuzhiyun #define WM5100_DSP3_CORE_ENA 0x0002 /* DSP3_CORE_ENA */ 4710*4882a593Smuzhiyun #define WM5100_DSP3_CORE_ENA_MASK 0x0002 /* DSP3_CORE_ENA */ 4711*4882a593Smuzhiyun #define WM5100_DSP3_CORE_ENA_SHIFT 1 /* DSP3_CORE_ENA */ 4712*4882a593Smuzhiyun #define WM5100_DSP3_CORE_ENA_WIDTH 1 /* DSP3_CORE_ENA */ 4713*4882a593Smuzhiyun #define WM5100_DSP3_START 0x0001 /* DSP3_START */ 4714*4882a593Smuzhiyun #define WM5100_DSP3_START_MASK 0x0001 /* DSP3_START */ 4715*4882a593Smuzhiyun #define WM5100_DSP3_START_SHIFT 0 /* DSP3_START */ 4716*4882a593Smuzhiyun #define WM5100_DSP3_START_WIDTH 1 /* DSP3_START */ 4717*4882a593Smuzhiyun 4718*4882a593Smuzhiyun /* 4719*4882a593Smuzhiyun * R16384 (0x4000) - DSP1 DM 0 4720*4882a593Smuzhiyun */ 4721*4882a593Smuzhiyun #define WM5100_DSP1_DM_START_1_MASK 0x00FF /* DSP1_DM_START - [7:0] */ 4722*4882a593Smuzhiyun #define WM5100_DSP1_DM_START_1_SHIFT 0 /* DSP1_DM_START - [7:0] */ 4723*4882a593Smuzhiyun #define WM5100_DSP1_DM_START_1_WIDTH 8 /* DSP1_DM_START - [7:0] */ 4724*4882a593Smuzhiyun 4725*4882a593Smuzhiyun /* 4726*4882a593Smuzhiyun * R16385 (0x4001) - DSP1 DM 1 4727*4882a593Smuzhiyun */ 4728*4882a593Smuzhiyun #define WM5100_DSP1_DM_START_MASK 0xFFFF /* DSP1_DM_START - [15:0] */ 4729*4882a593Smuzhiyun #define WM5100_DSP1_DM_START_SHIFT 0 /* DSP1_DM_START - [15:0] */ 4730*4882a593Smuzhiyun #define WM5100_DSP1_DM_START_WIDTH 16 /* DSP1_DM_START - [15:0] */ 4731*4882a593Smuzhiyun 4732*4882a593Smuzhiyun /* 4733*4882a593Smuzhiyun * R16386 (0x4002) - DSP1 DM 2 4734*4882a593Smuzhiyun */ 4735*4882a593Smuzhiyun #define WM5100_DSP1_DM_1_1_MASK 0x00FF /* DSP1_DM_1 - [7:0] */ 4736*4882a593Smuzhiyun #define WM5100_DSP1_DM_1_1_SHIFT 0 /* DSP1_DM_1 - [7:0] */ 4737*4882a593Smuzhiyun #define WM5100_DSP1_DM_1_1_WIDTH 8 /* DSP1_DM_1 - [7:0] */ 4738*4882a593Smuzhiyun 4739*4882a593Smuzhiyun /* 4740*4882a593Smuzhiyun * R16387 (0x4003) - DSP1 DM 3 4741*4882a593Smuzhiyun */ 4742*4882a593Smuzhiyun #define WM5100_DSP1_DM_1_MASK 0xFFFF /* DSP1_DM_1 - [15:0] */ 4743*4882a593Smuzhiyun #define WM5100_DSP1_DM_1_SHIFT 0 /* DSP1_DM_1 - [15:0] */ 4744*4882a593Smuzhiyun #define WM5100_DSP1_DM_1_WIDTH 16 /* DSP1_DM_1 - [15:0] */ 4745*4882a593Smuzhiyun 4746*4882a593Smuzhiyun /* 4747*4882a593Smuzhiyun * R16892 (0x41FC) - DSP1 DM 508 4748*4882a593Smuzhiyun */ 4749*4882a593Smuzhiyun #define WM5100_DSP1_DM_254_1_MASK 0x00FF /* DSP1_DM_254 - [7:0] */ 4750*4882a593Smuzhiyun #define WM5100_DSP1_DM_254_1_SHIFT 0 /* DSP1_DM_254 - [7:0] */ 4751*4882a593Smuzhiyun #define WM5100_DSP1_DM_254_1_WIDTH 8 /* DSP1_DM_254 - [7:0] */ 4752*4882a593Smuzhiyun 4753*4882a593Smuzhiyun /* 4754*4882a593Smuzhiyun * R16893 (0x41FD) - DSP1 DM 509 4755*4882a593Smuzhiyun */ 4756*4882a593Smuzhiyun #define WM5100_DSP1_DM_254_MASK 0xFFFF /* DSP1_DM_254 - [15:0] */ 4757*4882a593Smuzhiyun #define WM5100_DSP1_DM_254_SHIFT 0 /* DSP1_DM_254 - [15:0] */ 4758*4882a593Smuzhiyun #define WM5100_DSP1_DM_254_WIDTH 16 /* DSP1_DM_254 - [15:0] */ 4759*4882a593Smuzhiyun 4760*4882a593Smuzhiyun /* 4761*4882a593Smuzhiyun * R16894 (0x41FE) - DSP1 DM 510 4762*4882a593Smuzhiyun */ 4763*4882a593Smuzhiyun #define WM5100_DSP1_DM_END_1_MASK 0x00FF /* DSP1_DM_END - [7:0] */ 4764*4882a593Smuzhiyun #define WM5100_DSP1_DM_END_1_SHIFT 0 /* DSP1_DM_END - [7:0] */ 4765*4882a593Smuzhiyun #define WM5100_DSP1_DM_END_1_WIDTH 8 /* DSP1_DM_END - [7:0] */ 4766*4882a593Smuzhiyun 4767*4882a593Smuzhiyun /* 4768*4882a593Smuzhiyun * R16895 (0x41FF) - DSP1 DM 511 4769*4882a593Smuzhiyun */ 4770*4882a593Smuzhiyun #define WM5100_DSP1_DM_END_MASK 0xFFFF /* DSP1_DM_END - [15:0] */ 4771*4882a593Smuzhiyun #define WM5100_DSP1_DM_END_SHIFT 0 /* DSP1_DM_END - [15:0] */ 4772*4882a593Smuzhiyun #define WM5100_DSP1_DM_END_WIDTH 16 /* DSP1_DM_END - [15:0] */ 4773*4882a593Smuzhiyun 4774*4882a593Smuzhiyun /* 4775*4882a593Smuzhiyun * R18432 (0x4800) - DSP1 PM 0 4776*4882a593Smuzhiyun */ 4777*4882a593Smuzhiyun #define WM5100_DSP1_PM_START_2_MASK 0x00FF /* DSP1_PM_START - [7:0] */ 4778*4882a593Smuzhiyun #define WM5100_DSP1_PM_START_2_SHIFT 0 /* DSP1_PM_START - [7:0] */ 4779*4882a593Smuzhiyun #define WM5100_DSP1_PM_START_2_WIDTH 8 /* DSP1_PM_START - [7:0] */ 4780*4882a593Smuzhiyun 4781*4882a593Smuzhiyun /* 4782*4882a593Smuzhiyun * R18433 (0x4801) - DSP1 PM 1 4783*4882a593Smuzhiyun */ 4784*4882a593Smuzhiyun #define WM5100_DSP1_PM_START_1_MASK 0xFFFF /* DSP1_PM_START - [15:0] */ 4785*4882a593Smuzhiyun #define WM5100_DSP1_PM_START_1_SHIFT 0 /* DSP1_PM_START - [15:0] */ 4786*4882a593Smuzhiyun #define WM5100_DSP1_PM_START_1_WIDTH 16 /* DSP1_PM_START - [15:0] */ 4787*4882a593Smuzhiyun 4788*4882a593Smuzhiyun /* 4789*4882a593Smuzhiyun * R18434 (0x4802) - DSP1 PM 2 4790*4882a593Smuzhiyun */ 4791*4882a593Smuzhiyun #define WM5100_DSP1_PM_START_MASK 0xFFFF /* DSP1_PM_START - [15:0] */ 4792*4882a593Smuzhiyun #define WM5100_DSP1_PM_START_SHIFT 0 /* DSP1_PM_START - [15:0] */ 4793*4882a593Smuzhiyun #define WM5100_DSP1_PM_START_WIDTH 16 /* DSP1_PM_START - [15:0] */ 4794*4882a593Smuzhiyun 4795*4882a593Smuzhiyun /* 4796*4882a593Smuzhiyun * R18435 (0x4803) - DSP1 PM 3 4797*4882a593Smuzhiyun */ 4798*4882a593Smuzhiyun #define WM5100_DSP1_PM_1_2_MASK 0x00FF /* DSP1_PM_1 - [7:0] */ 4799*4882a593Smuzhiyun #define WM5100_DSP1_PM_1_2_SHIFT 0 /* DSP1_PM_1 - [7:0] */ 4800*4882a593Smuzhiyun #define WM5100_DSP1_PM_1_2_WIDTH 8 /* DSP1_PM_1 - [7:0] */ 4801*4882a593Smuzhiyun 4802*4882a593Smuzhiyun /* 4803*4882a593Smuzhiyun * R18436 (0x4804) - DSP1 PM 4 4804*4882a593Smuzhiyun */ 4805*4882a593Smuzhiyun #define WM5100_DSP1_PM_1_1_MASK 0xFFFF /* DSP1_PM_1 - [15:0] */ 4806*4882a593Smuzhiyun #define WM5100_DSP1_PM_1_1_SHIFT 0 /* DSP1_PM_1 - [15:0] */ 4807*4882a593Smuzhiyun #define WM5100_DSP1_PM_1_1_WIDTH 16 /* DSP1_PM_1 - [15:0] */ 4808*4882a593Smuzhiyun 4809*4882a593Smuzhiyun /* 4810*4882a593Smuzhiyun * R18437 (0x4805) - DSP1 PM 5 4811*4882a593Smuzhiyun */ 4812*4882a593Smuzhiyun #define WM5100_DSP1_PM_1_MASK 0xFFFF /* DSP1_PM_1 - [15:0] */ 4813*4882a593Smuzhiyun #define WM5100_DSP1_PM_1_SHIFT 0 /* DSP1_PM_1 - [15:0] */ 4814*4882a593Smuzhiyun #define WM5100_DSP1_PM_1_WIDTH 16 /* DSP1_PM_1 - [15:0] */ 4815*4882a593Smuzhiyun 4816*4882a593Smuzhiyun /* 4817*4882a593Smuzhiyun * R19962 (0x4DFA) - DSP1 PM 1530 4818*4882a593Smuzhiyun */ 4819*4882a593Smuzhiyun #define WM5100_DSP1_PM_510_2_MASK 0x00FF /* DSP1_PM_510 - [7:0] */ 4820*4882a593Smuzhiyun #define WM5100_DSP1_PM_510_2_SHIFT 0 /* DSP1_PM_510 - [7:0] */ 4821*4882a593Smuzhiyun #define WM5100_DSP1_PM_510_2_WIDTH 8 /* DSP1_PM_510 - [7:0] */ 4822*4882a593Smuzhiyun 4823*4882a593Smuzhiyun /* 4824*4882a593Smuzhiyun * R19963 (0x4DFB) - DSP1 PM 1531 4825*4882a593Smuzhiyun */ 4826*4882a593Smuzhiyun #define WM5100_DSP1_PM_510_1_MASK 0xFFFF /* DSP1_PM_510 - [15:0] */ 4827*4882a593Smuzhiyun #define WM5100_DSP1_PM_510_1_SHIFT 0 /* DSP1_PM_510 - [15:0] */ 4828*4882a593Smuzhiyun #define WM5100_DSP1_PM_510_1_WIDTH 16 /* DSP1_PM_510 - [15:0] */ 4829*4882a593Smuzhiyun 4830*4882a593Smuzhiyun /* 4831*4882a593Smuzhiyun * R19964 (0x4DFC) - DSP1 PM 1532 4832*4882a593Smuzhiyun */ 4833*4882a593Smuzhiyun #define WM5100_DSP1_PM_510_MASK 0xFFFF /* DSP1_PM_510 - [15:0] */ 4834*4882a593Smuzhiyun #define WM5100_DSP1_PM_510_SHIFT 0 /* DSP1_PM_510 - [15:0] */ 4835*4882a593Smuzhiyun #define WM5100_DSP1_PM_510_WIDTH 16 /* DSP1_PM_510 - [15:0] */ 4836*4882a593Smuzhiyun 4837*4882a593Smuzhiyun /* 4838*4882a593Smuzhiyun * R19965 (0x4DFD) - DSP1 PM 1533 4839*4882a593Smuzhiyun */ 4840*4882a593Smuzhiyun #define WM5100_DSP1_PM_END_2_MASK 0x00FF /* DSP1_PM_END - [7:0] */ 4841*4882a593Smuzhiyun #define WM5100_DSP1_PM_END_2_SHIFT 0 /* DSP1_PM_END - [7:0] */ 4842*4882a593Smuzhiyun #define WM5100_DSP1_PM_END_2_WIDTH 8 /* DSP1_PM_END - [7:0] */ 4843*4882a593Smuzhiyun 4844*4882a593Smuzhiyun /* 4845*4882a593Smuzhiyun * R19966 (0x4DFE) - DSP1 PM 1534 4846*4882a593Smuzhiyun */ 4847*4882a593Smuzhiyun #define WM5100_DSP1_PM_END_1_MASK 0xFFFF /* DSP1_PM_END - [15:0] */ 4848*4882a593Smuzhiyun #define WM5100_DSP1_PM_END_1_SHIFT 0 /* DSP1_PM_END - [15:0] */ 4849*4882a593Smuzhiyun #define WM5100_DSP1_PM_END_1_WIDTH 16 /* DSP1_PM_END - [15:0] */ 4850*4882a593Smuzhiyun 4851*4882a593Smuzhiyun /* 4852*4882a593Smuzhiyun * R19967 (0x4DFF) - DSP1 PM 1535 4853*4882a593Smuzhiyun */ 4854*4882a593Smuzhiyun #define WM5100_DSP1_PM_END_MASK 0xFFFF /* DSP1_PM_END - [15:0] */ 4855*4882a593Smuzhiyun #define WM5100_DSP1_PM_END_SHIFT 0 /* DSP1_PM_END - [15:0] */ 4856*4882a593Smuzhiyun #define WM5100_DSP1_PM_END_WIDTH 16 /* DSP1_PM_END - [15:0] */ 4857*4882a593Smuzhiyun 4858*4882a593Smuzhiyun /* 4859*4882a593Smuzhiyun * R20480 (0x5000) - DSP1 ZM 0 4860*4882a593Smuzhiyun */ 4861*4882a593Smuzhiyun #define WM5100_DSP1_ZM_START_1_MASK 0x00FF /* DSP1_ZM_START - [7:0] */ 4862*4882a593Smuzhiyun #define WM5100_DSP1_ZM_START_1_SHIFT 0 /* DSP1_ZM_START - [7:0] */ 4863*4882a593Smuzhiyun #define WM5100_DSP1_ZM_START_1_WIDTH 8 /* DSP1_ZM_START - [7:0] */ 4864*4882a593Smuzhiyun 4865*4882a593Smuzhiyun /* 4866*4882a593Smuzhiyun * R20481 (0x5001) - DSP1 ZM 1 4867*4882a593Smuzhiyun */ 4868*4882a593Smuzhiyun #define WM5100_DSP1_ZM_START_MASK 0xFFFF /* DSP1_ZM_START - [15:0] */ 4869*4882a593Smuzhiyun #define WM5100_DSP1_ZM_START_SHIFT 0 /* DSP1_ZM_START - [15:0] */ 4870*4882a593Smuzhiyun #define WM5100_DSP1_ZM_START_WIDTH 16 /* DSP1_ZM_START - [15:0] */ 4871*4882a593Smuzhiyun 4872*4882a593Smuzhiyun /* 4873*4882a593Smuzhiyun * R20482 (0x5002) - DSP1 ZM 2 4874*4882a593Smuzhiyun */ 4875*4882a593Smuzhiyun #define WM5100_DSP1_ZM_1_1_MASK 0x00FF /* DSP1_ZM_1 - [7:0] */ 4876*4882a593Smuzhiyun #define WM5100_DSP1_ZM_1_1_SHIFT 0 /* DSP1_ZM_1 - [7:0] */ 4877*4882a593Smuzhiyun #define WM5100_DSP1_ZM_1_1_WIDTH 8 /* DSP1_ZM_1 - [7:0] */ 4878*4882a593Smuzhiyun 4879*4882a593Smuzhiyun /* 4880*4882a593Smuzhiyun * R20483 (0x5003) - DSP1 ZM 3 4881*4882a593Smuzhiyun */ 4882*4882a593Smuzhiyun #define WM5100_DSP1_ZM_1_MASK 0xFFFF /* DSP1_ZM_1 - [15:0] */ 4883*4882a593Smuzhiyun #define WM5100_DSP1_ZM_1_SHIFT 0 /* DSP1_ZM_1 - [15:0] */ 4884*4882a593Smuzhiyun #define WM5100_DSP1_ZM_1_WIDTH 16 /* DSP1_ZM_1 - [15:0] */ 4885*4882a593Smuzhiyun 4886*4882a593Smuzhiyun /* 4887*4882a593Smuzhiyun * R22524 (0x57FC) - DSP1 ZM 2044 4888*4882a593Smuzhiyun */ 4889*4882a593Smuzhiyun #define WM5100_DSP1_ZM_1022_1_MASK 0x00FF /* DSP1_ZM_1022 - [7:0] */ 4890*4882a593Smuzhiyun #define WM5100_DSP1_ZM_1022_1_SHIFT 0 /* DSP1_ZM_1022 - [7:0] */ 4891*4882a593Smuzhiyun #define WM5100_DSP1_ZM_1022_1_WIDTH 8 /* DSP1_ZM_1022 - [7:0] */ 4892*4882a593Smuzhiyun 4893*4882a593Smuzhiyun /* 4894*4882a593Smuzhiyun * R22525 (0x57FD) - DSP1 ZM 2045 4895*4882a593Smuzhiyun */ 4896*4882a593Smuzhiyun #define WM5100_DSP1_ZM_1022_MASK 0xFFFF /* DSP1_ZM_1022 - [15:0] */ 4897*4882a593Smuzhiyun #define WM5100_DSP1_ZM_1022_SHIFT 0 /* DSP1_ZM_1022 - [15:0] */ 4898*4882a593Smuzhiyun #define WM5100_DSP1_ZM_1022_WIDTH 16 /* DSP1_ZM_1022 - [15:0] */ 4899*4882a593Smuzhiyun 4900*4882a593Smuzhiyun /* 4901*4882a593Smuzhiyun * R22526 (0x57FE) - DSP1 ZM 2046 4902*4882a593Smuzhiyun */ 4903*4882a593Smuzhiyun #define WM5100_DSP1_ZM_END_1_MASK 0x00FF /* DSP1_ZM_END - [7:0] */ 4904*4882a593Smuzhiyun #define WM5100_DSP1_ZM_END_1_SHIFT 0 /* DSP1_ZM_END - [7:0] */ 4905*4882a593Smuzhiyun #define WM5100_DSP1_ZM_END_1_WIDTH 8 /* DSP1_ZM_END - [7:0] */ 4906*4882a593Smuzhiyun 4907*4882a593Smuzhiyun /* 4908*4882a593Smuzhiyun * R22527 (0x57FF) - DSP1 ZM 2047 4909*4882a593Smuzhiyun */ 4910*4882a593Smuzhiyun #define WM5100_DSP1_ZM_END_MASK 0xFFFF /* DSP1_ZM_END - [15:0] */ 4911*4882a593Smuzhiyun #define WM5100_DSP1_ZM_END_SHIFT 0 /* DSP1_ZM_END - [15:0] */ 4912*4882a593Smuzhiyun #define WM5100_DSP1_ZM_END_WIDTH 16 /* DSP1_ZM_END - [15:0] */ 4913*4882a593Smuzhiyun 4914*4882a593Smuzhiyun /* 4915*4882a593Smuzhiyun * R24576 (0x6000) - DSP2 DM 0 4916*4882a593Smuzhiyun */ 4917*4882a593Smuzhiyun #define WM5100_DSP2_DM_START_1_MASK 0x00FF /* DSP2_DM_START - [7:0] */ 4918*4882a593Smuzhiyun #define WM5100_DSP2_DM_START_1_SHIFT 0 /* DSP2_DM_START - [7:0] */ 4919*4882a593Smuzhiyun #define WM5100_DSP2_DM_START_1_WIDTH 8 /* DSP2_DM_START - [7:0] */ 4920*4882a593Smuzhiyun 4921*4882a593Smuzhiyun /* 4922*4882a593Smuzhiyun * R24577 (0x6001) - DSP2 DM 1 4923*4882a593Smuzhiyun */ 4924*4882a593Smuzhiyun #define WM5100_DSP2_DM_START_MASK 0xFFFF /* DSP2_DM_START - [15:0] */ 4925*4882a593Smuzhiyun #define WM5100_DSP2_DM_START_SHIFT 0 /* DSP2_DM_START - [15:0] */ 4926*4882a593Smuzhiyun #define WM5100_DSP2_DM_START_WIDTH 16 /* DSP2_DM_START - [15:0] */ 4927*4882a593Smuzhiyun 4928*4882a593Smuzhiyun /* 4929*4882a593Smuzhiyun * R24578 (0x6002) - DSP2 DM 2 4930*4882a593Smuzhiyun */ 4931*4882a593Smuzhiyun #define WM5100_DSP2_DM_1_1_MASK 0x00FF /* DSP2_DM_1 - [7:0] */ 4932*4882a593Smuzhiyun #define WM5100_DSP2_DM_1_1_SHIFT 0 /* DSP2_DM_1 - [7:0] */ 4933*4882a593Smuzhiyun #define WM5100_DSP2_DM_1_1_WIDTH 8 /* DSP2_DM_1 - [7:0] */ 4934*4882a593Smuzhiyun 4935*4882a593Smuzhiyun /* 4936*4882a593Smuzhiyun * R24579 (0x6003) - DSP2 DM 3 4937*4882a593Smuzhiyun */ 4938*4882a593Smuzhiyun #define WM5100_DSP2_DM_1_MASK 0xFFFF /* DSP2_DM_1 - [15:0] */ 4939*4882a593Smuzhiyun #define WM5100_DSP2_DM_1_SHIFT 0 /* DSP2_DM_1 - [15:0] */ 4940*4882a593Smuzhiyun #define WM5100_DSP2_DM_1_WIDTH 16 /* DSP2_DM_1 - [15:0] */ 4941*4882a593Smuzhiyun 4942*4882a593Smuzhiyun /* 4943*4882a593Smuzhiyun * R25084 (0x61FC) - DSP2 DM 508 4944*4882a593Smuzhiyun */ 4945*4882a593Smuzhiyun #define WM5100_DSP2_DM_254_1_MASK 0x00FF /* DSP2_DM_254 - [7:0] */ 4946*4882a593Smuzhiyun #define WM5100_DSP2_DM_254_1_SHIFT 0 /* DSP2_DM_254 - [7:0] */ 4947*4882a593Smuzhiyun #define WM5100_DSP2_DM_254_1_WIDTH 8 /* DSP2_DM_254 - [7:0] */ 4948*4882a593Smuzhiyun 4949*4882a593Smuzhiyun /* 4950*4882a593Smuzhiyun * R25085 (0x61FD) - DSP2 DM 509 4951*4882a593Smuzhiyun */ 4952*4882a593Smuzhiyun #define WM5100_DSP2_DM_254_MASK 0xFFFF /* DSP2_DM_254 - [15:0] */ 4953*4882a593Smuzhiyun #define WM5100_DSP2_DM_254_SHIFT 0 /* DSP2_DM_254 - [15:0] */ 4954*4882a593Smuzhiyun #define WM5100_DSP2_DM_254_WIDTH 16 /* DSP2_DM_254 - [15:0] */ 4955*4882a593Smuzhiyun 4956*4882a593Smuzhiyun /* 4957*4882a593Smuzhiyun * R25086 (0x61FE) - DSP2 DM 510 4958*4882a593Smuzhiyun */ 4959*4882a593Smuzhiyun #define WM5100_DSP2_DM_END_1_MASK 0x00FF /* DSP2_DM_END - [7:0] */ 4960*4882a593Smuzhiyun #define WM5100_DSP2_DM_END_1_SHIFT 0 /* DSP2_DM_END - [7:0] */ 4961*4882a593Smuzhiyun #define WM5100_DSP2_DM_END_1_WIDTH 8 /* DSP2_DM_END - [7:0] */ 4962*4882a593Smuzhiyun 4963*4882a593Smuzhiyun /* 4964*4882a593Smuzhiyun * R25087 (0x61FF) - DSP2 DM 511 4965*4882a593Smuzhiyun */ 4966*4882a593Smuzhiyun #define WM5100_DSP2_DM_END_MASK 0xFFFF /* DSP2_DM_END - [15:0] */ 4967*4882a593Smuzhiyun #define WM5100_DSP2_DM_END_SHIFT 0 /* DSP2_DM_END - [15:0] */ 4968*4882a593Smuzhiyun #define WM5100_DSP2_DM_END_WIDTH 16 /* DSP2_DM_END - [15:0] */ 4969*4882a593Smuzhiyun 4970*4882a593Smuzhiyun /* 4971*4882a593Smuzhiyun * R26624 (0x6800) - DSP2 PM 0 4972*4882a593Smuzhiyun */ 4973*4882a593Smuzhiyun #define WM5100_DSP2_PM_START_2_MASK 0x00FF /* DSP2_PM_START - [7:0] */ 4974*4882a593Smuzhiyun #define WM5100_DSP2_PM_START_2_SHIFT 0 /* DSP2_PM_START - [7:0] */ 4975*4882a593Smuzhiyun #define WM5100_DSP2_PM_START_2_WIDTH 8 /* DSP2_PM_START - [7:0] */ 4976*4882a593Smuzhiyun 4977*4882a593Smuzhiyun /* 4978*4882a593Smuzhiyun * R26625 (0x6801) - DSP2 PM 1 4979*4882a593Smuzhiyun */ 4980*4882a593Smuzhiyun #define WM5100_DSP2_PM_START_1_MASK 0xFFFF /* DSP2_PM_START - [15:0] */ 4981*4882a593Smuzhiyun #define WM5100_DSP2_PM_START_1_SHIFT 0 /* DSP2_PM_START - [15:0] */ 4982*4882a593Smuzhiyun #define WM5100_DSP2_PM_START_1_WIDTH 16 /* DSP2_PM_START - [15:0] */ 4983*4882a593Smuzhiyun 4984*4882a593Smuzhiyun /* 4985*4882a593Smuzhiyun * R26626 (0x6802) - DSP2 PM 2 4986*4882a593Smuzhiyun */ 4987*4882a593Smuzhiyun #define WM5100_DSP2_PM_START_MASK 0xFFFF /* DSP2_PM_START - [15:0] */ 4988*4882a593Smuzhiyun #define WM5100_DSP2_PM_START_SHIFT 0 /* DSP2_PM_START - [15:0] */ 4989*4882a593Smuzhiyun #define WM5100_DSP2_PM_START_WIDTH 16 /* DSP2_PM_START - [15:0] */ 4990*4882a593Smuzhiyun 4991*4882a593Smuzhiyun /* 4992*4882a593Smuzhiyun * R26627 (0x6803) - DSP2 PM 3 4993*4882a593Smuzhiyun */ 4994*4882a593Smuzhiyun #define WM5100_DSP2_PM_1_2_MASK 0x00FF /* DSP2_PM_1 - [7:0] */ 4995*4882a593Smuzhiyun #define WM5100_DSP2_PM_1_2_SHIFT 0 /* DSP2_PM_1 - [7:0] */ 4996*4882a593Smuzhiyun #define WM5100_DSP2_PM_1_2_WIDTH 8 /* DSP2_PM_1 - [7:0] */ 4997*4882a593Smuzhiyun 4998*4882a593Smuzhiyun /* 4999*4882a593Smuzhiyun * R26628 (0x6804) - DSP2 PM 4 5000*4882a593Smuzhiyun */ 5001*4882a593Smuzhiyun #define WM5100_DSP2_PM_1_1_MASK 0xFFFF /* DSP2_PM_1 - [15:0] */ 5002*4882a593Smuzhiyun #define WM5100_DSP2_PM_1_1_SHIFT 0 /* DSP2_PM_1 - [15:0] */ 5003*4882a593Smuzhiyun #define WM5100_DSP2_PM_1_1_WIDTH 16 /* DSP2_PM_1 - [15:0] */ 5004*4882a593Smuzhiyun 5005*4882a593Smuzhiyun /* 5006*4882a593Smuzhiyun * R26629 (0x6805) - DSP2 PM 5 5007*4882a593Smuzhiyun */ 5008*4882a593Smuzhiyun #define WM5100_DSP2_PM_1_MASK 0xFFFF /* DSP2_PM_1 - [15:0] */ 5009*4882a593Smuzhiyun #define WM5100_DSP2_PM_1_SHIFT 0 /* DSP2_PM_1 - [15:0] */ 5010*4882a593Smuzhiyun #define WM5100_DSP2_PM_1_WIDTH 16 /* DSP2_PM_1 - [15:0] */ 5011*4882a593Smuzhiyun 5012*4882a593Smuzhiyun /* 5013*4882a593Smuzhiyun * R28154 (0x6DFA) - DSP2 PM 1530 5014*4882a593Smuzhiyun */ 5015*4882a593Smuzhiyun #define WM5100_DSP2_PM_510_2_MASK 0x00FF /* DSP2_PM_510 - [7:0] */ 5016*4882a593Smuzhiyun #define WM5100_DSP2_PM_510_2_SHIFT 0 /* DSP2_PM_510 - [7:0] */ 5017*4882a593Smuzhiyun #define WM5100_DSP2_PM_510_2_WIDTH 8 /* DSP2_PM_510 - [7:0] */ 5018*4882a593Smuzhiyun 5019*4882a593Smuzhiyun /* 5020*4882a593Smuzhiyun * R28155 (0x6DFB) - DSP2 PM 1531 5021*4882a593Smuzhiyun */ 5022*4882a593Smuzhiyun #define WM5100_DSP2_PM_510_1_MASK 0xFFFF /* DSP2_PM_510 - [15:0] */ 5023*4882a593Smuzhiyun #define WM5100_DSP2_PM_510_1_SHIFT 0 /* DSP2_PM_510 - [15:0] */ 5024*4882a593Smuzhiyun #define WM5100_DSP2_PM_510_1_WIDTH 16 /* DSP2_PM_510 - [15:0] */ 5025*4882a593Smuzhiyun 5026*4882a593Smuzhiyun /* 5027*4882a593Smuzhiyun * R28156 (0x6DFC) - DSP2 PM 1532 5028*4882a593Smuzhiyun */ 5029*4882a593Smuzhiyun #define WM5100_DSP2_PM_510_MASK 0xFFFF /* DSP2_PM_510 - [15:0] */ 5030*4882a593Smuzhiyun #define WM5100_DSP2_PM_510_SHIFT 0 /* DSP2_PM_510 - [15:0] */ 5031*4882a593Smuzhiyun #define WM5100_DSP2_PM_510_WIDTH 16 /* DSP2_PM_510 - [15:0] */ 5032*4882a593Smuzhiyun 5033*4882a593Smuzhiyun /* 5034*4882a593Smuzhiyun * R28157 (0x6DFD) - DSP2 PM 1533 5035*4882a593Smuzhiyun */ 5036*4882a593Smuzhiyun #define WM5100_DSP2_PM_END_2_MASK 0x00FF /* DSP2_PM_END - [7:0] */ 5037*4882a593Smuzhiyun #define WM5100_DSP2_PM_END_2_SHIFT 0 /* DSP2_PM_END - [7:0] */ 5038*4882a593Smuzhiyun #define WM5100_DSP2_PM_END_2_WIDTH 8 /* DSP2_PM_END - [7:0] */ 5039*4882a593Smuzhiyun 5040*4882a593Smuzhiyun /* 5041*4882a593Smuzhiyun * R28158 (0x6DFE) - DSP2 PM 1534 5042*4882a593Smuzhiyun */ 5043*4882a593Smuzhiyun #define WM5100_DSP2_PM_END_1_MASK 0xFFFF /* DSP2_PM_END - [15:0] */ 5044*4882a593Smuzhiyun #define WM5100_DSP2_PM_END_1_SHIFT 0 /* DSP2_PM_END - [15:0] */ 5045*4882a593Smuzhiyun #define WM5100_DSP2_PM_END_1_WIDTH 16 /* DSP2_PM_END - [15:0] */ 5046*4882a593Smuzhiyun 5047*4882a593Smuzhiyun /* 5048*4882a593Smuzhiyun * R28159 (0x6DFF) - DSP2 PM 1535 5049*4882a593Smuzhiyun */ 5050*4882a593Smuzhiyun #define WM5100_DSP2_PM_END_MASK 0xFFFF /* DSP2_PM_END - [15:0] */ 5051*4882a593Smuzhiyun #define WM5100_DSP2_PM_END_SHIFT 0 /* DSP2_PM_END - [15:0] */ 5052*4882a593Smuzhiyun #define WM5100_DSP2_PM_END_WIDTH 16 /* DSP2_PM_END - [15:0] */ 5053*4882a593Smuzhiyun 5054*4882a593Smuzhiyun /* 5055*4882a593Smuzhiyun * R28672 (0x7000) - DSP2 ZM 0 5056*4882a593Smuzhiyun */ 5057*4882a593Smuzhiyun #define WM5100_DSP2_ZM_START_1_MASK 0x00FF /* DSP2_ZM_START - [7:0] */ 5058*4882a593Smuzhiyun #define WM5100_DSP2_ZM_START_1_SHIFT 0 /* DSP2_ZM_START - [7:0] */ 5059*4882a593Smuzhiyun #define WM5100_DSP2_ZM_START_1_WIDTH 8 /* DSP2_ZM_START - [7:0] */ 5060*4882a593Smuzhiyun 5061*4882a593Smuzhiyun /* 5062*4882a593Smuzhiyun * R28673 (0x7001) - DSP2 ZM 1 5063*4882a593Smuzhiyun */ 5064*4882a593Smuzhiyun #define WM5100_DSP2_ZM_START_MASK 0xFFFF /* DSP2_ZM_START - [15:0] */ 5065*4882a593Smuzhiyun #define WM5100_DSP2_ZM_START_SHIFT 0 /* DSP2_ZM_START - [15:0] */ 5066*4882a593Smuzhiyun #define WM5100_DSP2_ZM_START_WIDTH 16 /* DSP2_ZM_START - [15:0] */ 5067*4882a593Smuzhiyun 5068*4882a593Smuzhiyun /* 5069*4882a593Smuzhiyun * R28674 (0x7002) - DSP2 ZM 2 5070*4882a593Smuzhiyun */ 5071*4882a593Smuzhiyun #define WM5100_DSP2_ZM_1_1_MASK 0x00FF /* DSP2_ZM_1 - [7:0] */ 5072*4882a593Smuzhiyun #define WM5100_DSP2_ZM_1_1_SHIFT 0 /* DSP2_ZM_1 - [7:0] */ 5073*4882a593Smuzhiyun #define WM5100_DSP2_ZM_1_1_WIDTH 8 /* DSP2_ZM_1 - [7:0] */ 5074*4882a593Smuzhiyun 5075*4882a593Smuzhiyun /* 5076*4882a593Smuzhiyun * R28675 (0x7003) - DSP2 ZM 3 5077*4882a593Smuzhiyun */ 5078*4882a593Smuzhiyun #define WM5100_DSP2_ZM_1_MASK 0xFFFF /* DSP2_ZM_1 - [15:0] */ 5079*4882a593Smuzhiyun #define WM5100_DSP2_ZM_1_SHIFT 0 /* DSP2_ZM_1 - [15:0] */ 5080*4882a593Smuzhiyun #define WM5100_DSP2_ZM_1_WIDTH 16 /* DSP2_ZM_1 - [15:0] */ 5081*4882a593Smuzhiyun 5082*4882a593Smuzhiyun /* 5083*4882a593Smuzhiyun * R30716 (0x77FC) - DSP2 ZM 2044 5084*4882a593Smuzhiyun */ 5085*4882a593Smuzhiyun #define WM5100_DSP2_ZM_1022_1_MASK 0x00FF /* DSP2_ZM_1022 - [7:0] */ 5086*4882a593Smuzhiyun #define WM5100_DSP2_ZM_1022_1_SHIFT 0 /* DSP2_ZM_1022 - [7:0] */ 5087*4882a593Smuzhiyun #define WM5100_DSP2_ZM_1022_1_WIDTH 8 /* DSP2_ZM_1022 - [7:0] */ 5088*4882a593Smuzhiyun 5089*4882a593Smuzhiyun /* 5090*4882a593Smuzhiyun * R30717 (0x77FD) - DSP2 ZM 2045 5091*4882a593Smuzhiyun */ 5092*4882a593Smuzhiyun #define WM5100_DSP2_ZM_1022_MASK 0xFFFF /* DSP2_ZM_1022 - [15:0] */ 5093*4882a593Smuzhiyun #define WM5100_DSP2_ZM_1022_SHIFT 0 /* DSP2_ZM_1022 - [15:0] */ 5094*4882a593Smuzhiyun #define WM5100_DSP2_ZM_1022_WIDTH 16 /* DSP2_ZM_1022 - [15:0] */ 5095*4882a593Smuzhiyun 5096*4882a593Smuzhiyun /* 5097*4882a593Smuzhiyun * R30718 (0x77FE) - DSP2 ZM 2046 5098*4882a593Smuzhiyun */ 5099*4882a593Smuzhiyun #define WM5100_DSP2_ZM_END_1_MASK 0x00FF /* DSP2_ZM_END - [7:0] */ 5100*4882a593Smuzhiyun #define WM5100_DSP2_ZM_END_1_SHIFT 0 /* DSP2_ZM_END - [7:0] */ 5101*4882a593Smuzhiyun #define WM5100_DSP2_ZM_END_1_WIDTH 8 /* DSP2_ZM_END - [7:0] */ 5102*4882a593Smuzhiyun 5103*4882a593Smuzhiyun /* 5104*4882a593Smuzhiyun * R30719 (0x77FF) - DSP2 ZM 2047 5105*4882a593Smuzhiyun */ 5106*4882a593Smuzhiyun #define WM5100_DSP2_ZM_END_MASK 0xFFFF /* DSP2_ZM_END - [15:0] */ 5107*4882a593Smuzhiyun #define WM5100_DSP2_ZM_END_SHIFT 0 /* DSP2_ZM_END - [15:0] */ 5108*4882a593Smuzhiyun #define WM5100_DSP2_ZM_END_WIDTH 16 /* DSP2_ZM_END - [15:0] */ 5109*4882a593Smuzhiyun 5110*4882a593Smuzhiyun /* 5111*4882a593Smuzhiyun * R32768 (0x8000) - DSP3 DM 0 5112*4882a593Smuzhiyun */ 5113*4882a593Smuzhiyun #define WM5100_DSP3_DM_START_1_MASK 0x00FF /* DSP3_DM_START - [7:0] */ 5114*4882a593Smuzhiyun #define WM5100_DSP3_DM_START_1_SHIFT 0 /* DSP3_DM_START - [7:0] */ 5115*4882a593Smuzhiyun #define WM5100_DSP3_DM_START_1_WIDTH 8 /* DSP3_DM_START - [7:0] */ 5116*4882a593Smuzhiyun 5117*4882a593Smuzhiyun /* 5118*4882a593Smuzhiyun * R32769 (0x8001) - DSP3 DM 1 5119*4882a593Smuzhiyun */ 5120*4882a593Smuzhiyun #define WM5100_DSP3_DM_START_MASK 0xFFFF /* DSP3_DM_START - [15:0] */ 5121*4882a593Smuzhiyun #define WM5100_DSP3_DM_START_SHIFT 0 /* DSP3_DM_START - [15:0] */ 5122*4882a593Smuzhiyun #define WM5100_DSP3_DM_START_WIDTH 16 /* DSP3_DM_START - [15:0] */ 5123*4882a593Smuzhiyun 5124*4882a593Smuzhiyun /* 5125*4882a593Smuzhiyun * R32770 (0x8002) - DSP3 DM 2 5126*4882a593Smuzhiyun */ 5127*4882a593Smuzhiyun #define WM5100_DSP3_DM_1_1_MASK 0x00FF /* DSP3_DM_1 - [7:0] */ 5128*4882a593Smuzhiyun #define WM5100_DSP3_DM_1_1_SHIFT 0 /* DSP3_DM_1 - [7:0] */ 5129*4882a593Smuzhiyun #define WM5100_DSP3_DM_1_1_WIDTH 8 /* DSP3_DM_1 - [7:0] */ 5130*4882a593Smuzhiyun 5131*4882a593Smuzhiyun /* 5132*4882a593Smuzhiyun * R32771 (0x8003) - DSP3 DM 3 5133*4882a593Smuzhiyun */ 5134*4882a593Smuzhiyun #define WM5100_DSP3_DM_1_MASK 0xFFFF /* DSP3_DM_1 - [15:0] */ 5135*4882a593Smuzhiyun #define WM5100_DSP3_DM_1_SHIFT 0 /* DSP3_DM_1 - [15:0] */ 5136*4882a593Smuzhiyun #define WM5100_DSP3_DM_1_WIDTH 16 /* DSP3_DM_1 - [15:0] */ 5137*4882a593Smuzhiyun 5138*4882a593Smuzhiyun /* 5139*4882a593Smuzhiyun * R33276 (0x81FC) - DSP3 DM 508 5140*4882a593Smuzhiyun */ 5141*4882a593Smuzhiyun #define WM5100_DSP3_DM_254_1_MASK 0x00FF /* DSP3_DM_254 - [7:0] */ 5142*4882a593Smuzhiyun #define WM5100_DSP3_DM_254_1_SHIFT 0 /* DSP3_DM_254 - [7:0] */ 5143*4882a593Smuzhiyun #define WM5100_DSP3_DM_254_1_WIDTH 8 /* DSP3_DM_254 - [7:0] */ 5144*4882a593Smuzhiyun 5145*4882a593Smuzhiyun /* 5146*4882a593Smuzhiyun * R33277 (0x81FD) - DSP3 DM 509 5147*4882a593Smuzhiyun */ 5148*4882a593Smuzhiyun #define WM5100_DSP3_DM_254_MASK 0xFFFF /* DSP3_DM_254 - [15:0] */ 5149*4882a593Smuzhiyun #define WM5100_DSP3_DM_254_SHIFT 0 /* DSP3_DM_254 - [15:0] */ 5150*4882a593Smuzhiyun #define WM5100_DSP3_DM_254_WIDTH 16 /* DSP3_DM_254 - [15:0] */ 5151*4882a593Smuzhiyun 5152*4882a593Smuzhiyun /* 5153*4882a593Smuzhiyun * R33278 (0x81FE) - DSP3 DM 510 5154*4882a593Smuzhiyun */ 5155*4882a593Smuzhiyun #define WM5100_DSP3_DM_END_1_MASK 0x00FF /* DSP3_DM_END - [7:0] */ 5156*4882a593Smuzhiyun #define WM5100_DSP3_DM_END_1_SHIFT 0 /* DSP3_DM_END - [7:0] */ 5157*4882a593Smuzhiyun #define WM5100_DSP3_DM_END_1_WIDTH 8 /* DSP3_DM_END - [7:0] */ 5158*4882a593Smuzhiyun 5159*4882a593Smuzhiyun /* 5160*4882a593Smuzhiyun * R33279 (0x81FF) - DSP3 DM 511 5161*4882a593Smuzhiyun */ 5162*4882a593Smuzhiyun #define WM5100_DSP3_DM_END_MASK 0xFFFF /* DSP3_DM_END - [15:0] */ 5163*4882a593Smuzhiyun #define WM5100_DSP3_DM_END_SHIFT 0 /* DSP3_DM_END - [15:0] */ 5164*4882a593Smuzhiyun #define WM5100_DSP3_DM_END_WIDTH 16 /* DSP3_DM_END - [15:0] */ 5165*4882a593Smuzhiyun 5166*4882a593Smuzhiyun /* 5167*4882a593Smuzhiyun * R34816 (0x8800) - DSP3 PM 0 5168*4882a593Smuzhiyun */ 5169*4882a593Smuzhiyun #define WM5100_DSP3_PM_START_2_MASK 0x00FF /* DSP3_PM_START - [7:0] */ 5170*4882a593Smuzhiyun #define WM5100_DSP3_PM_START_2_SHIFT 0 /* DSP3_PM_START - [7:0] */ 5171*4882a593Smuzhiyun #define WM5100_DSP3_PM_START_2_WIDTH 8 /* DSP3_PM_START - [7:0] */ 5172*4882a593Smuzhiyun 5173*4882a593Smuzhiyun /* 5174*4882a593Smuzhiyun * R34817 (0x8801) - DSP3 PM 1 5175*4882a593Smuzhiyun */ 5176*4882a593Smuzhiyun #define WM5100_DSP3_PM_START_1_MASK 0xFFFF /* DSP3_PM_START - [15:0] */ 5177*4882a593Smuzhiyun #define WM5100_DSP3_PM_START_1_SHIFT 0 /* DSP3_PM_START - [15:0] */ 5178*4882a593Smuzhiyun #define WM5100_DSP3_PM_START_1_WIDTH 16 /* DSP3_PM_START - [15:0] */ 5179*4882a593Smuzhiyun 5180*4882a593Smuzhiyun /* 5181*4882a593Smuzhiyun * R34818 (0x8802) - DSP3 PM 2 5182*4882a593Smuzhiyun */ 5183*4882a593Smuzhiyun #define WM5100_DSP3_PM_START_MASK 0xFFFF /* DSP3_PM_START - [15:0] */ 5184*4882a593Smuzhiyun #define WM5100_DSP3_PM_START_SHIFT 0 /* DSP3_PM_START - [15:0] */ 5185*4882a593Smuzhiyun #define WM5100_DSP3_PM_START_WIDTH 16 /* DSP3_PM_START - [15:0] */ 5186*4882a593Smuzhiyun 5187*4882a593Smuzhiyun /* 5188*4882a593Smuzhiyun * R34819 (0x8803) - DSP3 PM 3 5189*4882a593Smuzhiyun */ 5190*4882a593Smuzhiyun #define WM5100_DSP3_PM_1_2_MASK 0x00FF /* DSP3_PM_1 - [7:0] */ 5191*4882a593Smuzhiyun #define WM5100_DSP3_PM_1_2_SHIFT 0 /* DSP3_PM_1 - [7:0] */ 5192*4882a593Smuzhiyun #define WM5100_DSP3_PM_1_2_WIDTH 8 /* DSP3_PM_1 - [7:0] */ 5193*4882a593Smuzhiyun 5194*4882a593Smuzhiyun /* 5195*4882a593Smuzhiyun * R34820 (0x8804) - DSP3 PM 4 5196*4882a593Smuzhiyun */ 5197*4882a593Smuzhiyun #define WM5100_DSP3_PM_1_1_MASK 0xFFFF /* DSP3_PM_1 - [15:0] */ 5198*4882a593Smuzhiyun #define WM5100_DSP3_PM_1_1_SHIFT 0 /* DSP3_PM_1 - [15:0] */ 5199*4882a593Smuzhiyun #define WM5100_DSP3_PM_1_1_WIDTH 16 /* DSP3_PM_1 - [15:0] */ 5200*4882a593Smuzhiyun 5201*4882a593Smuzhiyun /* 5202*4882a593Smuzhiyun * R34821 (0x8805) - DSP3 PM 5 5203*4882a593Smuzhiyun */ 5204*4882a593Smuzhiyun #define WM5100_DSP3_PM_1_MASK 0xFFFF /* DSP3_PM_1 - [15:0] */ 5205*4882a593Smuzhiyun #define WM5100_DSP3_PM_1_SHIFT 0 /* DSP3_PM_1 - [15:0] */ 5206*4882a593Smuzhiyun #define WM5100_DSP3_PM_1_WIDTH 16 /* DSP3_PM_1 - [15:0] */ 5207*4882a593Smuzhiyun 5208*4882a593Smuzhiyun /* 5209*4882a593Smuzhiyun * R36346 (0x8DFA) - DSP3 PM 1530 5210*4882a593Smuzhiyun */ 5211*4882a593Smuzhiyun #define WM5100_DSP3_PM_510_2_MASK 0x00FF /* DSP3_PM_510 - [7:0] */ 5212*4882a593Smuzhiyun #define WM5100_DSP3_PM_510_2_SHIFT 0 /* DSP3_PM_510 - [7:0] */ 5213*4882a593Smuzhiyun #define WM5100_DSP3_PM_510_2_WIDTH 8 /* DSP3_PM_510 - [7:0] */ 5214*4882a593Smuzhiyun 5215*4882a593Smuzhiyun /* 5216*4882a593Smuzhiyun * R36347 (0x8DFB) - DSP3 PM 1531 5217*4882a593Smuzhiyun */ 5218*4882a593Smuzhiyun #define WM5100_DSP3_PM_510_1_MASK 0xFFFF /* DSP3_PM_510 - [15:0] */ 5219*4882a593Smuzhiyun #define WM5100_DSP3_PM_510_1_SHIFT 0 /* DSP3_PM_510 - [15:0] */ 5220*4882a593Smuzhiyun #define WM5100_DSP3_PM_510_1_WIDTH 16 /* DSP3_PM_510 - [15:0] */ 5221*4882a593Smuzhiyun 5222*4882a593Smuzhiyun /* 5223*4882a593Smuzhiyun * R36348 (0x8DFC) - DSP3 PM 1532 5224*4882a593Smuzhiyun */ 5225*4882a593Smuzhiyun #define WM5100_DSP3_PM_510_MASK 0xFFFF /* DSP3_PM_510 - [15:0] */ 5226*4882a593Smuzhiyun #define WM5100_DSP3_PM_510_SHIFT 0 /* DSP3_PM_510 - [15:0] */ 5227*4882a593Smuzhiyun #define WM5100_DSP3_PM_510_WIDTH 16 /* DSP3_PM_510 - [15:0] */ 5228*4882a593Smuzhiyun 5229*4882a593Smuzhiyun /* 5230*4882a593Smuzhiyun * R36349 (0x8DFD) - DSP3 PM 1533 5231*4882a593Smuzhiyun */ 5232*4882a593Smuzhiyun #define WM5100_DSP3_PM_END_2_MASK 0x00FF /* DSP3_PM_END - [7:0] */ 5233*4882a593Smuzhiyun #define WM5100_DSP3_PM_END_2_SHIFT 0 /* DSP3_PM_END - [7:0] */ 5234*4882a593Smuzhiyun #define WM5100_DSP3_PM_END_2_WIDTH 8 /* DSP3_PM_END - [7:0] */ 5235*4882a593Smuzhiyun 5236*4882a593Smuzhiyun /* 5237*4882a593Smuzhiyun * R36350 (0x8DFE) - DSP3 PM 1534 5238*4882a593Smuzhiyun */ 5239*4882a593Smuzhiyun #define WM5100_DSP3_PM_END_1_MASK 0xFFFF /* DSP3_PM_END - [15:0] */ 5240*4882a593Smuzhiyun #define WM5100_DSP3_PM_END_1_SHIFT 0 /* DSP3_PM_END - [15:0] */ 5241*4882a593Smuzhiyun #define WM5100_DSP3_PM_END_1_WIDTH 16 /* DSP3_PM_END - [15:0] */ 5242*4882a593Smuzhiyun 5243*4882a593Smuzhiyun /* 5244*4882a593Smuzhiyun * R36351 (0x8DFF) - DSP3 PM 1535 5245*4882a593Smuzhiyun */ 5246*4882a593Smuzhiyun #define WM5100_DSP3_PM_END_MASK 0xFFFF /* DSP3_PM_END - [15:0] */ 5247*4882a593Smuzhiyun #define WM5100_DSP3_PM_END_SHIFT 0 /* DSP3_PM_END - [15:0] */ 5248*4882a593Smuzhiyun #define WM5100_DSP3_PM_END_WIDTH 16 /* DSP3_PM_END - [15:0] */ 5249*4882a593Smuzhiyun 5250*4882a593Smuzhiyun /* 5251*4882a593Smuzhiyun * R36864 (0x9000) - DSP3 ZM 0 5252*4882a593Smuzhiyun */ 5253*4882a593Smuzhiyun #define WM5100_DSP3_ZM_START_1_MASK 0x00FF /* DSP3_ZM_START - [7:0] */ 5254*4882a593Smuzhiyun #define WM5100_DSP3_ZM_START_1_SHIFT 0 /* DSP3_ZM_START - [7:0] */ 5255*4882a593Smuzhiyun #define WM5100_DSP3_ZM_START_1_WIDTH 8 /* DSP3_ZM_START - [7:0] */ 5256*4882a593Smuzhiyun 5257*4882a593Smuzhiyun /* 5258*4882a593Smuzhiyun * R36865 (0x9001) - DSP3 ZM 1 5259*4882a593Smuzhiyun */ 5260*4882a593Smuzhiyun #define WM5100_DSP3_ZM_START_MASK 0xFFFF /* DSP3_ZM_START - [15:0] */ 5261*4882a593Smuzhiyun #define WM5100_DSP3_ZM_START_SHIFT 0 /* DSP3_ZM_START - [15:0] */ 5262*4882a593Smuzhiyun #define WM5100_DSP3_ZM_START_WIDTH 16 /* DSP3_ZM_START - [15:0] */ 5263*4882a593Smuzhiyun 5264*4882a593Smuzhiyun /* 5265*4882a593Smuzhiyun * R36866 (0x9002) - DSP3 ZM 2 5266*4882a593Smuzhiyun */ 5267*4882a593Smuzhiyun #define WM5100_DSP3_ZM_1_1_MASK 0x00FF /* DSP3_ZM_1 - [7:0] */ 5268*4882a593Smuzhiyun #define WM5100_DSP3_ZM_1_1_SHIFT 0 /* DSP3_ZM_1 - [7:0] */ 5269*4882a593Smuzhiyun #define WM5100_DSP3_ZM_1_1_WIDTH 8 /* DSP3_ZM_1 - [7:0] */ 5270*4882a593Smuzhiyun 5271*4882a593Smuzhiyun /* 5272*4882a593Smuzhiyun * R36867 (0x9003) - DSP3 ZM 3 5273*4882a593Smuzhiyun */ 5274*4882a593Smuzhiyun #define WM5100_DSP3_ZM_1_MASK 0xFFFF /* DSP3_ZM_1 - [15:0] */ 5275*4882a593Smuzhiyun #define WM5100_DSP3_ZM_1_SHIFT 0 /* DSP3_ZM_1 - [15:0] */ 5276*4882a593Smuzhiyun #define WM5100_DSP3_ZM_1_WIDTH 16 /* DSP3_ZM_1 - [15:0] */ 5277*4882a593Smuzhiyun 5278*4882a593Smuzhiyun /* 5279*4882a593Smuzhiyun * R38908 (0x97FC) - DSP3 ZM 2044 5280*4882a593Smuzhiyun */ 5281*4882a593Smuzhiyun #define WM5100_DSP3_ZM_1022_1_MASK 0x00FF /* DSP3_ZM_1022 - [7:0] */ 5282*4882a593Smuzhiyun #define WM5100_DSP3_ZM_1022_1_SHIFT 0 /* DSP3_ZM_1022 - [7:0] */ 5283*4882a593Smuzhiyun #define WM5100_DSP3_ZM_1022_1_WIDTH 8 /* DSP3_ZM_1022 - [7:0] */ 5284*4882a593Smuzhiyun 5285*4882a593Smuzhiyun /* 5286*4882a593Smuzhiyun * R38909 (0x97FD) - DSP3 ZM 2045 5287*4882a593Smuzhiyun */ 5288*4882a593Smuzhiyun #define WM5100_DSP3_ZM_1022_MASK 0xFFFF /* DSP3_ZM_1022 - [15:0] */ 5289*4882a593Smuzhiyun #define WM5100_DSP3_ZM_1022_SHIFT 0 /* DSP3_ZM_1022 - [15:0] */ 5290*4882a593Smuzhiyun #define WM5100_DSP3_ZM_1022_WIDTH 16 /* DSP3_ZM_1022 - [15:0] */ 5291*4882a593Smuzhiyun 5292*4882a593Smuzhiyun /* 5293*4882a593Smuzhiyun * R38910 (0x97FE) - DSP3 ZM 2046 5294*4882a593Smuzhiyun */ 5295*4882a593Smuzhiyun #define WM5100_DSP3_ZM_END_1_MASK 0x00FF /* DSP3_ZM_END - [7:0] */ 5296*4882a593Smuzhiyun #define WM5100_DSP3_ZM_END_1_SHIFT 0 /* DSP3_ZM_END - [7:0] */ 5297*4882a593Smuzhiyun #define WM5100_DSP3_ZM_END_1_WIDTH 8 /* DSP3_ZM_END - [7:0] */ 5298*4882a593Smuzhiyun 5299*4882a593Smuzhiyun /* 5300*4882a593Smuzhiyun * R38911 (0x97FF) - DSP3 ZM 2047 5301*4882a593Smuzhiyun */ 5302*4882a593Smuzhiyun #define WM5100_DSP3_ZM_END_MASK 0xFFFF /* DSP3_ZM_END - [15:0] */ 5303*4882a593Smuzhiyun #define WM5100_DSP3_ZM_END_SHIFT 0 /* DSP3_ZM_END - [15:0] */ 5304*4882a593Smuzhiyun #define WM5100_DSP3_ZM_END_WIDTH 16 /* DSP3_ZM_END - [15:0] */ 5305*4882a593Smuzhiyun 5306*4882a593Smuzhiyun bool wm5100_readable_register(struct device *dev, unsigned int reg); 5307*4882a593Smuzhiyun bool wm5100_volatile_register(struct device *dev, unsigned int reg); 5308*4882a593Smuzhiyun 5309*4882a593Smuzhiyun extern struct reg_default wm5100_reg_defaults[WM5100_REGISTER_COUNT]; 5310*4882a593Smuzhiyun 5311*4882a593Smuzhiyun #endif 5312