1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * wm2200.h - WM2200 audio codec interface 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright 2012 Wolfson Microelectronics PLC. 6*4882a593Smuzhiyun * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef _WM2200_H 10*4882a593Smuzhiyun #define _WM2200_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define WM2200_CLK_SYSCLK 1 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define WM2200_CLKSRC_MCLK1 0 15*4882a593Smuzhiyun #define WM2200_CLKSRC_MCLK2 1 16*4882a593Smuzhiyun #define WM2200_CLKSRC_FLL 4 17*4882a593Smuzhiyun #define WM2200_CLKSRC_BCLK1 8 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define WM2200_FLL_SRC_MCLK1 0 20*4882a593Smuzhiyun #define WM2200_FLL_SRC_MCLK2 1 21*4882a593Smuzhiyun #define WM2200_FLL_SRC_BCLK 2 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun /* 24*4882a593Smuzhiyun * Register values. 25*4882a593Smuzhiyun */ 26*4882a593Smuzhiyun #define WM2200_SOFTWARE_RESET 0x00 27*4882a593Smuzhiyun #define WM2200_DEVICE_REVISION 0x01 28*4882a593Smuzhiyun #define WM2200_TONE_GENERATOR_1 0x0B 29*4882a593Smuzhiyun #define WM2200_CLOCKING_3 0x102 30*4882a593Smuzhiyun #define WM2200_CLOCKING_4 0x103 31*4882a593Smuzhiyun #define WM2200_FLL_CONTROL_1 0x111 32*4882a593Smuzhiyun #define WM2200_FLL_CONTROL_2 0x112 33*4882a593Smuzhiyun #define WM2200_FLL_CONTROL_3 0x113 34*4882a593Smuzhiyun #define WM2200_FLL_CONTROL_4 0x114 35*4882a593Smuzhiyun #define WM2200_FLL_CONTROL_6 0x116 36*4882a593Smuzhiyun #define WM2200_FLL_CONTROL_7 0x117 37*4882a593Smuzhiyun #define WM2200_FLL_EFS_1 0x119 38*4882a593Smuzhiyun #define WM2200_FLL_EFS_2 0x11A 39*4882a593Smuzhiyun #define WM2200_MIC_CHARGE_PUMP_1 0x200 40*4882a593Smuzhiyun #define WM2200_MIC_CHARGE_PUMP_2 0x201 41*4882a593Smuzhiyun #define WM2200_DM_CHARGE_PUMP_1 0x202 42*4882a593Smuzhiyun #define WM2200_MIC_BIAS_CTRL_1 0x20C 43*4882a593Smuzhiyun #define WM2200_MIC_BIAS_CTRL_2 0x20D 44*4882a593Smuzhiyun #define WM2200_EAR_PIECE_CTRL_1 0x20F 45*4882a593Smuzhiyun #define WM2200_EAR_PIECE_CTRL_2 0x210 46*4882a593Smuzhiyun #define WM2200_INPUT_ENABLES 0x301 47*4882a593Smuzhiyun #define WM2200_IN1L_CONTROL 0x302 48*4882a593Smuzhiyun #define WM2200_IN1R_CONTROL 0x303 49*4882a593Smuzhiyun #define WM2200_IN2L_CONTROL 0x304 50*4882a593Smuzhiyun #define WM2200_IN2R_CONTROL 0x305 51*4882a593Smuzhiyun #define WM2200_IN3L_CONTROL 0x306 52*4882a593Smuzhiyun #define WM2200_IN3R_CONTROL 0x307 53*4882a593Smuzhiyun #define WM2200_RXANC_SRC 0x30A 54*4882a593Smuzhiyun #define WM2200_INPUT_VOLUME_RAMP 0x30B 55*4882a593Smuzhiyun #define WM2200_ADC_DIGITAL_VOLUME_1L 0x30C 56*4882a593Smuzhiyun #define WM2200_ADC_DIGITAL_VOLUME_1R 0x30D 57*4882a593Smuzhiyun #define WM2200_ADC_DIGITAL_VOLUME_2L 0x30E 58*4882a593Smuzhiyun #define WM2200_ADC_DIGITAL_VOLUME_2R 0x30F 59*4882a593Smuzhiyun #define WM2200_ADC_DIGITAL_VOLUME_3L 0x310 60*4882a593Smuzhiyun #define WM2200_ADC_DIGITAL_VOLUME_3R 0x311 61*4882a593Smuzhiyun #define WM2200_OUTPUT_ENABLES 0x400 62*4882a593Smuzhiyun #define WM2200_DAC_VOLUME_LIMIT_1L 0x401 63*4882a593Smuzhiyun #define WM2200_DAC_VOLUME_LIMIT_1R 0x402 64*4882a593Smuzhiyun #define WM2200_DAC_VOLUME_LIMIT_2L 0x403 65*4882a593Smuzhiyun #define WM2200_DAC_VOLUME_LIMIT_2R 0x404 66*4882a593Smuzhiyun #define WM2200_DAC_AEC_CONTROL_1 0x409 67*4882a593Smuzhiyun #define WM2200_OUTPUT_VOLUME_RAMP 0x40A 68*4882a593Smuzhiyun #define WM2200_DAC_DIGITAL_VOLUME_1L 0x40B 69*4882a593Smuzhiyun #define WM2200_DAC_DIGITAL_VOLUME_1R 0x40C 70*4882a593Smuzhiyun #define WM2200_DAC_DIGITAL_VOLUME_2L 0x40D 71*4882a593Smuzhiyun #define WM2200_DAC_DIGITAL_VOLUME_2R 0x40E 72*4882a593Smuzhiyun #define WM2200_PDM_1 0x417 73*4882a593Smuzhiyun #define WM2200_PDM_2 0x418 74*4882a593Smuzhiyun #define WM2200_AUDIO_IF_1_1 0x500 75*4882a593Smuzhiyun #define WM2200_AUDIO_IF_1_2 0x501 76*4882a593Smuzhiyun #define WM2200_AUDIO_IF_1_3 0x502 77*4882a593Smuzhiyun #define WM2200_AUDIO_IF_1_4 0x503 78*4882a593Smuzhiyun #define WM2200_AUDIO_IF_1_5 0x504 79*4882a593Smuzhiyun #define WM2200_AUDIO_IF_1_6 0x505 80*4882a593Smuzhiyun #define WM2200_AUDIO_IF_1_7 0x506 81*4882a593Smuzhiyun #define WM2200_AUDIO_IF_1_8 0x507 82*4882a593Smuzhiyun #define WM2200_AUDIO_IF_1_9 0x508 83*4882a593Smuzhiyun #define WM2200_AUDIO_IF_1_10 0x509 84*4882a593Smuzhiyun #define WM2200_AUDIO_IF_1_11 0x50A 85*4882a593Smuzhiyun #define WM2200_AUDIO_IF_1_12 0x50B 86*4882a593Smuzhiyun #define WM2200_AUDIO_IF_1_13 0x50C 87*4882a593Smuzhiyun #define WM2200_AUDIO_IF_1_14 0x50D 88*4882a593Smuzhiyun #define WM2200_AUDIO_IF_1_15 0x50E 89*4882a593Smuzhiyun #define WM2200_AUDIO_IF_1_16 0x50F 90*4882a593Smuzhiyun #define WM2200_AUDIO_IF_1_17 0x510 91*4882a593Smuzhiyun #define WM2200_AUDIO_IF_1_18 0x511 92*4882a593Smuzhiyun #define WM2200_AUDIO_IF_1_19 0x512 93*4882a593Smuzhiyun #define WM2200_AUDIO_IF_1_20 0x513 94*4882a593Smuzhiyun #define WM2200_AUDIO_IF_1_21 0x514 95*4882a593Smuzhiyun #define WM2200_AUDIO_IF_1_22 0x515 96*4882a593Smuzhiyun #define WM2200_OUT1LMIX_INPUT_1_SOURCE 0x600 97*4882a593Smuzhiyun #define WM2200_OUT1LMIX_INPUT_1_VOLUME 0x601 98*4882a593Smuzhiyun #define WM2200_OUT1LMIX_INPUT_2_SOURCE 0x602 99*4882a593Smuzhiyun #define WM2200_OUT1LMIX_INPUT_2_VOLUME 0x603 100*4882a593Smuzhiyun #define WM2200_OUT1LMIX_INPUT_3_SOURCE 0x604 101*4882a593Smuzhiyun #define WM2200_OUT1LMIX_INPUT_3_VOLUME 0x605 102*4882a593Smuzhiyun #define WM2200_OUT1LMIX_INPUT_4_SOURCE 0x606 103*4882a593Smuzhiyun #define WM2200_OUT1LMIX_INPUT_4_VOLUME 0x607 104*4882a593Smuzhiyun #define WM2200_OUT1RMIX_INPUT_1_SOURCE 0x608 105*4882a593Smuzhiyun #define WM2200_OUT1RMIX_INPUT_1_VOLUME 0x609 106*4882a593Smuzhiyun #define WM2200_OUT1RMIX_INPUT_2_SOURCE 0x60A 107*4882a593Smuzhiyun #define WM2200_OUT1RMIX_INPUT_2_VOLUME 0x60B 108*4882a593Smuzhiyun #define WM2200_OUT1RMIX_INPUT_3_SOURCE 0x60C 109*4882a593Smuzhiyun #define WM2200_OUT1RMIX_INPUT_3_VOLUME 0x60D 110*4882a593Smuzhiyun #define WM2200_OUT1RMIX_INPUT_4_SOURCE 0x60E 111*4882a593Smuzhiyun #define WM2200_OUT1RMIX_INPUT_4_VOLUME 0x60F 112*4882a593Smuzhiyun #define WM2200_OUT2LMIX_INPUT_1_SOURCE 0x610 113*4882a593Smuzhiyun #define WM2200_OUT2LMIX_INPUT_1_VOLUME 0x611 114*4882a593Smuzhiyun #define WM2200_OUT2LMIX_INPUT_2_SOURCE 0x612 115*4882a593Smuzhiyun #define WM2200_OUT2LMIX_INPUT_2_VOLUME 0x613 116*4882a593Smuzhiyun #define WM2200_OUT2LMIX_INPUT_3_SOURCE 0x614 117*4882a593Smuzhiyun #define WM2200_OUT2LMIX_INPUT_3_VOLUME 0x615 118*4882a593Smuzhiyun #define WM2200_OUT2LMIX_INPUT_4_SOURCE 0x616 119*4882a593Smuzhiyun #define WM2200_OUT2LMIX_INPUT_4_VOLUME 0x617 120*4882a593Smuzhiyun #define WM2200_OUT2RMIX_INPUT_1_SOURCE 0x618 121*4882a593Smuzhiyun #define WM2200_OUT2RMIX_INPUT_1_VOLUME 0x619 122*4882a593Smuzhiyun #define WM2200_OUT2RMIX_INPUT_2_SOURCE 0x61A 123*4882a593Smuzhiyun #define WM2200_OUT2RMIX_INPUT_2_VOLUME 0x61B 124*4882a593Smuzhiyun #define WM2200_OUT2RMIX_INPUT_3_SOURCE 0x61C 125*4882a593Smuzhiyun #define WM2200_OUT2RMIX_INPUT_3_VOLUME 0x61D 126*4882a593Smuzhiyun #define WM2200_OUT2RMIX_INPUT_4_SOURCE 0x61E 127*4882a593Smuzhiyun #define WM2200_OUT2RMIX_INPUT_4_VOLUME 0x61F 128*4882a593Smuzhiyun #define WM2200_AIF1TX1MIX_INPUT_1_SOURCE 0x620 129*4882a593Smuzhiyun #define WM2200_AIF1TX1MIX_INPUT_1_VOLUME 0x621 130*4882a593Smuzhiyun #define WM2200_AIF1TX1MIX_INPUT_2_SOURCE 0x622 131*4882a593Smuzhiyun #define WM2200_AIF1TX1MIX_INPUT_2_VOLUME 0x623 132*4882a593Smuzhiyun #define WM2200_AIF1TX1MIX_INPUT_3_SOURCE 0x624 133*4882a593Smuzhiyun #define WM2200_AIF1TX1MIX_INPUT_3_VOLUME 0x625 134*4882a593Smuzhiyun #define WM2200_AIF1TX1MIX_INPUT_4_SOURCE 0x626 135*4882a593Smuzhiyun #define WM2200_AIF1TX1MIX_INPUT_4_VOLUME 0x627 136*4882a593Smuzhiyun #define WM2200_AIF1TX2MIX_INPUT_1_SOURCE 0x628 137*4882a593Smuzhiyun #define WM2200_AIF1TX2MIX_INPUT_1_VOLUME 0x629 138*4882a593Smuzhiyun #define WM2200_AIF1TX2MIX_INPUT_2_SOURCE 0x62A 139*4882a593Smuzhiyun #define WM2200_AIF1TX2MIX_INPUT_2_VOLUME 0x62B 140*4882a593Smuzhiyun #define WM2200_AIF1TX2MIX_INPUT_3_SOURCE 0x62C 141*4882a593Smuzhiyun #define WM2200_AIF1TX2MIX_INPUT_3_VOLUME 0x62D 142*4882a593Smuzhiyun #define WM2200_AIF1TX2MIX_INPUT_4_SOURCE 0x62E 143*4882a593Smuzhiyun #define WM2200_AIF1TX2MIX_INPUT_4_VOLUME 0x62F 144*4882a593Smuzhiyun #define WM2200_AIF1TX3MIX_INPUT_1_SOURCE 0x630 145*4882a593Smuzhiyun #define WM2200_AIF1TX3MIX_INPUT_1_VOLUME 0x631 146*4882a593Smuzhiyun #define WM2200_AIF1TX3MIX_INPUT_2_SOURCE 0x632 147*4882a593Smuzhiyun #define WM2200_AIF1TX3MIX_INPUT_2_VOLUME 0x633 148*4882a593Smuzhiyun #define WM2200_AIF1TX3MIX_INPUT_3_SOURCE 0x634 149*4882a593Smuzhiyun #define WM2200_AIF1TX3MIX_INPUT_3_VOLUME 0x635 150*4882a593Smuzhiyun #define WM2200_AIF1TX3MIX_INPUT_4_SOURCE 0x636 151*4882a593Smuzhiyun #define WM2200_AIF1TX3MIX_INPUT_4_VOLUME 0x637 152*4882a593Smuzhiyun #define WM2200_AIF1TX4MIX_INPUT_1_SOURCE 0x638 153*4882a593Smuzhiyun #define WM2200_AIF1TX4MIX_INPUT_1_VOLUME 0x639 154*4882a593Smuzhiyun #define WM2200_AIF1TX4MIX_INPUT_2_SOURCE 0x63A 155*4882a593Smuzhiyun #define WM2200_AIF1TX4MIX_INPUT_2_VOLUME 0x63B 156*4882a593Smuzhiyun #define WM2200_AIF1TX4MIX_INPUT_3_SOURCE 0x63C 157*4882a593Smuzhiyun #define WM2200_AIF1TX4MIX_INPUT_3_VOLUME 0x63D 158*4882a593Smuzhiyun #define WM2200_AIF1TX4MIX_INPUT_4_SOURCE 0x63E 159*4882a593Smuzhiyun #define WM2200_AIF1TX4MIX_INPUT_4_VOLUME 0x63F 160*4882a593Smuzhiyun #define WM2200_AIF1TX5MIX_INPUT_1_SOURCE 0x640 161*4882a593Smuzhiyun #define WM2200_AIF1TX5MIX_INPUT_1_VOLUME 0x641 162*4882a593Smuzhiyun #define WM2200_AIF1TX5MIX_INPUT_2_SOURCE 0x642 163*4882a593Smuzhiyun #define WM2200_AIF1TX5MIX_INPUT_2_VOLUME 0x643 164*4882a593Smuzhiyun #define WM2200_AIF1TX5MIX_INPUT_3_SOURCE 0x644 165*4882a593Smuzhiyun #define WM2200_AIF1TX5MIX_INPUT_3_VOLUME 0x645 166*4882a593Smuzhiyun #define WM2200_AIF1TX5MIX_INPUT_4_SOURCE 0x646 167*4882a593Smuzhiyun #define WM2200_AIF1TX5MIX_INPUT_4_VOLUME 0x647 168*4882a593Smuzhiyun #define WM2200_AIF1TX6MIX_INPUT_1_SOURCE 0x648 169*4882a593Smuzhiyun #define WM2200_AIF1TX6MIX_INPUT_1_VOLUME 0x649 170*4882a593Smuzhiyun #define WM2200_AIF1TX6MIX_INPUT_2_SOURCE 0x64A 171*4882a593Smuzhiyun #define WM2200_AIF1TX6MIX_INPUT_2_VOLUME 0x64B 172*4882a593Smuzhiyun #define WM2200_AIF1TX6MIX_INPUT_3_SOURCE 0x64C 173*4882a593Smuzhiyun #define WM2200_AIF1TX6MIX_INPUT_3_VOLUME 0x64D 174*4882a593Smuzhiyun #define WM2200_AIF1TX6MIX_INPUT_4_SOURCE 0x64E 175*4882a593Smuzhiyun #define WM2200_AIF1TX6MIX_INPUT_4_VOLUME 0x64F 176*4882a593Smuzhiyun #define WM2200_EQLMIX_INPUT_1_SOURCE 0x650 177*4882a593Smuzhiyun #define WM2200_EQLMIX_INPUT_1_VOLUME 0x651 178*4882a593Smuzhiyun #define WM2200_EQLMIX_INPUT_2_SOURCE 0x652 179*4882a593Smuzhiyun #define WM2200_EQLMIX_INPUT_2_VOLUME 0x653 180*4882a593Smuzhiyun #define WM2200_EQLMIX_INPUT_3_SOURCE 0x654 181*4882a593Smuzhiyun #define WM2200_EQLMIX_INPUT_3_VOLUME 0x655 182*4882a593Smuzhiyun #define WM2200_EQLMIX_INPUT_4_SOURCE 0x656 183*4882a593Smuzhiyun #define WM2200_EQLMIX_INPUT_4_VOLUME 0x657 184*4882a593Smuzhiyun #define WM2200_EQRMIX_INPUT_1_SOURCE 0x658 185*4882a593Smuzhiyun #define WM2200_EQRMIX_INPUT_1_VOLUME 0x659 186*4882a593Smuzhiyun #define WM2200_EQRMIX_INPUT_2_SOURCE 0x65A 187*4882a593Smuzhiyun #define WM2200_EQRMIX_INPUT_2_VOLUME 0x65B 188*4882a593Smuzhiyun #define WM2200_EQRMIX_INPUT_3_SOURCE 0x65C 189*4882a593Smuzhiyun #define WM2200_EQRMIX_INPUT_3_VOLUME 0x65D 190*4882a593Smuzhiyun #define WM2200_EQRMIX_INPUT_4_SOURCE 0x65E 191*4882a593Smuzhiyun #define WM2200_EQRMIX_INPUT_4_VOLUME 0x65F 192*4882a593Smuzhiyun #define WM2200_LHPF1MIX_INPUT_1_SOURCE 0x660 193*4882a593Smuzhiyun #define WM2200_LHPF1MIX_INPUT_1_VOLUME 0x661 194*4882a593Smuzhiyun #define WM2200_LHPF1MIX_INPUT_2_SOURCE 0x662 195*4882a593Smuzhiyun #define WM2200_LHPF1MIX_INPUT_2_VOLUME 0x663 196*4882a593Smuzhiyun #define WM2200_LHPF1MIX_INPUT_3_SOURCE 0x664 197*4882a593Smuzhiyun #define WM2200_LHPF1MIX_INPUT_3_VOLUME 0x665 198*4882a593Smuzhiyun #define WM2200_LHPF1MIX_INPUT_4_SOURCE 0x666 199*4882a593Smuzhiyun #define WM2200_LHPF1MIX_INPUT_4_VOLUME 0x667 200*4882a593Smuzhiyun #define WM2200_LHPF2MIX_INPUT_1_SOURCE 0x668 201*4882a593Smuzhiyun #define WM2200_LHPF2MIX_INPUT_1_VOLUME 0x669 202*4882a593Smuzhiyun #define WM2200_LHPF2MIX_INPUT_2_SOURCE 0x66A 203*4882a593Smuzhiyun #define WM2200_LHPF2MIX_INPUT_2_VOLUME 0x66B 204*4882a593Smuzhiyun #define WM2200_LHPF2MIX_INPUT_3_SOURCE 0x66C 205*4882a593Smuzhiyun #define WM2200_LHPF2MIX_INPUT_3_VOLUME 0x66D 206*4882a593Smuzhiyun #define WM2200_LHPF2MIX_INPUT_4_SOURCE 0x66E 207*4882a593Smuzhiyun #define WM2200_LHPF2MIX_INPUT_4_VOLUME 0x66F 208*4882a593Smuzhiyun #define WM2200_DSP1LMIX_INPUT_1_SOURCE 0x670 209*4882a593Smuzhiyun #define WM2200_DSP1LMIX_INPUT_1_VOLUME 0x671 210*4882a593Smuzhiyun #define WM2200_DSP1LMIX_INPUT_2_SOURCE 0x672 211*4882a593Smuzhiyun #define WM2200_DSP1LMIX_INPUT_2_VOLUME 0x673 212*4882a593Smuzhiyun #define WM2200_DSP1LMIX_INPUT_3_SOURCE 0x674 213*4882a593Smuzhiyun #define WM2200_DSP1LMIX_INPUT_3_VOLUME 0x675 214*4882a593Smuzhiyun #define WM2200_DSP1LMIX_INPUT_4_SOURCE 0x676 215*4882a593Smuzhiyun #define WM2200_DSP1LMIX_INPUT_4_VOLUME 0x677 216*4882a593Smuzhiyun #define WM2200_DSP1RMIX_INPUT_1_SOURCE 0x678 217*4882a593Smuzhiyun #define WM2200_DSP1RMIX_INPUT_1_VOLUME 0x679 218*4882a593Smuzhiyun #define WM2200_DSP1RMIX_INPUT_2_SOURCE 0x67A 219*4882a593Smuzhiyun #define WM2200_DSP1RMIX_INPUT_2_VOLUME 0x67B 220*4882a593Smuzhiyun #define WM2200_DSP1RMIX_INPUT_3_SOURCE 0x67C 221*4882a593Smuzhiyun #define WM2200_DSP1RMIX_INPUT_3_VOLUME 0x67D 222*4882a593Smuzhiyun #define WM2200_DSP1RMIX_INPUT_4_SOURCE 0x67E 223*4882a593Smuzhiyun #define WM2200_DSP1RMIX_INPUT_4_VOLUME 0x67F 224*4882a593Smuzhiyun #define WM2200_DSP1AUX1MIX_INPUT_1_SOURCE 0x680 225*4882a593Smuzhiyun #define WM2200_DSP1AUX2MIX_INPUT_1_SOURCE 0x681 226*4882a593Smuzhiyun #define WM2200_DSP1AUX3MIX_INPUT_1_SOURCE 0x682 227*4882a593Smuzhiyun #define WM2200_DSP1AUX4MIX_INPUT_1_SOURCE 0x683 228*4882a593Smuzhiyun #define WM2200_DSP1AUX5MIX_INPUT_1_SOURCE 0x684 229*4882a593Smuzhiyun #define WM2200_DSP1AUX6MIX_INPUT_1_SOURCE 0x685 230*4882a593Smuzhiyun #define WM2200_DSP2LMIX_INPUT_1_SOURCE 0x686 231*4882a593Smuzhiyun #define WM2200_DSP2LMIX_INPUT_1_VOLUME 0x687 232*4882a593Smuzhiyun #define WM2200_DSP2LMIX_INPUT_2_SOURCE 0x688 233*4882a593Smuzhiyun #define WM2200_DSP2LMIX_INPUT_2_VOLUME 0x689 234*4882a593Smuzhiyun #define WM2200_DSP2LMIX_INPUT_3_SOURCE 0x68A 235*4882a593Smuzhiyun #define WM2200_DSP2LMIX_INPUT_3_VOLUME 0x68B 236*4882a593Smuzhiyun #define WM2200_DSP2LMIX_INPUT_4_SOURCE 0x68C 237*4882a593Smuzhiyun #define WM2200_DSP2LMIX_INPUT_4_VOLUME 0x68D 238*4882a593Smuzhiyun #define WM2200_DSP2RMIX_INPUT_1_SOURCE 0x68E 239*4882a593Smuzhiyun #define WM2200_DSP2RMIX_INPUT_1_VOLUME 0x68F 240*4882a593Smuzhiyun #define WM2200_DSP2RMIX_INPUT_2_SOURCE 0x690 241*4882a593Smuzhiyun #define WM2200_DSP2RMIX_INPUT_2_VOLUME 0x691 242*4882a593Smuzhiyun #define WM2200_DSP2RMIX_INPUT_3_SOURCE 0x692 243*4882a593Smuzhiyun #define WM2200_DSP2RMIX_INPUT_3_VOLUME 0x693 244*4882a593Smuzhiyun #define WM2200_DSP2RMIX_INPUT_4_SOURCE 0x694 245*4882a593Smuzhiyun #define WM2200_DSP2RMIX_INPUT_4_VOLUME 0x695 246*4882a593Smuzhiyun #define WM2200_DSP2AUX1MIX_INPUT_1_SOURCE 0x696 247*4882a593Smuzhiyun #define WM2200_DSP2AUX2MIX_INPUT_1_SOURCE 0x697 248*4882a593Smuzhiyun #define WM2200_DSP2AUX3MIX_INPUT_1_SOURCE 0x698 249*4882a593Smuzhiyun #define WM2200_DSP2AUX4MIX_INPUT_1_SOURCE 0x699 250*4882a593Smuzhiyun #define WM2200_DSP2AUX5MIX_INPUT_1_SOURCE 0x69A 251*4882a593Smuzhiyun #define WM2200_DSP2AUX6MIX_INPUT_1_SOURCE 0x69B 252*4882a593Smuzhiyun #define WM2200_GPIO_CTRL_1 0x700 253*4882a593Smuzhiyun #define WM2200_GPIO_CTRL_2 0x701 254*4882a593Smuzhiyun #define WM2200_GPIO_CTRL_3 0x702 255*4882a593Smuzhiyun #define WM2200_GPIO_CTRL_4 0x703 256*4882a593Smuzhiyun #define WM2200_ADPS1_IRQ0 0x707 257*4882a593Smuzhiyun #define WM2200_ADPS1_IRQ1 0x708 258*4882a593Smuzhiyun #define WM2200_MISC_PAD_CTRL_1 0x709 259*4882a593Smuzhiyun #define WM2200_INTERRUPT_STATUS_1 0x800 260*4882a593Smuzhiyun #define WM2200_INTERRUPT_STATUS_1_MASK 0x801 261*4882a593Smuzhiyun #define WM2200_INTERRUPT_STATUS_2 0x802 262*4882a593Smuzhiyun #define WM2200_INTERRUPT_RAW_STATUS_2 0x803 263*4882a593Smuzhiyun #define WM2200_INTERRUPT_STATUS_2_MASK 0x804 264*4882a593Smuzhiyun #define WM2200_INTERRUPT_CONTROL 0x808 265*4882a593Smuzhiyun #define WM2200_EQL_1 0x900 266*4882a593Smuzhiyun #define WM2200_EQL_2 0x901 267*4882a593Smuzhiyun #define WM2200_EQL_3 0x902 268*4882a593Smuzhiyun #define WM2200_EQL_4 0x903 269*4882a593Smuzhiyun #define WM2200_EQL_5 0x904 270*4882a593Smuzhiyun #define WM2200_EQL_6 0x905 271*4882a593Smuzhiyun #define WM2200_EQL_7 0x906 272*4882a593Smuzhiyun #define WM2200_EQL_8 0x907 273*4882a593Smuzhiyun #define WM2200_EQL_9 0x908 274*4882a593Smuzhiyun #define WM2200_EQL_10 0x909 275*4882a593Smuzhiyun #define WM2200_EQL_11 0x90A 276*4882a593Smuzhiyun #define WM2200_EQL_12 0x90B 277*4882a593Smuzhiyun #define WM2200_EQL_13 0x90C 278*4882a593Smuzhiyun #define WM2200_EQL_14 0x90D 279*4882a593Smuzhiyun #define WM2200_EQL_15 0x90E 280*4882a593Smuzhiyun #define WM2200_EQL_16 0x90F 281*4882a593Smuzhiyun #define WM2200_EQL_17 0x910 282*4882a593Smuzhiyun #define WM2200_EQL_18 0x911 283*4882a593Smuzhiyun #define WM2200_EQL_19 0x912 284*4882a593Smuzhiyun #define WM2200_EQL_20 0x913 285*4882a593Smuzhiyun #define WM2200_EQR_1 0x916 286*4882a593Smuzhiyun #define WM2200_EQR_2 0x917 287*4882a593Smuzhiyun #define WM2200_EQR_3 0x918 288*4882a593Smuzhiyun #define WM2200_EQR_4 0x919 289*4882a593Smuzhiyun #define WM2200_EQR_5 0x91A 290*4882a593Smuzhiyun #define WM2200_EQR_6 0x91B 291*4882a593Smuzhiyun #define WM2200_EQR_7 0x91C 292*4882a593Smuzhiyun #define WM2200_EQR_8 0x91D 293*4882a593Smuzhiyun #define WM2200_EQR_9 0x91E 294*4882a593Smuzhiyun #define WM2200_EQR_10 0x91F 295*4882a593Smuzhiyun #define WM2200_EQR_11 0x920 296*4882a593Smuzhiyun #define WM2200_EQR_12 0x921 297*4882a593Smuzhiyun #define WM2200_EQR_13 0x922 298*4882a593Smuzhiyun #define WM2200_EQR_14 0x923 299*4882a593Smuzhiyun #define WM2200_EQR_15 0x924 300*4882a593Smuzhiyun #define WM2200_EQR_16 0x925 301*4882a593Smuzhiyun #define WM2200_EQR_17 0x926 302*4882a593Smuzhiyun #define WM2200_EQR_18 0x927 303*4882a593Smuzhiyun #define WM2200_EQR_19 0x928 304*4882a593Smuzhiyun #define WM2200_EQR_20 0x929 305*4882a593Smuzhiyun #define WM2200_HPLPF1_1 0x93E 306*4882a593Smuzhiyun #define WM2200_HPLPF1_2 0x93F 307*4882a593Smuzhiyun #define WM2200_HPLPF2_1 0x942 308*4882a593Smuzhiyun #define WM2200_HPLPF2_2 0x943 309*4882a593Smuzhiyun #define WM2200_DSP1_CONTROL_1 0xA00 310*4882a593Smuzhiyun #define WM2200_DSP1_CONTROL_2 0xA02 311*4882a593Smuzhiyun #define WM2200_DSP1_CONTROL_3 0xA03 312*4882a593Smuzhiyun #define WM2200_DSP1_CONTROL_4 0xA04 313*4882a593Smuzhiyun #define WM2200_DSP1_CONTROL_5 0xA06 314*4882a593Smuzhiyun #define WM2200_DSP1_CONTROL_6 0xA07 315*4882a593Smuzhiyun #define WM2200_DSP1_CONTROL_7 0xA08 316*4882a593Smuzhiyun #define WM2200_DSP1_CONTROL_8 0xA09 317*4882a593Smuzhiyun #define WM2200_DSP1_CONTROL_9 0xA0A 318*4882a593Smuzhiyun #define WM2200_DSP1_CONTROL_10 0xA0B 319*4882a593Smuzhiyun #define WM2200_DSP1_CONTROL_11 0xA0C 320*4882a593Smuzhiyun #define WM2200_DSP1_CONTROL_12 0xA0D 321*4882a593Smuzhiyun #define WM2200_DSP1_CONTROL_13 0xA0F 322*4882a593Smuzhiyun #define WM2200_DSP1_CONTROL_14 0xA10 323*4882a593Smuzhiyun #define WM2200_DSP1_CONTROL_15 0xA11 324*4882a593Smuzhiyun #define WM2200_DSP1_CONTROL_16 0xA12 325*4882a593Smuzhiyun #define WM2200_DSP1_CONTROL_17 0xA13 326*4882a593Smuzhiyun #define WM2200_DSP1_CONTROL_18 0xA14 327*4882a593Smuzhiyun #define WM2200_DSP1_CONTROL_19 0xA16 328*4882a593Smuzhiyun #define WM2200_DSP1_CONTROL_20 0xA17 329*4882a593Smuzhiyun #define WM2200_DSP1_CONTROL_21 0xA18 330*4882a593Smuzhiyun #define WM2200_DSP1_CONTROL_22 0xA1A 331*4882a593Smuzhiyun #define WM2200_DSP1_CONTROL_23 0xA1B 332*4882a593Smuzhiyun #define WM2200_DSP1_CONTROL_24 0xA1C 333*4882a593Smuzhiyun #define WM2200_DSP1_CONTROL_25 0xA1E 334*4882a593Smuzhiyun #define WM2200_DSP1_CONTROL_26 0xA20 335*4882a593Smuzhiyun #define WM2200_DSP1_CONTROL_27 0xA21 336*4882a593Smuzhiyun #define WM2200_DSP1_CONTROL_28 0xA22 337*4882a593Smuzhiyun #define WM2200_DSP1_CONTROL_29 0xA23 338*4882a593Smuzhiyun #define WM2200_DSP1_CONTROL_30 0xA24 339*4882a593Smuzhiyun #define WM2200_DSP1_CONTROL_31 0xA26 340*4882a593Smuzhiyun #define WM2200_DSP2_CONTROL_1 0xB00 341*4882a593Smuzhiyun #define WM2200_DSP2_CONTROL_2 0xB02 342*4882a593Smuzhiyun #define WM2200_DSP2_CONTROL_3 0xB03 343*4882a593Smuzhiyun #define WM2200_DSP2_CONTROL_4 0xB04 344*4882a593Smuzhiyun #define WM2200_DSP2_CONTROL_5 0xB06 345*4882a593Smuzhiyun #define WM2200_DSP2_CONTROL_6 0xB07 346*4882a593Smuzhiyun #define WM2200_DSP2_CONTROL_7 0xB08 347*4882a593Smuzhiyun #define WM2200_DSP2_CONTROL_8 0xB09 348*4882a593Smuzhiyun #define WM2200_DSP2_CONTROL_9 0xB0A 349*4882a593Smuzhiyun #define WM2200_DSP2_CONTROL_10 0xB0B 350*4882a593Smuzhiyun #define WM2200_DSP2_CONTROL_11 0xB0C 351*4882a593Smuzhiyun #define WM2200_DSP2_CONTROL_12 0xB0D 352*4882a593Smuzhiyun #define WM2200_DSP2_CONTROL_13 0xB0F 353*4882a593Smuzhiyun #define WM2200_DSP2_CONTROL_14 0xB10 354*4882a593Smuzhiyun #define WM2200_DSP2_CONTROL_15 0xB11 355*4882a593Smuzhiyun #define WM2200_DSP2_CONTROL_16 0xB12 356*4882a593Smuzhiyun #define WM2200_DSP2_CONTROL_17 0xB13 357*4882a593Smuzhiyun #define WM2200_DSP2_CONTROL_18 0xB14 358*4882a593Smuzhiyun #define WM2200_DSP2_CONTROL_19 0xB16 359*4882a593Smuzhiyun #define WM2200_DSP2_CONTROL_20 0xB17 360*4882a593Smuzhiyun #define WM2200_DSP2_CONTROL_21 0xB18 361*4882a593Smuzhiyun #define WM2200_DSP2_CONTROL_22 0xB1A 362*4882a593Smuzhiyun #define WM2200_DSP2_CONTROL_23 0xB1B 363*4882a593Smuzhiyun #define WM2200_DSP2_CONTROL_24 0xB1C 364*4882a593Smuzhiyun #define WM2200_DSP2_CONTROL_25 0xB1E 365*4882a593Smuzhiyun #define WM2200_DSP2_CONTROL_26 0xB20 366*4882a593Smuzhiyun #define WM2200_DSP2_CONTROL_27 0xB21 367*4882a593Smuzhiyun #define WM2200_DSP2_CONTROL_28 0xB22 368*4882a593Smuzhiyun #define WM2200_DSP2_CONTROL_29 0xB23 369*4882a593Smuzhiyun #define WM2200_DSP2_CONTROL_30 0xB24 370*4882a593Smuzhiyun #define WM2200_DSP2_CONTROL_31 0xB26 371*4882a593Smuzhiyun #define WM2200_ANC_CTRL1 0xD00 372*4882a593Smuzhiyun #define WM2200_ANC_CTRL2 0xD01 373*4882a593Smuzhiyun #define WM2200_ANC_CTRL3 0xD02 374*4882a593Smuzhiyun #define WM2200_ANC_CTRL7 0xD08 375*4882a593Smuzhiyun #define WM2200_ANC_CTRL8 0xD09 376*4882a593Smuzhiyun #define WM2200_ANC_CTRL9 0xD0A 377*4882a593Smuzhiyun #define WM2200_ANC_CTRL10 0xD0B 378*4882a593Smuzhiyun #define WM2200_ANC_CTRL11 0xD0C 379*4882a593Smuzhiyun #define WM2200_ANC_CTRL12 0xD0D 380*4882a593Smuzhiyun #define WM2200_ANC_CTRL13 0xD0E 381*4882a593Smuzhiyun #define WM2200_ANC_CTRL14 0xD0F 382*4882a593Smuzhiyun #define WM2200_ANC_CTRL15 0xD10 383*4882a593Smuzhiyun #define WM2200_ANC_CTRL16 0xD11 384*4882a593Smuzhiyun #define WM2200_ANC_CTRL17 0xD12 385*4882a593Smuzhiyun #define WM2200_ANC_CTRL18 0xD15 386*4882a593Smuzhiyun #define WM2200_ANC_CTRL19 0xD16 387*4882a593Smuzhiyun #define WM2200_ANC_CTRL20 0xD17 388*4882a593Smuzhiyun #define WM2200_ANC_CTRL21 0xD18 389*4882a593Smuzhiyun #define WM2200_ANC_CTRL22 0xD19 390*4882a593Smuzhiyun #define WM2200_ANC_CTRL23 0xD1A 391*4882a593Smuzhiyun #define WM2200_ANC_CTRL24 0xD1B 392*4882a593Smuzhiyun #define WM2200_ANC_CTRL25 0xD1C 393*4882a593Smuzhiyun #define WM2200_ANC_CTRL26 0xD1D 394*4882a593Smuzhiyun #define WM2200_ANC_CTRL27 0xD1E 395*4882a593Smuzhiyun #define WM2200_ANC_CTRL28 0xD1F 396*4882a593Smuzhiyun #define WM2200_ANC_CTRL29 0xD20 397*4882a593Smuzhiyun #define WM2200_ANC_CTRL30 0xD21 398*4882a593Smuzhiyun #define WM2200_ANC_CTRL31 0xD23 399*4882a593Smuzhiyun #define WM2200_ANC_CTRL32 0xD24 400*4882a593Smuzhiyun #define WM2200_ANC_CTRL33 0xD25 401*4882a593Smuzhiyun #define WM2200_ANC_CTRL34 0xD27 402*4882a593Smuzhiyun #define WM2200_ANC_CTRL35 0xD28 403*4882a593Smuzhiyun #define WM2200_ANC_CTRL36 0xD29 404*4882a593Smuzhiyun #define WM2200_ANC_CTRL37 0xD2A 405*4882a593Smuzhiyun #define WM2200_ANC_CTRL38 0xD2B 406*4882a593Smuzhiyun #define WM2200_ANC_CTRL39 0xD2C 407*4882a593Smuzhiyun #define WM2200_ANC_CTRL40 0xD2D 408*4882a593Smuzhiyun #define WM2200_ANC_CTRL41 0xD2E 409*4882a593Smuzhiyun #define WM2200_ANC_CTRL42 0xD2F 410*4882a593Smuzhiyun #define WM2200_ANC_CTRL43 0xD30 411*4882a593Smuzhiyun #define WM2200_ANC_CTRL44 0xD31 412*4882a593Smuzhiyun #define WM2200_ANC_CTRL45 0xD32 413*4882a593Smuzhiyun #define WM2200_ANC_CTRL46 0xD33 414*4882a593Smuzhiyun #define WM2200_ANC_CTRL47 0xD34 415*4882a593Smuzhiyun #define WM2200_ANC_CTRL48 0xD35 416*4882a593Smuzhiyun #define WM2200_ANC_CTRL49 0xD36 417*4882a593Smuzhiyun #define WM2200_ANC_CTRL50 0xD37 418*4882a593Smuzhiyun #define WM2200_ANC_CTRL51 0xD38 419*4882a593Smuzhiyun #define WM2200_ANC_CTRL52 0xD39 420*4882a593Smuzhiyun #define WM2200_ANC_CTRL53 0xD3A 421*4882a593Smuzhiyun #define WM2200_ANC_CTRL54 0xD3B 422*4882a593Smuzhiyun #define WM2200_ANC_CTRL55 0xD3C 423*4882a593Smuzhiyun #define WM2200_ANC_CTRL56 0xD3D 424*4882a593Smuzhiyun #define WM2200_ANC_CTRL57 0xD3E 425*4882a593Smuzhiyun #define WM2200_ANC_CTRL58 0xD3F 426*4882a593Smuzhiyun #define WM2200_ANC_CTRL59 0xD40 427*4882a593Smuzhiyun #define WM2200_ANC_CTRL60 0xD41 428*4882a593Smuzhiyun #define WM2200_ANC_CTRL61 0xD42 429*4882a593Smuzhiyun #define WM2200_ANC_CTRL62 0xD43 430*4882a593Smuzhiyun #define WM2200_ANC_CTRL63 0xD44 431*4882a593Smuzhiyun #define WM2200_ANC_CTRL64 0xD45 432*4882a593Smuzhiyun #define WM2200_ANC_CTRL65 0xD46 433*4882a593Smuzhiyun #define WM2200_ANC_CTRL66 0xD47 434*4882a593Smuzhiyun #define WM2200_ANC_CTRL67 0xD48 435*4882a593Smuzhiyun #define WM2200_ANC_CTRL68 0xD49 436*4882a593Smuzhiyun #define WM2200_ANC_CTRL69 0xD4A 437*4882a593Smuzhiyun #define WM2200_ANC_CTRL70 0xD4B 438*4882a593Smuzhiyun #define WM2200_ANC_CTRL71 0xD4C 439*4882a593Smuzhiyun #define WM2200_ANC_CTRL72 0xD4D 440*4882a593Smuzhiyun #define WM2200_ANC_CTRL73 0xD4E 441*4882a593Smuzhiyun #define WM2200_ANC_CTRL74 0xD4F 442*4882a593Smuzhiyun #define WM2200_ANC_CTRL75 0xD50 443*4882a593Smuzhiyun #define WM2200_ANC_CTRL76 0xD51 444*4882a593Smuzhiyun #define WM2200_ANC_CTRL77 0xD52 445*4882a593Smuzhiyun #define WM2200_ANC_CTRL78 0xD53 446*4882a593Smuzhiyun #define WM2200_ANC_CTRL79 0xD54 447*4882a593Smuzhiyun #define WM2200_ANC_CTRL80 0xD55 448*4882a593Smuzhiyun #define WM2200_ANC_CTRL81 0xD56 449*4882a593Smuzhiyun #define WM2200_ANC_CTRL82 0xD57 450*4882a593Smuzhiyun #define WM2200_ANC_CTRL83 0xD58 451*4882a593Smuzhiyun #define WM2200_ANC_CTRL84 0xD5B 452*4882a593Smuzhiyun #define WM2200_ANC_CTRL85 0xD5C 453*4882a593Smuzhiyun #define WM2200_ANC_CTRL86 0xD5F 454*4882a593Smuzhiyun #define WM2200_ANC_CTRL87 0xD60 455*4882a593Smuzhiyun #define WM2200_ANC_CTRL88 0xD61 456*4882a593Smuzhiyun #define WM2200_ANC_CTRL89 0xD62 457*4882a593Smuzhiyun #define WM2200_ANC_CTRL90 0xD63 458*4882a593Smuzhiyun #define WM2200_ANC_CTRL91 0xD64 459*4882a593Smuzhiyun #define WM2200_ANC_CTRL92 0xD65 460*4882a593Smuzhiyun #define WM2200_ANC_CTRL93 0xD66 461*4882a593Smuzhiyun #define WM2200_ANC_CTRL94 0xD67 462*4882a593Smuzhiyun #define WM2200_ANC_CTRL95 0xD68 463*4882a593Smuzhiyun #define WM2200_ANC_CTRL96 0xD69 464*4882a593Smuzhiyun #define WM2200_DSP1_DM_0 0x3000 465*4882a593Smuzhiyun #define WM2200_DSP1_DM_1 0x3001 466*4882a593Smuzhiyun #define WM2200_DSP1_DM_2 0x3002 467*4882a593Smuzhiyun #define WM2200_DSP1_DM_3 0x3003 468*4882a593Smuzhiyun #define WM2200_DSP1_DM_2044 0x37FC 469*4882a593Smuzhiyun #define WM2200_DSP1_DM_2045 0x37FD 470*4882a593Smuzhiyun #define WM2200_DSP1_DM_2046 0x37FE 471*4882a593Smuzhiyun #define WM2200_DSP1_DM_2047 0x37FF 472*4882a593Smuzhiyun #define WM2200_DSP1_PM_0 0x3800 473*4882a593Smuzhiyun #define WM2200_DSP1_PM_1 0x3801 474*4882a593Smuzhiyun #define WM2200_DSP1_PM_2 0x3802 475*4882a593Smuzhiyun #define WM2200_DSP1_PM_3 0x3803 476*4882a593Smuzhiyun #define WM2200_DSP1_PM_4 0x3804 477*4882a593Smuzhiyun #define WM2200_DSP1_PM_5 0x3805 478*4882a593Smuzhiyun #define WM2200_DSP1_PM_762 0x3AFA 479*4882a593Smuzhiyun #define WM2200_DSP1_PM_763 0x3AFB 480*4882a593Smuzhiyun #define WM2200_DSP1_PM_764 0x3AFC 481*4882a593Smuzhiyun #define WM2200_DSP1_PM_765 0x3AFD 482*4882a593Smuzhiyun #define WM2200_DSP1_PM_766 0x3AFE 483*4882a593Smuzhiyun #define WM2200_DSP1_PM_767 0x3AFF 484*4882a593Smuzhiyun #define WM2200_DSP1_ZM_0 0x3C00 485*4882a593Smuzhiyun #define WM2200_DSP1_ZM_1 0x3C01 486*4882a593Smuzhiyun #define WM2200_DSP1_ZM_2 0x3C02 487*4882a593Smuzhiyun #define WM2200_DSP1_ZM_3 0x3C03 488*4882a593Smuzhiyun #define WM2200_DSP1_ZM_1020 0x3FFC 489*4882a593Smuzhiyun #define WM2200_DSP1_ZM_1021 0x3FFD 490*4882a593Smuzhiyun #define WM2200_DSP1_ZM_1022 0x3FFE 491*4882a593Smuzhiyun #define WM2200_DSP1_ZM_1023 0x3FFF 492*4882a593Smuzhiyun #define WM2200_DSP2_DM_0 0x4000 493*4882a593Smuzhiyun #define WM2200_DSP2_DM_1 0x4001 494*4882a593Smuzhiyun #define WM2200_DSP2_DM_2 0x4002 495*4882a593Smuzhiyun #define WM2200_DSP2_DM_3 0x4003 496*4882a593Smuzhiyun #define WM2200_DSP2_DM_2044 0x47FC 497*4882a593Smuzhiyun #define WM2200_DSP2_DM_2045 0x47FD 498*4882a593Smuzhiyun #define WM2200_DSP2_DM_2046 0x47FE 499*4882a593Smuzhiyun #define WM2200_DSP2_DM_2047 0x47FF 500*4882a593Smuzhiyun #define WM2200_DSP2_PM_0 0x4800 501*4882a593Smuzhiyun #define WM2200_DSP2_PM_1 0x4801 502*4882a593Smuzhiyun #define WM2200_DSP2_PM_2 0x4802 503*4882a593Smuzhiyun #define WM2200_DSP2_PM_3 0x4803 504*4882a593Smuzhiyun #define WM2200_DSP2_PM_4 0x4804 505*4882a593Smuzhiyun #define WM2200_DSP2_PM_5 0x4805 506*4882a593Smuzhiyun #define WM2200_DSP2_PM_762 0x4AFA 507*4882a593Smuzhiyun #define WM2200_DSP2_PM_763 0x4AFB 508*4882a593Smuzhiyun #define WM2200_DSP2_PM_764 0x4AFC 509*4882a593Smuzhiyun #define WM2200_DSP2_PM_765 0x4AFD 510*4882a593Smuzhiyun #define WM2200_DSP2_PM_766 0x4AFE 511*4882a593Smuzhiyun #define WM2200_DSP2_PM_767 0x4AFF 512*4882a593Smuzhiyun #define WM2200_DSP2_ZM_0 0x4C00 513*4882a593Smuzhiyun #define WM2200_DSP2_ZM_1 0x4C01 514*4882a593Smuzhiyun #define WM2200_DSP2_ZM_2 0x4C02 515*4882a593Smuzhiyun #define WM2200_DSP2_ZM_3 0x4C03 516*4882a593Smuzhiyun #define WM2200_DSP2_ZM_1020 0x4FFC 517*4882a593Smuzhiyun #define WM2200_DSP2_ZM_1021 0x4FFD 518*4882a593Smuzhiyun #define WM2200_DSP2_ZM_1022 0x4FFE 519*4882a593Smuzhiyun #define WM2200_DSP2_ZM_1023 0x4FFF 520*4882a593Smuzhiyun 521*4882a593Smuzhiyun #define WM2200_REGISTER_COUNT 494 522*4882a593Smuzhiyun #define WM2200_MAX_REGISTER 0x4FFF 523*4882a593Smuzhiyun 524*4882a593Smuzhiyun /* 525*4882a593Smuzhiyun * Field Definitions. 526*4882a593Smuzhiyun */ 527*4882a593Smuzhiyun 528*4882a593Smuzhiyun /* 529*4882a593Smuzhiyun * R0 (0x00) - software reset 530*4882a593Smuzhiyun */ 531*4882a593Smuzhiyun #define WM2200_SW_RESET_CHIP_ID1_MASK 0xFFFF /* SW_RESET_CHIP_ID1 - [15:0] */ 532*4882a593Smuzhiyun #define WM2200_SW_RESET_CHIP_ID1_SHIFT 0 /* SW_RESET_CHIP_ID1 - [15:0] */ 533*4882a593Smuzhiyun #define WM2200_SW_RESET_CHIP_ID1_WIDTH 16 /* SW_RESET_CHIP_ID1 - [15:0] */ 534*4882a593Smuzhiyun 535*4882a593Smuzhiyun /* 536*4882a593Smuzhiyun * R1 (0x01) - Device Revision 537*4882a593Smuzhiyun */ 538*4882a593Smuzhiyun #define WM2200_DEVICE_REVISION_MASK 0x000F /* DEVICE_REVISION - [3:0] */ 539*4882a593Smuzhiyun #define WM2200_DEVICE_REVISION_SHIFT 0 /* DEVICE_REVISION - [3:0] */ 540*4882a593Smuzhiyun #define WM2200_DEVICE_REVISION_WIDTH 4 /* DEVICE_REVISION - [3:0] */ 541*4882a593Smuzhiyun 542*4882a593Smuzhiyun /* 543*4882a593Smuzhiyun * R11 (0x0B) - Tone Generator 1 544*4882a593Smuzhiyun */ 545*4882a593Smuzhiyun #define WM2200_TONE_ENA 0x0001 /* TONE_ENA */ 546*4882a593Smuzhiyun #define WM2200_TONE_ENA_MASK 0x0001 /* TONE_ENA */ 547*4882a593Smuzhiyun #define WM2200_TONE_ENA_SHIFT 0 /* TONE_ENA */ 548*4882a593Smuzhiyun #define WM2200_TONE_ENA_WIDTH 1 /* TONE_ENA */ 549*4882a593Smuzhiyun 550*4882a593Smuzhiyun /* 551*4882a593Smuzhiyun * R258 (0x102) - Clocking 3 552*4882a593Smuzhiyun */ 553*4882a593Smuzhiyun #define WM2200_SYSCLK_FREQ_MASK 0x0700 /* SYSCLK_FREQ - [10:8] */ 554*4882a593Smuzhiyun #define WM2200_SYSCLK_FREQ_SHIFT 8 /* SYSCLK_FREQ - [10:8] */ 555*4882a593Smuzhiyun #define WM2200_SYSCLK_FREQ_WIDTH 3 /* SYSCLK_FREQ - [10:8] */ 556*4882a593Smuzhiyun #define WM2200_SYSCLK_ENA 0x0040 /* SYSCLK_ENA */ 557*4882a593Smuzhiyun #define WM2200_SYSCLK_ENA_MASK 0x0040 /* SYSCLK_ENA */ 558*4882a593Smuzhiyun #define WM2200_SYSCLK_ENA_SHIFT 6 /* SYSCLK_ENA */ 559*4882a593Smuzhiyun #define WM2200_SYSCLK_ENA_WIDTH 1 /* SYSCLK_ENA */ 560*4882a593Smuzhiyun #define WM2200_SYSCLK_SRC_MASK 0x000F /* SYSCLK_SRC - [3:0] */ 561*4882a593Smuzhiyun #define WM2200_SYSCLK_SRC_SHIFT 0 /* SYSCLK_SRC - [3:0] */ 562*4882a593Smuzhiyun #define WM2200_SYSCLK_SRC_WIDTH 4 /* SYSCLK_SRC - [3:0] */ 563*4882a593Smuzhiyun 564*4882a593Smuzhiyun /* 565*4882a593Smuzhiyun * R259 (0x103) - Clocking 4 566*4882a593Smuzhiyun */ 567*4882a593Smuzhiyun #define WM2200_SAMPLE_RATE_1_MASK 0x001F /* SAMPLE_RATE_1 - [4:0] */ 568*4882a593Smuzhiyun #define WM2200_SAMPLE_RATE_1_SHIFT 0 /* SAMPLE_RATE_1 - [4:0] */ 569*4882a593Smuzhiyun #define WM2200_SAMPLE_RATE_1_WIDTH 5 /* SAMPLE_RATE_1 - [4:0] */ 570*4882a593Smuzhiyun 571*4882a593Smuzhiyun /* 572*4882a593Smuzhiyun * R273 (0x111) - FLL Control 1 573*4882a593Smuzhiyun */ 574*4882a593Smuzhiyun #define WM2200_FLL_ENA 0x0001 /* FLL_ENA */ 575*4882a593Smuzhiyun #define WM2200_FLL_ENA_MASK 0x0001 /* FLL_ENA */ 576*4882a593Smuzhiyun #define WM2200_FLL_ENA_SHIFT 0 /* FLL_ENA */ 577*4882a593Smuzhiyun #define WM2200_FLL_ENA_WIDTH 1 /* FLL_ENA */ 578*4882a593Smuzhiyun 579*4882a593Smuzhiyun /* 580*4882a593Smuzhiyun * R274 (0x112) - FLL Control 2 581*4882a593Smuzhiyun */ 582*4882a593Smuzhiyun #define WM2200_FLL_OUTDIV_MASK 0x3F00 /* FLL_OUTDIV - [13:8] */ 583*4882a593Smuzhiyun #define WM2200_FLL_OUTDIV_SHIFT 8 /* FLL_OUTDIV - [13:8] */ 584*4882a593Smuzhiyun #define WM2200_FLL_OUTDIV_WIDTH 6 /* FLL_OUTDIV - [13:8] */ 585*4882a593Smuzhiyun #define WM2200_FLL_FRATIO_MASK 0x0007 /* FLL_FRATIO - [2:0] */ 586*4882a593Smuzhiyun #define WM2200_FLL_FRATIO_SHIFT 0 /* FLL_FRATIO - [2:0] */ 587*4882a593Smuzhiyun #define WM2200_FLL_FRATIO_WIDTH 3 /* FLL_FRATIO - [2:0] */ 588*4882a593Smuzhiyun 589*4882a593Smuzhiyun /* 590*4882a593Smuzhiyun * R275 (0x113) - FLL Control 3 591*4882a593Smuzhiyun */ 592*4882a593Smuzhiyun #define WM2200_FLL_FRACN_ENA 0x0001 /* FLL_FRACN_ENA */ 593*4882a593Smuzhiyun #define WM2200_FLL_FRACN_ENA_MASK 0x0001 /* FLL_FRACN_ENA */ 594*4882a593Smuzhiyun #define WM2200_FLL_FRACN_ENA_SHIFT 0 /* FLL_FRACN_ENA */ 595*4882a593Smuzhiyun #define WM2200_FLL_FRACN_ENA_WIDTH 1 /* FLL_FRACN_ENA */ 596*4882a593Smuzhiyun 597*4882a593Smuzhiyun /* 598*4882a593Smuzhiyun * R276 (0x114) - FLL Control 4 599*4882a593Smuzhiyun */ 600*4882a593Smuzhiyun #define WM2200_FLL_THETA_MASK 0xFFFF /* FLL_THETA - [15:0] */ 601*4882a593Smuzhiyun #define WM2200_FLL_THETA_SHIFT 0 /* FLL_THETA - [15:0] */ 602*4882a593Smuzhiyun #define WM2200_FLL_THETA_WIDTH 16 /* FLL_THETA - [15:0] */ 603*4882a593Smuzhiyun 604*4882a593Smuzhiyun /* 605*4882a593Smuzhiyun * R278 (0x116) - FLL Control 6 606*4882a593Smuzhiyun */ 607*4882a593Smuzhiyun #define WM2200_FLL_N_MASK 0x03FF /* FLL_N - [9:0] */ 608*4882a593Smuzhiyun #define WM2200_FLL_N_SHIFT 0 /* FLL_N - [9:0] */ 609*4882a593Smuzhiyun #define WM2200_FLL_N_WIDTH 10 /* FLL_N - [9:0] */ 610*4882a593Smuzhiyun 611*4882a593Smuzhiyun /* 612*4882a593Smuzhiyun * R279 (0x117) - FLL Control 7 613*4882a593Smuzhiyun */ 614*4882a593Smuzhiyun #define WM2200_FLL_CLK_REF_DIV_MASK 0x0030 /* FLL_CLK_REF_DIV - [5:4] */ 615*4882a593Smuzhiyun #define WM2200_FLL_CLK_REF_DIV_SHIFT 4 /* FLL_CLK_REF_DIV - [5:4] */ 616*4882a593Smuzhiyun #define WM2200_FLL_CLK_REF_DIV_WIDTH 2 /* FLL_CLK_REF_DIV - [5:4] */ 617*4882a593Smuzhiyun #define WM2200_FLL_CLK_REF_SRC_MASK 0x0003 /* FLL_CLK_REF_SRC - [1:0] */ 618*4882a593Smuzhiyun #define WM2200_FLL_CLK_REF_SRC_SHIFT 0 /* FLL_CLK_REF_SRC - [1:0] */ 619*4882a593Smuzhiyun #define WM2200_FLL_CLK_REF_SRC_WIDTH 2 /* FLL_CLK_REF_SRC - [1:0] */ 620*4882a593Smuzhiyun 621*4882a593Smuzhiyun /* 622*4882a593Smuzhiyun * R281 (0x119) - FLL EFS 1 623*4882a593Smuzhiyun */ 624*4882a593Smuzhiyun #define WM2200_FLL_LAMBDA_MASK 0xFFFF /* FLL_LAMBDA - [15:0] */ 625*4882a593Smuzhiyun #define WM2200_FLL_LAMBDA_SHIFT 0 /* FLL_LAMBDA - [15:0] */ 626*4882a593Smuzhiyun #define WM2200_FLL_LAMBDA_WIDTH 16 /* FLL_LAMBDA - [15:0] */ 627*4882a593Smuzhiyun 628*4882a593Smuzhiyun /* 629*4882a593Smuzhiyun * R282 (0x11A) - FLL EFS 2 630*4882a593Smuzhiyun */ 631*4882a593Smuzhiyun #define WM2200_FLL_EFS_ENA 0x0001 /* FLL_EFS_ENA */ 632*4882a593Smuzhiyun #define WM2200_FLL_EFS_ENA_MASK 0x0001 /* FLL_EFS_ENA */ 633*4882a593Smuzhiyun #define WM2200_FLL_EFS_ENA_SHIFT 0 /* FLL_EFS_ENA */ 634*4882a593Smuzhiyun #define WM2200_FLL_EFS_ENA_WIDTH 1 /* FLL_EFS_ENA */ 635*4882a593Smuzhiyun 636*4882a593Smuzhiyun /* 637*4882a593Smuzhiyun * R512 (0x200) - Mic Charge Pump 1 638*4882a593Smuzhiyun */ 639*4882a593Smuzhiyun #define WM2200_CPMIC_BYPASS_MODE 0x0020 /* CPMIC_BYPASS_MODE */ 640*4882a593Smuzhiyun #define WM2200_CPMIC_BYPASS_MODE_MASK 0x0020 /* CPMIC_BYPASS_MODE */ 641*4882a593Smuzhiyun #define WM2200_CPMIC_BYPASS_MODE_SHIFT 5 /* CPMIC_BYPASS_MODE */ 642*4882a593Smuzhiyun #define WM2200_CPMIC_BYPASS_MODE_WIDTH 1 /* CPMIC_BYPASS_MODE */ 643*4882a593Smuzhiyun #define WM2200_CPMIC_ENA 0x0001 /* CPMIC_ENA */ 644*4882a593Smuzhiyun #define WM2200_CPMIC_ENA_MASK 0x0001 /* CPMIC_ENA */ 645*4882a593Smuzhiyun #define WM2200_CPMIC_ENA_SHIFT 0 /* CPMIC_ENA */ 646*4882a593Smuzhiyun #define WM2200_CPMIC_ENA_WIDTH 1 /* CPMIC_ENA */ 647*4882a593Smuzhiyun 648*4882a593Smuzhiyun /* 649*4882a593Smuzhiyun * R513 (0x201) - Mic Charge Pump 2 650*4882a593Smuzhiyun */ 651*4882a593Smuzhiyun #define WM2200_CPMIC_LDO_VSEL_OVERRIDE_MASK 0xF800 /* CPMIC_LDO_VSEL_OVERRIDE - [15:11] */ 652*4882a593Smuzhiyun #define WM2200_CPMIC_LDO_VSEL_OVERRIDE_SHIFT 11 /* CPMIC_LDO_VSEL_OVERRIDE - [15:11] */ 653*4882a593Smuzhiyun #define WM2200_CPMIC_LDO_VSEL_OVERRIDE_WIDTH 5 /* CPMIC_LDO_VSEL_OVERRIDE - [15:11] */ 654*4882a593Smuzhiyun 655*4882a593Smuzhiyun /* 656*4882a593Smuzhiyun * R514 (0x202) - DM Charge Pump 1 657*4882a593Smuzhiyun */ 658*4882a593Smuzhiyun #define WM2200_CPDM_ENA 0x0001 /* CPDM_ENA */ 659*4882a593Smuzhiyun #define WM2200_CPDM_ENA_MASK 0x0001 /* CPDM_ENA */ 660*4882a593Smuzhiyun #define WM2200_CPDM_ENA_SHIFT 0 /* CPDM_ENA */ 661*4882a593Smuzhiyun #define WM2200_CPDM_ENA_WIDTH 1 /* CPDM_ENA */ 662*4882a593Smuzhiyun 663*4882a593Smuzhiyun /* 664*4882a593Smuzhiyun * R524 (0x20C) - Mic Bias Ctrl 1 665*4882a593Smuzhiyun */ 666*4882a593Smuzhiyun #define WM2200_MICB1_DISCH 0x0040 /* MICB1_DISCH */ 667*4882a593Smuzhiyun #define WM2200_MICB1_DISCH_MASK 0x0040 /* MICB1_DISCH */ 668*4882a593Smuzhiyun #define WM2200_MICB1_DISCH_SHIFT 6 /* MICB1_DISCH */ 669*4882a593Smuzhiyun #define WM2200_MICB1_DISCH_WIDTH 1 /* MICB1_DISCH */ 670*4882a593Smuzhiyun #define WM2200_MICB1_RATE 0x0020 /* MICB1_RATE */ 671*4882a593Smuzhiyun #define WM2200_MICB1_RATE_MASK 0x0020 /* MICB1_RATE */ 672*4882a593Smuzhiyun #define WM2200_MICB1_RATE_SHIFT 5 /* MICB1_RATE */ 673*4882a593Smuzhiyun #define WM2200_MICB1_RATE_WIDTH 1 /* MICB1_RATE */ 674*4882a593Smuzhiyun #define WM2200_MICB1_LVL_MASK 0x001C /* MICB1_LVL - [4:2] */ 675*4882a593Smuzhiyun #define WM2200_MICB1_LVL_SHIFT 2 /* MICB1_LVL - [4:2] */ 676*4882a593Smuzhiyun #define WM2200_MICB1_LVL_WIDTH 3 /* MICB1_LVL - [4:2] */ 677*4882a593Smuzhiyun #define WM2200_MICB1_MODE 0x0002 /* MICB1_MODE */ 678*4882a593Smuzhiyun #define WM2200_MICB1_MODE_MASK 0x0002 /* MICB1_MODE */ 679*4882a593Smuzhiyun #define WM2200_MICB1_MODE_SHIFT 1 /* MICB1_MODE */ 680*4882a593Smuzhiyun #define WM2200_MICB1_MODE_WIDTH 1 /* MICB1_MODE */ 681*4882a593Smuzhiyun #define WM2200_MICB1_ENA 0x0001 /* MICB1_ENA */ 682*4882a593Smuzhiyun #define WM2200_MICB1_ENA_MASK 0x0001 /* MICB1_ENA */ 683*4882a593Smuzhiyun #define WM2200_MICB1_ENA_SHIFT 0 /* MICB1_ENA */ 684*4882a593Smuzhiyun #define WM2200_MICB1_ENA_WIDTH 1 /* MICB1_ENA */ 685*4882a593Smuzhiyun 686*4882a593Smuzhiyun /* 687*4882a593Smuzhiyun * R525 (0x20D) - Mic Bias Ctrl 2 688*4882a593Smuzhiyun */ 689*4882a593Smuzhiyun #define WM2200_MICB2_DISCH 0x0040 /* MICB2_DISCH */ 690*4882a593Smuzhiyun #define WM2200_MICB2_DISCH_MASK 0x0040 /* MICB2_DISCH */ 691*4882a593Smuzhiyun #define WM2200_MICB2_DISCH_SHIFT 6 /* MICB2_DISCH */ 692*4882a593Smuzhiyun #define WM2200_MICB2_DISCH_WIDTH 1 /* MICB2_DISCH */ 693*4882a593Smuzhiyun #define WM2200_MICB2_RATE 0x0020 /* MICB2_RATE */ 694*4882a593Smuzhiyun #define WM2200_MICB2_RATE_MASK 0x0020 /* MICB2_RATE */ 695*4882a593Smuzhiyun #define WM2200_MICB2_RATE_SHIFT 5 /* MICB2_RATE */ 696*4882a593Smuzhiyun #define WM2200_MICB2_RATE_WIDTH 1 /* MICB2_RATE */ 697*4882a593Smuzhiyun #define WM2200_MICB2_LVL_MASK 0x001C /* MICB2_LVL - [4:2] */ 698*4882a593Smuzhiyun #define WM2200_MICB2_LVL_SHIFT 2 /* MICB2_LVL - [4:2] */ 699*4882a593Smuzhiyun #define WM2200_MICB2_LVL_WIDTH 3 /* MICB2_LVL - [4:2] */ 700*4882a593Smuzhiyun #define WM2200_MICB2_MODE 0x0002 /* MICB2_MODE */ 701*4882a593Smuzhiyun #define WM2200_MICB2_MODE_MASK 0x0002 /* MICB2_MODE */ 702*4882a593Smuzhiyun #define WM2200_MICB2_MODE_SHIFT 1 /* MICB2_MODE */ 703*4882a593Smuzhiyun #define WM2200_MICB2_MODE_WIDTH 1 /* MICB2_MODE */ 704*4882a593Smuzhiyun #define WM2200_MICB2_ENA 0x0001 /* MICB2_ENA */ 705*4882a593Smuzhiyun #define WM2200_MICB2_ENA_MASK 0x0001 /* MICB2_ENA */ 706*4882a593Smuzhiyun #define WM2200_MICB2_ENA_SHIFT 0 /* MICB2_ENA */ 707*4882a593Smuzhiyun #define WM2200_MICB2_ENA_WIDTH 1 /* MICB2_ENA */ 708*4882a593Smuzhiyun 709*4882a593Smuzhiyun /* 710*4882a593Smuzhiyun * R527 (0x20F) - Ear Piece Ctrl 1 711*4882a593Smuzhiyun */ 712*4882a593Smuzhiyun #define WM2200_EPD_LP_ENA 0x4000 /* EPD_LP_ENA */ 713*4882a593Smuzhiyun #define WM2200_EPD_LP_ENA_MASK 0x4000 /* EPD_LP_ENA */ 714*4882a593Smuzhiyun #define WM2200_EPD_LP_ENA_SHIFT 14 /* EPD_LP_ENA */ 715*4882a593Smuzhiyun #define WM2200_EPD_LP_ENA_WIDTH 1 /* EPD_LP_ENA */ 716*4882a593Smuzhiyun #define WM2200_EPD_OUTP_LP_ENA 0x2000 /* EPD_OUTP_LP_ENA */ 717*4882a593Smuzhiyun #define WM2200_EPD_OUTP_LP_ENA_MASK 0x2000 /* EPD_OUTP_LP_ENA */ 718*4882a593Smuzhiyun #define WM2200_EPD_OUTP_LP_ENA_SHIFT 13 /* EPD_OUTP_LP_ENA */ 719*4882a593Smuzhiyun #define WM2200_EPD_OUTP_LP_ENA_WIDTH 1 /* EPD_OUTP_LP_ENA */ 720*4882a593Smuzhiyun #define WM2200_EPD_RMV_SHRT_LP 0x1000 /* EPD_RMV_SHRT_LP */ 721*4882a593Smuzhiyun #define WM2200_EPD_RMV_SHRT_LP_MASK 0x1000 /* EPD_RMV_SHRT_LP */ 722*4882a593Smuzhiyun #define WM2200_EPD_RMV_SHRT_LP_SHIFT 12 /* EPD_RMV_SHRT_LP */ 723*4882a593Smuzhiyun #define WM2200_EPD_RMV_SHRT_LP_WIDTH 1 /* EPD_RMV_SHRT_LP */ 724*4882a593Smuzhiyun #define WM2200_EPD_LN_ENA 0x0800 /* EPD_LN_ENA */ 725*4882a593Smuzhiyun #define WM2200_EPD_LN_ENA_MASK 0x0800 /* EPD_LN_ENA */ 726*4882a593Smuzhiyun #define WM2200_EPD_LN_ENA_SHIFT 11 /* EPD_LN_ENA */ 727*4882a593Smuzhiyun #define WM2200_EPD_LN_ENA_WIDTH 1 /* EPD_LN_ENA */ 728*4882a593Smuzhiyun #define WM2200_EPD_OUTP_LN_ENA 0x0400 /* EPD_OUTP_LN_ENA */ 729*4882a593Smuzhiyun #define WM2200_EPD_OUTP_LN_ENA_MASK 0x0400 /* EPD_OUTP_LN_ENA */ 730*4882a593Smuzhiyun #define WM2200_EPD_OUTP_LN_ENA_SHIFT 10 /* EPD_OUTP_LN_ENA */ 731*4882a593Smuzhiyun #define WM2200_EPD_OUTP_LN_ENA_WIDTH 1 /* EPD_OUTP_LN_ENA */ 732*4882a593Smuzhiyun #define WM2200_EPD_RMV_SHRT_LN 0x0200 /* EPD_RMV_SHRT_LN */ 733*4882a593Smuzhiyun #define WM2200_EPD_RMV_SHRT_LN_MASK 0x0200 /* EPD_RMV_SHRT_LN */ 734*4882a593Smuzhiyun #define WM2200_EPD_RMV_SHRT_LN_SHIFT 9 /* EPD_RMV_SHRT_LN */ 735*4882a593Smuzhiyun #define WM2200_EPD_RMV_SHRT_LN_WIDTH 1 /* EPD_RMV_SHRT_LN */ 736*4882a593Smuzhiyun 737*4882a593Smuzhiyun /* 738*4882a593Smuzhiyun * R528 (0x210) - Ear Piece Ctrl 2 739*4882a593Smuzhiyun */ 740*4882a593Smuzhiyun #define WM2200_EPD_RP_ENA 0x4000 /* EPD_RP_ENA */ 741*4882a593Smuzhiyun #define WM2200_EPD_RP_ENA_MASK 0x4000 /* EPD_RP_ENA */ 742*4882a593Smuzhiyun #define WM2200_EPD_RP_ENA_SHIFT 14 /* EPD_RP_ENA */ 743*4882a593Smuzhiyun #define WM2200_EPD_RP_ENA_WIDTH 1 /* EPD_RP_ENA */ 744*4882a593Smuzhiyun #define WM2200_EPD_OUTP_RP_ENA 0x2000 /* EPD_OUTP_RP_ENA */ 745*4882a593Smuzhiyun #define WM2200_EPD_OUTP_RP_ENA_MASK 0x2000 /* EPD_OUTP_RP_ENA */ 746*4882a593Smuzhiyun #define WM2200_EPD_OUTP_RP_ENA_SHIFT 13 /* EPD_OUTP_RP_ENA */ 747*4882a593Smuzhiyun #define WM2200_EPD_OUTP_RP_ENA_WIDTH 1 /* EPD_OUTP_RP_ENA */ 748*4882a593Smuzhiyun #define WM2200_EPD_RMV_SHRT_RP 0x1000 /* EPD_RMV_SHRT_RP */ 749*4882a593Smuzhiyun #define WM2200_EPD_RMV_SHRT_RP_MASK 0x1000 /* EPD_RMV_SHRT_RP */ 750*4882a593Smuzhiyun #define WM2200_EPD_RMV_SHRT_RP_SHIFT 12 /* EPD_RMV_SHRT_RP */ 751*4882a593Smuzhiyun #define WM2200_EPD_RMV_SHRT_RP_WIDTH 1 /* EPD_RMV_SHRT_RP */ 752*4882a593Smuzhiyun #define WM2200_EPD_RN_ENA 0x0800 /* EPD_RN_ENA */ 753*4882a593Smuzhiyun #define WM2200_EPD_RN_ENA_MASK 0x0800 /* EPD_RN_ENA */ 754*4882a593Smuzhiyun #define WM2200_EPD_RN_ENA_SHIFT 11 /* EPD_RN_ENA */ 755*4882a593Smuzhiyun #define WM2200_EPD_RN_ENA_WIDTH 1 /* EPD_RN_ENA */ 756*4882a593Smuzhiyun #define WM2200_EPD_OUTP_RN_ENA 0x0400 /* EPD_OUTP_RN_ENA */ 757*4882a593Smuzhiyun #define WM2200_EPD_OUTP_RN_ENA_MASK 0x0400 /* EPD_OUTP_RN_ENA */ 758*4882a593Smuzhiyun #define WM2200_EPD_OUTP_RN_ENA_SHIFT 10 /* EPD_OUTP_RN_ENA */ 759*4882a593Smuzhiyun #define WM2200_EPD_OUTP_RN_ENA_WIDTH 1 /* EPD_OUTP_RN_ENA */ 760*4882a593Smuzhiyun #define WM2200_EPD_RMV_SHRT_RN 0x0200 /* EPD_RMV_SHRT_RN */ 761*4882a593Smuzhiyun #define WM2200_EPD_RMV_SHRT_RN_MASK 0x0200 /* EPD_RMV_SHRT_RN */ 762*4882a593Smuzhiyun #define WM2200_EPD_RMV_SHRT_RN_SHIFT 9 /* EPD_RMV_SHRT_RN */ 763*4882a593Smuzhiyun #define WM2200_EPD_RMV_SHRT_RN_WIDTH 1 /* EPD_RMV_SHRT_RN */ 764*4882a593Smuzhiyun 765*4882a593Smuzhiyun /* 766*4882a593Smuzhiyun * R769 (0x301) - Input Enables 767*4882a593Smuzhiyun */ 768*4882a593Smuzhiyun #define WM2200_IN3L_ENA 0x0020 /* IN3L_ENA */ 769*4882a593Smuzhiyun #define WM2200_IN3L_ENA_MASK 0x0020 /* IN3L_ENA */ 770*4882a593Smuzhiyun #define WM2200_IN3L_ENA_SHIFT 5 /* IN3L_ENA */ 771*4882a593Smuzhiyun #define WM2200_IN3L_ENA_WIDTH 1 /* IN3L_ENA */ 772*4882a593Smuzhiyun #define WM2200_IN3R_ENA 0x0010 /* IN3R_ENA */ 773*4882a593Smuzhiyun #define WM2200_IN3R_ENA_MASK 0x0010 /* IN3R_ENA */ 774*4882a593Smuzhiyun #define WM2200_IN3R_ENA_SHIFT 4 /* IN3R_ENA */ 775*4882a593Smuzhiyun #define WM2200_IN3R_ENA_WIDTH 1 /* IN3R_ENA */ 776*4882a593Smuzhiyun #define WM2200_IN2L_ENA 0x0008 /* IN2L_ENA */ 777*4882a593Smuzhiyun #define WM2200_IN2L_ENA_MASK 0x0008 /* IN2L_ENA */ 778*4882a593Smuzhiyun #define WM2200_IN2L_ENA_SHIFT 3 /* IN2L_ENA */ 779*4882a593Smuzhiyun #define WM2200_IN2L_ENA_WIDTH 1 /* IN2L_ENA */ 780*4882a593Smuzhiyun #define WM2200_IN2R_ENA 0x0004 /* IN2R_ENA */ 781*4882a593Smuzhiyun #define WM2200_IN2R_ENA_MASK 0x0004 /* IN2R_ENA */ 782*4882a593Smuzhiyun #define WM2200_IN2R_ENA_SHIFT 2 /* IN2R_ENA */ 783*4882a593Smuzhiyun #define WM2200_IN2R_ENA_WIDTH 1 /* IN2R_ENA */ 784*4882a593Smuzhiyun #define WM2200_IN1L_ENA 0x0002 /* IN1L_ENA */ 785*4882a593Smuzhiyun #define WM2200_IN1L_ENA_MASK 0x0002 /* IN1L_ENA */ 786*4882a593Smuzhiyun #define WM2200_IN1L_ENA_SHIFT 1 /* IN1L_ENA */ 787*4882a593Smuzhiyun #define WM2200_IN1L_ENA_WIDTH 1 /* IN1L_ENA */ 788*4882a593Smuzhiyun #define WM2200_IN1R_ENA 0x0001 /* IN1R_ENA */ 789*4882a593Smuzhiyun #define WM2200_IN1R_ENA_MASK 0x0001 /* IN1R_ENA */ 790*4882a593Smuzhiyun #define WM2200_IN1R_ENA_SHIFT 0 /* IN1R_ENA */ 791*4882a593Smuzhiyun #define WM2200_IN1R_ENA_WIDTH 1 /* IN1R_ENA */ 792*4882a593Smuzhiyun 793*4882a593Smuzhiyun /* 794*4882a593Smuzhiyun * R770 (0x302) - IN1L Control 795*4882a593Smuzhiyun */ 796*4882a593Smuzhiyun #define WM2200_IN1_OSR 0x2000 /* IN1_OSR */ 797*4882a593Smuzhiyun #define WM2200_IN1_OSR_MASK 0x2000 /* IN1_OSR */ 798*4882a593Smuzhiyun #define WM2200_IN1_OSR_SHIFT 13 /* IN1_OSR */ 799*4882a593Smuzhiyun #define WM2200_IN1_OSR_WIDTH 1 /* IN1_OSR */ 800*4882a593Smuzhiyun #define WM2200_IN1_DMIC_SUP_MASK 0x1800 /* IN1_DMIC_SUP - [12:11] */ 801*4882a593Smuzhiyun #define WM2200_IN1_DMIC_SUP_SHIFT 11 /* IN1_DMIC_SUP - [12:11] */ 802*4882a593Smuzhiyun #define WM2200_IN1_DMIC_SUP_WIDTH 2 /* IN1_DMIC_SUP - [12:11] */ 803*4882a593Smuzhiyun #define WM2200_IN1_MODE_MASK 0x0600 /* IN1_MODE - [10:9] */ 804*4882a593Smuzhiyun #define WM2200_IN1_MODE_SHIFT 9 /* IN1_MODE - [10:9] */ 805*4882a593Smuzhiyun #define WM2200_IN1_MODE_WIDTH 2 /* IN1_MODE - [10:9] */ 806*4882a593Smuzhiyun #define WM2200_IN1L_PGA_VOL_MASK 0x00FE /* IN1L_PGA_VOL - [7:1] */ 807*4882a593Smuzhiyun #define WM2200_IN1L_PGA_VOL_SHIFT 1 /* IN1L_PGA_VOL - [7:1] */ 808*4882a593Smuzhiyun #define WM2200_IN1L_PGA_VOL_WIDTH 7 /* IN1L_PGA_VOL - [7:1] */ 809*4882a593Smuzhiyun 810*4882a593Smuzhiyun /* 811*4882a593Smuzhiyun * R771 (0x303) - IN1R Control 812*4882a593Smuzhiyun */ 813*4882a593Smuzhiyun #define WM2200_IN1R_PGA_VOL_MASK 0x00FE /* IN1R_PGA_VOL - [7:1] */ 814*4882a593Smuzhiyun #define WM2200_IN1R_PGA_VOL_SHIFT 1 /* IN1R_PGA_VOL - [7:1] */ 815*4882a593Smuzhiyun #define WM2200_IN1R_PGA_VOL_WIDTH 7 /* IN1R_PGA_VOL - [7:1] */ 816*4882a593Smuzhiyun 817*4882a593Smuzhiyun /* 818*4882a593Smuzhiyun * R772 (0x304) - IN2L Control 819*4882a593Smuzhiyun */ 820*4882a593Smuzhiyun #define WM2200_IN2_OSR 0x2000 /* IN2_OSR */ 821*4882a593Smuzhiyun #define WM2200_IN2_OSR_MASK 0x2000 /* IN2_OSR */ 822*4882a593Smuzhiyun #define WM2200_IN2_OSR_SHIFT 13 /* IN2_OSR */ 823*4882a593Smuzhiyun #define WM2200_IN2_OSR_WIDTH 1 /* IN2_OSR */ 824*4882a593Smuzhiyun #define WM2200_IN2_DMIC_SUP_MASK 0x1800 /* IN2_DMIC_SUP - [12:11] */ 825*4882a593Smuzhiyun #define WM2200_IN2_DMIC_SUP_SHIFT 11 /* IN2_DMIC_SUP - [12:11] */ 826*4882a593Smuzhiyun #define WM2200_IN2_DMIC_SUP_WIDTH 2 /* IN2_DMIC_SUP - [12:11] */ 827*4882a593Smuzhiyun #define WM2200_IN2_MODE_MASK 0x0600 /* IN2_MODE - [10:9] */ 828*4882a593Smuzhiyun #define WM2200_IN2_MODE_SHIFT 9 /* IN2_MODE - [10:9] */ 829*4882a593Smuzhiyun #define WM2200_IN2_MODE_WIDTH 2 /* IN2_MODE - [10:9] */ 830*4882a593Smuzhiyun #define WM2200_IN2L_PGA_VOL_MASK 0x00FE /* IN2L_PGA_VOL - [7:1] */ 831*4882a593Smuzhiyun #define WM2200_IN2L_PGA_VOL_SHIFT 1 /* IN2L_PGA_VOL - [7:1] */ 832*4882a593Smuzhiyun #define WM2200_IN2L_PGA_VOL_WIDTH 7 /* IN2L_PGA_VOL - [7:1] */ 833*4882a593Smuzhiyun 834*4882a593Smuzhiyun /* 835*4882a593Smuzhiyun * R773 (0x305) - IN2R Control 836*4882a593Smuzhiyun */ 837*4882a593Smuzhiyun #define WM2200_IN2R_PGA_VOL_MASK 0x00FE /* IN2R_PGA_VOL - [7:1] */ 838*4882a593Smuzhiyun #define WM2200_IN2R_PGA_VOL_SHIFT 1 /* IN2R_PGA_VOL - [7:1] */ 839*4882a593Smuzhiyun #define WM2200_IN2R_PGA_VOL_WIDTH 7 /* IN2R_PGA_VOL - [7:1] */ 840*4882a593Smuzhiyun 841*4882a593Smuzhiyun /* 842*4882a593Smuzhiyun * R774 (0x306) - IN3L Control 843*4882a593Smuzhiyun */ 844*4882a593Smuzhiyun #define WM2200_IN3_OSR 0x2000 /* IN3_OSR */ 845*4882a593Smuzhiyun #define WM2200_IN3_OSR_MASK 0x2000 /* IN3_OSR */ 846*4882a593Smuzhiyun #define WM2200_IN3_OSR_SHIFT 13 /* IN3_OSR */ 847*4882a593Smuzhiyun #define WM2200_IN3_OSR_WIDTH 1 /* IN3_OSR */ 848*4882a593Smuzhiyun #define WM2200_IN3_DMIC_SUP_MASK 0x1800 /* IN3_DMIC_SUP - [12:11] */ 849*4882a593Smuzhiyun #define WM2200_IN3_DMIC_SUP_SHIFT 11 /* IN3_DMIC_SUP - [12:11] */ 850*4882a593Smuzhiyun #define WM2200_IN3_DMIC_SUP_WIDTH 2 /* IN3_DMIC_SUP - [12:11] */ 851*4882a593Smuzhiyun #define WM2200_IN3_MODE_MASK 0x0600 /* IN3_MODE - [10:9] */ 852*4882a593Smuzhiyun #define WM2200_IN3_MODE_SHIFT 9 /* IN3_MODE - [10:9] */ 853*4882a593Smuzhiyun #define WM2200_IN3_MODE_WIDTH 2 /* IN3_MODE - [10:9] */ 854*4882a593Smuzhiyun #define WM2200_IN3L_PGA_VOL_MASK 0x00FE /* IN3L_PGA_VOL - [7:1] */ 855*4882a593Smuzhiyun #define WM2200_IN3L_PGA_VOL_SHIFT 1 /* IN3L_PGA_VOL - [7:1] */ 856*4882a593Smuzhiyun #define WM2200_IN3L_PGA_VOL_WIDTH 7 /* IN3L_PGA_VOL - [7:1] */ 857*4882a593Smuzhiyun 858*4882a593Smuzhiyun /* 859*4882a593Smuzhiyun * R775 (0x307) - IN3R Control 860*4882a593Smuzhiyun */ 861*4882a593Smuzhiyun #define WM2200_IN3R_PGA_VOL_MASK 0x00FE /* IN3R_PGA_VOL - [7:1] */ 862*4882a593Smuzhiyun #define WM2200_IN3R_PGA_VOL_SHIFT 1 /* IN3R_PGA_VOL - [7:1] */ 863*4882a593Smuzhiyun #define WM2200_IN3R_PGA_VOL_WIDTH 7 /* IN3R_PGA_VOL - [7:1] */ 864*4882a593Smuzhiyun 865*4882a593Smuzhiyun /* 866*4882a593Smuzhiyun * R778 (0x30A) - RXANC_SRC 867*4882a593Smuzhiyun */ 868*4882a593Smuzhiyun #define WM2200_IN_RXANC_SEL_MASK 0x0007 /* IN_RXANC_SEL - [2:0] */ 869*4882a593Smuzhiyun #define WM2200_IN_RXANC_SEL_SHIFT 0 /* IN_RXANC_SEL - [2:0] */ 870*4882a593Smuzhiyun #define WM2200_IN_RXANC_SEL_WIDTH 3 /* IN_RXANC_SEL - [2:0] */ 871*4882a593Smuzhiyun 872*4882a593Smuzhiyun /* 873*4882a593Smuzhiyun * R779 (0x30B) - Input Volume Ramp 874*4882a593Smuzhiyun */ 875*4882a593Smuzhiyun #define WM2200_IN_VD_RAMP_MASK 0x0070 /* IN_VD_RAMP - [6:4] */ 876*4882a593Smuzhiyun #define WM2200_IN_VD_RAMP_SHIFT 4 /* IN_VD_RAMP - [6:4] */ 877*4882a593Smuzhiyun #define WM2200_IN_VD_RAMP_WIDTH 3 /* IN_VD_RAMP - [6:4] */ 878*4882a593Smuzhiyun #define WM2200_IN_VI_RAMP_MASK 0x0007 /* IN_VI_RAMP - [2:0] */ 879*4882a593Smuzhiyun #define WM2200_IN_VI_RAMP_SHIFT 0 /* IN_VI_RAMP - [2:0] */ 880*4882a593Smuzhiyun #define WM2200_IN_VI_RAMP_WIDTH 3 /* IN_VI_RAMP - [2:0] */ 881*4882a593Smuzhiyun 882*4882a593Smuzhiyun /* 883*4882a593Smuzhiyun * R780 (0x30C) - ADC Digital Volume 1L 884*4882a593Smuzhiyun */ 885*4882a593Smuzhiyun #define WM2200_IN_VU 0x0200 /* IN_VU */ 886*4882a593Smuzhiyun #define WM2200_IN_VU_MASK 0x0200 /* IN_VU */ 887*4882a593Smuzhiyun #define WM2200_IN_VU_SHIFT 9 /* IN_VU */ 888*4882a593Smuzhiyun #define WM2200_IN_VU_WIDTH 1 /* IN_VU */ 889*4882a593Smuzhiyun #define WM2200_IN1L_MUTE 0x0100 /* IN1L_MUTE */ 890*4882a593Smuzhiyun #define WM2200_IN1L_MUTE_MASK 0x0100 /* IN1L_MUTE */ 891*4882a593Smuzhiyun #define WM2200_IN1L_MUTE_SHIFT 8 /* IN1L_MUTE */ 892*4882a593Smuzhiyun #define WM2200_IN1L_MUTE_WIDTH 1 /* IN1L_MUTE */ 893*4882a593Smuzhiyun #define WM2200_IN1L_DIG_VOL_MASK 0x00FF /* IN1L_DIG_VOL - [7:0] */ 894*4882a593Smuzhiyun #define WM2200_IN1L_DIG_VOL_SHIFT 0 /* IN1L_DIG_VOL - [7:0] */ 895*4882a593Smuzhiyun #define WM2200_IN1L_DIG_VOL_WIDTH 8 /* IN1L_DIG_VOL - [7:0] */ 896*4882a593Smuzhiyun 897*4882a593Smuzhiyun /* 898*4882a593Smuzhiyun * R781 (0x30D) - ADC Digital Volume 1R 899*4882a593Smuzhiyun */ 900*4882a593Smuzhiyun #define WM2200_IN_VU 0x0200 /* IN_VU */ 901*4882a593Smuzhiyun #define WM2200_IN_VU_MASK 0x0200 /* IN_VU */ 902*4882a593Smuzhiyun #define WM2200_IN_VU_SHIFT 9 /* IN_VU */ 903*4882a593Smuzhiyun #define WM2200_IN_VU_WIDTH 1 /* IN_VU */ 904*4882a593Smuzhiyun #define WM2200_IN1R_MUTE 0x0100 /* IN1R_MUTE */ 905*4882a593Smuzhiyun #define WM2200_IN1R_MUTE_MASK 0x0100 /* IN1R_MUTE */ 906*4882a593Smuzhiyun #define WM2200_IN1R_MUTE_SHIFT 8 /* IN1R_MUTE */ 907*4882a593Smuzhiyun #define WM2200_IN1R_MUTE_WIDTH 1 /* IN1R_MUTE */ 908*4882a593Smuzhiyun #define WM2200_IN1R_DIG_VOL_MASK 0x00FF /* IN1R_DIG_VOL - [7:0] */ 909*4882a593Smuzhiyun #define WM2200_IN1R_DIG_VOL_SHIFT 0 /* IN1R_DIG_VOL - [7:0] */ 910*4882a593Smuzhiyun #define WM2200_IN1R_DIG_VOL_WIDTH 8 /* IN1R_DIG_VOL - [7:0] */ 911*4882a593Smuzhiyun 912*4882a593Smuzhiyun /* 913*4882a593Smuzhiyun * R782 (0x30E) - ADC Digital Volume 2L 914*4882a593Smuzhiyun */ 915*4882a593Smuzhiyun #define WM2200_IN_VU 0x0200 /* IN_VU */ 916*4882a593Smuzhiyun #define WM2200_IN_VU_MASK 0x0200 /* IN_VU */ 917*4882a593Smuzhiyun #define WM2200_IN_VU_SHIFT 9 /* IN_VU */ 918*4882a593Smuzhiyun #define WM2200_IN_VU_WIDTH 1 /* IN_VU */ 919*4882a593Smuzhiyun #define WM2200_IN2L_MUTE 0x0100 /* IN2L_MUTE */ 920*4882a593Smuzhiyun #define WM2200_IN2L_MUTE_MASK 0x0100 /* IN2L_MUTE */ 921*4882a593Smuzhiyun #define WM2200_IN2L_MUTE_SHIFT 8 /* IN2L_MUTE */ 922*4882a593Smuzhiyun #define WM2200_IN2L_MUTE_WIDTH 1 /* IN2L_MUTE */ 923*4882a593Smuzhiyun #define WM2200_IN2L_DIG_VOL_MASK 0x00FF /* IN2L_DIG_VOL - [7:0] */ 924*4882a593Smuzhiyun #define WM2200_IN2L_DIG_VOL_SHIFT 0 /* IN2L_DIG_VOL - [7:0] */ 925*4882a593Smuzhiyun #define WM2200_IN2L_DIG_VOL_WIDTH 8 /* IN2L_DIG_VOL - [7:0] */ 926*4882a593Smuzhiyun 927*4882a593Smuzhiyun /* 928*4882a593Smuzhiyun * R783 (0x30F) - ADC Digital Volume 2R 929*4882a593Smuzhiyun */ 930*4882a593Smuzhiyun #define WM2200_IN_VU 0x0200 /* IN_VU */ 931*4882a593Smuzhiyun #define WM2200_IN_VU_MASK 0x0200 /* IN_VU */ 932*4882a593Smuzhiyun #define WM2200_IN_VU_SHIFT 9 /* IN_VU */ 933*4882a593Smuzhiyun #define WM2200_IN_VU_WIDTH 1 /* IN_VU */ 934*4882a593Smuzhiyun #define WM2200_IN2R_MUTE 0x0100 /* IN2R_MUTE */ 935*4882a593Smuzhiyun #define WM2200_IN2R_MUTE_MASK 0x0100 /* IN2R_MUTE */ 936*4882a593Smuzhiyun #define WM2200_IN2R_MUTE_SHIFT 8 /* IN2R_MUTE */ 937*4882a593Smuzhiyun #define WM2200_IN2R_MUTE_WIDTH 1 /* IN2R_MUTE */ 938*4882a593Smuzhiyun #define WM2200_IN2R_DIG_VOL_MASK 0x00FF /* IN2R_DIG_VOL - [7:0] */ 939*4882a593Smuzhiyun #define WM2200_IN2R_DIG_VOL_SHIFT 0 /* IN2R_DIG_VOL - [7:0] */ 940*4882a593Smuzhiyun #define WM2200_IN2R_DIG_VOL_WIDTH 8 /* IN2R_DIG_VOL - [7:0] */ 941*4882a593Smuzhiyun 942*4882a593Smuzhiyun /* 943*4882a593Smuzhiyun * R784 (0x310) - ADC Digital Volume 3L 944*4882a593Smuzhiyun */ 945*4882a593Smuzhiyun #define WM2200_IN_VU 0x0200 /* IN_VU */ 946*4882a593Smuzhiyun #define WM2200_IN_VU_MASK 0x0200 /* IN_VU */ 947*4882a593Smuzhiyun #define WM2200_IN_VU_SHIFT 9 /* IN_VU */ 948*4882a593Smuzhiyun #define WM2200_IN_VU_WIDTH 1 /* IN_VU */ 949*4882a593Smuzhiyun #define WM2200_IN3L_MUTE 0x0100 /* IN3L_MUTE */ 950*4882a593Smuzhiyun #define WM2200_IN3L_MUTE_MASK 0x0100 /* IN3L_MUTE */ 951*4882a593Smuzhiyun #define WM2200_IN3L_MUTE_SHIFT 8 /* IN3L_MUTE */ 952*4882a593Smuzhiyun #define WM2200_IN3L_MUTE_WIDTH 1 /* IN3L_MUTE */ 953*4882a593Smuzhiyun #define WM2200_IN3L_DIG_VOL_MASK 0x00FF /* IN3L_DIG_VOL - [7:0] */ 954*4882a593Smuzhiyun #define WM2200_IN3L_DIG_VOL_SHIFT 0 /* IN3L_DIG_VOL - [7:0] */ 955*4882a593Smuzhiyun #define WM2200_IN3L_DIG_VOL_WIDTH 8 /* IN3L_DIG_VOL - [7:0] */ 956*4882a593Smuzhiyun 957*4882a593Smuzhiyun /* 958*4882a593Smuzhiyun * R785 (0x311) - ADC Digital Volume 3R 959*4882a593Smuzhiyun */ 960*4882a593Smuzhiyun #define WM2200_IN_VU 0x0200 /* IN_VU */ 961*4882a593Smuzhiyun #define WM2200_IN_VU_MASK 0x0200 /* IN_VU */ 962*4882a593Smuzhiyun #define WM2200_IN_VU_SHIFT 9 /* IN_VU */ 963*4882a593Smuzhiyun #define WM2200_IN_VU_WIDTH 1 /* IN_VU */ 964*4882a593Smuzhiyun #define WM2200_IN3R_MUTE 0x0100 /* IN3R_MUTE */ 965*4882a593Smuzhiyun #define WM2200_IN3R_MUTE_MASK 0x0100 /* IN3R_MUTE */ 966*4882a593Smuzhiyun #define WM2200_IN3R_MUTE_SHIFT 8 /* IN3R_MUTE */ 967*4882a593Smuzhiyun #define WM2200_IN3R_MUTE_WIDTH 1 /* IN3R_MUTE */ 968*4882a593Smuzhiyun #define WM2200_IN3R_DIG_VOL_MASK 0x00FF /* IN3R_DIG_VOL - [7:0] */ 969*4882a593Smuzhiyun #define WM2200_IN3R_DIG_VOL_SHIFT 0 /* IN3R_DIG_VOL - [7:0] */ 970*4882a593Smuzhiyun #define WM2200_IN3R_DIG_VOL_WIDTH 8 /* IN3R_DIG_VOL - [7:0] */ 971*4882a593Smuzhiyun 972*4882a593Smuzhiyun /* 973*4882a593Smuzhiyun * R1024 (0x400) - Output Enables 974*4882a593Smuzhiyun */ 975*4882a593Smuzhiyun #define WM2200_OUT2L_ENA 0x0008 /* OUT2L_ENA */ 976*4882a593Smuzhiyun #define WM2200_OUT2L_ENA_MASK 0x0008 /* OUT2L_ENA */ 977*4882a593Smuzhiyun #define WM2200_OUT2L_ENA_SHIFT 3 /* OUT2L_ENA */ 978*4882a593Smuzhiyun #define WM2200_OUT2L_ENA_WIDTH 1 /* OUT2L_ENA */ 979*4882a593Smuzhiyun #define WM2200_OUT2R_ENA 0x0004 /* OUT2R_ENA */ 980*4882a593Smuzhiyun #define WM2200_OUT2R_ENA_MASK 0x0004 /* OUT2R_ENA */ 981*4882a593Smuzhiyun #define WM2200_OUT2R_ENA_SHIFT 2 /* OUT2R_ENA */ 982*4882a593Smuzhiyun #define WM2200_OUT2R_ENA_WIDTH 1 /* OUT2R_ENA */ 983*4882a593Smuzhiyun #define WM2200_OUT1L_ENA 0x0002 /* OUT1L_ENA */ 984*4882a593Smuzhiyun #define WM2200_OUT1L_ENA_MASK 0x0002 /* OUT1L_ENA */ 985*4882a593Smuzhiyun #define WM2200_OUT1L_ENA_SHIFT 1 /* OUT1L_ENA */ 986*4882a593Smuzhiyun #define WM2200_OUT1L_ENA_WIDTH 1 /* OUT1L_ENA */ 987*4882a593Smuzhiyun #define WM2200_OUT1R_ENA 0x0001 /* OUT1R_ENA */ 988*4882a593Smuzhiyun #define WM2200_OUT1R_ENA_MASK 0x0001 /* OUT1R_ENA */ 989*4882a593Smuzhiyun #define WM2200_OUT1R_ENA_SHIFT 0 /* OUT1R_ENA */ 990*4882a593Smuzhiyun #define WM2200_OUT1R_ENA_WIDTH 1 /* OUT1R_ENA */ 991*4882a593Smuzhiyun 992*4882a593Smuzhiyun /* 993*4882a593Smuzhiyun * R1025 (0x401) - DAC Volume Limit 1L 994*4882a593Smuzhiyun */ 995*4882a593Smuzhiyun #define WM2200_OUT1_OSR 0x2000 /* OUT1_OSR */ 996*4882a593Smuzhiyun #define WM2200_OUT1_OSR_MASK 0x2000 /* OUT1_OSR */ 997*4882a593Smuzhiyun #define WM2200_OUT1_OSR_SHIFT 13 /* OUT1_OSR */ 998*4882a593Smuzhiyun #define WM2200_OUT1_OSR_WIDTH 1 /* OUT1_OSR */ 999*4882a593Smuzhiyun #define WM2200_OUT1L_ANC_SRC 0x0800 /* OUT1L_ANC_SRC */ 1000*4882a593Smuzhiyun #define WM2200_OUT1L_ANC_SRC_MASK 0x0800 /* OUT1L_ANC_SRC */ 1001*4882a593Smuzhiyun #define WM2200_OUT1L_ANC_SRC_SHIFT 11 /* OUT1L_ANC_SRC */ 1002*4882a593Smuzhiyun #define WM2200_OUT1L_ANC_SRC_WIDTH 1 /* OUT1L_ANC_SRC */ 1003*4882a593Smuzhiyun #define WM2200_OUT1L_PGA_VOL_MASK 0x00FE /* OUT1L_PGA_VOL - [7:1] */ 1004*4882a593Smuzhiyun #define WM2200_OUT1L_PGA_VOL_SHIFT 1 /* OUT1L_PGA_VOL - [7:1] */ 1005*4882a593Smuzhiyun #define WM2200_OUT1L_PGA_VOL_WIDTH 7 /* OUT1L_PGA_VOL - [7:1] */ 1006*4882a593Smuzhiyun 1007*4882a593Smuzhiyun /* 1008*4882a593Smuzhiyun * R1026 (0x402) - DAC Volume Limit 1R 1009*4882a593Smuzhiyun */ 1010*4882a593Smuzhiyun #define WM2200_OUT1R_ANC_SRC 0x0800 /* OUT1R_ANC_SRC */ 1011*4882a593Smuzhiyun #define WM2200_OUT1R_ANC_SRC_MASK 0x0800 /* OUT1R_ANC_SRC */ 1012*4882a593Smuzhiyun #define WM2200_OUT1R_ANC_SRC_SHIFT 11 /* OUT1R_ANC_SRC */ 1013*4882a593Smuzhiyun #define WM2200_OUT1R_ANC_SRC_WIDTH 1 /* OUT1R_ANC_SRC */ 1014*4882a593Smuzhiyun #define WM2200_OUT1R_PGA_VOL_MASK 0x00FE /* OUT1R_PGA_VOL - [7:1] */ 1015*4882a593Smuzhiyun #define WM2200_OUT1R_PGA_VOL_SHIFT 1 /* OUT1R_PGA_VOL - [7:1] */ 1016*4882a593Smuzhiyun #define WM2200_OUT1R_PGA_VOL_WIDTH 7 /* OUT1R_PGA_VOL - [7:1] */ 1017*4882a593Smuzhiyun 1018*4882a593Smuzhiyun /* 1019*4882a593Smuzhiyun * R1027 (0x403) - DAC Volume Limit 2L 1020*4882a593Smuzhiyun */ 1021*4882a593Smuzhiyun #define WM2200_OUT2_OSR 0x2000 /* OUT2_OSR */ 1022*4882a593Smuzhiyun #define WM2200_OUT2_OSR_MASK 0x2000 /* OUT2_OSR */ 1023*4882a593Smuzhiyun #define WM2200_OUT2_OSR_SHIFT 13 /* OUT2_OSR */ 1024*4882a593Smuzhiyun #define WM2200_OUT2_OSR_WIDTH 1 /* OUT2_OSR */ 1025*4882a593Smuzhiyun #define WM2200_OUT2L_ANC_SRC 0x0800 /* OUT2L_ANC_SRC */ 1026*4882a593Smuzhiyun #define WM2200_OUT2L_ANC_SRC_MASK 0x0800 /* OUT2L_ANC_SRC */ 1027*4882a593Smuzhiyun #define WM2200_OUT2L_ANC_SRC_SHIFT 11 /* OUT2L_ANC_SRC */ 1028*4882a593Smuzhiyun #define WM2200_OUT2L_ANC_SRC_WIDTH 1 /* OUT2L_ANC_SRC */ 1029*4882a593Smuzhiyun 1030*4882a593Smuzhiyun /* 1031*4882a593Smuzhiyun * R1028 (0x404) - DAC Volume Limit 2R 1032*4882a593Smuzhiyun */ 1033*4882a593Smuzhiyun #define WM2200_OUT2R_ANC_SRC 0x0800 /* OUT2R_ANC_SRC */ 1034*4882a593Smuzhiyun #define WM2200_OUT2R_ANC_SRC_MASK 0x0800 /* OUT2R_ANC_SRC */ 1035*4882a593Smuzhiyun #define WM2200_OUT2R_ANC_SRC_SHIFT 11 /* OUT2R_ANC_SRC */ 1036*4882a593Smuzhiyun #define WM2200_OUT2R_ANC_SRC_WIDTH 1 /* OUT2R_ANC_SRC */ 1037*4882a593Smuzhiyun 1038*4882a593Smuzhiyun /* 1039*4882a593Smuzhiyun * R1033 (0x409) - DAC AEC Control 1 1040*4882a593Smuzhiyun */ 1041*4882a593Smuzhiyun #define WM2200_AEC_LOOPBACK_ENA 0x0004 /* AEC_LOOPBACK_ENA */ 1042*4882a593Smuzhiyun #define WM2200_AEC_LOOPBACK_ENA_MASK 0x0004 /* AEC_LOOPBACK_ENA */ 1043*4882a593Smuzhiyun #define WM2200_AEC_LOOPBACK_ENA_SHIFT 2 /* AEC_LOOPBACK_ENA */ 1044*4882a593Smuzhiyun #define WM2200_AEC_LOOPBACK_ENA_WIDTH 1 /* AEC_LOOPBACK_ENA */ 1045*4882a593Smuzhiyun #define WM2200_AEC_LOOPBACK_SRC_MASK 0x0003 /* AEC_LOOPBACK_SRC - [1:0] */ 1046*4882a593Smuzhiyun #define WM2200_AEC_LOOPBACK_SRC_SHIFT 0 /* AEC_LOOPBACK_SRC - [1:0] */ 1047*4882a593Smuzhiyun #define WM2200_AEC_LOOPBACK_SRC_WIDTH 2 /* AEC_LOOPBACK_SRC - [1:0] */ 1048*4882a593Smuzhiyun 1049*4882a593Smuzhiyun /* 1050*4882a593Smuzhiyun * R1034 (0x40A) - Output Volume Ramp 1051*4882a593Smuzhiyun */ 1052*4882a593Smuzhiyun #define WM2200_OUT_VD_RAMP_MASK 0x0070 /* OUT_VD_RAMP - [6:4] */ 1053*4882a593Smuzhiyun #define WM2200_OUT_VD_RAMP_SHIFT 4 /* OUT_VD_RAMP - [6:4] */ 1054*4882a593Smuzhiyun #define WM2200_OUT_VD_RAMP_WIDTH 3 /* OUT_VD_RAMP - [6:4] */ 1055*4882a593Smuzhiyun #define WM2200_OUT_VI_RAMP_MASK 0x0007 /* OUT_VI_RAMP - [2:0] */ 1056*4882a593Smuzhiyun #define WM2200_OUT_VI_RAMP_SHIFT 0 /* OUT_VI_RAMP - [2:0] */ 1057*4882a593Smuzhiyun #define WM2200_OUT_VI_RAMP_WIDTH 3 /* OUT_VI_RAMP - [2:0] */ 1058*4882a593Smuzhiyun 1059*4882a593Smuzhiyun /* 1060*4882a593Smuzhiyun * R1035 (0x40B) - DAC Digital Volume 1L 1061*4882a593Smuzhiyun */ 1062*4882a593Smuzhiyun #define WM2200_OUT_VU 0x0200 /* OUT_VU */ 1063*4882a593Smuzhiyun #define WM2200_OUT_VU_MASK 0x0200 /* OUT_VU */ 1064*4882a593Smuzhiyun #define WM2200_OUT_VU_SHIFT 9 /* OUT_VU */ 1065*4882a593Smuzhiyun #define WM2200_OUT_VU_WIDTH 1 /* OUT_VU */ 1066*4882a593Smuzhiyun #define WM2200_OUT1L_MUTE 0x0100 /* OUT1L_MUTE */ 1067*4882a593Smuzhiyun #define WM2200_OUT1L_MUTE_MASK 0x0100 /* OUT1L_MUTE */ 1068*4882a593Smuzhiyun #define WM2200_OUT1L_MUTE_SHIFT 8 /* OUT1L_MUTE */ 1069*4882a593Smuzhiyun #define WM2200_OUT1L_MUTE_WIDTH 1 /* OUT1L_MUTE */ 1070*4882a593Smuzhiyun #define WM2200_OUT1L_VOL_MASK 0x00FF /* OUT1L_VOL - [7:0] */ 1071*4882a593Smuzhiyun #define WM2200_OUT1L_VOL_SHIFT 0 /* OUT1L_VOL - [7:0] */ 1072*4882a593Smuzhiyun #define WM2200_OUT1L_VOL_WIDTH 8 /* OUT1L_VOL - [7:0] */ 1073*4882a593Smuzhiyun 1074*4882a593Smuzhiyun /* 1075*4882a593Smuzhiyun * R1036 (0x40C) - DAC Digital Volume 1R 1076*4882a593Smuzhiyun */ 1077*4882a593Smuzhiyun #define WM2200_OUT_VU 0x0200 /* OUT_VU */ 1078*4882a593Smuzhiyun #define WM2200_OUT_VU_MASK 0x0200 /* OUT_VU */ 1079*4882a593Smuzhiyun #define WM2200_OUT_VU_SHIFT 9 /* OUT_VU */ 1080*4882a593Smuzhiyun #define WM2200_OUT_VU_WIDTH 1 /* OUT_VU */ 1081*4882a593Smuzhiyun #define WM2200_OUT1R_MUTE 0x0100 /* OUT1R_MUTE */ 1082*4882a593Smuzhiyun #define WM2200_OUT1R_MUTE_MASK 0x0100 /* OUT1R_MUTE */ 1083*4882a593Smuzhiyun #define WM2200_OUT1R_MUTE_SHIFT 8 /* OUT1R_MUTE */ 1084*4882a593Smuzhiyun #define WM2200_OUT1R_MUTE_WIDTH 1 /* OUT1R_MUTE */ 1085*4882a593Smuzhiyun #define WM2200_OUT1R_VOL_MASK 0x00FF /* OUT1R_VOL - [7:0] */ 1086*4882a593Smuzhiyun #define WM2200_OUT1R_VOL_SHIFT 0 /* OUT1R_VOL - [7:0] */ 1087*4882a593Smuzhiyun #define WM2200_OUT1R_VOL_WIDTH 8 /* OUT1R_VOL - [7:0] */ 1088*4882a593Smuzhiyun 1089*4882a593Smuzhiyun /* 1090*4882a593Smuzhiyun * R1037 (0x40D) - DAC Digital Volume 2L 1091*4882a593Smuzhiyun */ 1092*4882a593Smuzhiyun #define WM2200_OUT_VU 0x0200 /* OUT_VU */ 1093*4882a593Smuzhiyun #define WM2200_OUT_VU_MASK 0x0200 /* OUT_VU */ 1094*4882a593Smuzhiyun #define WM2200_OUT_VU_SHIFT 9 /* OUT_VU */ 1095*4882a593Smuzhiyun #define WM2200_OUT_VU_WIDTH 1 /* OUT_VU */ 1096*4882a593Smuzhiyun #define WM2200_OUT2L_MUTE 0x0100 /* OUT2L_MUTE */ 1097*4882a593Smuzhiyun #define WM2200_OUT2L_MUTE_MASK 0x0100 /* OUT2L_MUTE */ 1098*4882a593Smuzhiyun #define WM2200_OUT2L_MUTE_SHIFT 8 /* OUT2L_MUTE */ 1099*4882a593Smuzhiyun #define WM2200_OUT2L_MUTE_WIDTH 1 /* OUT2L_MUTE */ 1100*4882a593Smuzhiyun #define WM2200_OUT2L_VOL_MASK 0x00FF /* OUT2L_VOL - [7:0] */ 1101*4882a593Smuzhiyun #define WM2200_OUT2L_VOL_SHIFT 0 /* OUT2L_VOL - [7:0] */ 1102*4882a593Smuzhiyun #define WM2200_OUT2L_VOL_WIDTH 8 /* OUT2L_VOL - [7:0] */ 1103*4882a593Smuzhiyun 1104*4882a593Smuzhiyun /* 1105*4882a593Smuzhiyun * R1038 (0x40E) - DAC Digital Volume 2R 1106*4882a593Smuzhiyun */ 1107*4882a593Smuzhiyun #define WM2200_OUT_VU 0x0200 /* OUT_VU */ 1108*4882a593Smuzhiyun #define WM2200_OUT_VU_MASK 0x0200 /* OUT_VU */ 1109*4882a593Smuzhiyun #define WM2200_OUT_VU_SHIFT 9 /* OUT_VU */ 1110*4882a593Smuzhiyun #define WM2200_OUT_VU_WIDTH 1 /* OUT_VU */ 1111*4882a593Smuzhiyun #define WM2200_OUT2R_MUTE 0x0100 /* OUT2R_MUTE */ 1112*4882a593Smuzhiyun #define WM2200_OUT2R_MUTE_MASK 0x0100 /* OUT2R_MUTE */ 1113*4882a593Smuzhiyun #define WM2200_OUT2R_MUTE_SHIFT 8 /* OUT2R_MUTE */ 1114*4882a593Smuzhiyun #define WM2200_OUT2R_MUTE_WIDTH 1 /* OUT2R_MUTE */ 1115*4882a593Smuzhiyun #define WM2200_OUT2R_VOL_MASK 0x00FF /* OUT2R_VOL - [7:0] */ 1116*4882a593Smuzhiyun #define WM2200_OUT2R_VOL_SHIFT 0 /* OUT2R_VOL - [7:0] */ 1117*4882a593Smuzhiyun #define WM2200_OUT2R_VOL_WIDTH 8 /* OUT2R_VOL - [7:0] */ 1118*4882a593Smuzhiyun 1119*4882a593Smuzhiyun /* 1120*4882a593Smuzhiyun * R1047 (0x417) - PDM 1 1121*4882a593Smuzhiyun */ 1122*4882a593Smuzhiyun #define WM2200_SPK1R_MUTE 0x2000 /* SPK1R_MUTE */ 1123*4882a593Smuzhiyun #define WM2200_SPK1R_MUTE_MASK 0x2000 /* SPK1R_MUTE */ 1124*4882a593Smuzhiyun #define WM2200_SPK1R_MUTE_SHIFT 13 /* SPK1R_MUTE */ 1125*4882a593Smuzhiyun #define WM2200_SPK1R_MUTE_WIDTH 1 /* SPK1R_MUTE */ 1126*4882a593Smuzhiyun #define WM2200_SPK1L_MUTE 0x1000 /* SPK1L_MUTE */ 1127*4882a593Smuzhiyun #define WM2200_SPK1L_MUTE_MASK 0x1000 /* SPK1L_MUTE */ 1128*4882a593Smuzhiyun #define WM2200_SPK1L_MUTE_SHIFT 12 /* SPK1L_MUTE */ 1129*4882a593Smuzhiyun #define WM2200_SPK1L_MUTE_WIDTH 1 /* SPK1L_MUTE */ 1130*4882a593Smuzhiyun #define WM2200_SPK1_MUTE_ENDIAN 0x0100 /* SPK1_MUTE_ENDIAN */ 1131*4882a593Smuzhiyun #define WM2200_SPK1_MUTE_ENDIAN_MASK 0x0100 /* SPK1_MUTE_ENDIAN */ 1132*4882a593Smuzhiyun #define WM2200_SPK1_MUTE_ENDIAN_SHIFT 8 /* SPK1_MUTE_ENDIAN */ 1133*4882a593Smuzhiyun #define WM2200_SPK1_MUTE_ENDIAN_WIDTH 1 /* SPK1_MUTE_ENDIAN */ 1134*4882a593Smuzhiyun #define WM2200_SPK1_MUTE_SEQL_MASK 0x00FF /* SPK1_MUTE_SEQL - [7:0] */ 1135*4882a593Smuzhiyun #define WM2200_SPK1_MUTE_SEQL_SHIFT 0 /* SPK1_MUTE_SEQL - [7:0] */ 1136*4882a593Smuzhiyun #define WM2200_SPK1_MUTE_SEQL_WIDTH 8 /* SPK1_MUTE_SEQL - [7:0] */ 1137*4882a593Smuzhiyun 1138*4882a593Smuzhiyun /* 1139*4882a593Smuzhiyun * R1048 (0x418) - PDM 2 1140*4882a593Smuzhiyun */ 1141*4882a593Smuzhiyun #define WM2200_SPK1_FMT 0x0001 /* SPK1_FMT */ 1142*4882a593Smuzhiyun #define WM2200_SPK1_FMT_MASK 0x0001 /* SPK1_FMT */ 1143*4882a593Smuzhiyun #define WM2200_SPK1_FMT_SHIFT 0 /* SPK1_FMT */ 1144*4882a593Smuzhiyun #define WM2200_SPK1_FMT_WIDTH 1 /* SPK1_FMT */ 1145*4882a593Smuzhiyun 1146*4882a593Smuzhiyun /* 1147*4882a593Smuzhiyun * R1280 (0x500) - Audio IF 1_1 1148*4882a593Smuzhiyun */ 1149*4882a593Smuzhiyun #define WM2200_AIF1_BCLK_INV 0x0040 /* AIF1_BCLK_INV */ 1150*4882a593Smuzhiyun #define WM2200_AIF1_BCLK_INV_MASK 0x0040 /* AIF1_BCLK_INV */ 1151*4882a593Smuzhiyun #define WM2200_AIF1_BCLK_INV_SHIFT 6 /* AIF1_BCLK_INV */ 1152*4882a593Smuzhiyun #define WM2200_AIF1_BCLK_INV_WIDTH 1 /* AIF1_BCLK_INV */ 1153*4882a593Smuzhiyun #define WM2200_AIF1_BCLK_FRC 0x0020 /* AIF1_BCLK_FRC */ 1154*4882a593Smuzhiyun #define WM2200_AIF1_BCLK_FRC_MASK 0x0020 /* AIF1_BCLK_FRC */ 1155*4882a593Smuzhiyun #define WM2200_AIF1_BCLK_FRC_SHIFT 5 /* AIF1_BCLK_FRC */ 1156*4882a593Smuzhiyun #define WM2200_AIF1_BCLK_FRC_WIDTH 1 /* AIF1_BCLK_FRC */ 1157*4882a593Smuzhiyun #define WM2200_AIF1_BCLK_MSTR 0x0010 /* AIF1_BCLK_MSTR */ 1158*4882a593Smuzhiyun #define WM2200_AIF1_BCLK_MSTR_MASK 0x0010 /* AIF1_BCLK_MSTR */ 1159*4882a593Smuzhiyun #define WM2200_AIF1_BCLK_MSTR_SHIFT 4 /* AIF1_BCLK_MSTR */ 1160*4882a593Smuzhiyun #define WM2200_AIF1_BCLK_MSTR_WIDTH 1 /* AIF1_BCLK_MSTR */ 1161*4882a593Smuzhiyun #define WM2200_AIF1_BCLK_DIV_MASK 0x000F /* AIF1_BCLK_DIV - [3:0] */ 1162*4882a593Smuzhiyun #define WM2200_AIF1_BCLK_DIV_SHIFT 0 /* AIF1_BCLK_DIV - [3:0] */ 1163*4882a593Smuzhiyun #define WM2200_AIF1_BCLK_DIV_WIDTH 4 /* AIF1_BCLK_DIV - [3:0] */ 1164*4882a593Smuzhiyun 1165*4882a593Smuzhiyun /* 1166*4882a593Smuzhiyun * R1281 (0x501) - Audio IF 1_2 1167*4882a593Smuzhiyun */ 1168*4882a593Smuzhiyun #define WM2200_AIF1TX_DAT_TRI 0x0020 /* AIF1TX_DAT_TRI */ 1169*4882a593Smuzhiyun #define WM2200_AIF1TX_DAT_TRI_MASK 0x0020 /* AIF1TX_DAT_TRI */ 1170*4882a593Smuzhiyun #define WM2200_AIF1TX_DAT_TRI_SHIFT 5 /* AIF1TX_DAT_TRI */ 1171*4882a593Smuzhiyun #define WM2200_AIF1TX_DAT_TRI_WIDTH 1 /* AIF1TX_DAT_TRI */ 1172*4882a593Smuzhiyun #define WM2200_AIF1TX_LRCLK_SRC 0x0008 /* AIF1TX_LRCLK_SRC */ 1173*4882a593Smuzhiyun #define WM2200_AIF1TX_LRCLK_SRC_MASK 0x0008 /* AIF1TX_LRCLK_SRC */ 1174*4882a593Smuzhiyun #define WM2200_AIF1TX_LRCLK_SRC_SHIFT 3 /* AIF1TX_LRCLK_SRC */ 1175*4882a593Smuzhiyun #define WM2200_AIF1TX_LRCLK_SRC_WIDTH 1 /* AIF1TX_LRCLK_SRC */ 1176*4882a593Smuzhiyun #define WM2200_AIF1TX_LRCLK_INV 0x0004 /* AIF1TX_LRCLK_INV */ 1177*4882a593Smuzhiyun #define WM2200_AIF1TX_LRCLK_INV_MASK 0x0004 /* AIF1TX_LRCLK_INV */ 1178*4882a593Smuzhiyun #define WM2200_AIF1TX_LRCLK_INV_SHIFT 2 /* AIF1TX_LRCLK_INV */ 1179*4882a593Smuzhiyun #define WM2200_AIF1TX_LRCLK_INV_WIDTH 1 /* AIF1TX_LRCLK_INV */ 1180*4882a593Smuzhiyun #define WM2200_AIF1TX_LRCLK_FRC 0x0002 /* AIF1TX_LRCLK_FRC */ 1181*4882a593Smuzhiyun #define WM2200_AIF1TX_LRCLK_FRC_MASK 0x0002 /* AIF1TX_LRCLK_FRC */ 1182*4882a593Smuzhiyun #define WM2200_AIF1TX_LRCLK_FRC_SHIFT 1 /* AIF1TX_LRCLK_FRC */ 1183*4882a593Smuzhiyun #define WM2200_AIF1TX_LRCLK_FRC_WIDTH 1 /* AIF1TX_LRCLK_FRC */ 1184*4882a593Smuzhiyun #define WM2200_AIF1TX_LRCLK_MSTR 0x0001 /* AIF1TX_LRCLK_MSTR */ 1185*4882a593Smuzhiyun #define WM2200_AIF1TX_LRCLK_MSTR_MASK 0x0001 /* AIF1TX_LRCLK_MSTR */ 1186*4882a593Smuzhiyun #define WM2200_AIF1TX_LRCLK_MSTR_SHIFT 0 /* AIF1TX_LRCLK_MSTR */ 1187*4882a593Smuzhiyun #define WM2200_AIF1TX_LRCLK_MSTR_WIDTH 1 /* AIF1TX_LRCLK_MSTR */ 1188*4882a593Smuzhiyun 1189*4882a593Smuzhiyun /* 1190*4882a593Smuzhiyun * R1282 (0x502) - Audio IF 1_3 1191*4882a593Smuzhiyun */ 1192*4882a593Smuzhiyun #define WM2200_AIF1RX_LRCLK_INV 0x0004 /* AIF1RX_LRCLK_INV */ 1193*4882a593Smuzhiyun #define WM2200_AIF1RX_LRCLK_INV_MASK 0x0004 /* AIF1RX_LRCLK_INV */ 1194*4882a593Smuzhiyun #define WM2200_AIF1RX_LRCLK_INV_SHIFT 2 /* AIF1RX_LRCLK_INV */ 1195*4882a593Smuzhiyun #define WM2200_AIF1RX_LRCLK_INV_WIDTH 1 /* AIF1RX_LRCLK_INV */ 1196*4882a593Smuzhiyun #define WM2200_AIF1RX_LRCLK_FRC 0x0002 /* AIF1RX_LRCLK_FRC */ 1197*4882a593Smuzhiyun #define WM2200_AIF1RX_LRCLK_FRC_MASK 0x0002 /* AIF1RX_LRCLK_FRC */ 1198*4882a593Smuzhiyun #define WM2200_AIF1RX_LRCLK_FRC_SHIFT 1 /* AIF1RX_LRCLK_FRC */ 1199*4882a593Smuzhiyun #define WM2200_AIF1RX_LRCLK_FRC_WIDTH 1 /* AIF1RX_LRCLK_FRC */ 1200*4882a593Smuzhiyun #define WM2200_AIF1RX_LRCLK_MSTR 0x0001 /* AIF1RX_LRCLK_MSTR */ 1201*4882a593Smuzhiyun #define WM2200_AIF1RX_LRCLK_MSTR_MASK 0x0001 /* AIF1RX_LRCLK_MSTR */ 1202*4882a593Smuzhiyun #define WM2200_AIF1RX_LRCLK_MSTR_SHIFT 0 /* AIF1RX_LRCLK_MSTR */ 1203*4882a593Smuzhiyun #define WM2200_AIF1RX_LRCLK_MSTR_WIDTH 1 /* AIF1RX_LRCLK_MSTR */ 1204*4882a593Smuzhiyun 1205*4882a593Smuzhiyun /* 1206*4882a593Smuzhiyun * R1283 (0x503) - Audio IF 1_4 1207*4882a593Smuzhiyun */ 1208*4882a593Smuzhiyun #define WM2200_AIF1_TRI 0x0040 /* AIF1_TRI */ 1209*4882a593Smuzhiyun #define WM2200_AIF1_TRI_MASK 0x0040 /* AIF1_TRI */ 1210*4882a593Smuzhiyun #define WM2200_AIF1_TRI_SHIFT 6 /* AIF1_TRI */ 1211*4882a593Smuzhiyun #define WM2200_AIF1_TRI_WIDTH 1 /* AIF1_TRI */ 1212*4882a593Smuzhiyun 1213*4882a593Smuzhiyun /* 1214*4882a593Smuzhiyun * R1284 (0x504) - Audio IF 1_5 1215*4882a593Smuzhiyun */ 1216*4882a593Smuzhiyun #define WM2200_AIF1_FMT_MASK 0x0007 /* AIF1_FMT - [2:0] */ 1217*4882a593Smuzhiyun #define WM2200_AIF1_FMT_SHIFT 0 /* AIF1_FMT - [2:0] */ 1218*4882a593Smuzhiyun #define WM2200_AIF1_FMT_WIDTH 3 /* AIF1_FMT - [2:0] */ 1219*4882a593Smuzhiyun 1220*4882a593Smuzhiyun /* 1221*4882a593Smuzhiyun * R1285 (0x505) - Audio IF 1_6 1222*4882a593Smuzhiyun */ 1223*4882a593Smuzhiyun #define WM2200_AIF1TX_BCPF_MASK 0x07FF /* AIF1TX_BCPF - [10:0] */ 1224*4882a593Smuzhiyun #define WM2200_AIF1TX_BCPF_SHIFT 0 /* AIF1TX_BCPF - [10:0] */ 1225*4882a593Smuzhiyun #define WM2200_AIF1TX_BCPF_WIDTH 11 /* AIF1TX_BCPF - [10:0] */ 1226*4882a593Smuzhiyun 1227*4882a593Smuzhiyun /* 1228*4882a593Smuzhiyun * R1286 (0x506) - Audio IF 1_7 1229*4882a593Smuzhiyun */ 1230*4882a593Smuzhiyun #define WM2200_AIF1RX_BCPF_MASK 0x07FF /* AIF1RX_BCPF - [10:0] */ 1231*4882a593Smuzhiyun #define WM2200_AIF1RX_BCPF_SHIFT 0 /* AIF1RX_BCPF - [10:0] */ 1232*4882a593Smuzhiyun #define WM2200_AIF1RX_BCPF_WIDTH 11 /* AIF1RX_BCPF - [10:0] */ 1233*4882a593Smuzhiyun 1234*4882a593Smuzhiyun /* 1235*4882a593Smuzhiyun * R1287 (0x507) - Audio IF 1_8 1236*4882a593Smuzhiyun */ 1237*4882a593Smuzhiyun #define WM2200_AIF1TX_WL_MASK 0x3F00 /* AIF1TX_WL - [13:8] */ 1238*4882a593Smuzhiyun #define WM2200_AIF1TX_WL_SHIFT 8 /* AIF1TX_WL - [13:8] */ 1239*4882a593Smuzhiyun #define WM2200_AIF1TX_WL_WIDTH 6 /* AIF1TX_WL - [13:8] */ 1240*4882a593Smuzhiyun #define WM2200_AIF1TX_SLOT_LEN_MASK 0x00FF /* AIF1TX_SLOT_LEN - [7:0] */ 1241*4882a593Smuzhiyun #define WM2200_AIF1TX_SLOT_LEN_SHIFT 0 /* AIF1TX_SLOT_LEN - [7:0] */ 1242*4882a593Smuzhiyun #define WM2200_AIF1TX_SLOT_LEN_WIDTH 8 /* AIF1TX_SLOT_LEN - [7:0] */ 1243*4882a593Smuzhiyun 1244*4882a593Smuzhiyun /* 1245*4882a593Smuzhiyun * R1288 (0x508) - Audio IF 1_9 1246*4882a593Smuzhiyun */ 1247*4882a593Smuzhiyun #define WM2200_AIF1RX_WL_MASK 0x3F00 /* AIF1RX_WL - [13:8] */ 1248*4882a593Smuzhiyun #define WM2200_AIF1RX_WL_SHIFT 8 /* AIF1RX_WL - [13:8] */ 1249*4882a593Smuzhiyun #define WM2200_AIF1RX_WL_WIDTH 6 /* AIF1RX_WL - [13:8] */ 1250*4882a593Smuzhiyun #define WM2200_AIF1RX_SLOT_LEN_MASK 0x00FF /* AIF1RX_SLOT_LEN - [7:0] */ 1251*4882a593Smuzhiyun #define WM2200_AIF1RX_SLOT_LEN_SHIFT 0 /* AIF1RX_SLOT_LEN - [7:0] */ 1252*4882a593Smuzhiyun #define WM2200_AIF1RX_SLOT_LEN_WIDTH 8 /* AIF1RX_SLOT_LEN - [7:0] */ 1253*4882a593Smuzhiyun 1254*4882a593Smuzhiyun /* 1255*4882a593Smuzhiyun * R1289 (0x509) - Audio IF 1_10 1256*4882a593Smuzhiyun */ 1257*4882a593Smuzhiyun #define WM2200_AIF1TX1_SLOT_MASK 0x003F /* AIF1TX1_SLOT - [5:0] */ 1258*4882a593Smuzhiyun #define WM2200_AIF1TX1_SLOT_SHIFT 0 /* AIF1TX1_SLOT - [5:0] */ 1259*4882a593Smuzhiyun #define WM2200_AIF1TX1_SLOT_WIDTH 6 /* AIF1TX1_SLOT - [5:0] */ 1260*4882a593Smuzhiyun 1261*4882a593Smuzhiyun /* 1262*4882a593Smuzhiyun * R1290 (0x50A) - Audio IF 1_11 1263*4882a593Smuzhiyun */ 1264*4882a593Smuzhiyun #define WM2200_AIF1TX2_SLOT_MASK 0x003F /* AIF1TX2_SLOT - [5:0] */ 1265*4882a593Smuzhiyun #define WM2200_AIF1TX2_SLOT_SHIFT 0 /* AIF1TX2_SLOT - [5:0] */ 1266*4882a593Smuzhiyun #define WM2200_AIF1TX2_SLOT_WIDTH 6 /* AIF1TX2_SLOT - [5:0] */ 1267*4882a593Smuzhiyun 1268*4882a593Smuzhiyun /* 1269*4882a593Smuzhiyun * R1291 (0x50B) - Audio IF 1_12 1270*4882a593Smuzhiyun */ 1271*4882a593Smuzhiyun #define WM2200_AIF1TX3_SLOT_MASK 0x003F /* AIF1TX3_SLOT - [5:0] */ 1272*4882a593Smuzhiyun #define WM2200_AIF1TX3_SLOT_SHIFT 0 /* AIF1TX3_SLOT - [5:0] */ 1273*4882a593Smuzhiyun #define WM2200_AIF1TX3_SLOT_WIDTH 6 /* AIF1TX3_SLOT - [5:0] */ 1274*4882a593Smuzhiyun 1275*4882a593Smuzhiyun /* 1276*4882a593Smuzhiyun * R1292 (0x50C) - Audio IF 1_13 1277*4882a593Smuzhiyun */ 1278*4882a593Smuzhiyun #define WM2200_AIF1TX4_SLOT_MASK 0x003F /* AIF1TX4_SLOT - [5:0] */ 1279*4882a593Smuzhiyun #define WM2200_AIF1TX4_SLOT_SHIFT 0 /* AIF1TX4_SLOT - [5:0] */ 1280*4882a593Smuzhiyun #define WM2200_AIF1TX4_SLOT_WIDTH 6 /* AIF1TX4_SLOT - [5:0] */ 1281*4882a593Smuzhiyun 1282*4882a593Smuzhiyun /* 1283*4882a593Smuzhiyun * R1293 (0x50D) - Audio IF 1_14 1284*4882a593Smuzhiyun */ 1285*4882a593Smuzhiyun #define WM2200_AIF1TX5_SLOT_MASK 0x003F /* AIF1TX5_SLOT - [5:0] */ 1286*4882a593Smuzhiyun #define WM2200_AIF1TX5_SLOT_SHIFT 0 /* AIF1TX5_SLOT - [5:0] */ 1287*4882a593Smuzhiyun #define WM2200_AIF1TX5_SLOT_WIDTH 6 /* AIF1TX5_SLOT - [5:0] */ 1288*4882a593Smuzhiyun 1289*4882a593Smuzhiyun /* 1290*4882a593Smuzhiyun * R1294 (0x50E) - Audio IF 1_15 1291*4882a593Smuzhiyun */ 1292*4882a593Smuzhiyun #define WM2200_AIF1TX6_SLOT_MASK 0x003F /* AIF1TX6_SLOT - [5:0] */ 1293*4882a593Smuzhiyun #define WM2200_AIF1TX6_SLOT_SHIFT 0 /* AIF1TX6_SLOT - [5:0] */ 1294*4882a593Smuzhiyun #define WM2200_AIF1TX6_SLOT_WIDTH 6 /* AIF1TX6_SLOT - [5:0] */ 1295*4882a593Smuzhiyun 1296*4882a593Smuzhiyun /* 1297*4882a593Smuzhiyun * R1295 (0x50F) - Audio IF 1_16 1298*4882a593Smuzhiyun */ 1299*4882a593Smuzhiyun #define WM2200_AIF1RX1_SLOT_MASK 0x003F /* AIF1RX1_SLOT - [5:0] */ 1300*4882a593Smuzhiyun #define WM2200_AIF1RX1_SLOT_SHIFT 0 /* AIF1RX1_SLOT - [5:0] */ 1301*4882a593Smuzhiyun #define WM2200_AIF1RX1_SLOT_WIDTH 6 /* AIF1RX1_SLOT - [5:0] */ 1302*4882a593Smuzhiyun 1303*4882a593Smuzhiyun /* 1304*4882a593Smuzhiyun * R1296 (0x510) - Audio IF 1_17 1305*4882a593Smuzhiyun */ 1306*4882a593Smuzhiyun #define WM2200_AIF1RX2_SLOT_MASK 0x003F /* AIF1RX2_SLOT - [5:0] */ 1307*4882a593Smuzhiyun #define WM2200_AIF1RX2_SLOT_SHIFT 0 /* AIF1RX2_SLOT - [5:0] */ 1308*4882a593Smuzhiyun #define WM2200_AIF1RX2_SLOT_WIDTH 6 /* AIF1RX2_SLOT - [5:0] */ 1309*4882a593Smuzhiyun 1310*4882a593Smuzhiyun /* 1311*4882a593Smuzhiyun * R1297 (0x511) - Audio IF 1_18 1312*4882a593Smuzhiyun */ 1313*4882a593Smuzhiyun #define WM2200_AIF1RX3_SLOT_MASK 0x003F /* AIF1RX3_SLOT - [5:0] */ 1314*4882a593Smuzhiyun #define WM2200_AIF1RX3_SLOT_SHIFT 0 /* AIF1RX3_SLOT - [5:0] */ 1315*4882a593Smuzhiyun #define WM2200_AIF1RX3_SLOT_WIDTH 6 /* AIF1RX3_SLOT - [5:0] */ 1316*4882a593Smuzhiyun 1317*4882a593Smuzhiyun /* 1318*4882a593Smuzhiyun * R1298 (0x512) - Audio IF 1_19 1319*4882a593Smuzhiyun */ 1320*4882a593Smuzhiyun #define WM2200_AIF1RX4_SLOT_MASK 0x003F /* AIF1RX4_SLOT - [5:0] */ 1321*4882a593Smuzhiyun #define WM2200_AIF1RX4_SLOT_SHIFT 0 /* AIF1RX4_SLOT - [5:0] */ 1322*4882a593Smuzhiyun #define WM2200_AIF1RX4_SLOT_WIDTH 6 /* AIF1RX4_SLOT - [5:0] */ 1323*4882a593Smuzhiyun 1324*4882a593Smuzhiyun /* 1325*4882a593Smuzhiyun * R1299 (0x513) - Audio IF 1_20 1326*4882a593Smuzhiyun */ 1327*4882a593Smuzhiyun #define WM2200_AIF1RX5_SLOT_MASK 0x003F /* AIF1RX5_SLOT - [5:0] */ 1328*4882a593Smuzhiyun #define WM2200_AIF1RX5_SLOT_SHIFT 0 /* AIF1RX5_SLOT - [5:0] */ 1329*4882a593Smuzhiyun #define WM2200_AIF1RX5_SLOT_WIDTH 6 /* AIF1RX5_SLOT - [5:0] */ 1330*4882a593Smuzhiyun 1331*4882a593Smuzhiyun /* 1332*4882a593Smuzhiyun * R1300 (0x514) - Audio IF 1_21 1333*4882a593Smuzhiyun */ 1334*4882a593Smuzhiyun #define WM2200_AIF1RX6_SLOT_MASK 0x003F /* AIF1RX6_SLOT - [5:0] */ 1335*4882a593Smuzhiyun #define WM2200_AIF1RX6_SLOT_SHIFT 0 /* AIF1RX6_SLOT - [5:0] */ 1336*4882a593Smuzhiyun #define WM2200_AIF1RX6_SLOT_WIDTH 6 /* AIF1RX6_SLOT - [5:0] */ 1337*4882a593Smuzhiyun 1338*4882a593Smuzhiyun /* 1339*4882a593Smuzhiyun * R1301 (0x515) - Audio IF 1_22 1340*4882a593Smuzhiyun */ 1341*4882a593Smuzhiyun #define WM2200_AIF1RX6_ENA 0x0800 /* AIF1RX6_ENA */ 1342*4882a593Smuzhiyun #define WM2200_AIF1RX6_ENA_MASK 0x0800 /* AIF1RX6_ENA */ 1343*4882a593Smuzhiyun #define WM2200_AIF1RX6_ENA_SHIFT 11 /* AIF1RX6_ENA */ 1344*4882a593Smuzhiyun #define WM2200_AIF1RX6_ENA_WIDTH 1 /* AIF1RX6_ENA */ 1345*4882a593Smuzhiyun #define WM2200_AIF1RX5_ENA 0x0400 /* AIF1RX5_ENA */ 1346*4882a593Smuzhiyun #define WM2200_AIF1RX5_ENA_MASK 0x0400 /* AIF1RX5_ENA */ 1347*4882a593Smuzhiyun #define WM2200_AIF1RX5_ENA_SHIFT 10 /* AIF1RX5_ENA */ 1348*4882a593Smuzhiyun #define WM2200_AIF1RX5_ENA_WIDTH 1 /* AIF1RX5_ENA */ 1349*4882a593Smuzhiyun #define WM2200_AIF1RX4_ENA 0x0200 /* AIF1RX4_ENA */ 1350*4882a593Smuzhiyun #define WM2200_AIF1RX4_ENA_MASK 0x0200 /* AIF1RX4_ENA */ 1351*4882a593Smuzhiyun #define WM2200_AIF1RX4_ENA_SHIFT 9 /* AIF1RX4_ENA */ 1352*4882a593Smuzhiyun #define WM2200_AIF1RX4_ENA_WIDTH 1 /* AIF1RX4_ENA */ 1353*4882a593Smuzhiyun #define WM2200_AIF1RX3_ENA 0x0100 /* AIF1RX3_ENA */ 1354*4882a593Smuzhiyun #define WM2200_AIF1RX3_ENA_MASK 0x0100 /* AIF1RX3_ENA */ 1355*4882a593Smuzhiyun #define WM2200_AIF1RX3_ENA_SHIFT 8 /* AIF1RX3_ENA */ 1356*4882a593Smuzhiyun #define WM2200_AIF1RX3_ENA_WIDTH 1 /* AIF1RX3_ENA */ 1357*4882a593Smuzhiyun #define WM2200_AIF1RX2_ENA 0x0080 /* AIF1RX2_ENA */ 1358*4882a593Smuzhiyun #define WM2200_AIF1RX2_ENA_MASK 0x0080 /* AIF1RX2_ENA */ 1359*4882a593Smuzhiyun #define WM2200_AIF1RX2_ENA_SHIFT 7 /* AIF1RX2_ENA */ 1360*4882a593Smuzhiyun #define WM2200_AIF1RX2_ENA_WIDTH 1 /* AIF1RX2_ENA */ 1361*4882a593Smuzhiyun #define WM2200_AIF1RX1_ENA 0x0040 /* AIF1RX1_ENA */ 1362*4882a593Smuzhiyun #define WM2200_AIF1RX1_ENA_MASK 0x0040 /* AIF1RX1_ENA */ 1363*4882a593Smuzhiyun #define WM2200_AIF1RX1_ENA_SHIFT 6 /* AIF1RX1_ENA */ 1364*4882a593Smuzhiyun #define WM2200_AIF1RX1_ENA_WIDTH 1 /* AIF1RX1_ENA */ 1365*4882a593Smuzhiyun #define WM2200_AIF1TX6_ENA 0x0020 /* AIF1TX6_ENA */ 1366*4882a593Smuzhiyun #define WM2200_AIF1TX6_ENA_MASK 0x0020 /* AIF1TX6_ENA */ 1367*4882a593Smuzhiyun #define WM2200_AIF1TX6_ENA_SHIFT 5 /* AIF1TX6_ENA */ 1368*4882a593Smuzhiyun #define WM2200_AIF1TX6_ENA_WIDTH 1 /* AIF1TX6_ENA */ 1369*4882a593Smuzhiyun #define WM2200_AIF1TX5_ENA 0x0010 /* AIF1TX5_ENA */ 1370*4882a593Smuzhiyun #define WM2200_AIF1TX5_ENA_MASK 0x0010 /* AIF1TX5_ENA */ 1371*4882a593Smuzhiyun #define WM2200_AIF1TX5_ENA_SHIFT 4 /* AIF1TX5_ENA */ 1372*4882a593Smuzhiyun #define WM2200_AIF1TX5_ENA_WIDTH 1 /* AIF1TX5_ENA */ 1373*4882a593Smuzhiyun #define WM2200_AIF1TX4_ENA 0x0008 /* AIF1TX4_ENA */ 1374*4882a593Smuzhiyun #define WM2200_AIF1TX4_ENA_MASK 0x0008 /* AIF1TX4_ENA */ 1375*4882a593Smuzhiyun #define WM2200_AIF1TX4_ENA_SHIFT 3 /* AIF1TX4_ENA */ 1376*4882a593Smuzhiyun #define WM2200_AIF1TX4_ENA_WIDTH 1 /* AIF1TX4_ENA */ 1377*4882a593Smuzhiyun #define WM2200_AIF1TX3_ENA 0x0004 /* AIF1TX3_ENA */ 1378*4882a593Smuzhiyun #define WM2200_AIF1TX3_ENA_MASK 0x0004 /* AIF1TX3_ENA */ 1379*4882a593Smuzhiyun #define WM2200_AIF1TX3_ENA_SHIFT 2 /* AIF1TX3_ENA */ 1380*4882a593Smuzhiyun #define WM2200_AIF1TX3_ENA_WIDTH 1 /* AIF1TX3_ENA */ 1381*4882a593Smuzhiyun #define WM2200_AIF1TX2_ENA 0x0002 /* AIF1TX2_ENA */ 1382*4882a593Smuzhiyun #define WM2200_AIF1TX2_ENA_MASK 0x0002 /* AIF1TX2_ENA */ 1383*4882a593Smuzhiyun #define WM2200_AIF1TX2_ENA_SHIFT 1 /* AIF1TX2_ENA */ 1384*4882a593Smuzhiyun #define WM2200_AIF1TX2_ENA_WIDTH 1 /* AIF1TX2_ENA */ 1385*4882a593Smuzhiyun #define WM2200_AIF1TX1_ENA 0x0001 /* AIF1TX1_ENA */ 1386*4882a593Smuzhiyun #define WM2200_AIF1TX1_ENA_MASK 0x0001 /* AIF1TX1_ENA */ 1387*4882a593Smuzhiyun #define WM2200_AIF1TX1_ENA_SHIFT 0 /* AIF1TX1_ENA */ 1388*4882a593Smuzhiyun #define WM2200_AIF1TX1_ENA_WIDTH 1 /* AIF1TX1_ENA */ 1389*4882a593Smuzhiyun 1390*4882a593Smuzhiyun /* 1391*4882a593Smuzhiyun * R1536 (0x600) - OUT1LMIX Input 1 Source 1392*4882a593Smuzhiyun */ 1393*4882a593Smuzhiyun #define WM2200_OUT1LMIX_SRC1_MASK 0x007F /* OUT1LMIX_SRC1 - [6:0] */ 1394*4882a593Smuzhiyun #define WM2200_OUT1LMIX_SRC1_SHIFT 0 /* OUT1LMIX_SRC1 - [6:0] */ 1395*4882a593Smuzhiyun #define WM2200_OUT1LMIX_SRC1_WIDTH 7 /* OUT1LMIX_SRC1 - [6:0] */ 1396*4882a593Smuzhiyun 1397*4882a593Smuzhiyun /* 1398*4882a593Smuzhiyun * R1537 (0x601) - OUT1LMIX Input 1 Volume 1399*4882a593Smuzhiyun */ 1400*4882a593Smuzhiyun #define WM2200_OUT1LMIX_VOL1_MASK 0x00FE /* OUT1LMIX_VOL1 - [7:1] */ 1401*4882a593Smuzhiyun #define WM2200_OUT1LMIX_VOL1_SHIFT 1 /* OUT1LMIX_VOL1 - [7:1] */ 1402*4882a593Smuzhiyun #define WM2200_OUT1LMIX_VOL1_WIDTH 7 /* OUT1LMIX_VOL1 - [7:1] */ 1403*4882a593Smuzhiyun 1404*4882a593Smuzhiyun /* 1405*4882a593Smuzhiyun * R1538 (0x602) - OUT1LMIX Input 2 Source 1406*4882a593Smuzhiyun */ 1407*4882a593Smuzhiyun #define WM2200_OUT1LMIX_SRC2_MASK 0x007F /* OUT1LMIX_SRC2 - [6:0] */ 1408*4882a593Smuzhiyun #define WM2200_OUT1LMIX_SRC2_SHIFT 0 /* OUT1LMIX_SRC2 - [6:0] */ 1409*4882a593Smuzhiyun #define WM2200_OUT1LMIX_SRC2_WIDTH 7 /* OUT1LMIX_SRC2 - [6:0] */ 1410*4882a593Smuzhiyun 1411*4882a593Smuzhiyun /* 1412*4882a593Smuzhiyun * R1539 (0x603) - OUT1LMIX Input 2 Volume 1413*4882a593Smuzhiyun */ 1414*4882a593Smuzhiyun #define WM2200_OUT1LMIX_VOL2_MASK 0x00FE /* OUT1LMIX_VOL2 - [7:1] */ 1415*4882a593Smuzhiyun #define WM2200_OUT1LMIX_VOL2_SHIFT 1 /* OUT1LMIX_VOL2 - [7:1] */ 1416*4882a593Smuzhiyun #define WM2200_OUT1LMIX_VOL2_WIDTH 7 /* OUT1LMIX_VOL2 - [7:1] */ 1417*4882a593Smuzhiyun 1418*4882a593Smuzhiyun /* 1419*4882a593Smuzhiyun * R1540 (0x604) - OUT1LMIX Input 3 Source 1420*4882a593Smuzhiyun */ 1421*4882a593Smuzhiyun #define WM2200_OUT1LMIX_SRC3_MASK 0x007F /* OUT1LMIX_SRC3 - [6:0] */ 1422*4882a593Smuzhiyun #define WM2200_OUT1LMIX_SRC3_SHIFT 0 /* OUT1LMIX_SRC3 - [6:0] */ 1423*4882a593Smuzhiyun #define WM2200_OUT1LMIX_SRC3_WIDTH 7 /* OUT1LMIX_SRC3 - [6:0] */ 1424*4882a593Smuzhiyun 1425*4882a593Smuzhiyun /* 1426*4882a593Smuzhiyun * R1541 (0x605) - OUT1LMIX Input 3 Volume 1427*4882a593Smuzhiyun */ 1428*4882a593Smuzhiyun #define WM2200_OUT1LMIX_VOL3_MASK 0x00FE /* OUT1LMIX_VOL3 - [7:1] */ 1429*4882a593Smuzhiyun #define WM2200_OUT1LMIX_VOL3_SHIFT 1 /* OUT1LMIX_VOL3 - [7:1] */ 1430*4882a593Smuzhiyun #define WM2200_OUT1LMIX_VOL3_WIDTH 7 /* OUT1LMIX_VOL3 - [7:1] */ 1431*4882a593Smuzhiyun 1432*4882a593Smuzhiyun /* 1433*4882a593Smuzhiyun * R1542 (0x606) - OUT1LMIX Input 4 Source 1434*4882a593Smuzhiyun */ 1435*4882a593Smuzhiyun #define WM2200_OUT1LMIX_SRC4_MASK 0x007F /* OUT1LMIX_SRC4 - [6:0] */ 1436*4882a593Smuzhiyun #define WM2200_OUT1LMIX_SRC4_SHIFT 0 /* OUT1LMIX_SRC4 - [6:0] */ 1437*4882a593Smuzhiyun #define WM2200_OUT1LMIX_SRC4_WIDTH 7 /* OUT1LMIX_SRC4 - [6:0] */ 1438*4882a593Smuzhiyun 1439*4882a593Smuzhiyun /* 1440*4882a593Smuzhiyun * R1543 (0x607) - OUT1LMIX Input 4 Volume 1441*4882a593Smuzhiyun */ 1442*4882a593Smuzhiyun #define WM2200_OUT1LMIX_VOL4_MASK 0x00FE /* OUT1LMIX_VOL4 - [7:1] */ 1443*4882a593Smuzhiyun #define WM2200_OUT1LMIX_VOL4_SHIFT 1 /* OUT1LMIX_VOL4 - [7:1] */ 1444*4882a593Smuzhiyun #define WM2200_OUT1LMIX_VOL4_WIDTH 7 /* OUT1LMIX_VOL4 - [7:1] */ 1445*4882a593Smuzhiyun 1446*4882a593Smuzhiyun /* 1447*4882a593Smuzhiyun * R1544 (0x608) - OUT1RMIX Input 1 Source 1448*4882a593Smuzhiyun */ 1449*4882a593Smuzhiyun #define WM2200_OUT1RMIX_SRC1_MASK 0x007F /* OUT1RMIX_SRC1 - [6:0] */ 1450*4882a593Smuzhiyun #define WM2200_OUT1RMIX_SRC1_SHIFT 0 /* OUT1RMIX_SRC1 - [6:0] */ 1451*4882a593Smuzhiyun #define WM2200_OUT1RMIX_SRC1_WIDTH 7 /* OUT1RMIX_SRC1 - [6:0] */ 1452*4882a593Smuzhiyun 1453*4882a593Smuzhiyun /* 1454*4882a593Smuzhiyun * R1545 (0x609) - OUT1RMIX Input 1 Volume 1455*4882a593Smuzhiyun */ 1456*4882a593Smuzhiyun #define WM2200_OUT1RMIX_VOL1_MASK 0x00FE /* OUT1RMIX_VOL1 - [7:1] */ 1457*4882a593Smuzhiyun #define WM2200_OUT1RMIX_VOL1_SHIFT 1 /* OUT1RMIX_VOL1 - [7:1] */ 1458*4882a593Smuzhiyun #define WM2200_OUT1RMIX_VOL1_WIDTH 7 /* OUT1RMIX_VOL1 - [7:1] */ 1459*4882a593Smuzhiyun 1460*4882a593Smuzhiyun /* 1461*4882a593Smuzhiyun * R1546 (0x60A) - OUT1RMIX Input 2 Source 1462*4882a593Smuzhiyun */ 1463*4882a593Smuzhiyun #define WM2200_OUT1RMIX_SRC2_MASK 0x007F /* OUT1RMIX_SRC2 - [6:0] */ 1464*4882a593Smuzhiyun #define WM2200_OUT1RMIX_SRC2_SHIFT 0 /* OUT1RMIX_SRC2 - [6:0] */ 1465*4882a593Smuzhiyun #define WM2200_OUT1RMIX_SRC2_WIDTH 7 /* OUT1RMIX_SRC2 - [6:0] */ 1466*4882a593Smuzhiyun 1467*4882a593Smuzhiyun /* 1468*4882a593Smuzhiyun * R1547 (0x60B) - OUT1RMIX Input 2 Volume 1469*4882a593Smuzhiyun */ 1470*4882a593Smuzhiyun #define WM2200_OUT1RMIX_VOL2_MASK 0x00FE /* OUT1RMIX_VOL2 - [7:1] */ 1471*4882a593Smuzhiyun #define WM2200_OUT1RMIX_VOL2_SHIFT 1 /* OUT1RMIX_VOL2 - [7:1] */ 1472*4882a593Smuzhiyun #define WM2200_OUT1RMIX_VOL2_WIDTH 7 /* OUT1RMIX_VOL2 - [7:1] */ 1473*4882a593Smuzhiyun 1474*4882a593Smuzhiyun /* 1475*4882a593Smuzhiyun * R1548 (0x60C) - OUT1RMIX Input 3 Source 1476*4882a593Smuzhiyun */ 1477*4882a593Smuzhiyun #define WM2200_OUT1RMIX_SRC3_MASK 0x007F /* OUT1RMIX_SRC3 - [6:0] */ 1478*4882a593Smuzhiyun #define WM2200_OUT1RMIX_SRC3_SHIFT 0 /* OUT1RMIX_SRC3 - [6:0] */ 1479*4882a593Smuzhiyun #define WM2200_OUT1RMIX_SRC3_WIDTH 7 /* OUT1RMIX_SRC3 - [6:0] */ 1480*4882a593Smuzhiyun 1481*4882a593Smuzhiyun /* 1482*4882a593Smuzhiyun * R1549 (0x60D) - OUT1RMIX Input 3 Volume 1483*4882a593Smuzhiyun */ 1484*4882a593Smuzhiyun #define WM2200_OUT1RMIX_VOL3_MASK 0x00FE /* OUT1RMIX_VOL3 - [7:1] */ 1485*4882a593Smuzhiyun #define WM2200_OUT1RMIX_VOL3_SHIFT 1 /* OUT1RMIX_VOL3 - [7:1] */ 1486*4882a593Smuzhiyun #define WM2200_OUT1RMIX_VOL3_WIDTH 7 /* OUT1RMIX_VOL3 - [7:1] */ 1487*4882a593Smuzhiyun 1488*4882a593Smuzhiyun /* 1489*4882a593Smuzhiyun * R1550 (0x60E) - OUT1RMIX Input 4 Source 1490*4882a593Smuzhiyun */ 1491*4882a593Smuzhiyun #define WM2200_OUT1RMIX_SRC4_MASK 0x007F /* OUT1RMIX_SRC4 - [6:0] */ 1492*4882a593Smuzhiyun #define WM2200_OUT1RMIX_SRC4_SHIFT 0 /* OUT1RMIX_SRC4 - [6:0] */ 1493*4882a593Smuzhiyun #define WM2200_OUT1RMIX_SRC4_WIDTH 7 /* OUT1RMIX_SRC4 - [6:0] */ 1494*4882a593Smuzhiyun 1495*4882a593Smuzhiyun /* 1496*4882a593Smuzhiyun * R1551 (0x60F) - OUT1RMIX Input 4 Volume 1497*4882a593Smuzhiyun */ 1498*4882a593Smuzhiyun #define WM2200_OUT1RMIX_VOL4_MASK 0x00FE /* OUT1RMIX_VOL4 - [7:1] */ 1499*4882a593Smuzhiyun #define WM2200_OUT1RMIX_VOL4_SHIFT 1 /* OUT1RMIX_VOL4 - [7:1] */ 1500*4882a593Smuzhiyun #define WM2200_OUT1RMIX_VOL4_WIDTH 7 /* OUT1RMIX_VOL4 - [7:1] */ 1501*4882a593Smuzhiyun 1502*4882a593Smuzhiyun /* 1503*4882a593Smuzhiyun * R1552 (0x610) - OUT2LMIX Input 1 Source 1504*4882a593Smuzhiyun */ 1505*4882a593Smuzhiyun #define WM2200_OUT2LMIX_SRC1_MASK 0x007F /* OUT2LMIX_SRC1 - [6:0] */ 1506*4882a593Smuzhiyun #define WM2200_OUT2LMIX_SRC1_SHIFT 0 /* OUT2LMIX_SRC1 - [6:0] */ 1507*4882a593Smuzhiyun #define WM2200_OUT2LMIX_SRC1_WIDTH 7 /* OUT2LMIX_SRC1 - [6:0] */ 1508*4882a593Smuzhiyun 1509*4882a593Smuzhiyun /* 1510*4882a593Smuzhiyun * R1553 (0x611) - OUT2LMIX Input 1 Volume 1511*4882a593Smuzhiyun */ 1512*4882a593Smuzhiyun #define WM2200_OUT2LMIX_VOL1_MASK 0x00FE /* OUT2LMIX_VOL1 - [7:1] */ 1513*4882a593Smuzhiyun #define WM2200_OUT2LMIX_VOL1_SHIFT 1 /* OUT2LMIX_VOL1 - [7:1] */ 1514*4882a593Smuzhiyun #define WM2200_OUT2LMIX_VOL1_WIDTH 7 /* OUT2LMIX_VOL1 - [7:1] */ 1515*4882a593Smuzhiyun 1516*4882a593Smuzhiyun /* 1517*4882a593Smuzhiyun * R1554 (0x612) - OUT2LMIX Input 2 Source 1518*4882a593Smuzhiyun */ 1519*4882a593Smuzhiyun #define WM2200_OUT2LMIX_SRC2_MASK 0x007F /* OUT2LMIX_SRC2 - [6:0] */ 1520*4882a593Smuzhiyun #define WM2200_OUT2LMIX_SRC2_SHIFT 0 /* OUT2LMIX_SRC2 - [6:0] */ 1521*4882a593Smuzhiyun #define WM2200_OUT2LMIX_SRC2_WIDTH 7 /* OUT2LMIX_SRC2 - [6:0] */ 1522*4882a593Smuzhiyun 1523*4882a593Smuzhiyun /* 1524*4882a593Smuzhiyun * R1555 (0x613) - OUT2LMIX Input 2 Volume 1525*4882a593Smuzhiyun */ 1526*4882a593Smuzhiyun #define WM2200_OUT2LMIX_VOL2_MASK 0x00FE /* OUT2LMIX_VOL2 - [7:1] */ 1527*4882a593Smuzhiyun #define WM2200_OUT2LMIX_VOL2_SHIFT 1 /* OUT2LMIX_VOL2 - [7:1] */ 1528*4882a593Smuzhiyun #define WM2200_OUT2LMIX_VOL2_WIDTH 7 /* OUT2LMIX_VOL2 - [7:1] */ 1529*4882a593Smuzhiyun 1530*4882a593Smuzhiyun /* 1531*4882a593Smuzhiyun * R1556 (0x614) - OUT2LMIX Input 3 Source 1532*4882a593Smuzhiyun */ 1533*4882a593Smuzhiyun #define WM2200_OUT2LMIX_SRC3_MASK 0x007F /* OUT2LMIX_SRC3 - [6:0] */ 1534*4882a593Smuzhiyun #define WM2200_OUT2LMIX_SRC3_SHIFT 0 /* OUT2LMIX_SRC3 - [6:0] */ 1535*4882a593Smuzhiyun #define WM2200_OUT2LMIX_SRC3_WIDTH 7 /* OUT2LMIX_SRC3 - [6:0] */ 1536*4882a593Smuzhiyun 1537*4882a593Smuzhiyun /* 1538*4882a593Smuzhiyun * R1557 (0x615) - OUT2LMIX Input 3 Volume 1539*4882a593Smuzhiyun */ 1540*4882a593Smuzhiyun #define WM2200_OUT2LMIX_VOL3_MASK 0x00FE /* OUT2LMIX_VOL3 - [7:1] */ 1541*4882a593Smuzhiyun #define WM2200_OUT2LMIX_VOL3_SHIFT 1 /* OUT2LMIX_VOL3 - [7:1] */ 1542*4882a593Smuzhiyun #define WM2200_OUT2LMIX_VOL3_WIDTH 7 /* OUT2LMIX_VOL3 - [7:1] */ 1543*4882a593Smuzhiyun 1544*4882a593Smuzhiyun /* 1545*4882a593Smuzhiyun * R1558 (0x616) - OUT2LMIX Input 4 Source 1546*4882a593Smuzhiyun */ 1547*4882a593Smuzhiyun #define WM2200_OUT2LMIX_SRC4_MASK 0x007F /* OUT2LMIX_SRC4 - [6:0] */ 1548*4882a593Smuzhiyun #define WM2200_OUT2LMIX_SRC4_SHIFT 0 /* OUT2LMIX_SRC4 - [6:0] */ 1549*4882a593Smuzhiyun #define WM2200_OUT2LMIX_SRC4_WIDTH 7 /* OUT2LMIX_SRC4 - [6:0] */ 1550*4882a593Smuzhiyun 1551*4882a593Smuzhiyun /* 1552*4882a593Smuzhiyun * R1559 (0x617) - OUT2LMIX Input 4 Volume 1553*4882a593Smuzhiyun */ 1554*4882a593Smuzhiyun #define WM2200_OUT2LMIX_VOL4_MASK 0x00FE /* OUT2LMIX_VOL4 - [7:1] */ 1555*4882a593Smuzhiyun #define WM2200_OUT2LMIX_VOL4_SHIFT 1 /* OUT2LMIX_VOL4 - [7:1] */ 1556*4882a593Smuzhiyun #define WM2200_OUT2LMIX_VOL4_WIDTH 7 /* OUT2LMIX_VOL4 - [7:1] */ 1557*4882a593Smuzhiyun 1558*4882a593Smuzhiyun /* 1559*4882a593Smuzhiyun * R1560 (0x618) - OUT2RMIX Input 1 Source 1560*4882a593Smuzhiyun */ 1561*4882a593Smuzhiyun #define WM2200_OUT2RMIX_SRC1_MASK 0x007F /* OUT2RMIX_SRC1 - [6:0] */ 1562*4882a593Smuzhiyun #define WM2200_OUT2RMIX_SRC1_SHIFT 0 /* OUT2RMIX_SRC1 - [6:0] */ 1563*4882a593Smuzhiyun #define WM2200_OUT2RMIX_SRC1_WIDTH 7 /* OUT2RMIX_SRC1 - [6:0] */ 1564*4882a593Smuzhiyun 1565*4882a593Smuzhiyun /* 1566*4882a593Smuzhiyun * R1561 (0x619) - OUT2RMIX Input 1 Volume 1567*4882a593Smuzhiyun */ 1568*4882a593Smuzhiyun #define WM2200_OUT2RMIX_VOL1_MASK 0x00FE /* OUT2RMIX_VOL1 - [7:1] */ 1569*4882a593Smuzhiyun #define WM2200_OUT2RMIX_VOL1_SHIFT 1 /* OUT2RMIX_VOL1 - [7:1] */ 1570*4882a593Smuzhiyun #define WM2200_OUT2RMIX_VOL1_WIDTH 7 /* OUT2RMIX_VOL1 - [7:1] */ 1571*4882a593Smuzhiyun 1572*4882a593Smuzhiyun /* 1573*4882a593Smuzhiyun * R1562 (0x61A) - OUT2RMIX Input 2 Source 1574*4882a593Smuzhiyun */ 1575*4882a593Smuzhiyun #define WM2200_OUT2RMIX_SRC2_MASK 0x007F /* OUT2RMIX_SRC2 - [6:0] */ 1576*4882a593Smuzhiyun #define WM2200_OUT2RMIX_SRC2_SHIFT 0 /* OUT2RMIX_SRC2 - [6:0] */ 1577*4882a593Smuzhiyun #define WM2200_OUT2RMIX_SRC2_WIDTH 7 /* OUT2RMIX_SRC2 - [6:0] */ 1578*4882a593Smuzhiyun 1579*4882a593Smuzhiyun /* 1580*4882a593Smuzhiyun * R1563 (0x61B) - OUT2RMIX Input 2 Volume 1581*4882a593Smuzhiyun */ 1582*4882a593Smuzhiyun #define WM2200_OUT2RMIX_VOL2_MASK 0x00FE /* OUT2RMIX_VOL2 - [7:1] */ 1583*4882a593Smuzhiyun #define WM2200_OUT2RMIX_VOL2_SHIFT 1 /* OUT2RMIX_VOL2 - [7:1] */ 1584*4882a593Smuzhiyun #define WM2200_OUT2RMIX_VOL2_WIDTH 7 /* OUT2RMIX_VOL2 - [7:1] */ 1585*4882a593Smuzhiyun 1586*4882a593Smuzhiyun /* 1587*4882a593Smuzhiyun * R1564 (0x61C) - OUT2RMIX Input 3 Source 1588*4882a593Smuzhiyun */ 1589*4882a593Smuzhiyun #define WM2200_OUT2RMIX_SRC3_MASK 0x007F /* OUT2RMIX_SRC3 - [6:0] */ 1590*4882a593Smuzhiyun #define WM2200_OUT2RMIX_SRC3_SHIFT 0 /* OUT2RMIX_SRC3 - [6:0] */ 1591*4882a593Smuzhiyun #define WM2200_OUT2RMIX_SRC3_WIDTH 7 /* OUT2RMIX_SRC3 - [6:0] */ 1592*4882a593Smuzhiyun 1593*4882a593Smuzhiyun /* 1594*4882a593Smuzhiyun * R1565 (0x61D) - OUT2RMIX Input 3 Volume 1595*4882a593Smuzhiyun */ 1596*4882a593Smuzhiyun #define WM2200_OUT2RMIX_VOL3_MASK 0x00FE /* OUT2RMIX_VOL3 - [7:1] */ 1597*4882a593Smuzhiyun #define WM2200_OUT2RMIX_VOL3_SHIFT 1 /* OUT2RMIX_VOL3 - [7:1] */ 1598*4882a593Smuzhiyun #define WM2200_OUT2RMIX_VOL3_WIDTH 7 /* OUT2RMIX_VOL3 - [7:1] */ 1599*4882a593Smuzhiyun 1600*4882a593Smuzhiyun /* 1601*4882a593Smuzhiyun * R1566 (0x61E) - OUT2RMIX Input 4 Source 1602*4882a593Smuzhiyun */ 1603*4882a593Smuzhiyun #define WM2200_OUT2RMIX_SRC4_MASK 0x007F /* OUT2RMIX_SRC4 - [6:0] */ 1604*4882a593Smuzhiyun #define WM2200_OUT2RMIX_SRC4_SHIFT 0 /* OUT2RMIX_SRC4 - [6:0] */ 1605*4882a593Smuzhiyun #define WM2200_OUT2RMIX_SRC4_WIDTH 7 /* OUT2RMIX_SRC4 - [6:0] */ 1606*4882a593Smuzhiyun 1607*4882a593Smuzhiyun /* 1608*4882a593Smuzhiyun * R1567 (0x61F) - OUT2RMIX Input 4 Volume 1609*4882a593Smuzhiyun */ 1610*4882a593Smuzhiyun #define WM2200_OUT2RMIX_VOL4_MASK 0x00FE /* OUT2RMIX_VOL4 - [7:1] */ 1611*4882a593Smuzhiyun #define WM2200_OUT2RMIX_VOL4_SHIFT 1 /* OUT2RMIX_VOL4 - [7:1] */ 1612*4882a593Smuzhiyun #define WM2200_OUT2RMIX_VOL4_WIDTH 7 /* OUT2RMIX_VOL4 - [7:1] */ 1613*4882a593Smuzhiyun 1614*4882a593Smuzhiyun /* 1615*4882a593Smuzhiyun * R1568 (0x620) - AIF1TX1MIX Input 1 Source 1616*4882a593Smuzhiyun */ 1617*4882a593Smuzhiyun #define WM2200_AIF1TX1MIX_SRC1_MASK 0x007F /* AIF1TX1MIX_SRC1 - [6:0] */ 1618*4882a593Smuzhiyun #define WM2200_AIF1TX1MIX_SRC1_SHIFT 0 /* AIF1TX1MIX_SRC1 - [6:0] */ 1619*4882a593Smuzhiyun #define WM2200_AIF1TX1MIX_SRC1_WIDTH 7 /* AIF1TX1MIX_SRC1 - [6:0] */ 1620*4882a593Smuzhiyun 1621*4882a593Smuzhiyun /* 1622*4882a593Smuzhiyun * R1569 (0x621) - AIF1TX1MIX Input 1 Volume 1623*4882a593Smuzhiyun */ 1624*4882a593Smuzhiyun #define WM2200_AIF1TX1MIX_VOL1_MASK 0x00FE /* AIF1TX1MIX_VOL1 - [7:1] */ 1625*4882a593Smuzhiyun #define WM2200_AIF1TX1MIX_VOL1_SHIFT 1 /* AIF1TX1MIX_VOL1 - [7:1] */ 1626*4882a593Smuzhiyun #define WM2200_AIF1TX1MIX_VOL1_WIDTH 7 /* AIF1TX1MIX_VOL1 - [7:1] */ 1627*4882a593Smuzhiyun 1628*4882a593Smuzhiyun /* 1629*4882a593Smuzhiyun * R1570 (0x622) - AIF1TX1MIX Input 2 Source 1630*4882a593Smuzhiyun */ 1631*4882a593Smuzhiyun #define WM2200_AIF1TX1MIX_SRC2_MASK 0x007F /* AIF1TX1MIX_SRC2 - [6:0] */ 1632*4882a593Smuzhiyun #define WM2200_AIF1TX1MIX_SRC2_SHIFT 0 /* AIF1TX1MIX_SRC2 - [6:0] */ 1633*4882a593Smuzhiyun #define WM2200_AIF1TX1MIX_SRC2_WIDTH 7 /* AIF1TX1MIX_SRC2 - [6:0] */ 1634*4882a593Smuzhiyun 1635*4882a593Smuzhiyun /* 1636*4882a593Smuzhiyun * R1571 (0x623) - AIF1TX1MIX Input 2 Volume 1637*4882a593Smuzhiyun */ 1638*4882a593Smuzhiyun #define WM2200_AIF1TX1MIX_VOL2_MASK 0x00FE /* AIF1TX1MIX_VOL2 - [7:1] */ 1639*4882a593Smuzhiyun #define WM2200_AIF1TX1MIX_VOL2_SHIFT 1 /* AIF1TX1MIX_VOL2 - [7:1] */ 1640*4882a593Smuzhiyun #define WM2200_AIF1TX1MIX_VOL2_WIDTH 7 /* AIF1TX1MIX_VOL2 - [7:1] */ 1641*4882a593Smuzhiyun 1642*4882a593Smuzhiyun /* 1643*4882a593Smuzhiyun * R1572 (0x624) - AIF1TX1MIX Input 3 Source 1644*4882a593Smuzhiyun */ 1645*4882a593Smuzhiyun #define WM2200_AIF1TX1MIX_SRC3_MASK 0x007F /* AIF1TX1MIX_SRC3 - [6:0] */ 1646*4882a593Smuzhiyun #define WM2200_AIF1TX1MIX_SRC3_SHIFT 0 /* AIF1TX1MIX_SRC3 - [6:0] */ 1647*4882a593Smuzhiyun #define WM2200_AIF1TX1MIX_SRC3_WIDTH 7 /* AIF1TX1MIX_SRC3 - [6:0] */ 1648*4882a593Smuzhiyun 1649*4882a593Smuzhiyun /* 1650*4882a593Smuzhiyun * R1573 (0x625) - AIF1TX1MIX Input 3 Volume 1651*4882a593Smuzhiyun */ 1652*4882a593Smuzhiyun #define WM2200_AIF1TX1MIX_VOL3_MASK 0x00FE /* AIF1TX1MIX_VOL3 - [7:1] */ 1653*4882a593Smuzhiyun #define WM2200_AIF1TX1MIX_VOL3_SHIFT 1 /* AIF1TX1MIX_VOL3 - [7:1] */ 1654*4882a593Smuzhiyun #define WM2200_AIF1TX1MIX_VOL3_WIDTH 7 /* AIF1TX1MIX_VOL3 - [7:1] */ 1655*4882a593Smuzhiyun 1656*4882a593Smuzhiyun /* 1657*4882a593Smuzhiyun * R1574 (0x626) - AIF1TX1MIX Input 4 Source 1658*4882a593Smuzhiyun */ 1659*4882a593Smuzhiyun #define WM2200_AIF1TX1MIX_SRC4_MASK 0x007F /* AIF1TX1MIX_SRC4 - [6:0] */ 1660*4882a593Smuzhiyun #define WM2200_AIF1TX1MIX_SRC4_SHIFT 0 /* AIF1TX1MIX_SRC4 - [6:0] */ 1661*4882a593Smuzhiyun #define WM2200_AIF1TX1MIX_SRC4_WIDTH 7 /* AIF1TX1MIX_SRC4 - [6:0] */ 1662*4882a593Smuzhiyun 1663*4882a593Smuzhiyun /* 1664*4882a593Smuzhiyun * R1575 (0x627) - AIF1TX1MIX Input 4 Volume 1665*4882a593Smuzhiyun */ 1666*4882a593Smuzhiyun #define WM2200_AIF1TX1MIX_VOL4_MASK 0x00FE /* AIF1TX1MIX_VOL4 - [7:1] */ 1667*4882a593Smuzhiyun #define WM2200_AIF1TX1MIX_VOL4_SHIFT 1 /* AIF1TX1MIX_VOL4 - [7:1] */ 1668*4882a593Smuzhiyun #define WM2200_AIF1TX1MIX_VOL4_WIDTH 7 /* AIF1TX1MIX_VOL4 - [7:1] */ 1669*4882a593Smuzhiyun 1670*4882a593Smuzhiyun /* 1671*4882a593Smuzhiyun * R1576 (0x628) - AIF1TX2MIX Input 1 Source 1672*4882a593Smuzhiyun */ 1673*4882a593Smuzhiyun #define WM2200_AIF1TX2MIX_SRC1_MASK 0x007F /* AIF1TX2MIX_SRC1 - [6:0] */ 1674*4882a593Smuzhiyun #define WM2200_AIF1TX2MIX_SRC1_SHIFT 0 /* AIF1TX2MIX_SRC1 - [6:0] */ 1675*4882a593Smuzhiyun #define WM2200_AIF1TX2MIX_SRC1_WIDTH 7 /* AIF1TX2MIX_SRC1 - [6:0] */ 1676*4882a593Smuzhiyun 1677*4882a593Smuzhiyun /* 1678*4882a593Smuzhiyun * R1577 (0x629) - AIF1TX2MIX Input 1 Volume 1679*4882a593Smuzhiyun */ 1680*4882a593Smuzhiyun #define WM2200_AIF1TX2MIX_VOL1_MASK 0x00FE /* AIF1TX2MIX_VOL1 - [7:1] */ 1681*4882a593Smuzhiyun #define WM2200_AIF1TX2MIX_VOL1_SHIFT 1 /* AIF1TX2MIX_VOL1 - [7:1] */ 1682*4882a593Smuzhiyun #define WM2200_AIF1TX2MIX_VOL1_WIDTH 7 /* AIF1TX2MIX_VOL1 - [7:1] */ 1683*4882a593Smuzhiyun 1684*4882a593Smuzhiyun /* 1685*4882a593Smuzhiyun * R1578 (0x62A) - AIF1TX2MIX Input 2 Source 1686*4882a593Smuzhiyun */ 1687*4882a593Smuzhiyun #define WM2200_AIF1TX2MIX_SRC2_MASK 0x007F /* AIF1TX2MIX_SRC2 - [6:0] */ 1688*4882a593Smuzhiyun #define WM2200_AIF1TX2MIX_SRC2_SHIFT 0 /* AIF1TX2MIX_SRC2 - [6:0] */ 1689*4882a593Smuzhiyun #define WM2200_AIF1TX2MIX_SRC2_WIDTH 7 /* AIF1TX2MIX_SRC2 - [6:0] */ 1690*4882a593Smuzhiyun 1691*4882a593Smuzhiyun /* 1692*4882a593Smuzhiyun * R1579 (0x62B) - AIF1TX2MIX Input 2 Volume 1693*4882a593Smuzhiyun */ 1694*4882a593Smuzhiyun #define WM2200_AIF1TX2MIX_VOL2_MASK 0x00FE /* AIF1TX2MIX_VOL2 - [7:1] */ 1695*4882a593Smuzhiyun #define WM2200_AIF1TX2MIX_VOL2_SHIFT 1 /* AIF1TX2MIX_VOL2 - [7:1] */ 1696*4882a593Smuzhiyun #define WM2200_AIF1TX2MIX_VOL2_WIDTH 7 /* AIF1TX2MIX_VOL2 - [7:1] */ 1697*4882a593Smuzhiyun 1698*4882a593Smuzhiyun /* 1699*4882a593Smuzhiyun * R1580 (0x62C) - AIF1TX2MIX Input 3 Source 1700*4882a593Smuzhiyun */ 1701*4882a593Smuzhiyun #define WM2200_AIF1TX2MIX_SRC3_MASK 0x007F /* AIF1TX2MIX_SRC3 - [6:0] */ 1702*4882a593Smuzhiyun #define WM2200_AIF1TX2MIX_SRC3_SHIFT 0 /* AIF1TX2MIX_SRC3 - [6:0] */ 1703*4882a593Smuzhiyun #define WM2200_AIF1TX2MIX_SRC3_WIDTH 7 /* AIF1TX2MIX_SRC3 - [6:0] */ 1704*4882a593Smuzhiyun 1705*4882a593Smuzhiyun /* 1706*4882a593Smuzhiyun * R1581 (0x62D) - AIF1TX2MIX Input 3 Volume 1707*4882a593Smuzhiyun */ 1708*4882a593Smuzhiyun #define WM2200_AIF1TX2MIX_VOL3_MASK 0x00FE /* AIF1TX2MIX_VOL3 - [7:1] */ 1709*4882a593Smuzhiyun #define WM2200_AIF1TX2MIX_VOL3_SHIFT 1 /* AIF1TX2MIX_VOL3 - [7:1] */ 1710*4882a593Smuzhiyun #define WM2200_AIF1TX2MIX_VOL3_WIDTH 7 /* AIF1TX2MIX_VOL3 - [7:1] */ 1711*4882a593Smuzhiyun 1712*4882a593Smuzhiyun /* 1713*4882a593Smuzhiyun * R1582 (0x62E) - AIF1TX2MIX Input 4 Source 1714*4882a593Smuzhiyun */ 1715*4882a593Smuzhiyun #define WM2200_AIF1TX2MIX_SRC4_MASK 0x007F /* AIF1TX2MIX_SRC4 - [6:0] */ 1716*4882a593Smuzhiyun #define WM2200_AIF1TX2MIX_SRC4_SHIFT 0 /* AIF1TX2MIX_SRC4 - [6:0] */ 1717*4882a593Smuzhiyun #define WM2200_AIF1TX2MIX_SRC4_WIDTH 7 /* AIF1TX2MIX_SRC4 - [6:0] */ 1718*4882a593Smuzhiyun 1719*4882a593Smuzhiyun /* 1720*4882a593Smuzhiyun * R1583 (0x62F) - AIF1TX2MIX Input 4 Volume 1721*4882a593Smuzhiyun */ 1722*4882a593Smuzhiyun #define WM2200_AIF1TX2MIX_VOL4_MASK 0x00FE /* AIF1TX2MIX_VOL4 - [7:1] */ 1723*4882a593Smuzhiyun #define WM2200_AIF1TX2MIX_VOL4_SHIFT 1 /* AIF1TX2MIX_VOL4 - [7:1] */ 1724*4882a593Smuzhiyun #define WM2200_AIF1TX2MIX_VOL4_WIDTH 7 /* AIF1TX2MIX_VOL4 - [7:1] */ 1725*4882a593Smuzhiyun 1726*4882a593Smuzhiyun /* 1727*4882a593Smuzhiyun * R1584 (0x630) - AIF1TX3MIX Input 1 Source 1728*4882a593Smuzhiyun */ 1729*4882a593Smuzhiyun #define WM2200_AIF1TX3MIX_SRC1_MASK 0x007F /* AIF1TX3MIX_SRC1 - [6:0] */ 1730*4882a593Smuzhiyun #define WM2200_AIF1TX3MIX_SRC1_SHIFT 0 /* AIF1TX3MIX_SRC1 - [6:0] */ 1731*4882a593Smuzhiyun #define WM2200_AIF1TX3MIX_SRC1_WIDTH 7 /* AIF1TX3MIX_SRC1 - [6:0] */ 1732*4882a593Smuzhiyun 1733*4882a593Smuzhiyun /* 1734*4882a593Smuzhiyun * R1585 (0x631) - AIF1TX3MIX Input 1 Volume 1735*4882a593Smuzhiyun */ 1736*4882a593Smuzhiyun #define WM2200_AIF1TX3MIX_VOL1_MASK 0x00FE /* AIF1TX3MIX_VOL1 - [7:1] */ 1737*4882a593Smuzhiyun #define WM2200_AIF1TX3MIX_VOL1_SHIFT 1 /* AIF1TX3MIX_VOL1 - [7:1] */ 1738*4882a593Smuzhiyun #define WM2200_AIF1TX3MIX_VOL1_WIDTH 7 /* AIF1TX3MIX_VOL1 - [7:1] */ 1739*4882a593Smuzhiyun 1740*4882a593Smuzhiyun /* 1741*4882a593Smuzhiyun * R1586 (0x632) - AIF1TX3MIX Input 2 Source 1742*4882a593Smuzhiyun */ 1743*4882a593Smuzhiyun #define WM2200_AIF1TX3MIX_SRC2_MASK 0x007F /* AIF1TX3MIX_SRC2 - [6:0] */ 1744*4882a593Smuzhiyun #define WM2200_AIF1TX3MIX_SRC2_SHIFT 0 /* AIF1TX3MIX_SRC2 - [6:0] */ 1745*4882a593Smuzhiyun #define WM2200_AIF1TX3MIX_SRC2_WIDTH 7 /* AIF1TX3MIX_SRC2 - [6:0] */ 1746*4882a593Smuzhiyun 1747*4882a593Smuzhiyun /* 1748*4882a593Smuzhiyun * R1587 (0x633) - AIF1TX3MIX Input 2 Volume 1749*4882a593Smuzhiyun */ 1750*4882a593Smuzhiyun #define WM2200_AIF1TX3MIX_VOL2_MASK 0x00FE /* AIF1TX3MIX_VOL2 - [7:1] */ 1751*4882a593Smuzhiyun #define WM2200_AIF1TX3MIX_VOL2_SHIFT 1 /* AIF1TX3MIX_VOL2 - [7:1] */ 1752*4882a593Smuzhiyun #define WM2200_AIF1TX3MIX_VOL2_WIDTH 7 /* AIF1TX3MIX_VOL2 - [7:1] */ 1753*4882a593Smuzhiyun 1754*4882a593Smuzhiyun /* 1755*4882a593Smuzhiyun * R1588 (0x634) - AIF1TX3MIX Input 3 Source 1756*4882a593Smuzhiyun */ 1757*4882a593Smuzhiyun #define WM2200_AIF1TX3MIX_SRC3_MASK 0x007F /* AIF1TX3MIX_SRC3 - [6:0] */ 1758*4882a593Smuzhiyun #define WM2200_AIF1TX3MIX_SRC3_SHIFT 0 /* AIF1TX3MIX_SRC3 - [6:0] */ 1759*4882a593Smuzhiyun #define WM2200_AIF1TX3MIX_SRC3_WIDTH 7 /* AIF1TX3MIX_SRC3 - [6:0] */ 1760*4882a593Smuzhiyun 1761*4882a593Smuzhiyun /* 1762*4882a593Smuzhiyun * R1589 (0x635) - AIF1TX3MIX Input 3 Volume 1763*4882a593Smuzhiyun */ 1764*4882a593Smuzhiyun #define WM2200_AIF1TX3MIX_VOL3_MASK 0x00FE /* AIF1TX3MIX_VOL3 - [7:1] */ 1765*4882a593Smuzhiyun #define WM2200_AIF1TX3MIX_VOL3_SHIFT 1 /* AIF1TX3MIX_VOL3 - [7:1] */ 1766*4882a593Smuzhiyun #define WM2200_AIF1TX3MIX_VOL3_WIDTH 7 /* AIF1TX3MIX_VOL3 - [7:1] */ 1767*4882a593Smuzhiyun 1768*4882a593Smuzhiyun /* 1769*4882a593Smuzhiyun * R1590 (0x636) - AIF1TX3MIX Input 4 Source 1770*4882a593Smuzhiyun */ 1771*4882a593Smuzhiyun #define WM2200_AIF1TX3MIX_SRC4_MASK 0x007F /* AIF1TX3MIX_SRC4 - [6:0] */ 1772*4882a593Smuzhiyun #define WM2200_AIF1TX3MIX_SRC4_SHIFT 0 /* AIF1TX3MIX_SRC4 - [6:0] */ 1773*4882a593Smuzhiyun #define WM2200_AIF1TX3MIX_SRC4_WIDTH 7 /* AIF1TX3MIX_SRC4 - [6:0] */ 1774*4882a593Smuzhiyun 1775*4882a593Smuzhiyun /* 1776*4882a593Smuzhiyun * R1591 (0x637) - AIF1TX3MIX Input 4 Volume 1777*4882a593Smuzhiyun */ 1778*4882a593Smuzhiyun #define WM2200_AIF1TX3MIX_VOL4_MASK 0x00FE /* AIF1TX3MIX_VOL4 - [7:1] */ 1779*4882a593Smuzhiyun #define WM2200_AIF1TX3MIX_VOL4_SHIFT 1 /* AIF1TX3MIX_VOL4 - [7:1] */ 1780*4882a593Smuzhiyun #define WM2200_AIF1TX3MIX_VOL4_WIDTH 7 /* AIF1TX3MIX_VOL4 - [7:1] */ 1781*4882a593Smuzhiyun 1782*4882a593Smuzhiyun /* 1783*4882a593Smuzhiyun * R1592 (0x638) - AIF1TX4MIX Input 1 Source 1784*4882a593Smuzhiyun */ 1785*4882a593Smuzhiyun #define WM2200_AIF1TX4MIX_SRC1_MASK 0x007F /* AIF1TX4MIX_SRC1 - [6:0] */ 1786*4882a593Smuzhiyun #define WM2200_AIF1TX4MIX_SRC1_SHIFT 0 /* AIF1TX4MIX_SRC1 - [6:0] */ 1787*4882a593Smuzhiyun #define WM2200_AIF1TX4MIX_SRC1_WIDTH 7 /* AIF1TX4MIX_SRC1 - [6:0] */ 1788*4882a593Smuzhiyun 1789*4882a593Smuzhiyun /* 1790*4882a593Smuzhiyun * R1593 (0x639) - AIF1TX4MIX Input 1 Volume 1791*4882a593Smuzhiyun */ 1792*4882a593Smuzhiyun #define WM2200_AIF1TX4MIX_VOL1_MASK 0x00FE /* AIF1TX4MIX_VOL1 - [7:1] */ 1793*4882a593Smuzhiyun #define WM2200_AIF1TX4MIX_VOL1_SHIFT 1 /* AIF1TX4MIX_VOL1 - [7:1] */ 1794*4882a593Smuzhiyun #define WM2200_AIF1TX4MIX_VOL1_WIDTH 7 /* AIF1TX4MIX_VOL1 - [7:1] */ 1795*4882a593Smuzhiyun 1796*4882a593Smuzhiyun /* 1797*4882a593Smuzhiyun * R1594 (0x63A) - AIF1TX4MIX Input 2 Source 1798*4882a593Smuzhiyun */ 1799*4882a593Smuzhiyun #define WM2200_AIF1TX4MIX_SRC2_MASK 0x007F /* AIF1TX4MIX_SRC2 - [6:0] */ 1800*4882a593Smuzhiyun #define WM2200_AIF1TX4MIX_SRC2_SHIFT 0 /* AIF1TX4MIX_SRC2 - [6:0] */ 1801*4882a593Smuzhiyun #define WM2200_AIF1TX4MIX_SRC2_WIDTH 7 /* AIF1TX4MIX_SRC2 - [6:0] */ 1802*4882a593Smuzhiyun 1803*4882a593Smuzhiyun /* 1804*4882a593Smuzhiyun * R1595 (0x63B) - AIF1TX4MIX Input 2 Volume 1805*4882a593Smuzhiyun */ 1806*4882a593Smuzhiyun #define WM2200_AIF1TX4MIX_VOL2_MASK 0x00FE /* AIF1TX4MIX_VOL2 - [7:1] */ 1807*4882a593Smuzhiyun #define WM2200_AIF1TX4MIX_VOL2_SHIFT 1 /* AIF1TX4MIX_VOL2 - [7:1] */ 1808*4882a593Smuzhiyun #define WM2200_AIF1TX4MIX_VOL2_WIDTH 7 /* AIF1TX4MIX_VOL2 - [7:1] */ 1809*4882a593Smuzhiyun 1810*4882a593Smuzhiyun /* 1811*4882a593Smuzhiyun * R1596 (0x63C) - AIF1TX4MIX Input 3 Source 1812*4882a593Smuzhiyun */ 1813*4882a593Smuzhiyun #define WM2200_AIF1TX4MIX_SRC3_MASK 0x007F /* AIF1TX4MIX_SRC3 - [6:0] */ 1814*4882a593Smuzhiyun #define WM2200_AIF1TX4MIX_SRC3_SHIFT 0 /* AIF1TX4MIX_SRC3 - [6:0] */ 1815*4882a593Smuzhiyun #define WM2200_AIF1TX4MIX_SRC3_WIDTH 7 /* AIF1TX4MIX_SRC3 - [6:0] */ 1816*4882a593Smuzhiyun 1817*4882a593Smuzhiyun /* 1818*4882a593Smuzhiyun * R1597 (0x63D) - AIF1TX4MIX Input 3 Volume 1819*4882a593Smuzhiyun */ 1820*4882a593Smuzhiyun #define WM2200_AIF1TX4MIX_VOL3_MASK 0x00FE /* AIF1TX4MIX_VOL3 - [7:1] */ 1821*4882a593Smuzhiyun #define WM2200_AIF1TX4MIX_VOL3_SHIFT 1 /* AIF1TX4MIX_VOL3 - [7:1] */ 1822*4882a593Smuzhiyun #define WM2200_AIF1TX4MIX_VOL3_WIDTH 7 /* AIF1TX4MIX_VOL3 - [7:1] */ 1823*4882a593Smuzhiyun 1824*4882a593Smuzhiyun /* 1825*4882a593Smuzhiyun * R1598 (0x63E) - AIF1TX4MIX Input 4 Source 1826*4882a593Smuzhiyun */ 1827*4882a593Smuzhiyun #define WM2200_AIF1TX4MIX_SRC4_MASK 0x007F /* AIF1TX4MIX_SRC4 - [6:0] */ 1828*4882a593Smuzhiyun #define WM2200_AIF1TX4MIX_SRC4_SHIFT 0 /* AIF1TX4MIX_SRC4 - [6:0] */ 1829*4882a593Smuzhiyun #define WM2200_AIF1TX4MIX_SRC4_WIDTH 7 /* AIF1TX4MIX_SRC4 - [6:0] */ 1830*4882a593Smuzhiyun 1831*4882a593Smuzhiyun /* 1832*4882a593Smuzhiyun * R1599 (0x63F) - AIF1TX4MIX Input 4 Volume 1833*4882a593Smuzhiyun */ 1834*4882a593Smuzhiyun #define WM2200_AIF1TX4MIX_VOL4_MASK 0x00FE /* AIF1TX4MIX_VOL4 - [7:1] */ 1835*4882a593Smuzhiyun #define WM2200_AIF1TX4MIX_VOL4_SHIFT 1 /* AIF1TX4MIX_VOL4 - [7:1] */ 1836*4882a593Smuzhiyun #define WM2200_AIF1TX4MIX_VOL4_WIDTH 7 /* AIF1TX4MIX_VOL4 - [7:1] */ 1837*4882a593Smuzhiyun 1838*4882a593Smuzhiyun /* 1839*4882a593Smuzhiyun * R1600 (0x640) - AIF1TX5MIX Input 1 Source 1840*4882a593Smuzhiyun */ 1841*4882a593Smuzhiyun #define WM2200_AIF1TX5MIX_SRC1_MASK 0x007F /* AIF1TX5MIX_SRC1 - [6:0] */ 1842*4882a593Smuzhiyun #define WM2200_AIF1TX5MIX_SRC1_SHIFT 0 /* AIF1TX5MIX_SRC1 - [6:0] */ 1843*4882a593Smuzhiyun #define WM2200_AIF1TX5MIX_SRC1_WIDTH 7 /* AIF1TX5MIX_SRC1 - [6:0] */ 1844*4882a593Smuzhiyun 1845*4882a593Smuzhiyun /* 1846*4882a593Smuzhiyun * R1601 (0x641) - AIF1TX5MIX Input 1 Volume 1847*4882a593Smuzhiyun */ 1848*4882a593Smuzhiyun #define WM2200_AIF1TX5MIX_VOL1_MASK 0x00FE /* AIF1TX5MIX_VOL1 - [7:1] */ 1849*4882a593Smuzhiyun #define WM2200_AIF1TX5MIX_VOL1_SHIFT 1 /* AIF1TX5MIX_VOL1 - [7:1] */ 1850*4882a593Smuzhiyun #define WM2200_AIF1TX5MIX_VOL1_WIDTH 7 /* AIF1TX5MIX_VOL1 - [7:1] */ 1851*4882a593Smuzhiyun 1852*4882a593Smuzhiyun /* 1853*4882a593Smuzhiyun * R1602 (0x642) - AIF1TX5MIX Input 2 Source 1854*4882a593Smuzhiyun */ 1855*4882a593Smuzhiyun #define WM2200_AIF1TX5MIX_SRC2_MASK 0x007F /* AIF1TX5MIX_SRC2 - [6:0] */ 1856*4882a593Smuzhiyun #define WM2200_AIF1TX5MIX_SRC2_SHIFT 0 /* AIF1TX5MIX_SRC2 - [6:0] */ 1857*4882a593Smuzhiyun #define WM2200_AIF1TX5MIX_SRC2_WIDTH 7 /* AIF1TX5MIX_SRC2 - [6:0] */ 1858*4882a593Smuzhiyun 1859*4882a593Smuzhiyun /* 1860*4882a593Smuzhiyun * R1603 (0x643) - AIF1TX5MIX Input 2 Volume 1861*4882a593Smuzhiyun */ 1862*4882a593Smuzhiyun #define WM2200_AIF1TX5MIX_VOL2_MASK 0x00FE /* AIF1TX5MIX_VOL2 - [7:1] */ 1863*4882a593Smuzhiyun #define WM2200_AIF1TX5MIX_VOL2_SHIFT 1 /* AIF1TX5MIX_VOL2 - [7:1] */ 1864*4882a593Smuzhiyun #define WM2200_AIF1TX5MIX_VOL2_WIDTH 7 /* AIF1TX5MIX_VOL2 - [7:1] */ 1865*4882a593Smuzhiyun 1866*4882a593Smuzhiyun /* 1867*4882a593Smuzhiyun * R1604 (0x644) - AIF1TX5MIX Input 3 Source 1868*4882a593Smuzhiyun */ 1869*4882a593Smuzhiyun #define WM2200_AIF1TX5MIX_SRC3_MASK 0x007F /* AIF1TX5MIX_SRC3 - [6:0] */ 1870*4882a593Smuzhiyun #define WM2200_AIF1TX5MIX_SRC3_SHIFT 0 /* AIF1TX5MIX_SRC3 - [6:0] */ 1871*4882a593Smuzhiyun #define WM2200_AIF1TX5MIX_SRC3_WIDTH 7 /* AIF1TX5MIX_SRC3 - [6:0] */ 1872*4882a593Smuzhiyun 1873*4882a593Smuzhiyun /* 1874*4882a593Smuzhiyun * R1605 (0x645) - AIF1TX5MIX Input 3 Volume 1875*4882a593Smuzhiyun */ 1876*4882a593Smuzhiyun #define WM2200_AIF1TX5MIX_VOL3_MASK 0x00FE /* AIF1TX5MIX_VOL3 - [7:1] */ 1877*4882a593Smuzhiyun #define WM2200_AIF1TX5MIX_VOL3_SHIFT 1 /* AIF1TX5MIX_VOL3 - [7:1] */ 1878*4882a593Smuzhiyun #define WM2200_AIF1TX5MIX_VOL3_WIDTH 7 /* AIF1TX5MIX_VOL3 - [7:1] */ 1879*4882a593Smuzhiyun 1880*4882a593Smuzhiyun /* 1881*4882a593Smuzhiyun * R1606 (0x646) - AIF1TX5MIX Input 4 Source 1882*4882a593Smuzhiyun */ 1883*4882a593Smuzhiyun #define WM2200_AIF1TX5MIX_SRC4_MASK 0x007F /* AIF1TX5MIX_SRC4 - [6:0] */ 1884*4882a593Smuzhiyun #define WM2200_AIF1TX5MIX_SRC4_SHIFT 0 /* AIF1TX5MIX_SRC4 - [6:0] */ 1885*4882a593Smuzhiyun #define WM2200_AIF1TX5MIX_SRC4_WIDTH 7 /* AIF1TX5MIX_SRC4 - [6:0] */ 1886*4882a593Smuzhiyun 1887*4882a593Smuzhiyun /* 1888*4882a593Smuzhiyun * R1607 (0x647) - AIF1TX5MIX Input 4 Volume 1889*4882a593Smuzhiyun */ 1890*4882a593Smuzhiyun #define WM2200_AIF1TX5MIX_VOL4_MASK 0x00FE /* AIF1TX5MIX_VOL4 - [7:1] */ 1891*4882a593Smuzhiyun #define WM2200_AIF1TX5MIX_VOL4_SHIFT 1 /* AIF1TX5MIX_VOL4 - [7:1] */ 1892*4882a593Smuzhiyun #define WM2200_AIF1TX5MIX_VOL4_WIDTH 7 /* AIF1TX5MIX_VOL4 - [7:1] */ 1893*4882a593Smuzhiyun 1894*4882a593Smuzhiyun /* 1895*4882a593Smuzhiyun * R1608 (0x648) - AIF1TX6MIX Input 1 Source 1896*4882a593Smuzhiyun */ 1897*4882a593Smuzhiyun #define WM2200_AIF1TX6MIX_SRC1_MASK 0x007F /* AIF1TX6MIX_SRC1 - [6:0] */ 1898*4882a593Smuzhiyun #define WM2200_AIF1TX6MIX_SRC1_SHIFT 0 /* AIF1TX6MIX_SRC1 - [6:0] */ 1899*4882a593Smuzhiyun #define WM2200_AIF1TX6MIX_SRC1_WIDTH 7 /* AIF1TX6MIX_SRC1 - [6:0] */ 1900*4882a593Smuzhiyun 1901*4882a593Smuzhiyun /* 1902*4882a593Smuzhiyun * R1609 (0x649) - AIF1TX6MIX Input 1 Volume 1903*4882a593Smuzhiyun */ 1904*4882a593Smuzhiyun #define WM2200_AIF1TX6MIX_VOL1_MASK 0x00FE /* AIF1TX6MIX_VOL1 - [7:1] */ 1905*4882a593Smuzhiyun #define WM2200_AIF1TX6MIX_VOL1_SHIFT 1 /* AIF1TX6MIX_VOL1 - [7:1] */ 1906*4882a593Smuzhiyun #define WM2200_AIF1TX6MIX_VOL1_WIDTH 7 /* AIF1TX6MIX_VOL1 - [7:1] */ 1907*4882a593Smuzhiyun 1908*4882a593Smuzhiyun /* 1909*4882a593Smuzhiyun * R1610 (0x64A) - AIF1TX6MIX Input 2 Source 1910*4882a593Smuzhiyun */ 1911*4882a593Smuzhiyun #define WM2200_AIF1TX6MIX_SRC2_MASK 0x007F /* AIF1TX6MIX_SRC2 - [6:0] */ 1912*4882a593Smuzhiyun #define WM2200_AIF1TX6MIX_SRC2_SHIFT 0 /* AIF1TX6MIX_SRC2 - [6:0] */ 1913*4882a593Smuzhiyun #define WM2200_AIF1TX6MIX_SRC2_WIDTH 7 /* AIF1TX6MIX_SRC2 - [6:0] */ 1914*4882a593Smuzhiyun 1915*4882a593Smuzhiyun /* 1916*4882a593Smuzhiyun * R1611 (0x64B) - AIF1TX6MIX Input 2 Volume 1917*4882a593Smuzhiyun */ 1918*4882a593Smuzhiyun #define WM2200_AIF1TX6MIX_VOL2_MASK 0x00FE /* AIF1TX6MIX_VOL2 - [7:1] */ 1919*4882a593Smuzhiyun #define WM2200_AIF1TX6MIX_VOL2_SHIFT 1 /* AIF1TX6MIX_VOL2 - [7:1] */ 1920*4882a593Smuzhiyun #define WM2200_AIF1TX6MIX_VOL2_WIDTH 7 /* AIF1TX6MIX_VOL2 - [7:1] */ 1921*4882a593Smuzhiyun 1922*4882a593Smuzhiyun /* 1923*4882a593Smuzhiyun * R1612 (0x64C) - AIF1TX6MIX Input 3 Source 1924*4882a593Smuzhiyun */ 1925*4882a593Smuzhiyun #define WM2200_AIF1TX6MIX_SRC3_MASK 0x007F /* AIF1TX6MIX_SRC3 - [6:0] */ 1926*4882a593Smuzhiyun #define WM2200_AIF1TX6MIX_SRC3_SHIFT 0 /* AIF1TX6MIX_SRC3 - [6:0] */ 1927*4882a593Smuzhiyun #define WM2200_AIF1TX6MIX_SRC3_WIDTH 7 /* AIF1TX6MIX_SRC3 - [6:0] */ 1928*4882a593Smuzhiyun 1929*4882a593Smuzhiyun /* 1930*4882a593Smuzhiyun * R1613 (0x64D) - AIF1TX6MIX Input 3 Volume 1931*4882a593Smuzhiyun */ 1932*4882a593Smuzhiyun #define WM2200_AIF1TX6MIX_VOL3_MASK 0x00FE /* AIF1TX6MIX_VOL3 - [7:1] */ 1933*4882a593Smuzhiyun #define WM2200_AIF1TX6MIX_VOL3_SHIFT 1 /* AIF1TX6MIX_VOL3 - [7:1] */ 1934*4882a593Smuzhiyun #define WM2200_AIF1TX6MIX_VOL3_WIDTH 7 /* AIF1TX6MIX_VOL3 - [7:1] */ 1935*4882a593Smuzhiyun 1936*4882a593Smuzhiyun /* 1937*4882a593Smuzhiyun * R1614 (0x64E) - AIF1TX6MIX Input 4 Source 1938*4882a593Smuzhiyun */ 1939*4882a593Smuzhiyun #define WM2200_AIF1TX6MIX_SRC4_MASK 0x007F /* AIF1TX6MIX_SRC4 - [6:0] */ 1940*4882a593Smuzhiyun #define WM2200_AIF1TX6MIX_SRC4_SHIFT 0 /* AIF1TX6MIX_SRC4 - [6:0] */ 1941*4882a593Smuzhiyun #define WM2200_AIF1TX6MIX_SRC4_WIDTH 7 /* AIF1TX6MIX_SRC4 - [6:0] */ 1942*4882a593Smuzhiyun 1943*4882a593Smuzhiyun /* 1944*4882a593Smuzhiyun * R1615 (0x64F) - AIF1TX6MIX Input 4 Volume 1945*4882a593Smuzhiyun */ 1946*4882a593Smuzhiyun #define WM2200_AIF1TX6MIX_VOL4_MASK 0x00FE /* AIF1TX6MIX_VOL4 - [7:1] */ 1947*4882a593Smuzhiyun #define WM2200_AIF1TX6MIX_VOL4_SHIFT 1 /* AIF1TX6MIX_VOL4 - [7:1] */ 1948*4882a593Smuzhiyun #define WM2200_AIF1TX6MIX_VOL4_WIDTH 7 /* AIF1TX6MIX_VOL4 - [7:1] */ 1949*4882a593Smuzhiyun 1950*4882a593Smuzhiyun /* 1951*4882a593Smuzhiyun * R1616 (0x650) - EQLMIX Input 1 Source 1952*4882a593Smuzhiyun */ 1953*4882a593Smuzhiyun #define WM2200_EQLMIX_SRC1_MASK 0x007F /* EQLMIX_SRC1 - [6:0] */ 1954*4882a593Smuzhiyun #define WM2200_EQLMIX_SRC1_SHIFT 0 /* EQLMIX_SRC1 - [6:0] */ 1955*4882a593Smuzhiyun #define WM2200_EQLMIX_SRC1_WIDTH 7 /* EQLMIX_SRC1 - [6:0] */ 1956*4882a593Smuzhiyun 1957*4882a593Smuzhiyun /* 1958*4882a593Smuzhiyun * R1617 (0x651) - EQLMIX Input 1 Volume 1959*4882a593Smuzhiyun */ 1960*4882a593Smuzhiyun #define WM2200_EQLMIX_VOL1_MASK 0x00FE /* EQLMIX_VOL1 - [7:1] */ 1961*4882a593Smuzhiyun #define WM2200_EQLMIX_VOL1_SHIFT 1 /* EQLMIX_VOL1 - [7:1] */ 1962*4882a593Smuzhiyun #define WM2200_EQLMIX_VOL1_WIDTH 7 /* EQLMIX_VOL1 - [7:1] */ 1963*4882a593Smuzhiyun 1964*4882a593Smuzhiyun /* 1965*4882a593Smuzhiyun * R1618 (0x652) - EQLMIX Input 2 Source 1966*4882a593Smuzhiyun */ 1967*4882a593Smuzhiyun #define WM2200_EQLMIX_SRC2_MASK 0x007F /* EQLMIX_SRC2 - [6:0] */ 1968*4882a593Smuzhiyun #define WM2200_EQLMIX_SRC2_SHIFT 0 /* EQLMIX_SRC2 - [6:0] */ 1969*4882a593Smuzhiyun #define WM2200_EQLMIX_SRC2_WIDTH 7 /* EQLMIX_SRC2 - [6:0] */ 1970*4882a593Smuzhiyun 1971*4882a593Smuzhiyun /* 1972*4882a593Smuzhiyun * R1619 (0x653) - EQLMIX Input 2 Volume 1973*4882a593Smuzhiyun */ 1974*4882a593Smuzhiyun #define WM2200_EQLMIX_VOL2_MASK 0x00FE /* EQLMIX_VOL2 - [7:1] */ 1975*4882a593Smuzhiyun #define WM2200_EQLMIX_VOL2_SHIFT 1 /* EQLMIX_VOL2 - [7:1] */ 1976*4882a593Smuzhiyun #define WM2200_EQLMIX_VOL2_WIDTH 7 /* EQLMIX_VOL2 - [7:1] */ 1977*4882a593Smuzhiyun 1978*4882a593Smuzhiyun /* 1979*4882a593Smuzhiyun * R1620 (0x654) - EQLMIX Input 3 Source 1980*4882a593Smuzhiyun */ 1981*4882a593Smuzhiyun #define WM2200_EQLMIX_SRC3_MASK 0x007F /* EQLMIX_SRC3 - [6:0] */ 1982*4882a593Smuzhiyun #define WM2200_EQLMIX_SRC3_SHIFT 0 /* EQLMIX_SRC3 - [6:0] */ 1983*4882a593Smuzhiyun #define WM2200_EQLMIX_SRC3_WIDTH 7 /* EQLMIX_SRC3 - [6:0] */ 1984*4882a593Smuzhiyun 1985*4882a593Smuzhiyun /* 1986*4882a593Smuzhiyun * R1621 (0x655) - EQLMIX Input 3 Volume 1987*4882a593Smuzhiyun */ 1988*4882a593Smuzhiyun #define WM2200_EQLMIX_VOL3_MASK 0x00FE /* EQLMIX_VOL3 - [7:1] */ 1989*4882a593Smuzhiyun #define WM2200_EQLMIX_VOL3_SHIFT 1 /* EQLMIX_VOL3 - [7:1] */ 1990*4882a593Smuzhiyun #define WM2200_EQLMIX_VOL3_WIDTH 7 /* EQLMIX_VOL3 - [7:1] */ 1991*4882a593Smuzhiyun 1992*4882a593Smuzhiyun /* 1993*4882a593Smuzhiyun * R1622 (0x656) - EQLMIX Input 4 Source 1994*4882a593Smuzhiyun */ 1995*4882a593Smuzhiyun #define WM2200_EQLMIX_SRC4_MASK 0x007F /* EQLMIX_SRC4 - [6:0] */ 1996*4882a593Smuzhiyun #define WM2200_EQLMIX_SRC4_SHIFT 0 /* EQLMIX_SRC4 - [6:0] */ 1997*4882a593Smuzhiyun #define WM2200_EQLMIX_SRC4_WIDTH 7 /* EQLMIX_SRC4 - [6:0] */ 1998*4882a593Smuzhiyun 1999*4882a593Smuzhiyun /* 2000*4882a593Smuzhiyun * R1623 (0x657) - EQLMIX Input 4 Volume 2001*4882a593Smuzhiyun */ 2002*4882a593Smuzhiyun #define WM2200_EQLMIX_VOL4_MASK 0x00FE /* EQLMIX_VOL4 - [7:1] */ 2003*4882a593Smuzhiyun #define WM2200_EQLMIX_VOL4_SHIFT 1 /* EQLMIX_VOL4 - [7:1] */ 2004*4882a593Smuzhiyun #define WM2200_EQLMIX_VOL4_WIDTH 7 /* EQLMIX_VOL4 - [7:1] */ 2005*4882a593Smuzhiyun 2006*4882a593Smuzhiyun /* 2007*4882a593Smuzhiyun * R1624 (0x658) - EQRMIX Input 1 Source 2008*4882a593Smuzhiyun */ 2009*4882a593Smuzhiyun #define WM2200_EQRMIX_SRC1_MASK 0x007F /* EQRMIX_SRC1 - [6:0] */ 2010*4882a593Smuzhiyun #define WM2200_EQRMIX_SRC1_SHIFT 0 /* EQRMIX_SRC1 - [6:0] */ 2011*4882a593Smuzhiyun #define WM2200_EQRMIX_SRC1_WIDTH 7 /* EQRMIX_SRC1 - [6:0] */ 2012*4882a593Smuzhiyun 2013*4882a593Smuzhiyun /* 2014*4882a593Smuzhiyun * R1625 (0x659) - EQRMIX Input 1 Volume 2015*4882a593Smuzhiyun */ 2016*4882a593Smuzhiyun #define WM2200_EQRMIX_VOL1_MASK 0x00FE /* EQRMIX_VOL1 - [7:1] */ 2017*4882a593Smuzhiyun #define WM2200_EQRMIX_VOL1_SHIFT 1 /* EQRMIX_VOL1 - [7:1] */ 2018*4882a593Smuzhiyun #define WM2200_EQRMIX_VOL1_WIDTH 7 /* EQRMIX_VOL1 - [7:1] */ 2019*4882a593Smuzhiyun 2020*4882a593Smuzhiyun /* 2021*4882a593Smuzhiyun * R1626 (0x65A) - EQRMIX Input 2 Source 2022*4882a593Smuzhiyun */ 2023*4882a593Smuzhiyun #define WM2200_EQRMIX_SRC2_MASK 0x007F /* EQRMIX_SRC2 - [6:0] */ 2024*4882a593Smuzhiyun #define WM2200_EQRMIX_SRC2_SHIFT 0 /* EQRMIX_SRC2 - [6:0] */ 2025*4882a593Smuzhiyun #define WM2200_EQRMIX_SRC2_WIDTH 7 /* EQRMIX_SRC2 - [6:0] */ 2026*4882a593Smuzhiyun 2027*4882a593Smuzhiyun /* 2028*4882a593Smuzhiyun * R1627 (0x65B) - EQRMIX Input 2 Volume 2029*4882a593Smuzhiyun */ 2030*4882a593Smuzhiyun #define WM2200_EQRMIX_VOL2_MASK 0x00FE /* EQRMIX_VOL2 - [7:1] */ 2031*4882a593Smuzhiyun #define WM2200_EQRMIX_VOL2_SHIFT 1 /* EQRMIX_VOL2 - [7:1] */ 2032*4882a593Smuzhiyun #define WM2200_EQRMIX_VOL2_WIDTH 7 /* EQRMIX_VOL2 - [7:1] */ 2033*4882a593Smuzhiyun 2034*4882a593Smuzhiyun /* 2035*4882a593Smuzhiyun * R1628 (0x65C) - EQRMIX Input 3 Source 2036*4882a593Smuzhiyun */ 2037*4882a593Smuzhiyun #define WM2200_EQRMIX_SRC3_MASK 0x007F /* EQRMIX_SRC3 - [6:0] */ 2038*4882a593Smuzhiyun #define WM2200_EQRMIX_SRC3_SHIFT 0 /* EQRMIX_SRC3 - [6:0] */ 2039*4882a593Smuzhiyun #define WM2200_EQRMIX_SRC3_WIDTH 7 /* EQRMIX_SRC3 - [6:0] */ 2040*4882a593Smuzhiyun 2041*4882a593Smuzhiyun /* 2042*4882a593Smuzhiyun * R1629 (0x65D) - EQRMIX Input 3 Volume 2043*4882a593Smuzhiyun */ 2044*4882a593Smuzhiyun #define WM2200_EQRMIX_VOL3_MASK 0x00FE /* EQRMIX_VOL3 - [7:1] */ 2045*4882a593Smuzhiyun #define WM2200_EQRMIX_VOL3_SHIFT 1 /* EQRMIX_VOL3 - [7:1] */ 2046*4882a593Smuzhiyun #define WM2200_EQRMIX_VOL3_WIDTH 7 /* EQRMIX_VOL3 - [7:1] */ 2047*4882a593Smuzhiyun 2048*4882a593Smuzhiyun /* 2049*4882a593Smuzhiyun * R1630 (0x65E) - EQRMIX Input 4 Source 2050*4882a593Smuzhiyun */ 2051*4882a593Smuzhiyun #define WM2200_EQRMIX_SRC4_MASK 0x007F /* EQRMIX_SRC4 - [6:0] */ 2052*4882a593Smuzhiyun #define WM2200_EQRMIX_SRC4_SHIFT 0 /* EQRMIX_SRC4 - [6:0] */ 2053*4882a593Smuzhiyun #define WM2200_EQRMIX_SRC4_WIDTH 7 /* EQRMIX_SRC4 - [6:0] */ 2054*4882a593Smuzhiyun 2055*4882a593Smuzhiyun /* 2056*4882a593Smuzhiyun * R1631 (0x65F) - EQRMIX Input 4 Volume 2057*4882a593Smuzhiyun */ 2058*4882a593Smuzhiyun #define WM2200_EQRMIX_VOL4_MASK 0x00FE /* EQRMIX_VOL4 - [7:1] */ 2059*4882a593Smuzhiyun #define WM2200_EQRMIX_VOL4_SHIFT 1 /* EQRMIX_VOL4 - [7:1] */ 2060*4882a593Smuzhiyun #define WM2200_EQRMIX_VOL4_WIDTH 7 /* EQRMIX_VOL4 - [7:1] */ 2061*4882a593Smuzhiyun 2062*4882a593Smuzhiyun /* 2063*4882a593Smuzhiyun * R1632 (0x660) - LHPF1MIX Input 1 Source 2064*4882a593Smuzhiyun */ 2065*4882a593Smuzhiyun #define WM2200_LHPF1MIX_SRC1_MASK 0x007F /* LHPF1MIX_SRC1 - [6:0] */ 2066*4882a593Smuzhiyun #define WM2200_LHPF1MIX_SRC1_SHIFT 0 /* LHPF1MIX_SRC1 - [6:0] */ 2067*4882a593Smuzhiyun #define WM2200_LHPF1MIX_SRC1_WIDTH 7 /* LHPF1MIX_SRC1 - [6:0] */ 2068*4882a593Smuzhiyun 2069*4882a593Smuzhiyun /* 2070*4882a593Smuzhiyun * R1633 (0x661) - LHPF1MIX Input 1 Volume 2071*4882a593Smuzhiyun */ 2072*4882a593Smuzhiyun #define WM2200_LHPF1MIX_VOL1_MASK 0x00FE /* LHPF1MIX_VOL1 - [7:1] */ 2073*4882a593Smuzhiyun #define WM2200_LHPF1MIX_VOL1_SHIFT 1 /* LHPF1MIX_VOL1 - [7:1] */ 2074*4882a593Smuzhiyun #define WM2200_LHPF1MIX_VOL1_WIDTH 7 /* LHPF1MIX_VOL1 - [7:1] */ 2075*4882a593Smuzhiyun 2076*4882a593Smuzhiyun /* 2077*4882a593Smuzhiyun * R1634 (0x662) - LHPF1MIX Input 2 Source 2078*4882a593Smuzhiyun */ 2079*4882a593Smuzhiyun #define WM2200_LHPF1MIX_SRC2_MASK 0x007F /* LHPF1MIX_SRC2 - [6:0] */ 2080*4882a593Smuzhiyun #define WM2200_LHPF1MIX_SRC2_SHIFT 0 /* LHPF1MIX_SRC2 - [6:0] */ 2081*4882a593Smuzhiyun #define WM2200_LHPF1MIX_SRC2_WIDTH 7 /* LHPF1MIX_SRC2 - [6:0] */ 2082*4882a593Smuzhiyun 2083*4882a593Smuzhiyun /* 2084*4882a593Smuzhiyun * R1635 (0x663) - LHPF1MIX Input 2 Volume 2085*4882a593Smuzhiyun */ 2086*4882a593Smuzhiyun #define WM2200_LHPF1MIX_VOL2_MASK 0x00FE /* LHPF1MIX_VOL2 - [7:1] */ 2087*4882a593Smuzhiyun #define WM2200_LHPF1MIX_VOL2_SHIFT 1 /* LHPF1MIX_VOL2 - [7:1] */ 2088*4882a593Smuzhiyun #define WM2200_LHPF1MIX_VOL2_WIDTH 7 /* LHPF1MIX_VOL2 - [7:1] */ 2089*4882a593Smuzhiyun 2090*4882a593Smuzhiyun /* 2091*4882a593Smuzhiyun * R1636 (0x664) - LHPF1MIX Input 3 Source 2092*4882a593Smuzhiyun */ 2093*4882a593Smuzhiyun #define WM2200_LHPF1MIX_SRC3_MASK 0x007F /* LHPF1MIX_SRC3 - [6:0] */ 2094*4882a593Smuzhiyun #define WM2200_LHPF1MIX_SRC3_SHIFT 0 /* LHPF1MIX_SRC3 - [6:0] */ 2095*4882a593Smuzhiyun #define WM2200_LHPF1MIX_SRC3_WIDTH 7 /* LHPF1MIX_SRC3 - [6:0] */ 2096*4882a593Smuzhiyun 2097*4882a593Smuzhiyun /* 2098*4882a593Smuzhiyun * R1637 (0x665) - LHPF1MIX Input 3 Volume 2099*4882a593Smuzhiyun */ 2100*4882a593Smuzhiyun #define WM2200_LHPF1MIX_VOL3_MASK 0x00FE /* LHPF1MIX_VOL3 - [7:1] */ 2101*4882a593Smuzhiyun #define WM2200_LHPF1MIX_VOL3_SHIFT 1 /* LHPF1MIX_VOL3 - [7:1] */ 2102*4882a593Smuzhiyun #define WM2200_LHPF1MIX_VOL3_WIDTH 7 /* LHPF1MIX_VOL3 - [7:1] */ 2103*4882a593Smuzhiyun 2104*4882a593Smuzhiyun /* 2105*4882a593Smuzhiyun * R1638 (0x666) - LHPF1MIX Input 4 Source 2106*4882a593Smuzhiyun */ 2107*4882a593Smuzhiyun #define WM2200_LHPF1MIX_SRC4_MASK 0x007F /* LHPF1MIX_SRC4 - [6:0] */ 2108*4882a593Smuzhiyun #define WM2200_LHPF1MIX_SRC4_SHIFT 0 /* LHPF1MIX_SRC4 - [6:0] */ 2109*4882a593Smuzhiyun #define WM2200_LHPF1MIX_SRC4_WIDTH 7 /* LHPF1MIX_SRC4 - [6:0] */ 2110*4882a593Smuzhiyun 2111*4882a593Smuzhiyun /* 2112*4882a593Smuzhiyun * R1639 (0x667) - LHPF1MIX Input 4 Volume 2113*4882a593Smuzhiyun */ 2114*4882a593Smuzhiyun #define WM2200_LHPF1MIX_VOL4_MASK 0x00FE /* LHPF1MIX_VOL4 - [7:1] */ 2115*4882a593Smuzhiyun #define WM2200_LHPF1MIX_VOL4_SHIFT 1 /* LHPF1MIX_VOL4 - [7:1] */ 2116*4882a593Smuzhiyun #define WM2200_LHPF1MIX_VOL4_WIDTH 7 /* LHPF1MIX_VOL4 - [7:1] */ 2117*4882a593Smuzhiyun 2118*4882a593Smuzhiyun /* 2119*4882a593Smuzhiyun * R1640 (0x668) - LHPF2MIX Input 1 Source 2120*4882a593Smuzhiyun */ 2121*4882a593Smuzhiyun #define WM2200_LHPF2MIX_SRC1_MASK 0x007F /* LHPF2MIX_SRC1 - [6:0] */ 2122*4882a593Smuzhiyun #define WM2200_LHPF2MIX_SRC1_SHIFT 0 /* LHPF2MIX_SRC1 - [6:0] */ 2123*4882a593Smuzhiyun #define WM2200_LHPF2MIX_SRC1_WIDTH 7 /* LHPF2MIX_SRC1 - [6:0] */ 2124*4882a593Smuzhiyun 2125*4882a593Smuzhiyun /* 2126*4882a593Smuzhiyun * R1641 (0x669) - LHPF2MIX Input 1 Volume 2127*4882a593Smuzhiyun */ 2128*4882a593Smuzhiyun #define WM2200_LHPF2MIX_VOL1_MASK 0x00FE /* LHPF2MIX_VOL1 - [7:1] */ 2129*4882a593Smuzhiyun #define WM2200_LHPF2MIX_VOL1_SHIFT 1 /* LHPF2MIX_VOL1 - [7:1] */ 2130*4882a593Smuzhiyun #define WM2200_LHPF2MIX_VOL1_WIDTH 7 /* LHPF2MIX_VOL1 - [7:1] */ 2131*4882a593Smuzhiyun 2132*4882a593Smuzhiyun /* 2133*4882a593Smuzhiyun * R1642 (0x66A) - LHPF2MIX Input 2 Source 2134*4882a593Smuzhiyun */ 2135*4882a593Smuzhiyun #define WM2200_LHPF2MIX_SRC2_MASK 0x007F /* LHPF2MIX_SRC2 - [6:0] */ 2136*4882a593Smuzhiyun #define WM2200_LHPF2MIX_SRC2_SHIFT 0 /* LHPF2MIX_SRC2 - [6:0] */ 2137*4882a593Smuzhiyun #define WM2200_LHPF2MIX_SRC2_WIDTH 7 /* LHPF2MIX_SRC2 - [6:0] */ 2138*4882a593Smuzhiyun 2139*4882a593Smuzhiyun /* 2140*4882a593Smuzhiyun * R1643 (0x66B) - LHPF2MIX Input 2 Volume 2141*4882a593Smuzhiyun */ 2142*4882a593Smuzhiyun #define WM2200_LHPF2MIX_VOL2_MASK 0x00FE /* LHPF2MIX_VOL2 - [7:1] */ 2143*4882a593Smuzhiyun #define WM2200_LHPF2MIX_VOL2_SHIFT 1 /* LHPF2MIX_VOL2 - [7:1] */ 2144*4882a593Smuzhiyun #define WM2200_LHPF2MIX_VOL2_WIDTH 7 /* LHPF2MIX_VOL2 - [7:1] */ 2145*4882a593Smuzhiyun 2146*4882a593Smuzhiyun /* 2147*4882a593Smuzhiyun * R1644 (0x66C) - LHPF2MIX Input 3 Source 2148*4882a593Smuzhiyun */ 2149*4882a593Smuzhiyun #define WM2200_LHPF2MIX_SRC3_MASK 0x007F /* LHPF2MIX_SRC3 - [6:0] */ 2150*4882a593Smuzhiyun #define WM2200_LHPF2MIX_SRC3_SHIFT 0 /* LHPF2MIX_SRC3 - [6:0] */ 2151*4882a593Smuzhiyun #define WM2200_LHPF2MIX_SRC3_WIDTH 7 /* LHPF2MIX_SRC3 - [6:0] */ 2152*4882a593Smuzhiyun 2153*4882a593Smuzhiyun /* 2154*4882a593Smuzhiyun * R1645 (0x66D) - LHPF2MIX Input 3 Volume 2155*4882a593Smuzhiyun */ 2156*4882a593Smuzhiyun #define WM2200_LHPF2MIX_VOL3_MASK 0x00FE /* LHPF2MIX_VOL3 - [7:1] */ 2157*4882a593Smuzhiyun #define WM2200_LHPF2MIX_VOL3_SHIFT 1 /* LHPF2MIX_VOL3 - [7:1] */ 2158*4882a593Smuzhiyun #define WM2200_LHPF2MIX_VOL3_WIDTH 7 /* LHPF2MIX_VOL3 - [7:1] */ 2159*4882a593Smuzhiyun 2160*4882a593Smuzhiyun /* 2161*4882a593Smuzhiyun * R1646 (0x66E) - LHPF2MIX Input 4 Source 2162*4882a593Smuzhiyun */ 2163*4882a593Smuzhiyun #define WM2200_LHPF2MIX_SRC4_MASK 0x007F /* LHPF2MIX_SRC4 - [6:0] */ 2164*4882a593Smuzhiyun #define WM2200_LHPF2MIX_SRC4_SHIFT 0 /* LHPF2MIX_SRC4 - [6:0] */ 2165*4882a593Smuzhiyun #define WM2200_LHPF2MIX_SRC4_WIDTH 7 /* LHPF2MIX_SRC4 - [6:0] */ 2166*4882a593Smuzhiyun 2167*4882a593Smuzhiyun /* 2168*4882a593Smuzhiyun * R1647 (0x66F) - LHPF2MIX Input 4 Volume 2169*4882a593Smuzhiyun */ 2170*4882a593Smuzhiyun #define WM2200_LHPF2MIX_VOL4_MASK 0x00FE /* LHPF2MIX_VOL4 - [7:1] */ 2171*4882a593Smuzhiyun #define WM2200_LHPF2MIX_VOL4_SHIFT 1 /* LHPF2MIX_VOL4 - [7:1] */ 2172*4882a593Smuzhiyun #define WM2200_LHPF2MIX_VOL4_WIDTH 7 /* LHPF2MIX_VOL4 - [7:1] */ 2173*4882a593Smuzhiyun 2174*4882a593Smuzhiyun /* 2175*4882a593Smuzhiyun * R1648 (0x670) - DSP1LMIX Input 1 Source 2176*4882a593Smuzhiyun */ 2177*4882a593Smuzhiyun #define WM2200_DSP1LMIX_SRC1_MASK 0x007F /* DSP1LMIX_SRC1 - [6:0] */ 2178*4882a593Smuzhiyun #define WM2200_DSP1LMIX_SRC1_SHIFT 0 /* DSP1LMIX_SRC1 - [6:0] */ 2179*4882a593Smuzhiyun #define WM2200_DSP1LMIX_SRC1_WIDTH 7 /* DSP1LMIX_SRC1 - [6:0] */ 2180*4882a593Smuzhiyun 2181*4882a593Smuzhiyun /* 2182*4882a593Smuzhiyun * R1649 (0x671) - DSP1LMIX Input 1 Volume 2183*4882a593Smuzhiyun */ 2184*4882a593Smuzhiyun #define WM2200_DSP1LMIX_VOL1_MASK 0x00FE /* DSP1LMIX_VOL1 - [7:1] */ 2185*4882a593Smuzhiyun #define WM2200_DSP1LMIX_VOL1_SHIFT 1 /* DSP1LMIX_VOL1 - [7:1] */ 2186*4882a593Smuzhiyun #define WM2200_DSP1LMIX_VOL1_WIDTH 7 /* DSP1LMIX_VOL1 - [7:1] */ 2187*4882a593Smuzhiyun 2188*4882a593Smuzhiyun /* 2189*4882a593Smuzhiyun * R1650 (0x672) - DSP1LMIX Input 2 Source 2190*4882a593Smuzhiyun */ 2191*4882a593Smuzhiyun #define WM2200_DSP1LMIX_SRC2_MASK 0x007F /* DSP1LMIX_SRC2 - [6:0] */ 2192*4882a593Smuzhiyun #define WM2200_DSP1LMIX_SRC2_SHIFT 0 /* DSP1LMIX_SRC2 - [6:0] */ 2193*4882a593Smuzhiyun #define WM2200_DSP1LMIX_SRC2_WIDTH 7 /* DSP1LMIX_SRC2 - [6:0] */ 2194*4882a593Smuzhiyun 2195*4882a593Smuzhiyun /* 2196*4882a593Smuzhiyun * R1651 (0x673) - DSP1LMIX Input 2 Volume 2197*4882a593Smuzhiyun */ 2198*4882a593Smuzhiyun #define WM2200_DSP1LMIX_VOL2_MASK 0x00FE /* DSP1LMIX_VOL2 - [7:1] */ 2199*4882a593Smuzhiyun #define WM2200_DSP1LMIX_VOL2_SHIFT 1 /* DSP1LMIX_VOL2 - [7:1] */ 2200*4882a593Smuzhiyun #define WM2200_DSP1LMIX_VOL2_WIDTH 7 /* DSP1LMIX_VOL2 - [7:1] */ 2201*4882a593Smuzhiyun 2202*4882a593Smuzhiyun /* 2203*4882a593Smuzhiyun * R1652 (0x674) - DSP1LMIX Input 3 Source 2204*4882a593Smuzhiyun */ 2205*4882a593Smuzhiyun #define WM2200_DSP1LMIX_SRC3_MASK 0x007F /* DSP1LMIX_SRC3 - [6:0] */ 2206*4882a593Smuzhiyun #define WM2200_DSP1LMIX_SRC3_SHIFT 0 /* DSP1LMIX_SRC3 - [6:0] */ 2207*4882a593Smuzhiyun #define WM2200_DSP1LMIX_SRC3_WIDTH 7 /* DSP1LMIX_SRC3 - [6:0] */ 2208*4882a593Smuzhiyun 2209*4882a593Smuzhiyun /* 2210*4882a593Smuzhiyun * R1653 (0x675) - DSP1LMIX Input 3 Volume 2211*4882a593Smuzhiyun */ 2212*4882a593Smuzhiyun #define WM2200_DSP1LMIX_VOL3_MASK 0x00FE /* DSP1LMIX_VOL3 - [7:1] */ 2213*4882a593Smuzhiyun #define WM2200_DSP1LMIX_VOL3_SHIFT 1 /* DSP1LMIX_VOL3 - [7:1] */ 2214*4882a593Smuzhiyun #define WM2200_DSP1LMIX_VOL3_WIDTH 7 /* DSP1LMIX_VOL3 - [7:1] */ 2215*4882a593Smuzhiyun 2216*4882a593Smuzhiyun /* 2217*4882a593Smuzhiyun * R1654 (0x676) - DSP1LMIX Input 4 Source 2218*4882a593Smuzhiyun */ 2219*4882a593Smuzhiyun #define WM2200_DSP1LMIX_SRC4_MASK 0x007F /* DSP1LMIX_SRC4 - [6:0] */ 2220*4882a593Smuzhiyun #define WM2200_DSP1LMIX_SRC4_SHIFT 0 /* DSP1LMIX_SRC4 - [6:0] */ 2221*4882a593Smuzhiyun #define WM2200_DSP1LMIX_SRC4_WIDTH 7 /* DSP1LMIX_SRC4 - [6:0] */ 2222*4882a593Smuzhiyun 2223*4882a593Smuzhiyun /* 2224*4882a593Smuzhiyun * R1655 (0x677) - DSP1LMIX Input 4 Volume 2225*4882a593Smuzhiyun */ 2226*4882a593Smuzhiyun #define WM2200_DSP1LMIX_VOL4_MASK 0x00FE /* DSP1LMIX_VOL4 - [7:1] */ 2227*4882a593Smuzhiyun #define WM2200_DSP1LMIX_VOL4_SHIFT 1 /* DSP1LMIX_VOL4 - [7:1] */ 2228*4882a593Smuzhiyun #define WM2200_DSP1LMIX_VOL4_WIDTH 7 /* DSP1LMIX_VOL4 - [7:1] */ 2229*4882a593Smuzhiyun 2230*4882a593Smuzhiyun /* 2231*4882a593Smuzhiyun * R1656 (0x678) - DSP1RMIX Input 1 Source 2232*4882a593Smuzhiyun */ 2233*4882a593Smuzhiyun #define WM2200_DSP1RMIX_SRC1_MASK 0x007F /* DSP1RMIX_SRC1 - [6:0] */ 2234*4882a593Smuzhiyun #define WM2200_DSP1RMIX_SRC1_SHIFT 0 /* DSP1RMIX_SRC1 - [6:0] */ 2235*4882a593Smuzhiyun #define WM2200_DSP1RMIX_SRC1_WIDTH 7 /* DSP1RMIX_SRC1 - [6:0] */ 2236*4882a593Smuzhiyun 2237*4882a593Smuzhiyun /* 2238*4882a593Smuzhiyun * R1657 (0x679) - DSP1RMIX Input 1 Volume 2239*4882a593Smuzhiyun */ 2240*4882a593Smuzhiyun #define WM2200_DSP1RMIX_VOL1_MASK 0x00FE /* DSP1RMIX_VOL1 - [7:1] */ 2241*4882a593Smuzhiyun #define WM2200_DSP1RMIX_VOL1_SHIFT 1 /* DSP1RMIX_VOL1 - [7:1] */ 2242*4882a593Smuzhiyun #define WM2200_DSP1RMIX_VOL1_WIDTH 7 /* DSP1RMIX_VOL1 - [7:1] */ 2243*4882a593Smuzhiyun 2244*4882a593Smuzhiyun /* 2245*4882a593Smuzhiyun * R1658 (0x67A) - DSP1RMIX Input 2 Source 2246*4882a593Smuzhiyun */ 2247*4882a593Smuzhiyun #define WM2200_DSP1RMIX_SRC2_MASK 0x007F /* DSP1RMIX_SRC2 - [6:0] */ 2248*4882a593Smuzhiyun #define WM2200_DSP1RMIX_SRC2_SHIFT 0 /* DSP1RMIX_SRC2 - [6:0] */ 2249*4882a593Smuzhiyun #define WM2200_DSP1RMIX_SRC2_WIDTH 7 /* DSP1RMIX_SRC2 - [6:0] */ 2250*4882a593Smuzhiyun 2251*4882a593Smuzhiyun /* 2252*4882a593Smuzhiyun * R1659 (0x67B) - DSP1RMIX Input 2 Volume 2253*4882a593Smuzhiyun */ 2254*4882a593Smuzhiyun #define WM2200_DSP1RMIX_VOL2_MASK 0x00FE /* DSP1RMIX_VOL2 - [7:1] */ 2255*4882a593Smuzhiyun #define WM2200_DSP1RMIX_VOL2_SHIFT 1 /* DSP1RMIX_VOL2 - [7:1] */ 2256*4882a593Smuzhiyun #define WM2200_DSP1RMIX_VOL2_WIDTH 7 /* DSP1RMIX_VOL2 - [7:1] */ 2257*4882a593Smuzhiyun 2258*4882a593Smuzhiyun /* 2259*4882a593Smuzhiyun * R1660 (0x67C) - DSP1RMIX Input 3 Source 2260*4882a593Smuzhiyun */ 2261*4882a593Smuzhiyun #define WM2200_DSP1RMIX_SRC3_MASK 0x007F /* DSP1RMIX_SRC3 - [6:0] */ 2262*4882a593Smuzhiyun #define WM2200_DSP1RMIX_SRC3_SHIFT 0 /* DSP1RMIX_SRC3 - [6:0] */ 2263*4882a593Smuzhiyun #define WM2200_DSP1RMIX_SRC3_WIDTH 7 /* DSP1RMIX_SRC3 - [6:0] */ 2264*4882a593Smuzhiyun 2265*4882a593Smuzhiyun /* 2266*4882a593Smuzhiyun * R1661 (0x67D) - DSP1RMIX Input 3 Volume 2267*4882a593Smuzhiyun */ 2268*4882a593Smuzhiyun #define WM2200_DSP1RMIX_VOL3_MASK 0x00FE /* DSP1RMIX_VOL3 - [7:1] */ 2269*4882a593Smuzhiyun #define WM2200_DSP1RMIX_VOL3_SHIFT 1 /* DSP1RMIX_VOL3 - [7:1] */ 2270*4882a593Smuzhiyun #define WM2200_DSP1RMIX_VOL3_WIDTH 7 /* DSP1RMIX_VOL3 - [7:1] */ 2271*4882a593Smuzhiyun 2272*4882a593Smuzhiyun /* 2273*4882a593Smuzhiyun * R1662 (0x67E) - DSP1RMIX Input 4 Source 2274*4882a593Smuzhiyun */ 2275*4882a593Smuzhiyun #define WM2200_DSP1RMIX_SRC4_MASK 0x007F /* DSP1RMIX_SRC4 - [6:0] */ 2276*4882a593Smuzhiyun #define WM2200_DSP1RMIX_SRC4_SHIFT 0 /* DSP1RMIX_SRC4 - [6:0] */ 2277*4882a593Smuzhiyun #define WM2200_DSP1RMIX_SRC4_WIDTH 7 /* DSP1RMIX_SRC4 - [6:0] */ 2278*4882a593Smuzhiyun 2279*4882a593Smuzhiyun /* 2280*4882a593Smuzhiyun * R1663 (0x67F) - DSP1RMIX Input 4 Volume 2281*4882a593Smuzhiyun */ 2282*4882a593Smuzhiyun #define WM2200_DSP1RMIX_VOL4_MASK 0x00FE /* DSP1RMIX_VOL4 - [7:1] */ 2283*4882a593Smuzhiyun #define WM2200_DSP1RMIX_VOL4_SHIFT 1 /* DSP1RMIX_VOL4 - [7:1] */ 2284*4882a593Smuzhiyun #define WM2200_DSP1RMIX_VOL4_WIDTH 7 /* DSP1RMIX_VOL4 - [7:1] */ 2285*4882a593Smuzhiyun 2286*4882a593Smuzhiyun /* 2287*4882a593Smuzhiyun * R1664 (0x680) - DSP1AUX1MIX Input 1 Source 2288*4882a593Smuzhiyun */ 2289*4882a593Smuzhiyun #define WM2200_DSP1AUX1MIX_SRC1_MASK 0x007F /* DSP1AUX1MIX_SRC1 - [6:0] */ 2290*4882a593Smuzhiyun #define WM2200_DSP1AUX1MIX_SRC1_SHIFT 0 /* DSP1AUX1MIX_SRC1 - [6:0] */ 2291*4882a593Smuzhiyun #define WM2200_DSP1AUX1MIX_SRC1_WIDTH 7 /* DSP1AUX1MIX_SRC1 - [6:0] */ 2292*4882a593Smuzhiyun 2293*4882a593Smuzhiyun /* 2294*4882a593Smuzhiyun * R1665 (0x681) - DSP1AUX2MIX Input 1 Source 2295*4882a593Smuzhiyun */ 2296*4882a593Smuzhiyun #define WM2200_DSP1AUX2MIX_SRC1_MASK 0x007F /* DSP1AUX2MIX_SRC1 - [6:0] */ 2297*4882a593Smuzhiyun #define WM2200_DSP1AUX2MIX_SRC1_SHIFT 0 /* DSP1AUX2MIX_SRC1 - [6:0] */ 2298*4882a593Smuzhiyun #define WM2200_DSP1AUX2MIX_SRC1_WIDTH 7 /* DSP1AUX2MIX_SRC1 - [6:0] */ 2299*4882a593Smuzhiyun 2300*4882a593Smuzhiyun /* 2301*4882a593Smuzhiyun * R1666 (0x682) - DSP1AUX3MIX Input 1 Source 2302*4882a593Smuzhiyun */ 2303*4882a593Smuzhiyun #define WM2200_DSP1AUX3MIX_SRC1_MASK 0x007F /* DSP1AUX3MIX_SRC1 - [6:0] */ 2304*4882a593Smuzhiyun #define WM2200_DSP1AUX3MIX_SRC1_SHIFT 0 /* DSP1AUX3MIX_SRC1 - [6:0] */ 2305*4882a593Smuzhiyun #define WM2200_DSP1AUX3MIX_SRC1_WIDTH 7 /* DSP1AUX3MIX_SRC1 - [6:0] */ 2306*4882a593Smuzhiyun 2307*4882a593Smuzhiyun /* 2308*4882a593Smuzhiyun * R1667 (0x683) - DSP1AUX4MIX Input 1 Source 2309*4882a593Smuzhiyun */ 2310*4882a593Smuzhiyun #define WM2200_DSP1AUX4MIX_SRC1_MASK 0x007F /* DSP1AUX4MIX_SRC1 - [6:0] */ 2311*4882a593Smuzhiyun #define WM2200_DSP1AUX4MIX_SRC1_SHIFT 0 /* DSP1AUX4MIX_SRC1 - [6:0] */ 2312*4882a593Smuzhiyun #define WM2200_DSP1AUX4MIX_SRC1_WIDTH 7 /* DSP1AUX4MIX_SRC1 - [6:0] */ 2313*4882a593Smuzhiyun 2314*4882a593Smuzhiyun /* 2315*4882a593Smuzhiyun * R1668 (0x684) - DSP1AUX5MIX Input 1 Source 2316*4882a593Smuzhiyun */ 2317*4882a593Smuzhiyun #define WM2200_DSP1AUX5MIX_SRC1_MASK 0x007F /* DSP1AUX5MIX_SRC1 - [6:0] */ 2318*4882a593Smuzhiyun #define WM2200_DSP1AUX5MIX_SRC1_SHIFT 0 /* DSP1AUX5MIX_SRC1 - [6:0] */ 2319*4882a593Smuzhiyun #define WM2200_DSP1AUX5MIX_SRC1_WIDTH 7 /* DSP1AUX5MIX_SRC1 - [6:0] */ 2320*4882a593Smuzhiyun 2321*4882a593Smuzhiyun /* 2322*4882a593Smuzhiyun * R1669 (0x685) - DSP1AUX6MIX Input 1 Source 2323*4882a593Smuzhiyun */ 2324*4882a593Smuzhiyun #define WM2200_DSP1AUX6MIX_SRC1_MASK 0x007F /* DSP1AUX6MIX_SRC1 - [6:0] */ 2325*4882a593Smuzhiyun #define WM2200_DSP1AUX6MIX_SRC1_SHIFT 0 /* DSP1AUX6MIX_SRC1 - [6:0] */ 2326*4882a593Smuzhiyun #define WM2200_DSP1AUX6MIX_SRC1_WIDTH 7 /* DSP1AUX6MIX_SRC1 - [6:0] */ 2327*4882a593Smuzhiyun 2328*4882a593Smuzhiyun /* 2329*4882a593Smuzhiyun * R1670 (0x686) - DSP2LMIX Input 1 Source 2330*4882a593Smuzhiyun */ 2331*4882a593Smuzhiyun #define WM2200_DSP2LMIX_SRC1_MASK 0x007F /* DSP2LMIX_SRC1 - [6:0] */ 2332*4882a593Smuzhiyun #define WM2200_DSP2LMIX_SRC1_SHIFT 0 /* DSP2LMIX_SRC1 - [6:0] */ 2333*4882a593Smuzhiyun #define WM2200_DSP2LMIX_SRC1_WIDTH 7 /* DSP2LMIX_SRC1 - [6:0] */ 2334*4882a593Smuzhiyun 2335*4882a593Smuzhiyun /* 2336*4882a593Smuzhiyun * R1671 (0x687) - DSP2LMIX Input 1 Volume 2337*4882a593Smuzhiyun */ 2338*4882a593Smuzhiyun #define WM2200_DSP2LMIX_VOL1_MASK 0x00FE /* DSP2LMIX_VOL1 - [7:1] */ 2339*4882a593Smuzhiyun #define WM2200_DSP2LMIX_VOL1_SHIFT 1 /* DSP2LMIX_VOL1 - [7:1] */ 2340*4882a593Smuzhiyun #define WM2200_DSP2LMIX_VOL1_WIDTH 7 /* DSP2LMIX_VOL1 - [7:1] */ 2341*4882a593Smuzhiyun 2342*4882a593Smuzhiyun /* 2343*4882a593Smuzhiyun * R1672 (0x688) - DSP2LMIX Input 2 Source 2344*4882a593Smuzhiyun */ 2345*4882a593Smuzhiyun #define WM2200_DSP2LMIX_SRC2_MASK 0x007F /* DSP2LMIX_SRC2 - [6:0] */ 2346*4882a593Smuzhiyun #define WM2200_DSP2LMIX_SRC2_SHIFT 0 /* DSP2LMIX_SRC2 - [6:0] */ 2347*4882a593Smuzhiyun #define WM2200_DSP2LMIX_SRC2_WIDTH 7 /* DSP2LMIX_SRC2 - [6:0] */ 2348*4882a593Smuzhiyun 2349*4882a593Smuzhiyun /* 2350*4882a593Smuzhiyun * R1673 (0x689) - DSP2LMIX Input 2 Volume 2351*4882a593Smuzhiyun */ 2352*4882a593Smuzhiyun #define WM2200_DSP2LMIX_VOL2_MASK 0x00FE /* DSP2LMIX_VOL2 - [7:1] */ 2353*4882a593Smuzhiyun #define WM2200_DSP2LMIX_VOL2_SHIFT 1 /* DSP2LMIX_VOL2 - [7:1] */ 2354*4882a593Smuzhiyun #define WM2200_DSP2LMIX_VOL2_WIDTH 7 /* DSP2LMIX_VOL2 - [7:1] */ 2355*4882a593Smuzhiyun 2356*4882a593Smuzhiyun /* 2357*4882a593Smuzhiyun * R1674 (0x68A) - DSP2LMIX Input 3 Source 2358*4882a593Smuzhiyun */ 2359*4882a593Smuzhiyun #define WM2200_DSP2LMIX_SRC3_MASK 0x007F /* DSP2LMIX_SRC3 - [6:0] */ 2360*4882a593Smuzhiyun #define WM2200_DSP2LMIX_SRC3_SHIFT 0 /* DSP2LMIX_SRC3 - [6:0] */ 2361*4882a593Smuzhiyun #define WM2200_DSP2LMIX_SRC3_WIDTH 7 /* DSP2LMIX_SRC3 - [6:0] */ 2362*4882a593Smuzhiyun 2363*4882a593Smuzhiyun /* 2364*4882a593Smuzhiyun * R1675 (0x68B) - DSP2LMIX Input 3 Volume 2365*4882a593Smuzhiyun */ 2366*4882a593Smuzhiyun #define WM2200_DSP2LMIX_VOL3_MASK 0x00FE /* DSP2LMIX_VOL3 - [7:1] */ 2367*4882a593Smuzhiyun #define WM2200_DSP2LMIX_VOL3_SHIFT 1 /* DSP2LMIX_VOL3 - [7:1] */ 2368*4882a593Smuzhiyun #define WM2200_DSP2LMIX_VOL3_WIDTH 7 /* DSP2LMIX_VOL3 - [7:1] */ 2369*4882a593Smuzhiyun 2370*4882a593Smuzhiyun /* 2371*4882a593Smuzhiyun * R1676 (0x68C) - DSP2LMIX Input 4 Source 2372*4882a593Smuzhiyun */ 2373*4882a593Smuzhiyun #define WM2200_DSP2LMIX_SRC4_MASK 0x007F /* DSP2LMIX_SRC4 - [6:0] */ 2374*4882a593Smuzhiyun #define WM2200_DSP2LMIX_SRC4_SHIFT 0 /* DSP2LMIX_SRC4 - [6:0] */ 2375*4882a593Smuzhiyun #define WM2200_DSP2LMIX_SRC4_WIDTH 7 /* DSP2LMIX_SRC4 - [6:0] */ 2376*4882a593Smuzhiyun 2377*4882a593Smuzhiyun /* 2378*4882a593Smuzhiyun * R1677 (0x68D) - DSP2LMIX Input 4 Volume 2379*4882a593Smuzhiyun */ 2380*4882a593Smuzhiyun #define WM2200_DSP2LMIX_VOL4_MASK 0x00FE /* DSP2LMIX_VOL4 - [7:1] */ 2381*4882a593Smuzhiyun #define WM2200_DSP2LMIX_VOL4_SHIFT 1 /* DSP2LMIX_VOL4 - [7:1] */ 2382*4882a593Smuzhiyun #define WM2200_DSP2LMIX_VOL4_WIDTH 7 /* DSP2LMIX_VOL4 - [7:1] */ 2383*4882a593Smuzhiyun 2384*4882a593Smuzhiyun /* 2385*4882a593Smuzhiyun * R1678 (0x68E) - DSP2RMIX Input 1 Source 2386*4882a593Smuzhiyun */ 2387*4882a593Smuzhiyun #define WM2200_DSP2RMIX_SRC1_MASK 0x007F /* DSP2RMIX_SRC1 - [6:0] */ 2388*4882a593Smuzhiyun #define WM2200_DSP2RMIX_SRC1_SHIFT 0 /* DSP2RMIX_SRC1 - [6:0] */ 2389*4882a593Smuzhiyun #define WM2200_DSP2RMIX_SRC1_WIDTH 7 /* DSP2RMIX_SRC1 - [6:0] */ 2390*4882a593Smuzhiyun 2391*4882a593Smuzhiyun /* 2392*4882a593Smuzhiyun * R1679 (0x68F) - DSP2RMIX Input 1 Volume 2393*4882a593Smuzhiyun */ 2394*4882a593Smuzhiyun #define WM2200_DSP2RMIX_VOL1_MASK 0x00FE /* DSP2RMIX_VOL1 - [7:1] */ 2395*4882a593Smuzhiyun #define WM2200_DSP2RMIX_VOL1_SHIFT 1 /* DSP2RMIX_VOL1 - [7:1] */ 2396*4882a593Smuzhiyun #define WM2200_DSP2RMIX_VOL1_WIDTH 7 /* DSP2RMIX_VOL1 - [7:1] */ 2397*4882a593Smuzhiyun 2398*4882a593Smuzhiyun /* 2399*4882a593Smuzhiyun * R1680 (0x690) - DSP2RMIX Input 2 Source 2400*4882a593Smuzhiyun */ 2401*4882a593Smuzhiyun #define WM2200_DSP2RMIX_SRC2_MASK 0x007F /* DSP2RMIX_SRC2 - [6:0] */ 2402*4882a593Smuzhiyun #define WM2200_DSP2RMIX_SRC2_SHIFT 0 /* DSP2RMIX_SRC2 - [6:0] */ 2403*4882a593Smuzhiyun #define WM2200_DSP2RMIX_SRC2_WIDTH 7 /* DSP2RMIX_SRC2 - [6:0] */ 2404*4882a593Smuzhiyun 2405*4882a593Smuzhiyun /* 2406*4882a593Smuzhiyun * R1681 (0x691) - DSP2RMIX Input 2 Volume 2407*4882a593Smuzhiyun */ 2408*4882a593Smuzhiyun #define WM2200_DSP2RMIX_VOL2_MASK 0x00FE /* DSP2RMIX_VOL2 - [7:1] */ 2409*4882a593Smuzhiyun #define WM2200_DSP2RMIX_VOL2_SHIFT 1 /* DSP2RMIX_VOL2 - [7:1] */ 2410*4882a593Smuzhiyun #define WM2200_DSP2RMIX_VOL2_WIDTH 7 /* DSP2RMIX_VOL2 - [7:1] */ 2411*4882a593Smuzhiyun 2412*4882a593Smuzhiyun /* 2413*4882a593Smuzhiyun * R1682 (0x692) - DSP2RMIX Input 3 Source 2414*4882a593Smuzhiyun */ 2415*4882a593Smuzhiyun #define WM2200_DSP2RMIX_SRC3_MASK 0x007F /* DSP2RMIX_SRC3 - [6:0] */ 2416*4882a593Smuzhiyun #define WM2200_DSP2RMIX_SRC3_SHIFT 0 /* DSP2RMIX_SRC3 - [6:0] */ 2417*4882a593Smuzhiyun #define WM2200_DSP2RMIX_SRC3_WIDTH 7 /* DSP2RMIX_SRC3 - [6:0] */ 2418*4882a593Smuzhiyun 2419*4882a593Smuzhiyun /* 2420*4882a593Smuzhiyun * R1683 (0x693) - DSP2RMIX Input 3 Volume 2421*4882a593Smuzhiyun */ 2422*4882a593Smuzhiyun #define WM2200_DSP2RMIX_VOL3_MASK 0x00FE /* DSP2RMIX_VOL3 - [7:1] */ 2423*4882a593Smuzhiyun #define WM2200_DSP2RMIX_VOL3_SHIFT 1 /* DSP2RMIX_VOL3 - [7:1] */ 2424*4882a593Smuzhiyun #define WM2200_DSP2RMIX_VOL3_WIDTH 7 /* DSP2RMIX_VOL3 - [7:1] */ 2425*4882a593Smuzhiyun 2426*4882a593Smuzhiyun /* 2427*4882a593Smuzhiyun * R1684 (0x694) - DSP2RMIX Input 4 Source 2428*4882a593Smuzhiyun */ 2429*4882a593Smuzhiyun #define WM2200_DSP2RMIX_SRC4_MASK 0x007F /* DSP2RMIX_SRC4 - [6:0] */ 2430*4882a593Smuzhiyun #define WM2200_DSP2RMIX_SRC4_SHIFT 0 /* DSP2RMIX_SRC4 - [6:0] */ 2431*4882a593Smuzhiyun #define WM2200_DSP2RMIX_SRC4_WIDTH 7 /* DSP2RMIX_SRC4 - [6:0] */ 2432*4882a593Smuzhiyun 2433*4882a593Smuzhiyun /* 2434*4882a593Smuzhiyun * R1685 (0x695) - DSP2RMIX Input 4 Volume 2435*4882a593Smuzhiyun */ 2436*4882a593Smuzhiyun #define WM2200_DSP2RMIX_VOL4_MASK 0x00FE /* DSP2RMIX_VOL4 - [7:1] */ 2437*4882a593Smuzhiyun #define WM2200_DSP2RMIX_VOL4_SHIFT 1 /* DSP2RMIX_VOL4 - [7:1] */ 2438*4882a593Smuzhiyun #define WM2200_DSP2RMIX_VOL4_WIDTH 7 /* DSP2RMIX_VOL4 - [7:1] */ 2439*4882a593Smuzhiyun 2440*4882a593Smuzhiyun /* 2441*4882a593Smuzhiyun * R1686 (0x696) - DSP2AUX1MIX Input 1 Source 2442*4882a593Smuzhiyun */ 2443*4882a593Smuzhiyun #define WM2200_DSP2AUX1MIX_SRC1_MASK 0x007F /* DSP2AUX1MIX_SRC1 - [6:0] */ 2444*4882a593Smuzhiyun #define WM2200_DSP2AUX1MIX_SRC1_SHIFT 0 /* DSP2AUX1MIX_SRC1 - [6:0] */ 2445*4882a593Smuzhiyun #define WM2200_DSP2AUX1MIX_SRC1_WIDTH 7 /* DSP2AUX1MIX_SRC1 - [6:0] */ 2446*4882a593Smuzhiyun 2447*4882a593Smuzhiyun /* 2448*4882a593Smuzhiyun * R1687 (0x697) - DSP2AUX2MIX Input 1 Source 2449*4882a593Smuzhiyun */ 2450*4882a593Smuzhiyun #define WM2200_DSP2AUX2MIX_SRC1_MASK 0x007F /* DSP2AUX2MIX_SRC1 - [6:0] */ 2451*4882a593Smuzhiyun #define WM2200_DSP2AUX2MIX_SRC1_SHIFT 0 /* DSP2AUX2MIX_SRC1 - [6:0] */ 2452*4882a593Smuzhiyun #define WM2200_DSP2AUX2MIX_SRC1_WIDTH 7 /* DSP2AUX2MIX_SRC1 - [6:0] */ 2453*4882a593Smuzhiyun 2454*4882a593Smuzhiyun /* 2455*4882a593Smuzhiyun * R1688 (0x698) - DSP2AUX3MIX Input 1 Source 2456*4882a593Smuzhiyun */ 2457*4882a593Smuzhiyun #define WM2200_DSP2AUX3MIX_SRC1_MASK 0x007F /* DSP2AUX3MIX_SRC1 - [6:0] */ 2458*4882a593Smuzhiyun #define WM2200_DSP2AUX3MIX_SRC1_SHIFT 0 /* DSP2AUX3MIX_SRC1 - [6:0] */ 2459*4882a593Smuzhiyun #define WM2200_DSP2AUX3MIX_SRC1_WIDTH 7 /* DSP2AUX3MIX_SRC1 - [6:0] */ 2460*4882a593Smuzhiyun 2461*4882a593Smuzhiyun /* 2462*4882a593Smuzhiyun * R1689 (0x699) - DSP2AUX4MIX Input 1 Source 2463*4882a593Smuzhiyun */ 2464*4882a593Smuzhiyun #define WM2200_DSP2AUX4MIX_SRC1_MASK 0x007F /* DSP2AUX4MIX_SRC1 - [6:0] */ 2465*4882a593Smuzhiyun #define WM2200_DSP2AUX4MIX_SRC1_SHIFT 0 /* DSP2AUX4MIX_SRC1 - [6:0] */ 2466*4882a593Smuzhiyun #define WM2200_DSP2AUX4MIX_SRC1_WIDTH 7 /* DSP2AUX4MIX_SRC1 - [6:0] */ 2467*4882a593Smuzhiyun 2468*4882a593Smuzhiyun /* 2469*4882a593Smuzhiyun * R1690 (0x69A) - DSP2AUX5MIX Input 1 Source 2470*4882a593Smuzhiyun */ 2471*4882a593Smuzhiyun #define WM2200_DSP2AUX5MIX_SRC1_MASK 0x007F /* DSP2AUX5MIX_SRC1 - [6:0] */ 2472*4882a593Smuzhiyun #define WM2200_DSP2AUX5MIX_SRC1_SHIFT 0 /* DSP2AUX5MIX_SRC1 - [6:0] */ 2473*4882a593Smuzhiyun #define WM2200_DSP2AUX5MIX_SRC1_WIDTH 7 /* DSP2AUX5MIX_SRC1 - [6:0] */ 2474*4882a593Smuzhiyun 2475*4882a593Smuzhiyun /* 2476*4882a593Smuzhiyun * R1691 (0x69B) - DSP2AUX6MIX Input 1 Source 2477*4882a593Smuzhiyun */ 2478*4882a593Smuzhiyun #define WM2200_DSP2AUX6MIX_SRC1_MASK 0x007F /* DSP2AUX6MIX_SRC1 - [6:0] */ 2479*4882a593Smuzhiyun #define WM2200_DSP2AUX6MIX_SRC1_SHIFT 0 /* DSP2AUX6MIX_SRC1 - [6:0] */ 2480*4882a593Smuzhiyun #define WM2200_DSP2AUX6MIX_SRC1_WIDTH 7 /* DSP2AUX6MIX_SRC1 - [6:0] */ 2481*4882a593Smuzhiyun 2482*4882a593Smuzhiyun /* 2483*4882a593Smuzhiyun * R1792 (0x700) - GPIO CTRL 1 2484*4882a593Smuzhiyun */ 2485*4882a593Smuzhiyun #define WM2200_GP1_DIR 0x8000 /* GP1_DIR */ 2486*4882a593Smuzhiyun #define WM2200_GP1_DIR_MASK 0x8000 /* GP1_DIR */ 2487*4882a593Smuzhiyun #define WM2200_GP1_DIR_SHIFT 15 /* GP1_DIR */ 2488*4882a593Smuzhiyun #define WM2200_GP1_DIR_WIDTH 1 /* GP1_DIR */ 2489*4882a593Smuzhiyun #define WM2200_GP1_PU 0x4000 /* GP1_PU */ 2490*4882a593Smuzhiyun #define WM2200_GP1_PU_MASK 0x4000 /* GP1_PU */ 2491*4882a593Smuzhiyun #define WM2200_GP1_PU_SHIFT 14 /* GP1_PU */ 2492*4882a593Smuzhiyun #define WM2200_GP1_PU_WIDTH 1 /* GP1_PU */ 2493*4882a593Smuzhiyun #define WM2200_GP1_PD 0x2000 /* GP1_PD */ 2494*4882a593Smuzhiyun #define WM2200_GP1_PD_MASK 0x2000 /* GP1_PD */ 2495*4882a593Smuzhiyun #define WM2200_GP1_PD_SHIFT 13 /* GP1_PD */ 2496*4882a593Smuzhiyun #define WM2200_GP1_PD_WIDTH 1 /* GP1_PD */ 2497*4882a593Smuzhiyun #define WM2200_GP1_POL 0x0400 /* GP1_POL */ 2498*4882a593Smuzhiyun #define WM2200_GP1_POL_MASK 0x0400 /* GP1_POL */ 2499*4882a593Smuzhiyun #define WM2200_GP1_POL_SHIFT 10 /* GP1_POL */ 2500*4882a593Smuzhiyun #define WM2200_GP1_POL_WIDTH 1 /* GP1_POL */ 2501*4882a593Smuzhiyun #define WM2200_GP1_OP_CFG 0x0200 /* GP1_OP_CFG */ 2502*4882a593Smuzhiyun #define WM2200_GP1_OP_CFG_MASK 0x0200 /* GP1_OP_CFG */ 2503*4882a593Smuzhiyun #define WM2200_GP1_OP_CFG_SHIFT 9 /* GP1_OP_CFG */ 2504*4882a593Smuzhiyun #define WM2200_GP1_OP_CFG_WIDTH 1 /* GP1_OP_CFG */ 2505*4882a593Smuzhiyun #define WM2200_GP1_DB 0x0100 /* GP1_DB */ 2506*4882a593Smuzhiyun #define WM2200_GP1_DB_MASK 0x0100 /* GP1_DB */ 2507*4882a593Smuzhiyun #define WM2200_GP1_DB_SHIFT 8 /* GP1_DB */ 2508*4882a593Smuzhiyun #define WM2200_GP1_DB_WIDTH 1 /* GP1_DB */ 2509*4882a593Smuzhiyun #define WM2200_GP1_LVL 0x0040 /* GP1_LVL */ 2510*4882a593Smuzhiyun #define WM2200_GP1_LVL_MASK 0x0040 /* GP1_LVL */ 2511*4882a593Smuzhiyun #define WM2200_GP1_LVL_SHIFT 6 /* GP1_LVL */ 2512*4882a593Smuzhiyun #define WM2200_GP1_LVL_WIDTH 1 /* GP1_LVL */ 2513*4882a593Smuzhiyun #define WM2200_GP1_FN_MASK 0x003F /* GP1_FN - [5:0] */ 2514*4882a593Smuzhiyun #define WM2200_GP1_FN_SHIFT 0 /* GP1_FN - [5:0] */ 2515*4882a593Smuzhiyun #define WM2200_GP1_FN_WIDTH 6 /* GP1_FN - [5:0] */ 2516*4882a593Smuzhiyun 2517*4882a593Smuzhiyun /* 2518*4882a593Smuzhiyun * R1793 (0x701) - GPIO CTRL 2 2519*4882a593Smuzhiyun */ 2520*4882a593Smuzhiyun #define WM2200_GP2_DIR 0x8000 /* GP2_DIR */ 2521*4882a593Smuzhiyun #define WM2200_GP2_DIR_MASK 0x8000 /* GP2_DIR */ 2522*4882a593Smuzhiyun #define WM2200_GP2_DIR_SHIFT 15 /* GP2_DIR */ 2523*4882a593Smuzhiyun #define WM2200_GP2_DIR_WIDTH 1 /* GP2_DIR */ 2524*4882a593Smuzhiyun #define WM2200_GP2_PU 0x4000 /* GP2_PU */ 2525*4882a593Smuzhiyun #define WM2200_GP2_PU_MASK 0x4000 /* GP2_PU */ 2526*4882a593Smuzhiyun #define WM2200_GP2_PU_SHIFT 14 /* GP2_PU */ 2527*4882a593Smuzhiyun #define WM2200_GP2_PU_WIDTH 1 /* GP2_PU */ 2528*4882a593Smuzhiyun #define WM2200_GP2_PD 0x2000 /* GP2_PD */ 2529*4882a593Smuzhiyun #define WM2200_GP2_PD_MASK 0x2000 /* GP2_PD */ 2530*4882a593Smuzhiyun #define WM2200_GP2_PD_SHIFT 13 /* GP2_PD */ 2531*4882a593Smuzhiyun #define WM2200_GP2_PD_WIDTH 1 /* GP2_PD */ 2532*4882a593Smuzhiyun #define WM2200_GP2_POL 0x0400 /* GP2_POL */ 2533*4882a593Smuzhiyun #define WM2200_GP2_POL_MASK 0x0400 /* GP2_POL */ 2534*4882a593Smuzhiyun #define WM2200_GP2_POL_SHIFT 10 /* GP2_POL */ 2535*4882a593Smuzhiyun #define WM2200_GP2_POL_WIDTH 1 /* GP2_POL */ 2536*4882a593Smuzhiyun #define WM2200_GP2_OP_CFG 0x0200 /* GP2_OP_CFG */ 2537*4882a593Smuzhiyun #define WM2200_GP2_OP_CFG_MASK 0x0200 /* GP2_OP_CFG */ 2538*4882a593Smuzhiyun #define WM2200_GP2_OP_CFG_SHIFT 9 /* GP2_OP_CFG */ 2539*4882a593Smuzhiyun #define WM2200_GP2_OP_CFG_WIDTH 1 /* GP2_OP_CFG */ 2540*4882a593Smuzhiyun #define WM2200_GP2_DB 0x0100 /* GP2_DB */ 2541*4882a593Smuzhiyun #define WM2200_GP2_DB_MASK 0x0100 /* GP2_DB */ 2542*4882a593Smuzhiyun #define WM2200_GP2_DB_SHIFT 8 /* GP2_DB */ 2543*4882a593Smuzhiyun #define WM2200_GP2_DB_WIDTH 1 /* GP2_DB */ 2544*4882a593Smuzhiyun #define WM2200_GP2_LVL 0x0040 /* GP2_LVL */ 2545*4882a593Smuzhiyun #define WM2200_GP2_LVL_MASK 0x0040 /* GP2_LVL */ 2546*4882a593Smuzhiyun #define WM2200_GP2_LVL_SHIFT 6 /* GP2_LVL */ 2547*4882a593Smuzhiyun #define WM2200_GP2_LVL_WIDTH 1 /* GP2_LVL */ 2548*4882a593Smuzhiyun #define WM2200_GP2_FN_MASK 0x003F /* GP2_FN - [5:0] */ 2549*4882a593Smuzhiyun #define WM2200_GP2_FN_SHIFT 0 /* GP2_FN - [5:0] */ 2550*4882a593Smuzhiyun #define WM2200_GP2_FN_WIDTH 6 /* GP2_FN - [5:0] */ 2551*4882a593Smuzhiyun 2552*4882a593Smuzhiyun /* 2553*4882a593Smuzhiyun * R1794 (0x702) - GPIO CTRL 3 2554*4882a593Smuzhiyun */ 2555*4882a593Smuzhiyun #define WM2200_GP3_DIR 0x8000 /* GP3_DIR */ 2556*4882a593Smuzhiyun #define WM2200_GP3_DIR_MASK 0x8000 /* GP3_DIR */ 2557*4882a593Smuzhiyun #define WM2200_GP3_DIR_SHIFT 15 /* GP3_DIR */ 2558*4882a593Smuzhiyun #define WM2200_GP3_DIR_WIDTH 1 /* GP3_DIR */ 2559*4882a593Smuzhiyun #define WM2200_GP3_PU 0x4000 /* GP3_PU */ 2560*4882a593Smuzhiyun #define WM2200_GP3_PU_MASK 0x4000 /* GP3_PU */ 2561*4882a593Smuzhiyun #define WM2200_GP3_PU_SHIFT 14 /* GP3_PU */ 2562*4882a593Smuzhiyun #define WM2200_GP3_PU_WIDTH 1 /* GP3_PU */ 2563*4882a593Smuzhiyun #define WM2200_GP3_PD 0x2000 /* GP3_PD */ 2564*4882a593Smuzhiyun #define WM2200_GP3_PD_MASK 0x2000 /* GP3_PD */ 2565*4882a593Smuzhiyun #define WM2200_GP3_PD_SHIFT 13 /* GP3_PD */ 2566*4882a593Smuzhiyun #define WM2200_GP3_PD_WIDTH 1 /* GP3_PD */ 2567*4882a593Smuzhiyun #define WM2200_GP3_POL 0x0400 /* GP3_POL */ 2568*4882a593Smuzhiyun #define WM2200_GP3_POL_MASK 0x0400 /* GP3_POL */ 2569*4882a593Smuzhiyun #define WM2200_GP3_POL_SHIFT 10 /* GP3_POL */ 2570*4882a593Smuzhiyun #define WM2200_GP3_POL_WIDTH 1 /* GP3_POL */ 2571*4882a593Smuzhiyun #define WM2200_GP3_OP_CFG 0x0200 /* GP3_OP_CFG */ 2572*4882a593Smuzhiyun #define WM2200_GP3_OP_CFG_MASK 0x0200 /* GP3_OP_CFG */ 2573*4882a593Smuzhiyun #define WM2200_GP3_OP_CFG_SHIFT 9 /* GP3_OP_CFG */ 2574*4882a593Smuzhiyun #define WM2200_GP3_OP_CFG_WIDTH 1 /* GP3_OP_CFG */ 2575*4882a593Smuzhiyun #define WM2200_GP3_DB 0x0100 /* GP3_DB */ 2576*4882a593Smuzhiyun #define WM2200_GP3_DB_MASK 0x0100 /* GP3_DB */ 2577*4882a593Smuzhiyun #define WM2200_GP3_DB_SHIFT 8 /* GP3_DB */ 2578*4882a593Smuzhiyun #define WM2200_GP3_DB_WIDTH 1 /* GP3_DB */ 2579*4882a593Smuzhiyun #define WM2200_GP3_LVL 0x0040 /* GP3_LVL */ 2580*4882a593Smuzhiyun #define WM2200_GP3_LVL_MASK 0x0040 /* GP3_LVL */ 2581*4882a593Smuzhiyun #define WM2200_GP3_LVL_SHIFT 6 /* GP3_LVL */ 2582*4882a593Smuzhiyun #define WM2200_GP3_LVL_WIDTH 1 /* GP3_LVL */ 2583*4882a593Smuzhiyun #define WM2200_GP3_FN_MASK 0x003F /* GP3_FN - [5:0] */ 2584*4882a593Smuzhiyun #define WM2200_GP3_FN_SHIFT 0 /* GP3_FN - [5:0] */ 2585*4882a593Smuzhiyun #define WM2200_GP3_FN_WIDTH 6 /* GP3_FN - [5:0] */ 2586*4882a593Smuzhiyun 2587*4882a593Smuzhiyun /* 2588*4882a593Smuzhiyun * R1795 (0x703) - GPIO CTRL 4 2589*4882a593Smuzhiyun */ 2590*4882a593Smuzhiyun #define WM2200_GP4_DIR 0x8000 /* GP4_DIR */ 2591*4882a593Smuzhiyun #define WM2200_GP4_DIR_MASK 0x8000 /* GP4_DIR */ 2592*4882a593Smuzhiyun #define WM2200_GP4_DIR_SHIFT 15 /* GP4_DIR */ 2593*4882a593Smuzhiyun #define WM2200_GP4_DIR_WIDTH 1 /* GP4_DIR */ 2594*4882a593Smuzhiyun #define WM2200_GP4_PU 0x4000 /* GP4_PU */ 2595*4882a593Smuzhiyun #define WM2200_GP4_PU_MASK 0x4000 /* GP4_PU */ 2596*4882a593Smuzhiyun #define WM2200_GP4_PU_SHIFT 14 /* GP4_PU */ 2597*4882a593Smuzhiyun #define WM2200_GP4_PU_WIDTH 1 /* GP4_PU */ 2598*4882a593Smuzhiyun #define WM2200_GP4_PD 0x2000 /* GP4_PD */ 2599*4882a593Smuzhiyun #define WM2200_GP4_PD_MASK 0x2000 /* GP4_PD */ 2600*4882a593Smuzhiyun #define WM2200_GP4_PD_SHIFT 13 /* GP4_PD */ 2601*4882a593Smuzhiyun #define WM2200_GP4_PD_WIDTH 1 /* GP4_PD */ 2602*4882a593Smuzhiyun #define WM2200_GP4_POL 0x0400 /* GP4_POL */ 2603*4882a593Smuzhiyun #define WM2200_GP4_POL_MASK 0x0400 /* GP4_POL */ 2604*4882a593Smuzhiyun #define WM2200_GP4_POL_SHIFT 10 /* GP4_POL */ 2605*4882a593Smuzhiyun #define WM2200_GP4_POL_WIDTH 1 /* GP4_POL */ 2606*4882a593Smuzhiyun #define WM2200_GP4_OP_CFG 0x0200 /* GP4_OP_CFG */ 2607*4882a593Smuzhiyun #define WM2200_GP4_OP_CFG_MASK 0x0200 /* GP4_OP_CFG */ 2608*4882a593Smuzhiyun #define WM2200_GP4_OP_CFG_SHIFT 9 /* GP4_OP_CFG */ 2609*4882a593Smuzhiyun #define WM2200_GP4_OP_CFG_WIDTH 1 /* GP4_OP_CFG */ 2610*4882a593Smuzhiyun #define WM2200_GP4_DB 0x0100 /* GP4_DB */ 2611*4882a593Smuzhiyun #define WM2200_GP4_DB_MASK 0x0100 /* GP4_DB */ 2612*4882a593Smuzhiyun #define WM2200_GP4_DB_SHIFT 8 /* GP4_DB */ 2613*4882a593Smuzhiyun #define WM2200_GP4_DB_WIDTH 1 /* GP4_DB */ 2614*4882a593Smuzhiyun #define WM2200_GP4_LVL 0x0040 /* GP4_LVL */ 2615*4882a593Smuzhiyun #define WM2200_GP4_LVL_MASK 0x0040 /* GP4_LVL */ 2616*4882a593Smuzhiyun #define WM2200_GP4_LVL_SHIFT 6 /* GP4_LVL */ 2617*4882a593Smuzhiyun #define WM2200_GP4_LVL_WIDTH 1 /* GP4_LVL */ 2618*4882a593Smuzhiyun #define WM2200_GP4_FN_MASK 0x003F /* GP4_FN - [5:0] */ 2619*4882a593Smuzhiyun #define WM2200_GP4_FN_SHIFT 0 /* GP4_FN - [5:0] */ 2620*4882a593Smuzhiyun #define WM2200_GP4_FN_WIDTH 6 /* GP4_FN - [5:0] */ 2621*4882a593Smuzhiyun 2622*4882a593Smuzhiyun /* 2623*4882a593Smuzhiyun * R1799 (0x707) - ADPS1 IRQ0 2624*4882a593Smuzhiyun */ 2625*4882a593Smuzhiyun #define WM2200_DSP_IRQ1 0x0002 /* DSP_IRQ1 */ 2626*4882a593Smuzhiyun #define WM2200_DSP_IRQ1_MASK 0x0002 /* DSP_IRQ1 */ 2627*4882a593Smuzhiyun #define WM2200_DSP_IRQ1_SHIFT 1 /* DSP_IRQ1 */ 2628*4882a593Smuzhiyun #define WM2200_DSP_IRQ1_WIDTH 1 /* DSP_IRQ1 */ 2629*4882a593Smuzhiyun #define WM2200_DSP_IRQ0 0x0001 /* DSP_IRQ0 */ 2630*4882a593Smuzhiyun #define WM2200_DSP_IRQ0_MASK 0x0001 /* DSP_IRQ0 */ 2631*4882a593Smuzhiyun #define WM2200_DSP_IRQ0_SHIFT 0 /* DSP_IRQ0 */ 2632*4882a593Smuzhiyun #define WM2200_DSP_IRQ0_WIDTH 1 /* DSP_IRQ0 */ 2633*4882a593Smuzhiyun 2634*4882a593Smuzhiyun /* 2635*4882a593Smuzhiyun * R1800 (0x708) - ADPS1 IRQ1 2636*4882a593Smuzhiyun */ 2637*4882a593Smuzhiyun #define WM2200_DSP_IRQ3 0x0002 /* DSP_IRQ3 */ 2638*4882a593Smuzhiyun #define WM2200_DSP_IRQ3_MASK 0x0002 /* DSP_IRQ3 */ 2639*4882a593Smuzhiyun #define WM2200_DSP_IRQ3_SHIFT 1 /* DSP_IRQ3 */ 2640*4882a593Smuzhiyun #define WM2200_DSP_IRQ3_WIDTH 1 /* DSP_IRQ3 */ 2641*4882a593Smuzhiyun #define WM2200_DSP_IRQ2 0x0001 /* DSP_IRQ2 */ 2642*4882a593Smuzhiyun #define WM2200_DSP_IRQ2_MASK 0x0001 /* DSP_IRQ2 */ 2643*4882a593Smuzhiyun #define WM2200_DSP_IRQ2_SHIFT 0 /* DSP_IRQ2 */ 2644*4882a593Smuzhiyun #define WM2200_DSP_IRQ2_WIDTH 1 /* DSP_IRQ2 */ 2645*4882a593Smuzhiyun 2646*4882a593Smuzhiyun /* 2647*4882a593Smuzhiyun * R1801 (0x709) - Misc Pad Ctrl 1 2648*4882a593Smuzhiyun */ 2649*4882a593Smuzhiyun #define WM2200_LDO1ENA_PD 0x8000 /* LDO1ENA_PD */ 2650*4882a593Smuzhiyun #define WM2200_LDO1ENA_PD_MASK 0x8000 /* LDO1ENA_PD */ 2651*4882a593Smuzhiyun #define WM2200_LDO1ENA_PD_SHIFT 15 /* LDO1ENA_PD */ 2652*4882a593Smuzhiyun #define WM2200_LDO1ENA_PD_WIDTH 1 /* LDO1ENA_PD */ 2653*4882a593Smuzhiyun #define WM2200_MCLK2_PD 0x2000 /* MCLK2_PD */ 2654*4882a593Smuzhiyun #define WM2200_MCLK2_PD_MASK 0x2000 /* MCLK2_PD */ 2655*4882a593Smuzhiyun #define WM2200_MCLK2_PD_SHIFT 13 /* MCLK2_PD */ 2656*4882a593Smuzhiyun #define WM2200_MCLK2_PD_WIDTH 1 /* MCLK2_PD */ 2657*4882a593Smuzhiyun #define WM2200_MCLK1_PD 0x1000 /* MCLK1_PD */ 2658*4882a593Smuzhiyun #define WM2200_MCLK1_PD_MASK 0x1000 /* MCLK1_PD */ 2659*4882a593Smuzhiyun #define WM2200_MCLK1_PD_SHIFT 12 /* MCLK1_PD */ 2660*4882a593Smuzhiyun #define WM2200_MCLK1_PD_WIDTH 1 /* MCLK1_PD */ 2661*4882a593Smuzhiyun #define WM2200_DACLRCLK1_PU 0x0400 /* DACLRCLK1_PU */ 2662*4882a593Smuzhiyun #define WM2200_DACLRCLK1_PU_MASK 0x0400 /* DACLRCLK1_PU */ 2663*4882a593Smuzhiyun #define WM2200_DACLRCLK1_PU_SHIFT 10 /* DACLRCLK1_PU */ 2664*4882a593Smuzhiyun #define WM2200_DACLRCLK1_PU_WIDTH 1 /* DACLRCLK1_PU */ 2665*4882a593Smuzhiyun #define WM2200_DACLRCLK1_PD 0x0200 /* DACLRCLK1_PD */ 2666*4882a593Smuzhiyun #define WM2200_DACLRCLK1_PD_MASK 0x0200 /* DACLRCLK1_PD */ 2667*4882a593Smuzhiyun #define WM2200_DACLRCLK1_PD_SHIFT 9 /* DACLRCLK1_PD */ 2668*4882a593Smuzhiyun #define WM2200_DACLRCLK1_PD_WIDTH 1 /* DACLRCLK1_PD */ 2669*4882a593Smuzhiyun #define WM2200_BCLK1_PU 0x0100 /* BCLK1_PU */ 2670*4882a593Smuzhiyun #define WM2200_BCLK1_PU_MASK 0x0100 /* BCLK1_PU */ 2671*4882a593Smuzhiyun #define WM2200_BCLK1_PU_SHIFT 8 /* BCLK1_PU */ 2672*4882a593Smuzhiyun #define WM2200_BCLK1_PU_WIDTH 1 /* BCLK1_PU */ 2673*4882a593Smuzhiyun #define WM2200_BCLK1_PD 0x0080 /* BCLK1_PD */ 2674*4882a593Smuzhiyun #define WM2200_BCLK1_PD_MASK 0x0080 /* BCLK1_PD */ 2675*4882a593Smuzhiyun #define WM2200_BCLK1_PD_SHIFT 7 /* BCLK1_PD */ 2676*4882a593Smuzhiyun #define WM2200_BCLK1_PD_WIDTH 1 /* BCLK1_PD */ 2677*4882a593Smuzhiyun #define WM2200_DACDAT1_PU 0x0040 /* DACDAT1_PU */ 2678*4882a593Smuzhiyun #define WM2200_DACDAT1_PU_MASK 0x0040 /* DACDAT1_PU */ 2679*4882a593Smuzhiyun #define WM2200_DACDAT1_PU_SHIFT 6 /* DACDAT1_PU */ 2680*4882a593Smuzhiyun #define WM2200_DACDAT1_PU_WIDTH 1 /* DACDAT1_PU */ 2681*4882a593Smuzhiyun #define WM2200_DACDAT1_PD 0x0020 /* DACDAT1_PD */ 2682*4882a593Smuzhiyun #define WM2200_DACDAT1_PD_MASK 0x0020 /* DACDAT1_PD */ 2683*4882a593Smuzhiyun #define WM2200_DACDAT1_PD_SHIFT 5 /* DACDAT1_PD */ 2684*4882a593Smuzhiyun #define WM2200_DACDAT1_PD_WIDTH 1 /* DACDAT1_PD */ 2685*4882a593Smuzhiyun #define WM2200_DMICDAT3_PD 0x0010 /* DMICDAT3_PD */ 2686*4882a593Smuzhiyun #define WM2200_DMICDAT3_PD_MASK 0x0010 /* DMICDAT3_PD */ 2687*4882a593Smuzhiyun #define WM2200_DMICDAT3_PD_SHIFT 4 /* DMICDAT3_PD */ 2688*4882a593Smuzhiyun #define WM2200_DMICDAT3_PD_WIDTH 1 /* DMICDAT3_PD */ 2689*4882a593Smuzhiyun #define WM2200_DMICDAT2_PD 0x0008 /* DMICDAT2_PD */ 2690*4882a593Smuzhiyun #define WM2200_DMICDAT2_PD_MASK 0x0008 /* DMICDAT2_PD */ 2691*4882a593Smuzhiyun #define WM2200_DMICDAT2_PD_SHIFT 3 /* DMICDAT2_PD */ 2692*4882a593Smuzhiyun #define WM2200_DMICDAT2_PD_WIDTH 1 /* DMICDAT2_PD */ 2693*4882a593Smuzhiyun #define WM2200_DMICDAT1_PD 0x0004 /* DMICDAT1_PD */ 2694*4882a593Smuzhiyun #define WM2200_DMICDAT1_PD_MASK 0x0004 /* DMICDAT1_PD */ 2695*4882a593Smuzhiyun #define WM2200_DMICDAT1_PD_SHIFT 2 /* DMICDAT1_PD */ 2696*4882a593Smuzhiyun #define WM2200_DMICDAT1_PD_WIDTH 1 /* DMICDAT1_PD */ 2697*4882a593Smuzhiyun #define WM2200_RSTB_PU 0x0002 /* RSTB_PU */ 2698*4882a593Smuzhiyun #define WM2200_RSTB_PU_MASK 0x0002 /* RSTB_PU */ 2699*4882a593Smuzhiyun #define WM2200_RSTB_PU_SHIFT 1 /* RSTB_PU */ 2700*4882a593Smuzhiyun #define WM2200_RSTB_PU_WIDTH 1 /* RSTB_PU */ 2701*4882a593Smuzhiyun #define WM2200_ADDR_PD 0x0001 /* ADDR_PD */ 2702*4882a593Smuzhiyun #define WM2200_ADDR_PD_MASK 0x0001 /* ADDR_PD */ 2703*4882a593Smuzhiyun #define WM2200_ADDR_PD_SHIFT 0 /* ADDR_PD */ 2704*4882a593Smuzhiyun #define WM2200_ADDR_PD_WIDTH 1 /* ADDR_PD */ 2705*4882a593Smuzhiyun 2706*4882a593Smuzhiyun /* 2707*4882a593Smuzhiyun * R2048 (0x800) - Interrupt Status 1 2708*4882a593Smuzhiyun */ 2709*4882a593Smuzhiyun #define WM2200_DSP_IRQ0_EINT 0x0080 /* DSP_IRQ0_EINT */ 2710*4882a593Smuzhiyun #define WM2200_DSP_IRQ0_EINT_MASK 0x0080 /* DSP_IRQ0_EINT */ 2711*4882a593Smuzhiyun #define WM2200_DSP_IRQ0_EINT_SHIFT 7 /* DSP_IRQ0_EINT */ 2712*4882a593Smuzhiyun #define WM2200_DSP_IRQ0_EINT_WIDTH 1 /* DSP_IRQ0_EINT */ 2713*4882a593Smuzhiyun #define WM2200_DSP_IRQ1_EINT 0x0040 /* DSP_IRQ1_EINT */ 2714*4882a593Smuzhiyun #define WM2200_DSP_IRQ1_EINT_MASK 0x0040 /* DSP_IRQ1_EINT */ 2715*4882a593Smuzhiyun #define WM2200_DSP_IRQ1_EINT_SHIFT 6 /* DSP_IRQ1_EINT */ 2716*4882a593Smuzhiyun #define WM2200_DSP_IRQ1_EINT_WIDTH 1 /* DSP_IRQ1_EINT */ 2717*4882a593Smuzhiyun #define WM2200_DSP_IRQ2_EINT 0x0020 /* DSP_IRQ2_EINT */ 2718*4882a593Smuzhiyun #define WM2200_DSP_IRQ2_EINT_MASK 0x0020 /* DSP_IRQ2_EINT */ 2719*4882a593Smuzhiyun #define WM2200_DSP_IRQ2_EINT_SHIFT 5 /* DSP_IRQ2_EINT */ 2720*4882a593Smuzhiyun #define WM2200_DSP_IRQ2_EINT_WIDTH 1 /* DSP_IRQ2_EINT */ 2721*4882a593Smuzhiyun #define WM2200_DSP_IRQ3_EINT 0x0010 /* DSP_IRQ3_EINT */ 2722*4882a593Smuzhiyun #define WM2200_DSP_IRQ3_EINT_MASK 0x0010 /* DSP_IRQ3_EINT */ 2723*4882a593Smuzhiyun #define WM2200_DSP_IRQ3_EINT_SHIFT 4 /* DSP_IRQ3_EINT */ 2724*4882a593Smuzhiyun #define WM2200_DSP_IRQ3_EINT_WIDTH 1 /* DSP_IRQ3_EINT */ 2725*4882a593Smuzhiyun #define WM2200_GP4_EINT 0x0008 /* GP4_EINT */ 2726*4882a593Smuzhiyun #define WM2200_GP4_EINT_MASK 0x0008 /* GP4_EINT */ 2727*4882a593Smuzhiyun #define WM2200_GP4_EINT_SHIFT 3 /* GP4_EINT */ 2728*4882a593Smuzhiyun #define WM2200_GP4_EINT_WIDTH 1 /* GP4_EINT */ 2729*4882a593Smuzhiyun #define WM2200_GP3_EINT 0x0004 /* GP3_EINT */ 2730*4882a593Smuzhiyun #define WM2200_GP3_EINT_MASK 0x0004 /* GP3_EINT */ 2731*4882a593Smuzhiyun #define WM2200_GP3_EINT_SHIFT 2 /* GP3_EINT */ 2732*4882a593Smuzhiyun #define WM2200_GP3_EINT_WIDTH 1 /* GP3_EINT */ 2733*4882a593Smuzhiyun #define WM2200_GP2_EINT 0x0002 /* GP2_EINT */ 2734*4882a593Smuzhiyun #define WM2200_GP2_EINT_MASK 0x0002 /* GP2_EINT */ 2735*4882a593Smuzhiyun #define WM2200_GP2_EINT_SHIFT 1 /* GP2_EINT */ 2736*4882a593Smuzhiyun #define WM2200_GP2_EINT_WIDTH 1 /* GP2_EINT */ 2737*4882a593Smuzhiyun #define WM2200_GP1_EINT 0x0001 /* GP1_EINT */ 2738*4882a593Smuzhiyun #define WM2200_GP1_EINT_MASK 0x0001 /* GP1_EINT */ 2739*4882a593Smuzhiyun #define WM2200_GP1_EINT_SHIFT 0 /* GP1_EINT */ 2740*4882a593Smuzhiyun #define WM2200_GP1_EINT_WIDTH 1 /* GP1_EINT */ 2741*4882a593Smuzhiyun 2742*4882a593Smuzhiyun /* 2743*4882a593Smuzhiyun * R2049 (0x801) - Interrupt Status 1 Mask 2744*4882a593Smuzhiyun */ 2745*4882a593Smuzhiyun #define WM2200_IM_DSP_IRQ0_EINT 0x0080 /* IM_DSP_IRQ0_EINT */ 2746*4882a593Smuzhiyun #define WM2200_IM_DSP_IRQ0_EINT_MASK 0x0080 /* IM_DSP_IRQ0_EINT */ 2747*4882a593Smuzhiyun #define WM2200_IM_DSP_IRQ0_EINT_SHIFT 7 /* IM_DSP_IRQ0_EINT */ 2748*4882a593Smuzhiyun #define WM2200_IM_DSP_IRQ0_EINT_WIDTH 1 /* IM_DSP_IRQ0_EINT */ 2749*4882a593Smuzhiyun #define WM2200_IM_DSP_IRQ1_EINT 0x0040 /* IM_DSP_IRQ1_EINT */ 2750*4882a593Smuzhiyun #define WM2200_IM_DSP_IRQ1_EINT_MASK 0x0040 /* IM_DSP_IRQ1_EINT */ 2751*4882a593Smuzhiyun #define WM2200_IM_DSP_IRQ1_EINT_SHIFT 6 /* IM_DSP_IRQ1_EINT */ 2752*4882a593Smuzhiyun #define WM2200_IM_DSP_IRQ1_EINT_WIDTH 1 /* IM_DSP_IRQ1_EINT */ 2753*4882a593Smuzhiyun #define WM2200_IM_DSP_IRQ2_EINT 0x0020 /* IM_DSP_IRQ2_EINT */ 2754*4882a593Smuzhiyun #define WM2200_IM_DSP_IRQ2_EINT_MASK 0x0020 /* IM_DSP_IRQ2_EINT */ 2755*4882a593Smuzhiyun #define WM2200_IM_DSP_IRQ2_EINT_SHIFT 5 /* IM_DSP_IRQ2_EINT */ 2756*4882a593Smuzhiyun #define WM2200_IM_DSP_IRQ2_EINT_WIDTH 1 /* IM_DSP_IRQ2_EINT */ 2757*4882a593Smuzhiyun #define WM2200_IM_DSP_IRQ3_EINT 0x0010 /* IM_DSP_IRQ3_EINT */ 2758*4882a593Smuzhiyun #define WM2200_IM_DSP_IRQ3_EINT_MASK 0x0010 /* IM_DSP_IRQ3_EINT */ 2759*4882a593Smuzhiyun #define WM2200_IM_DSP_IRQ3_EINT_SHIFT 4 /* IM_DSP_IRQ3_EINT */ 2760*4882a593Smuzhiyun #define WM2200_IM_DSP_IRQ3_EINT_WIDTH 1 /* IM_DSP_IRQ3_EINT */ 2761*4882a593Smuzhiyun #define WM2200_IM_GP4_EINT 0x0008 /* IM_GP4_EINT */ 2762*4882a593Smuzhiyun #define WM2200_IM_GP4_EINT_MASK 0x0008 /* IM_GP4_EINT */ 2763*4882a593Smuzhiyun #define WM2200_IM_GP4_EINT_SHIFT 3 /* IM_GP4_EINT */ 2764*4882a593Smuzhiyun #define WM2200_IM_GP4_EINT_WIDTH 1 /* IM_GP4_EINT */ 2765*4882a593Smuzhiyun #define WM2200_IM_GP3_EINT 0x0004 /* IM_GP3_EINT */ 2766*4882a593Smuzhiyun #define WM2200_IM_GP3_EINT_MASK 0x0004 /* IM_GP3_EINT */ 2767*4882a593Smuzhiyun #define WM2200_IM_GP3_EINT_SHIFT 2 /* IM_GP3_EINT */ 2768*4882a593Smuzhiyun #define WM2200_IM_GP3_EINT_WIDTH 1 /* IM_GP3_EINT */ 2769*4882a593Smuzhiyun #define WM2200_IM_GP2_EINT 0x0002 /* IM_GP2_EINT */ 2770*4882a593Smuzhiyun #define WM2200_IM_GP2_EINT_MASK 0x0002 /* IM_GP2_EINT */ 2771*4882a593Smuzhiyun #define WM2200_IM_GP2_EINT_SHIFT 1 /* IM_GP2_EINT */ 2772*4882a593Smuzhiyun #define WM2200_IM_GP2_EINT_WIDTH 1 /* IM_GP2_EINT */ 2773*4882a593Smuzhiyun #define WM2200_IM_GP1_EINT 0x0001 /* IM_GP1_EINT */ 2774*4882a593Smuzhiyun #define WM2200_IM_GP1_EINT_MASK 0x0001 /* IM_GP1_EINT */ 2775*4882a593Smuzhiyun #define WM2200_IM_GP1_EINT_SHIFT 0 /* IM_GP1_EINT */ 2776*4882a593Smuzhiyun #define WM2200_IM_GP1_EINT_WIDTH 1 /* IM_GP1_EINT */ 2777*4882a593Smuzhiyun 2778*4882a593Smuzhiyun /* 2779*4882a593Smuzhiyun * R2050 (0x802) - Interrupt Status 2 2780*4882a593Smuzhiyun */ 2781*4882a593Smuzhiyun #define WM2200_WSEQ_BUSY_EINT 0x0100 /* WSEQ_BUSY_EINT */ 2782*4882a593Smuzhiyun #define WM2200_WSEQ_BUSY_EINT_MASK 0x0100 /* WSEQ_BUSY_EINT */ 2783*4882a593Smuzhiyun #define WM2200_WSEQ_BUSY_EINT_SHIFT 8 /* WSEQ_BUSY_EINT */ 2784*4882a593Smuzhiyun #define WM2200_WSEQ_BUSY_EINT_WIDTH 1 /* WSEQ_BUSY_EINT */ 2785*4882a593Smuzhiyun #define WM2200_FLL_LOCK_EINT 0x0002 /* FLL_LOCK_EINT */ 2786*4882a593Smuzhiyun #define WM2200_FLL_LOCK_EINT_MASK 0x0002 /* FLL_LOCK_EINT */ 2787*4882a593Smuzhiyun #define WM2200_FLL_LOCK_EINT_SHIFT 1 /* FLL_LOCK_EINT */ 2788*4882a593Smuzhiyun #define WM2200_FLL_LOCK_EINT_WIDTH 1 /* FLL_LOCK_EINT */ 2789*4882a593Smuzhiyun #define WM2200_CLKGEN_EINT 0x0001 /* CLKGEN_EINT */ 2790*4882a593Smuzhiyun #define WM2200_CLKGEN_EINT_MASK 0x0001 /* CLKGEN_EINT */ 2791*4882a593Smuzhiyun #define WM2200_CLKGEN_EINT_SHIFT 0 /* CLKGEN_EINT */ 2792*4882a593Smuzhiyun #define WM2200_CLKGEN_EINT_WIDTH 1 /* CLKGEN_EINT */ 2793*4882a593Smuzhiyun 2794*4882a593Smuzhiyun /* 2795*4882a593Smuzhiyun * R2051 (0x803) - Interrupt Raw Status 2 2796*4882a593Smuzhiyun */ 2797*4882a593Smuzhiyun #define WM2200_WSEQ_BUSY_STS 0x0100 /* WSEQ_BUSY_STS */ 2798*4882a593Smuzhiyun #define WM2200_WSEQ_BUSY_STS_MASK 0x0100 /* WSEQ_BUSY_STS */ 2799*4882a593Smuzhiyun #define WM2200_WSEQ_BUSY_STS_SHIFT 8 /* WSEQ_BUSY_STS */ 2800*4882a593Smuzhiyun #define WM2200_WSEQ_BUSY_STS_WIDTH 1 /* WSEQ_BUSY_STS */ 2801*4882a593Smuzhiyun #define WM2200_FLL_LOCK_STS 0x0002 /* FLL_LOCK_STS */ 2802*4882a593Smuzhiyun #define WM2200_FLL_LOCK_STS_MASK 0x0002 /* FLL_LOCK_STS */ 2803*4882a593Smuzhiyun #define WM2200_FLL_LOCK_STS_SHIFT 1 /* FLL_LOCK_STS */ 2804*4882a593Smuzhiyun #define WM2200_FLL_LOCK_STS_WIDTH 1 /* FLL_LOCK_STS */ 2805*4882a593Smuzhiyun #define WM2200_CLKGEN_STS 0x0001 /* CLKGEN_STS */ 2806*4882a593Smuzhiyun #define WM2200_CLKGEN_STS_MASK 0x0001 /* CLKGEN_STS */ 2807*4882a593Smuzhiyun #define WM2200_CLKGEN_STS_SHIFT 0 /* CLKGEN_STS */ 2808*4882a593Smuzhiyun #define WM2200_CLKGEN_STS_WIDTH 1 /* CLKGEN_STS */ 2809*4882a593Smuzhiyun 2810*4882a593Smuzhiyun /* 2811*4882a593Smuzhiyun * R2052 (0x804) - Interrupt Status 2 Mask 2812*4882a593Smuzhiyun */ 2813*4882a593Smuzhiyun #define WM2200_IM_WSEQ_BUSY_EINT 0x0100 /* IM_WSEQ_BUSY_EINT */ 2814*4882a593Smuzhiyun #define WM2200_IM_WSEQ_BUSY_EINT_MASK 0x0100 /* IM_WSEQ_BUSY_EINT */ 2815*4882a593Smuzhiyun #define WM2200_IM_WSEQ_BUSY_EINT_SHIFT 8 /* IM_WSEQ_BUSY_EINT */ 2816*4882a593Smuzhiyun #define WM2200_IM_WSEQ_BUSY_EINT_WIDTH 1 /* IM_WSEQ_BUSY_EINT */ 2817*4882a593Smuzhiyun #define WM2200_IM_FLL_LOCK_EINT 0x0002 /* IM_FLL_LOCK_EINT */ 2818*4882a593Smuzhiyun #define WM2200_IM_FLL_LOCK_EINT_MASK 0x0002 /* IM_FLL_LOCK_EINT */ 2819*4882a593Smuzhiyun #define WM2200_IM_FLL_LOCK_EINT_SHIFT 1 /* IM_FLL_LOCK_EINT */ 2820*4882a593Smuzhiyun #define WM2200_IM_FLL_LOCK_EINT_WIDTH 1 /* IM_FLL_LOCK_EINT */ 2821*4882a593Smuzhiyun #define WM2200_IM_CLKGEN_EINT 0x0001 /* IM_CLKGEN_EINT */ 2822*4882a593Smuzhiyun #define WM2200_IM_CLKGEN_EINT_MASK 0x0001 /* IM_CLKGEN_EINT */ 2823*4882a593Smuzhiyun #define WM2200_IM_CLKGEN_EINT_SHIFT 0 /* IM_CLKGEN_EINT */ 2824*4882a593Smuzhiyun #define WM2200_IM_CLKGEN_EINT_WIDTH 1 /* IM_CLKGEN_EINT */ 2825*4882a593Smuzhiyun 2826*4882a593Smuzhiyun /* 2827*4882a593Smuzhiyun * R2056 (0x808) - Interrupt Control 2828*4882a593Smuzhiyun */ 2829*4882a593Smuzhiyun #define WM2200_IM_IRQ 0x0001 /* IM_IRQ */ 2830*4882a593Smuzhiyun #define WM2200_IM_IRQ_MASK 0x0001 /* IM_IRQ */ 2831*4882a593Smuzhiyun #define WM2200_IM_IRQ_SHIFT 0 /* IM_IRQ */ 2832*4882a593Smuzhiyun #define WM2200_IM_IRQ_WIDTH 1 /* IM_IRQ */ 2833*4882a593Smuzhiyun 2834*4882a593Smuzhiyun /* 2835*4882a593Smuzhiyun * R2304 (0x900) - EQL_1 2836*4882a593Smuzhiyun */ 2837*4882a593Smuzhiyun #define WM2200_EQL_B1_GAIN_MASK 0xF800 /* EQL_B1_GAIN - [15:11] */ 2838*4882a593Smuzhiyun #define WM2200_EQL_B1_GAIN_SHIFT 11 /* EQL_B1_GAIN - [15:11] */ 2839*4882a593Smuzhiyun #define WM2200_EQL_B1_GAIN_WIDTH 5 /* EQL_B1_GAIN - [15:11] */ 2840*4882a593Smuzhiyun #define WM2200_EQL_B2_GAIN_MASK 0x07C0 /* EQL_B2_GAIN - [10:6] */ 2841*4882a593Smuzhiyun #define WM2200_EQL_B2_GAIN_SHIFT 6 /* EQL_B2_GAIN - [10:6] */ 2842*4882a593Smuzhiyun #define WM2200_EQL_B2_GAIN_WIDTH 5 /* EQL_B2_GAIN - [10:6] */ 2843*4882a593Smuzhiyun #define WM2200_EQL_B3_GAIN_MASK 0x003E /* EQL_B3_GAIN - [5:1] */ 2844*4882a593Smuzhiyun #define WM2200_EQL_B3_GAIN_SHIFT 1 /* EQL_B3_GAIN - [5:1] */ 2845*4882a593Smuzhiyun #define WM2200_EQL_B3_GAIN_WIDTH 5 /* EQL_B3_GAIN - [5:1] */ 2846*4882a593Smuzhiyun #define WM2200_EQL_ENA 0x0001 /* EQL_ENA */ 2847*4882a593Smuzhiyun #define WM2200_EQL_ENA_MASK 0x0001 /* EQL_ENA */ 2848*4882a593Smuzhiyun #define WM2200_EQL_ENA_SHIFT 0 /* EQL_ENA */ 2849*4882a593Smuzhiyun #define WM2200_EQL_ENA_WIDTH 1 /* EQL_ENA */ 2850*4882a593Smuzhiyun 2851*4882a593Smuzhiyun /* 2852*4882a593Smuzhiyun * R2305 (0x901) - EQL_2 2853*4882a593Smuzhiyun */ 2854*4882a593Smuzhiyun #define WM2200_EQL_B4_GAIN_MASK 0xF800 /* EQL_B4_GAIN - [15:11] */ 2855*4882a593Smuzhiyun #define WM2200_EQL_B4_GAIN_SHIFT 11 /* EQL_B4_GAIN - [15:11] */ 2856*4882a593Smuzhiyun #define WM2200_EQL_B4_GAIN_WIDTH 5 /* EQL_B4_GAIN - [15:11] */ 2857*4882a593Smuzhiyun #define WM2200_EQL_B5_GAIN_MASK 0x07C0 /* EQL_B5_GAIN - [10:6] */ 2858*4882a593Smuzhiyun #define WM2200_EQL_B5_GAIN_SHIFT 6 /* EQL_B5_GAIN - [10:6] */ 2859*4882a593Smuzhiyun #define WM2200_EQL_B5_GAIN_WIDTH 5 /* EQL_B5_GAIN - [10:6] */ 2860*4882a593Smuzhiyun 2861*4882a593Smuzhiyun /* 2862*4882a593Smuzhiyun * R2306 (0x902) - EQL_3 2863*4882a593Smuzhiyun */ 2864*4882a593Smuzhiyun #define WM2200_EQL_B1_A_MASK 0xFFFF /* EQL_B1_A - [15:0] */ 2865*4882a593Smuzhiyun #define WM2200_EQL_B1_A_SHIFT 0 /* EQL_B1_A - [15:0] */ 2866*4882a593Smuzhiyun #define WM2200_EQL_B1_A_WIDTH 16 /* EQL_B1_A - [15:0] */ 2867*4882a593Smuzhiyun 2868*4882a593Smuzhiyun /* 2869*4882a593Smuzhiyun * R2307 (0x903) - EQL_4 2870*4882a593Smuzhiyun */ 2871*4882a593Smuzhiyun #define WM2200_EQL_B1_B_MASK 0xFFFF /* EQL_B1_B - [15:0] */ 2872*4882a593Smuzhiyun #define WM2200_EQL_B1_B_SHIFT 0 /* EQL_B1_B - [15:0] */ 2873*4882a593Smuzhiyun #define WM2200_EQL_B1_B_WIDTH 16 /* EQL_B1_B - [15:0] */ 2874*4882a593Smuzhiyun 2875*4882a593Smuzhiyun /* 2876*4882a593Smuzhiyun * R2308 (0x904) - EQL_5 2877*4882a593Smuzhiyun */ 2878*4882a593Smuzhiyun #define WM2200_EQL_B1_PG_MASK 0xFFFF /* EQL_B1_PG - [15:0] */ 2879*4882a593Smuzhiyun #define WM2200_EQL_B1_PG_SHIFT 0 /* EQL_B1_PG - [15:0] */ 2880*4882a593Smuzhiyun #define WM2200_EQL_B1_PG_WIDTH 16 /* EQL_B1_PG - [15:0] */ 2881*4882a593Smuzhiyun 2882*4882a593Smuzhiyun /* 2883*4882a593Smuzhiyun * R2309 (0x905) - EQL_6 2884*4882a593Smuzhiyun */ 2885*4882a593Smuzhiyun #define WM2200_EQL_B2_A_MASK 0xFFFF /* EQL_B2_A - [15:0] */ 2886*4882a593Smuzhiyun #define WM2200_EQL_B2_A_SHIFT 0 /* EQL_B2_A - [15:0] */ 2887*4882a593Smuzhiyun #define WM2200_EQL_B2_A_WIDTH 16 /* EQL_B2_A - [15:0] */ 2888*4882a593Smuzhiyun 2889*4882a593Smuzhiyun /* 2890*4882a593Smuzhiyun * R2310 (0x906) - EQL_7 2891*4882a593Smuzhiyun */ 2892*4882a593Smuzhiyun #define WM2200_EQL_B2_B_MASK 0xFFFF /* EQL_B2_B - [15:0] */ 2893*4882a593Smuzhiyun #define WM2200_EQL_B2_B_SHIFT 0 /* EQL_B2_B - [15:0] */ 2894*4882a593Smuzhiyun #define WM2200_EQL_B2_B_WIDTH 16 /* EQL_B2_B - [15:0] */ 2895*4882a593Smuzhiyun 2896*4882a593Smuzhiyun /* 2897*4882a593Smuzhiyun * R2311 (0x907) - EQL_8 2898*4882a593Smuzhiyun */ 2899*4882a593Smuzhiyun #define WM2200_EQL_B2_C_MASK 0xFFFF /* EQL_B2_C - [15:0] */ 2900*4882a593Smuzhiyun #define WM2200_EQL_B2_C_SHIFT 0 /* EQL_B2_C - [15:0] */ 2901*4882a593Smuzhiyun #define WM2200_EQL_B2_C_WIDTH 16 /* EQL_B2_C - [15:0] */ 2902*4882a593Smuzhiyun 2903*4882a593Smuzhiyun /* 2904*4882a593Smuzhiyun * R2312 (0x908) - EQL_9 2905*4882a593Smuzhiyun */ 2906*4882a593Smuzhiyun #define WM2200_EQL_B2_PG_MASK 0xFFFF /* EQL_B2_PG - [15:0] */ 2907*4882a593Smuzhiyun #define WM2200_EQL_B2_PG_SHIFT 0 /* EQL_B2_PG - [15:0] */ 2908*4882a593Smuzhiyun #define WM2200_EQL_B2_PG_WIDTH 16 /* EQL_B2_PG - [15:0] */ 2909*4882a593Smuzhiyun 2910*4882a593Smuzhiyun /* 2911*4882a593Smuzhiyun * R2313 (0x909) - EQL_10 2912*4882a593Smuzhiyun */ 2913*4882a593Smuzhiyun #define WM2200_EQL_B3_A_MASK 0xFFFF /* EQL_B3_A - [15:0] */ 2914*4882a593Smuzhiyun #define WM2200_EQL_B3_A_SHIFT 0 /* EQL_B3_A - [15:0] */ 2915*4882a593Smuzhiyun #define WM2200_EQL_B3_A_WIDTH 16 /* EQL_B3_A - [15:0] */ 2916*4882a593Smuzhiyun 2917*4882a593Smuzhiyun /* 2918*4882a593Smuzhiyun * R2314 (0x90A) - EQL_11 2919*4882a593Smuzhiyun */ 2920*4882a593Smuzhiyun #define WM2200_EQL_B3_B_MASK 0xFFFF /* EQL_B3_B - [15:0] */ 2921*4882a593Smuzhiyun #define WM2200_EQL_B3_B_SHIFT 0 /* EQL_B3_B - [15:0] */ 2922*4882a593Smuzhiyun #define WM2200_EQL_B3_B_WIDTH 16 /* EQL_B3_B - [15:0] */ 2923*4882a593Smuzhiyun 2924*4882a593Smuzhiyun /* 2925*4882a593Smuzhiyun * R2315 (0x90B) - EQL_12 2926*4882a593Smuzhiyun */ 2927*4882a593Smuzhiyun #define WM2200_EQL_B3_C_MASK 0xFFFF /* EQL_B3_C - [15:0] */ 2928*4882a593Smuzhiyun #define WM2200_EQL_B3_C_SHIFT 0 /* EQL_B3_C - [15:0] */ 2929*4882a593Smuzhiyun #define WM2200_EQL_B3_C_WIDTH 16 /* EQL_B3_C - [15:0] */ 2930*4882a593Smuzhiyun 2931*4882a593Smuzhiyun /* 2932*4882a593Smuzhiyun * R2316 (0x90C) - EQL_13 2933*4882a593Smuzhiyun */ 2934*4882a593Smuzhiyun #define WM2200_EQL_B3_PG_MASK 0xFFFF /* EQL_B3_PG - [15:0] */ 2935*4882a593Smuzhiyun #define WM2200_EQL_B3_PG_SHIFT 0 /* EQL_B3_PG - [15:0] */ 2936*4882a593Smuzhiyun #define WM2200_EQL_B3_PG_WIDTH 16 /* EQL_B3_PG - [15:0] */ 2937*4882a593Smuzhiyun 2938*4882a593Smuzhiyun /* 2939*4882a593Smuzhiyun * R2317 (0x90D) - EQL_14 2940*4882a593Smuzhiyun */ 2941*4882a593Smuzhiyun #define WM2200_EQL_B4_A_MASK 0xFFFF /* EQL_B4_A - [15:0] */ 2942*4882a593Smuzhiyun #define WM2200_EQL_B4_A_SHIFT 0 /* EQL_B4_A - [15:0] */ 2943*4882a593Smuzhiyun #define WM2200_EQL_B4_A_WIDTH 16 /* EQL_B4_A - [15:0] */ 2944*4882a593Smuzhiyun 2945*4882a593Smuzhiyun /* 2946*4882a593Smuzhiyun * R2318 (0x90E) - EQL_15 2947*4882a593Smuzhiyun */ 2948*4882a593Smuzhiyun #define WM2200_EQL_B4_B_MASK 0xFFFF /* EQL_B4_B - [15:0] */ 2949*4882a593Smuzhiyun #define WM2200_EQL_B4_B_SHIFT 0 /* EQL_B4_B - [15:0] */ 2950*4882a593Smuzhiyun #define WM2200_EQL_B4_B_WIDTH 16 /* EQL_B4_B - [15:0] */ 2951*4882a593Smuzhiyun 2952*4882a593Smuzhiyun /* 2953*4882a593Smuzhiyun * R2319 (0x90F) - EQL_16 2954*4882a593Smuzhiyun */ 2955*4882a593Smuzhiyun #define WM2200_EQL_B4_C_MASK 0xFFFF /* EQL_B4_C - [15:0] */ 2956*4882a593Smuzhiyun #define WM2200_EQL_B4_C_SHIFT 0 /* EQL_B4_C - [15:0] */ 2957*4882a593Smuzhiyun #define WM2200_EQL_B4_C_WIDTH 16 /* EQL_B4_C - [15:0] */ 2958*4882a593Smuzhiyun 2959*4882a593Smuzhiyun /* 2960*4882a593Smuzhiyun * R2320 (0x910) - EQL_17 2961*4882a593Smuzhiyun */ 2962*4882a593Smuzhiyun #define WM2200_EQL_B4_PG_MASK 0xFFFF /* EQL_B4_PG - [15:0] */ 2963*4882a593Smuzhiyun #define WM2200_EQL_B4_PG_SHIFT 0 /* EQL_B4_PG - [15:0] */ 2964*4882a593Smuzhiyun #define WM2200_EQL_B4_PG_WIDTH 16 /* EQL_B4_PG - [15:0] */ 2965*4882a593Smuzhiyun 2966*4882a593Smuzhiyun /* 2967*4882a593Smuzhiyun * R2321 (0x911) - EQL_18 2968*4882a593Smuzhiyun */ 2969*4882a593Smuzhiyun #define WM2200_EQL_B5_A_MASK 0xFFFF /* EQL_B5_A - [15:0] */ 2970*4882a593Smuzhiyun #define WM2200_EQL_B5_A_SHIFT 0 /* EQL_B5_A - [15:0] */ 2971*4882a593Smuzhiyun #define WM2200_EQL_B5_A_WIDTH 16 /* EQL_B5_A - [15:0] */ 2972*4882a593Smuzhiyun 2973*4882a593Smuzhiyun /* 2974*4882a593Smuzhiyun * R2322 (0x912) - EQL_19 2975*4882a593Smuzhiyun */ 2976*4882a593Smuzhiyun #define WM2200_EQL_B5_B_MASK 0xFFFF /* EQL_B5_B - [15:0] */ 2977*4882a593Smuzhiyun #define WM2200_EQL_B5_B_SHIFT 0 /* EQL_B5_B - [15:0] */ 2978*4882a593Smuzhiyun #define WM2200_EQL_B5_B_WIDTH 16 /* EQL_B5_B - [15:0] */ 2979*4882a593Smuzhiyun 2980*4882a593Smuzhiyun /* 2981*4882a593Smuzhiyun * R2323 (0x913) - EQL_20 2982*4882a593Smuzhiyun */ 2983*4882a593Smuzhiyun #define WM2200_EQL_B5_PG_MASK 0xFFFF /* EQL_B5_PG - [15:0] */ 2984*4882a593Smuzhiyun #define WM2200_EQL_B5_PG_SHIFT 0 /* EQL_B5_PG - [15:0] */ 2985*4882a593Smuzhiyun #define WM2200_EQL_B5_PG_WIDTH 16 /* EQL_B5_PG - [15:0] */ 2986*4882a593Smuzhiyun 2987*4882a593Smuzhiyun /* 2988*4882a593Smuzhiyun * R2326 (0x916) - EQR_1 2989*4882a593Smuzhiyun */ 2990*4882a593Smuzhiyun #define WM2200_EQR_B1_GAIN_MASK 0xF800 /* EQR_B1_GAIN - [15:11] */ 2991*4882a593Smuzhiyun #define WM2200_EQR_B1_GAIN_SHIFT 11 /* EQR_B1_GAIN - [15:11] */ 2992*4882a593Smuzhiyun #define WM2200_EQR_B1_GAIN_WIDTH 5 /* EQR_B1_GAIN - [15:11] */ 2993*4882a593Smuzhiyun #define WM2200_EQR_B2_GAIN_MASK 0x07C0 /* EQR_B2_GAIN - [10:6] */ 2994*4882a593Smuzhiyun #define WM2200_EQR_B2_GAIN_SHIFT 6 /* EQR_B2_GAIN - [10:6] */ 2995*4882a593Smuzhiyun #define WM2200_EQR_B2_GAIN_WIDTH 5 /* EQR_B2_GAIN - [10:6] */ 2996*4882a593Smuzhiyun #define WM2200_EQR_B3_GAIN_MASK 0x003E /* EQR_B3_GAIN - [5:1] */ 2997*4882a593Smuzhiyun #define WM2200_EQR_B3_GAIN_SHIFT 1 /* EQR_B3_GAIN - [5:1] */ 2998*4882a593Smuzhiyun #define WM2200_EQR_B3_GAIN_WIDTH 5 /* EQR_B3_GAIN - [5:1] */ 2999*4882a593Smuzhiyun #define WM2200_EQR_ENA 0x0001 /* EQR_ENA */ 3000*4882a593Smuzhiyun #define WM2200_EQR_ENA_MASK 0x0001 /* EQR_ENA */ 3001*4882a593Smuzhiyun #define WM2200_EQR_ENA_SHIFT 0 /* EQR_ENA */ 3002*4882a593Smuzhiyun #define WM2200_EQR_ENA_WIDTH 1 /* EQR_ENA */ 3003*4882a593Smuzhiyun 3004*4882a593Smuzhiyun /* 3005*4882a593Smuzhiyun * R2327 (0x917) - EQR_2 3006*4882a593Smuzhiyun */ 3007*4882a593Smuzhiyun #define WM2200_EQR_B4_GAIN_MASK 0xF800 /* EQR_B4_GAIN - [15:11] */ 3008*4882a593Smuzhiyun #define WM2200_EQR_B4_GAIN_SHIFT 11 /* EQR_B4_GAIN - [15:11] */ 3009*4882a593Smuzhiyun #define WM2200_EQR_B4_GAIN_WIDTH 5 /* EQR_B4_GAIN - [15:11] */ 3010*4882a593Smuzhiyun #define WM2200_EQR_B5_GAIN_MASK 0x07C0 /* EQR_B5_GAIN - [10:6] */ 3011*4882a593Smuzhiyun #define WM2200_EQR_B5_GAIN_SHIFT 6 /* EQR_B5_GAIN - [10:6] */ 3012*4882a593Smuzhiyun #define WM2200_EQR_B5_GAIN_WIDTH 5 /* EQR_B5_GAIN - [10:6] */ 3013*4882a593Smuzhiyun 3014*4882a593Smuzhiyun /* 3015*4882a593Smuzhiyun * R2328 (0x918) - EQR_3 3016*4882a593Smuzhiyun */ 3017*4882a593Smuzhiyun #define WM2200_EQR_B1_A_MASK 0xFFFF /* EQR_B1_A - [15:0] */ 3018*4882a593Smuzhiyun #define WM2200_EQR_B1_A_SHIFT 0 /* EQR_B1_A - [15:0] */ 3019*4882a593Smuzhiyun #define WM2200_EQR_B1_A_WIDTH 16 /* EQR_B1_A - [15:0] */ 3020*4882a593Smuzhiyun 3021*4882a593Smuzhiyun /* 3022*4882a593Smuzhiyun * R2329 (0x919) - EQR_4 3023*4882a593Smuzhiyun */ 3024*4882a593Smuzhiyun #define WM2200_EQR_B1_B_MASK 0xFFFF /* EQR_B1_B - [15:0] */ 3025*4882a593Smuzhiyun #define WM2200_EQR_B1_B_SHIFT 0 /* EQR_B1_B - [15:0] */ 3026*4882a593Smuzhiyun #define WM2200_EQR_B1_B_WIDTH 16 /* EQR_B1_B - [15:0] */ 3027*4882a593Smuzhiyun 3028*4882a593Smuzhiyun /* 3029*4882a593Smuzhiyun * R2330 (0x91A) - EQR_5 3030*4882a593Smuzhiyun */ 3031*4882a593Smuzhiyun #define WM2200_EQR_B1_PG_MASK 0xFFFF /* EQR_B1_PG - [15:0] */ 3032*4882a593Smuzhiyun #define WM2200_EQR_B1_PG_SHIFT 0 /* EQR_B1_PG - [15:0] */ 3033*4882a593Smuzhiyun #define WM2200_EQR_B1_PG_WIDTH 16 /* EQR_B1_PG - [15:0] */ 3034*4882a593Smuzhiyun 3035*4882a593Smuzhiyun /* 3036*4882a593Smuzhiyun * R2331 (0x91B) - EQR_6 3037*4882a593Smuzhiyun */ 3038*4882a593Smuzhiyun #define WM2200_EQR_B2_A_MASK 0xFFFF /* EQR_B2_A - [15:0] */ 3039*4882a593Smuzhiyun #define WM2200_EQR_B2_A_SHIFT 0 /* EQR_B2_A - [15:0] */ 3040*4882a593Smuzhiyun #define WM2200_EQR_B2_A_WIDTH 16 /* EQR_B2_A - [15:0] */ 3041*4882a593Smuzhiyun 3042*4882a593Smuzhiyun /* 3043*4882a593Smuzhiyun * R2332 (0x91C) - EQR_7 3044*4882a593Smuzhiyun */ 3045*4882a593Smuzhiyun #define WM2200_EQR_B2_B_MASK 0xFFFF /* EQR_B2_B - [15:0] */ 3046*4882a593Smuzhiyun #define WM2200_EQR_B2_B_SHIFT 0 /* EQR_B2_B - [15:0] */ 3047*4882a593Smuzhiyun #define WM2200_EQR_B2_B_WIDTH 16 /* EQR_B2_B - [15:0] */ 3048*4882a593Smuzhiyun 3049*4882a593Smuzhiyun /* 3050*4882a593Smuzhiyun * R2333 (0x91D) - EQR_8 3051*4882a593Smuzhiyun */ 3052*4882a593Smuzhiyun #define WM2200_EQR_B2_C_MASK 0xFFFF /* EQR_B2_C - [15:0] */ 3053*4882a593Smuzhiyun #define WM2200_EQR_B2_C_SHIFT 0 /* EQR_B2_C - [15:0] */ 3054*4882a593Smuzhiyun #define WM2200_EQR_B2_C_WIDTH 16 /* EQR_B2_C - [15:0] */ 3055*4882a593Smuzhiyun 3056*4882a593Smuzhiyun /* 3057*4882a593Smuzhiyun * R2334 (0x91E) - EQR_9 3058*4882a593Smuzhiyun */ 3059*4882a593Smuzhiyun #define WM2200_EQR_B2_PG_MASK 0xFFFF /* EQR_B2_PG - [15:0] */ 3060*4882a593Smuzhiyun #define WM2200_EQR_B2_PG_SHIFT 0 /* EQR_B2_PG - [15:0] */ 3061*4882a593Smuzhiyun #define WM2200_EQR_B2_PG_WIDTH 16 /* EQR_B2_PG - [15:0] */ 3062*4882a593Smuzhiyun 3063*4882a593Smuzhiyun /* 3064*4882a593Smuzhiyun * R2335 (0x91F) - EQR_10 3065*4882a593Smuzhiyun */ 3066*4882a593Smuzhiyun #define WM2200_EQR_B3_A_MASK 0xFFFF /* EQR_B3_A - [15:0] */ 3067*4882a593Smuzhiyun #define WM2200_EQR_B3_A_SHIFT 0 /* EQR_B3_A - [15:0] */ 3068*4882a593Smuzhiyun #define WM2200_EQR_B3_A_WIDTH 16 /* EQR_B3_A - [15:0] */ 3069*4882a593Smuzhiyun 3070*4882a593Smuzhiyun /* 3071*4882a593Smuzhiyun * R2336 (0x920) - EQR_11 3072*4882a593Smuzhiyun */ 3073*4882a593Smuzhiyun #define WM2200_EQR_B3_B_MASK 0xFFFF /* EQR_B3_B - [15:0] */ 3074*4882a593Smuzhiyun #define WM2200_EQR_B3_B_SHIFT 0 /* EQR_B3_B - [15:0] */ 3075*4882a593Smuzhiyun #define WM2200_EQR_B3_B_WIDTH 16 /* EQR_B3_B - [15:0] */ 3076*4882a593Smuzhiyun 3077*4882a593Smuzhiyun /* 3078*4882a593Smuzhiyun * R2337 (0x921) - EQR_12 3079*4882a593Smuzhiyun */ 3080*4882a593Smuzhiyun #define WM2200_EQR_B3_C_MASK 0xFFFF /* EQR_B3_C - [15:0] */ 3081*4882a593Smuzhiyun #define WM2200_EQR_B3_C_SHIFT 0 /* EQR_B3_C - [15:0] */ 3082*4882a593Smuzhiyun #define WM2200_EQR_B3_C_WIDTH 16 /* EQR_B3_C - [15:0] */ 3083*4882a593Smuzhiyun 3084*4882a593Smuzhiyun /* 3085*4882a593Smuzhiyun * R2338 (0x922) - EQR_13 3086*4882a593Smuzhiyun */ 3087*4882a593Smuzhiyun #define WM2200_EQR_B3_PG_MASK 0xFFFF /* EQR_B3_PG - [15:0] */ 3088*4882a593Smuzhiyun #define WM2200_EQR_B3_PG_SHIFT 0 /* EQR_B3_PG - [15:0] */ 3089*4882a593Smuzhiyun #define WM2200_EQR_B3_PG_WIDTH 16 /* EQR_B3_PG - [15:0] */ 3090*4882a593Smuzhiyun 3091*4882a593Smuzhiyun /* 3092*4882a593Smuzhiyun * R2339 (0x923) - EQR_14 3093*4882a593Smuzhiyun */ 3094*4882a593Smuzhiyun #define WM2200_EQR_B4_A_MASK 0xFFFF /* EQR_B4_A - [15:0] */ 3095*4882a593Smuzhiyun #define WM2200_EQR_B4_A_SHIFT 0 /* EQR_B4_A - [15:0] */ 3096*4882a593Smuzhiyun #define WM2200_EQR_B4_A_WIDTH 16 /* EQR_B4_A - [15:0] */ 3097*4882a593Smuzhiyun 3098*4882a593Smuzhiyun /* 3099*4882a593Smuzhiyun * R2340 (0x924) - EQR_15 3100*4882a593Smuzhiyun */ 3101*4882a593Smuzhiyun #define WM2200_EQR_B4_B_MASK 0xFFFF /* EQR_B4_B - [15:0] */ 3102*4882a593Smuzhiyun #define WM2200_EQR_B4_B_SHIFT 0 /* EQR_B4_B - [15:0] */ 3103*4882a593Smuzhiyun #define WM2200_EQR_B4_B_WIDTH 16 /* EQR_B4_B - [15:0] */ 3104*4882a593Smuzhiyun 3105*4882a593Smuzhiyun /* 3106*4882a593Smuzhiyun * R2341 (0x925) - EQR_16 3107*4882a593Smuzhiyun */ 3108*4882a593Smuzhiyun #define WM2200_EQR_B4_C_MASK 0xFFFF /* EQR_B4_C - [15:0] */ 3109*4882a593Smuzhiyun #define WM2200_EQR_B4_C_SHIFT 0 /* EQR_B4_C - [15:0] */ 3110*4882a593Smuzhiyun #define WM2200_EQR_B4_C_WIDTH 16 /* EQR_B4_C - [15:0] */ 3111*4882a593Smuzhiyun 3112*4882a593Smuzhiyun /* 3113*4882a593Smuzhiyun * R2342 (0x926) - EQR_17 3114*4882a593Smuzhiyun */ 3115*4882a593Smuzhiyun #define WM2200_EQR_B4_PG_MASK 0xFFFF /* EQR_B4_PG - [15:0] */ 3116*4882a593Smuzhiyun #define WM2200_EQR_B4_PG_SHIFT 0 /* EQR_B4_PG - [15:0] */ 3117*4882a593Smuzhiyun #define WM2200_EQR_B4_PG_WIDTH 16 /* EQR_B4_PG - [15:0] */ 3118*4882a593Smuzhiyun 3119*4882a593Smuzhiyun /* 3120*4882a593Smuzhiyun * R2343 (0x927) - EQR_18 3121*4882a593Smuzhiyun */ 3122*4882a593Smuzhiyun #define WM2200_EQR_B5_A_MASK 0xFFFF /* EQR_B5_A - [15:0] */ 3123*4882a593Smuzhiyun #define WM2200_EQR_B5_A_SHIFT 0 /* EQR_B5_A - [15:0] */ 3124*4882a593Smuzhiyun #define WM2200_EQR_B5_A_WIDTH 16 /* EQR_B5_A - [15:0] */ 3125*4882a593Smuzhiyun 3126*4882a593Smuzhiyun /* 3127*4882a593Smuzhiyun * R2344 (0x928) - EQR_19 3128*4882a593Smuzhiyun */ 3129*4882a593Smuzhiyun #define WM2200_EQR_B5_B_MASK 0xFFFF /* EQR_B5_B - [15:0] */ 3130*4882a593Smuzhiyun #define WM2200_EQR_B5_B_SHIFT 0 /* EQR_B5_B - [15:0] */ 3131*4882a593Smuzhiyun #define WM2200_EQR_B5_B_WIDTH 16 /* EQR_B5_B - [15:0] */ 3132*4882a593Smuzhiyun 3133*4882a593Smuzhiyun /* 3134*4882a593Smuzhiyun * R2345 (0x929) - EQR_20 3135*4882a593Smuzhiyun */ 3136*4882a593Smuzhiyun #define WM2200_EQR_B5_PG_MASK 0xFFFF /* EQR_B5_PG - [15:0] */ 3137*4882a593Smuzhiyun #define WM2200_EQR_B5_PG_SHIFT 0 /* EQR_B5_PG - [15:0] */ 3138*4882a593Smuzhiyun #define WM2200_EQR_B5_PG_WIDTH 16 /* EQR_B5_PG - [15:0] */ 3139*4882a593Smuzhiyun 3140*4882a593Smuzhiyun /* 3141*4882a593Smuzhiyun * R2366 (0x93E) - HPLPF1_1 3142*4882a593Smuzhiyun */ 3143*4882a593Smuzhiyun #define WM2200_LHPF1_MODE 0x0002 /* LHPF1_MODE */ 3144*4882a593Smuzhiyun #define WM2200_LHPF1_MODE_MASK 0x0002 /* LHPF1_MODE */ 3145*4882a593Smuzhiyun #define WM2200_LHPF1_MODE_SHIFT 1 /* LHPF1_MODE */ 3146*4882a593Smuzhiyun #define WM2200_LHPF1_MODE_WIDTH 1 /* LHPF1_MODE */ 3147*4882a593Smuzhiyun #define WM2200_LHPF1_ENA 0x0001 /* LHPF1_ENA */ 3148*4882a593Smuzhiyun #define WM2200_LHPF1_ENA_MASK 0x0001 /* LHPF1_ENA */ 3149*4882a593Smuzhiyun #define WM2200_LHPF1_ENA_SHIFT 0 /* LHPF1_ENA */ 3150*4882a593Smuzhiyun #define WM2200_LHPF1_ENA_WIDTH 1 /* LHPF1_ENA */ 3151*4882a593Smuzhiyun 3152*4882a593Smuzhiyun /* 3153*4882a593Smuzhiyun * R2367 (0x93F) - HPLPF1_2 3154*4882a593Smuzhiyun */ 3155*4882a593Smuzhiyun #define WM2200_LHPF1_COEFF_MASK 0xFFFF /* LHPF1_COEFF - [15:0] */ 3156*4882a593Smuzhiyun #define WM2200_LHPF1_COEFF_SHIFT 0 /* LHPF1_COEFF - [15:0] */ 3157*4882a593Smuzhiyun #define WM2200_LHPF1_COEFF_WIDTH 16 /* LHPF1_COEFF - [15:0] */ 3158*4882a593Smuzhiyun 3159*4882a593Smuzhiyun /* 3160*4882a593Smuzhiyun * R2370 (0x942) - HPLPF2_1 3161*4882a593Smuzhiyun */ 3162*4882a593Smuzhiyun #define WM2200_LHPF2_MODE 0x0002 /* LHPF2_MODE */ 3163*4882a593Smuzhiyun #define WM2200_LHPF2_MODE_MASK 0x0002 /* LHPF2_MODE */ 3164*4882a593Smuzhiyun #define WM2200_LHPF2_MODE_SHIFT 1 /* LHPF2_MODE */ 3165*4882a593Smuzhiyun #define WM2200_LHPF2_MODE_WIDTH 1 /* LHPF2_MODE */ 3166*4882a593Smuzhiyun #define WM2200_LHPF2_ENA 0x0001 /* LHPF2_ENA */ 3167*4882a593Smuzhiyun #define WM2200_LHPF2_ENA_MASK 0x0001 /* LHPF2_ENA */ 3168*4882a593Smuzhiyun #define WM2200_LHPF2_ENA_SHIFT 0 /* LHPF2_ENA */ 3169*4882a593Smuzhiyun #define WM2200_LHPF2_ENA_WIDTH 1 /* LHPF2_ENA */ 3170*4882a593Smuzhiyun 3171*4882a593Smuzhiyun /* 3172*4882a593Smuzhiyun * R2371 (0x943) - HPLPF2_2 3173*4882a593Smuzhiyun */ 3174*4882a593Smuzhiyun #define WM2200_LHPF2_COEFF_MASK 0xFFFF /* LHPF2_COEFF - [15:0] */ 3175*4882a593Smuzhiyun #define WM2200_LHPF2_COEFF_SHIFT 0 /* LHPF2_COEFF - [15:0] */ 3176*4882a593Smuzhiyun #define WM2200_LHPF2_COEFF_WIDTH 16 /* LHPF2_COEFF - [15:0] */ 3177*4882a593Smuzhiyun 3178*4882a593Smuzhiyun /* 3179*4882a593Smuzhiyun * R2560 (0xA00) - DSP1 Control 1 3180*4882a593Smuzhiyun */ 3181*4882a593Smuzhiyun #define WM2200_DSP1_RW_SEQUENCE_ENA 0x0001 /* DSP1_RW_SEQUENCE_ENA */ 3182*4882a593Smuzhiyun #define WM2200_DSP1_RW_SEQUENCE_ENA_MASK 0x0001 /* DSP1_RW_SEQUENCE_ENA */ 3183*4882a593Smuzhiyun #define WM2200_DSP1_RW_SEQUENCE_ENA_SHIFT 0 /* DSP1_RW_SEQUENCE_ENA */ 3184*4882a593Smuzhiyun #define WM2200_DSP1_RW_SEQUENCE_ENA_WIDTH 1 /* DSP1_RW_SEQUENCE_ENA */ 3185*4882a593Smuzhiyun 3186*4882a593Smuzhiyun /* 3187*4882a593Smuzhiyun * R2562 (0xA02) - DSP1 Control 2 3188*4882a593Smuzhiyun */ 3189*4882a593Smuzhiyun #define WM2200_DSP1_PAGE_BASE_PM_0_MASK 0xFF00 /* DSP1_PAGE_BASE_PM - [15:8] */ 3190*4882a593Smuzhiyun #define WM2200_DSP1_PAGE_BASE_PM_0_SHIFT 8 /* DSP1_PAGE_BASE_PM - [15:8] */ 3191*4882a593Smuzhiyun #define WM2200_DSP1_PAGE_BASE_PM_0_WIDTH 8 /* DSP1_PAGE_BASE_PM - [15:8] */ 3192*4882a593Smuzhiyun 3193*4882a593Smuzhiyun /* 3194*4882a593Smuzhiyun * R2563 (0xA03) - DSP1 Control 3 3195*4882a593Smuzhiyun */ 3196*4882a593Smuzhiyun #define WM2200_DSP1_PAGE_BASE_DM_0_MASK 0xFF00 /* DSP1_PAGE_BASE_DM - [15:8] */ 3197*4882a593Smuzhiyun #define WM2200_DSP1_PAGE_BASE_DM_0_SHIFT 8 /* DSP1_PAGE_BASE_DM - [15:8] */ 3198*4882a593Smuzhiyun #define WM2200_DSP1_PAGE_BASE_DM_0_WIDTH 8 /* DSP1_PAGE_BASE_DM - [15:8] */ 3199*4882a593Smuzhiyun 3200*4882a593Smuzhiyun /* 3201*4882a593Smuzhiyun * R2564 (0xA04) - DSP1 Control 4 3202*4882a593Smuzhiyun */ 3203*4882a593Smuzhiyun #define WM2200_DSP1_PAGE_BASE_ZM_0_MASK 0xFF00 /* DSP1_PAGE_BASE_ZM - [15:8] */ 3204*4882a593Smuzhiyun #define WM2200_DSP1_PAGE_BASE_ZM_0_SHIFT 8 /* DSP1_PAGE_BASE_ZM - [15:8] */ 3205*4882a593Smuzhiyun #define WM2200_DSP1_PAGE_BASE_ZM_0_WIDTH 8 /* DSP1_PAGE_BASE_ZM - [15:8] */ 3206*4882a593Smuzhiyun 3207*4882a593Smuzhiyun /* 3208*4882a593Smuzhiyun * R2566 (0xA06) - DSP1 Control 5 3209*4882a593Smuzhiyun */ 3210*4882a593Smuzhiyun #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_0_MASK 0x3FFF /* DSP1_START_ADDRESS_WDMA_BUFFER_0 - [13:0] */ 3211*4882a593Smuzhiyun #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_0_SHIFT 0 /* DSP1_START_ADDRESS_WDMA_BUFFER_0 - [13:0] */ 3212*4882a593Smuzhiyun #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_0_WIDTH 14 /* DSP1_START_ADDRESS_WDMA_BUFFER_0 - [13:0] */ 3213*4882a593Smuzhiyun 3214*4882a593Smuzhiyun /* 3215*4882a593Smuzhiyun * R2567 (0xA07) - DSP1 Control 6 3216*4882a593Smuzhiyun */ 3217*4882a593Smuzhiyun #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_1_MASK 0x3FFF /* DSP1_START_ADDRESS_WDMA_BUFFER_1 - [13:0] */ 3218*4882a593Smuzhiyun #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_1_SHIFT 0 /* DSP1_START_ADDRESS_WDMA_BUFFER_1 - [13:0] */ 3219*4882a593Smuzhiyun #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_1_WIDTH 14 /* DSP1_START_ADDRESS_WDMA_BUFFER_1 - [13:0] */ 3220*4882a593Smuzhiyun 3221*4882a593Smuzhiyun /* 3222*4882a593Smuzhiyun * R2568 (0xA08) - DSP1 Control 7 3223*4882a593Smuzhiyun */ 3224*4882a593Smuzhiyun #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_2_MASK 0x3FFF /* DSP1_START_ADDRESS_WDMA_BUFFER_2 - [13:0] */ 3225*4882a593Smuzhiyun #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_2_SHIFT 0 /* DSP1_START_ADDRESS_WDMA_BUFFER_2 - [13:0] */ 3226*4882a593Smuzhiyun #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_2_WIDTH 14 /* DSP1_START_ADDRESS_WDMA_BUFFER_2 - [13:0] */ 3227*4882a593Smuzhiyun 3228*4882a593Smuzhiyun /* 3229*4882a593Smuzhiyun * R2569 (0xA09) - DSP1 Control 8 3230*4882a593Smuzhiyun */ 3231*4882a593Smuzhiyun #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_3_MASK 0x3FFF /* DSP1_START_ADDRESS_WDMA_BUFFER_3 - [13:0] */ 3232*4882a593Smuzhiyun #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_3_SHIFT 0 /* DSP1_START_ADDRESS_WDMA_BUFFER_3 - [13:0] */ 3233*4882a593Smuzhiyun #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_3_WIDTH 14 /* DSP1_START_ADDRESS_WDMA_BUFFER_3 - [13:0] */ 3234*4882a593Smuzhiyun 3235*4882a593Smuzhiyun /* 3236*4882a593Smuzhiyun * R2570 (0xA0A) - DSP1 Control 9 3237*4882a593Smuzhiyun */ 3238*4882a593Smuzhiyun #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_4_MASK 0x3FFF /* DSP1_START_ADDRESS_WDMA_BUFFER_4 - [13:0] */ 3239*4882a593Smuzhiyun #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_4_SHIFT 0 /* DSP1_START_ADDRESS_WDMA_BUFFER_4 - [13:0] */ 3240*4882a593Smuzhiyun #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_4_WIDTH 14 /* DSP1_START_ADDRESS_WDMA_BUFFER_4 - [13:0] */ 3241*4882a593Smuzhiyun 3242*4882a593Smuzhiyun /* 3243*4882a593Smuzhiyun * R2571 (0xA0B) - DSP1 Control 10 3244*4882a593Smuzhiyun */ 3245*4882a593Smuzhiyun #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_5_MASK 0x3FFF /* DSP1_START_ADDRESS_WDMA_BUFFER_5 - [13:0] */ 3246*4882a593Smuzhiyun #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_5_SHIFT 0 /* DSP1_START_ADDRESS_WDMA_BUFFER_5 - [13:0] */ 3247*4882a593Smuzhiyun #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_5_WIDTH 14 /* DSP1_START_ADDRESS_WDMA_BUFFER_5 - [13:0] */ 3248*4882a593Smuzhiyun 3249*4882a593Smuzhiyun /* 3250*4882a593Smuzhiyun * R2572 (0xA0C) - DSP1 Control 11 3251*4882a593Smuzhiyun */ 3252*4882a593Smuzhiyun #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_6_MASK 0x3FFF /* DSP1_START_ADDRESS_WDMA_BUFFER_6 - [13:0] */ 3253*4882a593Smuzhiyun #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_6_SHIFT 0 /* DSP1_START_ADDRESS_WDMA_BUFFER_6 - [13:0] */ 3254*4882a593Smuzhiyun #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_6_WIDTH 14 /* DSP1_START_ADDRESS_WDMA_BUFFER_6 - [13:0] */ 3255*4882a593Smuzhiyun 3256*4882a593Smuzhiyun /* 3257*4882a593Smuzhiyun * R2573 (0xA0D) - DSP1 Control 12 3258*4882a593Smuzhiyun */ 3259*4882a593Smuzhiyun #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_7_MASK 0x3FFF /* DSP1_START_ADDRESS_WDMA_BUFFER_7 - [13:0] */ 3260*4882a593Smuzhiyun #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_7_SHIFT 0 /* DSP1_START_ADDRESS_WDMA_BUFFER_7 - [13:0] */ 3261*4882a593Smuzhiyun #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_7_WIDTH 14 /* DSP1_START_ADDRESS_WDMA_BUFFER_7 - [13:0] */ 3262*4882a593Smuzhiyun 3263*4882a593Smuzhiyun /* 3264*4882a593Smuzhiyun * R2575 (0xA0F) - DSP1 Control 13 3265*4882a593Smuzhiyun */ 3266*4882a593Smuzhiyun #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_0_MASK 0x3FFF /* DSP1_START_ADDRESS_RDMA_BUFFER_0 - [13:0] */ 3267*4882a593Smuzhiyun #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_0_SHIFT 0 /* DSP1_START_ADDRESS_RDMA_BUFFER_0 - [13:0] */ 3268*4882a593Smuzhiyun #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_0_WIDTH 14 /* DSP1_START_ADDRESS_RDMA_BUFFER_0 - [13:0] */ 3269*4882a593Smuzhiyun 3270*4882a593Smuzhiyun /* 3271*4882a593Smuzhiyun * R2576 (0xA10) - DSP1 Control 14 3272*4882a593Smuzhiyun */ 3273*4882a593Smuzhiyun #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_1_MASK 0x3FFF /* DSP1_START_ADDRESS_RDMA_BUFFER_1 - [13:0] */ 3274*4882a593Smuzhiyun #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_1_SHIFT 0 /* DSP1_START_ADDRESS_RDMA_BUFFER_1 - [13:0] */ 3275*4882a593Smuzhiyun #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_1_WIDTH 14 /* DSP1_START_ADDRESS_RDMA_BUFFER_1 - [13:0] */ 3276*4882a593Smuzhiyun 3277*4882a593Smuzhiyun /* 3278*4882a593Smuzhiyun * R2577 (0xA11) - DSP1 Control 15 3279*4882a593Smuzhiyun */ 3280*4882a593Smuzhiyun #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_2_MASK 0x3FFF /* DSP1_START_ADDRESS_RDMA_BUFFER_2 - [13:0] */ 3281*4882a593Smuzhiyun #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_2_SHIFT 0 /* DSP1_START_ADDRESS_RDMA_BUFFER_2 - [13:0] */ 3282*4882a593Smuzhiyun #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_2_WIDTH 14 /* DSP1_START_ADDRESS_RDMA_BUFFER_2 - [13:0] */ 3283*4882a593Smuzhiyun 3284*4882a593Smuzhiyun /* 3285*4882a593Smuzhiyun * R2578 (0xA12) - DSP1 Control 16 3286*4882a593Smuzhiyun */ 3287*4882a593Smuzhiyun #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_3_MASK 0x3FFF /* DSP1_START_ADDRESS_RDMA_BUFFER_3 - [13:0] */ 3288*4882a593Smuzhiyun #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_3_SHIFT 0 /* DSP1_START_ADDRESS_RDMA_BUFFER_3 - [13:0] */ 3289*4882a593Smuzhiyun #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_3_WIDTH 14 /* DSP1_START_ADDRESS_RDMA_BUFFER_3 - [13:0] */ 3290*4882a593Smuzhiyun 3291*4882a593Smuzhiyun /* 3292*4882a593Smuzhiyun * R2579 (0xA13) - DSP1 Control 17 3293*4882a593Smuzhiyun */ 3294*4882a593Smuzhiyun #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_4_MASK 0x3FFF /* DSP1_START_ADDRESS_RDMA_BUFFER_4 - [13:0] */ 3295*4882a593Smuzhiyun #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_4_SHIFT 0 /* DSP1_START_ADDRESS_RDMA_BUFFER_4 - [13:0] */ 3296*4882a593Smuzhiyun #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_4_WIDTH 14 /* DSP1_START_ADDRESS_RDMA_BUFFER_4 - [13:0] */ 3297*4882a593Smuzhiyun 3298*4882a593Smuzhiyun /* 3299*4882a593Smuzhiyun * R2580 (0xA14) - DSP1 Control 18 3300*4882a593Smuzhiyun */ 3301*4882a593Smuzhiyun #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_5_MASK 0x3FFF /* DSP1_START_ADDRESS_RDMA_BUFFER_5 - [13:0] */ 3302*4882a593Smuzhiyun #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_5_SHIFT 0 /* DSP1_START_ADDRESS_RDMA_BUFFER_5 - [13:0] */ 3303*4882a593Smuzhiyun #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_5_WIDTH 14 /* DSP1_START_ADDRESS_RDMA_BUFFER_5 - [13:0] */ 3304*4882a593Smuzhiyun 3305*4882a593Smuzhiyun /* 3306*4882a593Smuzhiyun * R2582 (0xA16) - DSP1 Control 19 3307*4882a593Smuzhiyun */ 3308*4882a593Smuzhiyun #define WM2200_DSP1_WDMA_BUFFER_LENGTH_MASK 0x00FF /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */ 3309*4882a593Smuzhiyun #define WM2200_DSP1_WDMA_BUFFER_LENGTH_SHIFT 0 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */ 3310*4882a593Smuzhiyun #define WM2200_DSP1_WDMA_BUFFER_LENGTH_WIDTH 8 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */ 3311*4882a593Smuzhiyun 3312*4882a593Smuzhiyun /* 3313*4882a593Smuzhiyun * R2583 (0xA17) - DSP1 Control 20 3314*4882a593Smuzhiyun */ 3315*4882a593Smuzhiyun #define WM2200_DSP1_WDMA_CHANNEL_ENABLE_MASK 0x00FF /* DSP1_WDMA_CHANNEL_ENABLE - [7:0] */ 3316*4882a593Smuzhiyun #define WM2200_DSP1_WDMA_CHANNEL_ENABLE_SHIFT 0 /* DSP1_WDMA_CHANNEL_ENABLE - [7:0] */ 3317*4882a593Smuzhiyun #define WM2200_DSP1_WDMA_CHANNEL_ENABLE_WIDTH 8 /* DSP1_WDMA_CHANNEL_ENABLE - [7:0] */ 3318*4882a593Smuzhiyun 3319*4882a593Smuzhiyun /* 3320*4882a593Smuzhiyun * R2584 (0xA18) - DSP1 Control 21 3321*4882a593Smuzhiyun */ 3322*4882a593Smuzhiyun #define WM2200_DSP1_RDMA_CHANNEL_ENABLE_MASK 0x003F /* DSP1_RDMA_CHANNEL_ENABLE - [5:0] */ 3323*4882a593Smuzhiyun #define WM2200_DSP1_RDMA_CHANNEL_ENABLE_SHIFT 0 /* DSP1_RDMA_CHANNEL_ENABLE - [5:0] */ 3324*4882a593Smuzhiyun #define WM2200_DSP1_RDMA_CHANNEL_ENABLE_WIDTH 6 /* DSP1_RDMA_CHANNEL_ENABLE - [5:0] */ 3325*4882a593Smuzhiyun 3326*4882a593Smuzhiyun /* 3327*4882a593Smuzhiyun * R2586 (0xA1A) - DSP1 Control 22 3328*4882a593Smuzhiyun */ 3329*4882a593Smuzhiyun #define WM2200_DSP1_DM_SIZE_MASK 0xFFFF /* DSP1_DM_SIZE - [15:0] */ 3330*4882a593Smuzhiyun #define WM2200_DSP1_DM_SIZE_SHIFT 0 /* DSP1_DM_SIZE - [15:0] */ 3331*4882a593Smuzhiyun #define WM2200_DSP1_DM_SIZE_WIDTH 16 /* DSP1_DM_SIZE - [15:0] */ 3332*4882a593Smuzhiyun 3333*4882a593Smuzhiyun /* 3334*4882a593Smuzhiyun * R2587 (0xA1B) - DSP1 Control 23 3335*4882a593Smuzhiyun */ 3336*4882a593Smuzhiyun #define WM2200_DSP1_PM_SIZE_MASK 0xFFFF /* DSP1_PM_SIZE - [15:0] */ 3337*4882a593Smuzhiyun #define WM2200_DSP1_PM_SIZE_SHIFT 0 /* DSP1_PM_SIZE - [15:0] */ 3338*4882a593Smuzhiyun #define WM2200_DSP1_PM_SIZE_WIDTH 16 /* DSP1_PM_SIZE - [15:0] */ 3339*4882a593Smuzhiyun 3340*4882a593Smuzhiyun /* 3341*4882a593Smuzhiyun * R2588 (0xA1C) - DSP1 Control 24 3342*4882a593Smuzhiyun */ 3343*4882a593Smuzhiyun #define WM2200_DSP1_ZM_SIZE_MASK 0xFFFF /* DSP1_ZM_SIZE - [15:0] */ 3344*4882a593Smuzhiyun #define WM2200_DSP1_ZM_SIZE_SHIFT 0 /* DSP1_ZM_SIZE - [15:0] */ 3345*4882a593Smuzhiyun #define WM2200_DSP1_ZM_SIZE_WIDTH 16 /* DSP1_ZM_SIZE - [15:0] */ 3346*4882a593Smuzhiyun 3347*4882a593Smuzhiyun /* 3348*4882a593Smuzhiyun * R2590 (0xA1E) - DSP1 Control 25 3349*4882a593Smuzhiyun */ 3350*4882a593Smuzhiyun #define WM2200_DSP1_PING_FULL 0x8000 /* DSP1_PING_FULL */ 3351*4882a593Smuzhiyun #define WM2200_DSP1_PING_FULL_MASK 0x8000 /* DSP1_PING_FULL */ 3352*4882a593Smuzhiyun #define WM2200_DSP1_PING_FULL_SHIFT 15 /* DSP1_PING_FULL */ 3353*4882a593Smuzhiyun #define WM2200_DSP1_PING_FULL_WIDTH 1 /* DSP1_PING_FULL */ 3354*4882a593Smuzhiyun #define WM2200_DSP1_PONG_FULL 0x4000 /* DSP1_PONG_FULL */ 3355*4882a593Smuzhiyun #define WM2200_DSP1_PONG_FULL_MASK 0x4000 /* DSP1_PONG_FULL */ 3356*4882a593Smuzhiyun #define WM2200_DSP1_PONG_FULL_SHIFT 14 /* DSP1_PONG_FULL */ 3357*4882a593Smuzhiyun #define WM2200_DSP1_PONG_FULL_WIDTH 1 /* DSP1_PONG_FULL */ 3358*4882a593Smuzhiyun #define WM2200_DSP1_WDMA_ACTIVE_CHANNELS_MASK 0x00FF /* DSP1_WDMA_ACTIVE_CHANNELS - [7:0] */ 3359*4882a593Smuzhiyun #define WM2200_DSP1_WDMA_ACTIVE_CHANNELS_SHIFT 0 /* DSP1_WDMA_ACTIVE_CHANNELS - [7:0] */ 3360*4882a593Smuzhiyun #define WM2200_DSP1_WDMA_ACTIVE_CHANNELS_WIDTH 8 /* DSP1_WDMA_ACTIVE_CHANNELS - [7:0] */ 3361*4882a593Smuzhiyun 3362*4882a593Smuzhiyun /* 3363*4882a593Smuzhiyun * R2592 (0xA20) - DSP1 Control 26 3364*4882a593Smuzhiyun */ 3365*4882a593Smuzhiyun #define WM2200_DSP1_SCRATCH_0_MASK 0xFFFF /* DSP1_SCRATCH_0 - [15:0] */ 3366*4882a593Smuzhiyun #define WM2200_DSP1_SCRATCH_0_SHIFT 0 /* DSP1_SCRATCH_0 - [15:0] */ 3367*4882a593Smuzhiyun #define WM2200_DSP1_SCRATCH_0_WIDTH 16 /* DSP1_SCRATCH_0 - [15:0] */ 3368*4882a593Smuzhiyun 3369*4882a593Smuzhiyun /* 3370*4882a593Smuzhiyun * R2593 (0xA21) - DSP1 Control 27 3371*4882a593Smuzhiyun */ 3372*4882a593Smuzhiyun #define WM2200_DSP1_SCRATCH_1_MASK 0xFFFF /* DSP1_SCRATCH_1 - [15:0] */ 3373*4882a593Smuzhiyun #define WM2200_DSP1_SCRATCH_1_SHIFT 0 /* DSP1_SCRATCH_1 - [15:0] */ 3374*4882a593Smuzhiyun #define WM2200_DSP1_SCRATCH_1_WIDTH 16 /* DSP1_SCRATCH_1 - [15:0] */ 3375*4882a593Smuzhiyun 3376*4882a593Smuzhiyun /* 3377*4882a593Smuzhiyun * R2594 (0xA22) - DSP1 Control 28 3378*4882a593Smuzhiyun */ 3379*4882a593Smuzhiyun #define WM2200_DSP1_SCRATCH_2_MASK 0xFFFF /* DSP1_SCRATCH_2 - [15:0] */ 3380*4882a593Smuzhiyun #define WM2200_DSP1_SCRATCH_2_SHIFT 0 /* DSP1_SCRATCH_2 - [15:0] */ 3381*4882a593Smuzhiyun #define WM2200_DSP1_SCRATCH_2_WIDTH 16 /* DSP1_SCRATCH_2 - [15:0] */ 3382*4882a593Smuzhiyun 3383*4882a593Smuzhiyun /* 3384*4882a593Smuzhiyun * R2595 (0xA23) - DSP1 Control 29 3385*4882a593Smuzhiyun */ 3386*4882a593Smuzhiyun #define WM2200_DSP1_SCRATCH_3_MASK 0xFFFF /* DSP1_SCRATCH_3 - [15:0] */ 3387*4882a593Smuzhiyun #define WM2200_DSP1_SCRATCH_3_SHIFT 0 /* DSP1_SCRATCH_3 - [15:0] */ 3388*4882a593Smuzhiyun #define WM2200_DSP1_SCRATCH_3_WIDTH 16 /* DSP1_SCRATCH_3 - [15:0] */ 3389*4882a593Smuzhiyun 3390*4882a593Smuzhiyun /* 3391*4882a593Smuzhiyun * R2596 (0xA24) - DSP1 Control 30 3392*4882a593Smuzhiyun */ 3393*4882a593Smuzhiyun #define WM2200_DSP1_DBG_CLK_ENA 0x0008 /* DSP1_DBG_CLK_ENA */ 3394*4882a593Smuzhiyun #define WM2200_DSP1_DBG_CLK_ENA_MASK 0x0008 /* DSP1_DBG_CLK_ENA */ 3395*4882a593Smuzhiyun #define WM2200_DSP1_DBG_CLK_ENA_SHIFT 3 /* DSP1_DBG_CLK_ENA */ 3396*4882a593Smuzhiyun #define WM2200_DSP1_DBG_CLK_ENA_WIDTH 1 /* DSP1_DBG_CLK_ENA */ 3397*4882a593Smuzhiyun #define WM2200_DSP1_SYS_ENA 0x0004 /* DSP1_SYS_ENA */ 3398*4882a593Smuzhiyun #define WM2200_DSP1_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */ 3399*4882a593Smuzhiyun #define WM2200_DSP1_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */ 3400*4882a593Smuzhiyun #define WM2200_DSP1_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */ 3401*4882a593Smuzhiyun #define WM2200_DSP1_CORE_ENA 0x0002 /* DSP1_CORE_ENA */ 3402*4882a593Smuzhiyun #define WM2200_DSP1_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */ 3403*4882a593Smuzhiyun #define WM2200_DSP1_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */ 3404*4882a593Smuzhiyun #define WM2200_DSP1_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */ 3405*4882a593Smuzhiyun #define WM2200_DSP1_START 0x0001 /* DSP1_START */ 3406*4882a593Smuzhiyun #define WM2200_DSP1_START_MASK 0x0001 /* DSP1_START */ 3407*4882a593Smuzhiyun #define WM2200_DSP1_START_SHIFT 0 /* DSP1_START */ 3408*4882a593Smuzhiyun #define WM2200_DSP1_START_WIDTH 1 /* DSP1_START */ 3409*4882a593Smuzhiyun 3410*4882a593Smuzhiyun /* 3411*4882a593Smuzhiyun * R2598 (0xA26) - DSP1 Control 31 3412*4882a593Smuzhiyun */ 3413*4882a593Smuzhiyun #define WM2200_DSP1_CLK_RATE_MASK 0x0018 /* DSP1_CLK_RATE - [4:3] */ 3414*4882a593Smuzhiyun #define WM2200_DSP1_CLK_RATE_SHIFT 3 /* DSP1_CLK_RATE - [4:3] */ 3415*4882a593Smuzhiyun #define WM2200_DSP1_CLK_RATE_WIDTH 2 /* DSP1_CLK_RATE - [4:3] */ 3416*4882a593Smuzhiyun #define WM2200_DSP1_CLK_AVAIL 0x0004 /* DSP1_CLK_AVAIL */ 3417*4882a593Smuzhiyun #define WM2200_DSP1_CLK_AVAIL_MASK 0x0004 /* DSP1_CLK_AVAIL */ 3418*4882a593Smuzhiyun #define WM2200_DSP1_CLK_AVAIL_SHIFT 2 /* DSP1_CLK_AVAIL */ 3419*4882a593Smuzhiyun #define WM2200_DSP1_CLK_AVAIL_WIDTH 1 /* DSP1_CLK_AVAIL */ 3420*4882a593Smuzhiyun #define WM2200_DSP1_CLK_REQ_MASK 0x0003 /* DSP1_CLK_REQ - [1:0] */ 3421*4882a593Smuzhiyun #define WM2200_DSP1_CLK_REQ_SHIFT 0 /* DSP1_CLK_REQ - [1:0] */ 3422*4882a593Smuzhiyun #define WM2200_DSP1_CLK_REQ_WIDTH 2 /* DSP1_CLK_REQ - [1:0] */ 3423*4882a593Smuzhiyun 3424*4882a593Smuzhiyun /* 3425*4882a593Smuzhiyun * R2816 (0xB00) - DSP2 Control 1 3426*4882a593Smuzhiyun */ 3427*4882a593Smuzhiyun #define WM2200_DSP2_RW_SEQUENCE_ENA 0x0001 /* DSP2_RW_SEQUENCE_ENA */ 3428*4882a593Smuzhiyun #define WM2200_DSP2_RW_SEQUENCE_ENA_MASK 0x0001 /* DSP2_RW_SEQUENCE_ENA */ 3429*4882a593Smuzhiyun #define WM2200_DSP2_RW_SEQUENCE_ENA_SHIFT 0 /* DSP2_RW_SEQUENCE_ENA */ 3430*4882a593Smuzhiyun #define WM2200_DSP2_RW_SEQUENCE_ENA_WIDTH 1 /* DSP2_RW_SEQUENCE_ENA */ 3431*4882a593Smuzhiyun 3432*4882a593Smuzhiyun /* 3433*4882a593Smuzhiyun * R2818 (0xB02) - DSP2 Control 2 3434*4882a593Smuzhiyun */ 3435*4882a593Smuzhiyun #define WM2200_DSP2_PAGE_BASE_PM_0_MASK 0xFF00 /* DSP2_PAGE_BASE_PM - [15:8] */ 3436*4882a593Smuzhiyun #define WM2200_DSP2_PAGE_BASE_PM_0_SHIFT 8 /* DSP2_PAGE_BASE_PM - [15:8] */ 3437*4882a593Smuzhiyun #define WM2200_DSP2_PAGE_BASE_PM_0_WIDTH 8 /* DSP2_PAGE_BASE_PM - [15:8] */ 3438*4882a593Smuzhiyun 3439*4882a593Smuzhiyun /* 3440*4882a593Smuzhiyun * R2819 (0xB03) - DSP2 Control 3 3441*4882a593Smuzhiyun */ 3442*4882a593Smuzhiyun #define WM2200_DSP2_PAGE_BASE_DM_0_MASK 0xFF00 /* DSP2_PAGE_BASE_DM - [15:8] */ 3443*4882a593Smuzhiyun #define WM2200_DSP2_PAGE_BASE_DM_0_SHIFT 8 /* DSP2_PAGE_BASE_DM - [15:8] */ 3444*4882a593Smuzhiyun #define WM2200_DSP2_PAGE_BASE_DM_0_WIDTH 8 /* DSP2_PAGE_BASE_DM - [15:8] */ 3445*4882a593Smuzhiyun 3446*4882a593Smuzhiyun /* 3447*4882a593Smuzhiyun * R2820 (0xB04) - DSP2 Control 4 3448*4882a593Smuzhiyun */ 3449*4882a593Smuzhiyun #define WM2200_DSP2_PAGE_BASE_ZM_0_MASK 0xFF00 /* DSP2_PAGE_BASE_ZM - [15:8] */ 3450*4882a593Smuzhiyun #define WM2200_DSP2_PAGE_BASE_ZM_0_SHIFT 8 /* DSP2_PAGE_BASE_ZM - [15:8] */ 3451*4882a593Smuzhiyun #define WM2200_DSP2_PAGE_BASE_ZM_0_WIDTH 8 /* DSP2_PAGE_BASE_ZM - [15:8] */ 3452*4882a593Smuzhiyun 3453*4882a593Smuzhiyun /* 3454*4882a593Smuzhiyun * R2822 (0xB06) - DSP2 Control 5 3455*4882a593Smuzhiyun */ 3456*4882a593Smuzhiyun #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_0_MASK 0x3FFF /* DSP2_START_ADDRESS_WDMA_BUFFER_0 - [13:0] */ 3457*4882a593Smuzhiyun #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_0_SHIFT 0 /* DSP2_START_ADDRESS_WDMA_BUFFER_0 - [13:0] */ 3458*4882a593Smuzhiyun #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_0_WIDTH 14 /* DSP2_START_ADDRESS_WDMA_BUFFER_0 - [13:0] */ 3459*4882a593Smuzhiyun 3460*4882a593Smuzhiyun /* 3461*4882a593Smuzhiyun * R2823 (0xB07) - DSP2 Control 6 3462*4882a593Smuzhiyun */ 3463*4882a593Smuzhiyun #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_1_MASK 0x3FFF /* DSP2_START_ADDRESS_WDMA_BUFFER_1 - [13:0] */ 3464*4882a593Smuzhiyun #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_1_SHIFT 0 /* DSP2_START_ADDRESS_WDMA_BUFFER_1 - [13:0] */ 3465*4882a593Smuzhiyun #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_1_WIDTH 14 /* DSP2_START_ADDRESS_WDMA_BUFFER_1 - [13:0] */ 3466*4882a593Smuzhiyun 3467*4882a593Smuzhiyun /* 3468*4882a593Smuzhiyun * R2824 (0xB08) - DSP2 Control 7 3469*4882a593Smuzhiyun */ 3470*4882a593Smuzhiyun #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_2_MASK 0x3FFF /* DSP2_START_ADDRESS_WDMA_BUFFER_2 - [13:0] */ 3471*4882a593Smuzhiyun #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_2_SHIFT 0 /* DSP2_START_ADDRESS_WDMA_BUFFER_2 - [13:0] */ 3472*4882a593Smuzhiyun #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_2_WIDTH 14 /* DSP2_START_ADDRESS_WDMA_BUFFER_2 - [13:0] */ 3473*4882a593Smuzhiyun 3474*4882a593Smuzhiyun /* 3475*4882a593Smuzhiyun * R2825 (0xB09) - DSP2 Control 8 3476*4882a593Smuzhiyun */ 3477*4882a593Smuzhiyun #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_3_MASK 0x3FFF /* DSP2_START_ADDRESS_WDMA_BUFFER_3 - [13:0] */ 3478*4882a593Smuzhiyun #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_3_SHIFT 0 /* DSP2_START_ADDRESS_WDMA_BUFFER_3 - [13:0] */ 3479*4882a593Smuzhiyun #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_3_WIDTH 14 /* DSP2_START_ADDRESS_WDMA_BUFFER_3 - [13:0] */ 3480*4882a593Smuzhiyun 3481*4882a593Smuzhiyun /* 3482*4882a593Smuzhiyun * R2826 (0xB0A) - DSP2 Control 9 3483*4882a593Smuzhiyun */ 3484*4882a593Smuzhiyun #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_4_MASK 0x3FFF /* DSP2_START_ADDRESS_WDMA_BUFFER_4 - [13:0] */ 3485*4882a593Smuzhiyun #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_4_SHIFT 0 /* DSP2_START_ADDRESS_WDMA_BUFFER_4 - [13:0] */ 3486*4882a593Smuzhiyun #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_4_WIDTH 14 /* DSP2_START_ADDRESS_WDMA_BUFFER_4 - [13:0] */ 3487*4882a593Smuzhiyun 3488*4882a593Smuzhiyun /* 3489*4882a593Smuzhiyun * R2827 (0xB0B) - DSP2 Control 10 3490*4882a593Smuzhiyun */ 3491*4882a593Smuzhiyun #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_5_MASK 0x3FFF /* DSP2_START_ADDRESS_WDMA_BUFFER_5 - [13:0] */ 3492*4882a593Smuzhiyun #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_5_SHIFT 0 /* DSP2_START_ADDRESS_WDMA_BUFFER_5 - [13:0] */ 3493*4882a593Smuzhiyun #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_5_WIDTH 14 /* DSP2_START_ADDRESS_WDMA_BUFFER_5 - [13:0] */ 3494*4882a593Smuzhiyun 3495*4882a593Smuzhiyun /* 3496*4882a593Smuzhiyun * R2828 (0xB0C) - DSP2 Control 11 3497*4882a593Smuzhiyun */ 3498*4882a593Smuzhiyun #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_6_MASK 0x3FFF /* DSP2_START_ADDRESS_WDMA_BUFFER_6 - [13:0] */ 3499*4882a593Smuzhiyun #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_6_SHIFT 0 /* DSP2_START_ADDRESS_WDMA_BUFFER_6 - [13:0] */ 3500*4882a593Smuzhiyun #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_6_WIDTH 14 /* DSP2_START_ADDRESS_WDMA_BUFFER_6 - [13:0] */ 3501*4882a593Smuzhiyun 3502*4882a593Smuzhiyun /* 3503*4882a593Smuzhiyun * R2829 (0xB0D) - DSP2 Control 12 3504*4882a593Smuzhiyun */ 3505*4882a593Smuzhiyun #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_7_MASK 0x3FFF /* DSP2_START_ADDRESS_WDMA_BUFFER_7 - [13:0] */ 3506*4882a593Smuzhiyun #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_7_SHIFT 0 /* DSP2_START_ADDRESS_WDMA_BUFFER_7 - [13:0] */ 3507*4882a593Smuzhiyun #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_7_WIDTH 14 /* DSP2_START_ADDRESS_WDMA_BUFFER_7 - [13:0] */ 3508*4882a593Smuzhiyun 3509*4882a593Smuzhiyun /* 3510*4882a593Smuzhiyun * R2831 (0xB0F) - DSP2 Control 13 3511*4882a593Smuzhiyun */ 3512*4882a593Smuzhiyun #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_0_MASK 0x3FFF /* DSP2_START_ADDRESS_RDMA_BUFFER_0 - [13:0] */ 3513*4882a593Smuzhiyun #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_0_SHIFT 0 /* DSP2_START_ADDRESS_RDMA_BUFFER_0 - [13:0] */ 3514*4882a593Smuzhiyun #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_0_WIDTH 14 /* DSP2_START_ADDRESS_RDMA_BUFFER_0 - [13:0] */ 3515*4882a593Smuzhiyun 3516*4882a593Smuzhiyun /* 3517*4882a593Smuzhiyun * R2832 (0xB10) - DSP2 Control 14 3518*4882a593Smuzhiyun */ 3519*4882a593Smuzhiyun #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_1_MASK 0x3FFF /* DSP2_START_ADDRESS_RDMA_BUFFER_1 - [13:0] */ 3520*4882a593Smuzhiyun #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_1_SHIFT 0 /* DSP2_START_ADDRESS_RDMA_BUFFER_1 - [13:0] */ 3521*4882a593Smuzhiyun #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_1_WIDTH 14 /* DSP2_START_ADDRESS_RDMA_BUFFER_1 - [13:0] */ 3522*4882a593Smuzhiyun 3523*4882a593Smuzhiyun /* 3524*4882a593Smuzhiyun * R2833 (0xB11) - DSP2 Control 15 3525*4882a593Smuzhiyun */ 3526*4882a593Smuzhiyun #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_2_MASK 0x3FFF /* DSP2_START_ADDRESS_RDMA_BUFFER_2 - [13:0] */ 3527*4882a593Smuzhiyun #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_2_SHIFT 0 /* DSP2_START_ADDRESS_RDMA_BUFFER_2 - [13:0] */ 3528*4882a593Smuzhiyun #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_2_WIDTH 14 /* DSP2_START_ADDRESS_RDMA_BUFFER_2 - [13:0] */ 3529*4882a593Smuzhiyun 3530*4882a593Smuzhiyun /* 3531*4882a593Smuzhiyun * R2834 (0xB12) - DSP2 Control 16 3532*4882a593Smuzhiyun */ 3533*4882a593Smuzhiyun #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_3_MASK 0x3FFF /* DSP2_START_ADDRESS_RDMA_BUFFER_3 - [13:0] */ 3534*4882a593Smuzhiyun #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_3_SHIFT 0 /* DSP2_START_ADDRESS_RDMA_BUFFER_3 - [13:0] */ 3535*4882a593Smuzhiyun #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_3_WIDTH 14 /* DSP2_START_ADDRESS_RDMA_BUFFER_3 - [13:0] */ 3536*4882a593Smuzhiyun 3537*4882a593Smuzhiyun /* 3538*4882a593Smuzhiyun * R2835 (0xB13) - DSP2 Control 17 3539*4882a593Smuzhiyun */ 3540*4882a593Smuzhiyun #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_4_MASK 0x3FFF /* DSP2_START_ADDRESS_RDMA_BUFFER_4 - [13:0] */ 3541*4882a593Smuzhiyun #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_4_SHIFT 0 /* DSP2_START_ADDRESS_RDMA_BUFFER_4 - [13:0] */ 3542*4882a593Smuzhiyun #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_4_WIDTH 14 /* DSP2_START_ADDRESS_RDMA_BUFFER_4 - [13:0] */ 3543*4882a593Smuzhiyun 3544*4882a593Smuzhiyun /* 3545*4882a593Smuzhiyun * R2836 (0xB14) - DSP2 Control 18 3546*4882a593Smuzhiyun */ 3547*4882a593Smuzhiyun #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_5_MASK 0x3FFF /* DSP2_START_ADDRESS_RDMA_BUFFER_5 - [13:0] */ 3548*4882a593Smuzhiyun #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_5_SHIFT 0 /* DSP2_START_ADDRESS_RDMA_BUFFER_5 - [13:0] */ 3549*4882a593Smuzhiyun #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_5_WIDTH 14 /* DSP2_START_ADDRESS_RDMA_BUFFER_5 - [13:0] */ 3550*4882a593Smuzhiyun 3551*4882a593Smuzhiyun /* 3552*4882a593Smuzhiyun * R2838 (0xB16) - DSP2 Control 19 3553*4882a593Smuzhiyun */ 3554*4882a593Smuzhiyun #define WM2200_DSP2_WDMA_BUFFER_LENGTH_MASK 0x00FF /* DSP2_WDMA_BUFFER_LENGTH - [7:0] */ 3555*4882a593Smuzhiyun #define WM2200_DSP2_WDMA_BUFFER_LENGTH_SHIFT 0 /* DSP2_WDMA_BUFFER_LENGTH - [7:0] */ 3556*4882a593Smuzhiyun #define WM2200_DSP2_WDMA_BUFFER_LENGTH_WIDTH 8 /* DSP2_WDMA_BUFFER_LENGTH - [7:0] */ 3557*4882a593Smuzhiyun 3558*4882a593Smuzhiyun /* 3559*4882a593Smuzhiyun * R2839 (0xB17) - DSP2 Control 20 3560*4882a593Smuzhiyun */ 3561*4882a593Smuzhiyun #define WM2200_DSP2_WDMA_CHANNEL_ENABLE_MASK 0x00FF /* DSP2_WDMA_CHANNEL_ENABLE - [7:0] */ 3562*4882a593Smuzhiyun #define WM2200_DSP2_WDMA_CHANNEL_ENABLE_SHIFT 0 /* DSP2_WDMA_CHANNEL_ENABLE - [7:0] */ 3563*4882a593Smuzhiyun #define WM2200_DSP2_WDMA_CHANNEL_ENABLE_WIDTH 8 /* DSP2_WDMA_CHANNEL_ENABLE - [7:0] */ 3564*4882a593Smuzhiyun 3565*4882a593Smuzhiyun /* 3566*4882a593Smuzhiyun * R2840 (0xB18) - DSP2 Control 21 3567*4882a593Smuzhiyun */ 3568*4882a593Smuzhiyun #define WM2200_DSP2_RDMA_CHANNEL_ENABLE_MASK 0x003F /* DSP2_RDMA_CHANNEL_ENABLE - [5:0] */ 3569*4882a593Smuzhiyun #define WM2200_DSP2_RDMA_CHANNEL_ENABLE_SHIFT 0 /* DSP2_RDMA_CHANNEL_ENABLE - [5:0] */ 3570*4882a593Smuzhiyun #define WM2200_DSP2_RDMA_CHANNEL_ENABLE_WIDTH 6 /* DSP2_RDMA_CHANNEL_ENABLE - [5:0] */ 3571*4882a593Smuzhiyun 3572*4882a593Smuzhiyun /* 3573*4882a593Smuzhiyun * R2842 (0xB1A) - DSP2 Control 22 3574*4882a593Smuzhiyun */ 3575*4882a593Smuzhiyun #define WM2200_DSP2_DM_SIZE_MASK 0xFFFF /* DSP2_DM_SIZE - [15:0] */ 3576*4882a593Smuzhiyun #define WM2200_DSP2_DM_SIZE_SHIFT 0 /* DSP2_DM_SIZE - [15:0] */ 3577*4882a593Smuzhiyun #define WM2200_DSP2_DM_SIZE_WIDTH 16 /* DSP2_DM_SIZE - [15:0] */ 3578*4882a593Smuzhiyun 3579*4882a593Smuzhiyun /* 3580*4882a593Smuzhiyun * R2843 (0xB1B) - DSP2 Control 23 3581*4882a593Smuzhiyun */ 3582*4882a593Smuzhiyun #define WM2200_DSP2_PM_SIZE_MASK 0xFFFF /* DSP2_PM_SIZE - [15:0] */ 3583*4882a593Smuzhiyun #define WM2200_DSP2_PM_SIZE_SHIFT 0 /* DSP2_PM_SIZE - [15:0] */ 3584*4882a593Smuzhiyun #define WM2200_DSP2_PM_SIZE_WIDTH 16 /* DSP2_PM_SIZE - [15:0] */ 3585*4882a593Smuzhiyun 3586*4882a593Smuzhiyun /* 3587*4882a593Smuzhiyun * R2844 (0xB1C) - DSP2 Control 24 3588*4882a593Smuzhiyun */ 3589*4882a593Smuzhiyun #define WM2200_DSP2_ZM_SIZE_MASK 0xFFFF /* DSP2_ZM_SIZE - [15:0] */ 3590*4882a593Smuzhiyun #define WM2200_DSP2_ZM_SIZE_SHIFT 0 /* DSP2_ZM_SIZE - [15:0] */ 3591*4882a593Smuzhiyun #define WM2200_DSP2_ZM_SIZE_WIDTH 16 /* DSP2_ZM_SIZE - [15:0] */ 3592*4882a593Smuzhiyun 3593*4882a593Smuzhiyun /* 3594*4882a593Smuzhiyun * R2846 (0xB1E) - DSP2 Control 25 3595*4882a593Smuzhiyun */ 3596*4882a593Smuzhiyun #define WM2200_DSP2_PING_FULL 0x8000 /* DSP2_PING_FULL */ 3597*4882a593Smuzhiyun #define WM2200_DSP2_PING_FULL_MASK 0x8000 /* DSP2_PING_FULL */ 3598*4882a593Smuzhiyun #define WM2200_DSP2_PING_FULL_SHIFT 15 /* DSP2_PING_FULL */ 3599*4882a593Smuzhiyun #define WM2200_DSP2_PING_FULL_WIDTH 1 /* DSP2_PING_FULL */ 3600*4882a593Smuzhiyun #define WM2200_DSP2_PONG_FULL 0x4000 /* DSP2_PONG_FULL */ 3601*4882a593Smuzhiyun #define WM2200_DSP2_PONG_FULL_MASK 0x4000 /* DSP2_PONG_FULL */ 3602*4882a593Smuzhiyun #define WM2200_DSP2_PONG_FULL_SHIFT 14 /* DSP2_PONG_FULL */ 3603*4882a593Smuzhiyun #define WM2200_DSP2_PONG_FULL_WIDTH 1 /* DSP2_PONG_FULL */ 3604*4882a593Smuzhiyun #define WM2200_DSP2_WDMA_ACTIVE_CHANNELS_MASK 0x00FF /* DSP2_WDMA_ACTIVE_CHANNELS - [7:0] */ 3605*4882a593Smuzhiyun #define WM2200_DSP2_WDMA_ACTIVE_CHANNELS_SHIFT 0 /* DSP2_WDMA_ACTIVE_CHANNELS - [7:0] */ 3606*4882a593Smuzhiyun #define WM2200_DSP2_WDMA_ACTIVE_CHANNELS_WIDTH 8 /* DSP2_WDMA_ACTIVE_CHANNELS - [7:0] */ 3607*4882a593Smuzhiyun 3608*4882a593Smuzhiyun /* 3609*4882a593Smuzhiyun * R2848 (0xB20) - DSP2 Control 26 3610*4882a593Smuzhiyun */ 3611*4882a593Smuzhiyun #define WM2200_DSP2_SCRATCH_0_MASK 0xFFFF /* DSP2_SCRATCH_0 - [15:0] */ 3612*4882a593Smuzhiyun #define WM2200_DSP2_SCRATCH_0_SHIFT 0 /* DSP2_SCRATCH_0 - [15:0] */ 3613*4882a593Smuzhiyun #define WM2200_DSP2_SCRATCH_0_WIDTH 16 /* DSP2_SCRATCH_0 - [15:0] */ 3614*4882a593Smuzhiyun 3615*4882a593Smuzhiyun /* 3616*4882a593Smuzhiyun * R2849 (0xB21) - DSP2 Control 27 3617*4882a593Smuzhiyun */ 3618*4882a593Smuzhiyun #define WM2200_DSP2_SCRATCH_1_MASK 0xFFFF /* DSP2_SCRATCH_1 - [15:0] */ 3619*4882a593Smuzhiyun #define WM2200_DSP2_SCRATCH_1_SHIFT 0 /* DSP2_SCRATCH_1 - [15:0] */ 3620*4882a593Smuzhiyun #define WM2200_DSP2_SCRATCH_1_WIDTH 16 /* DSP2_SCRATCH_1 - [15:0] */ 3621*4882a593Smuzhiyun 3622*4882a593Smuzhiyun /* 3623*4882a593Smuzhiyun * R2850 (0xB22) - DSP2 Control 28 3624*4882a593Smuzhiyun */ 3625*4882a593Smuzhiyun #define WM2200_DSP2_SCRATCH_2_MASK 0xFFFF /* DSP2_SCRATCH_2 - [15:0] */ 3626*4882a593Smuzhiyun #define WM2200_DSP2_SCRATCH_2_SHIFT 0 /* DSP2_SCRATCH_2 - [15:0] */ 3627*4882a593Smuzhiyun #define WM2200_DSP2_SCRATCH_2_WIDTH 16 /* DSP2_SCRATCH_2 - [15:0] */ 3628*4882a593Smuzhiyun 3629*4882a593Smuzhiyun /* 3630*4882a593Smuzhiyun * R2851 (0xB23) - DSP2 Control 29 3631*4882a593Smuzhiyun */ 3632*4882a593Smuzhiyun #define WM2200_DSP2_SCRATCH_3_MASK 0xFFFF /* DSP2_SCRATCH_3 - [15:0] */ 3633*4882a593Smuzhiyun #define WM2200_DSP2_SCRATCH_3_SHIFT 0 /* DSP2_SCRATCH_3 - [15:0] */ 3634*4882a593Smuzhiyun #define WM2200_DSP2_SCRATCH_3_WIDTH 16 /* DSP2_SCRATCH_3 - [15:0] */ 3635*4882a593Smuzhiyun 3636*4882a593Smuzhiyun /* 3637*4882a593Smuzhiyun * R2852 (0xB24) - DSP2 Control 30 3638*4882a593Smuzhiyun */ 3639*4882a593Smuzhiyun #define WM2200_DSP2_DBG_CLK_ENA 0x0008 /* DSP2_DBG_CLK_ENA */ 3640*4882a593Smuzhiyun #define WM2200_DSP2_DBG_CLK_ENA_MASK 0x0008 /* DSP2_DBG_CLK_ENA */ 3641*4882a593Smuzhiyun #define WM2200_DSP2_DBG_CLK_ENA_SHIFT 3 /* DSP2_DBG_CLK_ENA */ 3642*4882a593Smuzhiyun #define WM2200_DSP2_DBG_CLK_ENA_WIDTH 1 /* DSP2_DBG_CLK_ENA */ 3643*4882a593Smuzhiyun #define WM2200_DSP2_SYS_ENA 0x0004 /* DSP2_SYS_ENA */ 3644*4882a593Smuzhiyun #define WM2200_DSP2_SYS_ENA_MASK 0x0004 /* DSP2_SYS_ENA */ 3645*4882a593Smuzhiyun #define WM2200_DSP2_SYS_ENA_SHIFT 2 /* DSP2_SYS_ENA */ 3646*4882a593Smuzhiyun #define WM2200_DSP2_SYS_ENA_WIDTH 1 /* DSP2_SYS_ENA */ 3647*4882a593Smuzhiyun #define WM2200_DSP2_CORE_ENA 0x0002 /* DSP2_CORE_ENA */ 3648*4882a593Smuzhiyun #define WM2200_DSP2_CORE_ENA_MASK 0x0002 /* DSP2_CORE_ENA */ 3649*4882a593Smuzhiyun #define WM2200_DSP2_CORE_ENA_SHIFT 1 /* DSP2_CORE_ENA */ 3650*4882a593Smuzhiyun #define WM2200_DSP2_CORE_ENA_WIDTH 1 /* DSP2_CORE_ENA */ 3651*4882a593Smuzhiyun #define WM2200_DSP2_START 0x0001 /* DSP2_START */ 3652*4882a593Smuzhiyun #define WM2200_DSP2_START_MASK 0x0001 /* DSP2_START */ 3653*4882a593Smuzhiyun #define WM2200_DSP2_START_SHIFT 0 /* DSP2_START */ 3654*4882a593Smuzhiyun #define WM2200_DSP2_START_WIDTH 1 /* DSP2_START */ 3655*4882a593Smuzhiyun 3656*4882a593Smuzhiyun /* 3657*4882a593Smuzhiyun * R2854 (0xB26) - DSP2 Control 31 3658*4882a593Smuzhiyun */ 3659*4882a593Smuzhiyun #define WM2200_DSP2_CLK_RATE_MASK 0x0018 /* DSP2_CLK_RATE - [4:3] */ 3660*4882a593Smuzhiyun #define WM2200_DSP2_CLK_RATE_SHIFT 3 /* DSP2_CLK_RATE - [4:3] */ 3661*4882a593Smuzhiyun #define WM2200_DSP2_CLK_RATE_WIDTH 2 /* DSP2_CLK_RATE - [4:3] */ 3662*4882a593Smuzhiyun #define WM2200_DSP2_CLK_AVAIL 0x0004 /* DSP2_CLK_AVAIL */ 3663*4882a593Smuzhiyun #define WM2200_DSP2_CLK_AVAIL_MASK 0x0004 /* DSP2_CLK_AVAIL */ 3664*4882a593Smuzhiyun #define WM2200_DSP2_CLK_AVAIL_SHIFT 2 /* DSP2_CLK_AVAIL */ 3665*4882a593Smuzhiyun #define WM2200_DSP2_CLK_AVAIL_WIDTH 1 /* DSP2_CLK_AVAIL */ 3666*4882a593Smuzhiyun #define WM2200_DSP2_CLK_REQ_MASK 0x0003 /* DSP2_CLK_REQ - [1:0] */ 3667*4882a593Smuzhiyun #define WM2200_DSP2_CLK_REQ_SHIFT 0 /* DSP2_CLK_REQ - [1:0] */ 3668*4882a593Smuzhiyun #define WM2200_DSP2_CLK_REQ_WIDTH 2 /* DSP2_CLK_REQ - [1:0] */ 3669*4882a593Smuzhiyun 3670*4882a593Smuzhiyun #endif 3671