1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun 3*4882a593Smuzhiyun #ifndef _WCD_CLSH_V2_H_ 4*4882a593Smuzhiyun #define _WCD_CLSH_V2_H_ 5*4882a593Smuzhiyun #include <sound/soc.h> 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun enum wcd_clsh_event { 8*4882a593Smuzhiyun WCD_CLSH_EVENT_PRE_DAC = 1, 9*4882a593Smuzhiyun WCD_CLSH_EVENT_POST_PA, 10*4882a593Smuzhiyun }; 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* 13*4882a593Smuzhiyun * Basic states for Class H state machine. 14*4882a593Smuzhiyun * represented as a bit mask within a u8 data type 15*4882a593Smuzhiyun * bit 0: EAR mode 16*4882a593Smuzhiyun * bit 1: HPH Left mode 17*4882a593Smuzhiyun * bit 2: HPH Right mode 18*4882a593Smuzhiyun * bit 3: Lineout mode 19*4882a593Smuzhiyun */ 20*4882a593Smuzhiyun #define WCD_CLSH_STATE_IDLE 0 21*4882a593Smuzhiyun #define WCD_CLSH_STATE_EAR BIT(0) 22*4882a593Smuzhiyun #define WCD_CLSH_STATE_HPHL BIT(1) 23*4882a593Smuzhiyun #define WCD_CLSH_STATE_HPHR BIT(2) 24*4882a593Smuzhiyun #define WCD_CLSH_STATE_LO BIT(3) 25*4882a593Smuzhiyun #define WCD_CLSH_STATE_MAX 4 26*4882a593Smuzhiyun #define NUM_CLSH_STATES_V2 BIT(WCD_CLSH_STATE_MAX) 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun enum wcd_clsh_mode { 29*4882a593Smuzhiyun CLS_H_NORMAL = 0, /* Class-H Default */ 30*4882a593Smuzhiyun CLS_H_HIFI, /* Class-H HiFi */ 31*4882a593Smuzhiyun CLS_H_LP, /* Class-H Low Power */ 32*4882a593Smuzhiyun CLS_AB, /* Class-AB */ 33*4882a593Smuzhiyun CLS_H_LOHIFI, /* LoHIFI */ 34*4882a593Smuzhiyun CLS_NONE, /* None of the above modes */ 35*4882a593Smuzhiyun }; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun struct wcd_clsh_ctrl; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun extern struct wcd_clsh_ctrl *wcd_clsh_ctrl_alloc( 40*4882a593Smuzhiyun struct snd_soc_component *component, 41*4882a593Smuzhiyun int version); 42*4882a593Smuzhiyun extern void wcd_clsh_ctrl_free(struct wcd_clsh_ctrl *ctrl); 43*4882a593Smuzhiyun extern int wcd_clsh_ctrl_get_state(struct wcd_clsh_ctrl *ctrl); 44*4882a593Smuzhiyun extern int wcd_clsh_ctrl_set_state(struct wcd_clsh_ctrl *ctrl, 45*4882a593Smuzhiyun enum wcd_clsh_event event, 46*4882a593Smuzhiyun int state, 47*4882a593Smuzhiyun enum wcd_clsh_mode mode); 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun #endif /* _WCD_CLSH_V2_H_ */ 50