1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Audio support for Philips UDA1380 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (c) 2005 Giorgio Padrin <giorgio@mandarinlogiq.org> 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _UDA1380_H 9*4882a593Smuzhiyun #define _UDA1380_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define UDA1380_CLK 0x00 12*4882a593Smuzhiyun #define UDA1380_IFACE 0x01 13*4882a593Smuzhiyun #define UDA1380_PM 0x02 14*4882a593Smuzhiyun #define UDA1380_AMIX 0x03 15*4882a593Smuzhiyun #define UDA1380_HP 0x04 16*4882a593Smuzhiyun #define UDA1380_MVOL 0x10 17*4882a593Smuzhiyun #define UDA1380_MIXVOL 0x11 18*4882a593Smuzhiyun #define UDA1380_MODE 0x12 19*4882a593Smuzhiyun #define UDA1380_DEEMP 0x13 20*4882a593Smuzhiyun #define UDA1380_MIXER 0x14 21*4882a593Smuzhiyun #define UDA1380_INTSTAT 0x18 22*4882a593Smuzhiyun #define UDA1380_DEC 0x20 23*4882a593Smuzhiyun #define UDA1380_PGA 0x21 24*4882a593Smuzhiyun #define UDA1380_ADC 0x22 25*4882a593Smuzhiyun #define UDA1380_AGC 0x23 26*4882a593Smuzhiyun #define UDA1380_DECSTAT 0x28 27*4882a593Smuzhiyun #define UDA1380_RESET 0x7f 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun #define UDA1380_CACHEREGNUM 0x24 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /* Register flags */ 32*4882a593Smuzhiyun #define R00_EN_ADC 0x0800 33*4882a593Smuzhiyun #define R00_EN_DEC 0x0400 34*4882a593Smuzhiyun #define R00_EN_DAC 0x0200 35*4882a593Smuzhiyun #define R00_EN_INT 0x0100 36*4882a593Smuzhiyun #define R00_DAC_CLK 0x0010 37*4882a593Smuzhiyun #define R01_SFORI_I2S 0x0000 38*4882a593Smuzhiyun #define R01_SFORI_LSB16 0x0100 39*4882a593Smuzhiyun #define R01_SFORI_LSB18 0x0200 40*4882a593Smuzhiyun #define R01_SFORI_LSB20 0x0300 41*4882a593Smuzhiyun #define R01_SFORI_MSB 0x0500 42*4882a593Smuzhiyun #define R01_SFORI_MASK 0x0700 43*4882a593Smuzhiyun #define R01_SFORO_I2S 0x0000 44*4882a593Smuzhiyun #define R01_SFORO_LSB16 0x0001 45*4882a593Smuzhiyun #define R01_SFORO_LSB18 0x0002 46*4882a593Smuzhiyun #define R01_SFORO_LSB20 0x0003 47*4882a593Smuzhiyun #define R01_SFORO_LSB24 0x0004 48*4882a593Smuzhiyun #define R01_SFORO_MSB 0x0005 49*4882a593Smuzhiyun #define R01_SFORO_MASK 0x0007 50*4882a593Smuzhiyun #define R01_SEL_SOURCE 0x0040 51*4882a593Smuzhiyun #define R01_SIM 0x0010 52*4882a593Smuzhiyun #define R02_PON_PLL 0x8000 53*4882a593Smuzhiyun #define R02_PON_HP 0x2000 54*4882a593Smuzhiyun #define R02_PON_DAC 0x0400 55*4882a593Smuzhiyun #define R02_PON_BIAS 0x0100 56*4882a593Smuzhiyun #define R02_EN_AVC 0x0080 57*4882a593Smuzhiyun #define R02_PON_AVC 0x0040 58*4882a593Smuzhiyun #define R02_PON_LNA 0x0010 59*4882a593Smuzhiyun #define R02_PON_PGAL 0x0008 60*4882a593Smuzhiyun #define R02_PON_ADCL 0x0004 61*4882a593Smuzhiyun #define R02_PON_PGAR 0x0002 62*4882a593Smuzhiyun #define R02_PON_ADCR 0x0001 63*4882a593Smuzhiyun #define R13_MTM 0x4000 64*4882a593Smuzhiyun #define R14_SILENCE 0x0080 65*4882a593Smuzhiyun #define R14_SDET_ON 0x0040 66*4882a593Smuzhiyun #define R21_MT_ADC 0x8000 67*4882a593Smuzhiyun #define R22_SEL_LNA 0x0008 68*4882a593Smuzhiyun #define R22_SEL_MIC 0x0004 69*4882a593Smuzhiyun #define R22_SKIP_DCFIL 0x0002 70*4882a593Smuzhiyun #define R23_AGC_EN 0x0001 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun #endif /* _UDA1380_H */ 73