1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef _UDA134X_CODEC_H 3*4882a593Smuzhiyun #define _UDA134X_CODEC_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun #define UDA134X_L3ADDR 5 6*4882a593Smuzhiyun #define UDA134X_DATA0_ADDR ((UDA134X_L3ADDR << 2) | 0) 7*4882a593Smuzhiyun #define UDA134X_DATA1_ADDR ((UDA134X_L3ADDR << 2) | 1) 8*4882a593Smuzhiyun #define UDA134X_STATUS_ADDR ((UDA134X_L3ADDR << 2) | 2) 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #define UDA134X_EXTADDR_PREFIX 0xC0 11*4882a593Smuzhiyun #define UDA134X_EXTDATA_PREFIX 0xE0 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* UDA134X registers */ 14*4882a593Smuzhiyun #define UDA134X_EA000 0 15*4882a593Smuzhiyun #define UDA134X_EA001 1 16*4882a593Smuzhiyun #define UDA134X_EA010 2 17*4882a593Smuzhiyun #define UDA134X_EA011 3 18*4882a593Smuzhiyun #define UDA134X_EA100 4 19*4882a593Smuzhiyun #define UDA134X_EA101 5 20*4882a593Smuzhiyun #define UDA134X_EA110 6 21*4882a593Smuzhiyun #define UDA134X_EA111 7 22*4882a593Smuzhiyun #define UDA134X_STATUS0 8 23*4882a593Smuzhiyun #define UDA134X_STATUS1 9 24*4882a593Smuzhiyun #define UDA134X_DATA000 10 25*4882a593Smuzhiyun #define UDA134X_DATA001 11 26*4882a593Smuzhiyun #define UDA134X_DATA010 12 27*4882a593Smuzhiyun #define UDA134X_DATA011 13 28*4882a593Smuzhiyun #define UDA134X_DATA1 14 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #define STATUS0_DAIFMT_MASK (~(7<<1)) 31*4882a593Smuzhiyun #define STATUS0_SYSCLK_MASK (~(3<<4)) 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #endif 34