xref: /OK3568_Linux_fs/kernel/sound/soc/codecs/uda134x.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * uda134x.c  --  UDA134X ALSA SoC Codec driver
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Modifications by Christian Pellegrin <chripell@evolware.org>
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * Copyright 2007 Dension Audio Systems Ltd.
8*4882a593Smuzhiyun  * Author: Zoltan Devai
9*4882a593Smuzhiyun  *
10*4882a593Smuzhiyun  * Based on the WM87xx drivers by Liam Girdwood and Richard Purdie
11*4882a593Smuzhiyun  */
12*4882a593Smuzhiyun 
13*4882a593Smuzhiyun #include <linux/module.h>
14*4882a593Smuzhiyun #include <linux/delay.h>
15*4882a593Smuzhiyun #include <linux/slab.h>
16*4882a593Smuzhiyun #include <sound/pcm.h>
17*4882a593Smuzhiyun #include <sound/pcm_params.h>
18*4882a593Smuzhiyun #include <sound/soc.h>
19*4882a593Smuzhiyun #include <sound/initval.h>
20*4882a593Smuzhiyun 
21*4882a593Smuzhiyun #include <sound/uda134x.h>
22*4882a593Smuzhiyun #include <sound/l3.h>
23*4882a593Smuzhiyun 
24*4882a593Smuzhiyun #include "uda134x.h"
25*4882a593Smuzhiyun 
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun #define UDA134X_RATES SNDRV_PCM_RATE_8000_48000
28*4882a593Smuzhiyun #define UDA134X_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | \
29*4882a593Smuzhiyun 		SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S20_3LE)
30*4882a593Smuzhiyun 
31*4882a593Smuzhiyun struct uda134x_priv {
32*4882a593Smuzhiyun 	int sysclk;
33*4882a593Smuzhiyun 	int dai_fmt;
34*4882a593Smuzhiyun 
35*4882a593Smuzhiyun 	struct snd_pcm_substream *master_substream;
36*4882a593Smuzhiyun 	struct snd_pcm_substream *slave_substream;
37*4882a593Smuzhiyun 
38*4882a593Smuzhiyun 	struct regmap *regmap;
39*4882a593Smuzhiyun 	struct uda134x_platform_data *pd;
40*4882a593Smuzhiyun };
41*4882a593Smuzhiyun 
42*4882a593Smuzhiyun static const struct reg_default uda134x_reg_defaults[] = {
43*4882a593Smuzhiyun 	{ UDA134X_EA000, 0x04 },
44*4882a593Smuzhiyun 	{ UDA134X_EA001, 0x04 },
45*4882a593Smuzhiyun 	{ UDA134X_EA010, 0x04 },
46*4882a593Smuzhiyun 	{ UDA134X_EA011, 0x00 },
47*4882a593Smuzhiyun 	{ UDA134X_EA100, 0x00 },
48*4882a593Smuzhiyun 	{ UDA134X_EA101, 0x00 },
49*4882a593Smuzhiyun 	{ UDA134X_EA110, 0x00 },
50*4882a593Smuzhiyun 	{ UDA134X_EA111, 0x00 },
51*4882a593Smuzhiyun 	{ UDA134X_STATUS0, 0x00 },
52*4882a593Smuzhiyun 	{ UDA134X_STATUS1, 0x03 },
53*4882a593Smuzhiyun 	{ UDA134X_DATA000, 0x00 },
54*4882a593Smuzhiyun 	{ UDA134X_DATA001, 0x00 },
55*4882a593Smuzhiyun 	{ UDA134X_DATA010, 0x00 },
56*4882a593Smuzhiyun 	{ UDA134X_DATA011, 0x00 },
57*4882a593Smuzhiyun 	{ UDA134X_DATA1, 0x00 },
58*4882a593Smuzhiyun };
59*4882a593Smuzhiyun 
60*4882a593Smuzhiyun /*
61*4882a593Smuzhiyun  * Write to the uda134x registers
62*4882a593Smuzhiyun  *
63*4882a593Smuzhiyun  */
uda134x_regmap_write(void * context,unsigned int reg,unsigned int value)64*4882a593Smuzhiyun static int uda134x_regmap_write(void *context, unsigned int reg,
65*4882a593Smuzhiyun 	unsigned int value)
66*4882a593Smuzhiyun {
67*4882a593Smuzhiyun 	struct uda134x_platform_data *pd = context;
68*4882a593Smuzhiyun 	int ret;
69*4882a593Smuzhiyun 	u8 addr;
70*4882a593Smuzhiyun 	u8 data = value;
71*4882a593Smuzhiyun 
72*4882a593Smuzhiyun 	switch (reg) {
73*4882a593Smuzhiyun 	case UDA134X_STATUS0:
74*4882a593Smuzhiyun 	case UDA134X_STATUS1:
75*4882a593Smuzhiyun 		addr = UDA134X_STATUS_ADDR;
76*4882a593Smuzhiyun 		data |= (reg - UDA134X_STATUS0) << 7;
77*4882a593Smuzhiyun 		break;
78*4882a593Smuzhiyun 	case UDA134X_DATA000:
79*4882a593Smuzhiyun 	case UDA134X_DATA001:
80*4882a593Smuzhiyun 	case UDA134X_DATA010:
81*4882a593Smuzhiyun 	case UDA134X_DATA011:
82*4882a593Smuzhiyun 		addr = UDA134X_DATA0_ADDR;
83*4882a593Smuzhiyun 		data |= (reg - UDA134X_DATA000) << 6;
84*4882a593Smuzhiyun 		break;
85*4882a593Smuzhiyun 	case UDA134X_DATA1:
86*4882a593Smuzhiyun 		addr = UDA134X_DATA1_ADDR;
87*4882a593Smuzhiyun 		break;
88*4882a593Smuzhiyun 	default:
89*4882a593Smuzhiyun 		/* It's an extended address register */
90*4882a593Smuzhiyun 		addr =  (reg | UDA134X_EXTADDR_PREFIX);
91*4882a593Smuzhiyun 
92*4882a593Smuzhiyun 		ret = l3_write(&pd->l3,
93*4882a593Smuzhiyun 			       UDA134X_DATA0_ADDR, &addr, 1);
94*4882a593Smuzhiyun 		if (ret != 1)
95*4882a593Smuzhiyun 			return -EIO;
96*4882a593Smuzhiyun 
97*4882a593Smuzhiyun 		addr = UDA134X_DATA0_ADDR;
98*4882a593Smuzhiyun 		data = (value | UDA134X_EXTDATA_PREFIX);
99*4882a593Smuzhiyun 		break;
100*4882a593Smuzhiyun 	}
101*4882a593Smuzhiyun 
102*4882a593Smuzhiyun 	ret = l3_write(&pd->l3,
103*4882a593Smuzhiyun 		       addr, &data, 1);
104*4882a593Smuzhiyun 	if (ret != 1)
105*4882a593Smuzhiyun 		return -EIO;
106*4882a593Smuzhiyun 
107*4882a593Smuzhiyun 	return 0;
108*4882a593Smuzhiyun }
109*4882a593Smuzhiyun 
uda134x_reset(struct snd_soc_component * component)110*4882a593Smuzhiyun static inline void uda134x_reset(struct snd_soc_component *component)
111*4882a593Smuzhiyun {
112*4882a593Smuzhiyun 	struct uda134x_priv *uda134x = snd_soc_component_get_drvdata(component);
113*4882a593Smuzhiyun 	unsigned int mask = 1<<6;
114*4882a593Smuzhiyun 
115*4882a593Smuzhiyun 	regmap_update_bits(uda134x->regmap, UDA134X_STATUS0, mask, mask);
116*4882a593Smuzhiyun 	msleep(1);
117*4882a593Smuzhiyun 	regmap_update_bits(uda134x->regmap, UDA134X_STATUS0, mask, 0);
118*4882a593Smuzhiyun }
119*4882a593Smuzhiyun 
uda134x_mute(struct snd_soc_dai * dai,int mute,int direction)120*4882a593Smuzhiyun static int uda134x_mute(struct snd_soc_dai *dai, int mute, int direction)
121*4882a593Smuzhiyun {
122*4882a593Smuzhiyun 	struct uda134x_priv *uda134x = snd_soc_component_get_drvdata(dai->component);
123*4882a593Smuzhiyun 	unsigned int mask = 1<<2;
124*4882a593Smuzhiyun 	unsigned int val;
125*4882a593Smuzhiyun 
126*4882a593Smuzhiyun 	pr_debug("%s mute: %d\n", __func__, mute);
127*4882a593Smuzhiyun 
128*4882a593Smuzhiyun 	if (mute)
129*4882a593Smuzhiyun 		val = mask;
130*4882a593Smuzhiyun 	else
131*4882a593Smuzhiyun 		val = 0;
132*4882a593Smuzhiyun 
133*4882a593Smuzhiyun 	return regmap_update_bits(uda134x->regmap, UDA134X_DATA010, mask, val);
134*4882a593Smuzhiyun }
135*4882a593Smuzhiyun 
uda134x_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)136*4882a593Smuzhiyun static int uda134x_startup(struct snd_pcm_substream *substream,
137*4882a593Smuzhiyun 	struct snd_soc_dai *dai)
138*4882a593Smuzhiyun {
139*4882a593Smuzhiyun 	struct snd_soc_component *component = dai->component;
140*4882a593Smuzhiyun 	struct uda134x_priv *uda134x = snd_soc_component_get_drvdata(component);
141*4882a593Smuzhiyun 	struct snd_pcm_runtime *master_runtime;
142*4882a593Smuzhiyun 
143*4882a593Smuzhiyun 	if (uda134x->master_substream) {
144*4882a593Smuzhiyun 		master_runtime = uda134x->master_substream->runtime;
145*4882a593Smuzhiyun 
146*4882a593Smuzhiyun 		pr_debug("%s constraining to %d bits at %d\n", __func__,
147*4882a593Smuzhiyun 			 master_runtime->sample_bits,
148*4882a593Smuzhiyun 			 master_runtime->rate);
149*4882a593Smuzhiyun 
150*4882a593Smuzhiyun 		snd_pcm_hw_constraint_single(substream->runtime,
151*4882a593Smuzhiyun 					     SNDRV_PCM_HW_PARAM_RATE,
152*4882a593Smuzhiyun 					     master_runtime->rate);
153*4882a593Smuzhiyun 
154*4882a593Smuzhiyun 		snd_pcm_hw_constraint_single(substream->runtime,
155*4882a593Smuzhiyun 					     SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
156*4882a593Smuzhiyun 					     master_runtime->sample_bits);
157*4882a593Smuzhiyun 
158*4882a593Smuzhiyun 		uda134x->slave_substream = substream;
159*4882a593Smuzhiyun 	} else
160*4882a593Smuzhiyun 		uda134x->master_substream = substream;
161*4882a593Smuzhiyun 
162*4882a593Smuzhiyun 	return 0;
163*4882a593Smuzhiyun }
164*4882a593Smuzhiyun 
uda134x_shutdown(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)165*4882a593Smuzhiyun static void uda134x_shutdown(struct snd_pcm_substream *substream,
166*4882a593Smuzhiyun 	struct snd_soc_dai *dai)
167*4882a593Smuzhiyun {
168*4882a593Smuzhiyun 	struct snd_soc_component *component = dai->component;
169*4882a593Smuzhiyun 	struct uda134x_priv *uda134x = snd_soc_component_get_drvdata(component);
170*4882a593Smuzhiyun 
171*4882a593Smuzhiyun 	if (uda134x->master_substream == substream)
172*4882a593Smuzhiyun 		uda134x->master_substream = uda134x->slave_substream;
173*4882a593Smuzhiyun 
174*4882a593Smuzhiyun 	uda134x->slave_substream = NULL;
175*4882a593Smuzhiyun }
176*4882a593Smuzhiyun 
uda134x_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)177*4882a593Smuzhiyun static int uda134x_hw_params(struct snd_pcm_substream *substream,
178*4882a593Smuzhiyun 	struct snd_pcm_hw_params *params,
179*4882a593Smuzhiyun 	struct snd_soc_dai *dai)
180*4882a593Smuzhiyun {
181*4882a593Smuzhiyun 	struct snd_soc_component *component = dai->component;
182*4882a593Smuzhiyun 	struct uda134x_priv *uda134x = snd_soc_component_get_drvdata(component);
183*4882a593Smuzhiyun 	unsigned int hw_params = 0;
184*4882a593Smuzhiyun 
185*4882a593Smuzhiyun 	if (substream == uda134x->slave_substream) {
186*4882a593Smuzhiyun 		pr_debug("%s ignoring hw_params for slave substream\n",
187*4882a593Smuzhiyun 			 __func__);
188*4882a593Smuzhiyun 		return 0;
189*4882a593Smuzhiyun 	}
190*4882a593Smuzhiyun 
191*4882a593Smuzhiyun 	pr_debug("%s sysclk: %d, rate:%d\n", __func__,
192*4882a593Smuzhiyun 		 uda134x->sysclk, params_rate(params));
193*4882a593Smuzhiyun 
194*4882a593Smuzhiyun 	/* set SYSCLK / fs ratio */
195*4882a593Smuzhiyun 	switch (uda134x->sysclk / params_rate(params)) {
196*4882a593Smuzhiyun 	case 512:
197*4882a593Smuzhiyun 		break;
198*4882a593Smuzhiyun 	case 384:
199*4882a593Smuzhiyun 		hw_params |= (1<<4);
200*4882a593Smuzhiyun 		break;
201*4882a593Smuzhiyun 	case 256:
202*4882a593Smuzhiyun 		hw_params |= (1<<5);
203*4882a593Smuzhiyun 		break;
204*4882a593Smuzhiyun 	default:
205*4882a593Smuzhiyun 		printk(KERN_ERR "%s unsupported fs\n", __func__);
206*4882a593Smuzhiyun 		return -EINVAL;
207*4882a593Smuzhiyun 	}
208*4882a593Smuzhiyun 
209*4882a593Smuzhiyun 	pr_debug("%s dai_fmt: %d, params_format:%d\n", __func__,
210*4882a593Smuzhiyun 		 uda134x->dai_fmt, params_format(params));
211*4882a593Smuzhiyun 
212*4882a593Smuzhiyun 	/* set DAI format and word length */
213*4882a593Smuzhiyun 	switch (uda134x->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
214*4882a593Smuzhiyun 	case SND_SOC_DAIFMT_I2S:
215*4882a593Smuzhiyun 		break;
216*4882a593Smuzhiyun 	case SND_SOC_DAIFMT_RIGHT_J:
217*4882a593Smuzhiyun 		switch (params_width(params)) {
218*4882a593Smuzhiyun 		case 16:
219*4882a593Smuzhiyun 			hw_params |= (1<<1);
220*4882a593Smuzhiyun 			break;
221*4882a593Smuzhiyun 		case 18:
222*4882a593Smuzhiyun 			hw_params |= (1<<2);
223*4882a593Smuzhiyun 			break;
224*4882a593Smuzhiyun 		case 20:
225*4882a593Smuzhiyun 			hw_params |= ((1<<2) | (1<<1));
226*4882a593Smuzhiyun 			break;
227*4882a593Smuzhiyun 		default:
228*4882a593Smuzhiyun 			printk(KERN_ERR "%s unsupported format (right)\n",
229*4882a593Smuzhiyun 			       __func__);
230*4882a593Smuzhiyun 			return -EINVAL;
231*4882a593Smuzhiyun 		}
232*4882a593Smuzhiyun 		break;
233*4882a593Smuzhiyun 	case SND_SOC_DAIFMT_LEFT_J:
234*4882a593Smuzhiyun 		hw_params |= (1<<3);
235*4882a593Smuzhiyun 		break;
236*4882a593Smuzhiyun 	default:
237*4882a593Smuzhiyun 		printk(KERN_ERR "%s unsupported format\n", __func__);
238*4882a593Smuzhiyun 		return -EINVAL;
239*4882a593Smuzhiyun 	}
240*4882a593Smuzhiyun 
241*4882a593Smuzhiyun 	return regmap_update_bits(uda134x->regmap, UDA134X_STATUS0,
242*4882a593Smuzhiyun 		STATUS0_SYSCLK_MASK | STATUS0_DAIFMT_MASK, hw_params);
243*4882a593Smuzhiyun }
244*4882a593Smuzhiyun 
uda134x_set_dai_sysclk(struct snd_soc_dai * codec_dai,int clk_id,unsigned int freq,int dir)245*4882a593Smuzhiyun static int uda134x_set_dai_sysclk(struct snd_soc_dai *codec_dai,
246*4882a593Smuzhiyun 				  int clk_id, unsigned int freq, int dir)
247*4882a593Smuzhiyun {
248*4882a593Smuzhiyun 	struct snd_soc_component *component = codec_dai->component;
249*4882a593Smuzhiyun 	struct uda134x_priv *uda134x = snd_soc_component_get_drvdata(component);
250*4882a593Smuzhiyun 
251*4882a593Smuzhiyun 	pr_debug("%s clk_id: %d, freq: %u, dir: %d\n", __func__,
252*4882a593Smuzhiyun 		 clk_id, freq, dir);
253*4882a593Smuzhiyun 
254*4882a593Smuzhiyun 	/* Anything between 256fs*8Khz and 512fs*48Khz should be acceptable
255*4882a593Smuzhiyun 	   because the codec is slave. Of course limitations of the clock
256*4882a593Smuzhiyun 	   master (the IIS controller) apply.
257*4882a593Smuzhiyun 	   We'll error out on set_hw_params if it's not OK */
258*4882a593Smuzhiyun 	if ((freq >= (256 * 8000)) && (freq <= (512 * 48000))) {
259*4882a593Smuzhiyun 		uda134x->sysclk = freq;
260*4882a593Smuzhiyun 		return 0;
261*4882a593Smuzhiyun 	}
262*4882a593Smuzhiyun 
263*4882a593Smuzhiyun 	printk(KERN_ERR "%s unsupported sysclk\n", __func__);
264*4882a593Smuzhiyun 	return -EINVAL;
265*4882a593Smuzhiyun }
266*4882a593Smuzhiyun 
uda134x_set_dai_fmt(struct snd_soc_dai * codec_dai,unsigned int fmt)267*4882a593Smuzhiyun static int uda134x_set_dai_fmt(struct snd_soc_dai *codec_dai,
268*4882a593Smuzhiyun 			       unsigned int fmt)
269*4882a593Smuzhiyun {
270*4882a593Smuzhiyun 	struct snd_soc_component *component = codec_dai->component;
271*4882a593Smuzhiyun 	struct uda134x_priv *uda134x = snd_soc_component_get_drvdata(component);
272*4882a593Smuzhiyun 
273*4882a593Smuzhiyun 	pr_debug("%s fmt: %08X\n", __func__, fmt);
274*4882a593Smuzhiyun 
275*4882a593Smuzhiyun 	/* codec supports only full slave mode */
276*4882a593Smuzhiyun 	if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) != SND_SOC_DAIFMT_CBS_CFS) {
277*4882a593Smuzhiyun 		printk(KERN_ERR "%s unsupported slave mode\n", __func__);
278*4882a593Smuzhiyun 		return -EINVAL;
279*4882a593Smuzhiyun 	}
280*4882a593Smuzhiyun 
281*4882a593Smuzhiyun 	/* no support for clock inversion */
282*4882a593Smuzhiyun 	if ((fmt & SND_SOC_DAIFMT_INV_MASK) != SND_SOC_DAIFMT_NB_NF) {
283*4882a593Smuzhiyun 		printk(KERN_ERR "%s unsupported clock inversion\n", __func__);
284*4882a593Smuzhiyun 		return -EINVAL;
285*4882a593Smuzhiyun 	}
286*4882a593Smuzhiyun 
287*4882a593Smuzhiyun 	/* We can't setup DAI format here as it depends on the word bit num */
288*4882a593Smuzhiyun 	/* so let's just store the value for later */
289*4882a593Smuzhiyun 	uda134x->dai_fmt = fmt;
290*4882a593Smuzhiyun 
291*4882a593Smuzhiyun 	return 0;
292*4882a593Smuzhiyun }
293*4882a593Smuzhiyun 
uda134x_set_bias_level(struct snd_soc_component * component,enum snd_soc_bias_level level)294*4882a593Smuzhiyun static int uda134x_set_bias_level(struct snd_soc_component *component,
295*4882a593Smuzhiyun 				  enum snd_soc_bias_level level)
296*4882a593Smuzhiyun {
297*4882a593Smuzhiyun 	struct uda134x_priv *uda134x = snd_soc_component_get_drvdata(component);
298*4882a593Smuzhiyun 	struct uda134x_platform_data *pd = uda134x->pd;
299*4882a593Smuzhiyun 	pr_debug("%s bias level %d\n", __func__, level);
300*4882a593Smuzhiyun 
301*4882a593Smuzhiyun 	switch (level) {
302*4882a593Smuzhiyun 	case SND_SOC_BIAS_ON:
303*4882a593Smuzhiyun 		break;
304*4882a593Smuzhiyun 	case SND_SOC_BIAS_PREPARE:
305*4882a593Smuzhiyun 		/* power on */
306*4882a593Smuzhiyun 		if (pd->power) {
307*4882a593Smuzhiyun 			pd->power(1);
308*4882a593Smuzhiyun 			regcache_sync(uda134x->regmap);
309*4882a593Smuzhiyun 		}
310*4882a593Smuzhiyun 		break;
311*4882a593Smuzhiyun 	case SND_SOC_BIAS_STANDBY:
312*4882a593Smuzhiyun 		break;
313*4882a593Smuzhiyun 	case SND_SOC_BIAS_OFF:
314*4882a593Smuzhiyun 		/* power off */
315*4882a593Smuzhiyun 		if (pd->power) {
316*4882a593Smuzhiyun 			pd->power(0);
317*4882a593Smuzhiyun 			regcache_mark_dirty(uda134x->regmap);
318*4882a593Smuzhiyun 		}
319*4882a593Smuzhiyun 		break;
320*4882a593Smuzhiyun 	}
321*4882a593Smuzhiyun 	return 0;
322*4882a593Smuzhiyun }
323*4882a593Smuzhiyun 
324*4882a593Smuzhiyun static const char *uda134x_dsp_setting[] = {"Flat", "Minimum1",
325*4882a593Smuzhiyun 					    "Minimum2", "Maximum"};
326*4882a593Smuzhiyun static const char *uda134x_deemph[] = {"None", "32Khz", "44.1Khz", "48Khz"};
327*4882a593Smuzhiyun static const char *uda134x_mixmode[] = {"Differential", "Analog1",
328*4882a593Smuzhiyun 					"Analog2", "Both"};
329*4882a593Smuzhiyun 
330*4882a593Smuzhiyun static const struct soc_enum uda134x_mixer_enum[] = {
331*4882a593Smuzhiyun SOC_ENUM_SINGLE(UDA134X_DATA010, 0, 0x04, uda134x_dsp_setting),
332*4882a593Smuzhiyun SOC_ENUM_SINGLE(UDA134X_DATA010, 3, 0x04, uda134x_deemph),
333*4882a593Smuzhiyun SOC_ENUM_SINGLE(UDA134X_EA010, 0, 0x04, uda134x_mixmode),
334*4882a593Smuzhiyun };
335*4882a593Smuzhiyun 
336*4882a593Smuzhiyun static const struct snd_kcontrol_new uda1341_snd_controls[] = {
337*4882a593Smuzhiyun SOC_SINGLE("Master Playback Volume", UDA134X_DATA000, 0, 0x3F, 1),
338*4882a593Smuzhiyun SOC_SINGLE("Capture Volume", UDA134X_EA010, 2, 0x07, 0),
339*4882a593Smuzhiyun SOC_SINGLE("Analog1 Volume", UDA134X_EA000, 0, 0x1F, 1),
340*4882a593Smuzhiyun SOC_SINGLE("Analog2 Volume", UDA134X_EA001, 0, 0x1F, 1),
341*4882a593Smuzhiyun 
342*4882a593Smuzhiyun SOC_SINGLE("Mic Sensitivity", UDA134X_EA010, 2, 7, 0),
343*4882a593Smuzhiyun SOC_SINGLE("Mic Volume", UDA134X_EA101, 0, 0x1F, 0),
344*4882a593Smuzhiyun 
345*4882a593Smuzhiyun SOC_SINGLE("Tone Control - Bass", UDA134X_DATA001, 2, 0xF, 0),
346*4882a593Smuzhiyun SOC_SINGLE("Tone Control - Treble", UDA134X_DATA001, 0, 3, 0),
347*4882a593Smuzhiyun 
348*4882a593Smuzhiyun SOC_ENUM("Sound Processing Filter", uda134x_mixer_enum[0]),
349*4882a593Smuzhiyun SOC_ENUM("PCM Playback De-emphasis", uda134x_mixer_enum[1]),
350*4882a593Smuzhiyun SOC_ENUM("Input Mux", uda134x_mixer_enum[2]),
351*4882a593Smuzhiyun 
352*4882a593Smuzhiyun SOC_SINGLE("AGC Switch", UDA134X_EA100, 4, 1, 0),
353*4882a593Smuzhiyun SOC_SINGLE("AGC Target Volume", UDA134X_EA110, 0, 0x03, 1),
354*4882a593Smuzhiyun SOC_SINGLE("AGC Timing", UDA134X_EA110, 2, 0x07, 0),
355*4882a593Smuzhiyun 
356*4882a593Smuzhiyun SOC_SINGLE("DAC +6dB Switch", UDA134X_STATUS1, 6, 1, 0),
357*4882a593Smuzhiyun SOC_SINGLE("ADC +6dB Switch", UDA134X_STATUS1, 5, 1, 0),
358*4882a593Smuzhiyun SOC_SINGLE("ADC Polarity Switch", UDA134X_STATUS1, 4, 1, 0),
359*4882a593Smuzhiyun SOC_SINGLE("DAC Polarity Switch", UDA134X_STATUS1, 3, 1, 0),
360*4882a593Smuzhiyun SOC_SINGLE("Double Speed Playback Switch", UDA134X_STATUS1, 2, 1, 0),
361*4882a593Smuzhiyun SOC_SINGLE("DC Filter Enable Switch", UDA134X_STATUS0, 0, 1, 0),
362*4882a593Smuzhiyun };
363*4882a593Smuzhiyun 
364*4882a593Smuzhiyun static const struct snd_kcontrol_new uda1340_snd_controls[] = {
365*4882a593Smuzhiyun SOC_SINGLE("Master Playback Volume", UDA134X_DATA000, 0, 0x3F, 1),
366*4882a593Smuzhiyun 
367*4882a593Smuzhiyun SOC_SINGLE("Tone Control - Bass", UDA134X_DATA001, 2, 0xF, 0),
368*4882a593Smuzhiyun SOC_SINGLE("Tone Control - Treble", UDA134X_DATA001, 0, 3, 0),
369*4882a593Smuzhiyun 
370*4882a593Smuzhiyun SOC_ENUM("Sound Processing Filter", uda134x_mixer_enum[0]),
371*4882a593Smuzhiyun SOC_ENUM("PCM Playback De-emphasis", uda134x_mixer_enum[1]),
372*4882a593Smuzhiyun 
373*4882a593Smuzhiyun SOC_SINGLE("DC Filter Enable Switch", UDA134X_STATUS0, 0, 1, 0),
374*4882a593Smuzhiyun };
375*4882a593Smuzhiyun 
376*4882a593Smuzhiyun static const struct snd_kcontrol_new uda1345_snd_controls[] = {
377*4882a593Smuzhiyun SOC_SINGLE("Master Playback Volume", UDA134X_DATA000, 0, 0x3F, 1),
378*4882a593Smuzhiyun 
379*4882a593Smuzhiyun SOC_ENUM("PCM Playback De-emphasis", uda134x_mixer_enum[1]),
380*4882a593Smuzhiyun 
381*4882a593Smuzhiyun SOC_SINGLE("DC Filter Enable Switch", UDA134X_STATUS0, 0, 1, 0),
382*4882a593Smuzhiyun };
383*4882a593Smuzhiyun 
384*4882a593Smuzhiyun /* UDA1341 has the DAC/ADC power down in STATUS1 */
385*4882a593Smuzhiyun static const struct snd_soc_dapm_widget uda1341_dapm_widgets[] = {
386*4882a593Smuzhiyun 	SND_SOC_DAPM_DAC("DAC", "Playback", UDA134X_STATUS1, 0, 0),
387*4882a593Smuzhiyun 	SND_SOC_DAPM_ADC("ADC", "Capture", UDA134X_STATUS1, 1, 0),
388*4882a593Smuzhiyun };
389*4882a593Smuzhiyun 
390*4882a593Smuzhiyun /* UDA1340/4/5 has the DAC/ADC pwoer down in DATA0 11 */
391*4882a593Smuzhiyun static const struct snd_soc_dapm_widget uda1340_dapm_widgets[] = {
392*4882a593Smuzhiyun 	SND_SOC_DAPM_DAC("DAC", "Playback", UDA134X_DATA011, 0, 0),
393*4882a593Smuzhiyun 	SND_SOC_DAPM_ADC("ADC", "Capture", UDA134X_DATA011, 1, 0),
394*4882a593Smuzhiyun };
395*4882a593Smuzhiyun 
396*4882a593Smuzhiyun /* Common DAPM widgets */
397*4882a593Smuzhiyun static const struct snd_soc_dapm_widget uda134x_dapm_widgets[] = {
398*4882a593Smuzhiyun 	SND_SOC_DAPM_INPUT("VINL1"),
399*4882a593Smuzhiyun 	SND_SOC_DAPM_INPUT("VINR1"),
400*4882a593Smuzhiyun 	SND_SOC_DAPM_INPUT("VINL2"),
401*4882a593Smuzhiyun 	SND_SOC_DAPM_INPUT("VINR2"),
402*4882a593Smuzhiyun 	SND_SOC_DAPM_OUTPUT("VOUTL"),
403*4882a593Smuzhiyun 	SND_SOC_DAPM_OUTPUT("VOUTR"),
404*4882a593Smuzhiyun };
405*4882a593Smuzhiyun 
406*4882a593Smuzhiyun static const struct snd_soc_dapm_route uda134x_dapm_routes[] = {
407*4882a593Smuzhiyun 	{ "ADC", NULL, "VINL1" },
408*4882a593Smuzhiyun 	{ "ADC", NULL, "VINR1" },
409*4882a593Smuzhiyun 	{ "ADC", NULL, "VINL2" },
410*4882a593Smuzhiyun 	{ "ADC", NULL, "VINR2" },
411*4882a593Smuzhiyun 	{ "VOUTL", NULL, "DAC" },
412*4882a593Smuzhiyun 	{ "VOUTR", NULL, "DAC" },
413*4882a593Smuzhiyun };
414*4882a593Smuzhiyun 
415*4882a593Smuzhiyun static const struct snd_soc_dai_ops uda134x_dai_ops = {
416*4882a593Smuzhiyun 	.startup	= uda134x_startup,
417*4882a593Smuzhiyun 	.shutdown	= uda134x_shutdown,
418*4882a593Smuzhiyun 	.hw_params	= uda134x_hw_params,
419*4882a593Smuzhiyun 	.mute_stream	= uda134x_mute,
420*4882a593Smuzhiyun 	.set_sysclk	= uda134x_set_dai_sysclk,
421*4882a593Smuzhiyun 	.set_fmt	= uda134x_set_dai_fmt,
422*4882a593Smuzhiyun 	.no_capture_mute = 1,
423*4882a593Smuzhiyun };
424*4882a593Smuzhiyun 
425*4882a593Smuzhiyun static struct snd_soc_dai_driver uda134x_dai = {
426*4882a593Smuzhiyun 	.name = "uda134x-hifi",
427*4882a593Smuzhiyun 	/* playback capabilities */
428*4882a593Smuzhiyun 	.playback = {
429*4882a593Smuzhiyun 		.stream_name = "Playback",
430*4882a593Smuzhiyun 		.channels_min = 1,
431*4882a593Smuzhiyun 		.channels_max = 2,
432*4882a593Smuzhiyun 		.rates = UDA134X_RATES,
433*4882a593Smuzhiyun 		.formats = UDA134X_FORMATS,
434*4882a593Smuzhiyun 	},
435*4882a593Smuzhiyun 	/* capture capabilities */
436*4882a593Smuzhiyun 	.capture = {
437*4882a593Smuzhiyun 		.stream_name = "Capture",
438*4882a593Smuzhiyun 		.channels_min = 1,
439*4882a593Smuzhiyun 		.channels_max = 2,
440*4882a593Smuzhiyun 		.rates = UDA134X_RATES,
441*4882a593Smuzhiyun 		.formats = UDA134X_FORMATS,
442*4882a593Smuzhiyun 	},
443*4882a593Smuzhiyun 	/* pcm operations */
444*4882a593Smuzhiyun 	.ops = &uda134x_dai_ops,
445*4882a593Smuzhiyun };
446*4882a593Smuzhiyun 
uda134x_soc_probe(struct snd_soc_component * component)447*4882a593Smuzhiyun static int uda134x_soc_probe(struct snd_soc_component *component)
448*4882a593Smuzhiyun {
449*4882a593Smuzhiyun 	struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
450*4882a593Smuzhiyun 	struct uda134x_priv *uda134x = snd_soc_component_get_drvdata(component);
451*4882a593Smuzhiyun 	struct uda134x_platform_data *pd = uda134x->pd;
452*4882a593Smuzhiyun 	const struct snd_soc_dapm_widget *widgets;
453*4882a593Smuzhiyun 	unsigned num_widgets;
454*4882a593Smuzhiyun 	int ret;
455*4882a593Smuzhiyun 
456*4882a593Smuzhiyun 	printk(KERN_INFO "UDA134X SoC Audio Codec\n");
457*4882a593Smuzhiyun 
458*4882a593Smuzhiyun 	switch (pd->model) {
459*4882a593Smuzhiyun 	case UDA134X_UDA1340:
460*4882a593Smuzhiyun 	case UDA134X_UDA1341:
461*4882a593Smuzhiyun 	case UDA134X_UDA1344:
462*4882a593Smuzhiyun 	case UDA134X_UDA1345:
463*4882a593Smuzhiyun 		break;
464*4882a593Smuzhiyun 	default:
465*4882a593Smuzhiyun 		printk(KERN_ERR "UDA134X SoC codec: "
466*4882a593Smuzhiyun 		       "unsupported model %d\n",
467*4882a593Smuzhiyun 			pd->model);
468*4882a593Smuzhiyun 		return -EINVAL;
469*4882a593Smuzhiyun 	}
470*4882a593Smuzhiyun 
471*4882a593Smuzhiyun 	if (pd->power)
472*4882a593Smuzhiyun 		pd->power(1);
473*4882a593Smuzhiyun 
474*4882a593Smuzhiyun 	uda134x_reset(component);
475*4882a593Smuzhiyun 
476*4882a593Smuzhiyun 	if (pd->model == UDA134X_UDA1341) {
477*4882a593Smuzhiyun 		widgets = uda1341_dapm_widgets;
478*4882a593Smuzhiyun 		num_widgets = ARRAY_SIZE(uda1341_dapm_widgets);
479*4882a593Smuzhiyun 	} else {
480*4882a593Smuzhiyun 		widgets = uda1340_dapm_widgets;
481*4882a593Smuzhiyun 		num_widgets = ARRAY_SIZE(uda1340_dapm_widgets);
482*4882a593Smuzhiyun 	}
483*4882a593Smuzhiyun 
484*4882a593Smuzhiyun 	ret = snd_soc_dapm_new_controls(dapm, widgets, num_widgets);
485*4882a593Smuzhiyun 	if (ret) {
486*4882a593Smuzhiyun 		printk(KERN_ERR "%s failed to register dapm controls: %d",
487*4882a593Smuzhiyun 			__func__, ret);
488*4882a593Smuzhiyun 		return ret;
489*4882a593Smuzhiyun 	}
490*4882a593Smuzhiyun 
491*4882a593Smuzhiyun 	switch (pd->model) {
492*4882a593Smuzhiyun 	case UDA134X_UDA1340:
493*4882a593Smuzhiyun 	case UDA134X_UDA1344:
494*4882a593Smuzhiyun 		ret = snd_soc_add_component_controls(component, uda1340_snd_controls,
495*4882a593Smuzhiyun 					ARRAY_SIZE(uda1340_snd_controls));
496*4882a593Smuzhiyun 	break;
497*4882a593Smuzhiyun 	case UDA134X_UDA1341:
498*4882a593Smuzhiyun 		ret = snd_soc_add_component_controls(component, uda1341_snd_controls,
499*4882a593Smuzhiyun 					ARRAY_SIZE(uda1341_snd_controls));
500*4882a593Smuzhiyun 	break;
501*4882a593Smuzhiyun 	case UDA134X_UDA1345:
502*4882a593Smuzhiyun 		ret = snd_soc_add_component_controls(component, uda1345_snd_controls,
503*4882a593Smuzhiyun 					ARRAY_SIZE(uda1345_snd_controls));
504*4882a593Smuzhiyun 	break;
505*4882a593Smuzhiyun 	default:
506*4882a593Smuzhiyun 		printk(KERN_ERR "%s unknown codec type: %d",
507*4882a593Smuzhiyun 			__func__, pd->model);
508*4882a593Smuzhiyun 		return -EINVAL;
509*4882a593Smuzhiyun 	}
510*4882a593Smuzhiyun 
511*4882a593Smuzhiyun 	if (ret < 0) {
512*4882a593Smuzhiyun 		printk(KERN_ERR "UDA134X: failed to register controls\n");
513*4882a593Smuzhiyun 		return ret;
514*4882a593Smuzhiyun 	}
515*4882a593Smuzhiyun 
516*4882a593Smuzhiyun 	return 0;
517*4882a593Smuzhiyun }
518*4882a593Smuzhiyun 
519*4882a593Smuzhiyun static const struct snd_soc_component_driver soc_component_dev_uda134x = {
520*4882a593Smuzhiyun 	.probe			= uda134x_soc_probe,
521*4882a593Smuzhiyun 	.set_bias_level		= uda134x_set_bias_level,
522*4882a593Smuzhiyun 	.dapm_widgets		= uda134x_dapm_widgets,
523*4882a593Smuzhiyun 	.num_dapm_widgets	= ARRAY_SIZE(uda134x_dapm_widgets),
524*4882a593Smuzhiyun 	.dapm_routes		= uda134x_dapm_routes,
525*4882a593Smuzhiyun 	.num_dapm_routes	= ARRAY_SIZE(uda134x_dapm_routes),
526*4882a593Smuzhiyun 	.suspend_bias_off	= 1,
527*4882a593Smuzhiyun 	.idle_bias_on		= 1,
528*4882a593Smuzhiyun 	.use_pmdown_time	= 1,
529*4882a593Smuzhiyun 	.endianness		= 1,
530*4882a593Smuzhiyun 	.non_legacy_dai_naming	= 1,
531*4882a593Smuzhiyun };
532*4882a593Smuzhiyun 
533*4882a593Smuzhiyun static const struct regmap_config uda134x_regmap_config = {
534*4882a593Smuzhiyun 	.reg_bits = 8,
535*4882a593Smuzhiyun 	.val_bits = 8,
536*4882a593Smuzhiyun 	.max_register = UDA134X_DATA1,
537*4882a593Smuzhiyun 	.reg_defaults = uda134x_reg_defaults,
538*4882a593Smuzhiyun 	.num_reg_defaults = ARRAY_SIZE(uda134x_reg_defaults),
539*4882a593Smuzhiyun 	.cache_type = REGCACHE_RBTREE,
540*4882a593Smuzhiyun 
541*4882a593Smuzhiyun 	.reg_write = uda134x_regmap_write,
542*4882a593Smuzhiyun };
543*4882a593Smuzhiyun 
uda134x_codec_probe(struct platform_device * pdev)544*4882a593Smuzhiyun static int uda134x_codec_probe(struct platform_device *pdev)
545*4882a593Smuzhiyun {
546*4882a593Smuzhiyun 	struct uda134x_platform_data *pd = pdev->dev.platform_data;
547*4882a593Smuzhiyun 	struct uda134x_priv *uda134x;
548*4882a593Smuzhiyun 	int ret;
549*4882a593Smuzhiyun 
550*4882a593Smuzhiyun 	if (!pd) {
551*4882a593Smuzhiyun 		dev_err(&pdev->dev, "Missing L3 bitbang function\n");
552*4882a593Smuzhiyun 		return -ENODEV;
553*4882a593Smuzhiyun 	}
554*4882a593Smuzhiyun 
555*4882a593Smuzhiyun 	uda134x = devm_kzalloc(&pdev->dev, sizeof(*uda134x), GFP_KERNEL);
556*4882a593Smuzhiyun 	if (!uda134x)
557*4882a593Smuzhiyun 		return -ENOMEM;
558*4882a593Smuzhiyun 
559*4882a593Smuzhiyun 	uda134x->pd = pd;
560*4882a593Smuzhiyun 	platform_set_drvdata(pdev, uda134x);
561*4882a593Smuzhiyun 
562*4882a593Smuzhiyun 	if (pd->l3.use_gpios) {
563*4882a593Smuzhiyun 		ret = l3_set_gpio_ops(&pdev->dev, &uda134x->pd->l3);
564*4882a593Smuzhiyun 		if (ret < 0)
565*4882a593Smuzhiyun 			return ret;
566*4882a593Smuzhiyun 	}
567*4882a593Smuzhiyun 
568*4882a593Smuzhiyun 	uda134x->regmap = devm_regmap_init(&pdev->dev, NULL, pd,
569*4882a593Smuzhiyun 		&uda134x_regmap_config);
570*4882a593Smuzhiyun 	if (IS_ERR(uda134x->regmap))
571*4882a593Smuzhiyun 		return PTR_ERR(uda134x->regmap);
572*4882a593Smuzhiyun 
573*4882a593Smuzhiyun 	return devm_snd_soc_register_component(&pdev->dev,
574*4882a593Smuzhiyun 			&soc_component_dev_uda134x, &uda134x_dai, 1);
575*4882a593Smuzhiyun }
576*4882a593Smuzhiyun 
577*4882a593Smuzhiyun static struct platform_driver uda134x_codec_driver = {
578*4882a593Smuzhiyun 	.driver = {
579*4882a593Smuzhiyun 		.name = "uda134x-codec",
580*4882a593Smuzhiyun 	},
581*4882a593Smuzhiyun 	.probe = uda134x_codec_probe,
582*4882a593Smuzhiyun };
583*4882a593Smuzhiyun 
584*4882a593Smuzhiyun module_platform_driver(uda134x_codec_driver);
585*4882a593Smuzhiyun 
586*4882a593Smuzhiyun MODULE_DESCRIPTION("UDA134X ALSA soc codec driver");
587*4882a593Smuzhiyun MODULE_AUTHOR("Zoltan Devai, Christian Pellegrin <chripell@evolware.org>");
588*4882a593Smuzhiyun MODULE_LICENSE("GPL");
589