1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun //
3*4882a593Smuzhiyun // uda1334.c -- UDA1334 ALSA SoC Audio driver
4*4882a593Smuzhiyun //
5*4882a593Smuzhiyun // Based on WM8523 ALSA SoC Audio driver written by Mark Brown
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <linux/module.h>
8*4882a593Smuzhiyun #include <linux/moduleparam.h>
9*4882a593Smuzhiyun #include <linux/init.h>
10*4882a593Smuzhiyun #include <linux/delay.h>
11*4882a593Smuzhiyun #include <linux/slab.h>
12*4882a593Smuzhiyun #include <linux/gpio/consumer.h>
13*4882a593Smuzhiyun #include <linux/of_device.h>
14*4882a593Smuzhiyun #include <sound/core.h>
15*4882a593Smuzhiyun #include <sound/pcm.h>
16*4882a593Smuzhiyun #include <sound/pcm_params.h>
17*4882a593Smuzhiyun #include <sound/soc.h>
18*4882a593Smuzhiyun #include <sound/initval.h>
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun #define UDA1334_NUM_RATES 6
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun /* codec private data */
23*4882a593Smuzhiyun struct uda1334_priv {
24*4882a593Smuzhiyun struct gpio_desc *mute;
25*4882a593Smuzhiyun struct gpio_desc *deemph;
26*4882a593Smuzhiyun unsigned int sysclk;
27*4882a593Smuzhiyun unsigned int rate_constraint_list[UDA1334_NUM_RATES];
28*4882a593Smuzhiyun struct snd_pcm_hw_constraint_list rate_constraint;
29*4882a593Smuzhiyun };
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun static const struct snd_soc_dapm_widget uda1334_dapm_widgets[] = {
32*4882a593Smuzhiyun SND_SOC_DAPM_DAC("DAC", "Playback", SND_SOC_NOPM, 0, 0),
33*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("LINEVOUTL"),
34*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("LINEVOUTR"),
35*4882a593Smuzhiyun };
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun static const struct snd_soc_dapm_route uda1334_dapm_routes[] = {
38*4882a593Smuzhiyun { "LINEVOUTL", NULL, "DAC" },
39*4882a593Smuzhiyun { "LINEVOUTR", NULL, "DAC" },
40*4882a593Smuzhiyun };
41*4882a593Smuzhiyun
uda1334_put_deemph(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)42*4882a593Smuzhiyun static int uda1334_put_deemph(struct snd_kcontrol *kcontrol,
43*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
44*4882a593Smuzhiyun {
45*4882a593Smuzhiyun struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
46*4882a593Smuzhiyun struct uda1334_priv *uda1334 = snd_soc_component_get_drvdata(component);
47*4882a593Smuzhiyun int deemph = ucontrol->value.integer.value[0];
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun if (deemph > 1)
50*4882a593Smuzhiyun return -EINVAL;
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun gpiod_set_value_cansleep(uda1334->deemph, deemph);
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun return 0;
55*4882a593Smuzhiyun };
56*4882a593Smuzhiyun
uda1334_get_deemph(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)57*4882a593Smuzhiyun static int uda1334_get_deemph(struct snd_kcontrol *kcontrol,
58*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
59*4882a593Smuzhiyun {
60*4882a593Smuzhiyun struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
61*4882a593Smuzhiyun struct uda1334_priv *uda1334 = snd_soc_component_get_drvdata(component);
62*4882a593Smuzhiyun int ret;
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun ret = gpiod_get_value_cansleep(uda1334->deemph);
65*4882a593Smuzhiyun if (ret < 0)
66*4882a593Smuzhiyun return -EINVAL;
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun ucontrol->value.integer.value[0] = ret;
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun return 0;
71*4882a593Smuzhiyun };
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun static const struct snd_kcontrol_new uda1334_snd_controls[] = {
74*4882a593Smuzhiyun SOC_SINGLE_BOOL_EXT("Playback Deemphasis Switch", 0,
75*4882a593Smuzhiyun uda1334_get_deemph, uda1334_put_deemph),
76*4882a593Smuzhiyun };
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun static const struct {
79*4882a593Smuzhiyun int value;
80*4882a593Smuzhiyun int ratio;
81*4882a593Smuzhiyun } lrclk_ratios[UDA1334_NUM_RATES] = {
82*4882a593Smuzhiyun { 1, 128 },
83*4882a593Smuzhiyun { 2, 192 },
84*4882a593Smuzhiyun { 3, 256 },
85*4882a593Smuzhiyun { 4, 384 },
86*4882a593Smuzhiyun { 5, 512 },
87*4882a593Smuzhiyun { 6, 768 },
88*4882a593Smuzhiyun };
89*4882a593Smuzhiyun
uda1334_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)90*4882a593Smuzhiyun static int uda1334_startup(struct snd_pcm_substream *substream,
91*4882a593Smuzhiyun struct snd_soc_dai *dai)
92*4882a593Smuzhiyun {
93*4882a593Smuzhiyun struct snd_soc_component *component = dai->component;
94*4882a593Smuzhiyun struct uda1334_priv *uda1334 = snd_soc_component_get_drvdata(component);
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun /*
97*4882a593Smuzhiyun * The set of sample rates that can be supported depends on the
98*4882a593Smuzhiyun * MCLK supplied to the CODEC - enforce this.
99*4882a593Smuzhiyun */
100*4882a593Smuzhiyun if (!uda1334->sysclk) {
101*4882a593Smuzhiyun dev_err(component->dev,
102*4882a593Smuzhiyun "No MCLK configured, call set_sysclk() on init\n");
103*4882a593Smuzhiyun return -EINVAL;
104*4882a593Smuzhiyun }
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun snd_pcm_hw_constraint_list(substream->runtime, 0,
107*4882a593Smuzhiyun SNDRV_PCM_HW_PARAM_RATE,
108*4882a593Smuzhiyun &uda1334->rate_constraint);
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun gpiod_set_value_cansleep(uda1334->mute, 1);
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun return 0;
113*4882a593Smuzhiyun }
114*4882a593Smuzhiyun
uda1334_shutdown(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)115*4882a593Smuzhiyun static void uda1334_shutdown(struct snd_pcm_substream *substream,
116*4882a593Smuzhiyun struct snd_soc_dai *dai)
117*4882a593Smuzhiyun {
118*4882a593Smuzhiyun struct snd_soc_component *component = dai->component;
119*4882a593Smuzhiyun struct uda1334_priv *uda1334 = snd_soc_component_get_drvdata(component);
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun gpiod_set_value_cansleep(uda1334->mute, 0);
122*4882a593Smuzhiyun }
123*4882a593Smuzhiyun
uda1334_set_dai_sysclk(struct snd_soc_dai * codec_dai,int clk_id,unsigned int freq,int dir)124*4882a593Smuzhiyun static int uda1334_set_dai_sysclk(struct snd_soc_dai *codec_dai,
125*4882a593Smuzhiyun int clk_id, unsigned int freq, int dir)
126*4882a593Smuzhiyun {
127*4882a593Smuzhiyun struct snd_soc_component *component = codec_dai->component;
128*4882a593Smuzhiyun struct uda1334_priv *uda1334 = snd_soc_component_get_drvdata(component);
129*4882a593Smuzhiyun unsigned int val;
130*4882a593Smuzhiyun int i, j = 0;
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun uda1334->sysclk = freq;
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun uda1334->rate_constraint.count = 0;
135*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(lrclk_ratios); i++) {
136*4882a593Smuzhiyun val = freq / lrclk_ratios[i].ratio;
137*4882a593Smuzhiyun /*
138*4882a593Smuzhiyun * Check that it's a standard rate since core can't
139*4882a593Smuzhiyun * cope with others and having the odd rates confuses
140*4882a593Smuzhiyun * constraint matching.
141*4882a593Smuzhiyun */
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun switch (val) {
144*4882a593Smuzhiyun case 8000:
145*4882a593Smuzhiyun case 32000:
146*4882a593Smuzhiyun case 44100:
147*4882a593Smuzhiyun case 48000:
148*4882a593Smuzhiyun case 64000:
149*4882a593Smuzhiyun case 88200:
150*4882a593Smuzhiyun case 96000:
151*4882a593Smuzhiyun dev_dbg(component->dev, "Supported sample rate: %dHz\n",
152*4882a593Smuzhiyun val);
153*4882a593Smuzhiyun uda1334->rate_constraint_list[j++] = val;
154*4882a593Smuzhiyun uda1334->rate_constraint.count++;
155*4882a593Smuzhiyun break;
156*4882a593Smuzhiyun default:
157*4882a593Smuzhiyun dev_dbg(component->dev, "Skipping sample rate: %dHz\n",
158*4882a593Smuzhiyun val);
159*4882a593Smuzhiyun }
160*4882a593Smuzhiyun }
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun /* Need at least one supported rate... */
163*4882a593Smuzhiyun if (uda1334->rate_constraint.count == 0)
164*4882a593Smuzhiyun return -EINVAL;
165*4882a593Smuzhiyun
166*4882a593Smuzhiyun return 0;
167*4882a593Smuzhiyun }
168*4882a593Smuzhiyun
uda1334_set_fmt(struct snd_soc_dai * codec_dai,unsigned int fmt)169*4882a593Smuzhiyun static int uda1334_set_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
170*4882a593Smuzhiyun {
171*4882a593Smuzhiyun fmt &= (SND_SOC_DAIFMT_FORMAT_MASK | SND_SOC_DAIFMT_INV_MASK |
172*4882a593Smuzhiyun SND_SOC_DAIFMT_MASTER_MASK);
173*4882a593Smuzhiyun
174*4882a593Smuzhiyun if (fmt != (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
175*4882a593Smuzhiyun SND_SOC_DAIFMT_CBS_CFS)) {
176*4882a593Smuzhiyun dev_err(codec_dai->dev, "Invalid DAI format\n");
177*4882a593Smuzhiyun return -EINVAL;
178*4882a593Smuzhiyun }
179*4882a593Smuzhiyun
180*4882a593Smuzhiyun return 0;
181*4882a593Smuzhiyun }
182*4882a593Smuzhiyun
uda1334_mute_stream(struct snd_soc_dai * dai,int mute,int stream)183*4882a593Smuzhiyun static int uda1334_mute_stream(struct snd_soc_dai *dai, int mute, int stream)
184*4882a593Smuzhiyun {
185*4882a593Smuzhiyun struct uda1334_priv *uda1334 = snd_soc_component_get_drvdata(dai->component);
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun if (uda1334->mute)
188*4882a593Smuzhiyun gpiod_set_value_cansleep(uda1334->mute, mute);
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun return 0;
191*4882a593Smuzhiyun }
192*4882a593Smuzhiyun
193*4882a593Smuzhiyun #define UDA1334_RATES SNDRV_PCM_RATE_8000_96000
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun #define UDA1334_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE)
196*4882a593Smuzhiyun
197*4882a593Smuzhiyun static const struct snd_soc_dai_ops uda1334_dai_ops = {
198*4882a593Smuzhiyun .startup = uda1334_startup,
199*4882a593Smuzhiyun .shutdown = uda1334_shutdown,
200*4882a593Smuzhiyun .set_sysclk = uda1334_set_dai_sysclk,
201*4882a593Smuzhiyun .set_fmt = uda1334_set_fmt,
202*4882a593Smuzhiyun .mute_stream = uda1334_mute_stream,
203*4882a593Smuzhiyun };
204*4882a593Smuzhiyun
205*4882a593Smuzhiyun static struct snd_soc_dai_driver uda1334_dai = {
206*4882a593Smuzhiyun .name = "uda1334-hifi",
207*4882a593Smuzhiyun .playback = {
208*4882a593Smuzhiyun .stream_name = "Playback",
209*4882a593Smuzhiyun .channels_min = 2,
210*4882a593Smuzhiyun .channels_max = 2,
211*4882a593Smuzhiyun .rates = UDA1334_RATES,
212*4882a593Smuzhiyun .formats = UDA1334_FORMATS,
213*4882a593Smuzhiyun },
214*4882a593Smuzhiyun .ops = &uda1334_dai_ops,
215*4882a593Smuzhiyun };
216*4882a593Smuzhiyun
uda1334_probe(struct snd_soc_component * component)217*4882a593Smuzhiyun static int uda1334_probe(struct snd_soc_component *component)
218*4882a593Smuzhiyun {
219*4882a593Smuzhiyun struct uda1334_priv *uda1334 = snd_soc_component_get_drvdata(component);
220*4882a593Smuzhiyun
221*4882a593Smuzhiyun uda1334->rate_constraint.list = &uda1334->rate_constraint_list[0];
222*4882a593Smuzhiyun uda1334->rate_constraint.count =
223*4882a593Smuzhiyun ARRAY_SIZE(uda1334->rate_constraint_list);
224*4882a593Smuzhiyun
225*4882a593Smuzhiyun return 0;
226*4882a593Smuzhiyun }
227*4882a593Smuzhiyun
228*4882a593Smuzhiyun static const struct snd_soc_component_driver soc_component_dev_uda1334 = {
229*4882a593Smuzhiyun .probe = uda1334_probe,
230*4882a593Smuzhiyun .controls = uda1334_snd_controls,
231*4882a593Smuzhiyun .num_controls = ARRAY_SIZE(uda1334_snd_controls),
232*4882a593Smuzhiyun .dapm_widgets = uda1334_dapm_widgets,
233*4882a593Smuzhiyun .num_dapm_widgets = ARRAY_SIZE(uda1334_dapm_widgets),
234*4882a593Smuzhiyun .dapm_routes = uda1334_dapm_routes,
235*4882a593Smuzhiyun .num_dapm_routes = ARRAY_SIZE(uda1334_dapm_routes),
236*4882a593Smuzhiyun .idle_bias_on = 1,
237*4882a593Smuzhiyun .use_pmdown_time = 1,
238*4882a593Smuzhiyun .endianness = 1,
239*4882a593Smuzhiyun .non_legacy_dai_naming = 1,
240*4882a593Smuzhiyun };
241*4882a593Smuzhiyun
242*4882a593Smuzhiyun static const struct of_device_id uda1334_of_match[] = {
243*4882a593Smuzhiyun { .compatible = "nxp,uda1334" },
244*4882a593Smuzhiyun { /* sentinel*/ }
245*4882a593Smuzhiyun };
246*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, uda1334_of_match);
247*4882a593Smuzhiyun
uda1334_codec_probe(struct platform_device * pdev)248*4882a593Smuzhiyun static int uda1334_codec_probe(struct platform_device *pdev)
249*4882a593Smuzhiyun {
250*4882a593Smuzhiyun struct uda1334_priv *uda1334;
251*4882a593Smuzhiyun int ret;
252*4882a593Smuzhiyun
253*4882a593Smuzhiyun uda1334 = devm_kzalloc(&pdev->dev, sizeof(struct uda1334_priv),
254*4882a593Smuzhiyun GFP_KERNEL);
255*4882a593Smuzhiyun if (!uda1334)
256*4882a593Smuzhiyun return -ENOMEM;
257*4882a593Smuzhiyun
258*4882a593Smuzhiyun platform_set_drvdata(pdev, uda1334);
259*4882a593Smuzhiyun
260*4882a593Smuzhiyun uda1334->mute = devm_gpiod_get(&pdev->dev, "nxp,mute", GPIOD_OUT_LOW);
261*4882a593Smuzhiyun if (IS_ERR(uda1334->mute)) {
262*4882a593Smuzhiyun ret = PTR_ERR(uda1334->mute);
263*4882a593Smuzhiyun dev_err(&pdev->dev, "Failed to get mute line: %d\n", ret);
264*4882a593Smuzhiyun return ret;
265*4882a593Smuzhiyun }
266*4882a593Smuzhiyun
267*4882a593Smuzhiyun uda1334->deemph = devm_gpiod_get(&pdev->dev, "nxp,deemph", GPIOD_OUT_LOW);
268*4882a593Smuzhiyun if (IS_ERR(uda1334->deemph)) {
269*4882a593Smuzhiyun ret = PTR_ERR(uda1334->deemph);
270*4882a593Smuzhiyun dev_err(&pdev->dev, "Failed to get deemph line: %d\n", ret);
271*4882a593Smuzhiyun return ret;
272*4882a593Smuzhiyun }
273*4882a593Smuzhiyun
274*4882a593Smuzhiyun ret = devm_snd_soc_register_component(&pdev->dev,
275*4882a593Smuzhiyun &soc_component_dev_uda1334,
276*4882a593Smuzhiyun &uda1334_dai, 1);
277*4882a593Smuzhiyun if (ret < 0)
278*4882a593Smuzhiyun dev_err(&pdev->dev, "Failed to register component: %d\n", ret);
279*4882a593Smuzhiyun
280*4882a593Smuzhiyun return ret;
281*4882a593Smuzhiyun }
282*4882a593Smuzhiyun
283*4882a593Smuzhiyun static struct platform_driver uda1334_codec_driver = {
284*4882a593Smuzhiyun .probe = uda1334_codec_probe,
285*4882a593Smuzhiyun .driver = {
286*4882a593Smuzhiyun .name = "uda1334-codec",
287*4882a593Smuzhiyun .of_match_table = uda1334_of_match,
288*4882a593Smuzhiyun },
289*4882a593Smuzhiyun };
290*4882a593Smuzhiyun module_platform_driver(uda1334_codec_driver);
291*4882a593Smuzhiyun
292*4882a593Smuzhiyun MODULE_DESCRIPTION("ASoC UDA1334 driver");
293*4882a593Smuzhiyun MODULE_AUTHOR("Andra Danciu <andradanciu1997@gmail.com>");
294*4882a593Smuzhiyun MODULE_ALIAS("platform:uda1334-codec");
295*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
296