xref: /OK3568_Linux_fs/kernel/sound/soc/codecs/twl4030.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * ALSA SoC TWL4030 codec driver
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Author:      Steve Sakoman, <steve@sakoman.com>
6*4882a593Smuzhiyun  */
7*4882a593Smuzhiyun 
8*4882a593Smuzhiyun #include <linux/module.h>
9*4882a593Smuzhiyun #include <linux/moduleparam.h>
10*4882a593Smuzhiyun #include <linux/init.h>
11*4882a593Smuzhiyun #include <linux/delay.h>
12*4882a593Smuzhiyun #include <linux/pm.h>
13*4882a593Smuzhiyun #include <linux/i2c.h>
14*4882a593Smuzhiyun #include <linux/platform_device.h>
15*4882a593Smuzhiyun #include <linux/of.h>
16*4882a593Smuzhiyun #include <linux/of_gpio.h>
17*4882a593Smuzhiyun #include <linux/mfd/twl.h>
18*4882a593Smuzhiyun #include <linux/slab.h>
19*4882a593Smuzhiyun #include <linux/gpio.h>
20*4882a593Smuzhiyun #include <sound/core.h>
21*4882a593Smuzhiyun #include <sound/pcm.h>
22*4882a593Smuzhiyun #include <sound/pcm_params.h>
23*4882a593Smuzhiyun #include <sound/soc.h>
24*4882a593Smuzhiyun #include <sound/initval.h>
25*4882a593Smuzhiyun #include <sound/tlv.h>
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun /* Register descriptions are here */
28*4882a593Smuzhiyun #include <linux/mfd/twl4030-audio.h>
29*4882a593Smuzhiyun 
30*4882a593Smuzhiyun /* TWL4030 PMBR1 Register */
31*4882a593Smuzhiyun #define TWL4030_PMBR1_REG		0x0D
32*4882a593Smuzhiyun /* TWL4030 PMBR1 Register GPIO6 mux bits */
33*4882a593Smuzhiyun #define TWL4030_GPIO6_PWM0_MUTE(value)	((value & 0x03) << 2)
34*4882a593Smuzhiyun 
35*4882a593Smuzhiyun #define TWL4030_CACHEREGNUM	(TWL4030_REG_MISC_SET_2 + 1)
36*4882a593Smuzhiyun 
37*4882a593Smuzhiyun /* codec private data */
38*4882a593Smuzhiyun struct twl4030_priv {
39*4882a593Smuzhiyun 	unsigned int codec_powered;
40*4882a593Smuzhiyun 
41*4882a593Smuzhiyun 	/* reference counts of AIF/APLL users */
42*4882a593Smuzhiyun 	unsigned int apll_enabled;
43*4882a593Smuzhiyun 
44*4882a593Smuzhiyun 	struct snd_pcm_substream *master_substream;
45*4882a593Smuzhiyun 	struct snd_pcm_substream *slave_substream;
46*4882a593Smuzhiyun 
47*4882a593Smuzhiyun 	unsigned int configured;
48*4882a593Smuzhiyun 	unsigned int rate;
49*4882a593Smuzhiyun 	unsigned int sample_bits;
50*4882a593Smuzhiyun 	unsigned int channels;
51*4882a593Smuzhiyun 
52*4882a593Smuzhiyun 	unsigned int sysclk;
53*4882a593Smuzhiyun 
54*4882a593Smuzhiyun 	/* Output (with associated amp) states */
55*4882a593Smuzhiyun 	u8 hsl_enabled, hsr_enabled;
56*4882a593Smuzhiyun 	u8 earpiece_enabled;
57*4882a593Smuzhiyun 	u8 predrivel_enabled, predriver_enabled;
58*4882a593Smuzhiyun 	u8 carkitl_enabled, carkitr_enabled;
59*4882a593Smuzhiyun 	u8 ctl_cache[TWL4030_REG_PRECKR_CTL - TWL4030_REG_EAR_CTL + 1];
60*4882a593Smuzhiyun 
61*4882a593Smuzhiyun 	struct twl4030_codec_data *pdata;
62*4882a593Smuzhiyun };
63*4882a593Smuzhiyun 
tw4030_init_ctl_cache(struct twl4030_priv * twl4030)64*4882a593Smuzhiyun static void tw4030_init_ctl_cache(struct twl4030_priv *twl4030)
65*4882a593Smuzhiyun {
66*4882a593Smuzhiyun 	int i;
67*4882a593Smuzhiyun 	u8 byte;
68*4882a593Smuzhiyun 
69*4882a593Smuzhiyun 	for (i = TWL4030_REG_EAR_CTL; i <= TWL4030_REG_PRECKR_CTL; i++) {
70*4882a593Smuzhiyun 		twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte, i);
71*4882a593Smuzhiyun 		twl4030->ctl_cache[i - TWL4030_REG_EAR_CTL] = byte;
72*4882a593Smuzhiyun 	}
73*4882a593Smuzhiyun }
74*4882a593Smuzhiyun 
twl4030_read(struct snd_soc_component * component,unsigned int reg)75*4882a593Smuzhiyun static unsigned int twl4030_read(struct snd_soc_component *component, unsigned int reg)
76*4882a593Smuzhiyun {
77*4882a593Smuzhiyun 	struct twl4030_priv *twl4030 = snd_soc_component_get_drvdata(component);
78*4882a593Smuzhiyun 	u8 value = 0;
79*4882a593Smuzhiyun 
80*4882a593Smuzhiyun 	if (reg >= TWL4030_CACHEREGNUM)
81*4882a593Smuzhiyun 		return -EIO;
82*4882a593Smuzhiyun 
83*4882a593Smuzhiyun 	switch (reg) {
84*4882a593Smuzhiyun 	case TWL4030_REG_EAR_CTL:
85*4882a593Smuzhiyun 	case TWL4030_REG_PREDL_CTL:
86*4882a593Smuzhiyun 	case TWL4030_REG_PREDR_CTL:
87*4882a593Smuzhiyun 	case TWL4030_REG_PRECKL_CTL:
88*4882a593Smuzhiyun 	case TWL4030_REG_PRECKR_CTL:
89*4882a593Smuzhiyun 	case TWL4030_REG_HS_GAIN_SET:
90*4882a593Smuzhiyun 		value = twl4030->ctl_cache[reg - TWL4030_REG_EAR_CTL];
91*4882a593Smuzhiyun 		break;
92*4882a593Smuzhiyun 	default:
93*4882a593Smuzhiyun 		twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &value, reg);
94*4882a593Smuzhiyun 		break;
95*4882a593Smuzhiyun 	}
96*4882a593Smuzhiyun 
97*4882a593Smuzhiyun 	return value;
98*4882a593Smuzhiyun }
99*4882a593Smuzhiyun 
twl4030_can_write_to_chip(struct twl4030_priv * twl4030,unsigned int reg)100*4882a593Smuzhiyun static bool twl4030_can_write_to_chip(struct twl4030_priv *twl4030,
101*4882a593Smuzhiyun 				      unsigned int reg)
102*4882a593Smuzhiyun {
103*4882a593Smuzhiyun 	bool write_to_reg = false;
104*4882a593Smuzhiyun 
105*4882a593Smuzhiyun 	/* Decide if the given register can be written */
106*4882a593Smuzhiyun 	switch (reg) {
107*4882a593Smuzhiyun 	case TWL4030_REG_EAR_CTL:
108*4882a593Smuzhiyun 		if (twl4030->earpiece_enabled)
109*4882a593Smuzhiyun 			write_to_reg = true;
110*4882a593Smuzhiyun 		break;
111*4882a593Smuzhiyun 	case TWL4030_REG_PREDL_CTL:
112*4882a593Smuzhiyun 		if (twl4030->predrivel_enabled)
113*4882a593Smuzhiyun 			write_to_reg = true;
114*4882a593Smuzhiyun 		break;
115*4882a593Smuzhiyun 	case TWL4030_REG_PREDR_CTL:
116*4882a593Smuzhiyun 		if (twl4030->predriver_enabled)
117*4882a593Smuzhiyun 			write_to_reg = true;
118*4882a593Smuzhiyun 		break;
119*4882a593Smuzhiyun 	case TWL4030_REG_PRECKL_CTL:
120*4882a593Smuzhiyun 		if (twl4030->carkitl_enabled)
121*4882a593Smuzhiyun 			write_to_reg = true;
122*4882a593Smuzhiyun 		break;
123*4882a593Smuzhiyun 	case TWL4030_REG_PRECKR_CTL:
124*4882a593Smuzhiyun 		if (twl4030->carkitr_enabled)
125*4882a593Smuzhiyun 			write_to_reg = true;
126*4882a593Smuzhiyun 		break;
127*4882a593Smuzhiyun 	case TWL4030_REG_HS_GAIN_SET:
128*4882a593Smuzhiyun 		if (twl4030->hsl_enabled || twl4030->hsr_enabled)
129*4882a593Smuzhiyun 			write_to_reg = true;
130*4882a593Smuzhiyun 		break;
131*4882a593Smuzhiyun 	default:
132*4882a593Smuzhiyun 		/* All other register can be written */
133*4882a593Smuzhiyun 		write_to_reg = true;
134*4882a593Smuzhiyun 		break;
135*4882a593Smuzhiyun 	}
136*4882a593Smuzhiyun 
137*4882a593Smuzhiyun 	return write_to_reg;
138*4882a593Smuzhiyun }
139*4882a593Smuzhiyun 
twl4030_write(struct snd_soc_component * component,unsigned int reg,unsigned int value)140*4882a593Smuzhiyun static int twl4030_write(struct snd_soc_component *component, unsigned int reg,
141*4882a593Smuzhiyun 			 unsigned int value)
142*4882a593Smuzhiyun {
143*4882a593Smuzhiyun 	struct twl4030_priv *twl4030 = snd_soc_component_get_drvdata(component);
144*4882a593Smuzhiyun 
145*4882a593Smuzhiyun 	/* Update the ctl cache */
146*4882a593Smuzhiyun 	switch (reg) {
147*4882a593Smuzhiyun 	case TWL4030_REG_EAR_CTL:
148*4882a593Smuzhiyun 	case TWL4030_REG_PREDL_CTL:
149*4882a593Smuzhiyun 	case TWL4030_REG_PREDR_CTL:
150*4882a593Smuzhiyun 	case TWL4030_REG_PRECKL_CTL:
151*4882a593Smuzhiyun 	case TWL4030_REG_PRECKR_CTL:
152*4882a593Smuzhiyun 	case TWL4030_REG_HS_GAIN_SET:
153*4882a593Smuzhiyun 		twl4030->ctl_cache[reg - TWL4030_REG_EAR_CTL] = value;
154*4882a593Smuzhiyun 		break;
155*4882a593Smuzhiyun 	default:
156*4882a593Smuzhiyun 		break;
157*4882a593Smuzhiyun 	}
158*4882a593Smuzhiyun 
159*4882a593Smuzhiyun 	if (twl4030_can_write_to_chip(twl4030, reg))
160*4882a593Smuzhiyun 		return twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, value, reg);
161*4882a593Smuzhiyun 
162*4882a593Smuzhiyun 	return 0;
163*4882a593Smuzhiyun }
164*4882a593Smuzhiyun 
twl4030_wait_ms(int time)165*4882a593Smuzhiyun static inline void twl4030_wait_ms(int time)
166*4882a593Smuzhiyun {
167*4882a593Smuzhiyun 	if (time < 60) {
168*4882a593Smuzhiyun 		time *= 1000;
169*4882a593Smuzhiyun 		usleep_range(time, time + 500);
170*4882a593Smuzhiyun 	} else {
171*4882a593Smuzhiyun 		msleep(time);
172*4882a593Smuzhiyun 	}
173*4882a593Smuzhiyun }
174*4882a593Smuzhiyun 
twl4030_codec_enable(struct snd_soc_component * component,int enable)175*4882a593Smuzhiyun static void twl4030_codec_enable(struct snd_soc_component *component, int enable)
176*4882a593Smuzhiyun {
177*4882a593Smuzhiyun 	struct twl4030_priv *twl4030 = snd_soc_component_get_drvdata(component);
178*4882a593Smuzhiyun 	int mode;
179*4882a593Smuzhiyun 
180*4882a593Smuzhiyun 	if (enable == twl4030->codec_powered)
181*4882a593Smuzhiyun 		return;
182*4882a593Smuzhiyun 
183*4882a593Smuzhiyun 	if (enable)
184*4882a593Smuzhiyun 		mode = twl4030_audio_enable_resource(TWL4030_AUDIO_RES_POWER);
185*4882a593Smuzhiyun 	else
186*4882a593Smuzhiyun 		mode = twl4030_audio_disable_resource(TWL4030_AUDIO_RES_POWER);
187*4882a593Smuzhiyun 
188*4882a593Smuzhiyun 	if (mode >= 0)
189*4882a593Smuzhiyun 		twl4030->codec_powered = enable;
190*4882a593Smuzhiyun 
191*4882a593Smuzhiyun 	/* REVISIT: this delay is present in TI sample drivers */
192*4882a593Smuzhiyun 	/* but there seems to be no TRM requirement for it     */
193*4882a593Smuzhiyun 	udelay(10);
194*4882a593Smuzhiyun }
195*4882a593Smuzhiyun 
twl4030_setup_pdata_of(struct twl4030_codec_data * pdata,struct device_node * node)196*4882a593Smuzhiyun static void twl4030_setup_pdata_of(struct twl4030_codec_data *pdata,
197*4882a593Smuzhiyun 				   struct device_node *node)
198*4882a593Smuzhiyun {
199*4882a593Smuzhiyun 	int value;
200*4882a593Smuzhiyun 
201*4882a593Smuzhiyun 	of_property_read_u32(node, "ti,digimic_delay",
202*4882a593Smuzhiyun 			     &pdata->digimic_delay);
203*4882a593Smuzhiyun 	of_property_read_u32(node, "ti,ramp_delay_value",
204*4882a593Smuzhiyun 			     &pdata->ramp_delay_value);
205*4882a593Smuzhiyun 	of_property_read_u32(node, "ti,offset_cncl_path",
206*4882a593Smuzhiyun 			     &pdata->offset_cncl_path);
207*4882a593Smuzhiyun 	if (!of_property_read_u32(node, "ti,hs_extmute", &value))
208*4882a593Smuzhiyun 		pdata->hs_extmute = value;
209*4882a593Smuzhiyun 
210*4882a593Smuzhiyun 	pdata->hs_extmute_gpio = of_get_named_gpio(node,
211*4882a593Smuzhiyun 						   "ti,hs_extmute_gpio", 0);
212*4882a593Smuzhiyun 	if (gpio_is_valid(pdata->hs_extmute_gpio))
213*4882a593Smuzhiyun 		pdata->hs_extmute = 1;
214*4882a593Smuzhiyun }
215*4882a593Smuzhiyun 
twl4030_get_pdata(struct snd_soc_component * component)216*4882a593Smuzhiyun static struct twl4030_codec_data *twl4030_get_pdata(struct snd_soc_component *component)
217*4882a593Smuzhiyun {
218*4882a593Smuzhiyun 	struct twl4030_codec_data *pdata = dev_get_platdata(component->dev);
219*4882a593Smuzhiyun 	struct device_node *twl4030_codec_node = NULL;
220*4882a593Smuzhiyun 
221*4882a593Smuzhiyun 	twl4030_codec_node = of_get_child_by_name(component->dev->parent->of_node,
222*4882a593Smuzhiyun 						  "codec");
223*4882a593Smuzhiyun 
224*4882a593Smuzhiyun 	if (!pdata && twl4030_codec_node) {
225*4882a593Smuzhiyun 		pdata = devm_kzalloc(component->dev,
226*4882a593Smuzhiyun 				     sizeof(struct twl4030_codec_data),
227*4882a593Smuzhiyun 				     GFP_KERNEL);
228*4882a593Smuzhiyun 		if (!pdata) {
229*4882a593Smuzhiyun 			of_node_put(twl4030_codec_node);
230*4882a593Smuzhiyun 			return NULL;
231*4882a593Smuzhiyun 		}
232*4882a593Smuzhiyun 		twl4030_setup_pdata_of(pdata, twl4030_codec_node);
233*4882a593Smuzhiyun 		of_node_put(twl4030_codec_node);
234*4882a593Smuzhiyun 	}
235*4882a593Smuzhiyun 
236*4882a593Smuzhiyun 	return pdata;
237*4882a593Smuzhiyun }
238*4882a593Smuzhiyun 
twl4030_init_chip(struct snd_soc_component * component)239*4882a593Smuzhiyun static void twl4030_init_chip(struct snd_soc_component *component)
240*4882a593Smuzhiyun {
241*4882a593Smuzhiyun 	struct twl4030_codec_data *pdata;
242*4882a593Smuzhiyun 	struct twl4030_priv *twl4030 = snd_soc_component_get_drvdata(component);
243*4882a593Smuzhiyun 	u8 reg, byte;
244*4882a593Smuzhiyun 	int i = 0;
245*4882a593Smuzhiyun 
246*4882a593Smuzhiyun 	pdata = twl4030_get_pdata(component);
247*4882a593Smuzhiyun 
248*4882a593Smuzhiyun 	if (pdata && pdata->hs_extmute) {
249*4882a593Smuzhiyun 		if (gpio_is_valid(pdata->hs_extmute_gpio)) {
250*4882a593Smuzhiyun 			int ret;
251*4882a593Smuzhiyun 
252*4882a593Smuzhiyun 			if (!pdata->hs_extmute_gpio)
253*4882a593Smuzhiyun 				dev_warn(component->dev,
254*4882a593Smuzhiyun 					"Extmute GPIO is 0 is this correct?\n");
255*4882a593Smuzhiyun 
256*4882a593Smuzhiyun 			ret = gpio_request_one(pdata->hs_extmute_gpio,
257*4882a593Smuzhiyun 					       GPIOF_OUT_INIT_LOW,
258*4882a593Smuzhiyun 					       "hs_extmute");
259*4882a593Smuzhiyun 			if (ret) {
260*4882a593Smuzhiyun 				dev_err(component->dev,
261*4882a593Smuzhiyun 					"Failed to get hs_extmute GPIO\n");
262*4882a593Smuzhiyun 				pdata->hs_extmute_gpio = -1;
263*4882a593Smuzhiyun 			}
264*4882a593Smuzhiyun 		} else {
265*4882a593Smuzhiyun 			u8 pin_mux;
266*4882a593Smuzhiyun 
267*4882a593Smuzhiyun 			/* Set TWL4030 GPIO6 as EXTMUTE signal */
268*4882a593Smuzhiyun 			twl_i2c_read_u8(TWL4030_MODULE_INTBR, &pin_mux,
269*4882a593Smuzhiyun 					TWL4030_PMBR1_REG);
270*4882a593Smuzhiyun 			pin_mux &= ~TWL4030_GPIO6_PWM0_MUTE(0x03);
271*4882a593Smuzhiyun 			pin_mux |= TWL4030_GPIO6_PWM0_MUTE(0x02);
272*4882a593Smuzhiyun 			twl_i2c_write_u8(TWL4030_MODULE_INTBR, pin_mux,
273*4882a593Smuzhiyun 					 TWL4030_PMBR1_REG);
274*4882a593Smuzhiyun 		}
275*4882a593Smuzhiyun 	}
276*4882a593Smuzhiyun 
277*4882a593Smuzhiyun 	/* Initialize the local ctl register cache */
278*4882a593Smuzhiyun 	tw4030_init_ctl_cache(twl4030);
279*4882a593Smuzhiyun 
280*4882a593Smuzhiyun 	/* anti-pop when changing analog gain */
281*4882a593Smuzhiyun 	reg = twl4030_read(component, TWL4030_REG_MISC_SET_1);
282*4882a593Smuzhiyun 	twl4030_write(component, TWL4030_REG_MISC_SET_1,
283*4882a593Smuzhiyun 		      reg | TWL4030_SMOOTH_ANAVOL_EN);
284*4882a593Smuzhiyun 
285*4882a593Smuzhiyun 	twl4030_write(component, TWL4030_REG_OPTION,
286*4882a593Smuzhiyun 		      TWL4030_ATXL1_EN | TWL4030_ATXR1_EN |
287*4882a593Smuzhiyun 		      TWL4030_ARXL2_EN | TWL4030_ARXR2_EN);
288*4882a593Smuzhiyun 
289*4882a593Smuzhiyun 	/* REG_ARXR2_APGA_CTL reset according to the TRM: 0dB, DA_EN */
290*4882a593Smuzhiyun 	twl4030_write(component, TWL4030_REG_ARXR2_APGA_CTL, 0x32);
291*4882a593Smuzhiyun 
292*4882a593Smuzhiyun 	/* Machine dependent setup */
293*4882a593Smuzhiyun 	if (!pdata)
294*4882a593Smuzhiyun 		return;
295*4882a593Smuzhiyun 
296*4882a593Smuzhiyun 	twl4030->pdata = pdata;
297*4882a593Smuzhiyun 
298*4882a593Smuzhiyun 	reg = twl4030_read(component, TWL4030_REG_HS_POPN_SET);
299*4882a593Smuzhiyun 	reg &= ~TWL4030_RAMP_DELAY;
300*4882a593Smuzhiyun 	reg |= (pdata->ramp_delay_value << 2);
301*4882a593Smuzhiyun 	twl4030_write(component, TWL4030_REG_HS_POPN_SET, reg);
302*4882a593Smuzhiyun 
303*4882a593Smuzhiyun 	/* initiate offset cancellation */
304*4882a593Smuzhiyun 	twl4030_codec_enable(component, 1);
305*4882a593Smuzhiyun 
306*4882a593Smuzhiyun 	reg = twl4030_read(component, TWL4030_REG_ANAMICL);
307*4882a593Smuzhiyun 	reg &= ~TWL4030_OFFSET_CNCL_SEL;
308*4882a593Smuzhiyun 	reg |= pdata->offset_cncl_path;
309*4882a593Smuzhiyun 	twl4030_write(component, TWL4030_REG_ANAMICL,
310*4882a593Smuzhiyun 		      reg | TWL4030_CNCL_OFFSET_START);
311*4882a593Smuzhiyun 
312*4882a593Smuzhiyun 	/*
313*4882a593Smuzhiyun 	 * Wait for offset cancellation to complete.
314*4882a593Smuzhiyun 	 * Since this takes a while, do not slam the i2c.
315*4882a593Smuzhiyun 	 * Start polling the status after ~20ms.
316*4882a593Smuzhiyun 	 */
317*4882a593Smuzhiyun 	msleep(20);
318*4882a593Smuzhiyun 	do {
319*4882a593Smuzhiyun 		usleep_range(1000, 2000);
320*4882a593Smuzhiyun 		twl_set_regcache_bypass(TWL4030_MODULE_AUDIO_VOICE, true);
321*4882a593Smuzhiyun 		twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
322*4882a593Smuzhiyun 				TWL4030_REG_ANAMICL);
323*4882a593Smuzhiyun 		twl_set_regcache_bypass(TWL4030_MODULE_AUDIO_VOICE, false);
324*4882a593Smuzhiyun 	} while ((i++ < 100) &&
325*4882a593Smuzhiyun 		 ((byte & TWL4030_CNCL_OFFSET_START) ==
326*4882a593Smuzhiyun 		  TWL4030_CNCL_OFFSET_START));
327*4882a593Smuzhiyun 
328*4882a593Smuzhiyun 	twl4030_codec_enable(component, 0);
329*4882a593Smuzhiyun }
330*4882a593Smuzhiyun 
twl4030_apll_enable(struct snd_soc_component * component,int enable)331*4882a593Smuzhiyun static void twl4030_apll_enable(struct snd_soc_component *component, int enable)
332*4882a593Smuzhiyun {
333*4882a593Smuzhiyun 	struct twl4030_priv *twl4030 = snd_soc_component_get_drvdata(component);
334*4882a593Smuzhiyun 
335*4882a593Smuzhiyun 	if (enable) {
336*4882a593Smuzhiyun 		twl4030->apll_enabled++;
337*4882a593Smuzhiyun 		if (twl4030->apll_enabled == 1)
338*4882a593Smuzhiyun 			twl4030_audio_enable_resource(
339*4882a593Smuzhiyun 							TWL4030_AUDIO_RES_APLL);
340*4882a593Smuzhiyun 	} else {
341*4882a593Smuzhiyun 		twl4030->apll_enabled--;
342*4882a593Smuzhiyun 		if (!twl4030->apll_enabled)
343*4882a593Smuzhiyun 			twl4030_audio_disable_resource(
344*4882a593Smuzhiyun 							TWL4030_AUDIO_RES_APLL);
345*4882a593Smuzhiyun 	}
346*4882a593Smuzhiyun }
347*4882a593Smuzhiyun 
348*4882a593Smuzhiyun /* Earpiece */
349*4882a593Smuzhiyun static const struct snd_kcontrol_new twl4030_dapm_earpiece_controls[] = {
350*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("Voice", TWL4030_REG_EAR_CTL, 0, 1, 0),
351*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_EAR_CTL, 1, 1, 0),
352*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_EAR_CTL, 2, 1, 0),
353*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_EAR_CTL, 3, 1, 0),
354*4882a593Smuzhiyun };
355*4882a593Smuzhiyun 
356*4882a593Smuzhiyun /* PreDrive Left */
357*4882a593Smuzhiyun static const struct snd_kcontrol_new twl4030_dapm_predrivel_controls[] = {
358*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDL_CTL, 0, 1, 0),
359*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PREDL_CTL, 1, 1, 0),
360*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDL_CTL, 2, 1, 0),
361*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDL_CTL, 3, 1, 0),
362*4882a593Smuzhiyun };
363*4882a593Smuzhiyun 
364*4882a593Smuzhiyun /* PreDrive Right */
365*4882a593Smuzhiyun static const struct snd_kcontrol_new twl4030_dapm_predriver_controls[] = {
366*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDR_CTL, 0, 1, 0),
367*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PREDR_CTL, 1, 1, 0),
368*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDR_CTL, 2, 1, 0),
369*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDR_CTL, 3, 1, 0),
370*4882a593Smuzhiyun };
371*4882a593Smuzhiyun 
372*4882a593Smuzhiyun /* Headset Left */
373*4882a593Smuzhiyun static const struct snd_kcontrol_new twl4030_dapm_hsol_controls[] = {
374*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 0, 1, 0),
375*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_HS_SEL, 1, 1, 0),
376*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_HS_SEL, 2, 1, 0),
377*4882a593Smuzhiyun };
378*4882a593Smuzhiyun 
379*4882a593Smuzhiyun /* Headset Right */
380*4882a593Smuzhiyun static const struct snd_kcontrol_new twl4030_dapm_hsor_controls[] = {
381*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 3, 1, 0),
382*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_HS_SEL, 4, 1, 0),
383*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_HS_SEL, 5, 1, 0),
384*4882a593Smuzhiyun };
385*4882a593Smuzhiyun 
386*4882a593Smuzhiyun /* Carkit Left */
387*4882a593Smuzhiyun static const struct snd_kcontrol_new twl4030_dapm_carkitl_controls[] = {
388*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKL_CTL, 0, 1, 0),
389*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PRECKL_CTL, 1, 1, 0),
390*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PRECKL_CTL, 2, 1, 0),
391*4882a593Smuzhiyun };
392*4882a593Smuzhiyun 
393*4882a593Smuzhiyun /* Carkit Right */
394*4882a593Smuzhiyun static const struct snd_kcontrol_new twl4030_dapm_carkitr_controls[] = {
395*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKR_CTL, 0, 1, 0),
396*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PRECKR_CTL, 1, 1, 0),
397*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PRECKR_CTL, 2, 1, 0),
398*4882a593Smuzhiyun };
399*4882a593Smuzhiyun 
400*4882a593Smuzhiyun /* Handsfree Left */
401*4882a593Smuzhiyun static const char *twl4030_handsfreel_texts[] =
402*4882a593Smuzhiyun 		{"Voice", "AudioL1", "AudioL2", "AudioR2"};
403*4882a593Smuzhiyun 
404*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(twl4030_handsfreel_enum,
405*4882a593Smuzhiyun 			    TWL4030_REG_HFL_CTL, 0,
406*4882a593Smuzhiyun 			    twl4030_handsfreel_texts);
407*4882a593Smuzhiyun 
408*4882a593Smuzhiyun static const struct snd_kcontrol_new twl4030_dapm_handsfreel_control =
409*4882a593Smuzhiyun SOC_DAPM_ENUM("Route", twl4030_handsfreel_enum);
410*4882a593Smuzhiyun 
411*4882a593Smuzhiyun /* Handsfree Left virtual mute */
412*4882a593Smuzhiyun static const struct snd_kcontrol_new twl4030_dapm_handsfreelmute_control =
413*4882a593Smuzhiyun 	SOC_DAPM_SINGLE_VIRT("Switch", 1);
414*4882a593Smuzhiyun 
415*4882a593Smuzhiyun /* Handsfree Right */
416*4882a593Smuzhiyun static const char *twl4030_handsfreer_texts[] =
417*4882a593Smuzhiyun 		{"Voice", "AudioR1", "AudioR2", "AudioL2"};
418*4882a593Smuzhiyun 
419*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(twl4030_handsfreer_enum,
420*4882a593Smuzhiyun 			    TWL4030_REG_HFR_CTL, 0,
421*4882a593Smuzhiyun 			    twl4030_handsfreer_texts);
422*4882a593Smuzhiyun 
423*4882a593Smuzhiyun static const struct snd_kcontrol_new twl4030_dapm_handsfreer_control =
424*4882a593Smuzhiyun SOC_DAPM_ENUM("Route", twl4030_handsfreer_enum);
425*4882a593Smuzhiyun 
426*4882a593Smuzhiyun /* Handsfree Right virtual mute */
427*4882a593Smuzhiyun static const struct snd_kcontrol_new twl4030_dapm_handsfreermute_control =
428*4882a593Smuzhiyun 	SOC_DAPM_SINGLE_VIRT("Switch", 1);
429*4882a593Smuzhiyun 
430*4882a593Smuzhiyun /* Vibra */
431*4882a593Smuzhiyun /* Vibra audio path selection */
432*4882a593Smuzhiyun static const char *twl4030_vibra_texts[] =
433*4882a593Smuzhiyun 		{"AudioL1", "AudioR1", "AudioL2", "AudioR2"};
434*4882a593Smuzhiyun 
435*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(twl4030_vibra_enum,
436*4882a593Smuzhiyun 			    TWL4030_REG_VIBRA_CTL, 2,
437*4882a593Smuzhiyun 			    twl4030_vibra_texts);
438*4882a593Smuzhiyun 
439*4882a593Smuzhiyun static const struct snd_kcontrol_new twl4030_dapm_vibra_control =
440*4882a593Smuzhiyun SOC_DAPM_ENUM("Route", twl4030_vibra_enum);
441*4882a593Smuzhiyun 
442*4882a593Smuzhiyun /* Vibra path selection: local vibrator (PWM) or audio driven */
443*4882a593Smuzhiyun static const char *twl4030_vibrapath_texts[] =
444*4882a593Smuzhiyun 		{"Local vibrator", "Audio"};
445*4882a593Smuzhiyun 
446*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(twl4030_vibrapath_enum,
447*4882a593Smuzhiyun 			    TWL4030_REG_VIBRA_CTL, 4,
448*4882a593Smuzhiyun 			    twl4030_vibrapath_texts);
449*4882a593Smuzhiyun 
450*4882a593Smuzhiyun static const struct snd_kcontrol_new twl4030_dapm_vibrapath_control =
451*4882a593Smuzhiyun SOC_DAPM_ENUM("Route", twl4030_vibrapath_enum);
452*4882a593Smuzhiyun 
453*4882a593Smuzhiyun /* Left analog microphone selection */
454*4882a593Smuzhiyun static const struct snd_kcontrol_new twl4030_dapm_analoglmic_controls[] = {
455*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("Main Mic Capture Switch",
456*4882a593Smuzhiyun 			TWL4030_REG_ANAMICL, 0, 1, 0),
457*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("Headset Mic Capture Switch",
458*4882a593Smuzhiyun 			TWL4030_REG_ANAMICL, 1, 1, 0),
459*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("AUXL Capture Switch",
460*4882a593Smuzhiyun 			TWL4030_REG_ANAMICL, 2, 1, 0),
461*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("Carkit Mic Capture Switch",
462*4882a593Smuzhiyun 			TWL4030_REG_ANAMICL, 3, 1, 0),
463*4882a593Smuzhiyun };
464*4882a593Smuzhiyun 
465*4882a593Smuzhiyun /* Right analog microphone selection */
466*4882a593Smuzhiyun static const struct snd_kcontrol_new twl4030_dapm_analogrmic_controls[] = {
467*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("Sub Mic Capture Switch", TWL4030_REG_ANAMICR, 0, 1, 0),
468*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("AUXR Capture Switch", TWL4030_REG_ANAMICR, 2, 1, 0),
469*4882a593Smuzhiyun };
470*4882a593Smuzhiyun 
471*4882a593Smuzhiyun /* TX1 L/R Analog/Digital microphone selection */
472*4882a593Smuzhiyun static const char *twl4030_micpathtx1_texts[] =
473*4882a593Smuzhiyun 		{"Analog", "Digimic0"};
474*4882a593Smuzhiyun 
475*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(twl4030_micpathtx1_enum,
476*4882a593Smuzhiyun 			    TWL4030_REG_ADCMICSEL, 0,
477*4882a593Smuzhiyun 			    twl4030_micpathtx1_texts);
478*4882a593Smuzhiyun 
479*4882a593Smuzhiyun static const struct snd_kcontrol_new twl4030_dapm_micpathtx1_control =
480*4882a593Smuzhiyun SOC_DAPM_ENUM("Route", twl4030_micpathtx1_enum);
481*4882a593Smuzhiyun 
482*4882a593Smuzhiyun /* TX2 L/R Analog/Digital microphone selection */
483*4882a593Smuzhiyun static const char *twl4030_micpathtx2_texts[] =
484*4882a593Smuzhiyun 		{"Analog", "Digimic1"};
485*4882a593Smuzhiyun 
486*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(twl4030_micpathtx2_enum,
487*4882a593Smuzhiyun 			    TWL4030_REG_ADCMICSEL, 2,
488*4882a593Smuzhiyun 			    twl4030_micpathtx2_texts);
489*4882a593Smuzhiyun 
490*4882a593Smuzhiyun static const struct snd_kcontrol_new twl4030_dapm_micpathtx2_control =
491*4882a593Smuzhiyun SOC_DAPM_ENUM("Route", twl4030_micpathtx2_enum);
492*4882a593Smuzhiyun 
493*4882a593Smuzhiyun /* Analog bypass for AudioR1 */
494*4882a593Smuzhiyun static const struct snd_kcontrol_new twl4030_dapm_abypassr1_control =
495*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR1_APGA_CTL, 2, 1, 0);
496*4882a593Smuzhiyun 
497*4882a593Smuzhiyun /* Analog bypass for AudioL1 */
498*4882a593Smuzhiyun static const struct snd_kcontrol_new twl4030_dapm_abypassl1_control =
499*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL1_APGA_CTL, 2, 1, 0);
500*4882a593Smuzhiyun 
501*4882a593Smuzhiyun /* Analog bypass for AudioR2 */
502*4882a593Smuzhiyun static const struct snd_kcontrol_new twl4030_dapm_abypassr2_control =
503*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR2_APGA_CTL, 2, 1, 0);
504*4882a593Smuzhiyun 
505*4882a593Smuzhiyun /* Analog bypass for AudioL2 */
506*4882a593Smuzhiyun static const struct snd_kcontrol_new twl4030_dapm_abypassl2_control =
507*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL2_APGA_CTL, 2, 1, 0);
508*4882a593Smuzhiyun 
509*4882a593Smuzhiyun /* Analog bypass for Voice */
510*4882a593Smuzhiyun static const struct snd_kcontrol_new twl4030_dapm_abypassv_control =
511*4882a593Smuzhiyun 	SOC_DAPM_SINGLE("Switch", TWL4030_REG_VDL_APGA_CTL, 2, 1, 0);
512*4882a593Smuzhiyun 
513*4882a593Smuzhiyun /* Digital bypass gain, mute instead of -30dB */
514*4882a593Smuzhiyun static const DECLARE_TLV_DB_RANGE(twl4030_dapm_dbypass_tlv,
515*4882a593Smuzhiyun 	0, 1, TLV_DB_SCALE_ITEM(-3000, 600, 1),
516*4882a593Smuzhiyun 	2, 3, TLV_DB_SCALE_ITEM(-2400, 0, 0),
517*4882a593Smuzhiyun 	4, 7, TLV_DB_SCALE_ITEM(-1800, 600, 0)
518*4882a593Smuzhiyun );
519*4882a593Smuzhiyun 
520*4882a593Smuzhiyun /* Digital bypass left (TX1L -> RX2L) */
521*4882a593Smuzhiyun static const struct snd_kcontrol_new twl4030_dapm_dbypassl_control =
522*4882a593Smuzhiyun 	SOC_DAPM_SINGLE_TLV("Volume",
523*4882a593Smuzhiyun 			TWL4030_REG_ATX2ARXPGA, 3, 7, 0,
524*4882a593Smuzhiyun 			twl4030_dapm_dbypass_tlv);
525*4882a593Smuzhiyun 
526*4882a593Smuzhiyun /* Digital bypass right (TX1R -> RX2R) */
527*4882a593Smuzhiyun static const struct snd_kcontrol_new twl4030_dapm_dbypassr_control =
528*4882a593Smuzhiyun 	SOC_DAPM_SINGLE_TLV("Volume",
529*4882a593Smuzhiyun 			TWL4030_REG_ATX2ARXPGA, 0, 7, 0,
530*4882a593Smuzhiyun 			twl4030_dapm_dbypass_tlv);
531*4882a593Smuzhiyun 
532*4882a593Smuzhiyun /*
533*4882a593Smuzhiyun  * Voice Sidetone GAIN volume control:
534*4882a593Smuzhiyun  * from -51 to -10 dB in 1 dB steps (mute instead of -51 dB)
535*4882a593Smuzhiyun  */
536*4882a593Smuzhiyun static DECLARE_TLV_DB_SCALE(twl4030_dapm_dbypassv_tlv, -5100, 100, 1);
537*4882a593Smuzhiyun 
538*4882a593Smuzhiyun /* Digital bypass voice: sidetone (VUL -> VDL)*/
539*4882a593Smuzhiyun static const struct snd_kcontrol_new twl4030_dapm_dbypassv_control =
540*4882a593Smuzhiyun 	SOC_DAPM_SINGLE_TLV("Volume",
541*4882a593Smuzhiyun 			TWL4030_REG_VSTPGA, 0, 0x29, 0,
542*4882a593Smuzhiyun 			twl4030_dapm_dbypassv_tlv);
543*4882a593Smuzhiyun 
544*4882a593Smuzhiyun /*
545*4882a593Smuzhiyun  * Output PGA builder:
546*4882a593Smuzhiyun  * Handle the muting and unmuting of the given output (turning off the
547*4882a593Smuzhiyun  * amplifier associated with the output pin)
548*4882a593Smuzhiyun  * On mute bypass the reg_cache and write 0 to the register
549*4882a593Smuzhiyun  * On unmute: restore the register content from the reg_cache
550*4882a593Smuzhiyun  * Outputs handled in this way:  Earpiece, PreDrivL/R, CarkitL/R
551*4882a593Smuzhiyun  */
552*4882a593Smuzhiyun #define TWL4030_OUTPUT_PGA(pin_name, reg, mask)				\
553*4882a593Smuzhiyun static int pin_name##pga_event(struct snd_soc_dapm_widget *w,		\
554*4882a593Smuzhiyun 			       struct snd_kcontrol *kcontrol, int event) \
555*4882a593Smuzhiyun {									\
556*4882a593Smuzhiyun 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);	\
557*4882a593Smuzhiyun 	struct twl4030_priv *twl4030 = snd_soc_component_get_drvdata(component); \
558*4882a593Smuzhiyun 									\
559*4882a593Smuzhiyun 	switch (event) {						\
560*4882a593Smuzhiyun 	case SND_SOC_DAPM_POST_PMU:					\
561*4882a593Smuzhiyun 		twl4030->pin_name##_enabled = 1;			\
562*4882a593Smuzhiyun 		twl4030_write(component, reg, twl4030_read(component, reg));	\
563*4882a593Smuzhiyun 		break;							\
564*4882a593Smuzhiyun 	case SND_SOC_DAPM_POST_PMD:					\
565*4882a593Smuzhiyun 		twl4030->pin_name##_enabled = 0;			\
566*4882a593Smuzhiyun 		twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, 0, reg);	\
567*4882a593Smuzhiyun 		break;							\
568*4882a593Smuzhiyun 	}								\
569*4882a593Smuzhiyun 	return 0;							\
570*4882a593Smuzhiyun }
571*4882a593Smuzhiyun 
572*4882a593Smuzhiyun TWL4030_OUTPUT_PGA(earpiece, TWL4030_REG_EAR_CTL, TWL4030_EAR_GAIN);
573*4882a593Smuzhiyun TWL4030_OUTPUT_PGA(predrivel, TWL4030_REG_PREDL_CTL, TWL4030_PREDL_GAIN);
574*4882a593Smuzhiyun TWL4030_OUTPUT_PGA(predriver, TWL4030_REG_PREDR_CTL, TWL4030_PREDR_GAIN);
575*4882a593Smuzhiyun TWL4030_OUTPUT_PGA(carkitl, TWL4030_REG_PRECKL_CTL, TWL4030_PRECKL_GAIN);
576*4882a593Smuzhiyun TWL4030_OUTPUT_PGA(carkitr, TWL4030_REG_PRECKR_CTL, TWL4030_PRECKR_GAIN);
577*4882a593Smuzhiyun 
handsfree_ramp(struct snd_soc_component * component,int reg,int ramp)578*4882a593Smuzhiyun static void handsfree_ramp(struct snd_soc_component *component, int reg, int ramp)
579*4882a593Smuzhiyun {
580*4882a593Smuzhiyun 	unsigned char hs_ctl;
581*4882a593Smuzhiyun 
582*4882a593Smuzhiyun 	hs_ctl = twl4030_read(component, reg);
583*4882a593Smuzhiyun 
584*4882a593Smuzhiyun 	if (ramp) {
585*4882a593Smuzhiyun 		/* HF ramp-up */
586*4882a593Smuzhiyun 		hs_ctl |= TWL4030_HF_CTL_REF_EN;
587*4882a593Smuzhiyun 		twl4030_write(component, reg, hs_ctl);
588*4882a593Smuzhiyun 		udelay(10);
589*4882a593Smuzhiyun 		hs_ctl |= TWL4030_HF_CTL_RAMP_EN;
590*4882a593Smuzhiyun 		twl4030_write(component, reg, hs_ctl);
591*4882a593Smuzhiyun 		udelay(40);
592*4882a593Smuzhiyun 		hs_ctl |= TWL4030_HF_CTL_LOOP_EN;
593*4882a593Smuzhiyun 		hs_ctl |= TWL4030_HF_CTL_HB_EN;
594*4882a593Smuzhiyun 		twl4030_write(component, reg, hs_ctl);
595*4882a593Smuzhiyun 	} else {
596*4882a593Smuzhiyun 		/* HF ramp-down */
597*4882a593Smuzhiyun 		hs_ctl &= ~TWL4030_HF_CTL_LOOP_EN;
598*4882a593Smuzhiyun 		hs_ctl &= ~TWL4030_HF_CTL_HB_EN;
599*4882a593Smuzhiyun 		twl4030_write(component, reg, hs_ctl);
600*4882a593Smuzhiyun 		hs_ctl &= ~TWL4030_HF_CTL_RAMP_EN;
601*4882a593Smuzhiyun 		twl4030_write(component, reg, hs_ctl);
602*4882a593Smuzhiyun 		udelay(40);
603*4882a593Smuzhiyun 		hs_ctl &= ~TWL4030_HF_CTL_REF_EN;
604*4882a593Smuzhiyun 		twl4030_write(component, reg, hs_ctl);
605*4882a593Smuzhiyun 	}
606*4882a593Smuzhiyun }
607*4882a593Smuzhiyun 
handsfreelpga_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)608*4882a593Smuzhiyun static int handsfreelpga_event(struct snd_soc_dapm_widget *w,
609*4882a593Smuzhiyun 			       struct snd_kcontrol *kcontrol, int event)
610*4882a593Smuzhiyun {
611*4882a593Smuzhiyun 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
612*4882a593Smuzhiyun 
613*4882a593Smuzhiyun 	switch (event) {
614*4882a593Smuzhiyun 	case SND_SOC_DAPM_POST_PMU:
615*4882a593Smuzhiyun 		handsfree_ramp(component, TWL4030_REG_HFL_CTL, 1);
616*4882a593Smuzhiyun 		break;
617*4882a593Smuzhiyun 	case SND_SOC_DAPM_POST_PMD:
618*4882a593Smuzhiyun 		handsfree_ramp(component, TWL4030_REG_HFL_CTL, 0);
619*4882a593Smuzhiyun 		break;
620*4882a593Smuzhiyun 	}
621*4882a593Smuzhiyun 	return 0;
622*4882a593Smuzhiyun }
623*4882a593Smuzhiyun 
handsfreerpga_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)624*4882a593Smuzhiyun static int handsfreerpga_event(struct snd_soc_dapm_widget *w,
625*4882a593Smuzhiyun 			       struct snd_kcontrol *kcontrol, int event)
626*4882a593Smuzhiyun {
627*4882a593Smuzhiyun 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
628*4882a593Smuzhiyun 
629*4882a593Smuzhiyun 	switch (event) {
630*4882a593Smuzhiyun 	case SND_SOC_DAPM_POST_PMU:
631*4882a593Smuzhiyun 		handsfree_ramp(component, TWL4030_REG_HFR_CTL, 1);
632*4882a593Smuzhiyun 		break;
633*4882a593Smuzhiyun 	case SND_SOC_DAPM_POST_PMD:
634*4882a593Smuzhiyun 		handsfree_ramp(component, TWL4030_REG_HFR_CTL, 0);
635*4882a593Smuzhiyun 		break;
636*4882a593Smuzhiyun 	}
637*4882a593Smuzhiyun 	return 0;
638*4882a593Smuzhiyun }
639*4882a593Smuzhiyun 
vibramux_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)640*4882a593Smuzhiyun static int vibramux_event(struct snd_soc_dapm_widget *w,
641*4882a593Smuzhiyun 			  struct snd_kcontrol *kcontrol, int event)
642*4882a593Smuzhiyun {
643*4882a593Smuzhiyun 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
644*4882a593Smuzhiyun 
645*4882a593Smuzhiyun 	twl4030_write(component, TWL4030_REG_VIBRA_SET, 0xff);
646*4882a593Smuzhiyun 	return 0;
647*4882a593Smuzhiyun }
648*4882a593Smuzhiyun 
apll_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)649*4882a593Smuzhiyun static int apll_event(struct snd_soc_dapm_widget *w,
650*4882a593Smuzhiyun 		      struct snd_kcontrol *kcontrol, int event)
651*4882a593Smuzhiyun {
652*4882a593Smuzhiyun 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
653*4882a593Smuzhiyun 
654*4882a593Smuzhiyun 	switch (event) {
655*4882a593Smuzhiyun 	case SND_SOC_DAPM_PRE_PMU:
656*4882a593Smuzhiyun 		twl4030_apll_enable(component, 1);
657*4882a593Smuzhiyun 		break;
658*4882a593Smuzhiyun 	case SND_SOC_DAPM_POST_PMD:
659*4882a593Smuzhiyun 		twl4030_apll_enable(component, 0);
660*4882a593Smuzhiyun 		break;
661*4882a593Smuzhiyun 	}
662*4882a593Smuzhiyun 	return 0;
663*4882a593Smuzhiyun }
664*4882a593Smuzhiyun 
aif_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)665*4882a593Smuzhiyun static int aif_event(struct snd_soc_dapm_widget *w,
666*4882a593Smuzhiyun 		     struct snd_kcontrol *kcontrol, int event)
667*4882a593Smuzhiyun {
668*4882a593Smuzhiyun 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
669*4882a593Smuzhiyun 	u8 audio_if;
670*4882a593Smuzhiyun 
671*4882a593Smuzhiyun 	audio_if = twl4030_read(component, TWL4030_REG_AUDIO_IF);
672*4882a593Smuzhiyun 	switch (event) {
673*4882a593Smuzhiyun 	case SND_SOC_DAPM_PRE_PMU:
674*4882a593Smuzhiyun 		/* Enable AIF */
675*4882a593Smuzhiyun 		/* enable the PLL before we use it to clock the DAI */
676*4882a593Smuzhiyun 		twl4030_apll_enable(component, 1);
677*4882a593Smuzhiyun 
678*4882a593Smuzhiyun 		twl4030_write(component, TWL4030_REG_AUDIO_IF,
679*4882a593Smuzhiyun 			      audio_if | TWL4030_AIF_EN);
680*4882a593Smuzhiyun 		break;
681*4882a593Smuzhiyun 	case SND_SOC_DAPM_POST_PMD:
682*4882a593Smuzhiyun 		/* disable the DAI before we stop it's source PLL */
683*4882a593Smuzhiyun 		twl4030_write(component, TWL4030_REG_AUDIO_IF,
684*4882a593Smuzhiyun 			      audio_if &  ~TWL4030_AIF_EN);
685*4882a593Smuzhiyun 		twl4030_apll_enable(component, 0);
686*4882a593Smuzhiyun 		break;
687*4882a593Smuzhiyun 	}
688*4882a593Smuzhiyun 	return 0;
689*4882a593Smuzhiyun }
690*4882a593Smuzhiyun 
headset_ramp(struct snd_soc_component * component,int ramp)691*4882a593Smuzhiyun static void headset_ramp(struct snd_soc_component *component, int ramp)
692*4882a593Smuzhiyun {
693*4882a593Smuzhiyun 	unsigned char hs_gain, hs_pop;
694*4882a593Smuzhiyun 	struct twl4030_priv *twl4030 = snd_soc_component_get_drvdata(component);
695*4882a593Smuzhiyun 	struct twl4030_codec_data *pdata = twl4030->pdata;
696*4882a593Smuzhiyun 	/* Base values for ramp delay calculation: 2^19 - 2^26 */
697*4882a593Smuzhiyun 	unsigned int ramp_base[] = {524288, 1048576, 2097152, 4194304,
698*4882a593Smuzhiyun 				    8388608, 16777216, 33554432, 67108864};
699*4882a593Smuzhiyun 	unsigned int delay;
700*4882a593Smuzhiyun 
701*4882a593Smuzhiyun 	hs_gain = twl4030_read(component, TWL4030_REG_HS_GAIN_SET);
702*4882a593Smuzhiyun 	hs_pop = twl4030_read(component, TWL4030_REG_HS_POPN_SET);
703*4882a593Smuzhiyun 	delay = (ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] /
704*4882a593Smuzhiyun 		twl4030->sysclk) + 1;
705*4882a593Smuzhiyun 
706*4882a593Smuzhiyun 	/* Enable external mute control, this dramatically reduces
707*4882a593Smuzhiyun 	 * the pop-noise */
708*4882a593Smuzhiyun 	if (pdata && pdata->hs_extmute) {
709*4882a593Smuzhiyun 		if (gpio_is_valid(pdata->hs_extmute_gpio)) {
710*4882a593Smuzhiyun 			gpio_set_value(pdata->hs_extmute_gpio, 1);
711*4882a593Smuzhiyun 		} else {
712*4882a593Smuzhiyun 			hs_pop |= TWL4030_EXTMUTE;
713*4882a593Smuzhiyun 			twl4030_write(component, TWL4030_REG_HS_POPN_SET, hs_pop);
714*4882a593Smuzhiyun 		}
715*4882a593Smuzhiyun 	}
716*4882a593Smuzhiyun 
717*4882a593Smuzhiyun 	if (ramp) {
718*4882a593Smuzhiyun 		/* Headset ramp-up according to the TRM */
719*4882a593Smuzhiyun 		hs_pop |= TWL4030_VMID_EN;
720*4882a593Smuzhiyun 		twl4030_write(component, TWL4030_REG_HS_POPN_SET, hs_pop);
721*4882a593Smuzhiyun 		/* Actually write to the register */
722*4882a593Smuzhiyun 		twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, hs_gain,
723*4882a593Smuzhiyun 				 TWL4030_REG_HS_GAIN_SET);
724*4882a593Smuzhiyun 		hs_pop |= TWL4030_RAMP_EN;
725*4882a593Smuzhiyun 		twl4030_write(component, TWL4030_REG_HS_POPN_SET, hs_pop);
726*4882a593Smuzhiyun 		/* Wait ramp delay time + 1, so the VMID can settle */
727*4882a593Smuzhiyun 		twl4030_wait_ms(delay);
728*4882a593Smuzhiyun 	} else {
729*4882a593Smuzhiyun 		/* Headset ramp-down _not_ according to
730*4882a593Smuzhiyun 		 * the TRM, but in a way that it is working */
731*4882a593Smuzhiyun 		hs_pop &= ~TWL4030_RAMP_EN;
732*4882a593Smuzhiyun 		twl4030_write(component, TWL4030_REG_HS_POPN_SET, hs_pop);
733*4882a593Smuzhiyun 		/* Wait ramp delay time + 1, so the VMID can settle */
734*4882a593Smuzhiyun 		twl4030_wait_ms(delay);
735*4882a593Smuzhiyun 		/* Bypass the reg_cache to mute the headset */
736*4882a593Smuzhiyun 		twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, hs_gain & (~0x0f),
737*4882a593Smuzhiyun 				 TWL4030_REG_HS_GAIN_SET);
738*4882a593Smuzhiyun 
739*4882a593Smuzhiyun 		hs_pop &= ~TWL4030_VMID_EN;
740*4882a593Smuzhiyun 		twl4030_write(component, TWL4030_REG_HS_POPN_SET, hs_pop);
741*4882a593Smuzhiyun 	}
742*4882a593Smuzhiyun 
743*4882a593Smuzhiyun 	/* Disable external mute */
744*4882a593Smuzhiyun 	if (pdata && pdata->hs_extmute) {
745*4882a593Smuzhiyun 		if (gpio_is_valid(pdata->hs_extmute_gpio)) {
746*4882a593Smuzhiyun 			gpio_set_value(pdata->hs_extmute_gpio, 0);
747*4882a593Smuzhiyun 		} else {
748*4882a593Smuzhiyun 			hs_pop &= ~TWL4030_EXTMUTE;
749*4882a593Smuzhiyun 			twl4030_write(component, TWL4030_REG_HS_POPN_SET, hs_pop);
750*4882a593Smuzhiyun 		}
751*4882a593Smuzhiyun 	}
752*4882a593Smuzhiyun }
753*4882a593Smuzhiyun 
headsetlpga_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)754*4882a593Smuzhiyun static int headsetlpga_event(struct snd_soc_dapm_widget *w,
755*4882a593Smuzhiyun 			     struct snd_kcontrol *kcontrol, int event)
756*4882a593Smuzhiyun {
757*4882a593Smuzhiyun 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
758*4882a593Smuzhiyun 	struct twl4030_priv *twl4030 = snd_soc_component_get_drvdata(component);
759*4882a593Smuzhiyun 
760*4882a593Smuzhiyun 	switch (event) {
761*4882a593Smuzhiyun 	case SND_SOC_DAPM_POST_PMU:
762*4882a593Smuzhiyun 		/* Do the ramp-up only once */
763*4882a593Smuzhiyun 		if (!twl4030->hsr_enabled)
764*4882a593Smuzhiyun 			headset_ramp(component, 1);
765*4882a593Smuzhiyun 
766*4882a593Smuzhiyun 		twl4030->hsl_enabled = 1;
767*4882a593Smuzhiyun 		break;
768*4882a593Smuzhiyun 	case SND_SOC_DAPM_POST_PMD:
769*4882a593Smuzhiyun 		/* Do the ramp-down only if both headsetL/R is disabled */
770*4882a593Smuzhiyun 		if (!twl4030->hsr_enabled)
771*4882a593Smuzhiyun 			headset_ramp(component, 0);
772*4882a593Smuzhiyun 
773*4882a593Smuzhiyun 		twl4030->hsl_enabled = 0;
774*4882a593Smuzhiyun 		break;
775*4882a593Smuzhiyun 	}
776*4882a593Smuzhiyun 	return 0;
777*4882a593Smuzhiyun }
778*4882a593Smuzhiyun 
headsetrpga_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)779*4882a593Smuzhiyun static int headsetrpga_event(struct snd_soc_dapm_widget *w,
780*4882a593Smuzhiyun 			     struct snd_kcontrol *kcontrol, int event)
781*4882a593Smuzhiyun {
782*4882a593Smuzhiyun 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
783*4882a593Smuzhiyun 	struct twl4030_priv *twl4030 = snd_soc_component_get_drvdata(component);
784*4882a593Smuzhiyun 
785*4882a593Smuzhiyun 	switch (event) {
786*4882a593Smuzhiyun 	case SND_SOC_DAPM_POST_PMU:
787*4882a593Smuzhiyun 		/* Do the ramp-up only once */
788*4882a593Smuzhiyun 		if (!twl4030->hsl_enabled)
789*4882a593Smuzhiyun 			headset_ramp(component, 1);
790*4882a593Smuzhiyun 
791*4882a593Smuzhiyun 		twl4030->hsr_enabled = 1;
792*4882a593Smuzhiyun 		break;
793*4882a593Smuzhiyun 	case SND_SOC_DAPM_POST_PMD:
794*4882a593Smuzhiyun 		/* Do the ramp-down only if both headsetL/R is disabled */
795*4882a593Smuzhiyun 		if (!twl4030->hsl_enabled)
796*4882a593Smuzhiyun 			headset_ramp(component, 0);
797*4882a593Smuzhiyun 
798*4882a593Smuzhiyun 		twl4030->hsr_enabled = 0;
799*4882a593Smuzhiyun 		break;
800*4882a593Smuzhiyun 	}
801*4882a593Smuzhiyun 	return 0;
802*4882a593Smuzhiyun }
803*4882a593Smuzhiyun 
digimic_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)804*4882a593Smuzhiyun static int digimic_event(struct snd_soc_dapm_widget *w,
805*4882a593Smuzhiyun 			 struct snd_kcontrol *kcontrol, int event)
806*4882a593Smuzhiyun {
807*4882a593Smuzhiyun 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
808*4882a593Smuzhiyun 	struct twl4030_priv *twl4030 = snd_soc_component_get_drvdata(component);
809*4882a593Smuzhiyun 	struct twl4030_codec_data *pdata = twl4030->pdata;
810*4882a593Smuzhiyun 
811*4882a593Smuzhiyun 	if (pdata && pdata->digimic_delay)
812*4882a593Smuzhiyun 		twl4030_wait_ms(pdata->digimic_delay);
813*4882a593Smuzhiyun 	return 0;
814*4882a593Smuzhiyun }
815*4882a593Smuzhiyun 
816*4882a593Smuzhiyun /*
817*4882a593Smuzhiyun  * Some of the gain controls in TWL (mostly those which are associated with
818*4882a593Smuzhiyun  * the outputs) are implemented in an interesting way:
819*4882a593Smuzhiyun  * 0x0 : Power down (mute)
820*4882a593Smuzhiyun  * 0x1 : 6dB
821*4882a593Smuzhiyun  * 0x2 : 0 dB
822*4882a593Smuzhiyun  * 0x3 : -6 dB
823*4882a593Smuzhiyun  * Inverting not going to help with these.
824*4882a593Smuzhiyun  * Custom volsw and volsw_2r get/put functions to handle these gain bits.
825*4882a593Smuzhiyun  */
snd_soc_get_volsw_twl4030(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)826*4882a593Smuzhiyun static int snd_soc_get_volsw_twl4030(struct snd_kcontrol *kcontrol,
827*4882a593Smuzhiyun 				     struct snd_ctl_elem_value *ucontrol)
828*4882a593Smuzhiyun {
829*4882a593Smuzhiyun 	struct soc_mixer_control *mc =
830*4882a593Smuzhiyun 		(struct soc_mixer_control *)kcontrol->private_value;
831*4882a593Smuzhiyun 	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
832*4882a593Smuzhiyun 	unsigned int reg = mc->reg;
833*4882a593Smuzhiyun 	unsigned int shift = mc->shift;
834*4882a593Smuzhiyun 	unsigned int rshift = mc->rshift;
835*4882a593Smuzhiyun 	int max = mc->max;
836*4882a593Smuzhiyun 	int mask = (1 << fls(max)) - 1;
837*4882a593Smuzhiyun 
838*4882a593Smuzhiyun 	ucontrol->value.integer.value[0] =
839*4882a593Smuzhiyun 		(twl4030_read(component, reg) >> shift) & mask;
840*4882a593Smuzhiyun 	if (ucontrol->value.integer.value[0])
841*4882a593Smuzhiyun 		ucontrol->value.integer.value[0] =
842*4882a593Smuzhiyun 			max + 1 - ucontrol->value.integer.value[0];
843*4882a593Smuzhiyun 
844*4882a593Smuzhiyun 	if (shift != rshift) {
845*4882a593Smuzhiyun 		ucontrol->value.integer.value[1] =
846*4882a593Smuzhiyun 			(twl4030_read(component, reg) >> rshift) & mask;
847*4882a593Smuzhiyun 		if (ucontrol->value.integer.value[1])
848*4882a593Smuzhiyun 			ucontrol->value.integer.value[1] =
849*4882a593Smuzhiyun 				max + 1 - ucontrol->value.integer.value[1];
850*4882a593Smuzhiyun 	}
851*4882a593Smuzhiyun 
852*4882a593Smuzhiyun 	return 0;
853*4882a593Smuzhiyun }
854*4882a593Smuzhiyun 
snd_soc_put_volsw_twl4030(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)855*4882a593Smuzhiyun static int snd_soc_put_volsw_twl4030(struct snd_kcontrol *kcontrol,
856*4882a593Smuzhiyun 				     struct snd_ctl_elem_value *ucontrol)
857*4882a593Smuzhiyun {
858*4882a593Smuzhiyun 	struct soc_mixer_control *mc =
859*4882a593Smuzhiyun 		(struct soc_mixer_control *)kcontrol->private_value;
860*4882a593Smuzhiyun 	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
861*4882a593Smuzhiyun 	unsigned int reg = mc->reg;
862*4882a593Smuzhiyun 	unsigned int shift = mc->shift;
863*4882a593Smuzhiyun 	unsigned int rshift = mc->rshift;
864*4882a593Smuzhiyun 	int max = mc->max;
865*4882a593Smuzhiyun 	int mask = (1 << fls(max)) - 1;
866*4882a593Smuzhiyun 	unsigned short val, val2, val_mask;
867*4882a593Smuzhiyun 
868*4882a593Smuzhiyun 	val = (ucontrol->value.integer.value[0] & mask);
869*4882a593Smuzhiyun 
870*4882a593Smuzhiyun 	val_mask = mask << shift;
871*4882a593Smuzhiyun 	if (val)
872*4882a593Smuzhiyun 		val = max + 1 - val;
873*4882a593Smuzhiyun 	val = val << shift;
874*4882a593Smuzhiyun 	if (shift != rshift) {
875*4882a593Smuzhiyun 		val2 = (ucontrol->value.integer.value[1] & mask);
876*4882a593Smuzhiyun 		val_mask |= mask << rshift;
877*4882a593Smuzhiyun 		if (val2)
878*4882a593Smuzhiyun 			val2 = max + 1 - val2;
879*4882a593Smuzhiyun 		val |= val2 << rshift;
880*4882a593Smuzhiyun 	}
881*4882a593Smuzhiyun 	return snd_soc_component_update_bits(component, reg, val_mask, val);
882*4882a593Smuzhiyun }
883*4882a593Smuzhiyun 
snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)884*4882a593Smuzhiyun static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
885*4882a593Smuzhiyun 					struct snd_ctl_elem_value *ucontrol)
886*4882a593Smuzhiyun {
887*4882a593Smuzhiyun 	struct soc_mixer_control *mc =
888*4882a593Smuzhiyun 		(struct soc_mixer_control *)kcontrol->private_value;
889*4882a593Smuzhiyun 	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
890*4882a593Smuzhiyun 	unsigned int reg = mc->reg;
891*4882a593Smuzhiyun 	unsigned int reg2 = mc->rreg;
892*4882a593Smuzhiyun 	unsigned int shift = mc->shift;
893*4882a593Smuzhiyun 	int max = mc->max;
894*4882a593Smuzhiyun 	int mask = (1<<fls(max))-1;
895*4882a593Smuzhiyun 
896*4882a593Smuzhiyun 	ucontrol->value.integer.value[0] =
897*4882a593Smuzhiyun 		(twl4030_read(component, reg) >> shift) & mask;
898*4882a593Smuzhiyun 	ucontrol->value.integer.value[1] =
899*4882a593Smuzhiyun 		(twl4030_read(component, reg2) >> shift) & mask;
900*4882a593Smuzhiyun 
901*4882a593Smuzhiyun 	if (ucontrol->value.integer.value[0])
902*4882a593Smuzhiyun 		ucontrol->value.integer.value[0] =
903*4882a593Smuzhiyun 			max + 1 - ucontrol->value.integer.value[0];
904*4882a593Smuzhiyun 	if (ucontrol->value.integer.value[1])
905*4882a593Smuzhiyun 		ucontrol->value.integer.value[1] =
906*4882a593Smuzhiyun 			max + 1 - ucontrol->value.integer.value[1];
907*4882a593Smuzhiyun 
908*4882a593Smuzhiyun 	return 0;
909*4882a593Smuzhiyun }
910*4882a593Smuzhiyun 
snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)911*4882a593Smuzhiyun static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
912*4882a593Smuzhiyun 					struct snd_ctl_elem_value *ucontrol)
913*4882a593Smuzhiyun {
914*4882a593Smuzhiyun 	struct soc_mixer_control *mc =
915*4882a593Smuzhiyun 		(struct soc_mixer_control *)kcontrol->private_value;
916*4882a593Smuzhiyun 	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
917*4882a593Smuzhiyun 	unsigned int reg = mc->reg;
918*4882a593Smuzhiyun 	unsigned int reg2 = mc->rreg;
919*4882a593Smuzhiyun 	unsigned int shift = mc->shift;
920*4882a593Smuzhiyun 	int max = mc->max;
921*4882a593Smuzhiyun 	int mask = (1 << fls(max)) - 1;
922*4882a593Smuzhiyun 	int err;
923*4882a593Smuzhiyun 	unsigned short val, val2, val_mask;
924*4882a593Smuzhiyun 
925*4882a593Smuzhiyun 	val_mask = mask << shift;
926*4882a593Smuzhiyun 	val = (ucontrol->value.integer.value[0] & mask);
927*4882a593Smuzhiyun 	val2 = (ucontrol->value.integer.value[1] & mask);
928*4882a593Smuzhiyun 
929*4882a593Smuzhiyun 	if (val)
930*4882a593Smuzhiyun 		val = max + 1 - val;
931*4882a593Smuzhiyun 	if (val2)
932*4882a593Smuzhiyun 		val2 = max + 1 - val2;
933*4882a593Smuzhiyun 
934*4882a593Smuzhiyun 	val = val << shift;
935*4882a593Smuzhiyun 	val2 = val2 << shift;
936*4882a593Smuzhiyun 
937*4882a593Smuzhiyun 	err = snd_soc_component_update_bits(component, reg, val_mask, val);
938*4882a593Smuzhiyun 	if (err < 0)
939*4882a593Smuzhiyun 		return err;
940*4882a593Smuzhiyun 
941*4882a593Smuzhiyun 	err = snd_soc_component_update_bits(component, reg2, val_mask, val2);
942*4882a593Smuzhiyun 	return err;
943*4882a593Smuzhiyun }
944*4882a593Smuzhiyun 
945*4882a593Smuzhiyun /* Codec operation modes */
946*4882a593Smuzhiyun static const char *twl4030_op_modes_texts[] = {
947*4882a593Smuzhiyun 	"Option 2 (voice/audio)", "Option 1 (audio)"
948*4882a593Smuzhiyun };
949*4882a593Smuzhiyun 
950*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(twl4030_op_modes_enum,
951*4882a593Smuzhiyun 			    TWL4030_REG_CODEC_MODE, 0,
952*4882a593Smuzhiyun 			    twl4030_op_modes_texts);
953*4882a593Smuzhiyun 
snd_soc_put_twl4030_opmode_enum_double(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)954*4882a593Smuzhiyun static int snd_soc_put_twl4030_opmode_enum_double(struct snd_kcontrol *kcontrol,
955*4882a593Smuzhiyun 	struct snd_ctl_elem_value *ucontrol)
956*4882a593Smuzhiyun {
957*4882a593Smuzhiyun 	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
958*4882a593Smuzhiyun 	struct twl4030_priv *twl4030 = snd_soc_component_get_drvdata(component);
959*4882a593Smuzhiyun 
960*4882a593Smuzhiyun 	if (twl4030->configured) {
961*4882a593Smuzhiyun 		dev_err(component->dev,
962*4882a593Smuzhiyun 			"operation mode cannot be changed on-the-fly\n");
963*4882a593Smuzhiyun 		return -EBUSY;
964*4882a593Smuzhiyun 	}
965*4882a593Smuzhiyun 
966*4882a593Smuzhiyun 	return snd_soc_put_enum_double(kcontrol, ucontrol);
967*4882a593Smuzhiyun }
968*4882a593Smuzhiyun 
969*4882a593Smuzhiyun /*
970*4882a593Smuzhiyun  * FGAIN volume control:
971*4882a593Smuzhiyun  * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB)
972*4882a593Smuzhiyun  */
973*4882a593Smuzhiyun static DECLARE_TLV_DB_SCALE(digital_fine_tlv, -6300, 100, 1);
974*4882a593Smuzhiyun 
975*4882a593Smuzhiyun /*
976*4882a593Smuzhiyun  * CGAIN volume control:
977*4882a593Smuzhiyun  * 0 dB to 12 dB in 6 dB steps
978*4882a593Smuzhiyun  * value 2 and 3 means 12 dB
979*4882a593Smuzhiyun  */
980*4882a593Smuzhiyun static DECLARE_TLV_DB_SCALE(digital_coarse_tlv, 0, 600, 0);
981*4882a593Smuzhiyun 
982*4882a593Smuzhiyun /*
983*4882a593Smuzhiyun  * Voice Downlink GAIN volume control:
984*4882a593Smuzhiyun  * from -37 to 12 dB in 1 dB steps (mute instead of -37 dB)
985*4882a593Smuzhiyun  */
986*4882a593Smuzhiyun static DECLARE_TLV_DB_SCALE(digital_voice_downlink_tlv, -3700, 100, 1);
987*4882a593Smuzhiyun 
988*4882a593Smuzhiyun /*
989*4882a593Smuzhiyun  * Analog playback gain
990*4882a593Smuzhiyun  * -24 dB to 12 dB in 2 dB steps
991*4882a593Smuzhiyun  */
992*4882a593Smuzhiyun static DECLARE_TLV_DB_SCALE(analog_tlv, -2400, 200, 0);
993*4882a593Smuzhiyun 
994*4882a593Smuzhiyun /*
995*4882a593Smuzhiyun  * Gain controls tied to outputs
996*4882a593Smuzhiyun  * -6 dB to 6 dB in 6 dB steps (mute instead of -12)
997*4882a593Smuzhiyun  */
998*4882a593Smuzhiyun static DECLARE_TLV_DB_SCALE(output_tvl, -1200, 600, 1);
999*4882a593Smuzhiyun 
1000*4882a593Smuzhiyun /*
1001*4882a593Smuzhiyun  * Gain control for earpiece amplifier
1002*4882a593Smuzhiyun  * 0 dB to 12 dB in 6 dB steps (mute instead of -6)
1003*4882a593Smuzhiyun  */
1004*4882a593Smuzhiyun static DECLARE_TLV_DB_SCALE(output_ear_tvl, -600, 600, 1);
1005*4882a593Smuzhiyun 
1006*4882a593Smuzhiyun /*
1007*4882a593Smuzhiyun  * Capture gain after the ADCs
1008*4882a593Smuzhiyun  * from 0 dB to 31 dB in 1 dB steps
1009*4882a593Smuzhiyun  */
1010*4882a593Smuzhiyun static DECLARE_TLV_DB_SCALE(digital_capture_tlv, 0, 100, 0);
1011*4882a593Smuzhiyun 
1012*4882a593Smuzhiyun /*
1013*4882a593Smuzhiyun  * Gain control for input amplifiers
1014*4882a593Smuzhiyun  * 0 dB to 30 dB in 6 dB steps
1015*4882a593Smuzhiyun  */
1016*4882a593Smuzhiyun static DECLARE_TLV_DB_SCALE(input_gain_tlv, 0, 600, 0);
1017*4882a593Smuzhiyun 
1018*4882a593Smuzhiyun /* AVADC clock priority */
1019*4882a593Smuzhiyun static const char *twl4030_avadc_clk_priority_texts[] = {
1020*4882a593Smuzhiyun 	"Voice high priority", "HiFi high priority"
1021*4882a593Smuzhiyun };
1022*4882a593Smuzhiyun 
1023*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(twl4030_avadc_clk_priority_enum,
1024*4882a593Smuzhiyun 			    TWL4030_REG_AVADC_CTL, 2,
1025*4882a593Smuzhiyun 			    twl4030_avadc_clk_priority_texts);
1026*4882a593Smuzhiyun 
1027*4882a593Smuzhiyun static const char *twl4030_rampdelay_texts[] = {
1028*4882a593Smuzhiyun 	"27/20/14 ms", "55/40/27 ms", "109/81/55 ms", "218/161/109 ms",
1029*4882a593Smuzhiyun 	"437/323/218 ms", "874/645/437 ms", "1748/1291/874 ms",
1030*4882a593Smuzhiyun 	"3495/2581/1748 ms"
1031*4882a593Smuzhiyun };
1032*4882a593Smuzhiyun 
1033*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(twl4030_rampdelay_enum,
1034*4882a593Smuzhiyun 			    TWL4030_REG_HS_POPN_SET, 2,
1035*4882a593Smuzhiyun 			    twl4030_rampdelay_texts);
1036*4882a593Smuzhiyun 
1037*4882a593Smuzhiyun /* Vibra H-bridge direction mode */
1038*4882a593Smuzhiyun static const char *twl4030_vibradirmode_texts[] = {
1039*4882a593Smuzhiyun 	"Vibra H-bridge direction", "Audio data MSB",
1040*4882a593Smuzhiyun };
1041*4882a593Smuzhiyun 
1042*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(twl4030_vibradirmode_enum,
1043*4882a593Smuzhiyun 			    TWL4030_REG_VIBRA_CTL, 5,
1044*4882a593Smuzhiyun 			    twl4030_vibradirmode_texts);
1045*4882a593Smuzhiyun 
1046*4882a593Smuzhiyun /* Vibra H-bridge direction */
1047*4882a593Smuzhiyun static const char *twl4030_vibradir_texts[] = {
1048*4882a593Smuzhiyun 	"Positive polarity", "Negative polarity",
1049*4882a593Smuzhiyun };
1050*4882a593Smuzhiyun 
1051*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(twl4030_vibradir_enum,
1052*4882a593Smuzhiyun 			    TWL4030_REG_VIBRA_CTL, 1,
1053*4882a593Smuzhiyun 			    twl4030_vibradir_texts);
1054*4882a593Smuzhiyun 
1055*4882a593Smuzhiyun /* Digimic Left and right swapping */
1056*4882a593Smuzhiyun static const char *twl4030_digimicswap_texts[] = {
1057*4882a593Smuzhiyun 	"Not swapped", "Swapped",
1058*4882a593Smuzhiyun };
1059*4882a593Smuzhiyun 
1060*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(twl4030_digimicswap_enum,
1061*4882a593Smuzhiyun 			    TWL4030_REG_MISC_SET_1, 0,
1062*4882a593Smuzhiyun 			    twl4030_digimicswap_texts);
1063*4882a593Smuzhiyun 
1064*4882a593Smuzhiyun static const struct snd_kcontrol_new twl4030_snd_controls[] = {
1065*4882a593Smuzhiyun 	/* Codec operation mode control */
1066*4882a593Smuzhiyun 	SOC_ENUM_EXT("Codec Operation Mode", twl4030_op_modes_enum,
1067*4882a593Smuzhiyun 		snd_soc_get_enum_double,
1068*4882a593Smuzhiyun 		snd_soc_put_twl4030_opmode_enum_double),
1069*4882a593Smuzhiyun 
1070*4882a593Smuzhiyun 	/* Common playback gain controls */
1071*4882a593Smuzhiyun 	SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume",
1072*4882a593Smuzhiyun 		TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
1073*4882a593Smuzhiyun 		0, 0x3f, 0, digital_fine_tlv),
1074*4882a593Smuzhiyun 	SOC_DOUBLE_R_TLV("DAC2 Digital Fine Playback Volume",
1075*4882a593Smuzhiyun 		TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
1076*4882a593Smuzhiyun 		0, 0x3f, 0, digital_fine_tlv),
1077*4882a593Smuzhiyun 
1078*4882a593Smuzhiyun 	SOC_DOUBLE_R_TLV("DAC1 Digital Coarse Playback Volume",
1079*4882a593Smuzhiyun 		TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
1080*4882a593Smuzhiyun 		6, 0x2, 0, digital_coarse_tlv),
1081*4882a593Smuzhiyun 	SOC_DOUBLE_R_TLV("DAC2 Digital Coarse Playback Volume",
1082*4882a593Smuzhiyun 		TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
1083*4882a593Smuzhiyun 		6, 0x2, 0, digital_coarse_tlv),
1084*4882a593Smuzhiyun 
1085*4882a593Smuzhiyun 	SOC_DOUBLE_R_TLV("DAC1 Analog Playback Volume",
1086*4882a593Smuzhiyun 		TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
1087*4882a593Smuzhiyun 		3, 0x12, 1, analog_tlv),
1088*4882a593Smuzhiyun 	SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume",
1089*4882a593Smuzhiyun 		TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
1090*4882a593Smuzhiyun 		3, 0x12, 1, analog_tlv),
1091*4882a593Smuzhiyun 	SOC_DOUBLE_R("DAC1 Analog Playback Switch",
1092*4882a593Smuzhiyun 		TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
1093*4882a593Smuzhiyun 		1, 1, 0),
1094*4882a593Smuzhiyun 	SOC_DOUBLE_R("DAC2 Analog Playback Switch",
1095*4882a593Smuzhiyun 		TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
1096*4882a593Smuzhiyun 		1, 1, 0),
1097*4882a593Smuzhiyun 
1098*4882a593Smuzhiyun 	/* Common voice downlink gain controls */
1099*4882a593Smuzhiyun 	SOC_SINGLE_TLV("DAC Voice Digital Downlink Volume",
1100*4882a593Smuzhiyun 		TWL4030_REG_VRXPGA, 0, 0x31, 0, digital_voice_downlink_tlv),
1101*4882a593Smuzhiyun 
1102*4882a593Smuzhiyun 	SOC_SINGLE_TLV("DAC Voice Analog Downlink Volume",
1103*4882a593Smuzhiyun 		TWL4030_REG_VDL_APGA_CTL, 3, 0x12, 1, analog_tlv),
1104*4882a593Smuzhiyun 
1105*4882a593Smuzhiyun 	SOC_SINGLE("DAC Voice Analog Downlink Switch",
1106*4882a593Smuzhiyun 		TWL4030_REG_VDL_APGA_CTL, 1, 1, 0),
1107*4882a593Smuzhiyun 
1108*4882a593Smuzhiyun 	/* Separate output gain controls */
1109*4882a593Smuzhiyun 	SOC_DOUBLE_R_EXT_TLV("PreDriv Playback Volume",
1110*4882a593Smuzhiyun 		TWL4030_REG_PREDL_CTL, TWL4030_REG_PREDR_CTL,
1111*4882a593Smuzhiyun 		4, 3, 0, snd_soc_get_volsw_r2_twl4030,
1112*4882a593Smuzhiyun 		snd_soc_put_volsw_r2_twl4030, output_tvl),
1113*4882a593Smuzhiyun 
1114*4882a593Smuzhiyun 	SOC_DOUBLE_EXT_TLV("Headset Playback Volume",
1115*4882a593Smuzhiyun 		TWL4030_REG_HS_GAIN_SET, 0, 2, 3, 0, snd_soc_get_volsw_twl4030,
1116*4882a593Smuzhiyun 		snd_soc_put_volsw_twl4030, output_tvl),
1117*4882a593Smuzhiyun 
1118*4882a593Smuzhiyun 	SOC_DOUBLE_R_EXT_TLV("Carkit Playback Volume",
1119*4882a593Smuzhiyun 		TWL4030_REG_PRECKL_CTL, TWL4030_REG_PRECKR_CTL,
1120*4882a593Smuzhiyun 		4, 3, 0, snd_soc_get_volsw_r2_twl4030,
1121*4882a593Smuzhiyun 		snd_soc_put_volsw_r2_twl4030, output_tvl),
1122*4882a593Smuzhiyun 
1123*4882a593Smuzhiyun 	SOC_SINGLE_EXT_TLV("Earpiece Playback Volume",
1124*4882a593Smuzhiyun 		TWL4030_REG_EAR_CTL, 4, 3, 0, snd_soc_get_volsw_twl4030,
1125*4882a593Smuzhiyun 		snd_soc_put_volsw_twl4030, output_ear_tvl),
1126*4882a593Smuzhiyun 
1127*4882a593Smuzhiyun 	/* Common capture gain controls */
1128*4882a593Smuzhiyun 	SOC_DOUBLE_R_TLV("TX1 Digital Capture Volume",
1129*4882a593Smuzhiyun 		TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA,
1130*4882a593Smuzhiyun 		0, 0x1f, 0, digital_capture_tlv),
1131*4882a593Smuzhiyun 	SOC_DOUBLE_R_TLV("TX2 Digital Capture Volume",
1132*4882a593Smuzhiyun 		TWL4030_REG_AVTXL2PGA, TWL4030_REG_AVTXR2PGA,
1133*4882a593Smuzhiyun 		0, 0x1f, 0, digital_capture_tlv),
1134*4882a593Smuzhiyun 
1135*4882a593Smuzhiyun 	SOC_DOUBLE_TLV("Analog Capture Volume", TWL4030_REG_ANAMIC_GAIN,
1136*4882a593Smuzhiyun 		0, 3, 5, 0, input_gain_tlv),
1137*4882a593Smuzhiyun 
1138*4882a593Smuzhiyun 	SOC_ENUM("AVADC Clock Priority", twl4030_avadc_clk_priority_enum),
1139*4882a593Smuzhiyun 
1140*4882a593Smuzhiyun 	SOC_ENUM("HS ramp delay", twl4030_rampdelay_enum),
1141*4882a593Smuzhiyun 
1142*4882a593Smuzhiyun 	SOC_ENUM("Vibra H-bridge mode", twl4030_vibradirmode_enum),
1143*4882a593Smuzhiyun 	SOC_ENUM("Vibra H-bridge direction", twl4030_vibradir_enum),
1144*4882a593Smuzhiyun 
1145*4882a593Smuzhiyun 	SOC_ENUM("Digimic LR Swap", twl4030_digimicswap_enum),
1146*4882a593Smuzhiyun };
1147*4882a593Smuzhiyun 
1148*4882a593Smuzhiyun static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
1149*4882a593Smuzhiyun 	/* Left channel inputs */
1150*4882a593Smuzhiyun 	SND_SOC_DAPM_INPUT("MAINMIC"),
1151*4882a593Smuzhiyun 	SND_SOC_DAPM_INPUT("HSMIC"),
1152*4882a593Smuzhiyun 	SND_SOC_DAPM_INPUT("AUXL"),
1153*4882a593Smuzhiyun 	SND_SOC_DAPM_INPUT("CARKITMIC"),
1154*4882a593Smuzhiyun 	/* Right channel inputs */
1155*4882a593Smuzhiyun 	SND_SOC_DAPM_INPUT("SUBMIC"),
1156*4882a593Smuzhiyun 	SND_SOC_DAPM_INPUT("AUXR"),
1157*4882a593Smuzhiyun 	/* Digital microphones (Stereo) */
1158*4882a593Smuzhiyun 	SND_SOC_DAPM_INPUT("DIGIMIC0"),
1159*4882a593Smuzhiyun 	SND_SOC_DAPM_INPUT("DIGIMIC1"),
1160*4882a593Smuzhiyun 
1161*4882a593Smuzhiyun 	/* Outputs */
1162*4882a593Smuzhiyun 	SND_SOC_DAPM_OUTPUT("EARPIECE"),
1163*4882a593Smuzhiyun 	SND_SOC_DAPM_OUTPUT("PREDRIVEL"),
1164*4882a593Smuzhiyun 	SND_SOC_DAPM_OUTPUT("PREDRIVER"),
1165*4882a593Smuzhiyun 	SND_SOC_DAPM_OUTPUT("HSOL"),
1166*4882a593Smuzhiyun 	SND_SOC_DAPM_OUTPUT("HSOR"),
1167*4882a593Smuzhiyun 	SND_SOC_DAPM_OUTPUT("CARKITL"),
1168*4882a593Smuzhiyun 	SND_SOC_DAPM_OUTPUT("CARKITR"),
1169*4882a593Smuzhiyun 	SND_SOC_DAPM_OUTPUT("HFL"),
1170*4882a593Smuzhiyun 	SND_SOC_DAPM_OUTPUT("HFR"),
1171*4882a593Smuzhiyun 	SND_SOC_DAPM_OUTPUT("VIBRA"),
1172*4882a593Smuzhiyun 
1173*4882a593Smuzhiyun 	/* AIF and APLL clocks for running DAIs (including loopback) */
1174*4882a593Smuzhiyun 	SND_SOC_DAPM_OUTPUT("Virtual HiFi OUT"),
1175*4882a593Smuzhiyun 	SND_SOC_DAPM_INPUT("Virtual HiFi IN"),
1176*4882a593Smuzhiyun 	SND_SOC_DAPM_OUTPUT("Virtual Voice OUT"),
1177*4882a593Smuzhiyun 
1178*4882a593Smuzhiyun 	/* DACs */
1179*4882a593Smuzhiyun 	SND_SOC_DAPM_DAC("DAC Right1", NULL, SND_SOC_NOPM, 0, 0),
1180*4882a593Smuzhiyun 	SND_SOC_DAPM_DAC("DAC Left1", NULL, SND_SOC_NOPM, 0, 0),
1181*4882a593Smuzhiyun 	SND_SOC_DAPM_DAC("DAC Right2", NULL, SND_SOC_NOPM, 0, 0),
1182*4882a593Smuzhiyun 	SND_SOC_DAPM_DAC("DAC Left2", NULL, SND_SOC_NOPM, 0, 0),
1183*4882a593Smuzhiyun 	SND_SOC_DAPM_DAC("DAC Voice", NULL, SND_SOC_NOPM, 0, 0),
1184*4882a593Smuzhiyun 
1185*4882a593Smuzhiyun 	SND_SOC_DAPM_AIF_IN("VAIFIN", "Voice Playback", 0,
1186*4882a593Smuzhiyun 			    TWL4030_REG_VOICE_IF, 6, 0),
1187*4882a593Smuzhiyun 
1188*4882a593Smuzhiyun 	/* Analog bypasses */
1189*4882a593Smuzhiyun 	SND_SOC_DAPM_SWITCH("Right1 Analog Loopback", SND_SOC_NOPM, 0, 0,
1190*4882a593Smuzhiyun 			&twl4030_dapm_abypassr1_control),
1191*4882a593Smuzhiyun 	SND_SOC_DAPM_SWITCH("Left1 Analog Loopback", SND_SOC_NOPM, 0, 0,
1192*4882a593Smuzhiyun 			&twl4030_dapm_abypassl1_control),
1193*4882a593Smuzhiyun 	SND_SOC_DAPM_SWITCH("Right2 Analog Loopback", SND_SOC_NOPM, 0, 0,
1194*4882a593Smuzhiyun 			&twl4030_dapm_abypassr2_control),
1195*4882a593Smuzhiyun 	SND_SOC_DAPM_SWITCH("Left2 Analog Loopback", SND_SOC_NOPM, 0, 0,
1196*4882a593Smuzhiyun 			&twl4030_dapm_abypassl2_control),
1197*4882a593Smuzhiyun 	SND_SOC_DAPM_SWITCH("Voice Analog Loopback", SND_SOC_NOPM, 0, 0,
1198*4882a593Smuzhiyun 			&twl4030_dapm_abypassv_control),
1199*4882a593Smuzhiyun 
1200*4882a593Smuzhiyun 	/* Master analog loopback switch */
1201*4882a593Smuzhiyun 	SND_SOC_DAPM_SUPPLY("FM Loop Enable", TWL4030_REG_MISC_SET_1, 5, 0,
1202*4882a593Smuzhiyun 			    NULL, 0),
1203*4882a593Smuzhiyun 
1204*4882a593Smuzhiyun 	/* Digital bypasses */
1205*4882a593Smuzhiyun 	SND_SOC_DAPM_SWITCH("Left Digital Loopback", SND_SOC_NOPM, 0, 0,
1206*4882a593Smuzhiyun 			&twl4030_dapm_dbypassl_control),
1207*4882a593Smuzhiyun 	SND_SOC_DAPM_SWITCH("Right Digital Loopback", SND_SOC_NOPM, 0, 0,
1208*4882a593Smuzhiyun 			&twl4030_dapm_dbypassr_control),
1209*4882a593Smuzhiyun 	SND_SOC_DAPM_SWITCH("Voice Digital Loopback", SND_SOC_NOPM, 0, 0,
1210*4882a593Smuzhiyun 			&twl4030_dapm_dbypassv_control),
1211*4882a593Smuzhiyun 
1212*4882a593Smuzhiyun 	/* Digital mixers, power control for the physical DACs */
1213*4882a593Smuzhiyun 	SND_SOC_DAPM_MIXER("Digital R1 Playback Mixer",
1214*4882a593Smuzhiyun 			TWL4030_REG_AVDAC_CTL, 0, 0, NULL, 0),
1215*4882a593Smuzhiyun 	SND_SOC_DAPM_MIXER("Digital L1 Playback Mixer",
1216*4882a593Smuzhiyun 			TWL4030_REG_AVDAC_CTL, 1, 0, NULL, 0),
1217*4882a593Smuzhiyun 	SND_SOC_DAPM_MIXER("Digital R2 Playback Mixer",
1218*4882a593Smuzhiyun 			TWL4030_REG_AVDAC_CTL, 2, 0, NULL, 0),
1219*4882a593Smuzhiyun 	SND_SOC_DAPM_MIXER("Digital L2 Playback Mixer",
1220*4882a593Smuzhiyun 			TWL4030_REG_AVDAC_CTL, 3, 0, NULL, 0),
1221*4882a593Smuzhiyun 	SND_SOC_DAPM_MIXER("Digital Voice Playback Mixer",
1222*4882a593Smuzhiyun 			TWL4030_REG_AVDAC_CTL, 4, 0, NULL, 0),
1223*4882a593Smuzhiyun 
1224*4882a593Smuzhiyun 	/* Analog mixers, power control for the physical PGAs */
1225*4882a593Smuzhiyun 	SND_SOC_DAPM_MIXER("Analog R1 Playback Mixer",
1226*4882a593Smuzhiyun 			TWL4030_REG_ARXR1_APGA_CTL, 0, 0, NULL, 0),
1227*4882a593Smuzhiyun 	SND_SOC_DAPM_MIXER("Analog L1 Playback Mixer",
1228*4882a593Smuzhiyun 			TWL4030_REG_ARXL1_APGA_CTL, 0, 0, NULL, 0),
1229*4882a593Smuzhiyun 	SND_SOC_DAPM_MIXER("Analog R2 Playback Mixer",
1230*4882a593Smuzhiyun 			TWL4030_REG_ARXR2_APGA_CTL, 0, 0, NULL, 0),
1231*4882a593Smuzhiyun 	SND_SOC_DAPM_MIXER("Analog L2 Playback Mixer",
1232*4882a593Smuzhiyun 			TWL4030_REG_ARXL2_APGA_CTL, 0, 0, NULL, 0),
1233*4882a593Smuzhiyun 	SND_SOC_DAPM_MIXER("Analog Voice Playback Mixer",
1234*4882a593Smuzhiyun 			TWL4030_REG_VDL_APGA_CTL, 0, 0, NULL, 0),
1235*4882a593Smuzhiyun 
1236*4882a593Smuzhiyun 	SND_SOC_DAPM_SUPPLY("APLL Enable", SND_SOC_NOPM, 0, 0, apll_event,
1237*4882a593Smuzhiyun 			    SND_SOC_DAPM_PRE_PMU|SND_SOC_DAPM_POST_PMD),
1238*4882a593Smuzhiyun 
1239*4882a593Smuzhiyun 	SND_SOC_DAPM_SUPPLY("AIF Enable", SND_SOC_NOPM, 0, 0, aif_event,
1240*4882a593Smuzhiyun 			    SND_SOC_DAPM_PRE_PMU|SND_SOC_DAPM_POST_PMD),
1241*4882a593Smuzhiyun 
1242*4882a593Smuzhiyun 	/* Output MIXER controls */
1243*4882a593Smuzhiyun 	/* Earpiece */
1244*4882a593Smuzhiyun 	SND_SOC_DAPM_MIXER("Earpiece Mixer", SND_SOC_NOPM, 0, 0,
1245*4882a593Smuzhiyun 			&twl4030_dapm_earpiece_controls[0],
1246*4882a593Smuzhiyun 			ARRAY_SIZE(twl4030_dapm_earpiece_controls)),
1247*4882a593Smuzhiyun 	SND_SOC_DAPM_PGA_E("Earpiece PGA", SND_SOC_NOPM,
1248*4882a593Smuzhiyun 			0, 0, NULL, 0, earpiecepga_event,
1249*4882a593Smuzhiyun 			SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1250*4882a593Smuzhiyun 	/* PreDrivL/R */
1251*4882a593Smuzhiyun 	SND_SOC_DAPM_MIXER("PredriveL Mixer", SND_SOC_NOPM, 0, 0,
1252*4882a593Smuzhiyun 			&twl4030_dapm_predrivel_controls[0],
1253*4882a593Smuzhiyun 			ARRAY_SIZE(twl4030_dapm_predrivel_controls)),
1254*4882a593Smuzhiyun 	SND_SOC_DAPM_PGA_E("PredriveL PGA", SND_SOC_NOPM,
1255*4882a593Smuzhiyun 			0, 0, NULL, 0, predrivelpga_event,
1256*4882a593Smuzhiyun 			SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1257*4882a593Smuzhiyun 	SND_SOC_DAPM_MIXER("PredriveR Mixer", SND_SOC_NOPM, 0, 0,
1258*4882a593Smuzhiyun 			&twl4030_dapm_predriver_controls[0],
1259*4882a593Smuzhiyun 			ARRAY_SIZE(twl4030_dapm_predriver_controls)),
1260*4882a593Smuzhiyun 	SND_SOC_DAPM_PGA_E("PredriveR PGA", SND_SOC_NOPM,
1261*4882a593Smuzhiyun 			0, 0, NULL, 0, predriverpga_event,
1262*4882a593Smuzhiyun 			SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1263*4882a593Smuzhiyun 	/* HeadsetL/R */
1264*4882a593Smuzhiyun 	SND_SOC_DAPM_MIXER("HeadsetL Mixer", SND_SOC_NOPM, 0, 0,
1265*4882a593Smuzhiyun 			&twl4030_dapm_hsol_controls[0],
1266*4882a593Smuzhiyun 			ARRAY_SIZE(twl4030_dapm_hsol_controls)),
1267*4882a593Smuzhiyun 	SND_SOC_DAPM_PGA_E("HeadsetL PGA", SND_SOC_NOPM,
1268*4882a593Smuzhiyun 			0, 0, NULL, 0, headsetlpga_event,
1269*4882a593Smuzhiyun 			SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1270*4882a593Smuzhiyun 	SND_SOC_DAPM_MIXER("HeadsetR Mixer", SND_SOC_NOPM, 0, 0,
1271*4882a593Smuzhiyun 			&twl4030_dapm_hsor_controls[0],
1272*4882a593Smuzhiyun 			ARRAY_SIZE(twl4030_dapm_hsor_controls)),
1273*4882a593Smuzhiyun 	SND_SOC_DAPM_PGA_E("HeadsetR PGA", SND_SOC_NOPM,
1274*4882a593Smuzhiyun 			0, 0, NULL, 0, headsetrpga_event,
1275*4882a593Smuzhiyun 			SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1276*4882a593Smuzhiyun 	/* CarkitL/R */
1277*4882a593Smuzhiyun 	SND_SOC_DAPM_MIXER("CarkitL Mixer", SND_SOC_NOPM, 0, 0,
1278*4882a593Smuzhiyun 			&twl4030_dapm_carkitl_controls[0],
1279*4882a593Smuzhiyun 			ARRAY_SIZE(twl4030_dapm_carkitl_controls)),
1280*4882a593Smuzhiyun 	SND_SOC_DAPM_PGA_E("CarkitL PGA", SND_SOC_NOPM,
1281*4882a593Smuzhiyun 			0, 0, NULL, 0, carkitlpga_event,
1282*4882a593Smuzhiyun 			SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1283*4882a593Smuzhiyun 	SND_SOC_DAPM_MIXER("CarkitR Mixer", SND_SOC_NOPM, 0, 0,
1284*4882a593Smuzhiyun 			&twl4030_dapm_carkitr_controls[0],
1285*4882a593Smuzhiyun 			ARRAY_SIZE(twl4030_dapm_carkitr_controls)),
1286*4882a593Smuzhiyun 	SND_SOC_DAPM_PGA_E("CarkitR PGA", SND_SOC_NOPM,
1287*4882a593Smuzhiyun 			0, 0, NULL, 0, carkitrpga_event,
1288*4882a593Smuzhiyun 			SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1289*4882a593Smuzhiyun 
1290*4882a593Smuzhiyun 	/* Output MUX controls */
1291*4882a593Smuzhiyun 	/* HandsfreeL/R */
1292*4882a593Smuzhiyun 	SND_SOC_DAPM_MUX("HandsfreeL Mux", SND_SOC_NOPM, 0, 0,
1293*4882a593Smuzhiyun 		&twl4030_dapm_handsfreel_control),
1294*4882a593Smuzhiyun 	SND_SOC_DAPM_SWITCH("HandsfreeL", SND_SOC_NOPM, 0, 0,
1295*4882a593Smuzhiyun 			&twl4030_dapm_handsfreelmute_control),
1296*4882a593Smuzhiyun 	SND_SOC_DAPM_PGA_E("HandsfreeL PGA", SND_SOC_NOPM,
1297*4882a593Smuzhiyun 			0, 0, NULL, 0, handsfreelpga_event,
1298*4882a593Smuzhiyun 			SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1299*4882a593Smuzhiyun 	SND_SOC_DAPM_MUX("HandsfreeR Mux", SND_SOC_NOPM, 5, 0,
1300*4882a593Smuzhiyun 		&twl4030_dapm_handsfreer_control),
1301*4882a593Smuzhiyun 	SND_SOC_DAPM_SWITCH("HandsfreeR", SND_SOC_NOPM, 0, 0,
1302*4882a593Smuzhiyun 			&twl4030_dapm_handsfreermute_control),
1303*4882a593Smuzhiyun 	SND_SOC_DAPM_PGA_E("HandsfreeR PGA", SND_SOC_NOPM,
1304*4882a593Smuzhiyun 			0, 0, NULL, 0, handsfreerpga_event,
1305*4882a593Smuzhiyun 			SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1306*4882a593Smuzhiyun 	/* Vibra */
1307*4882a593Smuzhiyun 	SND_SOC_DAPM_MUX_E("Vibra Mux", TWL4030_REG_VIBRA_CTL, 0, 0,
1308*4882a593Smuzhiyun 			   &twl4030_dapm_vibra_control, vibramux_event,
1309*4882a593Smuzhiyun 			   SND_SOC_DAPM_PRE_PMU),
1310*4882a593Smuzhiyun 	SND_SOC_DAPM_MUX("Vibra Route", SND_SOC_NOPM, 0, 0,
1311*4882a593Smuzhiyun 		&twl4030_dapm_vibrapath_control),
1312*4882a593Smuzhiyun 
1313*4882a593Smuzhiyun 	/* Introducing four virtual ADC, since TWL4030 have four channel for
1314*4882a593Smuzhiyun 	   capture */
1315*4882a593Smuzhiyun 	SND_SOC_DAPM_ADC("ADC Virtual Left1", NULL, SND_SOC_NOPM, 0, 0),
1316*4882a593Smuzhiyun 	SND_SOC_DAPM_ADC("ADC Virtual Right1", NULL, SND_SOC_NOPM, 0, 0),
1317*4882a593Smuzhiyun 	SND_SOC_DAPM_ADC("ADC Virtual Left2", NULL, SND_SOC_NOPM, 0, 0),
1318*4882a593Smuzhiyun 	SND_SOC_DAPM_ADC("ADC Virtual Right2", NULL, SND_SOC_NOPM, 0, 0),
1319*4882a593Smuzhiyun 
1320*4882a593Smuzhiyun 	SND_SOC_DAPM_AIF_OUT("VAIFOUT", "Voice Capture", 0,
1321*4882a593Smuzhiyun 			     TWL4030_REG_VOICE_IF, 5, 0),
1322*4882a593Smuzhiyun 
1323*4882a593Smuzhiyun 	/* Analog/Digital mic path selection.
1324*4882a593Smuzhiyun 	   TX1 Left/Right: either analog Left/Right or Digimic0
1325*4882a593Smuzhiyun 	   TX2 Left/Right: either analog Left/Right or Digimic1 */
1326*4882a593Smuzhiyun 	SND_SOC_DAPM_MUX("TX1 Capture Route", SND_SOC_NOPM, 0, 0,
1327*4882a593Smuzhiyun 		&twl4030_dapm_micpathtx1_control),
1328*4882a593Smuzhiyun 	SND_SOC_DAPM_MUX("TX2 Capture Route", SND_SOC_NOPM, 0, 0,
1329*4882a593Smuzhiyun 		&twl4030_dapm_micpathtx2_control),
1330*4882a593Smuzhiyun 
1331*4882a593Smuzhiyun 	/* Analog input mixers for the capture amplifiers */
1332*4882a593Smuzhiyun 	SND_SOC_DAPM_MIXER("Analog Left",
1333*4882a593Smuzhiyun 		TWL4030_REG_ANAMICL, 4, 0,
1334*4882a593Smuzhiyun 		&twl4030_dapm_analoglmic_controls[0],
1335*4882a593Smuzhiyun 		ARRAY_SIZE(twl4030_dapm_analoglmic_controls)),
1336*4882a593Smuzhiyun 	SND_SOC_DAPM_MIXER("Analog Right",
1337*4882a593Smuzhiyun 		TWL4030_REG_ANAMICR, 4, 0,
1338*4882a593Smuzhiyun 		&twl4030_dapm_analogrmic_controls[0],
1339*4882a593Smuzhiyun 		ARRAY_SIZE(twl4030_dapm_analogrmic_controls)),
1340*4882a593Smuzhiyun 
1341*4882a593Smuzhiyun 	SND_SOC_DAPM_PGA("ADC Physical Left",
1342*4882a593Smuzhiyun 		TWL4030_REG_AVADC_CTL, 3, 0, NULL, 0),
1343*4882a593Smuzhiyun 	SND_SOC_DAPM_PGA("ADC Physical Right",
1344*4882a593Smuzhiyun 		TWL4030_REG_AVADC_CTL, 1, 0, NULL, 0),
1345*4882a593Smuzhiyun 
1346*4882a593Smuzhiyun 	SND_SOC_DAPM_PGA_E("Digimic0 Enable",
1347*4882a593Smuzhiyun 		TWL4030_REG_ADCMICSEL, 1, 0, NULL, 0,
1348*4882a593Smuzhiyun 		digimic_event, SND_SOC_DAPM_POST_PMU),
1349*4882a593Smuzhiyun 	SND_SOC_DAPM_PGA_E("Digimic1 Enable",
1350*4882a593Smuzhiyun 		TWL4030_REG_ADCMICSEL, 3, 0, NULL, 0,
1351*4882a593Smuzhiyun 		digimic_event, SND_SOC_DAPM_POST_PMU),
1352*4882a593Smuzhiyun 
1353*4882a593Smuzhiyun 	SND_SOC_DAPM_SUPPLY("micbias1 select", TWL4030_REG_MICBIAS_CTL, 5, 0,
1354*4882a593Smuzhiyun 			    NULL, 0),
1355*4882a593Smuzhiyun 	SND_SOC_DAPM_SUPPLY("micbias2 select", TWL4030_REG_MICBIAS_CTL, 6, 0,
1356*4882a593Smuzhiyun 			    NULL, 0),
1357*4882a593Smuzhiyun 
1358*4882a593Smuzhiyun 	/* Microphone bias */
1359*4882a593Smuzhiyun 	SND_SOC_DAPM_SUPPLY("Mic Bias 1",
1360*4882a593Smuzhiyun 			    TWL4030_REG_MICBIAS_CTL, 0, 0, NULL, 0),
1361*4882a593Smuzhiyun 	SND_SOC_DAPM_SUPPLY("Mic Bias 2",
1362*4882a593Smuzhiyun 			    TWL4030_REG_MICBIAS_CTL, 1, 0, NULL, 0),
1363*4882a593Smuzhiyun 	SND_SOC_DAPM_SUPPLY("Headset Mic Bias",
1364*4882a593Smuzhiyun 			    TWL4030_REG_MICBIAS_CTL, 2, 0, NULL, 0),
1365*4882a593Smuzhiyun 
1366*4882a593Smuzhiyun 	SND_SOC_DAPM_SUPPLY("VIF Enable", TWL4030_REG_VOICE_IF, 0, 0, NULL, 0),
1367*4882a593Smuzhiyun };
1368*4882a593Smuzhiyun 
1369*4882a593Smuzhiyun static const struct snd_soc_dapm_route intercon[] = {
1370*4882a593Smuzhiyun 	/* Stream -> DAC mapping */
1371*4882a593Smuzhiyun 	{"DAC Right1", NULL, "HiFi Playback"},
1372*4882a593Smuzhiyun 	{"DAC Left1", NULL, "HiFi Playback"},
1373*4882a593Smuzhiyun 	{"DAC Right2", NULL, "HiFi Playback"},
1374*4882a593Smuzhiyun 	{"DAC Left2", NULL, "HiFi Playback"},
1375*4882a593Smuzhiyun 	{"DAC Voice", NULL, "VAIFIN"},
1376*4882a593Smuzhiyun 
1377*4882a593Smuzhiyun 	/* ADC -> Stream mapping */
1378*4882a593Smuzhiyun 	{"HiFi Capture", NULL, "ADC Virtual Left1"},
1379*4882a593Smuzhiyun 	{"HiFi Capture", NULL, "ADC Virtual Right1"},
1380*4882a593Smuzhiyun 	{"HiFi Capture", NULL, "ADC Virtual Left2"},
1381*4882a593Smuzhiyun 	{"HiFi Capture", NULL, "ADC Virtual Right2"},
1382*4882a593Smuzhiyun 	{"VAIFOUT", NULL, "ADC Virtual Left2"},
1383*4882a593Smuzhiyun 	{"VAIFOUT", NULL, "ADC Virtual Right2"},
1384*4882a593Smuzhiyun 	{"VAIFOUT", NULL, "VIF Enable"},
1385*4882a593Smuzhiyun 
1386*4882a593Smuzhiyun 	{"Digital L1 Playback Mixer", NULL, "DAC Left1"},
1387*4882a593Smuzhiyun 	{"Digital R1 Playback Mixer", NULL, "DAC Right1"},
1388*4882a593Smuzhiyun 	{"Digital L2 Playback Mixer", NULL, "DAC Left2"},
1389*4882a593Smuzhiyun 	{"Digital R2 Playback Mixer", NULL, "DAC Right2"},
1390*4882a593Smuzhiyun 	{"Digital Voice Playback Mixer", NULL, "DAC Voice"},
1391*4882a593Smuzhiyun 
1392*4882a593Smuzhiyun 	/* Supply for the digital part (APLL) */
1393*4882a593Smuzhiyun 	{"Digital Voice Playback Mixer", NULL, "APLL Enable"},
1394*4882a593Smuzhiyun 
1395*4882a593Smuzhiyun 	{"DAC Left1", NULL, "AIF Enable"},
1396*4882a593Smuzhiyun 	{"DAC Right1", NULL, "AIF Enable"},
1397*4882a593Smuzhiyun 	{"DAC Left2", NULL, "AIF Enable"},
1398*4882a593Smuzhiyun 	{"DAC Right1", NULL, "AIF Enable"},
1399*4882a593Smuzhiyun 	{"DAC Voice", NULL, "VIF Enable"},
1400*4882a593Smuzhiyun 
1401*4882a593Smuzhiyun 	{"Digital R2 Playback Mixer", NULL, "AIF Enable"},
1402*4882a593Smuzhiyun 	{"Digital L2 Playback Mixer", NULL, "AIF Enable"},
1403*4882a593Smuzhiyun 
1404*4882a593Smuzhiyun 	{"Analog L1 Playback Mixer", NULL, "Digital L1 Playback Mixer"},
1405*4882a593Smuzhiyun 	{"Analog R1 Playback Mixer", NULL, "Digital R1 Playback Mixer"},
1406*4882a593Smuzhiyun 	{"Analog L2 Playback Mixer", NULL, "Digital L2 Playback Mixer"},
1407*4882a593Smuzhiyun 	{"Analog R2 Playback Mixer", NULL, "Digital R2 Playback Mixer"},
1408*4882a593Smuzhiyun 	{"Analog Voice Playback Mixer", NULL, "Digital Voice Playback Mixer"},
1409*4882a593Smuzhiyun 
1410*4882a593Smuzhiyun 	/* Internal playback routings */
1411*4882a593Smuzhiyun 	/* Earpiece */
1412*4882a593Smuzhiyun 	{"Earpiece Mixer", "Voice", "Analog Voice Playback Mixer"},
1413*4882a593Smuzhiyun 	{"Earpiece Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1414*4882a593Smuzhiyun 	{"Earpiece Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1415*4882a593Smuzhiyun 	{"Earpiece Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1416*4882a593Smuzhiyun 	{"Earpiece PGA", NULL, "Earpiece Mixer"},
1417*4882a593Smuzhiyun 	/* PreDrivL */
1418*4882a593Smuzhiyun 	{"PredriveL Mixer", "Voice", "Analog Voice Playback Mixer"},
1419*4882a593Smuzhiyun 	{"PredriveL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1420*4882a593Smuzhiyun 	{"PredriveL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1421*4882a593Smuzhiyun 	{"PredriveL Mixer", "AudioR2", "Analog R2 Playback Mixer"},
1422*4882a593Smuzhiyun 	{"PredriveL PGA", NULL, "PredriveL Mixer"},
1423*4882a593Smuzhiyun 	/* PreDrivR */
1424*4882a593Smuzhiyun 	{"PredriveR Mixer", "Voice", "Analog Voice Playback Mixer"},
1425*4882a593Smuzhiyun 	{"PredriveR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1426*4882a593Smuzhiyun 	{"PredriveR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
1427*4882a593Smuzhiyun 	{"PredriveR Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1428*4882a593Smuzhiyun 	{"PredriveR PGA", NULL, "PredriveR Mixer"},
1429*4882a593Smuzhiyun 	/* HeadsetL */
1430*4882a593Smuzhiyun 	{"HeadsetL Mixer", "Voice", "Analog Voice Playback Mixer"},
1431*4882a593Smuzhiyun 	{"HeadsetL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1432*4882a593Smuzhiyun 	{"HeadsetL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1433*4882a593Smuzhiyun 	{"HeadsetL PGA", NULL, "HeadsetL Mixer"},
1434*4882a593Smuzhiyun 	/* HeadsetR */
1435*4882a593Smuzhiyun 	{"HeadsetR Mixer", "Voice", "Analog Voice Playback Mixer"},
1436*4882a593Smuzhiyun 	{"HeadsetR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1437*4882a593Smuzhiyun 	{"HeadsetR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
1438*4882a593Smuzhiyun 	{"HeadsetR PGA", NULL, "HeadsetR Mixer"},
1439*4882a593Smuzhiyun 	/* CarkitL */
1440*4882a593Smuzhiyun 	{"CarkitL Mixer", "Voice", "Analog Voice Playback Mixer"},
1441*4882a593Smuzhiyun 	{"CarkitL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1442*4882a593Smuzhiyun 	{"CarkitL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1443*4882a593Smuzhiyun 	{"CarkitL PGA", NULL, "CarkitL Mixer"},
1444*4882a593Smuzhiyun 	/* CarkitR */
1445*4882a593Smuzhiyun 	{"CarkitR Mixer", "Voice", "Analog Voice Playback Mixer"},
1446*4882a593Smuzhiyun 	{"CarkitR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1447*4882a593Smuzhiyun 	{"CarkitR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
1448*4882a593Smuzhiyun 	{"CarkitR PGA", NULL, "CarkitR Mixer"},
1449*4882a593Smuzhiyun 	/* HandsfreeL */
1450*4882a593Smuzhiyun 	{"HandsfreeL Mux", "Voice", "Analog Voice Playback Mixer"},
1451*4882a593Smuzhiyun 	{"HandsfreeL Mux", "AudioL1", "Analog L1 Playback Mixer"},
1452*4882a593Smuzhiyun 	{"HandsfreeL Mux", "AudioL2", "Analog L2 Playback Mixer"},
1453*4882a593Smuzhiyun 	{"HandsfreeL Mux", "AudioR2", "Analog R2 Playback Mixer"},
1454*4882a593Smuzhiyun 	{"HandsfreeL", "Switch", "HandsfreeL Mux"},
1455*4882a593Smuzhiyun 	{"HandsfreeL PGA", NULL, "HandsfreeL"},
1456*4882a593Smuzhiyun 	/* HandsfreeR */
1457*4882a593Smuzhiyun 	{"HandsfreeR Mux", "Voice", "Analog Voice Playback Mixer"},
1458*4882a593Smuzhiyun 	{"HandsfreeR Mux", "AudioR1", "Analog R1 Playback Mixer"},
1459*4882a593Smuzhiyun 	{"HandsfreeR Mux", "AudioR2", "Analog R2 Playback Mixer"},
1460*4882a593Smuzhiyun 	{"HandsfreeR Mux", "AudioL2", "Analog L2 Playback Mixer"},
1461*4882a593Smuzhiyun 	{"HandsfreeR", "Switch", "HandsfreeR Mux"},
1462*4882a593Smuzhiyun 	{"HandsfreeR PGA", NULL, "HandsfreeR"},
1463*4882a593Smuzhiyun 	/* Vibra */
1464*4882a593Smuzhiyun 	{"Vibra Mux", "AudioL1", "DAC Left1"},
1465*4882a593Smuzhiyun 	{"Vibra Mux", "AudioR1", "DAC Right1"},
1466*4882a593Smuzhiyun 	{"Vibra Mux", "AudioL2", "DAC Left2"},
1467*4882a593Smuzhiyun 	{"Vibra Mux", "AudioR2", "DAC Right2"},
1468*4882a593Smuzhiyun 
1469*4882a593Smuzhiyun 	/* outputs */
1470*4882a593Smuzhiyun 	/* Must be always connected (for AIF and APLL) */
1471*4882a593Smuzhiyun 	{"Virtual HiFi OUT", NULL, "DAC Left1"},
1472*4882a593Smuzhiyun 	{"Virtual HiFi OUT", NULL, "DAC Right1"},
1473*4882a593Smuzhiyun 	{"Virtual HiFi OUT", NULL, "DAC Left2"},
1474*4882a593Smuzhiyun 	{"Virtual HiFi OUT", NULL, "DAC Right2"},
1475*4882a593Smuzhiyun 	/* Must be always connected (for APLL) */
1476*4882a593Smuzhiyun 	{"Virtual Voice OUT", NULL, "Digital Voice Playback Mixer"},
1477*4882a593Smuzhiyun 	/* Physical outputs */
1478*4882a593Smuzhiyun 	{"EARPIECE", NULL, "Earpiece PGA"},
1479*4882a593Smuzhiyun 	{"PREDRIVEL", NULL, "PredriveL PGA"},
1480*4882a593Smuzhiyun 	{"PREDRIVER", NULL, "PredriveR PGA"},
1481*4882a593Smuzhiyun 	{"HSOL", NULL, "HeadsetL PGA"},
1482*4882a593Smuzhiyun 	{"HSOR", NULL, "HeadsetR PGA"},
1483*4882a593Smuzhiyun 	{"CARKITL", NULL, "CarkitL PGA"},
1484*4882a593Smuzhiyun 	{"CARKITR", NULL, "CarkitR PGA"},
1485*4882a593Smuzhiyun 	{"HFL", NULL, "HandsfreeL PGA"},
1486*4882a593Smuzhiyun 	{"HFR", NULL, "HandsfreeR PGA"},
1487*4882a593Smuzhiyun 	{"Vibra Route", "Audio", "Vibra Mux"},
1488*4882a593Smuzhiyun 	{"VIBRA", NULL, "Vibra Route"},
1489*4882a593Smuzhiyun 
1490*4882a593Smuzhiyun 	/* Capture path */
1491*4882a593Smuzhiyun 	/* Must be always connected (for AIF and APLL) */
1492*4882a593Smuzhiyun 	{"ADC Virtual Left1", NULL, "Virtual HiFi IN"},
1493*4882a593Smuzhiyun 	{"ADC Virtual Right1", NULL, "Virtual HiFi IN"},
1494*4882a593Smuzhiyun 	{"ADC Virtual Left2", NULL, "Virtual HiFi IN"},
1495*4882a593Smuzhiyun 	{"ADC Virtual Right2", NULL, "Virtual HiFi IN"},
1496*4882a593Smuzhiyun 	/* Physical inputs */
1497*4882a593Smuzhiyun 	{"Analog Left", "Main Mic Capture Switch", "MAINMIC"},
1498*4882a593Smuzhiyun 	{"Analog Left", "Headset Mic Capture Switch", "HSMIC"},
1499*4882a593Smuzhiyun 	{"Analog Left", "AUXL Capture Switch", "AUXL"},
1500*4882a593Smuzhiyun 	{"Analog Left", "Carkit Mic Capture Switch", "CARKITMIC"},
1501*4882a593Smuzhiyun 
1502*4882a593Smuzhiyun 	{"Analog Right", "Sub Mic Capture Switch", "SUBMIC"},
1503*4882a593Smuzhiyun 	{"Analog Right", "AUXR Capture Switch", "AUXR"},
1504*4882a593Smuzhiyun 
1505*4882a593Smuzhiyun 	{"ADC Physical Left", NULL, "Analog Left"},
1506*4882a593Smuzhiyun 	{"ADC Physical Right", NULL, "Analog Right"},
1507*4882a593Smuzhiyun 
1508*4882a593Smuzhiyun 	{"Digimic0 Enable", NULL, "DIGIMIC0"},
1509*4882a593Smuzhiyun 	{"Digimic1 Enable", NULL, "DIGIMIC1"},
1510*4882a593Smuzhiyun 
1511*4882a593Smuzhiyun 	{"DIGIMIC0", NULL, "micbias1 select"},
1512*4882a593Smuzhiyun 	{"DIGIMIC1", NULL, "micbias2 select"},
1513*4882a593Smuzhiyun 
1514*4882a593Smuzhiyun 	/* TX1 Left capture path */
1515*4882a593Smuzhiyun 	{"TX1 Capture Route", "Analog", "ADC Physical Left"},
1516*4882a593Smuzhiyun 	{"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
1517*4882a593Smuzhiyun 	/* TX1 Right capture path */
1518*4882a593Smuzhiyun 	{"TX1 Capture Route", "Analog", "ADC Physical Right"},
1519*4882a593Smuzhiyun 	{"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
1520*4882a593Smuzhiyun 	/* TX2 Left capture path */
1521*4882a593Smuzhiyun 	{"TX2 Capture Route", "Analog", "ADC Physical Left"},
1522*4882a593Smuzhiyun 	{"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
1523*4882a593Smuzhiyun 	/* TX2 Right capture path */
1524*4882a593Smuzhiyun 	{"TX2 Capture Route", "Analog", "ADC Physical Right"},
1525*4882a593Smuzhiyun 	{"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
1526*4882a593Smuzhiyun 
1527*4882a593Smuzhiyun 	{"ADC Virtual Left1", NULL, "TX1 Capture Route"},
1528*4882a593Smuzhiyun 	{"ADC Virtual Right1", NULL, "TX1 Capture Route"},
1529*4882a593Smuzhiyun 	{"ADC Virtual Left2", NULL, "TX2 Capture Route"},
1530*4882a593Smuzhiyun 	{"ADC Virtual Right2", NULL, "TX2 Capture Route"},
1531*4882a593Smuzhiyun 
1532*4882a593Smuzhiyun 	{"ADC Virtual Left1", NULL, "AIF Enable"},
1533*4882a593Smuzhiyun 	{"ADC Virtual Right1", NULL, "AIF Enable"},
1534*4882a593Smuzhiyun 	{"ADC Virtual Left2", NULL, "AIF Enable"},
1535*4882a593Smuzhiyun 	{"ADC Virtual Right2", NULL, "AIF Enable"},
1536*4882a593Smuzhiyun 
1537*4882a593Smuzhiyun 	/* Analog bypass routes */
1538*4882a593Smuzhiyun 	{"Right1 Analog Loopback", "Switch", "Analog Right"},
1539*4882a593Smuzhiyun 	{"Left1 Analog Loopback", "Switch", "Analog Left"},
1540*4882a593Smuzhiyun 	{"Right2 Analog Loopback", "Switch", "Analog Right"},
1541*4882a593Smuzhiyun 	{"Left2 Analog Loopback", "Switch", "Analog Left"},
1542*4882a593Smuzhiyun 	{"Voice Analog Loopback", "Switch", "Analog Left"},
1543*4882a593Smuzhiyun 
1544*4882a593Smuzhiyun 	/* Supply for the Analog loopbacks */
1545*4882a593Smuzhiyun 	{"Right1 Analog Loopback", NULL, "FM Loop Enable"},
1546*4882a593Smuzhiyun 	{"Left1 Analog Loopback", NULL, "FM Loop Enable"},
1547*4882a593Smuzhiyun 	{"Right2 Analog Loopback", NULL, "FM Loop Enable"},
1548*4882a593Smuzhiyun 	{"Left2 Analog Loopback", NULL, "FM Loop Enable"},
1549*4882a593Smuzhiyun 	{"Voice Analog Loopback", NULL, "FM Loop Enable"},
1550*4882a593Smuzhiyun 
1551*4882a593Smuzhiyun 	{"Analog R1 Playback Mixer", NULL, "Right1 Analog Loopback"},
1552*4882a593Smuzhiyun 	{"Analog L1 Playback Mixer", NULL, "Left1 Analog Loopback"},
1553*4882a593Smuzhiyun 	{"Analog R2 Playback Mixer", NULL, "Right2 Analog Loopback"},
1554*4882a593Smuzhiyun 	{"Analog L2 Playback Mixer", NULL, "Left2 Analog Loopback"},
1555*4882a593Smuzhiyun 	{"Analog Voice Playback Mixer", NULL, "Voice Analog Loopback"},
1556*4882a593Smuzhiyun 
1557*4882a593Smuzhiyun 	/* Digital bypass routes */
1558*4882a593Smuzhiyun 	{"Right Digital Loopback", "Volume", "TX1 Capture Route"},
1559*4882a593Smuzhiyun 	{"Left Digital Loopback", "Volume", "TX1 Capture Route"},
1560*4882a593Smuzhiyun 	{"Voice Digital Loopback", "Volume", "TX2 Capture Route"},
1561*4882a593Smuzhiyun 
1562*4882a593Smuzhiyun 	{"Digital R2 Playback Mixer", NULL, "Right Digital Loopback"},
1563*4882a593Smuzhiyun 	{"Digital L2 Playback Mixer", NULL, "Left Digital Loopback"},
1564*4882a593Smuzhiyun 	{"Digital Voice Playback Mixer", NULL, "Voice Digital Loopback"},
1565*4882a593Smuzhiyun 
1566*4882a593Smuzhiyun };
1567*4882a593Smuzhiyun 
twl4030_set_bias_level(struct snd_soc_component * component,enum snd_soc_bias_level level)1568*4882a593Smuzhiyun static int twl4030_set_bias_level(struct snd_soc_component *component,
1569*4882a593Smuzhiyun 				  enum snd_soc_bias_level level)
1570*4882a593Smuzhiyun {
1571*4882a593Smuzhiyun 	switch (level) {
1572*4882a593Smuzhiyun 	case SND_SOC_BIAS_ON:
1573*4882a593Smuzhiyun 		break;
1574*4882a593Smuzhiyun 	case SND_SOC_BIAS_PREPARE:
1575*4882a593Smuzhiyun 		break;
1576*4882a593Smuzhiyun 	case SND_SOC_BIAS_STANDBY:
1577*4882a593Smuzhiyun 		if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF)
1578*4882a593Smuzhiyun 			twl4030_codec_enable(component, 1);
1579*4882a593Smuzhiyun 		break;
1580*4882a593Smuzhiyun 	case SND_SOC_BIAS_OFF:
1581*4882a593Smuzhiyun 		twl4030_codec_enable(component, 0);
1582*4882a593Smuzhiyun 		break;
1583*4882a593Smuzhiyun 	}
1584*4882a593Smuzhiyun 
1585*4882a593Smuzhiyun 	return 0;
1586*4882a593Smuzhiyun }
1587*4882a593Smuzhiyun 
twl4030_constraints(struct twl4030_priv * twl4030,struct snd_pcm_substream * mst_substream)1588*4882a593Smuzhiyun static void twl4030_constraints(struct twl4030_priv *twl4030,
1589*4882a593Smuzhiyun 				struct snd_pcm_substream *mst_substream)
1590*4882a593Smuzhiyun {
1591*4882a593Smuzhiyun 	struct snd_pcm_substream *slv_substream;
1592*4882a593Smuzhiyun 
1593*4882a593Smuzhiyun 	/* Pick the stream, which need to be constrained */
1594*4882a593Smuzhiyun 	if (mst_substream == twl4030->master_substream)
1595*4882a593Smuzhiyun 		slv_substream = twl4030->slave_substream;
1596*4882a593Smuzhiyun 	else if (mst_substream == twl4030->slave_substream)
1597*4882a593Smuzhiyun 		slv_substream = twl4030->master_substream;
1598*4882a593Smuzhiyun 	else /* This should not happen.. */
1599*4882a593Smuzhiyun 		return;
1600*4882a593Smuzhiyun 
1601*4882a593Smuzhiyun 	/* Set the constraints according to the already configured stream */
1602*4882a593Smuzhiyun 	snd_pcm_hw_constraint_single(slv_substream->runtime,
1603*4882a593Smuzhiyun 				SNDRV_PCM_HW_PARAM_RATE,
1604*4882a593Smuzhiyun 				twl4030->rate);
1605*4882a593Smuzhiyun 
1606*4882a593Smuzhiyun 	snd_pcm_hw_constraint_single(slv_substream->runtime,
1607*4882a593Smuzhiyun 				SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
1608*4882a593Smuzhiyun 				twl4030->sample_bits);
1609*4882a593Smuzhiyun 
1610*4882a593Smuzhiyun 	snd_pcm_hw_constraint_single(slv_substream->runtime,
1611*4882a593Smuzhiyun 				SNDRV_PCM_HW_PARAM_CHANNELS,
1612*4882a593Smuzhiyun 				twl4030->channels);
1613*4882a593Smuzhiyun }
1614*4882a593Smuzhiyun 
1615*4882a593Smuzhiyun /* In case of 4 channel mode, the RX1 L/R for playback and the TX2 L/R for
1616*4882a593Smuzhiyun  * capture has to be enabled/disabled. */
twl4030_tdm_enable(struct snd_soc_component * component,int direction,int enable)1617*4882a593Smuzhiyun static void twl4030_tdm_enable(struct snd_soc_component *component, int direction,
1618*4882a593Smuzhiyun 			       int enable)
1619*4882a593Smuzhiyun {
1620*4882a593Smuzhiyun 	u8 reg, mask;
1621*4882a593Smuzhiyun 
1622*4882a593Smuzhiyun 	reg = twl4030_read(component, TWL4030_REG_OPTION);
1623*4882a593Smuzhiyun 
1624*4882a593Smuzhiyun 	if (direction == SNDRV_PCM_STREAM_PLAYBACK)
1625*4882a593Smuzhiyun 		mask = TWL4030_ARXL1_VRX_EN | TWL4030_ARXR1_EN;
1626*4882a593Smuzhiyun 	else
1627*4882a593Smuzhiyun 		mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
1628*4882a593Smuzhiyun 
1629*4882a593Smuzhiyun 	if (enable)
1630*4882a593Smuzhiyun 		reg |= mask;
1631*4882a593Smuzhiyun 	else
1632*4882a593Smuzhiyun 		reg &= ~mask;
1633*4882a593Smuzhiyun 
1634*4882a593Smuzhiyun 	twl4030_write(component, TWL4030_REG_OPTION, reg);
1635*4882a593Smuzhiyun }
1636*4882a593Smuzhiyun 
twl4030_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)1637*4882a593Smuzhiyun static int twl4030_startup(struct snd_pcm_substream *substream,
1638*4882a593Smuzhiyun 			   struct snd_soc_dai *dai)
1639*4882a593Smuzhiyun {
1640*4882a593Smuzhiyun 	struct snd_soc_component *component = dai->component;
1641*4882a593Smuzhiyun 	struct twl4030_priv *twl4030 = snd_soc_component_get_drvdata(component);
1642*4882a593Smuzhiyun 
1643*4882a593Smuzhiyun 	if (twl4030->master_substream) {
1644*4882a593Smuzhiyun 		twl4030->slave_substream = substream;
1645*4882a593Smuzhiyun 		/* The DAI has one configuration for playback and capture, so
1646*4882a593Smuzhiyun 		 * if the DAI has been already configured then constrain this
1647*4882a593Smuzhiyun 		 * substream to match it. */
1648*4882a593Smuzhiyun 		if (twl4030->configured)
1649*4882a593Smuzhiyun 			twl4030_constraints(twl4030, twl4030->master_substream);
1650*4882a593Smuzhiyun 	} else {
1651*4882a593Smuzhiyun 		if (!(twl4030_read(component, TWL4030_REG_CODEC_MODE) &
1652*4882a593Smuzhiyun 			TWL4030_OPTION_1)) {
1653*4882a593Smuzhiyun 			/* In option2 4 channel is not supported, set the
1654*4882a593Smuzhiyun 			 * constraint for the first stream for channels, the
1655*4882a593Smuzhiyun 			 * second stream will 'inherit' this cosntraint */
1656*4882a593Smuzhiyun 			snd_pcm_hw_constraint_single(substream->runtime,
1657*4882a593Smuzhiyun 						     SNDRV_PCM_HW_PARAM_CHANNELS,
1658*4882a593Smuzhiyun 						     2);
1659*4882a593Smuzhiyun 		}
1660*4882a593Smuzhiyun 		twl4030->master_substream = substream;
1661*4882a593Smuzhiyun 	}
1662*4882a593Smuzhiyun 
1663*4882a593Smuzhiyun 	return 0;
1664*4882a593Smuzhiyun }
1665*4882a593Smuzhiyun 
twl4030_shutdown(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)1666*4882a593Smuzhiyun static void twl4030_shutdown(struct snd_pcm_substream *substream,
1667*4882a593Smuzhiyun 			     struct snd_soc_dai *dai)
1668*4882a593Smuzhiyun {
1669*4882a593Smuzhiyun 	struct snd_soc_component *component = dai->component;
1670*4882a593Smuzhiyun 	struct twl4030_priv *twl4030 = snd_soc_component_get_drvdata(component);
1671*4882a593Smuzhiyun 
1672*4882a593Smuzhiyun 	if (twl4030->master_substream == substream)
1673*4882a593Smuzhiyun 		twl4030->master_substream = twl4030->slave_substream;
1674*4882a593Smuzhiyun 
1675*4882a593Smuzhiyun 	twl4030->slave_substream = NULL;
1676*4882a593Smuzhiyun 
1677*4882a593Smuzhiyun 	/* If all streams are closed, or the remaining stream has not yet
1678*4882a593Smuzhiyun 	 * been configured than set the DAI as not configured. */
1679*4882a593Smuzhiyun 	if (!twl4030->master_substream)
1680*4882a593Smuzhiyun 		twl4030->configured = 0;
1681*4882a593Smuzhiyun 	 else if (!twl4030->master_substream->runtime->channels)
1682*4882a593Smuzhiyun 		twl4030->configured = 0;
1683*4882a593Smuzhiyun 
1684*4882a593Smuzhiyun 	 /* If the closing substream had 4 channel, do the necessary cleanup */
1685*4882a593Smuzhiyun 	if (substream->runtime->channels == 4)
1686*4882a593Smuzhiyun 		twl4030_tdm_enable(component, substream->stream, 0);
1687*4882a593Smuzhiyun }
1688*4882a593Smuzhiyun 
twl4030_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)1689*4882a593Smuzhiyun static int twl4030_hw_params(struct snd_pcm_substream *substream,
1690*4882a593Smuzhiyun 			     struct snd_pcm_hw_params *params,
1691*4882a593Smuzhiyun 			     struct snd_soc_dai *dai)
1692*4882a593Smuzhiyun {
1693*4882a593Smuzhiyun 	struct snd_soc_component *component = dai->component;
1694*4882a593Smuzhiyun 	struct twl4030_priv *twl4030 = snd_soc_component_get_drvdata(component);
1695*4882a593Smuzhiyun 	u8 mode, old_mode, format, old_format;
1696*4882a593Smuzhiyun 
1697*4882a593Smuzhiyun 	 /* If the substream has 4 channel, do the necessary setup */
1698*4882a593Smuzhiyun 	if (params_channels(params) == 4) {
1699*4882a593Smuzhiyun 		format = twl4030_read(component, TWL4030_REG_AUDIO_IF);
1700*4882a593Smuzhiyun 		mode = twl4030_read(component, TWL4030_REG_CODEC_MODE);
1701*4882a593Smuzhiyun 
1702*4882a593Smuzhiyun 		/* Safety check: are we in the correct operating mode and
1703*4882a593Smuzhiyun 		 * the interface is in TDM mode? */
1704*4882a593Smuzhiyun 		if ((mode & TWL4030_OPTION_1) &&
1705*4882a593Smuzhiyun 		    ((format & TWL4030_AIF_FORMAT) == TWL4030_AIF_FORMAT_TDM))
1706*4882a593Smuzhiyun 			twl4030_tdm_enable(component, substream->stream, 1);
1707*4882a593Smuzhiyun 		else
1708*4882a593Smuzhiyun 			return -EINVAL;
1709*4882a593Smuzhiyun 	}
1710*4882a593Smuzhiyun 
1711*4882a593Smuzhiyun 	if (twl4030->configured)
1712*4882a593Smuzhiyun 		/* Ignoring hw_params for already configured DAI */
1713*4882a593Smuzhiyun 		return 0;
1714*4882a593Smuzhiyun 
1715*4882a593Smuzhiyun 	/* bit rate */
1716*4882a593Smuzhiyun 	old_mode = twl4030_read(component,
1717*4882a593Smuzhiyun 				TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ;
1718*4882a593Smuzhiyun 	mode = old_mode & ~TWL4030_APLL_RATE;
1719*4882a593Smuzhiyun 
1720*4882a593Smuzhiyun 	switch (params_rate(params)) {
1721*4882a593Smuzhiyun 	case 8000:
1722*4882a593Smuzhiyun 		mode |= TWL4030_APLL_RATE_8000;
1723*4882a593Smuzhiyun 		break;
1724*4882a593Smuzhiyun 	case 11025:
1725*4882a593Smuzhiyun 		mode |= TWL4030_APLL_RATE_11025;
1726*4882a593Smuzhiyun 		break;
1727*4882a593Smuzhiyun 	case 12000:
1728*4882a593Smuzhiyun 		mode |= TWL4030_APLL_RATE_12000;
1729*4882a593Smuzhiyun 		break;
1730*4882a593Smuzhiyun 	case 16000:
1731*4882a593Smuzhiyun 		mode |= TWL4030_APLL_RATE_16000;
1732*4882a593Smuzhiyun 		break;
1733*4882a593Smuzhiyun 	case 22050:
1734*4882a593Smuzhiyun 		mode |= TWL4030_APLL_RATE_22050;
1735*4882a593Smuzhiyun 		break;
1736*4882a593Smuzhiyun 	case 24000:
1737*4882a593Smuzhiyun 		mode |= TWL4030_APLL_RATE_24000;
1738*4882a593Smuzhiyun 		break;
1739*4882a593Smuzhiyun 	case 32000:
1740*4882a593Smuzhiyun 		mode |= TWL4030_APLL_RATE_32000;
1741*4882a593Smuzhiyun 		break;
1742*4882a593Smuzhiyun 	case 44100:
1743*4882a593Smuzhiyun 		mode |= TWL4030_APLL_RATE_44100;
1744*4882a593Smuzhiyun 		break;
1745*4882a593Smuzhiyun 	case 48000:
1746*4882a593Smuzhiyun 		mode |= TWL4030_APLL_RATE_48000;
1747*4882a593Smuzhiyun 		break;
1748*4882a593Smuzhiyun 	case 96000:
1749*4882a593Smuzhiyun 		mode |= TWL4030_APLL_RATE_96000;
1750*4882a593Smuzhiyun 		break;
1751*4882a593Smuzhiyun 	default:
1752*4882a593Smuzhiyun 		dev_err(component->dev, "%s: unknown rate %d\n", __func__,
1753*4882a593Smuzhiyun 			params_rate(params));
1754*4882a593Smuzhiyun 		return -EINVAL;
1755*4882a593Smuzhiyun 	}
1756*4882a593Smuzhiyun 
1757*4882a593Smuzhiyun 	/* sample size */
1758*4882a593Smuzhiyun 	old_format = twl4030_read(component, TWL4030_REG_AUDIO_IF);
1759*4882a593Smuzhiyun 	format = old_format;
1760*4882a593Smuzhiyun 	format &= ~TWL4030_DATA_WIDTH;
1761*4882a593Smuzhiyun 	switch (params_width(params)) {
1762*4882a593Smuzhiyun 	case 16:
1763*4882a593Smuzhiyun 		format |= TWL4030_DATA_WIDTH_16S_16W;
1764*4882a593Smuzhiyun 		break;
1765*4882a593Smuzhiyun 	case 32:
1766*4882a593Smuzhiyun 		format |= TWL4030_DATA_WIDTH_32S_24W;
1767*4882a593Smuzhiyun 		break;
1768*4882a593Smuzhiyun 	default:
1769*4882a593Smuzhiyun 		dev_err(component->dev, "%s: unsupported bits/sample %d\n",
1770*4882a593Smuzhiyun 			__func__, params_width(params));
1771*4882a593Smuzhiyun 		return -EINVAL;
1772*4882a593Smuzhiyun 	}
1773*4882a593Smuzhiyun 
1774*4882a593Smuzhiyun 	if (format != old_format || mode != old_mode) {
1775*4882a593Smuzhiyun 		if (twl4030->codec_powered) {
1776*4882a593Smuzhiyun 			/*
1777*4882a593Smuzhiyun 			 * If the codec is powered, than we need to toggle the
1778*4882a593Smuzhiyun 			 * codec power.
1779*4882a593Smuzhiyun 			 */
1780*4882a593Smuzhiyun 			twl4030_codec_enable(component, 0);
1781*4882a593Smuzhiyun 			twl4030_write(component, TWL4030_REG_CODEC_MODE, mode);
1782*4882a593Smuzhiyun 			twl4030_write(component, TWL4030_REG_AUDIO_IF, format);
1783*4882a593Smuzhiyun 			twl4030_codec_enable(component, 1);
1784*4882a593Smuzhiyun 		} else {
1785*4882a593Smuzhiyun 			twl4030_write(component, TWL4030_REG_CODEC_MODE, mode);
1786*4882a593Smuzhiyun 			twl4030_write(component, TWL4030_REG_AUDIO_IF, format);
1787*4882a593Smuzhiyun 		}
1788*4882a593Smuzhiyun 	}
1789*4882a593Smuzhiyun 
1790*4882a593Smuzhiyun 	/* Store the important parameters for the DAI configuration and set
1791*4882a593Smuzhiyun 	 * the DAI as configured */
1792*4882a593Smuzhiyun 	twl4030->configured = 1;
1793*4882a593Smuzhiyun 	twl4030->rate = params_rate(params);
1794*4882a593Smuzhiyun 	twl4030->sample_bits = hw_param_interval(params,
1795*4882a593Smuzhiyun 					SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min;
1796*4882a593Smuzhiyun 	twl4030->channels = params_channels(params);
1797*4882a593Smuzhiyun 
1798*4882a593Smuzhiyun 	/* If both playback and capture streams are open, and one of them
1799*4882a593Smuzhiyun 	 * is setting the hw parameters right now (since we are here), set
1800*4882a593Smuzhiyun 	 * constraints to the other stream to match the current one. */
1801*4882a593Smuzhiyun 	if (twl4030->slave_substream)
1802*4882a593Smuzhiyun 		twl4030_constraints(twl4030, substream);
1803*4882a593Smuzhiyun 
1804*4882a593Smuzhiyun 	return 0;
1805*4882a593Smuzhiyun }
1806*4882a593Smuzhiyun 
twl4030_set_dai_sysclk(struct snd_soc_dai * codec_dai,int clk_id,unsigned int freq,int dir)1807*4882a593Smuzhiyun static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai, int clk_id,
1808*4882a593Smuzhiyun 				  unsigned int freq, int dir)
1809*4882a593Smuzhiyun {
1810*4882a593Smuzhiyun 	struct snd_soc_component *component = codec_dai->component;
1811*4882a593Smuzhiyun 	struct twl4030_priv *twl4030 = snd_soc_component_get_drvdata(component);
1812*4882a593Smuzhiyun 
1813*4882a593Smuzhiyun 	switch (freq) {
1814*4882a593Smuzhiyun 	case 19200000:
1815*4882a593Smuzhiyun 	case 26000000:
1816*4882a593Smuzhiyun 	case 38400000:
1817*4882a593Smuzhiyun 		break;
1818*4882a593Smuzhiyun 	default:
1819*4882a593Smuzhiyun 		dev_err(component->dev, "Unsupported HFCLKIN: %u\n", freq);
1820*4882a593Smuzhiyun 		return -EINVAL;
1821*4882a593Smuzhiyun 	}
1822*4882a593Smuzhiyun 
1823*4882a593Smuzhiyun 	if ((freq / 1000) != twl4030->sysclk) {
1824*4882a593Smuzhiyun 		dev_err(component->dev,
1825*4882a593Smuzhiyun 			"Mismatch in HFCLKIN: %u (configured: %u)\n",
1826*4882a593Smuzhiyun 			freq, twl4030->sysclk * 1000);
1827*4882a593Smuzhiyun 		return -EINVAL;
1828*4882a593Smuzhiyun 	}
1829*4882a593Smuzhiyun 
1830*4882a593Smuzhiyun 	return 0;
1831*4882a593Smuzhiyun }
1832*4882a593Smuzhiyun 
twl4030_set_dai_fmt(struct snd_soc_dai * codec_dai,unsigned int fmt)1833*4882a593Smuzhiyun static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
1834*4882a593Smuzhiyun {
1835*4882a593Smuzhiyun 	struct snd_soc_component *component = codec_dai->component;
1836*4882a593Smuzhiyun 	struct twl4030_priv *twl4030 = snd_soc_component_get_drvdata(component);
1837*4882a593Smuzhiyun 	u8 old_format, format;
1838*4882a593Smuzhiyun 
1839*4882a593Smuzhiyun 	/* get format */
1840*4882a593Smuzhiyun 	old_format = twl4030_read(component, TWL4030_REG_AUDIO_IF);
1841*4882a593Smuzhiyun 	format = old_format;
1842*4882a593Smuzhiyun 
1843*4882a593Smuzhiyun 	/* set master/slave audio interface */
1844*4882a593Smuzhiyun 	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1845*4882a593Smuzhiyun 	case SND_SOC_DAIFMT_CBM_CFM:
1846*4882a593Smuzhiyun 		format &= ~(TWL4030_AIF_SLAVE_EN);
1847*4882a593Smuzhiyun 		format &= ~(TWL4030_CLK256FS_EN);
1848*4882a593Smuzhiyun 		break;
1849*4882a593Smuzhiyun 	case SND_SOC_DAIFMT_CBS_CFS:
1850*4882a593Smuzhiyun 		format |= TWL4030_AIF_SLAVE_EN;
1851*4882a593Smuzhiyun 		format |= TWL4030_CLK256FS_EN;
1852*4882a593Smuzhiyun 		break;
1853*4882a593Smuzhiyun 	default:
1854*4882a593Smuzhiyun 		return -EINVAL;
1855*4882a593Smuzhiyun 	}
1856*4882a593Smuzhiyun 
1857*4882a593Smuzhiyun 	/* interface format */
1858*4882a593Smuzhiyun 	format &= ~TWL4030_AIF_FORMAT;
1859*4882a593Smuzhiyun 	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1860*4882a593Smuzhiyun 	case SND_SOC_DAIFMT_I2S:
1861*4882a593Smuzhiyun 		format |= TWL4030_AIF_FORMAT_CODEC;
1862*4882a593Smuzhiyun 		break;
1863*4882a593Smuzhiyun 	case SND_SOC_DAIFMT_DSP_A:
1864*4882a593Smuzhiyun 		format |= TWL4030_AIF_FORMAT_TDM;
1865*4882a593Smuzhiyun 		break;
1866*4882a593Smuzhiyun 	default:
1867*4882a593Smuzhiyun 		return -EINVAL;
1868*4882a593Smuzhiyun 	}
1869*4882a593Smuzhiyun 
1870*4882a593Smuzhiyun 	if (format != old_format) {
1871*4882a593Smuzhiyun 		if (twl4030->codec_powered) {
1872*4882a593Smuzhiyun 			/*
1873*4882a593Smuzhiyun 			 * If the codec is powered, than we need to toggle the
1874*4882a593Smuzhiyun 			 * codec power.
1875*4882a593Smuzhiyun 			 */
1876*4882a593Smuzhiyun 			twl4030_codec_enable(component, 0);
1877*4882a593Smuzhiyun 			twl4030_write(component, TWL4030_REG_AUDIO_IF, format);
1878*4882a593Smuzhiyun 			twl4030_codec_enable(component, 1);
1879*4882a593Smuzhiyun 		} else {
1880*4882a593Smuzhiyun 			twl4030_write(component, TWL4030_REG_AUDIO_IF, format);
1881*4882a593Smuzhiyun 		}
1882*4882a593Smuzhiyun 	}
1883*4882a593Smuzhiyun 
1884*4882a593Smuzhiyun 	return 0;
1885*4882a593Smuzhiyun }
1886*4882a593Smuzhiyun 
twl4030_set_tristate(struct snd_soc_dai * dai,int tristate)1887*4882a593Smuzhiyun static int twl4030_set_tristate(struct snd_soc_dai *dai, int tristate)
1888*4882a593Smuzhiyun {
1889*4882a593Smuzhiyun 	struct snd_soc_component *component = dai->component;
1890*4882a593Smuzhiyun 	u8 reg = twl4030_read(component, TWL4030_REG_AUDIO_IF);
1891*4882a593Smuzhiyun 
1892*4882a593Smuzhiyun 	if (tristate)
1893*4882a593Smuzhiyun 		reg |= TWL4030_AIF_TRI_EN;
1894*4882a593Smuzhiyun 	else
1895*4882a593Smuzhiyun 		reg &= ~TWL4030_AIF_TRI_EN;
1896*4882a593Smuzhiyun 
1897*4882a593Smuzhiyun 	return twl4030_write(component, TWL4030_REG_AUDIO_IF, reg);
1898*4882a593Smuzhiyun }
1899*4882a593Smuzhiyun 
1900*4882a593Smuzhiyun /* In case of voice mode, the RX1 L(VRX) for downlink and the TX2 L/R
1901*4882a593Smuzhiyun  * (VTXL, VTXR) for uplink has to be enabled/disabled. */
twl4030_voice_enable(struct snd_soc_component * component,int direction,int enable)1902*4882a593Smuzhiyun static void twl4030_voice_enable(struct snd_soc_component *component, int direction,
1903*4882a593Smuzhiyun 				 int enable)
1904*4882a593Smuzhiyun {
1905*4882a593Smuzhiyun 	u8 reg, mask;
1906*4882a593Smuzhiyun 
1907*4882a593Smuzhiyun 	reg = twl4030_read(component, TWL4030_REG_OPTION);
1908*4882a593Smuzhiyun 
1909*4882a593Smuzhiyun 	if (direction == SNDRV_PCM_STREAM_PLAYBACK)
1910*4882a593Smuzhiyun 		mask = TWL4030_ARXL1_VRX_EN;
1911*4882a593Smuzhiyun 	else
1912*4882a593Smuzhiyun 		mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
1913*4882a593Smuzhiyun 
1914*4882a593Smuzhiyun 	if (enable)
1915*4882a593Smuzhiyun 		reg |= mask;
1916*4882a593Smuzhiyun 	else
1917*4882a593Smuzhiyun 		reg &= ~mask;
1918*4882a593Smuzhiyun 
1919*4882a593Smuzhiyun 	twl4030_write(component, TWL4030_REG_OPTION, reg);
1920*4882a593Smuzhiyun }
1921*4882a593Smuzhiyun 
twl4030_voice_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)1922*4882a593Smuzhiyun static int twl4030_voice_startup(struct snd_pcm_substream *substream,
1923*4882a593Smuzhiyun 				 struct snd_soc_dai *dai)
1924*4882a593Smuzhiyun {
1925*4882a593Smuzhiyun 	struct snd_soc_component *component = dai->component;
1926*4882a593Smuzhiyun 	struct twl4030_priv *twl4030 = snd_soc_component_get_drvdata(component);
1927*4882a593Smuzhiyun 	u8 mode;
1928*4882a593Smuzhiyun 
1929*4882a593Smuzhiyun 	/* If the system master clock is not 26MHz, the voice PCM interface is
1930*4882a593Smuzhiyun 	 * not available.
1931*4882a593Smuzhiyun 	 */
1932*4882a593Smuzhiyun 	if (twl4030->sysclk != 26000) {
1933*4882a593Smuzhiyun 		dev_err(component->dev,
1934*4882a593Smuzhiyun 			"%s: HFCLKIN is %u KHz, voice interface needs 26MHz\n",
1935*4882a593Smuzhiyun 			__func__, twl4030->sysclk);
1936*4882a593Smuzhiyun 		return -EINVAL;
1937*4882a593Smuzhiyun 	}
1938*4882a593Smuzhiyun 
1939*4882a593Smuzhiyun 	/* If the codec mode is not option2, the voice PCM interface is not
1940*4882a593Smuzhiyun 	 * available.
1941*4882a593Smuzhiyun 	 */
1942*4882a593Smuzhiyun 	mode = twl4030_read(component, TWL4030_REG_CODEC_MODE)
1943*4882a593Smuzhiyun 		& TWL4030_OPT_MODE;
1944*4882a593Smuzhiyun 
1945*4882a593Smuzhiyun 	if (mode != TWL4030_OPTION_2) {
1946*4882a593Smuzhiyun 		dev_err(component->dev, "%s: the codec mode is not option2\n",
1947*4882a593Smuzhiyun 			__func__);
1948*4882a593Smuzhiyun 		return -EINVAL;
1949*4882a593Smuzhiyun 	}
1950*4882a593Smuzhiyun 
1951*4882a593Smuzhiyun 	return 0;
1952*4882a593Smuzhiyun }
1953*4882a593Smuzhiyun 
twl4030_voice_shutdown(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)1954*4882a593Smuzhiyun static void twl4030_voice_shutdown(struct snd_pcm_substream *substream,
1955*4882a593Smuzhiyun 				   struct snd_soc_dai *dai)
1956*4882a593Smuzhiyun {
1957*4882a593Smuzhiyun 	struct snd_soc_component *component = dai->component;
1958*4882a593Smuzhiyun 
1959*4882a593Smuzhiyun 	/* Enable voice digital filters */
1960*4882a593Smuzhiyun 	twl4030_voice_enable(component, substream->stream, 0);
1961*4882a593Smuzhiyun }
1962*4882a593Smuzhiyun 
twl4030_voice_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)1963*4882a593Smuzhiyun static int twl4030_voice_hw_params(struct snd_pcm_substream *substream,
1964*4882a593Smuzhiyun 				   struct snd_pcm_hw_params *params,
1965*4882a593Smuzhiyun 				   struct snd_soc_dai *dai)
1966*4882a593Smuzhiyun {
1967*4882a593Smuzhiyun 	struct snd_soc_component *component = dai->component;
1968*4882a593Smuzhiyun 	struct twl4030_priv *twl4030 = snd_soc_component_get_drvdata(component);
1969*4882a593Smuzhiyun 	u8 old_mode, mode;
1970*4882a593Smuzhiyun 
1971*4882a593Smuzhiyun 	/* Enable voice digital filters */
1972*4882a593Smuzhiyun 	twl4030_voice_enable(component, substream->stream, 1);
1973*4882a593Smuzhiyun 
1974*4882a593Smuzhiyun 	/* bit rate */
1975*4882a593Smuzhiyun 	old_mode = twl4030_read(component,
1976*4882a593Smuzhiyun 				TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ;
1977*4882a593Smuzhiyun 	mode = old_mode;
1978*4882a593Smuzhiyun 
1979*4882a593Smuzhiyun 	switch (params_rate(params)) {
1980*4882a593Smuzhiyun 	case 8000:
1981*4882a593Smuzhiyun 		mode &= ~(TWL4030_SEL_16K);
1982*4882a593Smuzhiyun 		break;
1983*4882a593Smuzhiyun 	case 16000:
1984*4882a593Smuzhiyun 		mode |= TWL4030_SEL_16K;
1985*4882a593Smuzhiyun 		break;
1986*4882a593Smuzhiyun 	default:
1987*4882a593Smuzhiyun 		dev_err(component->dev, "%s: unknown rate %d\n", __func__,
1988*4882a593Smuzhiyun 			params_rate(params));
1989*4882a593Smuzhiyun 		return -EINVAL;
1990*4882a593Smuzhiyun 	}
1991*4882a593Smuzhiyun 
1992*4882a593Smuzhiyun 	if (mode != old_mode) {
1993*4882a593Smuzhiyun 		if (twl4030->codec_powered) {
1994*4882a593Smuzhiyun 			/*
1995*4882a593Smuzhiyun 			 * If the codec is powered, than we need to toggle the
1996*4882a593Smuzhiyun 			 * codec power.
1997*4882a593Smuzhiyun 			 */
1998*4882a593Smuzhiyun 			twl4030_codec_enable(component, 0);
1999*4882a593Smuzhiyun 			twl4030_write(component, TWL4030_REG_CODEC_MODE, mode);
2000*4882a593Smuzhiyun 			twl4030_codec_enable(component, 1);
2001*4882a593Smuzhiyun 		} else {
2002*4882a593Smuzhiyun 			twl4030_write(component, TWL4030_REG_CODEC_MODE, mode);
2003*4882a593Smuzhiyun 		}
2004*4882a593Smuzhiyun 	}
2005*4882a593Smuzhiyun 
2006*4882a593Smuzhiyun 	return 0;
2007*4882a593Smuzhiyun }
2008*4882a593Smuzhiyun 
twl4030_voice_set_dai_sysclk(struct snd_soc_dai * codec_dai,int clk_id,unsigned int freq,int dir)2009*4882a593Smuzhiyun static int twl4030_voice_set_dai_sysclk(struct snd_soc_dai *codec_dai,
2010*4882a593Smuzhiyun 					int clk_id, unsigned int freq, int dir)
2011*4882a593Smuzhiyun {
2012*4882a593Smuzhiyun 	struct snd_soc_component *component = codec_dai->component;
2013*4882a593Smuzhiyun 	struct twl4030_priv *twl4030 = snd_soc_component_get_drvdata(component);
2014*4882a593Smuzhiyun 
2015*4882a593Smuzhiyun 	if (freq != 26000000) {
2016*4882a593Smuzhiyun 		dev_err(component->dev,
2017*4882a593Smuzhiyun 			"%s: HFCLKIN is %u KHz, voice interface needs 26MHz\n",
2018*4882a593Smuzhiyun 			__func__, freq / 1000);
2019*4882a593Smuzhiyun 		return -EINVAL;
2020*4882a593Smuzhiyun 	}
2021*4882a593Smuzhiyun 	if ((freq / 1000) != twl4030->sysclk) {
2022*4882a593Smuzhiyun 		dev_err(component->dev,
2023*4882a593Smuzhiyun 			"Mismatch in HFCLKIN: %u (configured: %u)\n",
2024*4882a593Smuzhiyun 			freq, twl4030->sysclk * 1000);
2025*4882a593Smuzhiyun 		return -EINVAL;
2026*4882a593Smuzhiyun 	}
2027*4882a593Smuzhiyun 	return 0;
2028*4882a593Smuzhiyun }
2029*4882a593Smuzhiyun 
twl4030_voice_set_dai_fmt(struct snd_soc_dai * codec_dai,unsigned int fmt)2030*4882a593Smuzhiyun static int twl4030_voice_set_dai_fmt(struct snd_soc_dai *codec_dai,
2031*4882a593Smuzhiyun 				     unsigned int fmt)
2032*4882a593Smuzhiyun {
2033*4882a593Smuzhiyun 	struct snd_soc_component *component = codec_dai->component;
2034*4882a593Smuzhiyun 	struct twl4030_priv *twl4030 = snd_soc_component_get_drvdata(component);
2035*4882a593Smuzhiyun 	u8 old_format, format;
2036*4882a593Smuzhiyun 
2037*4882a593Smuzhiyun 	/* get format */
2038*4882a593Smuzhiyun 	old_format = twl4030_read(component, TWL4030_REG_VOICE_IF);
2039*4882a593Smuzhiyun 	format = old_format;
2040*4882a593Smuzhiyun 
2041*4882a593Smuzhiyun 	/* set master/slave audio interface */
2042*4882a593Smuzhiyun 	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2043*4882a593Smuzhiyun 	case SND_SOC_DAIFMT_CBM_CFM:
2044*4882a593Smuzhiyun 		format &= ~(TWL4030_VIF_SLAVE_EN);
2045*4882a593Smuzhiyun 		break;
2046*4882a593Smuzhiyun 	case SND_SOC_DAIFMT_CBS_CFS:
2047*4882a593Smuzhiyun 		format |= TWL4030_VIF_SLAVE_EN;
2048*4882a593Smuzhiyun 		break;
2049*4882a593Smuzhiyun 	default:
2050*4882a593Smuzhiyun 		return -EINVAL;
2051*4882a593Smuzhiyun 	}
2052*4882a593Smuzhiyun 
2053*4882a593Smuzhiyun 	/* clock inversion */
2054*4882a593Smuzhiyun 	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2055*4882a593Smuzhiyun 	case SND_SOC_DAIFMT_IB_NF:
2056*4882a593Smuzhiyun 		format &= ~(TWL4030_VIF_FORMAT);
2057*4882a593Smuzhiyun 		break;
2058*4882a593Smuzhiyun 	case SND_SOC_DAIFMT_NB_IF:
2059*4882a593Smuzhiyun 		format |= TWL4030_VIF_FORMAT;
2060*4882a593Smuzhiyun 		break;
2061*4882a593Smuzhiyun 	default:
2062*4882a593Smuzhiyun 		return -EINVAL;
2063*4882a593Smuzhiyun 	}
2064*4882a593Smuzhiyun 
2065*4882a593Smuzhiyun 	if (format != old_format) {
2066*4882a593Smuzhiyun 		if (twl4030->codec_powered) {
2067*4882a593Smuzhiyun 			/*
2068*4882a593Smuzhiyun 			 * If the codec is powered, than we need to toggle the
2069*4882a593Smuzhiyun 			 * codec power.
2070*4882a593Smuzhiyun 			 */
2071*4882a593Smuzhiyun 			twl4030_codec_enable(component, 0);
2072*4882a593Smuzhiyun 			twl4030_write(component, TWL4030_REG_VOICE_IF, format);
2073*4882a593Smuzhiyun 			twl4030_codec_enable(component, 1);
2074*4882a593Smuzhiyun 		} else {
2075*4882a593Smuzhiyun 			twl4030_write(component, TWL4030_REG_VOICE_IF, format);
2076*4882a593Smuzhiyun 		}
2077*4882a593Smuzhiyun 	}
2078*4882a593Smuzhiyun 
2079*4882a593Smuzhiyun 	return 0;
2080*4882a593Smuzhiyun }
2081*4882a593Smuzhiyun 
twl4030_voice_set_tristate(struct snd_soc_dai * dai,int tristate)2082*4882a593Smuzhiyun static int twl4030_voice_set_tristate(struct snd_soc_dai *dai, int tristate)
2083*4882a593Smuzhiyun {
2084*4882a593Smuzhiyun 	struct snd_soc_component *component = dai->component;
2085*4882a593Smuzhiyun 	u8 reg = twl4030_read(component, TWL4030_REG_VOICE_IF);
2086*4882a593Smuzhiyun 
2087*4882a593Smuzhiyun 	if (tristate)
2088*4882a593Smuzhiyun 		reg |= TWL4030_VIF_TRI_EN;
2089*4882a593Smuzhiyun 	else
2090*4882a593Smuzhiyun 		reg &= ~TWL4030_VIF_TRI_EN;
2091*4882a593Smuzhiyun 
2092*4882a593Smuzhiyun 	return twl4030_write(component, TWL4030_REG_VOICE_IF, reg);
2093*4882a593Smuzhiyun }
2094*4882a593Smuzhiyun 
2095*4882a593Smuzhiyun #define TWL4030_RATES	 (SNDRV_PCM_RATE_8000_48000)
2096*4882a593Smuzhiyun #define TWL4030_FORMATS	 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
2097*4882a593Smuzhiyun 
2098*4882a593Smuzhiyun static const struct snd_soc_dai_ops twl4030_dai_hifi_ops = {
2099*4882a593Smuzhiyun 	.startup	= twl4030_startup,
2100*4882a593Smuzhiyun 	.shutdown	= twl4030_shutdown,
2101*4882a593Smuzhiyun 	.hw_params	= twl4030_hw_params,
2102*4882a593Smuzhiyun 	.set_sysclk	= twl4030_set_dai_sysclk,
2103*4882a593Smuzhiyun 	.set_fmt	= twl4030_set_dai_fmt,
2104*4882a593Smuzhiyun 	.set_tristate	= twl4030_set_tristate,
2105*4882a593Smuzhiyun };
2106*4882a593Smuzhiyun 
2107*4882a593Smuzhiyun static const struct snd_soc_dai_ops twl4030_dai_voice_ops = {
2108*4882a593Smuzhiyun 	.startup	= twl4030_voice_startup,
2109*4882a593Smuzhiyun 	.shutdown	= twl4030_voice_shutdown,
2110*4882a593Smuzhiyun 	.hw_params	= twl4030_voice_hw_params,
2111*4882a593Smuzhiyun 	.set_sysclk	= twl4030_voice_set_dai_sysclk,
2112*4882a593Smuzhiyun 	.set_fmt	= twl4030_voice_set_dai_fmt,
2113*4882a593Smuzhiyun 	.set_tristate	= twl4030_voice_set_tristate,
2114*4882a593Smuzhiyun };
2115*4882a593Smuzhiyun 
2116*4882a593Smuzhiyun static struct snd_soc_dai_driver twl4030_dai[] = {
2117*4882a593Smuzhiyun {
2118*4882a593Smuzhiyun 	.name = "twl4030-hifi",
2119*4882a593Smuzhiyun 	.playback = {
2120*4882a593Smuzhiyun 		.stream_name = "HiFi Playback",
2121*4882a593Smuzhiyun 		.channels_min = 2,
2122*4882a593Smuzhiyun 		.channels_max = 4,
2123*4882a593Smuzhiyun 		.rates = TWL4030_RATES | SNDRV_PCM_RATE_96000,
2124*4882a593Smuzhiyun 		.formats = TWL4030_FORMATS,
2125*4882a593Smuzhiyun 		.sig_bits = 24,},
2126*4882a593Smuzhiyun 	.capture = {
2127*4882a593Smuzhiyun 		.stream_name = "HiFi Capture",
2128*4882a593Smuzhiyun 		.channels_min = 2,
2129*4882a593Smuzhiyun 		.channels_max = 4,
2130*4882a593Smuzhiyun 		.rates = TWL4030_RATES,
2131*4882a593Smuzhiyun 		.formats = TWL4030_FORMATS,
2132*4882a593Smuzhiyun 		.sig_bits = 24,},
2133*4882a593Smuzhiyun 	.ops = &twl4030_dai_hifi_ops,
2134*4882a593Smuzhiyun },
2135*4882a593Smuzhiyun {
2136*4882a593Smuzhiyun 	.name = "twl4030-voice",
2137*4882a593Smuzhiyun 	.playback = {
2138*4882a593Smuzhiyun 		.stream_name = "Voice Playback",
2139*4882a593Smuzhiyun 		.channels_min = 1,
2140*4882a593Smuzhiyun 		.channels_max = 1,
2141*4882a593Smuzhiyun 		.rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
2142*4882a593Smuzhiyun 		.formats = SNDRV_PCM_FMTBIT_S16_LE,},
2143*4882a593Smuzhiyun 	.capture = {
2144*4882a593Smuzhiyun 		.stream_name = "Voice Capture",
2145*4882a593Smuzhiyun 		.channels_min = 1,
2146*4882a593Smuzhiyun 		.channels_max = 2,
2147*4882a593Smuzhiyun 		.rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
2148*4882a593Smuzhiyun 		.formats = SNDRV_PCM_FMTBIT_S16_LE,},
2149*4882a593Smuzhiyun 	.ops = &twl4030_dai_voice_ops,
2150*4882a593Smuzhiyun },
2151*4882a593Smuzhiyun };
2152*4882a593Smuzhiyun 
twl4030_soc_probe(struct snd_soc_component * component)2153*4882a593Smuzhiyun static int twl4030_soc_probe(struct snd_soc_component *component)
2154*4882a593Smuzhiyun {
2155*4882a593Smuzhiyun 	struct twl4030_priv *twl4030;
2156*4882a593Smuzhiyun 
2157*4882a593Smuzhiyun 	twl4030 = devm_kzalloc(component->dev, sizeof(struct twl4030_priv),
2158*4882a593Smuzhiyun 			       GFP_KERNEL);
2159*4882a593Smuzhiyun 	if (!twl4030)
2160*4882a593Smuzhiyun 		return -ENOMEM;
2161*4882a593Smuzhiyun 	snd_soc_component_set_drvdata(component, twl4030);
2162*4882a593Smuzhiyun 	/* Set the defaults, and power up the codec */
2163*4882a593Smuzhiyun 	twl4030->sysclk = twl4030_audio_get_mclk() / 1000;
2164*4882a593Smuzhiyun 
2165*4882a593Smuzhiyun 	twl4030_init_chip(component);
2166*4882a593Smuzhiyun 
2167*4882a593Smuzhiyun 	return 0;
2168*4882a593Smuzhiyun }
2169*4882a593Smuzhiyun 
twl4030_soc_remove(struct snd_soc_component * component)2170*4882a593Smuzhiyun static void twl4030_soc_remove(struct snd_soc_component *component)
2171*4882a593Smuzhiyun {
2172*4882a593Smuzhiyun 	struct twl4030_priv *twl4030 = snd_soc_component_get_drvdata(component);
2173*4882a593Smuzhiyun 	struct twl4030_codec_data *pdata = twl4030->pdata;
2174*4882a593Smuzhiyun 
2175*4882a593Smuzhiyun 	if (pdata && pdata->hs_extmute && gpio_is_valid(pdata->hs_extmute_gpio))
2176*4882a593Smuzhiyun 		gpio_free(pdata->hs_extmute_gpio);
2177*4882a593Smuzhiyun }
2178*4882a593Smuzhiyun 
2179*4882a593Smuzhiyun static const struct snd_soc_component_driver soc_component_dev_twl4030 = {
2180*4882a593Smuzhiyun 	.probe			= twl4030_soc_probe,
2181*4882a593Smuzhiyun 	.remove			= twl4030_soc_remove,
2182*4882a593Smuzhiyun 	.read			= twl4030_read,
2183*4882a593Smuzhiyun 	.write			= twl4030_write,
2184*4882a593Smuzhiyun 	.set_bias_level		= twl4030_set_bias_level,
2185*4882a593Smuzhiyun 	.controls		= twl4030_snd_controls,
2186*4882a593Smuzhiyun 	.num_controls		= ARRAY_SIZE(twl4030_snd_controls),
2187*4882a593Smuzhiyun 	.dapm_widgets		= twl4030_dapm_widgets,
2188*4882a593Smuzhiyun 	.num_dapm_widgets	= ARRAY_SIZE(twl4030_dapm_widgets),
2189*4882a593Smuzhiyun 	.dapm_routes		= intercon,
2190*4882a593Smuzhiyun 	.num_dapm_routes	= ARRAY_SIZE(intercon),
2191*4882a593Smuzhiyun 	.use_pmdown_time	= 1,
2192*4882a593Smuzhiyun 	.endianness		= 1,
2193*4882a593Smuzhiyun 	.non_legacy_dai_naming	= 1,
2194*4882a593Smuzhiyun };
2195*4882a593Smuzhiyun 
twl4030_codec_probe(struct platform_device * pdev)2196*4882a593Smuzhiyun static int twl4030_codec_probe(struct platform_device *pdev)
2197*4882a593Smuzhiyun {
2198*4882a593Smuzhiyun 	return devm_snd_soc_register_component(&pdev->dev,
2199*4882a593Smuzhiyun 				      &soc_component_dev_twl4030,
2200*4882a593Smuzhiyun 				      twl4030_dai, ARRAY_SIZE(twl4030_dai));
2201*4882a593Smuzhiyun }
2202*4882a593Smuzhiyun 
2203*4882a593Smuzhiyun MODULE_ALIAS("platform:twl4030-codec");
2204*4882a593Smuzhiyun 
2205*4882a593Smuzhiyun static struct platform_driver twl4030_codec_driver = {
2206*4882a593Smuzhiyun 	.probe		= twl4030_codec_probe,
2207*4882a593Smuzhiyun 	.driver		= {
2208*4882a593Smuzhiyun 		.name	= "twl4030-codec",
2209*4882a593Smuzhiyun 	},
2210*4882a593Smuzhiyun };
2211*4882a593Smuzhiyun 
2212*4882a593Smuzhiyun module_platform_driver(twl4030_codec_driver);
2213*4882a593Smuzhiyun 
2214*4882a593Smuzhiyun MODULE_DESCRIPTION("ASoC TWL4030 codec driver");
2215*4882a593Smuzhiyun MODULE_AUTHOR("Steve Sakoman");
2216*4882a593Smuzhiyun MODULE_LICENSE("GPL");
2217