1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * ALSA SoC TPA6130A2 amplifier driver 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) Nokia Corporation 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Author: Peter Ujfalusi <peter.ujfalusi@ti.com> 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __TPA6130A2_H__ 11*4882a593Smuzhiyun #define __TPA6130A2_H__ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* Register addresses */ 14*4882a593Smuzhiyun #define TPA6130A2_REG_CONTROL 0x01 15*4882a593Smuzhiyun #define TPA6130A2_REG_VOL_MUTE 0x02 16*4882a593Smuzhiyun #define TPA6130A2_REG_OUT_IMPEDANCE 0x03 17*4882a593Smuzhiyun #define TPA6130A2_REG_VERSION 0x04 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* Register bits */ 20*4882a593Smuzhiyun /* TPA6130A2_REG_CONTROL (0x01) */ 21*4882a593Smuzhiyun #define TPA6130A2_SWS_SHIFT 0 22*4882a593Smuzhiyun #define TPA6130A2_SWS (0x01 << TPA6130A2_SWS_SHIFT) 23*4882a593Smuzhiyun #define TPA6130A2_TERMAL (0x01 << 1) 24*4882a593Smuzhiyun #define TPA6130A2_MODE(x) (x << 4) 25*4882a593Smuzhiyun #define TPA6130A2_MODE_STEREO (0x00) 26*4882a593Smuzhiyun #define TPA6130A2_MODE_DUAL_MONO (0x01) 27*4882a593Smuzhiyun #define TPA6130A2_MODE_BRIDGE (0x02) 28*4882a593Smuzhiyun #define TPA6130A2_MODE_MASK (0x03) 29*4882a593Smuzhiyun #define TPA6130A2_HP_EN_R_SHIFT 6 30*4882a593Smuzhiyun #define TPA6130A2_HP_EN_R (0x01 << TPA6130A2_HP_EN_R_SHIFT) 31*4882a593Smuzhiyun #define TPA6130A2_HP_EN_L_SHIFT 7 32*4882a593Smuzhiyun #define TPA6130A2_HP_EN_L (0x01 << TPA6130A2_HP_EN_L_SHIFT) 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun /* TPA6130A2_REG_VOL_MUTE (0x02) */ 35*4882a593Smuzhiyun #define TPA6130A2_VOLUME(x) ((x & 0x3f) << 0) 36*4882a593Smuzhiyun #define TPA6130A2_MUTE_R (0x01 << 6) 37*4882a593Smuzhiyun #define TPA6130A2_MUTE_L (0x01 << 7) 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun /* TPA6130A2_REG_OUT_IMPEDANCE (0x03) */ 40*4882a593Smuzhiyun #define TPA6130A2_HIZ_R (0x01 << 0) 41*4882a593Smuzhiyun #define TPA6130A2_HIZ_L (0x01 << 1) 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun /* TPA6130A2_REG_VERSION (0x04) */ 44*4882a593Smuzhiyun #define TPA6130A2_VERSION_MASK (0x0f) 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #endif /* __TPA6130A2_H__ */ 47