1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Texas Instruments TLV320AIC26 low power audio CODEC 4*4882a593Smuzhiyun * register definitions 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Copyright (C) 2008 Secret Lab Technologies Ltd. 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef _TLV320AIC16_H_ 10*4882a593Smuzhiyun #define _TLV320AIC16_H_ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* AIC26 Registers */ 13*4882a593Smuzhiyun #define AIC26_PAGE_ADDR(page, offset) ((page << 11) | offset << 5) 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /* Page 0: Auxiliary data registers */ 16*4882a593Smuzhiyun #define AIC26_REG_BAT1 AIC26_PAGE_ADDR(0, 0x05) 17*4882a593Smuzhiyun #define AIC26_REG_BAT2 AIC26_PAGE_ADDR(0, 0x06) 18*4882a593Smuzhiyun #define AIC26_REG_AUX AIC26_PAGE_ADDR(0, 0x07) 19*4882a593Smuzhiyun #define AIC26_REG_TEMP1 AIC26_PAGE_ADDR(0, 0x09) 20*4882a593Smuzhiyun #define AIC26_REG_TEMP2 AIC26_PAGE_ADDR(0, 0x0A) 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* Page 1: Auxiliary control registers */ 23*4882a593Smuzhiyun #define AIC26_REG_AUX_ADC AIC26_PAGE_ADDR(1, 0x00) 24*4882a593Smuzhiyun #define AIC26_REG_STATUS AIC26_PAGE_ADDR(1, 0x01) 25*4882a593Smuzhiyun #define AIC26_REG_REFERENCE AIC26_PAGE_ADDR(1, 0x03) 26*4882a593Smuzhiyun #define AIC26_REG_RESET AIC26_PAGE_ADDR(1, 0x04) 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun /* Page 2: Audio control registers */ 29*4882a593Smuzhiyun #define AIC26_REG_AUDIO_CTRL1 AIC26_PAGE_ADDR(2, 0x00) 30*4882a593Smuzhiyun #define AIC26_REG_ADC_GAIN AIC26_PAGE_ADDR(2, 0x01) 31*4882a593Smuzhiyun #define AIC26_REG_DAC_GAIN AIC26_PAGE_ADDR(2, 0x02) 32*4882a593Smuzhiyun #define AIC26_REG_SIDETONE AIC26_PAGE_ADDR(2, 0x03) 33*4882a593Smuzhiyun #define AIC26_REG_AUDIO_CTRL2 AIC26_PAGE_ADDR(2, 0x04) 34*4882a593Smuzhiyun #define AIC26_REG_POWER_CTRL AIC26_PAGE_ADDR(2, 0x05) 35*4882a593Smuzhiyun #define AIC26_REG_AUDIO_CTRL3 AIC26_PAGE_ADDR(2, 0x06) 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun #define AIC26_REG_FILTER_COEFF_L_N0 AIC26_PAGE_ADDR(2, 0x07) 38*4882a593Smuzhiyun #define AIC26_REG_FILTER_COEFF_L_N1 AIC26_PAGE_ADDR(2, 0x08) 39*4882a593Smuzhiyun #define AIC26_REG_FILTER_COEFF_L_N2 AIC26_PAGE_ADDR(2, 0x09) 40*4882a593Smuzhiyun #define AIC26_REG_FILTER_COEFF_L_N3 AIC26_PAGE_ADDR(2, 0x0A) 41*4882a593Smuzhiyun #define AIC26_REG_FILTER_COEFF_L_N4 AIC26_PAGE_ADDR(2, 0x0B) 42*4882a593Smuzhiyun #define AIC26_REG_FILTER_COEFF_L_N5 AIC26_PAGE_ADDR(2, 0x0C) 43*4882a593Smuzhiyun #define AIC26_REG_FILTER_COEFF_L_D1 AIC26_PAGE_ADDR(2, 0x0D) 44*4882a593Smuzhiyun #define AIC26_REG_FILTER_COEFF_L_D2 AIC26_PAGE_ADDR(2, 0x0E) 45*4882a593Smuzhiyun #define AIC26_REG_FILTER_COEFF_L_D4 AIC26_PAGE_ADDR(2, 0x0F) 46*4882a593Smuzhiyun #define AIC26_REG_FILTER_COEFF_L_D5 AIC26_PAGE_ADDR(2, 0x10) 47*4882a593Smuzhiyun #define AIC26_REG_FILTER_COEFF_R_N0 AIC26_PAGE_ADDR(2, 0x11) 48*4882a593Smuzhiyun #define AIC26_REG_FILTER_COEFF_R_N1 AIC26_PAGE_ADDR(2, 0x12) 49*4882a593Smuzhiyun #define AIC26_REG_FILTER_COEFF_R_N2 AIC26_PAGE_ADDR(2, 0x13) 50*4882a593Smuzhiyun #define AIC26_REG_FILTER_COEFF_R_N3 AIC26_PAGE_ADDR(2, 0x14) 51*4882a593Smuzhiyun #define AIC26_REG_FILTER_COEFF_R_N4 AIC26_PAGE_ADDR(2, 0x15) 52*4882a593Smuzhiyun #define AIC26_REG_FILTER_COEFF_R_N5 AIC26_PAGE_ADDR(2, 0x16) 53*4882a593Smuzhiyun #define AIC26_REG_FILTER_COEFF_R_D1 AIC26_PAGE_ADDR(2, 0x17) 54*4882a593Smuzhiyun #define AIC26_REG_FILTER_COEFF_R_D2 AIC26_PAGE_ADDR(2, 0x18) 55*4882a593Smuzhiyun #define AIC26_REG_FILTER_COEFF_R_D4 AIC26_PAGE_ADDR(2, 0x19) 56*4882a593Smuzhiyun #define AIC26_REG_FILTER_COEFF_R_D5 AIC26_PAGE_ADDR(2, 0x1A) 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun #define AIC26_REG_PLL_PROG1 AIC26_PAGE_ADDR(2, 0x1B) 59*4882a593Smuzhiyun #define AIC26_REG_PLL_PROG2 AIC26_PAGE_ADDR(2, 0x1C) 60*4882a593Smuzhiyun #define AIC26_REG_AUDIO_CTRL4 AIC26_PAGE_ADDR(2, 0x1D) 61*4882a593Smuzhiyun #define AIC26_REG_AUDIO_CTRL5 AIC26_PAGE_ADDR(2, 0x1E) 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun /* fsref dividers; used in register 'Audio Control 1' */ 64*4882a593Smuzhiyun enum aic26_divisors { 65*4882a593Smuzhiyun AIC26_DIV_1 = 0, 66*4882a593Smuzhiyun AIC26_DIV_1_5 = 1, 67*4882a593Smuzhiyun AIC26_DIV_2 = 2, 68*4882a593Smuzhiyun AIC26_DIV_3 = 3, 69*4882a593Smuzhiyun AIC26_DIV_4 = 4, 70*4882a593Smuzhiyun AIC26_DIV_5 = 5, 71*4882a593Smuzhiyun AIC26_DIV_5_5 = 6, 72*4882a593Smuzhiyun AIC26_DIV_6 = 7, 73*4882a593Smuzhiyun }; 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun /* Digital data format */ 76*4882a593Smuzhiyun enum aic26_datfm { 77*4882a593Smuzhiyun AIC26_DATFM_I2S = 0 << 8, 78*4882a593Smuzhiyun AIC26_DATFM_DSP = 1 << 8, 79*4882a593Smuzhiyun AIC26_DATFM_RIGHTJ = 2 << 8, /* right justified */ 80*4882a593Smuzhiyun AIC26_DATFM_LEFTJ = 3 << 8, /* left justified */ 81*4882a593Smuzhiyun }; 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun /* Sample word length in bits; used in register 'Audio Control 1' */ 84*4882a593Smuzhiyun enum aic26_wlen { 85*4882a593Smuzhiyun AIC26_WLEN_16 = 0 << 10, 86*4882a593Smuzhiyun AIC26_WLEN_20 = 1 << 10, 87*4882a593Smuzhiyun AIC26_WLEN_24 = 2 << 10, 88*4882a593Smuzhiyun AIC26_WLEN_32 = 3 << 10, 89*4882a593Smuzhiyun }; 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun #endif /* _TLV320AIC16_H_ */ 92