1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * ALSA SoC TLV320AIC23 codec driver 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Author: Arun KS, <arunks@mistralsolutions.com> 6*4882a593Smuzhiyun * Copyright: (C) 2008 Mistral Solutions Pvt Ltd 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef _TLV320AIC23_H 10*4882a593Smuzhiyun #define _TLV320AIC23_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun struct device; 13*4882a593Smuzhiyun struct regmap_config; 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun extern const struct regmap_config tlv320aic23_regmap; 16*4882a593Smuzhiyun int tlv320aic23_probe(struct device *dev, struct regmap *regmap); 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /* Codec TLV320AIC23 */ 19*4882a593Smuzhiyun #define TLV320AIC23_LINVOL 0x00 20*4882a593Smuzhiyun #define TLV320AIC23_RINVOL 0x01 21*4882a593Smuzhiyun #define TLV320AIC23_LCHNVOL 0x02 22*4882a593Smuzhiyun #define TLV320AIC23_RCHNVOL 0x03 23*4882a593Smuzhiyun #define TLV320AIC23_ANLG 0x04 24*4882a593Smuzhiyun #define TLV320AIC23_DIGT 0x05 25*4882a593Smuzhiyun #define TLV320AIC23_PWR 0x06 26*4882a593Smuzhiyun #define TLV320AIC23_DIGT_FMT 0x07 27*4882a593Smuzhiyun #define TLV320AIC23_SRATE 0x08 28*4882a593Smuzhiyun #define TLV320AIC23_ACTIVE 0x09 29*4882a593Smuzhiyun #define TLV320AIC23_RESET 0x0F 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /* Left (right) line input volume control register */ 32*4882a593Smuzhiyun #define TLV320AIC23_LRS_ENABLED 0x0100 33*4882a593Smuzhiyun #define TLV320AIC23_LIM_MUTED 0x0080 34*4882a593Smuzhiyun #define TLV320AIC23_LIV_DEFAULT 0x0017 35*4882a593Smuzhiyun #define TLV320AIC23_LIV_MAX 0x001f 36*4882a593Smuzhiyun #define TLV320AIC23_LIV_MIN 0x0000 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun /* Left (right) channel headphone volume control register */ 39*4882a593Smuzhiyun #define TLV320AIC23_LZC_ON 0x0080 40*4882a593Smuzhiyun #define TLV320AIC23_LHV_DEFAULT 0x0079 41*4882a593Smuzhiyun #define TLV320AIC23_LHV_MAX 0x007f 42*4882a593Smuzhiyun #define TLV320AIC23_LHV_MIN 0x0000 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun /* Analog audio path control register */ 45*4882a593Smuzhiyun #define TLV320AIC23_STA_REG(x) ((x)<<6) 46*4882a593Smuzhiyun #define TLV320AIC23_STE_ENABLED 0x0020 47*4882a593Smuzhiyun #define TLV320AIC23_DAC_SELECTED 0x0010 48*4882a593Smuzhiyun #define TLV320AIC23_BYPASS_ON 0x0008 49*4882a593Smuzhiyun #define TLV320AIC23_INSEL_MIC 0x0004 50*4882a593Smuzhiyun #define TLV320AIC23_MICM_MUTED 0x0002 51*4882a593Smuzhiyun #define TLV320AIC23_MICB_20DB 0x0001 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun /* Digital audio path control register */ 54*4882a593Smuzhiyun #define TLV320AIC23_DACM_MUTE 0x0008 55*4882a593Smuzhiyun #define TLV320AIC23_DEEMP_32K 0x0002 56*4882a593Smuzhiyun #define TLV320AIC23_DEEMP_44K 0x0004 57*4882a593Smuzhiyun #define TLV320AIC23_DEEMP_48K 0x0006 58*4882a593Smuzhiyun #define TLV320AIC23_ADCHP_ON 0x0001 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun /* Power control down register */ 61*4882a593Smuzhiyun #define TLV320AIC23_DEVICE_PWR_OFF 0x0080 62*4882a593Smuzhiyun #define TLV320AIC23_CLK_OFF 0x0040 63*4882a593Smuzhiyun #define TLV320AIC23_OSC_OFF 0x0020 64*4882a593Smuzhiyun #define TLV320AIC23_OUT_OFF 0x0010 65*4882a593Smuzhiyun #define TLV320AIC23_DAC_OFF 0x0008 66*4882a593Smuzhiyun #define TLV320AIC23_ADC_OFF 0x0004 67*4882a593Smuzhiyun #define TLV320AIC23_MIC_OFF 0x0002 68*4882a593Smuzhiyun #define TLV320AIC23_LINE_OFF 0x0001 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun /* Digital audio interface register */ 71*4882a593Smuzhiyun #define TLV320AIC23_MS_MASTER 0x0040 72*4882a593Smuzhiyun #define TLV320AIC23_LRSWAP_ON 0x0020 73*4882a593Smuzhiyun #define TLV320AIC23_LRP_ON 0x0010 74*4882a593Smuzhiyun #define TLV320AIC23_IWL_16 0x0000 75*4882a593Smuzhiyun #define TLV320AIC23_IWL_20 0x0004 76*4882a593Smuzhiyun #define TLV320AIC23_IWL_24 0x0008 77*4882a593Smuzhiyun #define TLV320AIC23_IWL_32 0x000C 78*4882a593Smuzhiyun #define TLV320AIC23_FOR_I2S 0x0002 79*4882a593Smuzhiyun #define TLV320AIC23_FOR_DSP 0x0003 80*4882a593Smuzhiyun #define TLV320AIC23_FOR_LJUST 0x0001 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun /* Sample rate control register */ 83*4882a593Smuzhiyun #define TLV320AIC23_CLKOUT_HALF 0x0080 84*4882a593Smuzhiyun #define TLV320AIC23_CLKIN_HALF 0x0040 85*4882a593Smuzhiyun #define TLV320AIC23_BOSR_384fs 0x0002 /* BOSR_272fs in USB mode */ 86*4882a593Smuzhiyun #define TLV320AIC23_USB_CLK_ON 0x0001 87*4882a593Smuzhiyun #define TLV320AIC23_SR_MASK 0xf 88*4882a593Smuzhiyun #define TLV320AIC23_CLKOUT_SHIFT 7 89*4882a593Smuzhiyun #define TLV320AIC23_CLKIN_SHIFT 6 90*4882a593Smuzhiyun #define TLV320AIC23_SR_SHIFT 2 91*4882a593Smuzhiyun #define TLV320AIC23_BOSR_SHIFT 1 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun /* Digital interface register */ 94*4882a593Smuzhiyun #define TLV320AIC23_ACT_ON 0x0001 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun /* 97*4882a593Smuzhiyun * AUDIO related MACROS 98*4882a593Smuzhiyun */ 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun #define TLV320AIC23_DEFAULT_OUT_VOL 0x70 101*4882a593Smuzhiyun #define TLV320AIC23_DEFAULT_IN_VOLUME 0x10 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun #define TLV320AIC23_OUT_VOL_MIN TLV320AIC23_LHV_MIN 104*4882a593Smuzhiyun #define TLV320AIC23_OUT_VOL_MAX TLV320AIC23_LHV_MAX 105*4882a593Smuzhiyun #define TLV320AIC23_OUT_VO_RANGE (TLV320AIC23_OUT_VOL_MAX - \ 106*4882a593Smuzhiyun TLV320AIC23_OUT_VOL_MIN) 107*4882a593Smuzhiyun #define TLV320AIC23_OUT_VOL_MASK TLV320AIC23_OUT_VOL_MAX 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun #define TLV320AIC23_IN_VOL_MIN TLV320AIC23_LIV_MIN 110*4882a593Smuzhiyun #define TLV320AIC23_IN_VOL_MAX TLV320AIC23_LIV_MAX 111*4882a593Smuzhiyun #define TLV320AIC23_IN_VOL_RANGE (TLV320AIC23_IN_VOL_MAX - \ 112*4882a593Smuzhiyun TLV320AIC23_IN_VOL_MIN) 113*4882a593Smuzhiyun #define TLV320AIC23_IN_VOL_MASK TLV320AIC23_IN_VOL_MAX 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun #define TLV320AIC23_SIDETONE_MASK 0x1c0 116*4882a593Smuzhiyun #define TLV320AIC23_SIDETONE_0 0x100 117*4882a593Smuzhiyun #define TLV320AIC23_SIDETONE_6 0x000 118*4882a593Smuzhiyun #define TLV320AIC23_SIDETONE_9 0x040 119*4882a593Smuzhiyun #define TLV320AIC23_SIDETONE_12 0x080 120*4882a593Smuzhiyun #define TLV320AIC23_SIDETONE_18 0x0c0 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun #endif /* _TLV320AIC23_H */ 123