1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun // TLV320ADCX104 Sound driver 3*4882a593Smuzhiyun // Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun #ifndef _TLV320ADCX140_H 6*4882a593Smuzhiyun #define _TLV320ADCX140_H 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #define ADCX140_RATES (SNDRV_PCM_RATE_44100 | \ 9*4882a593Smuzhiyun SNDRV_PCM_RATE_48000) 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define ADCX140_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \ 12*4882a593Smuzhiyun SNDRV_PCM_FMTBIT_S20_3LE | \ 13*4882a593Smuzhiyun SNDRV_PCM_FMTBIT_S24_3LE | \ 14*4882a593Smuzhiyun SNDRV_PCM_FMTBIT_S24_LE | \ 15*4882a593Smuzhiyun SNDRV_PCM_FMTBIT_S32_LE) 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #define ADCX140_PAGE_SELECT 0x00 18*4882a593Smuzhiyun #define ADCX140_SW_RESET 0x01 19*4882a593Smuzhiyun #define ADCX140_SLEEP_CFG 0x02 20*4882a593Smuzhiyun #define ADCX140_SHDN_CFG 0x05 21*4882a593Smuzhiyun #define ADCX140_ASI_CFG0 0x07 22*4882a593Smuzhiyun #define ADCX140_ASI_CFG1 0x08 23*4882a593Smuzhiyun #define ADCX140_ASI_CFG2 0x09 24*4882a593Smuzhiyun #define ADCX140_ASI_CH1 0x0b 25*4882a593Smuzhiyun #define ADCX140_ASI_CH2 0x0c 26*4882a593Smuzhiyun #define ADCX140_ASI_CH3 0x0d 27*4882a593Smuzhiyun #define ADCX140_ASI_CH4 0x0e 28*4882a593Smuzhiyun #define ADCX140_ASI_CH5 0x0f 29*4882a593Smuzhiyun #define ADCX140_ASI_CH6 0x10 30*4882a593Smuzhiyun #define ADCX140_ASI_CH7 0x11 31*4882a593Smuzhiyun #define ADCX140_ASI_CH8 0x12 32*4882a593Smuzhiyun #define ADCX140_MST_CFG0 0x13 33*4882a593Smuzhiyun #define ADCX140_MST_CFG1 0x14 34*4882a593Smuzhiyun #define ADCX140_ASI_STS 0x15 35*4882a593Smuzhiyun #define ADCX140_CLK_SRC 0x16 36*4882a593Smuzhiyun #define ADCX140_PDMCLK_CFG 0x1f 37*4882a593Smuzhiyun #define ADCX140_PDM_CFG 0x20 38*4882a593Smuzhiyun #define ADCX140_GPIO_CFG0 0x21 39*4882a593Smuzhiyun #define ADCX140_GPO_CFG0 0x22 40*4882a593Smuzhiyun #define ADCX140_GPO_CFG1 0x23 41*4882a593Smuzhiyun #define ADCX140_GPO_CFG2 0x24 42*4882a593Smuzhiyun #define ADCX140_GPO_CFG3 0x25 43*4882a593Smuzhiyun #define ADCX140_GPO_VAL 0x29 44*4882a593Smuzhiyun #define ADCX140_GPIO_MON 0x2a 45*4882a593Smuzhiyun #define ADCX140_GPI_CFG0 0x2b 46*4882a593Smuzhiyun #define ADCX140_GPI_CFG1 0x2c 47*4882a593Smuzhiyun #define ADCX140_GPI_MON 0x2f 48*4882a593Smuzhiyun #define ADCX140_INT_CFG 0x32 49*4882a593Smuzhiyun #define ADCX140_INT_MASK0 0x33 50*4882a593Smuzhiyun #define ADCX140_INT_LTCH0 0x36 51*4882a593Smuzhiyun #define ADCX140_BIAS_CFG 0x3b 52*4882a593Smuzhiyun #define ADCX140_CH1_CFG0 0x3c 53*4882a593Smuzhiyun #define ADCX140_CH1_CFG1 0x3d 54*4882a593Smuzhiyun #define ADCX140_CH1_CFG2 0x3e 55*4882a593Smuzhiyun #define ADCX140_CH1_CFG3 0x3f 56*4882a593Smuzhiyun #define ADCX140_CH1_CFG4 0x40 57*4882a593Smuzhiyun #define ADCX140_CH2_CFG0 0x41 58*4882a593Smuzhiyun #define ADCX140_CH2_CFG1 0x42 59*4882a593Smuzhiyun #define ADCX140_CH2_CFG2 0x43 60*4882a593Smuzhiyun #define ADCX140_CH2_CFG3 0x44 61*4882a593Smuzhiyun #define ADCX140_CH2_CFG4 0x45 62*4882a593Smuzhiyun #define ADCX140_CH3_CFG0 0x46 63*4882a593Smuzhiyun #define ADCX140_CH3_CFG1 0x47 64*4882a593Smuzhiyun #define ADCX140_CH3_CFG2 0x48 65*4882a593Smuzhiyun #define ADCX140_CH3_CFG3 0x49 66*4882a593Smuzhiyun #define ADCX140_CH3_CFG4 0x4a 67*4882a593Smuzhiyun #define ADCX140_CH4_CFG0 0x4b 68*4882a593Smuzhiyun #define ADCX140_CH4_CFG1 0x4c 69*4882a593Smuzhiyun #define ADCX140_CH4_CFG2 0x4d 70*4882a593Smuzhiyun #define ADCX140_CH4_CFG3 0x4e 71*4882a593Smuzhiyun #define ADCX140_CH4_CFG4 0x4f 72*4882a593Smuzhiyun #define ADCX140_CH5_CFG2 0x52 73*4882a593Smuzhiyun #define ADCX140_CH5_CFG3 0x53 74*4882a593Smuzhiyun #define ADCX140_CH5_CFG4 0x54 75*4882a593Smuzhiyun #define ADCX140_CH6_CFG2 0x57 76*4882a593Smuzhiyun #define ADCX140_CH6_CFG3 0x58 77*4882a593Smuzhiyun #define ADCX140_CH6_CFG4 0x59 78*4882a593Smuzhiyun #define ADCX140_CH7_CFG2 0x5c 79*4882a593Smuzhiyun #define ADCX140_CH7_CFG3 0x5d 80*4882a593Smuzhiyun #define ADCX140_CH7_CFG4 0x5e 81*4882a593Smuzhiyun #define ADCX140_CH8_CFG2 0x61 82*4882a593Smuzhiyun #define ADCX140_CH8_CFG3 0x62 83*4882a593Smuzhiyun #define ADCX140_CH8_CFG4 0x63 84*4882a593Smuzhiyun #define ADCX140_DSP_CFG0 0x6b 85*4882a593Smuzhiyun #define ADCX140_DSP_CFG1 0x6c 86*4882a593Smuzhiyun #define ADCX140_DRE_CFG0 0x6d 87*4882a593Smuzhiyun #define ADCX140_AGC_CFG0 0x70 88*4882a593Smuzhiyun #define ADCX140_IN_CH_EN 0x73 89*4882a593Smuzhiyun #define ADCX140_ASI_OUT_CH_EN 0x74 90*4882a593Smuzhiyun #define ADCX140_PWR_CFG 0x75 91*4882a593Smuzhiyun #define ADCX140_DEV_STS0 0x76 92*4882a593Smuzhiyun #define ADCX140_DEV_STS1 0x77 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun #define ADCX140_RESET BIT(0) 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun #define ADCX140_WAKE_DEV BIT(0) 97*4882a593Smuzhiyun #define ADCX140_AREG_INTERNAL BIT(7) 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun #define ADCX140_BCLKINV_BIT BIT(2) 100*4882a593Smuzhiyun #define ADCX140_FSYNCINV_BIT BIT(3) 101*4882a593Smuzhiyun #define ADCX140_INV_MSK (ADCX140_BCLKINV_BIT | ADCX140_FSYNCINV_BIT) 102*4882a593Smuzhiyun #define ADCX140_BCLK_FSYNC_MASTER BIT(7) 103*4882a593Smuzhiyun #define ADCX140_I2S_MODE_BIT BIT(6) 104*4882a593Smuzhiyun #define ADCX140_LEFT_JUST_BIT BIT(7) 105*4882a593Smuzhiyun #define ADCX140_ASI_FORMAT_MSK (ADCX140_I2S_MODE_BIT | ADCX140_LEFT_JUST_BIT) 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun #define ADCX140_16_BIT_WORD 0x0 108*4882a593Smuzhiyun #define ADCX140_20_BIT_WORD BIT(4) 109*4882a593Smuzhiyun #define ADCX140_24_BIT_WORD BIT(5) 110*4882a593Smuzhiyun #define ADCX140_32_BIT_WORD (BIT(4) | BIT(5)) 111*4882a593Smuzhiyun #define ADCX140_WORD_LEN_MSK 0x30 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun #define ADCX140_MAX_CHANNELS 8 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun #define ADCX140_MIC_BIAS_VAL_VREF 0 116*4882a593Smuzhiyun #define ADCX140_MIC_BIAS_VAL_VREF_1096 1 117*4882a593Smuzhiyun #define ADCX140_MIC_BIAS_VAL_AVDD 6 118*4882a593Smuzhiyun #define ADCX140_MIC_BIAS_VAL_MSK GENMASK(6, 4) 119*4882a593Smuzhiyun #define ADCX140_MIC_BIAS_SHIFT 4 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun #define ADCX140_MIC_BIAS_VREF_275V 0 122*4882a593Smuzhiyun #define ADCX140_MIC_BIAS_VREF_25V 1 123*4882a593Smuzhiyun #define ADCX140_MIC_BIAS_VREF_1375V 2 124*4882a593Smuzhiyun #define ADCX140_MIC_BIAS_VREF_MSK GENMASK(1, 0) 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun #define ADCX140_PWR_CTRL_MSK GENMASK(7, 5) 127*4882a593Smuzhiyun #define ADCX140_PWR_CFG_BIAS_PDZ BIT(7) 128*4882a593Smuzhiyun #define ADCX140_PWR_CFG_ADC_PDZ BIT(6) 129*4882a593Smuzhiyun #define ADCX140_PWR_CFG_PLL_PDZ BIT(5) 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun #define ADCX140_TX_OFFSET_MASK GENMASK(4, 0) 132*4882a593Smuzhiyun 133*4882a593Smuzhiyun #define ADCX140_NUM_PDM_EDGES 4 134*4882a593Smuzhiyun #define ADCX140_PDM_EDGE_SHIFT 7 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun #define ADCX140_NUM_GPI_PINS 4 137*4882a593Smuzhiyun #define ADCX140_GPI_SHIFT 4 138*4882a593Smuzhiyun #define ADCX140_GPI1_INDEX 0 139*4882a593Smuzhiyun #define ADCX140_GPI2_INDEX 1 140*4882a593Smuzhiyun #define ADCX140_GPI3_INDEX 2 141*4882a593Smuzhiyun #define ADCX140_GPI4_INDEX 3 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun #define ADCX140_NUM_GPOS 4 144*4882a593Smuzhiyun #define ADCX140_NUM_GPO_CFGS 2 145*4882a593Smuzhiyun #define ADCX140_GPO_SHIFT 4 146*4882a593Smuzhiyun #define ADCX140_GPO_CFG_MAX 4 147*4882a593Smuzhiyun #define ADCX140_GPO_DRV_MAX 5 148*4882a593Smuzhiyun 149*4882a593Smuzhiyun #define ADCX140_TX_FILL BIT(0) 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun #define ADCX140_NUM_GPIO_CFGS 2 152*4882a593Smuzhiyun #define ADCX140_GPIO_SHIFT 4 153*4882a593Smuzhiyun #define ADCX140_GPIO_CFG_MAX 15 154*4882a593Smuzhiyun #define ADCX140_GPIO_DRV_MAX 5 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun #endif /* _TLV320ADCX140_ */ 157